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chisel-verilog-pairs

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Generate the Verilog code corresponding to this FIRRTL code module PE_455 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_199 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_455( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_199 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_25 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_25( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x1_18 : output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeIn : { sync : UInt<1>[1]} invalidate nodeIn.sync[0] wire nodeOut : UInt<1>[1] invalidate nodeOut[0] connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn.sync	module IntSyncSyncCrossingSink_n1x1_18( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ShuttleICache : input clock : Clock input reset : Reset output auto : { master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<39>}, flip s1_kill : UInt<1>, flip s2_kill : UInt<1>, flip s1_paddr : UInt<32>, flip invalidate : UInt<1>, resp : { valid : UInt<1>, bits : UInt<64>}} wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready connect auto.master_out, masterNodeOut node s0_valid = and(io.req.ready, io.req.valid) regreset s1_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg s1_vaddr : UInt<39>, clock when s0_valid : connect s1_vaddr, io.req.bits wire s1_tag_hit : UInt<1>[8] node _s1_hit_T = or(s1_tag_hit[0], s1_tag_hit[1]) node _s1_hit_T_1 = or(_s1_hit_T, s1_tag_hit[2]) node _s1_hit_T_2 = or(_s1_hit_T_1, s1_tag_hit[3]) node _s1_hit_T_3 = or(_s1_hit_T_2, s1_tag_hit[4]) node _s1_hit_T_4 = or(_s1_hit_T_3, s1_tag_hit[5]) node _s1_hit_T_5 = or(_s1_hit_T_4, s1_tag_hit[6]) node s1_hit = or(_s1_hit_T_5, s1_tag_hit[7]) node _s2_valid_T = eq(io.s1_kill, UInt<1>(0h0)) node _s2_valid_T_1 = and(s1_valid, _s2_valid_T) regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect s2_valid, _s2_valid_T_1 reg s2_hit : UInt<1>, clock connect s2_hit, s1_hit reg invalidated : UInt<1>, clock regreset refill_valid : UInt<1>, clock, reset, UInt<1>(0h0) regreset send_hint : UInt<1>, clock, reset, UInt<1>(0h0) node _refill_fire_T = and(masterNodeOut.a.ready, masterNodeOut.a.valid) node _refill_fire_T_1 = eq(send_hint, UInt<1>(0h0)) node refill_fire = and(_refill_fire_T, _refill_fire_T_1) regreset hint_outstanding : UInt<1>, clock, reset, UInt<1>(0h0) node _s2_miss_T = eq(s2_hit, UInt<1>(0h0)) node _s2_miss_T_1 = and(s2_valid, _s2_miss_T) node _s2_miss_T_2 = eq(io.s2_kill, UInt<1>(0h0)) node s2_miss = and(_s2_miss_T_1, _s2_miss_T_2) node _s1_can_request_refill_T = or(s2_miss, refill_valid) node s1_can_request_refill = eq(_s1_can_request_refill_T, UInt<1>(0h0)) reg s2_request_refill_REG : UInt<1>, clock connect s2_request_refill_REG, s1_can_request_refill node s2_request_refill = and(s2_miss, s2_request_refill_REG) node _refill_paddr_T = and(s1_valid, s1_can_request_refill) reg refill_paddr : UInt<32>, clock when _refill_paddr_T : connect refill_paddr, io.s1_paddr node _refill_vaddr_T = and(s1_valid, s1_can_request_refill) reg refill_vaddr : UInt<39>, clock when _refill_vaddr_T : connect refill_vaddr, s1_vaddr node refill_tag = shr(refill_paddr, 12) node refill_idx = bits(refill_paddr, 11, 6) node _refill_one_beat_T = and(masterNodeOut.d.ready, masterNodeOut.d.valid) node refill_one_beat_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) node refill_one_beat = and(_refill_one_beat_T, refill_one_beat_opdata) node _io_req_ready_T = eq(refill_one_beat, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T connect s1_valid, s0_valid node _T = and(masterNodeOut.d.ready, masterNodeOut.d.valid) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), masterNodeOut.d.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) node r_beats1_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node d_done = and(r_2, _T) node _r_count_T = not(r_counter1) node refill_cnt = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(r_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_done = and(refill_one_beat, d_done) connect masterNodeOut.d.ready, UInt<1>(0h1) inst repl_way_prng of MaxPeriodFibonacciLFSR_1 connect repl_way_prng.clock, clock connect repl_way_prng.reset, reset connect repl_way_prng.io.seed.valid, UInt<1>(0h0) invalidate repl_way_prng.io.seed.bits[0] invalidate repl_way_prng.io.seed.bits[1] invalidate repl_way_prng.io.seed.bits[2] invalidate repl_way_prng.io.seed.bits[3] invalidate repl_way_prng.io.seed.bits[4] invalidate repl_way_prng.io.seed.bits[5] invalidate repl_way_prng.io.seed.bits[6] invalidate repl_way_prng.io.seed.bits[7] invalidate repl_way_prng.io.seed.bits[8] invalidate repl_way_prng.io.seed.bits[9] invalidate repl_way_prng.io.seed.bits[10] invalidate repl_way_prng.io.seed.bits[11] invalidate repl_way_prng.io.seed.bits[12] invalidate repl_way_prng.io.seed.bits[13] invalidate repl_way_prng.io.seed.bits[14] invalidate repl_way_prng.io.seed.bits[15] connect repl_way_prng.io.increment, refill_fire node repl_way_lo_lo_lo = cat(repl_way_prng.io.out[1], repl_way_prng.io.out[0]) node repl_way_lo_lo_hi = cat(repl_way_prng.io.out[3], repl_way_prng.io.out[2]) node repl_way_lo_lo = cat(repl_way_lo_lo_hi, repl_way_lo_lo_lo) node repl_way_lo_hi_lo = cat(repl_way_prng.io.out[5], repl_way_prng.io.out[4]) node repl_way_lo_hi_hi = cat(repl_way_prng.io.out[7], repl_way_prng.io.out[6]) node repl_way_lo_hi = cat(repl_way_lo_hi_hi, repl_way_lo_hi_lo) node repl_way_lo = cat(repl_way_lo_hi, repl_way_lo_lo) node repl_way_hi_lo_lo = cat(repl_way_prng.io.out[9], repl_way_prng.io.out[8]) node repl_way_hi_lo_hi = cat(repl_way_prng.io.out[11], repl_way_prng.io.out[10]) node repl_way_hi_lo = cat(repl_way_hi_lo_hi, repl_way_hi_lo_lo) node repl_way_hi_hi_lo = cat(repl_way_prng.io.out[13], repl_way_prng.io.out[12]) node repl_way_hi_hi_hi = cat(repl_way_prng.io.out[15], repl_way_prng.io.out[14]) node repl_way_hi_hi = cat(repl_way_hi_hi_hi, repl_way_hi_hi_lo) node repl_way_hi = cat(repl_way_hi_hi, repl_way_hi_lo) node _repl_way_T = cat(repl_way_hi, repl_way_lo) node repl_way = bits(_repl_way_T, 2, 0) smem tag_array : UInt<20>[8] [64] node _tag_rdata_T = bits(io.req.bits, 11, 6) node _tag_rdata_T_1 = eq(refill_done, UInt<1>(0h0)) node _tag_rdata_T_2 = and(_tag_rdata_T_1, s0_valid) wire _tag_rdata_WIRE : UInt<6> invalidate _tag_rdata_WIRE when _tag_rdata_T_2 : connect _tag_rdata_WIRE, _tag_rdata_T read mport tag_rdata = tag_array[_tag_rdata_WIRE], clock when refill_done : wire _WIRE : UInt<20>[8] connect _WIRE[0], refill_tag connect _WIRE[1], refill_tag connect _WIRE[2], refill_tag connect _WIRE[3], refill_tag connect _WIRE[4], refill_tag connect _WIRE[5], refill_tag connect _WIRE[6], refill_tag connect _WIRE[7], refill_tag node _T_1 = eq(repl_way, UInt<1>(0h0)) node _T_2 = eq(repl_way, UInt<1>(0h1)) node _T_3 = eq(repl_way, UInt<2>(0h2)) node _T_4 = eq(repl_way, UInt<2>(0h3)) node _T_5 = eq(repl_way, UInt<3>(0h4)) node _T_6 = eq(repl_way, UInt<3>(0h5)) node _T_7 = eq(repl_way, UInt<3>(0h6)) node _T_8 = eq(repl_way, UInt<3>(0h7)) write mport MPORT = tag_array[refill_idx], clock when _T_1 : connect MPORT[0], _WIRE[0] when _T_2 : connect MPORT[1], _WIRE[1] when _T_3 : connect MPORT[2], _WIRE[2] when _T_4 : connect MPORT[3], _WIRE[3] when _T_5 : connect MPORT[4], _WIRE[4] when _T_6 : connect MPORT[5], _WIRE[5] when _T_7 : connect MPORT[6], _WIRE[6] when _T_8 : connect MPORT[7], _WIRE[7] regreset vb_array : UInt<512>, clock, reset, UInt<512>(0h0) when refill_one_beat : node _vb_array_T = cat(repl_way, refill_idx) node _vb_array_T_1 = eq(invalidated, UInt<1>(0h0)) node _vb_array_T_2 = and(refill_done, _vb_array_T_1) node _vb_array_T_3 = dshl(UInt<1>(0h1), _vb_array_T) node _vb_array_T_4 = or(vb_array, _vb_array_T_3) node _vb_array_T_5 = not(vb_array) node _vb_array_T_6 = or(_vb_array_T_5, _vb_array_T_3) node _vb_array_T_7 = not(_vb_array_T_6) node _vb_array_T_8 = mux(_vb_array_T_2, _vb_array_T_4, _vb_array_T_7) connect vb_array, _vb_array_T_8 wire invalidate : UInt<1> connect invalidate, io.invalidate when invalidate : connect vb_array, UInt<1>(0h0) connect invalidated, UInt<1>(0h1) wire s1_dout : UInt<64>[8] invalidate s1_dout[0] invalidate s1_dout[1] invalidate s1_dout[2] invalidate s1_dout[3] invalidate s1_dout[4] invalidate s1_dout[5] invalidate s1_dout[6] invalidate s1_dout[7] node s1_idx = bits(io.s1_paddr, 11, 6) node s1_tag = shr(io.s1_paddr, 12) node _s1_vb_T = cat(UInt<1>(0h0), s1_idx) node _s1_vb_T_1 = dshr(vb_array, _s1_vb_T) node s1_vb = bits(_s1_vb_T_1, 0, 0) node _tagMatch_T = eq(tag_rdata[0], s1_tag) node tagMatch = and(s1_vb, _tagMatch_T) connect s1_tag_hit[0], tagMatch node s1_idx_1 = bits(io.s1_paddr, 11, 6) node s1_tag_1 = shr(io.s1_paddr, 12) node _s1_vb_T_2 = cat(UInt<1>(0h1), s1_idx_1) node _s1_vb_T_3 = dshr(vb_array, _s1_vb_T_2) node s1_vb_1 = bits(_s1_vb_T_3, 0, 0) node _tagMatch_T_1 = eq(tag_rdata[1], s1_tag_1) node tagMatch_1 = and(s1_vb_1, _tagMatch_T_1) connect s1_tag_hit[1], tagMatch_1 node s1_idx_2 = bits(io.s1_paddr, 11, 6) node s1_tag_2 = shr(io.s1_paddr, 12) node _s1_vb_T_4 = cat(UInt<2>(0h2), s1_idx_2) node _s1_vb_T_5 = dshr(vb_array, _s1_vb_T_4) node s1_vb_2 = bits(_s1_vb_T_5, 0, 0) node _tagMatch_T_2 = eq(tag_rdata[2], s1_tag_2) node tagMatch_2 = and(s1_vb_2, _tagMatch_T_2) connect s1_tag_hit[2], tagMatch_2 node s1_idx_3 = bits(io.s1_paddr, 11, 6) node s1_tag_3 = shr(io.s1_paddr, 12) node _s1_vb_T_6 = cat(UInt<2>(0h3), s1_idx_3) node _s1_vb_T_7 = dshr(vb_array, _s1_vb_T_6) node s1_vb_3 = bits(_s1_vb_T_7, 0, 0) node _tagMatch_T_3 = eq(tag_rdata[3], s1_tag_3) node tagMatch_3 = and(s1_vb_3, _tagMatch_T_3) connect s1_tag_hit[3], tagMatch_3 node s1_idx_4 = bits(io.s1_paddr, 11, 6) node s1_tag_4 = shr(io.s1_paddr, 12) node _s1_vb_T_8 = cat(UInt<3>(0h4), s1_idx_4) node _s1_vb_T_9 = dshr(vb_array, _s1_vb_T_8) node s1_vb_4 = bits(_s1_vb_T_9, 0, 0) node _tagMatch_T_4 = eq(tag_rdata[4], s1_tag_4) node tagMatch_4 = and(s1_vb_4, _tagMatch_T_4) connect s1_tag_hit[4], tagMatch_4 node s1_idx_5 = bits(io.s1_paddr, 11, 6) node s1_tag_5 = shr(io.s1_paddr, 12) node _s1_vb_T_10 = cat(UInt<3>(0h5), s1_idx_5) node _s1_vb_T_11 = dshr(vb_array, _s1_vb_T_10) node s1_vb_5 = bits(_s1_vb_T_11, 0, 0) node _tagMatch_T_5 = eq(tag_rdata[5], s1_tag_5) node tagMatch_5 = and(s1_vb_5, _tagMatch_T_5) connect s1_tag_hit[5], tagMatch_5 node s1_idx_6 = bits(io.s1_paddr, 11, 6) node s1_tag_6 = shr(io.s1_paddr, 12) node _s1_vb_T_12 = cat(UInt<3>(0h6), s1_idx_6) node _s1_vb_T_13 = dshr(vb_array, _s1_vb_T_12) node s1_vb_6 = bits(_s1_vb_T_13, 0, 0) node _tagMatch_T_6 = eq(tag_rdata[6], s1_tag_6) node tagMatch_6 = and(s1_vb_6, _tagMatch_T_6) connect s1_tag_hit[6], tagMatch_6 node s1_idx_7 = bits(io.s1_paddr, 11, 6) node s1_tag_7 = shr(io.s1_paddr, 12) node _s1_vb_T_14 = cat(UInt<3>(0h7), s1_idx_7) node _s1_vb_T_15 = dshr(vb_array, _s1_vb_T_14) node s1_vb_7 = bits(_s1_vb_T_15, 0, 0) node _tagMatch_T_7 = eq(tag_rdata[7], s1_tag_7) node tagMatch_7 = and(s1_vb_7, _tagMatch_T_7) connect s1_tag_hit[7], tagMatch_7 node _T_9 = eq(s1_valid, UInt<1>(0h0)) node _T_10 = add(s1_tag_hit[0], s1_tag_hit[1]) node _T_11 = bits(_T_10, 1, 0) node _T_12 = add(s1_tag_hit[2], s1_tag_hit[3]) node _T_13 = bits(_T_12, 1, 0) node _T_14 = add(_T_11, _T_13) node _T_15 = bits(_T_14, 2, 0) node _T_16 = add(s1_tag_hit[4], s1_tag_hit[5]) node _T_17 = bits(_T_16, 1, 0) node _T_18 = add(s1_tag_hit[6], s1_tag_hit[7]) node _T_19 = bits(_T_18, 1, 0) node _T_20 = add(_T_17, _T_19) node _T_21 = bits(_T_20, 2, 0) node _T_22 = add(_T_15, _T_21) node _T_23 = bits(_T_22, 3, 0) node _T_24 = leq(_T_23, UInt<1>(0h1)) node _T_25 = or(_T_9, _T_24) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ICache.scala:121 assert(!s1_valid \|\| PopCount(s1_tag_hit) <= 1.U)\n") : printf assert(clock, _T_25, UInt<1>(0h1), "") : assert smem data_arrays_0 : UInt<64>[8] [512] node _s0_ren_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node s0_ren = and(s0_valid, _s0_ren_T) node _wen_T = eq(invalidated, UInt<1>(0h0)) node wen = and(refill_one_beat, _wen_T) node _mem_idx_T = shl(refill_idx, 3) node _mem_idx_T_1 = or(_mem_idx_T, refill_cnt) node _mem_idx_T_2 = bits(io.req.bits, 11, 3) node mem_idx = mux(refill_one_beat, _mem_idx_T_1, _mem_idx_T_2) when wen : node data = bits(masterNodeOut.d.bits.data, 63, 0) wire _WIRE_1 : UInt<64>[8] connect _WIRE_1[0], data connect _WIRE_1[1], data connect _WIRE_1[2], data connect _WIRE_1[3], data connect _WIRE_1[4], data connect _WIRE_1[5], data connect _WIRE_1[6], data connect _WIRE_1[7], data node _T_29 = eq(repl_way, UInt<1>(0h0)) node _T_30 = eq(repl_way, UInt<1>(0h1)) node _T_31 = eq(repl_way, UInt<2>(0h2)) node _T_32 = eq(repl_way, UInt<2>(0h3)) node _T_33 = eq(repl_way, UInt<3>(0h4)) node _T_34 = eq(repl_way, UInt<3>(0h5)) node _T_35 = eq(repl_way, UInt<3>(0h6)) node _T_36 = eq(repl_way, UInt<3>(0h7)) write mport MPORT_1 = data_arrays_0[mem_idx], clock when _T_29 : connect MPORT_1[0], _WIRE_1[0] when _T_30 : connect MPORT_1[1], _WIRE_1[1] when _T_31 : connect MPORT_1[2], _WIRE_1[2] when _T_32 : connect MPORT_1[3], _WIRE_1[3] when _T_33 : connect MPORT_1[4], _WIRE_1[4] when _T_34 : connect MPORT_1[5], _WIRE_1[5] when _T_35 : connect MPORT_1[6], _WIRE_1[6] when _T_36 : connect MPORT_1[7], _WIRE_1[7] node _dout_T = eq(wen, UInt<1>(0h0)) node _dout_T_1 = and(_dout_T, s0_ren) wire _dout_WIRE : UInt<9> invalidate _dout_WIRE when _dout_T_1 : connect _dout_WIRE, mem_idx read mport dout = data_arrays_0[_dout_WIRE], clock node _T_37 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_37 : connect s1_dout, dout reg s2_tag_hit : UInt<1>[8], clock when s1_valid : connect s2_tag_hit, s1_tag_hit node s2_hit_way_lo_lo = cat(s2_tag_hit[1], s2_tag_hit[0]) node s2_hit_way_lo_hi = cat(s2_tag_hit[3], s2_tag_hit[2]) node s2_hit_way_lo = cat(s2_hit_way_lo_hi, s2_hit_way_lo_lo) node s2_hit_way_hi_lo = cat(s2_tag_hit[5], s2_tag_hit[4]) node s2_hit_way_hi_hi = cat(s2_tag_hit[7], s2_tag_hit[6]) node s2_hit_way_hi = cat(s2_hit_way_hi_hi, s2_hit_way_hi_lo) node _s2_hit_way_T = cat(s2_hit_way_hi, s2_hit_way_lo) node s2_hit_way_hi_1 = bits(_s2_hit_way_T, 7, 4) node s2_hit_way_lo_1 = bits(_s2_hit_way_T, 3, 0) node _s2_hit_way_T_1 = orr(s2_hit_way_hi_1) node _s2_hit_way_T_2 = or(s2_hit_way_hi_1, s2_hit_way_lo_1) node s2_hit_way_hi_2 = bits(_s2_hit_way_T_2, 3, 2) node s2_hit_way_lo_2 = bits(_s2_hit_way_T_2, 1, 0) node _s2_hit_way_T_3 = orr(s2_hit_way_hi_2) node _s2_hit_way_T_4 = or(s2_hit_way_hi_2, s2_hit_way_lo_2) node _s2_hit_way_T_5 = bits(_s2_hit_way_T_4, 1, 1) node _s2_hit_way_T_6 = cat(_s2_hit_way_T_3, _s2_hit_way_T_5) node s2_hit_way = cat(_s2_hit_way_T_1, _s2_hit_way_T_6) reg s2_dout : UInt<64>[8], clock when s1_valid : connect s2_dout, s1_dout node _s2_way_mux_T = mux(s2_tag_hit[0], s2_dout[0], UInt<1>(0h0)) node _s2_way_mux_T_1 = mux(s2_tag_hit[1], s2_dout[1], UInt<1>(0h0)) node _s2_way_mux_T_2 = mux(s2_tag_hit[2], s2_dout[2], UInt<1>(0h0)) node _s2_way_mux_T_3 = mux(s2_tag_hit[3], s2_dout[3], UInt<1>(0h0)) node _s2_way_mux_T_4 = mux(s2_tag_hit[4], s2_dout[4], UInt<1>(0h0)) node _s2_way_mux_T_5 = mux(s2_tag_hit[5], s2_dout[5], UInt<1>(0h0)) node _s2_way_mux_T_6 = mux(s2_tag_hit[6], s2_dout[6], UInt<1>(0h0)) node _s2_way_mux_T_7 = mux(s2_tag_hit[7], s2_dout[7], UInt<1>(0h0)) node _s2_way_mux_T_8 = or(_s2_way_mux_T, _s2_way_mux_T_1) node _s2_way_mux_T_9 = or(_s2_way_mux_T_8, _s2_way_mux_T_2) node _s2_way_mux_T_10 = or(_s2_way_mux_T_9, _s2_way_mux_T_3) node _s2_way_mux_T_11 = or(_s2_way_mux_T_10, _s2_way_mux_T_4) node _s2_way_mux_T_12 = or(_s2_way_mux_T_11, _s2_way_mux_T_5) node _s2_way_mux_T_13 = or(_s2_way_mux_T_12, _s2_way_mux_T_6) node _s2_way_mux_T_14 = or(_s2_way_mux_T_13, _s2_way_mux_T_7) wire s2_way_mux : UInt<64> connect s2_way_mux, _s2_way_mux_T_14 wire s2_full_word_write : UInt<1> connect s2_full_word_write, UInt<1>(0h0) connect io.resp.bits, s2_way_mux node _io_resp_valid_T = and(s2_valid, s2_hit) connect io.resp.valid, _io_resp_valid_T connect masterNodeOut.a.valid, s2_request_refill node _masterNodeOut_a_bits_T = shr(refill_paddr, 6) node _masterNodeOut_a_bits_T_1 = shl(_masterNodeOut_a_bits_T, 6) node _masterNodeOut_a_bits_legal_T = leq(UInt<1>(0h0), UInt<3>(0h6)) node _masterNodeOut_a_bits_legal_T_1 = leq(UInt<3>(0h6), UInt<4>(0hc)) node _masterNodeOut_a_bits_legal_T_2 = and(_masterNodeOut_a_bits_legal_T, _masterNodeOut_a_bits_legal_T_1) node _masterNodeOut_a_bits_legal_T_3 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_2) node _masterNodeOut_a_bits_legal_T_4 = xor(_masterNodeOut_a_bits_T_1, UInt<14>(0h3000)) node _masterNodeOut_a_bits_legal_T_5 = cvt(_masterNodeOut_a_bits_legal_T_4) node _masterNodeOut_a_bits_legal_T_6 = and(_masterNodeOut_a_bits_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _masterNodeOut_a_bits_legal_T_7 = asSInt(_masterNodeOut_a_bits_legal_T_6) node _masterNodeOut_a_bits_legal_T_8 = eq(_masterNodeOut_a_bits_legal_T_7, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_9 = and(_masterNodeOut_a_bits_legal_T_3, _masterNodeOut_a_bits_legal_T_8) node _masterNodeOut_a_bits_legal_T_10 = leq(UInt<1>(0h0), UInt<3>(0h6)) node _masterNodeOut_a_bits_legal_T_11 = leq(UInt<3>(0h6), UInt<3>(0h6)) node _masterNodeOut_a_bits_legal_T_12 = and(_masterNodeOut_a_bits_legal_T_10, _masterNodeOut_a_bits_legal_T_11) node _masterNodeOut_a_bits_legal_T_13 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_12) node _masterNodeOut_a_bits_legal_T_14 = xor(_masterNodeOut_a_bits_T_1, UInt<1>(0h0)) node _masterNodeOut_a_bits_legal_T_15 = cvt(_masterNodeOut_a_bits_legal_T_14) node _masterNodeOut_a_bits_legal_T_16 = and(_masterNodeOut_a_bits_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _masterNodeOut_a_bits_legal_T_17 = asSInt(_masterNodeOut_a_bits_legal_T_16) node _masterNodeOut_a_bits_legal_T_18 = eq(_masterNodeOut_a_bits_legal_T_17, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_19 = xor(_masterNodeOut_a_bits_T_1, UInt<17>(0h10000)) node _masterNodeOut_a_bits_legal_T_20 = cvt(_masterNodeOut_a_bits_legal_T_19) node _masterNodeOut_a_bits_legal_T_21 = and(_masterNodeOut_a_bits_legal_T_20, asSInt(UInt<33>(0h98013000))) node _masterNodeOut_a_bits_legal_T_22 = asSInt(_masterNodeOut_a_bits_legal_T_21) node _masterNodeOut_a_bits_legal_T_23 = eq(_masterNodeOut_a_bits_legal_T_22, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_24 = xor(_masterNodeOut_a_bits_T_1, UInt<17>(0h10000)) node _masterNodeOut_a_bits_legal_T_25 = cvt(_masterNodeOut_a_bits_legal_T_24) node _masterNodeOut_a_bits_legal_T_26 = and(_masterNodeOut_a_bits_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _masterNodeOut_a_bits_legal_T_27 = asSInt(_masterNodeOut_a_bits_legal_T_26) node _masterNodeOut_a_bits_legal_T_28 = eq(_masterNodeOut_a_bits_legal_T_27, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_29 = xor(_masterNodeOut_a_bits_T_1, UInt<26>(0h2000000)) node _masterNodeOut_a_bits_legal_T_30 = cvt(_masterNodeOut_a_bits_legal_T_29) node _masterNodeOut_a_bits_legal_T_31 = and(_masterNodeOut_a_bits_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _masterNodeOut_a_bits_legal_T_32 = asSInt(_masterNodeOut_a_bits_legal_T_31) node _masterNodeOut_a_bits_legal_T_33 = eq(_masterNodeOut_a_bits_legal_T_32, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_34 = xor(_masterNodeOut_a_bits_T_1, UInt<28>(0h8000000)) node _masterNodeOut_a_bits_legal_T_35 = cvt(_masterNodeOut_a_bits_legal_T_34) node _masterNodeOut_a_bits_legal_T_36 = and(_masterNodeOut_a_bits_legal_T_35, asSInt(UInt<33>(0h98000000))) node _masterNodeOut_a_bits_legal_T_37 = asSInt(_masterNodeOut_a_bits_legal_T_36) node _masterNodeOut_a_bits_legal_T_38 = eq(_masterNodeOut_a_bits_legal_T_37, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_39 = xor(_masterNodeOut_a_bits_T_1, UInt<28>(0h8000000)) node _masterNodeOut_a_bits_legal_T_40 = cvt(_masterNodeOut_a_bits_legal_T_39) node _masterNodeOut_a_bits_legal_T_41 = and(_masterNodeOut_a_bits_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _masterNodeOut_a_bits_legal_T_42 = asSInt(_masterNodeOut_a_bits_legal_T_41) node _masterNodeOut_a_bits_legal_T_43 = eq(_masterNodeOut_a_bits_legal_T_42, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_44 = xor(_masterNodeOut_a_bits_T_1, UInt<29>(0h10000000)) node _masterNodeOut_a_bits_legal_T_45 = cvt(_masterNodeOut_a_bits_legal_T_44) node _masterNodeOut_a_bits_legal_T_46 = and(_masterNodeOut_a_bits_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _masterNodeOut_a_bits_legal_T_47 = asSInt(_masterNodeOut_a_bits_legal_T_46) node _masterNodeOut_a_bits_legal_T_48 = eq(_masterNodeOut_a_bits_legal_T_47, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_49 = xor(_masterNodeOut_a_bits_T_1, UInt<32>(0h80000000)) node _masterNodeOut_a_bits_legal_T_50 = cvt(_masterNodeOut_a_bits_legal_T_49) node _masterNodeOut_a_bits_legal_T_51 = and(_masterNodeOut_a_bits_legal_T_50, asSInt(UInt<33>(0h90000000))) node _masterNodeOut_a_bits_legal_T_52 = asSInt(_masterNodeOut_a_bits_legal_T_51) node _masterNodeOut_a_bits_legal_T_53 = eq(_masterNodeOut_a_bits_legal_T_52, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_54 = or(_masterNodeOut_a_bits_legal_T_18, _masterNodeOut_a_bits_legal_T_23) node _masterNodeOut_a_bits_legal_T_55 = or(_masterNodeOut_a_bits_legal_T_54, _masterNodeOut_a_bits_legal_T_28) node _masterNodeOut_a_bits_legal_T_56 = or(_masterNodeOut_a_bits_legal_T_55, _masterNodeOut_a_bits_legal_T_33) node _masterNodeOut_a_bits_legal_T_57 = or(_masterNodeOut_a_bits_legal_T_56, _masterNodeOut_a_bits_legal_T_38) node _masterNodeOut_a_bits_legal_T_58 = or(_masterNodeOut_a_bits_legal_T_57, _masterNodeOut_a_bits_legal_T_43) node _masterNodeOut_a_bits_legal_T_59 = or(_masterNodeOut_a_bits_legal_T_58, _masterNodeOut_a_bits_legal_T_48) node _masterNodeOut_a_bits_legal_T_60 = or(_masterNodeOut_a_bits_legal_T_59, _masterNodeOut_a_bits_legal_T_53) node _masterNodeOut_a_bits_legal_T_61 = and(_masterNodeOut_a_bits_legal_T_13, _masterNodeOut_a_bits_legal_T_60) node _masterNodeOut_a_bits_legal_T_62 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_9) node masterNodeOut_a_bits_legal = or(_masterNodeOut_a_bits_legal_T_62, _masterNodeOut_a_bits_legal_T_61) wire masterNodeOut_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect masterNodeOut_a_bits_a.opcode, UInt<3>(0h4) connect masterNodeOut_a_bits_a.param, UInt<1>(0h0) connect masterNodeOut_a_bits_a.size, UInt<3>(0h6) connect masterNodeOut_a_bits_a.source, UInt<1>(0h0) connect masterNodeOut_a_bits_a.address, _masterNodeOut_a_bits_T_1 node _masterNodeOut_a_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0)) node masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T, 1, 0) node _masterNodeOut_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount) node _masterNodeOut_a_bits_a_mask_sizeOH_T_2 = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T_1, 2, 0) node masterNodeOut_a_bits_a_mask_sizeOH = or(_masterNodeOut_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3)) node masterNodeOut_a_bits_a_mask_sub_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 2, 2) node masterNodeOut_a_bits_a_mask_sub_sub_bit = bits(_masterNodeOut_a_bits_T_1, 2, 2) node masterNodeOut_a_bits_a_mask_sub_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_0_2) node masterNodeOut_a_bits_a_mask_sub_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T) node masterNodeOut_a_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_1_2) node masterNodeOut_a_bits_a_mask_sub_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1) node masterNodeOut_a_bits_a_mask_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 1, 1) node masterNodeOut_a_bits_a_mask_sub_bit = bits(_masterNodeOut_a_bits_T_1, 1, 1) node masterNodeOut_a_bits_a_mask_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_sub_0_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_0_2) node masterNodeOut_a_bits_a_mask_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T) node masterNodeOut_a_bits_a_mask_sub_1_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_1_2) node masterNodeOut_a_bits_a_mask_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_1) node masterNodeOut_a_bits_a_mask_sub_2_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_2 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_2_2) node masterNodeOut_a_bits_a_mask_sub_2_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_2) node masterNodeOut_a_bits_a_mask_sub_3_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_3 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_3_2) node masterNodeOut_a_bits_a_mask_sub_3_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_3) node masterNodeOut_a_bits_a_mask_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 0, 0) node masterNodeOut_a_bits_a_mask_bit = bits(_masterNodeOut_a_bits_T_1, 0, 0) node masterNodeOut_a_bits_a_mask_nbit = eq(masterNodeOut_a_bits_a_mask_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_eq = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq) node masterNodeOut_a_bits_a_mask_acc = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T) node masterNodeOut_a_bits_a_mask_eq_1 = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_1 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_1) node masterNodeOut_a_bits_a_mask_acc_1 = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T_1) node masterNodeOut_a_bits_a_mask_eq_2 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_2 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_2) node masterNodeOut_a_bits_a_mask_acc_2 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_2) node masterNodeOut_a_bits_a_mask_eq_3 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_3 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_3) node masterNodeOut_a_bits_a_mask_acc_3 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_3) node masterNodeOut_a_bits_a_mask_eq_4 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_4 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_4) node masterNodeOut_a_bits_a_mask_acc_4 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_4) node masterNodeOut_a_bits_a_mask_eq_5 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_5 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_5) node masterNodeOut_a_bits_a_mask_acc_5 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_5) node masterNodeOut_a_bits_a_mask_eq_6 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_6 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_6) node masterNodeOut_a_bits_a_mask_acc_6 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_6) node masterNodeOut_a_bits_a_mask_eq_7 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_7 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_7) node masterNodeOut_a_bits_a_mask_acc_7 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_7) node masterNodeOut_a_bits_a_mask_lo_lo = cat(masterNodeOut_a_bits_a_mask_acc_1, masterNodeOut_a_bits_a_mask_acc) node masterNodeOut_a_bits_a_mask_lo_hi = cat(masterNodeOut_a_bits_a_mask_acc_3, masterNodeOut_a_bits_a_mask_acc_2) node masterNodeOut_a_bits_a_mask_lo = cat(masterNodeOut_a_bits_a_mask_lo_hi, masterNodeOut_a_bits_a_mask_lo_lo) node masterNodeOut_a_bits_a_mask_hi_lo = cat(masterNodeOut_a_bits_a_mask_acc_5, masterNodeOut_a_bits_a_mask_acc_4) node masterNodeOut_a_bits_a_mask_hi_hi = cat(masterNodeOut_a_bits_a_mask_acc_7, masterNodeOut_a_bits_a_mask_acc_6) node masterNodeOut_a_bits_a_mask_hi = cat(masterNodeOut_a_bits_a_mask_hi_hi, masterNodeOut_a_bits_a_mask_hi_lo) node _masterNodeOut_a_bits_a_mask_T = cat(masterNodeOut_a_bits_a_mask_hi, masterNodeOut_a_bits_a_mask_lo) connect masterNodeOut_a_bits_a.mask, _masterNodeOut_a_bits_a_mask_T invalidate masterNodeOut_a_bits_a.data connect masterNodeOut_a_bits_a.corrupt, UInt<1>(0h0) connect masterNodeOut.a.bits, masterNodeOut_a_bits_a wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<1>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<3>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.valid, UInt<1>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_6.bits.sink, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) node _T_38 = eq(refill_valid, UInt<1>(0h0)) when _T_38 : connect invalidated, UInt<1>(0h0) when refill_fire : connect refill_valid, UInt<1>(0h1) when refill_done : connect refill_valid, UInt<1>(0h0)	module ShuttleICache( // @[ICache.scala:30:7] input clock, // @[ICache.scala:30:7] input reset, // @[ICache.scala:30:7] input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_req_valid, // @[ICache.scala:36:14] input [38:0] io_req_bits, // @[ICache.scala:36:14] input io_s1_kill, // @[ICache.scala:36:14] input io_s2_kill, // @[ICache.scala:36:14] input [31:0] io_s1_paddr, // @[ICache.scala:36:14] input io_invalidate, // @[ICache.scala:36:14] output io_resp_valid, // @[ICache.scala:36:14] output [63:0] io_resp_bits // @[ICache.scala:36:14] ); wire data_arrays_0_MPORT_1_mask_7; // @[ICache.scala:146:89] wire data_arrays_0_MPORT_1_mask_6; // @[ICache.scala:146:89] wire data_arrays_0_MPORT_1_mask_5; // @[ICache.scala:146:89] wire data_arrays_0_MPORT_1_mask_4; // @[ICache.scala:146:89] wire data_arrays_0_MPORT_1_mask_3; // @[ICache.scala:146:89] wire data_arrays_0_MPORT_1_mask_2; // @[ICache.scala:146:89] wire data_arrays_0_MPORT_1_mask_1; // @[ICache.scala:146:89] wire data_arrays_0_MPORT_1_mask_0; // @[ICache.scala:146:89] wire tag_array_MPORT_mask_7; // @[ICache.scala:94:97] wire tag_array_MPORT_mask_6; // @[ICache.scala:94:97] wire tag_array_MPORT_mask_5; // @[ICache.scala:94:97] wire tag_array_MPORT_mask_4; // @[ICache.scala:94:97] wire tag_array_MPORT_mask_3; // @[ICache.scala:94:97] wire tag_array_MPORT_mask_2; // @[ICache.scala:94:97] wire tag_array_MPORT_mask_1; // @[ICache.scala:94:97] wire tag_array_MPORT_mask_0; // @[ICache.scala:94:97] wire [511:0] _data_arrays_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [159:0] _tag_array_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire _repl_way_prng_io_out_0; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_1; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_2; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_3; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_4; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_5; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_6; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_7; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_8; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_9; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_10; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_11; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_12; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_13; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_14; // @[PRNG.scala:91:22] wire _repl_way_prng_io_out_15; // @[PRNG.scala:91:22] wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[ICache.scala:30:7] wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[ICache.scala:30:7] wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[ICache.scala:30:7] wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[ICache.scala:30:7] wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[ICache.scala:30:7] wire auto_master_out_d_bits_source_0 = auto_master_out_d_bits_source; // @[ICache.scala:30:7] wire [2:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[ICache.scala:30:7] wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[ICache.scala:30:7] wire [63:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[ICache.scala:30:7] wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[ICache.scala:30:7] wire io_req_valid_0 = io_req_valid; // @[ICache.scala:30:7] wire [38:0] io_req_bits_0 = io_req_bits; // @[ICache.scala:30:7] wire io_s1_kill_0 = io_s1_kill; // @[ICache.scala:30:7] wire io_s2_kill_0 = io_s2_kill; // @[ICache.scala:30:7] wire [31:0] io_s1_paddr_0 = io_s1_paddr; // @[ICache.scala:30:7] wire io_invalidate_0 = io_invalidate; // @[ICache.scala:30:7] wire auto_master_out_d_ready = 1'h1; // @[ICache.scala:30:7] wire masterNodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire _refill_fire_T_1 = 1'h1; // @[ICache.scala:61:38] wire _s0_ren_T = 1'h1; // @[ICache.scala:137:111] wire _masterNodeOut_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _masterNodeOut_a_bits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _masterNodeOut_a_bits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _masterNodeOut_a_bits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _masterNodeOut_a_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _masterNodeOut_a_bits_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _masterNodeOut_a_bits_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _masterNodeOut_a_bits_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire masterNodeOut_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire masterNodeOut_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire masterNodeOut_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire [2:0] auto_master_out_a_bits_opcode = 3'h4; // @[ICache.scala:30:7] wire [2:0] masterNodeOut_a_bits_opcode = 3'h4; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_a_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] _masterNodeOut_a_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] auto_master_out_a_bits_param = 3'h0; // @[ICache.scala:30:7] wire [2:0] masterNodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_a_param = 3'h0; // @[Edges.scala:460:17] wire [3:0] auto_master_out_a_bits_size = 4'h6; // @[ICache.scala:30:7] wire [3:0] masterNodeOut_a_bits_size = 4'h6; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_a_bits_a_size = 4'h6; // @[Edges.scala:460:17] wire auto_master_out_a_bits_source = 1'h0; // @[ICache.scala:30:7] wire auto_master_out_a_bits_corrupt = 1'h0; // @[ICache.scala:30:7] wire masterNodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire s2_full_word_write = 1'h0; // @[ICache.scala:161:36] wire masterNodeOut_a_bits_a_source = 1'h0; // @[Edges.scala:460:17] wire masterNodeOut_a_bits_a_corrupt = 1'h0; // @[Edges.scala:460:17] wire masterNodeOut_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _masterNodeOut_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire [7:0] auto_master_out_a_bits_mask = 8'hFF; // @[ICache.scala:30:7] wire [7:0] masterNodeOut_a_bits_mask = 8'hFF; // @[MixedNode.scala:542:17] wire [7:0] masterNodeOut_a_bits_a_mask = 8'hFF; // @[Edges.scala:460:17] wire [7:0] _masterNodeOut_a_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire [63:0] auto_master_out_a_bits_data = 64'h0; // @[ICache.scala:30:7] wire [63:0] masterNodeOut_a_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] masterNodeOut_a_bits_a_data = 64'h0; // @[Edges.scala:460:17] wire [3:0] masterNodeOut_a_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] masterNodeOut_a_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [2:0] masterNodeOut_a_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [3:0] _masterNodeOut_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [1:0] masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [2:0] _masterNodeOut_a_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[ICache.scala:30:7] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[ICache.scala:30:7] wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[ICache.scala:30:7] wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[ICache.scala:30:7] wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[ICache.scala:30:7] wire masterNodeOut_d_bits_source = auto_master_out_d_bits_source_0; // @[ICache.scala:30:7] wire [2:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[ICache.scala:30:7] wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[ICache.scala:30:7] wire [63:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[ICache.scala:30:7] wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[ICache.scala:30:7] wire _io_req_ready_T; // @[ICache.scala:72:19] wire invalidate = io_invalidate_0; // @[ICache.scala:30:7, :102:28] wire _io_resp_valid_T; // @[ICache.scala:167:29] wire [63:0] s2_way_mux; // @[Mux.scala:30:73] wire [31:0] auto_master_out_a_bits_address_0; // @[ICache.scala:30:7] wire auto_master_out_a_valid_0; // @[ICache.scala:30:7] wire io_req_ready; // @[ICache.scala:30:7] wire io_resp_valid_0; // @[ICache.scala:30:7] wire [63:0] io_resp_bits_0; // @[ICache.scala:30:7] wire s2_request_refill; // @[ICache.scala:65:35] assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[ICache.scala:30:7] wire [31:0] masterNodeOut_a_bits_a_address; // @[Edges.scala:460:17] assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[ICache.scala:30:7] wire _refill_one_beat_T = masterNodeOut_d_valid; // @[Decoupled.scala:51:35] wire [63:0] data = masterNodeOut_d_bits_data; // @[ICache.scala:144:36] wire s0_valid = io_req_ready & io_req_valid_0; // @[Decoupled.scala:51:35] wire s0_ren = s0_valid; // @[Decoupled.scala:51:35] reg s1_valid; // @[ICache.scala:51:25] reg [38:0] s1_vaddr; // @[ICache.scala:52:27] wire tagMatch; // @[ICache.scala:118:26] wire tagMatch_1; // @[ICache.scala:118:26] wire tagMatch_2; // @[ICache.scala:118:26] wire tagMatch_3; // @[ICache.scala:118:26] wire tagMatch_4; // @[ICache.scala:118:26] wire tagMatch_5; // @[ICache.scala:118:26] wire tagMatch_6; // @[ICache.scala:118:26] wire tagMatch_7; // @[ICache.scala:118:26] wire s1_tag_hit_0; // @[ICache.scala:53:24] wire s1_tag_hit_1; // @[ICache.scala:53:24] wire s1_tag_hit_2; // @[ICache.scala:53:24] wire s1_tag_hit_3; // @[ICache.scala:53:24] wire s1_tag_hit_4; // @[ICache.scala:53:24] wire s1_tag_hit_5; // @[ICache.scala:53:24] wire s1_tag_hit_6; // @[ICache.scala:53:24] wire s1_tag_hit_7; // @[ICache.scala:53:24] wire _s1_hit_T = s1_tag_hit_0 \| s1_tag_hit_1; // @[ICache.scala:53:24, :54:35] wire _s1_hit_T_1 = _s1_hit_T \| s1_tag_hit_2; // @[ICache.scala:53:24, :54:35] wire _s1_hit_T_2 = _s1_hit_T_1 \| s1_tag_hit_3; // @[ICache.scala:53:24, :54:35] wire _s1_hit_T_3 = _s1_hit_T_2 \| s1_tag_hit_4; // @[ICache.scala:53:24, :54:35] wire _s1_hit_T_4 = _s1_hit_T_3 \| s1_tag_hit_5; // @[ICache.scala:53:24, :54:35] wire _s1_hit_T_5 = _s1_hit_T_4 \| s1_tag_hit_6; // @[ICache.scala:53:24, :54:35] wire s1_hit = _s1_hit_T_5 \| s1_tag_hit_7; // @[ICache.scala:53:24, :54:35] wire _s2_valid_T = ~io_s1_kill_0; // @[ICache.scala:30:7, :55:38] wire _s2_valid_T_1 = s1_valid & _s2_valid_T; // @[ICache.scala:51:25, :55:{35,38}] reg s2_valid; // @[ICache.scala:55:25] reg s2_hit; // @[ICache.scala:56:23] reg invalidated; // @[ICache.scala:58:24] reg refill_valid; // @[ICache.scala:59:29] wire _refill_fire_T = masterNodeOut_a_ready & masterNodeOut_a_valid; // @[Decoupled.scala:51:35] wire refill_fire = _refill_fire_T; // @[Decoupled.scala:51:35] wire _s2_miss_T = ~s2_hit; // @[ICache.scala:56:23, :63:29] wire _s2_miss_T_1 = s2_valid & _s2_miss_T; // @[ICache.scala:55:25, :63:{26,29}] wire _s2_miss_T_2 = ~io_s2_kill_0; // @[ICache.scala:30:7, :63:40] wire s2_miss = _s2_miss_T_1 & _s2_miss_T_2; // @[ICache.scala:63:{26,37,40}] wire _s1_can_request_refill_T = s2_miss \| refill_valid; // @[ICache.scala:59:29, :63:37, :64:41] wire s1_can_request_refill = ~_s1_can_request_refill_T; // @[ICache.scala:64:{31,41}] reg s2_request_refill_REG; // @[ICache.scala:65:45] assign s2_request_refill = s2_miss & s2_request_refill_REG; // @[ICache.scala:63:37, :65:{35,45}] assign masterNodeOut_a_valid = s2_request_refill; // @[ICache.scala:65:35] wire _GEN = s1_valid & s1_can_request_refill; // @[ICache.scala:51:25, :64:31, :66:54] wire _refill_paddr_T; // @[ICache.scala:66:54] assign _refill_paddr_T = _GEN; // @[ICache.scala:66:54] wire _refill_vaddr_T; // @[ICache.scala:67:51] assign _refill_vaddr_T = _GEN; // @[ICache.scala:66:54, :67:51] reg [31:0] refill_paddr; // @[ICache.scala:66:31] reg [38:0] refill_vaddr; // @[ICache.scala:67:31] wire [19:0] refill_tag = refill_paddr[31:12]; // @[ICache.scala:66:31, :68:33] wire [5:0] refill_idx = refill_paddr[11:6]; // @[ICache.scala:66:31, :212:21] wire refill_one_beat_opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire r_beats1_opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire refill_one_beat = _refill_one_beat_T & refill_one_beat_opdata; // @[Decoupled.scala:51:35] assign _io_req_ready_T = ~refill_one_beat; // @[ICache.scala:70:39, :72:19] assign io_req_ready = _io_req_ready_T; // @[ICache.scala:30:7, :72:19] wire [26:0] _r_beats1_decode_T = 27'hFFF << masterNodeOut_d_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_done = r_2 & masterNodeOut_d_valid; // @[Edges.scala:232:33, :233:22] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] refill_cnt = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire refill_done = refill_one_beat & d_done; // @[ICache.scala:70:39, :76:37] wire [1:0] repl_way_lo_lo_lo = {_repl_way_prng_io_out_1, _repl_way_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_lo_lo_hi = {_repl_way_prng_io_out_3, _repl_way_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_lo_lo = {repl_way_lo_lo_hi, repl_way_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] repl_way_lo_hi_lo = {_repl_way_prng_io_out_5, _repl_way_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_lo_hi_hi = {_repl_way_prng_io_out_7, _repl_way_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_lo_hi = {repl_way_lo_hi_hi, repl_way_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] repl_way_lo = {repl_way_lo_hi, repl_way_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] repl_way_hi_lo_lo = {_repl_way_prng_io_out_9, _repl_way_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_hi_lo_hi = {_repl_way_prng_io_out_11, _repl_way_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_hi_lo = {repl_way_hi_lo_hi, repl_way_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] repl_way_hi_hi_lo = {_repl_way_prng_io_out_13, _repl_way_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_hi_hi_hi = {_repl_way_prng_io_out_15, _repl_way_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_hi_hi = {repl_way_hi_hi_hi, repl_way_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] repl_way_hi = {repl_way_hi_hi, repl_way_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] _repl_way_T = {repl_way_hi, repl_way_lo}; // @[PRNG.scala:95:17] wire [2:0] repl_way = _repl_way_T[2:0]; // @[PRNG.scala:95:17] wire [5:0] _tag_rdata_WIRE; // @[ICache.scala:90:33] wire _tag_rdata_T_2; // @[ICache.scala:90:83] wire [5:0] _tag_rdata_T = io_req_bits_0[11:6]; // @[ICache.scala:30:7, :90:42] assign _tag_rdata_WIRE = _tag_rdata_T; // @[ICache.scala:90:{33,42}] wire _tag_rdata_T_1 = ~refill_done; // @[ICache.scala:76:37, :90:70] assign _tag_rdata_T_2 = _tag_rdata_T_1 & s0_valid; // @[Decoupled.scala:51:35] assign tag_array_MPORT_mask_0 = ~(\|repl_way); // @[ICache.scala:81:26, :94:97] assign tag_array_MPORT_mask_1 = repl_way == 3'h1; // @[ICache.scala:81:26, :94:97] assign tag_array_MPORT_mask_2 = repl_way == 3'h2; // @[ICache.scala:81:26, :94:97] assign tag_array_MPORT_mask_3 = repl_way == 3'h3; // @[ICache.scala:81:26, :94:97] assign tag_array_MPORT_mask_4 = repl_way == 3'h4; // @[ICache.scala:81:26, :94:97] assign tag_array_MPORT_mask_5 = repl_way == 3'h5; // @[ICache.scala:81:26, :94:97] assign tag_array_MPORT_mask_6 = repl_way == 3'h6; // @[ICache.scala:81:26, :94:97] assign tag_array_MPORT_mask_7 = &repl_way; // @[ICache.scala:81:26, :94:97] reg [511:0] vb_array; // @[ICache.scala:97:25] wire [8:0] _vb_array_T = {repl_way, refill_idx}; // @[ICache.scala:81:26, :100:36, :212:21] wire _vb_array_T_1 = ~invalidated; // @[ICache.scala:58:24, :100:75] wire _vb_array_T_2 = refill_done & _vb_array_T_1; // @[ICache.scala:76:37, :100:{72,75}] wire [511:0] _vb_array_T_3 = 512'h1 << _vb_array_T; // @[ICache.scala:100:{32,36}] wire [511:0] _vb_array_T_4 = vb_array \| _vb_array_T_3; // @[ICache.scala:97:25, :100:32] wire [511:0] _vb_array_T_5 = ~vb_array; // @[ICache.scala:97:25, :100:32] wire [511:0] _vb_array_T_6 = _vb_array_T_5 \| _vb_array_T_3; // @[ICache.scala:100:32] wire [511:0] _vb_array_T_7 = ~_vb_array_T_6; // @[ICache.scala:100:32] wire [511:0] _vb_array_T_8 = _vb_array_T_2 ? _vb_array_T_4 : _vb_array_T_7; // @[ICache.scala:100:{32,72}] wire [63:0] s1_dout_0; // @[ICache.scala:109:21] wire [63:0] s1_dout_1; // @[ICache.scala:109:21] wire [63:0] s1_dout_2; // @[ICache.scala:109:21] wire [63:0] s1_dout_3; // @[ICache.scala:109:21] wire [63:0] s1_dout_4; // @[ICache.scala:109:21] wire [63:0] s1_dout_5; // @[ICache.scala:109:21] wire [63:0] s1_dout_6; // @[ICache.scala:109:21] wire [63:0] s1_dout_7; // @[ICache.scala:109:21] wire [5:0] s1_idx = io_s1_paddr_0[11:6]; // @[ICache.scala:30:7, :212:21] wire [5:0] s1_idx_1 = io_s1_paddr_0[11:6]; // @[ICache.scala:30:7, :212:21] wire [5:0] s1_idx_2 = io_s1_paddr_0[11:6]; // @[ICache.scala:30:7, :212:21] wire [5:0] s1_idx_3 = io_s1_paddr_0[11:6]; // @[ICache.scala:30:7, :212:21] wire [5:0] s1_idx_4 = io_s1_paddr_0[11:6]; // @[ICache.scala:30:7, :212:21] wire [5:0] s1_idx_5 = io_s1_paddr_0[11:6]; // @[ICache.scala:30:7, :212:21] wire [5:0] s1_idx_6 = io_s1_paddr_0[11:6]; // @[ICache.scala:30:7, :212:21] wire [5:0] s1_idx_7 = io_s1_paddr_0[11:6]; // @[ICache.scala:30:7, :212:21] wire [19:0] s1_tag = io_s1_paddr_0[31:12]; // @[ICache.scala:30:7, :114:30] wire [19:0] s1_tag_1 = io_s1_paddr_0[31:12]; // @[ICache.scala:30:7, :114:30] wire [19:0] s1_tag_2 = io_s1_paddr_0[31:12]; // @[ICache.scala:30:7, :114:30] wire [19:0] s1_tag_3 = io_s1_paddr_0[31:12]; // @[ICache.scala:30:7, :114:30] wire [19:0] s1_tag_4 = io_s1_paddr_0[31:12]; // @[ICache.scala:30:7, :114:30] wire [19:0] s1_tag_5 = io_s1_paddr_0[31:12]; // @[ICache.scala:30:7, :114:30] wire [19:0] s1_tag_6 = io_s1_paddr_0[31:12]; // @[ICache.scala:30:7, :114:30] wire [19:0] s1_tag_7 = io_s1_paddr_0[31:12]; // @[ICache.scala:30:7, :114:30] wire [6:0] _s1_vb_T = {1'h0, s1_idx}; // @[ICache.scala:115:29, :212:21] wire [511:0] _s1_vb_T_1 = vb_array >> _s1_vb_T; // @[ICache.scala:97:25, :115:{25,29}] wire s1_vb = _s1_vb_T_1[0]; // @[ICache.scala:115:25] wire _tagMatch_T = _tag_array_RW0_rdata[19:0] == s1_tag; // @[ICache.scala:114:30, :118:33] assign tagMatch = s1_vb & _tagMatch_T; // @[ICache.scala:115:25, :118:{26,33}] assign s1_tag_hit_0 = tagMatch; // @[ICache.scala:53:24, :118:26] wire [6:0] _s1_vb_T_2 = {1'h1, s1_idx_1}; // @[ICache.scala:115:29, :212:21] wire [511:0] _s1_vb_T_3 = vb_array >> _s1_vb_T_2; // @[ICache.scala:97:25, :115:{25,29}] wire s1_vb_1 = _s1_vb_T_3[0]; // @[ICache.scala:115:25] wire _tagMatch_T_1 = _tag_array_RW0_rdata[39:20] == s1_tag_1; // @[ICache.scala:114:30, :118:33] assign tagMatch_1 = s1_vb_1 & _tagMatch_T_1; // @[ICache.scala:115:25, :118:{26,33}] assign s1_tag_hit_1 = tagMatch_1; // @[ICache.scala:53:24, :118:26] wire [7:0] _s1_vb_T_4 = {2'h2, s1_idx_2}; // @[ICache.scala:115:29, :212:21] wire [511:0] _s1_vb_T_5 = vb_array >> _s1_vb_T_4; // @[ICache.scala:97:25, :115:{25,29}] wire s1_vb_2 = _s1_vb_T_5[0]; // @[ICache.scala:115:25] wire _tagMatch_T_2 = _tag_array_RW0_rdata[59:40] == s1_tag_2; // @[ICache.scala:114:30, :118:33] assign tagMatch_2 = s1_vb_2 & _tagMatch_T_2; // @[ICache.scala:115:25, :118:{26,33}] assign s1_tag_hit_2 = tagMatch_2; // @[ICache.scala:53:24, :118:26] wire [7:0] _s1_vb_T_6 = {2'h3, s1_idx_3}; // @[ICache.scala:115:29, :212:21] wire [511:0] _s1_vb_T_7 = vb_array >> _s1_vb_T_6; // @[ICache.scala:97:25, :115:{25,29}] wire s1_vb_3 = _s1_vb_T_7[0]; // @[ICache.scala:115:25] wire _tagMatch_T_3 = _tag_array_RW0_rdata[79:60] == s1_tag_3; // @[ICache.scala:114:30, :118:33] assign tagMatch_3 = s1_vb_3 & _tagMatch_T_3; // @[ICache.scala:115:25, :118:{26,33}] assign s1_tag_hit_3 = tagMatch_3; // @[ICache.scala:53:24, :118:26] wire [8:0] _s1_vb_T_8 = {3'h4, s1_idx_4}; // @[ICache.scala:115:29, :212:21] wire [511:0] _s1_vb_T_9 = vb_array >> _s1_vb_T_8; // @[ICache.scala:97:25, :115:{25,29}] wire s1_vb_4 = _s1_vb_T_9[0]; // @[ICache.scala:115:25] wire _tagMatch_T_4 = _tag_array_RW0_rdata[99:80] == s1_tag_4; // @[ICache.scala:114:30, :118:33] assign tagMatch_4 = s1_vb_4 & _tagMatch_T_4; // @[ICache.scala:115:25, :118:{26,33}] assign s1_tag_hit_4 = tagMatch_4; // @[ICache.scala:53:24, :118:26] wire [8:0] _s1_vb_T_10 = {3'h5, s1_idx_5}; // @[ICache.scala:115:29, :212:21] wire [511:0] _s1_vb_T_11 = vb_array >> _s1_vb_T_10; // @[ICache.scala:97:25, :115:{25,29}] wire s1_vb_5 = _s1_vb_T_11[0]; // @[ICache.scala:115:25] wire _tagMatch_T_5 = _tag_array_RW0_rdata[119:100] == s1_tag_5; // @[ICache.scala:114:30, :118:33] assign tagMatch_5 = s1_vb_5 & _tagMatch_T_5; // @[ICache.scala:115:25, :118:{26,33}] assign s1_tag_hit_5 = tagMatch_5; // @[ICache.scala:53:24, :118:26] wire [8:0] _s1_vb_T_12 = {3'h6, s1_idx_6}; // @[ICache.scala:115:29, :212:21] wire [511:0] _s1_vb_T_13 = vb_array >> _s1_vb_T_12; // @[ICache.scala:97:25, :115:{25,29}] wire s1_vb_6 = _s1_vb_T_13[0]; // @[ICache.scala:115:25] wire _tagMatch_T_6 = _tag_array_RW0_rdata[139:120] == s1_tag_6; // @[ICache.scala:114:30, :118:33] assign tagMatch_6 = s1_vb_6 & _tagMatch_T_6; // @[ICache.scala:115:25, :118:{26,33}] assign s1_tag_hit_6 = tagMatch_6; // @[ICache.scala:53:24, :118:26] wire [8:0] _s1_vb_T_14 = {3'h7, s1_idx_7}; // @[ICache.scala:115:29, :212:21] wire [511:0] _s1_vb_T_15 = vb_array >> _s1_vb_T_14; // @[ICache.scala:97:25, :115:{25,29}] wire s1_vb_7 = _s1_vb_T_15[0]; // @[ICache.scala:115:25] wire _tagMatch_T_7 = _tag_array_RW0_rdata[159:140] == s1_tag_7; // @[ICache.scala:114:30, :118:33] assign tagMatch_7 = s1_vb_7 & _tagMatch_T_7; // @[ICache.scala:115:25, :118:{26,33}] assign s1_tag_hit_7 = tagMatch_7; // @[ICache.scala:53:24, :118:26]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_165 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_165( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_505 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_505( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_179 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_194 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_179( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_194 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_22 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T	module MulAddRecFNToRaw_preMul_e8_s24_22( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero \| rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T \| _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign \| _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = \|_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = \|_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = \|_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = \|_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = \|_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = \|_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = \|_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = \|_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = \|_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 \| reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 \| _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 \| _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN \| rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e5_s11_4 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<23>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 22, 22) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 21, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 35, 12) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 12, 11) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 33, 13) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 11, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 12, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 23, 8) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 10, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 0) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[3] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 10, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_reducedVec[0]) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<5>(0h10)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 2, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 0, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_5, 1, 1) node _CDom_reduced4SigExtra_T_8 = cat(_CDom_reduced4SigExtra_T_6, _CDom_reduced4SigExtra_T_7) node _CDom_reduced4SigExtra_T_9 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_8) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_9) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 25, 25) node _notCDom_absSigSum_T = bits(sigSum, 24, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 24, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[13] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 24, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = mux(_notCDom_normDistReduced2_T_1, UInt<4>(0hb), UInt<4>(0hc)) node _notCDom_normDistReduced2_T_14 = mux(_notCDom_normDistReduced2_T_2, UInt<4>(0ha), _notCDom_normDistReduced2_T_13) node _notCDom_normDistReduced2_T_15 = mux(_notCDom_normDistReduced2_T_3, UInt<4>(0h9), _notCDom_normDistReduced2_T_14) node _notCDom_normDistReduced2_T_16 = mux(_notCDom_normDistReduced2_T_4, UInt<4>(0h8), _notCDom_normDistReduced2_T_15) node _notCDom_normDistReduced2_T_17 = mux(_notCDom_normDistReduced2_T_5, UInt<3>(0h7), _notCDom_normDistReduced2_T_16) node _notCDom_normDistReduced2_T_18 = mux(_notCDom_normDistReduced2_T_6, UInt<3>(0h6), _notCDom_normDistReduced2_T_17) node _notCDom_normDistReduced2_T_19 = mux(_notCDom_normDistReduced2_T_7, UInt<3>(0h5), _notCDom_normDistReduced2_T_18) node _notCDom_normDistReduced2_T_20 = mux(_notCDom_normDistReduced2_T_8, UInt<3>(0h4), _notCDom_normDistReduced2_T_19) node _notCDom_normDistReduced2_T_21 = mux(_notCDom_normDistReduced2_T_9, UInt<2>(0h3), _notCDom_normDistReduced2_T_20) node _notCDom_normDistReduced2_T_22 = mux(_notCDom_normDistReduced2_T_10, UInt<2>(0h2), _notCDom_normDistReduced2_T_21) node _notCDom_normDistReduced2_T_23 = mux(_notCDom_normDistReduced2_T_11, UInt<1>(0h1), _notCDom_normDistReduced2_T_22) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_12, UInt<1>(0h0), _notCDom_normDistReduced2_T_23) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 25, 10) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 5, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 1) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[4] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 6, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_reducedVec[1], notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_reducedVec[3], notCDom_reduced4SigExtra_reducedVec[2]) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 3, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 1, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 0, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_6, 1, 1) node _notCDom_reduced4SigExtra_T_9 = cat(_notCDom_reduced4SigExtra_T_7, _notCDom_reduced4SigExtra_T_8) node _notCDom_reduced4SigExtra_T_10 = bits(_notCDom_reduced4SigExtra_T_5, 2, 2) node _notCDom_reduced4SigExtra_T_11 = cat(_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_10) node _notCDom_reduced4SigExtra_T_12 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_11) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_12) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 13, 12) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T	module MulAddRecFNToRaw_postMul_e5_s11_4( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [6:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [3:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [12:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [22:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [6:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [13:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [6:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [3:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [12:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [22:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[MulAddRecFN.scala:169:7] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [6:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [13:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [6:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [13:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[MulAddRecFN.scala:169:7, :186:45] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[22]; // @[MulAddRecFN.scala:169:7, :192:32] wire [13:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 14'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [12:0] _sigSum_T_2 = _sigSum_T_1[12:0]; // @[MulAddRecFN.scala:193:47] wire [12:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [21:0] _sigSum_T_4 = io_mulAddResult_0[21:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [34:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [35:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [7:0] _GEN = {io_fromPreMul_sExpSum_0[6], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [7:0] _CDom_sExp_T_1 = _GEN - {{6{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [6:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[6:0]; // @[MulAddRecFN.scala:203:43] wire [6:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [23:0] _CDom_absSigSum_T = sigSum[35:12]; // @[MulAddRecFN.scala:192:12, :206:20] wire [23:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[12:11]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [20:0] _CDom_absSigSum_T_4 = sigSum[33:13]; // @[MulAddRecFN.scala:192:12, :210:23] wire [23:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [23:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [10:0] _CDom_absSigSumExtra_T = sigSum[11:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [10:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = \|_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [11:0] _CDom_absSigSumExtra_T_3 = sigSum[12:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = \|_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [38:0] _CDom_mainSig_T = {15'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [15:0] CDom_mainSig = _CDom_mainSig_T[23:8]; // @[MulAddRecFN.scala:219:{24,56}] wire [10:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[10:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [10:0] _CDom_reduced4SigExtra_T_1 = _CDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = \|_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = \|_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[10:8]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = \|_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[3:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [1:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [4:0] CDom_reduced4SigExtra_shift = $signed(5'sh10 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [1:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[2:1]; // @[primitives.scala:76:56, :78:22] wire _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[0]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_5[1]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_8 = {_CDom_reduced4SigExtra_T_6, _CDom_reduced4SigExtra_T_7}; // @[primitives.scala:77:20] wire [2:0] _CDom_reduced4SigExtra_T_9 = {1'h0, _CDom_reduced4SigExtra_T_2[1:0] & _CDom_reduced4SigExtra_T_8}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = \|_CDom_reduced4SigExtra_T_9; // @[MulAddRecFN.scala:222:72, :223:73] wire [12:0] _CDom_sig_T = CDom_mainSig[15:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = \|_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 \| CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 \| CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [13:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[25]; // @[MulAddRecFN.scala:192:12, :232:36] wire [24:0] _notCDom_absSigSum_T = sigSum[24:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [24:0] _notCDom_absSigSum_T_2 = sigSum[24:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [24:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [25:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {25'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [24:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[24:0]; // @[MulAddRecFN.scala:236:41] wire [24:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[24]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire [3:0] _notCDom_normDistReduced2_T_13 = _notCDom_normDistReduced2_T_1 ? 4'hB : 4'hC; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_14 = _notCDom_normDistReduced2_T_2 ? 4'hA : _notCDom_normDistReduced2_T_13; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_15 = _notCDom_normDistReduced2_T_3 ? 4'h9 : _notCDom_normDistReduced2_T_14; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_16 = _notCDom_normDistReduced2_T_4 ? 4'h8 : _notCDom_normDistReduced2_T_15; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_17 = _notCDom_normDistReduced2_T_5 ? 4'h7 : _notCDom_normDistReduced2_T_16; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_18 = _notCDom_normDistReduced2_T_6 ? 4'h6 : _notCDom_normDistReduced2_T_17; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_19 = _notCDom_normDistReduced2_T_7 ? 4'h5 : _notCDom_normDistReduced2_T_18; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_20 = _notCDom_normDistReduced2_T_8 ? 4'h4 : _notCDom_normDistReduced2_T_19; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_21 = _notCDom_normDistReduced2_T_9 ? 4'h3 : _notCDom_normDistReduced2_T_20; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_22 = _notCDom_normDistReduced2_T_10 ? 4'h2 : _notCDom_normDistReduced2_T_21; // @[Mux.scala:50:70] wire [3:0] _notCDom_normDistReduced2_T_23 = _notCDom_normDistReduced2_T_11 ? 4'h1 : _notCDom_normDistReduced2_T_22; // @[Mux.scala:50:70] wire [3:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_12 ? 4'h0 : _notCDom_normDistReduced2_T_23; // @[Mux.scala:50:70] wire [4:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [5:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [7:0] _notCDom_sExp_T_1 = _GEN - {{2{_notCDom_sExp_T[5]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [6:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[6:0]; // @[MulAddRecFN.scala:241:46] wire [6:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [55:0] _notCDom_mainSig_T = {31'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [15:0] notCDom_mainSig = _notCDom_mainSig_T[25:10]; // @[MulAddRecFN.scala:243:{27,50}] wire [5:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[5:0]; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_1 = {_notCDom_reduced4SigExtra_T, 1'h0}; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[6]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = _notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_reducedVec_1, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_reducedVec_3, notCDom_reduced4SigExtra_reducedVec_2}; // @[primitives.scala:101:30, :107:20] wire [3:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [2:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[3:1]; // @[Mux.scala:50:70] wire [2:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] notCDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [2:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[3:1]; // @[primitives.scala:76:56, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[1:0]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_6[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_9 = {_notCDom_reduced4SigExtra_T_7, _notCDom_reduced4SigExtra_T_8}; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_10 = _notCDom_reduced4SigExtra_T_5[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _notCDom_reduced4SigExtra_T_11 = {_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_10}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_12 = {1'h0, _notCDom_reduced4SigExtra_T_2[2:0] & _notCDom_reduced4SigExtra_T_11}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = \|_notCDom_reduced4SigExtra_T_12; // @[MulAddRecFN.scala:247:78, :249:11] wire [12:0] _notCDom_sig_T = notCDom_mainSig[15:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = \|_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 \| notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [13:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[13:12]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = notCDom_completeCancellation ? roundingMode_min : _notCDom_sign_T; // @[MulAddRecFN.scala:186:45, :255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 \| io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd \| io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 \| io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 \| _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 \| _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 \| _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 \| io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros \| _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T \| _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_3 = ~roundingMode_min; // @[MulAddRecFN.scala:186:45, :287:29] wire _io_rawOut_sign_T_4 = notNaN_addZeros & _io_rawOut_sign_T_3; // @[MulAddRecFN.scala:267:58, :287:{26,29}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 \| _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_8 = notNaN_addZeros & roundingMode_min; // @[MulAddRecFN.scala:186:45, :267:58, :289:26] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 \| opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_10 = _io_rawOut_sign_T_8 & _io_rawOut_sign_T_9; // @[MulAddRecFN.scala:289:{26,46}, :290:37] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7 \| _io_rawOut_sign_T_10; // @[MulAddRecFN.scala:286:43, :288:48, :289:46] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 \| _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PeripheryBus_pbus : output auto : { coupler_to_device_named_uart_0_control_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out : { clock : Clock, reset : Reset}, flip pbus_clock_groups_in : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst pbus_clock_groups of ClockGroupAggregator_pbus inst clockGroup of ClockGroup_1 inst fixedClockNode of FixedClockBroadcast_2 inst broadcast of BundleBridgeNexus_NoOutput_1 inst fixer of TLFIFOFixer_1 connect fixer.clock, childClock connect fixer.reset, childReset inst in_xbar of TLXbar_pbus_in_i1_o1_a29d64s10k1z3u connect in_xbar.clock, childClock connect in_xbar.reset, childReset inst out_xbar of TLXbar_pbus_out_i1_o2_a29d64s10k1z3u connect out_xbar.clock, childClock connect out_xbar.reset, childReset inst buffer of TLBuffer_a29d64s10k1z3u connect buffer.clock, childClock connect buffer.reset, childReset inst atomics of TLAtomicAutomata_pbus connect atomics.clock, childClock connect atomics.reset, childReset inst buffer_1 of TLBuffer_a29d64s10k1z3u_1 connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst coupler_to_bootaddressreg of TLInterconnectCoupler_pbus_to_bootaddressreg connect coupler_to_bootaddressreg.clock, childClock connect coupler_to_bootaddressreg.reset, childReset inst coupler_to_device_named_uart_0 of TLInterconnectCoupler_pbus_to_device_named_uart_0 connect coupler_to_device_named_uart_0.clock, childClock connect coupler_to_device_named_uart_0.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_26 connect monitor.clock, childClock connect monitor.reset, childReset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect clockGroup.auto.in, pbus_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect out_xbar.auto.anon_in, fixer.auto.anon_out connect atomics.auto.in, in_xbar.auto.anon_out connect coupler_to_bootaddressreg.auto.tl_in, out_xbar.auto.anon_out_0 connect coupler_to_device_named_uart_0.auto.tl_in, out_xbar.auto.anon_out_1 connect fixer.auto.anon_in, buffer.auto.out connect buffer.auto.in, atomics.auto.out connect in_xbar.auto.anon_in, buffer_1.auto.out connect buffer_1.auto.in, bus_xingOut connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.d, nodeIn.d connect nodeIn.a.bits, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.bits connect nodeIn.a.valid, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.valid connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.ready, nodeIn.a.ready connect bus_xingIn, auto.bus_xing_in connect pbus_clock_groups.auto.in, auto.pbus_clock_groups_in connect auto.fixedClockNode_anon_out, fixedClockNode.auto.anon_out_1 connect coupler_to_device_named_uart_0.auto.control_xing_out.d, auto.coupler_to_device_named_uart_0_control_xing_out.d connect auto.coupler_to_device_named_uart_0_control_xing_out.a.bits, coupler_to_device_named_uart_0.auto.control_xing_out.a.bits connect auto.coupler_to_device_named_uart_0_control_xing_out.a.valid, coupler_to_device_named_uart_0.auto.control_xing_out.a.valid connect coupler_to_device_named_uart_0.auto.control_xing_out.a.ready, auto.coupler_to_device_named_uart_0_control_xing_out.a.ready regreset bootAddrReg : UInt<64>, childClock, childReset, UInt<64>(0h80000000) node pad = or(bootAddrReg, UInt<64>(0h0)) node _oldBytes_T = bits(pad, 7, 0) node _oldBytes_T_1 = bits(pad, 15, 8) node _oldBytes_T_2 = bits(pad, 23, 16) node _oldBytes_T_3 = bits(pad, 31, 24) node _oldBytes_T_4 = bits(pad, 39, 32) node _oldBytes_T_5 = bits(pad, 47, 40) node _oldBytes_T_6 = bits(pad, 55, 48) node _oldBytes_T_7 = bits(pad, 63, 56) wire oldBytes : UInt<8>[8] connect oldBytes[0], _oldBytes_T connect oldBytes[1], _oldBytes_T_1 connect oldBytes[2], _oldBytes_T_2 connect oldBytes[3], _oldBytes_T_3 connect oldBytes[4], _oldBytes_T_4 connect oldBytes[5], _oldBytes_T_5 connect oldBytes[6], _oldBytes_T_6 connect oldBytes[7], _oldBytes_T_7 wire newBytes : UInt<8>[8] connect newBytes, oldBytes wire _valids_WIRE : UInt<1>[8] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) wire valids : UInt<1>[8] connect valids, _valids_WIRE node _T = or(valids[0], valids[1]) node _T_1 = or(_T, valids[2]) node _T_2 = or(_T_1, valids[3]) node _T_3 = or(_T_2, valids[4]) node _T_4 = or(_T_3, valids[5]) node _T_5 = or(_T_4, valids[6]) node _T_6 = or(_T_5, valids[7]) when _T_6 : node bootAddrReg_lo_lo = cat(newBytes[1], newBytes[0]) node bootAddrReg_lo_hi = cat(newBytes[3], newBytes[2]) node bootAddrReg_lo = cat(bootAddrReg_lo_hi, bootAddrReg_lo_lo) node bootAddrReg_hi_lo = cat(newBytes[5], newBytes[4]) node bootAddrReg_hi_hi = cat(newBytes[7], newBytes[6]) node bootAddrReg_hi = cat(bootAddrReg_hi_hi, bootAddrReg_hi_lo) node _bootAddrReg_T = cat(bootAddrReg_hi, bootAddrReg_lo) connect bootAddrReg, _bootAddrReg_T wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[8] wire out_wivalid : UInt<1>[8] wire out_roready : UInt<1>[8] wire out_woready : UInt<1>[8] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 7, 0) connect valids[0], out_f_woready when out_f_woready : connect newBytes[0], _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(oldBytes[0], UInt<8>(0h0)) node _out_T_8 = bits(_out_T_7, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 15, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 15, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 15, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 15, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_9 = bits(out_front.bits.data, 15, 8) connect valids[1], out_f_woready_1 when out_f_woready_1 : connect newBytes[1], _out_T_9 node _out_T_10 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_11 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_12 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_13 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_8, UInt<8>(0h0)) node out_prepend = cat(oldBytes[1], _out_prepend_T) node _out_T_14 = or(out_prepend, UInt<16>(0h0)) node _out_T_15 = bits(_out_T_14, 15, 0) node _out_rimask_T_2 = bits(out_frontMask, 23, 16) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 23, 16) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 23, 16) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 23, 16) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_16 = bits(out_front.bits.data, 23, 16) connect valids[2], out_f_woready_2 when out_f_woready_2 : connect newBytes[2], _out_T_16 node _out_T_17 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_18 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_19 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_20 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_15, UInt<16>(0h0)) node out_prepend_1 = cat(oldBytes[2], _out_prepend_T_1) node _out_T_21 = or(out_prepend_1, UInt<24>(0h0)) node _out_T_22 = bits(_out_T_21, 23, 0) node _out_rimask_T_3 = bits(out_frontMask, 31, 24) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 31, 24) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 31, 24) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 31, 24) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_23 = bits(out_front.bits.data, 31, 24) connect valids[3], out_f_woready_3 when out_f_woready_3 : connect newBytes[3], _out_T_23 node _out_T_24 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_25 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_26 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_27 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_22, UInt<24>(0h0)) node out_prepend_2 = cat(oldBytes[3], _out_prepend_T_2) node _out_T_28 = or(out_prepend_2, UInt<32>(0h0)) node _out_T_29 = bits(_out_T_28, 31, 0) node _out_rimask_T_4 = bits(out_frontMask, 39, 32) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 39, 32) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 39, 32) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 39, 32) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_30 = bits(out_front.bits.data, 39, 32) connect valids[4], out_f_woready_4 when out_f_woready_4 : connect newBytes[4], _out_T_30 node _out_T_31 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_32 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_33 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_34 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_29, UInt<32>(0h0)) node out_prepend_3 = cat(oldBytes[4], _out_prepend_T_3) node _out_T_35 = or(out_prepend_3, UInt<40>(0h0)) node _out_T_36 = bits(_out_T_35, 39, 0) node _out_rimask_T_5 = bits(out_frontMask, 47, 40) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 47, 40) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 47, 40) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 47, 40) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_37 = bits(out_front.bits.data, 47, 40) connect valids[5], out_f_woready_5 when out_f_woready_5 : connect newBytes[5], _out_T_37 node _out_T_38 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_39 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_40 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_41 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_36, UInt<40>(0h0)) node out_prepend_4 = cat(oldBytes[5], _out_prepend_T_4) node _out_T_42 = or(out_prepend_4, UInt<48>(0h0)) node _out_T_43 = bits(_out_T_42, 47, 0) node _out_rimask_T_6 = bits(out_frontMask, 55, 48) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 55, 48) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 55, 48) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 55, 48) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_44 = bits(out_front.bits.data, 55, 48) connect valids[6], out_f_woready_6 when out_f_woready_6 : connect newBytes[6], _out_T_44 node _out_T_45 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_46 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_47 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_48 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_43, UInt<48>(0h0)) node out_prepend_5 = cat(oldBytes[6], _out_prepend_T_5) node _out_T_49 = or(out_prepend_5, UInt<56>(0h0)) node _out_T_50 = bits(_out_T_49, 55, 0) node _out_rimask_T_7 = bits(out_frontMask, 63, 56) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 63, 56) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 63, 56) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 63, 56) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_51 = bits(out_front.bits.data, 63, 56) connect valids[7], out_f_woready_7 when out_f_woready_7 : connect newBytes[7], _out_T_51 node _out_T_52 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_53 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_54 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_55 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_50, UInt<56>(0h0)) node out_prepend_6 = cat(oldBytes[7], _out_prepend_T_6) node _out_T_56 = or(out_prepend_6, UInt<64>(0h0)) node _out_T_57 = bits(_out_T_56, 63, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[7], _out_rifireMux_T_3 connect out_rivalid[6], _out_rifireMux_T_3 connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[7], _out_wifireMux_T_4 connect out_wivalid[6], _out_wifireMux_T_4 connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[7], _out_rofireMux_T_3 connect out_roready[6], _out_rofireMux_T_3 connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[7], _out_wofireMux_T_4 connect out_woready[6], _out_wofireMux_T_4 connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<64>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_57 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<14>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<14>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset	module PeripheryBus_pbus( // @[ClockDomain.scala:14:9] input auto_coupler_to_device_named_uart_0_control_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_device_named_uart_0_control_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [13:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire nodeIn_d_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_a_bits_data; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_a_bits_mask; // @[MixedNode.scala:551:17] wire [13:0] nodeIn_a_bits_source; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_a_bits_size; // @[MixedNode.scala:551:17] wire bus_xingOut_d_valid; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17] wire [9:0] bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire bus_xingOut_a_ready; // @[MixedNode.scala:542:17] wire in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [9:0] in_xbar_in_0_d_bits_source; // @[Xbar.scala:159:18] wire [9:0] in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18] wire in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire [9:0] in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [28:0] in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [9:0] in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire [9:0] fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [9:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:53:9] wire _coupler_to_device_named_uart_0_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_device_named_uart_0_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [9:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [9:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29] wire [9:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29] wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [9:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30] wire [9:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30] wire [28:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30] wire [9:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30] wire [12:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0 = auto_coupler_to_device_named_uart_0_control_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [13:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_pbus_clock_groups_in_member_pbus_0_clock_0 = auto_pbus_clock_groups_in_member_pbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_pbus_clock_groups_in_member_pbus_0_reset_0 = auto_pbus_clock_groups_in_member_pbus_0_reset; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [9:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] fixer_auto_anon_in_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] fixer_anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] in_xbar__requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar__beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar__portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] in_xbar__portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] in_xbar_portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire pbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire pbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire pbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixer_auto_anon_in_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire fixer_anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire fixer_anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_65 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_66 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_67 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_68 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_69 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_70 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_71 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_72 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_73 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_74 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_75 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_76 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_77 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_78 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_79 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_80 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_81 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_82 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_83 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_84 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_85 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_86 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_87 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_88 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_89 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_90 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_91 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_92 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_93 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_94 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_95 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_96 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_97 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_98 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_99 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_100 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_101 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_102 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_103 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_104 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_105 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_106 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_107 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_108 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_109 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_110 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_111 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_112 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_113 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_114 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_115 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_116 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_117 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_118 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_119 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_120 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_121 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_122 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_123 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_124 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_125 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_126 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_127 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_128 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_129 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_130 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_131 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_132 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_133 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_134 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_135 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_136 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_137 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_138 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_139 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_140 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_141 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_142 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_143 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_144 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_145 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_146 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_147 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_148 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_149 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_150 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_151 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_152 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_153 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_154 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_155 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_156 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_157 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_158 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_159 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_160 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_161 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_162 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_163 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_164 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_165 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_166 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_167 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_168 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_169 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_170 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_171 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_172 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_173 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_174 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_175 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_176 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_177 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_178 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_179 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_180 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_181 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_182 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_183 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_184 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_185 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_186 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_187 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_188 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_189 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_190 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_191 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_192 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_193 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_194 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_195 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_196 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_197 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_198 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_199 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_200 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_201 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_202 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_203 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_204 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_205 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_206 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_207 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_208 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_209 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_210 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_211 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_212 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_213 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_214 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_215 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_216 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_217 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_218 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_219 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_220 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_221 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_222 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_223 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_224 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_225 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_226 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_227 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_228 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_229 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_230 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_231 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_232 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_233 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_234 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_235 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_236 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_237 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_238 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_239 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_240 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_241 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_242 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_243 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_244 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_245 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_246 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_247 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_248 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_249 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_250 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_251 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_252 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_253 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_254 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_255 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_256 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_257 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_258 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_259 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_260 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_261 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_262 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_263 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_264 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_265 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_266 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_267 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_268 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_269 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_270 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_271 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_272 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_273 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_274 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_275 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_276 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_277 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_278 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_279 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_280 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_281 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_282 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_283 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_284 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_285 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_286 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_287 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_288 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_289 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_290 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_291 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_292 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_293 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_294 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_295 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_296 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_297 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_298 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_299 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_300 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_301 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_302 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_303 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_304 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_305 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_306 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_307 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_308 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_309 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_310 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_311 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_312 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_313 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_314 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_315 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_316 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_317 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_318 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_319 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_320 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_321 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_322 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_323 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_324 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_325 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_326 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_327 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_328 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_329 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_330 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_331 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_332 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_333 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_334 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_335 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_336 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_337 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_338 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_339 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_340 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_341 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_342 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_343 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_344 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_345 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_346 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_347 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_348 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_349 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_350 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_351 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_352 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_353 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_354 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_355 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_356 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_357 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_358 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_359 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_360 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_361 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_362 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_363 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_364 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_365 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_366 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_367 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_368 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_369 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_370 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_371 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_372 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_373 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_374 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_375 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_376 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_377 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_378 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_379 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_380 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_381 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_382 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_383 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_384 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_385 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_386 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_387 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_388 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_389 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_390 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_391 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_392 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_393 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_394 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_395 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_396 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_397 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_398 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_399 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_400 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_401 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_402 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_403 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_404 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_405 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_406 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_407 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_408 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_409 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_410 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_411 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_412 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_413 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_414 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_415 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_416 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_417 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_418 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_419 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_420 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_421 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_422 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_423 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_424 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_425 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_426 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_427 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_428 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_429 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_430 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_431 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_432 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_433 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_434 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_435 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_436 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_437 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_438 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_439 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_440 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_441 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_442 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_443 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_444 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_445 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_446 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_447 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_448 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_449 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_450 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_451 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_452 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_453 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_454 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_455 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_456 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_457 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_458 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_459 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_460 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_461 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_462 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_463 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_464 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_465 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_466 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_467 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_468 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_469 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_470 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_471 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_472 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_473 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_474 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_475 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_476 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_477 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_478 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_479 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_480 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_481 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_482 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_483 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_484 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_485 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_486 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_487 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_488 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_489 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_490 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_491 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_492 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_493 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_494 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_495 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_496 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_497 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_498 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_499 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_500 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_501 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_502 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_503 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_504 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_505 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_506 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_507 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_508 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_509 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_510 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_511 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_512 = 1'h0; // @[FIFOFixer.scala:79:35] wire in_xbar__addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire in_xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire in_xbar__requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire in_xbar__beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar_beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire in_xbar__beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_xbar__portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire in_xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire in_xbar_portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire in_xbar__portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_xbar__portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire in_xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire in_xbar_portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire in_xbar__portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_xbar__portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire in_xbar__portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire in_xbar_portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire in_xbar_portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire in_xbar__portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] in_xbar__addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar__requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar__beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar__beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar__portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] in_xbar__portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] in_xbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] in_xbar__portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] in_xbar__portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] in_xbar_portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] in_xbar__addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar_beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] in_xbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] in_xbar__beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar_beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] in_xbar_beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] in_xbar__portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] in_xbar__portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar__portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] in_xbar_portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar__portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar__portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] in_xbar_portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] in_xbar_portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire in_xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire in_xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire in_xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire in_xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire in_xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire in_xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire in_xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire in_xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire in_xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire in_xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire in_xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire in_xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire in_xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire in_xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire in_xbar_beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire in_xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire in_xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire [28:0] in_xbar__addressC_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__addressC_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar__requestCIO_T = 29'h0; // @[Parameters.scala:137:31] wire [28:0] in_xbar__requestBOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__requestBOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar__beatsBO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__beatsBO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar__beatsCI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__beatsCI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar__portsBIO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74] wire [28:0] in_xbar__portsBIO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61] wire [28:0] in_xbar_portsBIO_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [28:0] in_xbar__portsCOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] in_xbar__portsCOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] in_xbar_portsCOI_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24] wire [9:0] in_xbar__addressC_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] in_xbar__addressC_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] in_xbar__requestBOI_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] in_xbar__requestBOI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] in_xbar__requestBOI_uncommonBits_T = 10'h0; // @[Parameters.scala:52:29] wire [9:0] in_xbar_requestBOI_uncommonBits = 10'h0; // @[Parameters.scala:52:56] wire [9:0] in_xbar__beatsBO_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] in_xbar__beatsBO_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] in_xbar__beatsCI_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] in_xbar__beatsCI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] in_xbar__portsBIO_WIRE_bits_source = 10'h0; // @[Bundles.scala:264:74] wire [9:0] in_xbar__portsBIO_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:264:61] wire [9:0] in_xbar_portsBIO_filtered_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [9:0] in_xbar__portsCOI_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] in_xbar__portsCOI_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] in_xbar_portsCOI_filtered_0_bits_source = 10'h0; // @[Xbar.scala:352:24] wire [7:0] in_xbar__requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar__portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] in_xbar__portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] in_xbar_portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] in_xbar__beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] in_xbar__beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] in_xbar__beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] in_xbar__beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] in_xbar__beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] in_xbar__beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [512:0] fixer__allIDs_FIFOed_T = 513'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [29:0] fixer__a_notFIFO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] fixer__a_notFIFO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestAIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestAIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestCIO_T_1 = 30'h0; // @[Parameters.scala:137:41] wire [29:0] in_xbar__requestCIO_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] in_xbar__requestCIO_T_3 = 30'h0; // @[Parameters.scala:137:46] wire pbus_clock_groups_auto_in_member_pbus_0_clock = auto_pbus_clock_groups_in_member_pbus_0_clock_0; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_auto_in_member_pbus_0_reset = auto_pbus_clock_groups_in_member_pbus_0_reset_0; // @[ClockGroup.scala:53:9] wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [9:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [9:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [13:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [9:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire pbus_clock_groups_nodeIn_member_pbus_0_clock = pbus_clock_groups_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire pbus_clock_groups_nodeIn_member_pbus_0_reset = pbus_clock_groups_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:53:9] wire pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_pbus_0_clock = pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_pbus_0_reset = pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign pbus_clock_groups_auto_out_member_pbus_0_clock = pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[ClockGroup.scala:53:9] assign pbus_clock_groups_auto_out_member_pbus_0_reset = pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[ClockGroup.scala:53:9] assign pbus_clock_groups_nodeOut_member_pbus_0_clock = pbus_clock_groups_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign pbus_clock_groups_nodeOut_member_pbus_0_reset = pbus_clock_groups_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_pbus_0_clock = clockGroup_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_pbus_0_reset = clockGroup_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [9:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [9:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [9:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [9:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9] wire [9:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [9:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [28:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [28:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] wire [29:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46] wire fixer__a_id_T_4 = fixer__a_id_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_id_T_10 = fixer__a_id_T_4; // @[Mux.scala:30:73] wire [28:0] fixer__a_id_T_5 = fixer_anonIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31] wire [29:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire [29:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 30'h10000000; // @[Parameters.scala:137:{41,46}] wire [29:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46] wire fixer__a_id_T_9 = fixer__a_id_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [1:0] fixer__a_id_T_11 = {fixer__a_id_T_9, 1'h0}; // @[Mux.scala:30:73] wire [1:0] fixer__a_id_T_12 = {1'h0, fixer__a_id_T_10} \| fixer__a_id_T_11; // @[Mux.scala:30:73] wire [1:0] fixer_a_id = fixer__a_id_T_12; // @[Mux.scala:30:73] wire fixer_a_noDomain = fixer_a_id == 2'h0; // @[Mux.scala:30:73] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__a_first_beats1_decode_T = 13'h3F << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [5:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T \| fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [12:0] fixer__d_first_beats1_decode_T = 13'h3F << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [5:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [3:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T \| fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [2:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] reg fixer_flight_3; // @[FIFOFixer.scala:79:27] reg fixer_flight_4; // @[FIFOFixer.scala:79:27] reg fixer_flight_5; // @[FIFOFixer.scala:79:27] reg fixer_flight_6; // @[FIFOFixer.scala:79:27] reg fixer_flight_7; // @[FIFOFixer.scala:79:27] reg fixer_flight_8; // @[FIFOFixer.scala:79:27] reg fixer_flight_9; // @[FIFOFixer.scala:79:27] reg fixer_flight_10; // @[FIFOFixer.scala:79:27] reg fixer_flight_11; // @[FIFOFixer.scala:79:27] reg fixer_flight_12; // @[FIFOFixer.scala:79:27] reg fixer_flight_13; // @[FIFOFixer.scala:79:27] reg fixer_flight_14; // @[FIFOFixer.scala:79:27] reg fixer_flight_15; // @[FIFOFixer.scala:79:27] reg fixer_flight_16; // @[FIFOFixer.scala:79:27] reg fixer_flight_17; // @[FIFOFixer.scala:79:27] reg fixer_flight_18; // @[FIFOFixer.scala:79:27] reg fixer_flight_19; // @[FIFOFixer.scala:79:27] reg fixer_flight_20; // @[FIFOFixer.scala:79:27] reg fixer_flight_21; // @[FIFOFixer.scala:79:27] reg fixer_flight_22; // @[FIFOFixer.scala:79:27] reg fixer_flight_23; // @[FIFOFixer.scala:79:27] reg fixer_flight_24; // @[FIFOFixer.scala:79:27] reg fixer_flight_25; // @[FIFOFixer.scala:79:27] reg fixer_flight_26; // @[FIFOFixer.scala:79:27] reg fixer_flight_27; // @[FIFOFixer.scala:79:27] reg fixer_flight_28; // @[FIFOFixer.scala:79:27] reg fixer_flight_29; // @[FIFOFixer.scala:79:27] reg fixer_flight_30; // @[FIFOFixer.scala:79:27] reg fixer_flight_31; // @[FIFOFixer.scala:79:27] reg fixer_flight_32; // @[FIFOFixer.scala:79:27] reg fixer_flight_33; // @[FIFOFixer.scala:79:27] reg fixer_flight_34; // @[FIFOFixer.scala:79:27] reg fixer_flight_35; // @[FIFOFixer.scala:79:27] reg fixer_flight_36; // @[FIFOFixer.scala:79:27] reg fixer_flight_37; // @[FIFOFixer.scala:79:27] reg fixer_flight_38; // @[FIFOFixer.scala:79:27] reg fixer_flight_39; // @[FIFOFixer.scala:79:27] reg fixer_flight_40; // @[FIFOFixer.scala:79:27] reg fixer_flight_41; // @[FIFOFixer.scala:79:27] reg fixer_flight_42; // @[FIFOFixer.scala:79:27] reg fixer_flight_43; // @[FIFOFixer.scala:79:27] reg fixer_flight_44; // @[FIFOFixer.scala:79:27] reg fixer_flight_45; // @[FIFOFixer.scala:79:27] reg fixer_flight_46; // @[FIFOFixer.scala:79:27] reg fixer_flight_47; // @[FIFOFixer.scala:79:27] reg fixer_flight_48; // @[FIFOFixer.scala:79:27] reg fixer_flight_49; // @[FIFOFixer.scala:79:27] reg fixer_flight_50; // @[FIFOFixer.scala:79:27] reg fixer_flight_51; // @[FIFOFixer.scala:79:27] reg fixer_flight_52; // @[FIFOFixer.scala:79:27] reg fixer_flight_53; // @[FIFOFixer.scala:79:27] reg fixer_flight_54; // @[FIFOFixer.scala:79:27] reg fixer_flight_55; // @[FIFOFixer.scala:79:27] reg fixer_flight_56; // @[FIFOFixer.scala:79:27] reg fixer_flight_57; // @[FIFOFixer.scala:79:27] reg fixer_flight_58; // @[FIFOFixer.scala:79:27] reg fixer_flight_59; // @[FIFOFixer.scala:79:27] reg fixer_flight_60; // @[FIFOFixer.scala:79:27] reg fixer_flight_61; // @[FIFOFixer.scala:79:27] reg fixer_flight_62; // @[FIFOFixer.scala:79:27] reg fixer_flight_63; // @[FIFOFixer.scala:79:27] reg fixer_flight_64; // @[FIFOFixer.scala:79:27] reg fixer_flight_65; // @[FIFOFixer.scala:79:27] reg fixer_flight_66; // @[FIFOFixer.scala:79:27] reg fixer_flight_67; // @[FIFOFixer.scala:79:27] reg fixer_flight_68; // @[FIFOFixer.scala:79:27] reg fixer_flight_69; // @[FIFOFixer.scala:79:27] reg fixer_flight_70; // @[FIFOFixer.scala:79:27] reg fixer_flight_71; // @[FIFOFixer.scala:79:27] reg fixer_flight_72; // @[FIFOFixer.scala:79:27] reg fixer_flight_73; // @[FIFOFixer.scala:79:27] reg fixer_flight_74; // @[FIFOFixer.scala:79:27] reg fixer_flight_75; // @[FIFOFixer.scala:79:27] reg fixer_flight_76; // @[FIFOFixer.scala:79:27] reg fixer_flight_77; // @[FIFOFixer.scala:79:27] reg fixer_flight_78; // @[FIFOFixer.scala:79:27] reg fixer_flight_79; // @[FIFOFixer.scala:79:27] reg fixer_flight_80; // @[FIFOFixer.scala:79:27] reg fixer_flight_81; // @[FIFOFixer.scala:79:27] reg fixer_flight_82; // @[FIFOFixer.scala:79:27] reg fixer_flight_83; // @[FIFOFixer.scala:79:27] reg fixer_flight_84; // @[FIFOFixer.scala:79:27] reg fixer_flight_85; // @[FIFOFixer.scala:79:27] reg fixer_flight_86; // @[FIFOFixer.scala:79:27] reg fixer_flight_87; // @[FIFOFixer.scala:79:27] reg fixer_flight_88; // @[FIFOFixer.scala:79:27] reg fixer_flight_89; // @[FIFOFixer.scala:79:27] reg fixer_flight_90; // @[FIFOFixer.scala:79:27] reg fixer_flight_91; // @[FIFOFixer.scala:79:27] reg fixer_flight_92; // @[FIFOFixer.scala:79:27] reg fixer_flight_93; // @[FIFOFixer.scala:79:27] reg fixer_flight_94; // @[FIFOFixer.scala:79:27] reg fixer_flight_95; // @[FIFOFixer.scala:79:27] reg fixer_flight_96; // @[FIFOFixer.scala:79:27] reg fixer_flight_97; // @[FIFOFixer.scala:79:27] reg fixer_flight_98; // @[FIFOFixer.scala:79:27] reg fixer_flight_99; // @[FIFOFixer.scala:79:27] reg fixer_flight_100; // @[FIFOFixer.scala:79:27] reg fixer_flight_101; // @[FIFOFixer.scala:79:27] reg fixer_flight_102; // @[FIFOFixer.scala:79:27] reg fixer_flight_103; // @[FIFOFixer.scala:79:27] reg fixer_flight_104; // @[FIFOFixer.scala:79:27] reg fixer_flight_105; // @[FIFOFixer.scala:79:27] reg fixer_flight_106; // @[FIFOFixer.scala:79:27] reg fixer_flight_107; // @[FIFOFixer.scala:79:27] reg fixer_flight_108; // @[FIFOFixer.scala:79:27] reg fixer_flight_109; // @[FIFOFixer.scala:79:27] reg fixer_flight_110; // @[FIFOFixer.scala:79:27] reg fixer_flight_111; // @[FIFOFixer.scala:79:27] reg fixer_flight_112; // @[FIFOFixer.scala:79:27] reg fixer_flight_113; // @[FIFOFixer.scala:79:27] reg fixer_flight_114; // @[FIFOFixer.scala:79:27] reg fixer_flight_115; // @[FIFOFixer.scala:79:27] reg fixer_flight_116; // @[FIFOFixer.scala:79:27] reg fixer_flight_117; // @[FIFOFixer.scala:79:27] reg fixer_flight_118; // @[FIFOFixer.scala:79:27] reg fixer_flight_119; // @[FIFOFixer.scala:79:27] reg fixer_flight_120; // @[FIFOFixer.scala:79:27] reg fixer_flight_121; // @[FIFOFixer.scala:79:27] reg fixer_flight_122; // @[FIFOFixer.scala:79:27] reg fixer_flight_123; // @[FIFOFixer.scala:79:27] reg fixer_flight_124; // @[FIFOFixer.scala:79:27] reg fixer_flight_125; // @[FIFOFixer.scala:79:27] reg fixer_flight_126; // @[FIFOFixer.scala:79:27] reg fixer_flight_127; // @[FIFOFixer.scala:79:27] reg fixer_flight_128; // @[FIFOFixer.scala:79:27] reg fixer_flight_129; // @[FIFOFixer.scala:79:27] reg fixer_flight_130; // @[FIFOFixer.scala:79:27] reg fixer_flight_131; // @[FIFOFixer.scala:79:27] reg fixer_flight_132; // @[FIFOFixer.scala:79:27] reg fixer_flight_133; // @[FIFOFixer.scala:79:27] reg fixer_flight_134; // @[FIFOFixer.scala:79:27] reg fixer_flight_135; // @[FIFOFixer.scala:79:27] reg fixer_flight_136; // @[FIFOFixer.scala:79:27] reg fixer_flight_137; // @[FIFOFixer.scala:79:27] reg fixer_flight_138; // @[FIFOFixer.scala:79:27] reg fixer_flight_139; // @[FIFOFixer.scala:79:27] reg fixer_flight_140; // @[FIFOFixer.scala:79:27] reg fixer_flight_141; // @[FIFOFixer.scala:79:27] reg fixer_flight_142; // @[FIFOFixer.scala:79:27] reg fixer_flight_143; // @[FIFOFixer.scala:79:27] reg fixer_flight_144; // @[FIFOFixer.scala:79:27] reg fixer_flight_145; // @[FIFOFixer.scala:79:27] reg fixer_flight_146; // @[FIFOFixer.scala:79:27] reg fixer_flight_147; // @[FIFOFixer.scala:79:27] reg fixer_flight_148; // @[FIFOFixer.scala:79:27] reg fixer_flight_149; // @[FIFOFixer.scala:79:27] reg fixer_flight_150; // @[FIFOFixer.scala:79:27] reg fixer_flight_151; // @[FIFOFixer.scala:79:27] reg fixer_flight_152; // @[FIFOFixer.scala:79:27] reg fixer_flight_153; // @[FIFOFixer.scala:79:27] reg fixer_flight_154; // @[FIFOFixer.scala:79:27] reg fixer_flight_155; // @[FIFOFixer.scala:79:27] reg fixer_flight_156; // @[FIFOFixer.scala:79:27] reg fixer_flight_157; // @[FIFOFixer.scala:79:27] reg fixer_flight_158; // @[FIFOFixer.scala:79:27] reg fixer_flight_159; // @[FIFOFixer.scala:79:27] reg fixer_flight_160; // @[FIFOFixer.scala:79:27] reg fixer_flight_161; // @[FIFOFixer.scala:79:27] reg fixer_flight_162; // @[FIFOFixer.scala:79:27] reg fixer_flight_163; // @[FIFOFixer.scala:79:27] reg fixer_flight_164; // @[FIFOFixer.scala:79:27] reg fixer_flight_165; // @[FIFOFixer.scala:79:27] reg fixer_flight_166; // @[FIFOFixer.scala:79:27] reg fixer_flight_167; // @[FIFOFixer.scala:79:27] reg fixer_flight_168; // @[FIFOFixer.scala:79:27] reg fixer_flight_169; // @[FIFOFixer.scala:79:27] reg fixer_flight_170; // @[FIFOFixer.scala:79:27] reg fixer_flight_171; // @[FIFOFixer.scala:79:27] reg fixer_flight_172; // @[FIFOFixer.scala:79:27] reg fixer_flight_173; // @[FIFOFixer.scala:79:27] reg fixer_flight_174; // @[FIFOFixer.scala:79:27] reg fixer_flight_175; // @[FIFOFixer.scala:79:27] reg fixer_flight_176; // @[FIFOFixer.scala:79:27] reg fixer_flight_177; // @[FIFOFixer.scala:79:27] reg fixer_flight_178; // @[FIFOFixer.scala:79:27] reg fixer_flight_179; // @[FIFOFixer.scala:79:27] reg fixer_flight_180; // @[FIFOFixer.scala:79:27] reg fixer_flight_181; // @[FIFOFixer.scala:79:27] reg fixer_flight_182; // @[FIFOFixer.scala:79:27] reg fixer_flight_183; // @[FIFOFixer.scala:79:27] reg fixer_flight_184; // @[FIFOFixer.scala:79:27] reg fixer_flight_185; // @[FIFOFixer.scala:79:27] reg fixer_flight_186; // @[FIFOFixer.scala:79:27] reg fixer_flight_187; // @[FIFOFixer.scala:79:27] reg fixer_flight_188; // @[FIFOFixer.scala:79:27] reg fixer_flight_189; // @[FIFOFixer.scala:79:27] reg fixer_flight_190; // @[FIFOFixer.scala:79:27] reg fixer_flight_191; // @[FIFOFixer.scala:79:27] reg fixer_flight_192; // @[FIFOFixer.scala:79:27] reg fixer_flight_193; // @[FIFOFixer.scala:79:27] reg fixer_flight_194; // @[FIFOFixer.scala:79:27] reg fixer_flight_195; // @[FIFOFixer.scala:79:27] reg fixer_flight_196; // @[FIFOFixer.scala:79:27] reg fixer_flight_197; // @[FIFOFixer.scala:79:27] reg fixer_flight_198; // @[FIFOFixer.scala:79:27] reg fixer_flight_199; // @[FIFOFixer.scala:79:27] reg fixer_flight_200; // @[FIFOFixer.scala:79:27] reg fixer_flight_201; // @[FIFOFixer.scala:79:27] reg fixer_flight_202; // @[FIFOFixer.scala:79:27] reg fixer_flight_203; // @[FIFOFixer.scala:79:27] reg fixer_flight_204; // @[FIFOFixer.scala:79:27] reg fixer_flight_205; // @[FIFOFixer.scala:79:27] reg fixer_flight_206; // @[FIFOFixer.scala:79:27] reg fixer_flight_207; // @[FIFOFixer.scala:79:27] reg fixer_flight_208; // @[FIFOFixer.scala:79:27] reg fixer_flight_209; // @[FIFOFixer.scala:79:27] reg fixer_flight_210; // @[FIFOFixer.scala:79:27] reg fixer_flight_211; // @[FIFOFixer.scala:79:27] reg fixer_flight_212; // @[FIFOFixer.scala:79:27] reg fixer_flight_213; // @[FIFOFixer.scala:79:27] reg fixer_flight_214; // @[FIFOFixer.scala:79:27] reg fixer_flight_215; // @[FIFOFixer.scala:79:27] reg fixer_flight_216; // @[FIFOFixer.scala:79:27] reg fixer_flight_217; // @[FIFOFixer.scala:79:27] reg fixer_flight_218; // @[FIFOFixer.scala:79:27] reg fixer_flight_219; // @[FIFOFixer.scala:79:27] reg fixer_flight_220; // @[FIFOFixer.scala:79:27] reg fixer_flight_221; // @[FIFOFixer.scala:79:27] reg fixer_flight_222; // @[FIFOFixer.scala:79:27] reg fixer_flight_223; // @[FIFOFixer.scala:79:27] reg fixer_flight_224; // @[FIFOFixer.scala:79:27] reg fixer_flight_225; // @[FIFOFixer.scala:79:27] reg fixer_flight_226; // @[FIFOFixer.scala:79:27] reg fixer_flight_227; // @[FIFOFixer.scala:79:27] reg fixer_flight_228; // @[FIFOFixer.scala:79:27] reg fixer_flight_229; // @[FIFOFixer.scala:79:27] reg fixer_flight_230; // @[FIFOFixer.scala:79:27] reg fixer_flight_231; // @[FIFOFixer.scala:79:27] reg fixer_flight_232; // @[FIFOFixer.scala:79:27] reg fixer_flight_233; // @[FIFOFixer.scala:79:27] reg fixer_flight_234; // @[FIFOFixer.scala:79:27] reg fixer_flight_235; // @[FIFOFixer.scala:79:27] reg fixer_flight_236; // @[FIFOFixer.scala:79:27] reg fixer_flight_237; // @[FIFOFixer.scala:79:27] reg fixer_flight_238; // @[FIFOFixer.scala:79:27] reg fixer_flight_239; // @[FIFOFixer.scala:79:27] reg fixer_flight_240; // @[FIFOFixer.scala:79:27] reg fixer_flight_241; // @[FIFOFixer.scala:79:27] reg fixer_flight_242; // @[FIFOFixer.scala:79:27] reg fixer_flight_243; // @[FIFOFixer.scala:79:27] reg fixer_flight_244; // @[FIFOFixer.scala:79:27] reg fixer_flight_245; // @[FIFOFixer.scala:79:27] reg fixer_flight_246; // @[FIFOFixer.scala:79:27] reg fixer_flight_247; // @[FIFOFixer.scala:79:27] reg fixer_flight_248; // @[FIFOFixer.scala:79:27] reg fixer_flight_249; // @[FIFOFixer.scala:79:27] reg fixer_flight_250; // @[FIFOFixer.scala:79:27] reg fixer_flight_251; // @[FIFOFixer.scala:79:27] reg fixer_flight_252; // @[FIFOFixer.scala:79:27] reg fixer_flight_253; // @[FIFOFixer.scala:79:27] reg fixer_flight_254; // @[FIFOFixer.scala:79:27] reg fixer_flight_255; // @[FIFOFixer.scala:79:27] reg fixer_flight_256; // @[FIFOFixer.scala:79:27] reg fixer_flight_257; // @[FIFOFixer.scala:79:27] reg fixer_flight_258; // @[FIFOFixer.scala:79:27] reg fixer_flight_259; // @[FIFOFixer.scala:79:27] reg fixer_flight_260; // @[FIFOFixer.scala:79:27] reg fixer_flight_261; // @[FIFOFixer.scala:79:27] reg fixer_flight_262; // @[FIFOFixer.scala:79:27] reg fixer_flight_263; // @[FIFOFixer.scala:79:27] reg fixer_flight_264; // @[FIFOFixer.scala:79:27] reg fixer_flight_265; // @[FIFOFixer.scala:79:27] reg fixer_flight_266; // @[FIFOFixer.scala:79:27] reg fixer_flight_267; // @[FIFOFixer.scala:79:27] reg fixer_flight_268; // @[FIFOFixer.scala:79:27] reg fixer_flight_269; // @[FIFOFixer.scala:79:27] reg fixer_flight_270; // @[FIFOFixer.scala:79:27] reg fixer_flight_271; // @[FIFOFixer.scala:79:27] reg fixer_flight_272; // @[FIFOFixer.scala:79:27] reg fixer_flight_273; // @[FIFOFixer.scala:79:27] reg fixer_flight_274; // @[FIFOFixer.scala:79:27] reg fixer_flight_275; // @[FIFOFixer.scala:79:27] reg fixer_flight_276; // @[FIFOFixer.scala:79:27] reg fixer_flight_277; // @[FIFOFixer.scala:79:27] reg fixer_flight_278; // @[FIFOFixer.scala:79:27] reg fixer_flight_279; // @[FIFOFixer.scala:79:27] reg fixer_flight_280; // @[FIFOFixer.scala:79:27] reg fixer_flight_281; // @[FIFOFixer.scala:79:27] reg fixer_flight_282; // @[FIFOFixer.scala:79:27] reg fixer_flight_283; // @[FIFOFixer.scala:79:27] reg fixer_flight_284; // @[FIFOFixer.scala:79:27] reg fixer_flight_285; // @[FIFOFixer.scala:79:27] reg fixer_flight_286; // @[FIFOFixer.scala:79:27] reg fixer_flight_287; // @[FIFOFixer.scala:79:27] reg fixer_flight_288; // @[FIFOFixer.scala:79:27] reg fixer_flight_289; // @[FIFOFixer.scala:79:27] reg fixer_flight_290; // @[FIFOFixer.scala:79:27] reg fixer_flight_291; // @[FIFOFixer.scala:79:27] reg fixer_flight_292; // @[FIFOFixer.scala:79:27] reg fixer_flight_293; // @[FIFOFixer.scala:79:27] reg fixer_flight_294; // @[FIFOFixer.scala:79:27] reg fixer_flight_295; // @[FIFOFixer.scala:79:27] reg fixer_flight_296; // @[FIFOFixer.scala:79:27] reg fixer_flight_297; // @[FIFOFixer.scala:79:27] reg fixer_flight_298; // @[FIFOFixer.scala:79:27] reg fixer_flight_299; // @[FIFOFixer.scala:79:27] reg fixer_flight_300; // @[FIFOFixer.scala:79:27] reg fixer_flight_301; // @[FIFOFixer.scala:79:27] reg fixer_flight_302; // @[FIFOFixer.scala:79:27] reg fixer_flight_303; // @[FIFOFixer.scala:79:27] reg fixer_flight_304; // @[FIFOFixer.scala:79:27] reg fixer_flight_305; // @[FIFOFixer.scala:79:27] reg fixer_flight_306; // @[FIFOFixer.scala:79:27] reg fixer_flight_307; // @[FIFOFixer.scala:79:27] reg fixer_flight_308; // @[FIFOFixer.scala:79:27] reg fixer_flight_309; // @[FIFOFixer.scala:79:27] reg fixer_flight_310; // @[FIFOFixer.scala:79:27] reg fixer_flight_311; // @[FIFOFixer.scala:79:27] reg fixer_flight_312; // @[FIFOFixer.scala:79:27] reg fixer_flight_313; // @[FIFOFixer.scala:79:27] reg fixer_flight_314; // @[FIFOFixer.scala:79:27] reg fixer_flight_315; // @[FIFOFixer.scala:79:27] reg fixer_flight_316; // @[FIFOFixer.scala:79:27] reg fixer_flight_317; // @[FIFOFixer.scala:79:27] reg fixer_flight_318; // @[FIFOFixer.scala:79:27] reg fixer_flight_319; // @[FIFOFixer.scala:79:27] reg fixer_flight_320; // @[FIFOFixer.scala:79:27] reg fixer_flight_321; // @[FIFOFixer.scala:79:27] reg fixer_flight_322; // @[FIFOFixer.scala:79:27] reg fixer_flight_323; // @[FIFOFixer.scala:79:27] reg fixer_flight_324; // @[FIFOFixer.scala:79:27] reg fixer_flight_325; // @[FIFOFixer.scala:79:27] reg fixer_flight_326; // @[FIFOFixer.scala:79:27] reg fixer_flight_327; // @[FIFOFixer.scala:79:27] reg fixer_flight_328; // @[FIFOFixer.scala:79:27] reg fixer_flight_329; // @[FIFOFixer.scala:79:27] reg fixer_flight_330; // @[FIFOFixer.scala:79:27] reg fixer_flight_331; // @[FIFOFixer.scala:79:27] reg fixer_flight_332; // @[FIFOFixer.scala:79:27] reg fixer_flight_333; // @[FIFOFixer.scala:79:27] reg fixer_flight_334; // @[FIFOFixer.scala:79:27] reg fixer_flight_335; // @[FIFOFixer.scala:79:27] reg fixer_flight_336; // @[FIFOFixer.scala:79:27] reg fixer_flight_337; // @[FIFOFixer.scala:79:27] reg fixer_flight_338; // @[FIFOFixer.scala:79:27] reg fixer_flight_339; // @[FIFOFixer.scala:79:27] reg fixer_flight_340; // @[FIFOFixer.scala:79:27] reg fixer_flight_341; // @[FIFOFixer.scala:79:27] reg fixer_flight_342; // @[FIFOFixer.scala:79:27] reg fixer_flight_343; // @[FIFOFixer.scala:79:27] reg fixer_flight_344; // @[FIFOFixer.scala:79:27] reg fixer_flight_345; // @[FIFOFixer.scala:79:27] reg fixer_flight_346; // @[FIFOFixer.scala:79:27] reg fixer_flight_347; // @[FIFOFixer.scala:79:27] reg fixer_flight_348; // @[FIFOFixer.scala:79:27] reg fixer_flight_349; // @[FIFOFixer.scala:79:27] reg fixer_flight_350; // @[FIFOFixer.scala:79:27] reg fixer_flight_351; // @[FIFOFixer.scala:79:27] reg fixer_flight_352; // @[FIFOFixer.scala:79:27] reg fixer_flight_353; // @[FIFOFixer.scala:79:27] reg fixer_flight_354; // @[FIFOFixer.scala:79:27] reg fixer_flight_355; // @[FIFOFixer.scala:79:27] reg fixer_flight_356; // @[FIFOFixer.scala:79:27] reg fixer_flight_357; // @[FIFOFixer.scala:79:27] reg fixer_flight_358; // @[FIFOFixer.scala:79:27] reg fixer_flight_359; // @[FIFOFixer.scala:79:27] reg fixer_flight_360; // @[FIFOFixer.scala:79:27] reg fixer_flight_361; // @[FIFOFixer.scala:79:27] reg fixer_flight_362; // @[FIFOFixer.scala:79:27] reg fixer_flight_363; // @[FIFOFixer.scala:79:27] reg fixer_flight_364; // @[FIFOFixer.scala:79:27] reg fixer_flight_365; // @[FIFOFixer.scala:79:27] reg fixer_flight_366; // @[FIFOFixer.scala:79:27] reg fixer_flight_367; // @[FIFOFixer.scala:79:27] reg fixer_flight_368; // @[FIFOFixer.scala:79:27] reg fixer_flight_369; // @[FIFOFixer.scala:79:27] reg fixer_flight_370; // @[FIFOFixer.scala:79:27] reg fixer_flight_371; // @[FIFOFixer.scala:79:27] reg fixer_flight_372; // @[FIFOFixer.scala:79:27] reg fixer_flight_373; // @[FIFOFixer.scala:79:27] reg fixer_flight_374; // @[FIFOFixer.scala:79:27] reg fixer_flight_375; // @[FIFOFixer.scala:79:27] reg fixer_flight_376; // @[FIFOFixer.scala:79:27] reg fixer_flight_377; // @[FIFOFixer.scala:79:27] reg fixer_flight_378; // @[FIFOFixer.scala:79:27] reg fixer_flight_379; // @[FIFOFixer.scala:79:27] reg fixer_flight_380; // @[FIFOFixer.scala:79:27] reg fixer_flight_381; // @[FIFOFixer.scala:79:27] reg fixer_flight_382; // @[FIFOFixer.scala:79:27] reg fixer_flight_383; // @[FIFOFixer.scala:79:27] reg fixer_flight_384; // @[FIFOFixer.scala:79:27] reg fixer_flight_385; // @[FIFOFixer.scala:79:27] reg fixer_flight_386; // @[FIFOFixer.scala:79:27] reg fixer_flight_387; // @[FIFOFixer.scala:79:27] reg fixer_flight_388; // @[FIFOFixer.scala:79:27] reg fixer_flight_389; // @[FIFOFixer.scala:79:27] reg fixer_flight_390; // @[FIFOFixer.scala:79:27] reg fixer_flight_391; // @[FIFOFixer.scala:79:27] reg fixer_flight_392; // @[FIFOFixer.scala:79:27] reg fixer_flight_393; // @[FIFOFixer.scala:79:27] reg fixer_flight_394; // @[FIFOFixer.scala:79:27] reg fixer_flight_395; // @[FIFOFixer.scala:79:27] reg fixer_flight_396; // @[FIFOFixer.scala:79:27] reg fixer_flight_397; // @[FIFOFixer.scala:79:27] reg fixer_flight_398; // @[FIFOFixer.scala:79:27] reg fixer_flight_399; // @[FIFOFixer.scala:79:27] reg fixer_flight_400; // @[FIFOFixer.scala:79:27] reg fixer_flight_401; // @[FIFOFixer.scala:79:27] reg fixer_flight_402; // @[FIFOFixer.scala:79:27] reg fixer_flight_403; // @[FIFOFixer.scala:79:27] reg fixer_flight_404; // @[FIFOFixer.scala:79:27] reg fixer_flight_405; // @[FIFOFixer.scala:79:27] reg fixer_flight_406; // @[FIFOFixer.scala:79:27] reg fixer_flight_407; // @[FIFOFixer.scala:79:27] reg fixer_flight_408; // @[FIFOFixer.scala:79:27] reg fixer_flight_409; // @[FIFOFixer.scala:79:27] reg fixer_flight_410; // @[FIFOFixer.scala:79:27] reg fixer_flight_411; // @[FIFOFixer.scala:79:27] reg fixer_flight_412; // @[FIFOFixer.scala:79:27] reg fixer_flight_413; // @[FIFOFixer.scala:79:27] reg fixer_flight_414; // @[FIFOFixer.scala:79:27] reg fixer_flight_415; // @[FIFOFixer.scala:79:27] reg fixer_flight_416; // @[FIFOFixer.scala:79:27] reg fixer_flight_417; // @[FIFOFixer.scala:79:27] reg fixer_flight_418; // @[FIFOFixer.scala:79:27] reg fixer_flight_419; // @[FIFOFixer.scala:79:27] reg fixer_flight_420; // @[FIFOFixer.scala:79:27] reg fixer_flight_421; // @[FIFOFixer.scala:79:27] reg fixer_flight_422; // @[FIFOFixer.scala:79:27] reg fixer_flight_423; // @[FIFOFixer.scala:79:27] reg fixer_flight_424; // @[FIFOFixer.scala:79:27] reg fixer_flight_425; // @[FIFOFixer.scala:79:27] reg fixer_flight_426; // @[FIFOFixer.scala:79:27] reg fixer_flight_427; // @[FIFOFixer.scala:79:27] reg fixer_flight_428; // @[FIFOFixer.scala:79:27] reg fixer_flight_429; // @[FIFOFixer.scala:79:27] reg fixer_flight_430; // @[FIFOFixer.scala:79:27] reg fixer_flight_431; // @[FIFOFixer.scala:79:27] reg fixer_flight_432; // @[FIFOFixer.scala:79:27] reg fixer_flight_433; // @[FIFOFixer.scala:79:27] reg fixer_flight_434; // @[FIFOFixer.scala:79:27] reg fixer_flight_435; // @[FIFOFixer.scala:79:27] reg fixer_flight_436; // @[FIFOFixer.scala:79:27] reg fixer_flight_437; // @[FIFOFixer.scala:79:27] reg fixer_flight_438; // @[FIFOFixer.scala:79:27] reg fixer_flight_439; // @[FIFOFixer.scala:79:27] reg fixer_flight_440; // @[FIFOFixer.scala:79:27] reg fixer_flight_441; // @[FIFOFixer.scala:79:27] reg fixer_flight_442; // @[FIFOFixer.scala:79:27] reg fixer_flight_443; // @[FIFOFixer.scala:79:27] reg fixer_flight_444; // @[FIFOFixer.scala:79:27] reg fixer_flight_445; // @[FIFOFixer.scala:79:27] reg fixer_flight_446; // @[FIFOFixer.scala:79:27] reg fixer_flight_447; // @[FIFOFixer.scala:79:27] reg fixer_flight_448; // @[FIFOFixer.scala:79:27] reg fixer_flight_449; // @[FIFOFixer.scala:79:27] reg fixer_flight_450; // @[FIFOFixer.scala:79:27] reg fixer_flight_451; // @[FIFOFixer.scala:79:27] reg fixer_flight_452; // @[FIFOFixer.scala:79:27] reg fixer_flight_453; // @[FIFOFixer.scala:79:27] reg fixer_flight_454; // @[FIFOFixer.scala:79:27] reg fixer_flight_455; // @[FIFOFixer.scala:79:27] reg fixer_flight_456; // @[FIFOFixer.scala:79:27] reg fixer_flight_457; // @[FIFOFixer.scala:79:27] reg fixer_flight_458; // @[FIFOFixer.scala:79:27] reg fixer_flight_459; // @[FIFOFixer.scala:79:27] reg fixer_flight_460; // @[FIFOFixer.scala:79:27] reg fixer_flight_461; // @[FIFOFixer.scala:79:27] reg fixer_flight_462; // @[FIFOFixer.scala:79:27] reg fixer_flight_463; // @[FIFOFixer.scala:79:27] reg fixer_flight_464; // @[FIFOFixer.scala:79:27] reg fixer_flight_465; // @[FIFOFixer.scala:79:27] reg fixer_flight_466; // @[FIFOFixer.scala:79:27] reg fixer_flight_467; // @[FIFOFixer.scala:79:27] reg fixer_flight_468; // @[FIFOFixer.scala:79:27] reg fixer_flight_469; // @[FIFOFixer.scala:79:27] reg fixer_flight_470; // @[FIFOFixer.scala:79:27] reg fixer_flight_471; // @[FIFOFixer.scala:79:27] reg fixer_flight_472; // @[FIFOFixer.scala:79:27] reg fixer_flight_473; // @[FIFOFixer.scala:79:27] reg fixer_flight_474; // @[FIFOFixer.scala:79:27] reg fixer_flight_475; // @[FIFOFixer.scala:79:27] reg fixer_flight_476; // @[FIFOFixer.scala:79:27] reg fixer_flight_477; // @[FIFOFixer.scala:79:27] reg fixer_flight_478; // @[FIFOFixer.scala:79:27] reg fixer_flight_479; // @[FIFOFixer.scala:79:27] reg fixer_flight_480; // @[FIFOFixer.scala:79:27] reg fixer_flight_481; // @[FIFOFixer.scala:79:27] reg fixer_flight_482; // @[FIFOFixer.scala:79:27] reg fixer_flight_483; // @[FIFOFixer.scala:79:27] reg fixer_flight_484; // @[FIFOFixer.scala:79:27] reg fixer_flight_485; // @[FIFOFixer.scala:79:27] reg fixer_flight_486; // @[FIFOFixer.scala:79:27] reg fixer_flight_487; // @[FIFOFixer.scala:79:27] reg fixer_flight_488; // @[FIFOFixer.scala:79:27] reg fixer_flight_489; // @[FIFOFixer.scala:79:27] reg fixer_flight_490; // @[FIFOFixer.scala:79:27] reg fixer_flight_491; // @[FIFOFixer.scala:79:27] reg fixer_flight_492; // @[FIFOFixer.scala:79:27] reg fixer_flight_493; // @[FIFOFixer.scala:79:27] reg fixer_flight_494; // @[FIFOFixer.scala:79:27] reg fixer_flight_495; // @[FIFOFixer.scala:79:27] reg fixer_flight_496; // @[FIFOFixer.scala:79:27] reg fixer_flight_497; // @[FIFOFixer.scala:79:27] reg fixer_flight_498; // @[FIFOFixer.scala:79:27] reg fixer_flight_499; // @[FIFOFixer.scala:79:27] reg fixer_flight_500; // @[FIFOFixer.scala:79:27] reg fixer_flight_501; // @[FIFOFixer.scala:79:27] reg fixer_flight_502; // @[FIFOFixer.scala:79:27] reg fixer_flight_503; // @[FIFOFixer.scala:79:27] reg fixer_flight_504; // @[FIFOFixer.scala:79:27] reg fixer_flight_505; // @[FIFOFixer.scala:79:27] reg fixer_flight_506; // @[FIFOFixer.scala:79:27] reg fixer_flight_507; // @[FIFOFixer.scala:79:27] reg fixer_flight_508; // @[FIFOFixer.scala:79:27] reg fixer_flight_509; // @[FIFOFixer.scala:79:27] reg fixer_flight_510; // @[FIFOFixer.scala:79:27] reg fixer_flight_511; // @[FIFOFixer.scala:79:27] reg fixer_flight_512; // @[FIFOFixer.scala:79:27] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [512:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [512:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [512:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [1023:0] fixer__SourceIdSet_T = 1024'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire [1023:0] fixer__SourceIdClear_T = 1024'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire [512:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed \| fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire in_xbar_anonIn_a_ready; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_a_valid = in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_opcode = in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_param = in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonIn_a_bits_size = in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] in_xbar_anonIn_a_bits_source = in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_anonIn_a_bits_address = in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_anonIn_a_bits_mask = in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_anonIn_a_bits_data = in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_anonIn_a_bits_corrupt = in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_ready = in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire in_xbar_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] in_xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] in_xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] in_xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [9:0] in_xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] in_xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire in_xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire in_xbar_anonOut_a_ready = in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire in_xbar_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] in_xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [9:0] in_xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] in_xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] in_xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] in_xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_d_ready; // @[MixedNode.scala:542:17] wire in_xbar_anonOut_d_valid = in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonOut_d_bits_opcode = in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_anonOut_d_bits_param = in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_anonOut_d_bits_size = in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] in_xbar_anonOut_d_bits_source = in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_sink = in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_denied = in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_anonOut_d_bits_data = in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_anonOut_d_bits_corrupt = in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] in_xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] in_xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9] wire in_xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9] wire in_xbar_out_0_a_ready = in_xbar_anonOut_a_ready; // @[Xbar.scala:216:19] wire in_xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_valid = in_xbar_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_opcode = in_xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_param = in_xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_size = in_xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [9:0] in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_source = in_xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [28:0] in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_address = in_xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_mask = in_xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_data = in_xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_a_bits_corrupt = in_xbar_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_out_0_d_ready; // @[Xbar.scala:216:19] assign in_xbar_auto_anon_out_d_ready = in_xbar_anonOut_d_ready; // @[Xbar.scala:74:9] wire in_xbar_out_0_d_valid = in_xbar_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] in_xbar_out_0_d_bits_opcode = in_xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] in_xbar_out_0_d_bits_param = in_xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] in_xbar_out_0_d_bits_size = in_xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [9:0] in_xbar_out_0_d_bits_source = in_xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire in_xbar__out_0_d_bits_sink_T = in_xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire in_xbar_out_0_d_bits_denied = in_xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] in_xbar_out_0_d_bits_data = in_xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire in_xbar_out_0_d_bits_corrupt = in_xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire in_xbar_in_0_a_ready; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_a_ready = in_xbar_anonIn_a_ready; // @[Xbar.scala:74:9] wire in_xbar_in_0_a_valid = in_xbar_anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_opcode = in_xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_param = in_xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_xbar_in_0_a_bits_size = in_xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [9:0] in_xbar__in_0_a_bits_source_T = in_xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [28:0] in_xbar_in_0_a_bits_address = in_xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_xbar_in_0_a_bits_mask = in_xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_xbar_in_0_a_bits_data = in_xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_xbar_in_0_a_bits_corrupt = in_xbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_xbar_in_0_d_ready = in_xbar_anonIn_d_ready; // @[Xbar.scala:159:18] wire in_xbar_in_0_d_valid; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_valid = in_xbar_anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_opcode = in_xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_param = in_xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_size = in_xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [9:0] in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign in_xbar_auto_anon_in_d_bits_source = in_xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_sink = in_xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_denied = in_xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_data = in_xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_xbar_auto_anon_in_d_bits_corrupt = in_xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign in_xbar_anonIn_a_ready = in_xbar_in_0_a_ready; // @[Xbar.scala:159:18] wire in_xbar__portsAOI_filtered_0_valid_T_1 = in_xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] in_xbar_portsAOI_filtered_0_bits_opcode = in_xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] in_xbar_portsAOI_filtered_0_bits_param = in_xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] in_xbar_portsAOI_filtered_0_bits_size = in_xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [9:0] in_xbar_portsAOI_filtered_0_bits_source = in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [28:0] in_xbar__requestAIO_T = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18] wire [28:0] in_xbar_portsAOI_filtered_0_bits_address = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] in_xbar_portsAOI_filtered_0_bits_mask = in_xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] in_xbar_portsAOI_filtered_0_bits_data = in_xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsAOI_filtered_0_bits_corrupt = in_xbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsDIO_filtered_0_ready = in_xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_valid = in_xbar_in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_opcode = in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_param = in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_size = in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] wire [9:0] in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign in_xbar__anonIn_d_bits_source_T = in_xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_sink = in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] wire in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_denied = in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_data = in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] wire in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign in_xbar_anonIn_d_bits_corrupt = in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_xbar_in_0_a_bits_source = in_xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign in_xbar_anonIn_d_bits_source = in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign in_xbar_portsAOI_filtered_0_ready = in_xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign in_xbar_anonOut_a_valid = in_xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_opcode = in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_param = in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_size = in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_source = in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_address = in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_mask = in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_data = in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign in_xbar_anonOut_a_bits_corrupt = in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign in_xbar_anonOut_d_ready = in_xbar_out_0_d_ready; // @[Xbar.scala:216:19] wire in_xbar__portsDIO_filtered_0_valid_T_1 = in_xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40] assign in_xbar_portsDIO_filtered_0_bits_opcode = in_xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_param = in_xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_size = in_xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [9:0] in_xbar__requestDOI_uncommonBits_T = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19] assign in_xbar_portsDIO_filtered_0_bits_source = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_sink = in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_denied = in_xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_data = in_xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsDIO_filtered_0_bits_corrupt = in_xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_d_bits_sink = in_xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [29:0] in_xbar__requestAIO_T_1 = {1'h0, in_xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [9:0] in_xbar_requestDOI_uncommonBits = in_xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] in_xbar__beatsAI_decode_T = 13'h3F << in_xbar_in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] in_xbar__beatsAI_decode_T_1 = in_xbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] in_xbar__beatsAI_decode_T_2 = ~in_xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] in_xbar_beatsAI_decode = in_xbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire in_xbar__beatsAI_opdata_T = in_xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire in_xbar_beatsAI_opdata = ~in_xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] in_xbar_beatsAI_0 = in_xbar_beatsAI_opdata ? in_xbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] in_xbar__beatsDO_decode_T = 13'h3F << in_xbar_out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] in_xbar__beatsDO_decode_T_1 = in_xbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] in_xbar__beatsDO_decode_T_2 = ~in_xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] in_xbar_beatsDO_decode = in_xbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire in_xbar_beatsDO_opdata = in_xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] in_xbar_beatsDO_0 = in_xbar_beatsDO_opdata ? in_xbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] assign in_xbar_in_0_a_ready = in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign in_xbar_out_0_a_valid = in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_opcode = in_xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_param = in_xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_size = in_xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_source = in_xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_address = in_xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_mask = in_xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_data = in_xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign in_xbar_out_0_a_bits_corrupt = in_xbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign in_xbar_portsAOI_filtered_0_valid = in_xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign in_xbar_out_0_d_ready = in_xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign in_xbar_in_0_d_valid = in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_opcode = in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_param = in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_size = in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_source = in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_sink = in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_denied = in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_data = in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_xbar_in_0_d_bits_corrupt = in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign in_xbar_portsDIO_filtered_0_valid = in_xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [9:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire in_ready; // @[RegisterRouter.scala:73:18] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [13:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] wire [13:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param; // @[MixedNode.scala:551:17] wire [12:0] nodeIn_a_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [13:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] reg [63:0] bootAddrReg; // @[BootAddrReg.scala:27:34] wire [63:0] pad = bootAddrReg; // @[BootAddrReg.scala:27:34] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_7 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready; // @[RegisterRouter.scala:87:24] wire out_f_woready_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] bootAddrReg_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] bootAddrReg_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] bootAddrReg_lo = {bootAddrReg_lo_hi, bootAddrReg_lo_lo}; // @[RegField.scala:154:52] wire [15:0] bootAddrReg_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] bootAddrReg_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] bootAddrReg_hi = {bootAddrReg_hi_hi, bootAddrReg_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _bootAddrReg_T = {bootAddrReg_hi, bootAddrReg_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [13:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [9:0] _in_bits_index_T = nodeIn_a_bits_address[12:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = \|_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = \|_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready ? _out_T_2 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8 = _out_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = _out_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] assign out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_1 ? _out_T_9 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend = {oldBytes_1, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_14 = out_prepend; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_15 = _out_T_14; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = _out_T_15; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = \|_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = \|_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_16 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_2 ? _out_T_16 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1 = {oldBytes_2, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_21 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_22 = _out_T_21; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = _out_T_22; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_23 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_3 ? _out_T_23 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_24 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_25 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_26 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_2 = {oldBytes_3, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_28 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_29 = _out_T_28; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_3 = _out_T_29; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_30 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_4 ? _out_T_30 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_3 = {oldBytes_4, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_35 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_4 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = \|_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = \|_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_5 ? _out_T_37 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_4 = {oldBytes_5, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_42 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_5 = _out_T_43; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = \|_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = \|_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_44 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_6 ? _out_T_44 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_46 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_5 = {oldBytes_6, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_49 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_50 = _out_T_49; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_6 = _out_T_50; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = \|_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = \|_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_51 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_7 ? _out_T_51 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_52 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_6 = {oldBytes_7, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_56 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_57 = _out_T_56; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_57; // @[MuxLiteral.scala:49:48] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31] fixer_a_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 3'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_65 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_66 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_67 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_68 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_69 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_70 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_71 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_72 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_73 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_74 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_75 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_76 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_77 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_78 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_79 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_80 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_81 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_82 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_83 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_84 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_85 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_86 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_87 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_88 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_89 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_90 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_91 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_92 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_93 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_94 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_95 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_96 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_97 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_98 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_99 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_100 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_101 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_102 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_103 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_104 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_105 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_106 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_107 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_108 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_109 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_110 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_111 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_112 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_113 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_114 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_115 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_116 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_117 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_118 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_119 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_120 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_121 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_122 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_123 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_124 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_125 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_126 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_127 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_128 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_129 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_130 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_131 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_132 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_133 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_134 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_135 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_136 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_137 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_138 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_139 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_140 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_141 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_142 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_143 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_144 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_145 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_146 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_147 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_148 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_149 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_150 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_151 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_152 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_153 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_154 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_155 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_156 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_157 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_158 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_159 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_160 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_161 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_162 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_163 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_164 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_165 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_166 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_167 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_168 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_169 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_170 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_171 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_172 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_173 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_174 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_175 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_176 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_177 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_178 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_179 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_180 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_181 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_182 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_183 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_184 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_185 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_186 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_187 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_188 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_189 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_190 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_191 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_192 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_193 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_194 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_195 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_196 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_197 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_198 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_199 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_200 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_201 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_202 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_203 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_204 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_205 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_206 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_207 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_208 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_209 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_210 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_211 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_212 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_213 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_214 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_215 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_216 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_217 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_218 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_219 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_220 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_221 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_222 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_223 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_224 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_225 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_226 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_227 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_228 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_229 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_230 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_231 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_232 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_233 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_234 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_235 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_236 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_237 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_238 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_239 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_240 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_241 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_242 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_243 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_244 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_245 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_246 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_247 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_248 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_249 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_250 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_251 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_252 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_253 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_254 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_255 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_256 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_257 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_258 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_259 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_260 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_261 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_262 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_263 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_264 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_265 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_266 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_267 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_268 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_269 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_270 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_271 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_272 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_273 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_274 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_275 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_276 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_277 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_278 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_279 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_280 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_281 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_282 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_283 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_284 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_285 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_286 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_287 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_288 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_289 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_290 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_291 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_292 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_293 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_294 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_295 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_296 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_297 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_298 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_299 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_300 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_301 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_302 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_303 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_304 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_305 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_306 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_307 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_308 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_309 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_310 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_311 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_312 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_313 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_314 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_315 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_316 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_317 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_318 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_319 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_320 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_321 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_322 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_323 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_324 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_325 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_326 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_327 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_328 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_329 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_330 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_331 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_332 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_333 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_334 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_335 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_336 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_337 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_338 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_339 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_340 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_341 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_342 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_343 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_344 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_345 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_346 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_347 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_348 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_349 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_350 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_351 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_352 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_353 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_354 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_355 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_356 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_357 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_358 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_359 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_360 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_361 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_362 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_363 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_364 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_365 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_366 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_367 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_368 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_369 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_370 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_371 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_372 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_373 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_374 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_375 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_376 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_377 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_378 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_379 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_380 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_381 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_382 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_383 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_384 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_385 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_386 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_387 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_388 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_389 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_390 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_391 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_392 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_393 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_394 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_395 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_396 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_397 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_398 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_399 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_400 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_401 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_402 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_403 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_404 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_405 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_406 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_407 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_408 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_409 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_410 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_411 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_412 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_413 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_414 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_415 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_416 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_417 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_418 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_419 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_420 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_421 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_422 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_423 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_424 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_425 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_426 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_427 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_428 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_429 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_430 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_431 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_432 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_433 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_434 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_435 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_436 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_437 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_438 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_439 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_440 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_441 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_442 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_443 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_444 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_445 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_446 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_447 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_448 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_449 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_450 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_451 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_452 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_453 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_454 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_455 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_456 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_457 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_458 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_459 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_460 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_461 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_462 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_463 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_464 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_465 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_466 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_467 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_468 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_469 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_470 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_471 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_472 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_473 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_474 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_475 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_476 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_477 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_478 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_479 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_480 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_481 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_482 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_483 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_484 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_485 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_486 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_487 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_488 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_489 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_490 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_491 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_492 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_493 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_494 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_495 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_496 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_497 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_498 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_499 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_500 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_501 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_502 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_503 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_504 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_505 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_506 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_507 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_508 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_509 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_510 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_511 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_512 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 513'h0; // @[FIFOFixer.scala:115:35] bootAddrReg <= 64'h80000000; // @[BootAddrReg.scala:27:34] end else begin // @[LazyModuleImp.scala:155:31] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h0 \| fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1 \| fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h2 \| fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h3 \| fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h4 \| fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h5 \| fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h6 \| fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h7 \| fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h8 \| fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h9 \| fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hA \| fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hB \| fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hC \| fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hD \| fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hE \| fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hF \| fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h10 \| fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_17 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h11) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h11 \| fixer_flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_18 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h12) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h12 \| fixer_flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_19 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h13) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h13 \| fixer_flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_20 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h14) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h14 \| fixer_flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_21 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h15) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h15 \| fixer_flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_22 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h16) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h16 \| fixer_flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_23 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h17) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h17 \| fixer_flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_24 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h18) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h18 \| fixer_flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_25 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h19) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h19 \| fixer_flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_26 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1A \| fixer_flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_27 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1B \| fixer_flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_28 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1C \| fixer_flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_29 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1D \| fixer_flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_30 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1E \| fixer_flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_31 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1F \| fixer_flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_32 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h20) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h20 \| fixer_flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_33 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h21) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h21 \| fixer_flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_34 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h22) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h22 \| fixer_flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_35 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h23) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h23 \| fixer_flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_36 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h24) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h24 \| fixer_flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_37 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h25) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h25 \| fixer_flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_38 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h26) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h26 \| fixer_flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_39 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h27) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h27 \| fixer_flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_40 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h28) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h28 \| fixer_flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_41 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h29) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h29 \| fixer_flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_42 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h2A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h2A \| fixer_flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_43 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h2B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h2B \| fixer_flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_44 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h2C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h2C \| fixer_flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_45 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h2D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h2D \| fixer_flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_46 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h2E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h2E \| fixer_flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_47 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h2F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h2F \| fixer_flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_48 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h30) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h30 \| fixer_flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_49 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h31) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h31 \| fixer_flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_50 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h32) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h32 \| fixer_flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_51 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h33) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h33 \| fixer_flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_52 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h34) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h34 \| fixer_flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_53 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h35) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h35 \| fixer_flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_54 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h36) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h36 \| fixer_flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_55 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h37) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h37 \| fixer_flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_56 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h38) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h38 \| fixer_flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_57 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h39) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h39 \| fixer_flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_58 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h3A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h3A \| fixer_flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_59 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h3B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h3B \| fixer_flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_60 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h3C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h3C \| fixer_flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_61 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h3D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h3D \| fixer_flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_62 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h3E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h3E \| fixer_flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_63 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h3F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h3F \| fixer_flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_64 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h40) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h40 \| fixer_flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_65 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h41) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h41 \| fixer_flight_65); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_66 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h42) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h42 \| fixer_flight_66); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_67 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h43) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h43 \| fixer_flight_67); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_68 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h44) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h44 \| fixer_flight_68); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_69 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h45) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h45 \| fixer_flight_69); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_70 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h46) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h46 \| fixer_flight_70); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_71 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h47) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h47 \| fixer_flight_71); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_72 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h48) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h48 \| fixer_flight_72); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_73 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h49) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h49 \| fixer_flight_73); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_74 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h4A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h4A \| fixer_flight_74); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_75 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h4B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h4B \| fixer_flight_75); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_76 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h4C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h4C \| fixer_flight_76); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_77 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h4D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h4D \| fixer_flight_77); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_78 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h4E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h4E \| fixer_flight_78); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_79 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h4F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h4F \| fixer_flight_79); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_80 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h50) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h50 \| fixer_flight_80); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_81 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h51) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h51 \| fixer_flight_81); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_82 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h52) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h52 \| fixer_flight_82); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_83 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h53) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h53 \| fixer_flight_83); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_84 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h54) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h54 \| fixer_flight_84); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_85 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h55) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h55 \| fixer_flight_85); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_86 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h56) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h56 \| fixer_flight_86); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_87 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h57) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h57 \| fixer_flight_87); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_88 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h58) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h58 \| fixer_flight_88); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_89 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h59) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h59 \| fixer_flight_89); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_90 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h5A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h5A \| fixer_flight_90); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_91 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h5B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h5B \| fixer_flight_91); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_92 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h5C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h5C \| fixer_flight_92); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_93 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h5D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h5D \| fixer_flight_93); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_94 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h5E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h5E \| fixer_flight_94); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_95 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h5F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h5F \| fixer_flight_95); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_96 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h60) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h60 \| fixer_flight_96); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_97 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h61) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h61 \| fixer_flight_97); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_98 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h62) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h62 \| fixer_flight_98); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_99 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h63) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h63 \| fixer_flight_99); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_100 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h64) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h64 \| fixer_flight_100); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_101 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h65) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h65 \| fixer_flight_101); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_102 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h66) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h66 \| fixer_flight_102); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_103 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h67) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h67 \| fixer_flight_103); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_104 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h68) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h68 \| fixer_flight_104); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_105 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h69) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h69 \| fixer_flight_105); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_106 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h6A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h6A \| fixer_flight_106); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_107 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h6B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h6B \| fixer_flight_107); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_108 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h6C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h6C \| fixer_flight_108); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_109 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h6D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h6D \| fixer_flight_109); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_110 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h6E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h6E \| fixer_flight_110); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_111 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h6F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h6F \| fixer_flight_111); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_112 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h70) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h70 \| fixer_flight_112); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_113 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h71) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h71 \| fixer_flight_113); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_114 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h72) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h72 \| fixer_flight_114); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_115 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h73) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h73 \| fixer_flight_115); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_116 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h74) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h74 \| fixer_flight_116); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_117 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h75) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h75 \| fixer_flight_117); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_118 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h76) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h76 \| fixer_flight_118); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_119 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h77) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h77 \| fixer_flight_119); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_120 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h78) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h78 \| fixer_flight_120); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_121 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h79) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h79 \| fixer_flight_121); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_122 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h7A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h7A \| fixer_flight_122); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_123 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h7B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h7B \| fixer_flight_123); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_124 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h7C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h7C \| fixer_flight_124); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_125 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h7D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h7D \| fixer_flight_125); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_126 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h7E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h7E \| fixer_flight_126); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_127 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h7F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h7F \| fixer_flight_127); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_128 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h80) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h80 \| fixer_flight_128); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_129 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h81) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h81 \| fixer_flight_129); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_130 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h82) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h82 \| fixer_flight_130); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_131 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h83) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h83 \| fixer_flight_131); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_132 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h84) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h84 \| fixer_flight_132); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_133 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h85) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h85 \| fixer_flight_133); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_134 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h86) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h86 \| fixer_flight_134); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_135 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h87) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h87 \| fixer_flight_135); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_136 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h88) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h88 \| fixer_flight_136); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_137 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h89) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h89 \| fixer_flight_137); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_138 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h8A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h8A \| fixer_flight_138); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_139 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h8B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h8B \| fixer_flight_139); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_140 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h8C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h8C \| fixer_flight_140); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_141 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h8D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h8D \| fixer_flight_141); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_142 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h8E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h8E \| fixer_flight_142); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_143 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h8F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h8F \| fixer_flight_143); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_144 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h90) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h90 \| fixer_flight_144); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_145 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h91) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h91 \| fixer_flight_145); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_146 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h92) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h92 \| fixer_flight_146); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_147 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h93) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h93 \| fixer_flight_147); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_148 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h94) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h94 \| fixer_flight_148); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_149 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h95) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h95 \| fixer_flight_149); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_150 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h96) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h96 \| fixer_flight_150); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_151 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h97) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h97 \| fixer_flight_151); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_152 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h98) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h98 \| fixer_flight_152); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_153 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h99) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h99 \| fixer_flight_153); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_154 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h9A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h9A \| fixer_flight_154); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_155 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h9B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h9B \| fixer_flight_155); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_156 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h9C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h9C \| fixer_flight_156); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_157 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h9D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h9D \| fixer_flight_157); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_158 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h9E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h9E \| fixer_flight_158); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_159 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h9F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h9F \| fixer_flight_159); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_160 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hA0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hA0 \| fixer_flight_160); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_161 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hA1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hA1 \| fixer_flight_161); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_162 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hA2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hA2 \| fixer_flight_162); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_163 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hA3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hA3 \| fixer_flight_163); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_164 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hA4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hA4 \| fixer_flight_164); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_165 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hA5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hA5 \| fixer_flight_165); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_166 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hA6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hA6 \| fixer_flight_166); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_167 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hA7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hA7 \| fixer_flight_167); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_168 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hA8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hA8 \| fixer_flight_168); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_169 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hA9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hA9 \| fixer_flight_169); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_170 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hAA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hAA \| fixer_flight_170); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_171 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hAB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hAB \| fixer_flight_171); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_172 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hAC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hAC \| fixer_flight_172); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_173 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hAD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hAD \| fixer_flight_173); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_174 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hAE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hAE \| fixer_flight_174); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_175 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hAF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hAF \| fixer_flight_175); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_176 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hB0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hB0 \| fixer_flight_176); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_177 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hB1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hB1 \| fixer_flight_177); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_178 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hB2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hB2 \| fixer_flight_178); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_179 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hB3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hB3 \| fixer_flight_179); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_180 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hB4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hB4 \| fixer_flight_180); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_181 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hB5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hB5 \| fixer_flight_181); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_182 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hB6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hB6 \| fixer_flight_182); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_183 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hB7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hB7 \| fixer_flight_183); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_184 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hB8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hB8 \| fixer_flight_184); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_185 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hB9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hB9 \| fixer_flight_185); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_186 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hBA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hBA \| fixer_flight_186); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_187 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hBB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hBB \| fixer_flight_187); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_188 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hBC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hBC \| fixer_flight_188); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_189 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hBD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hBD \| fixer_flight_189); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_190 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hBE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hBE \| fixer_flight_190); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_191 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hBF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hBF \| fixer_flight_191); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_192 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hC0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hC0 \| fixer_flight_192); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_193 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hC1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hC1 \| fixer_flight_193); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_194 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hC2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hC2 \| fixer_flight_194); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_195 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hC3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hC3 \| fixer_flight_195); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_196 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hC4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hC4 \| fixer_flight_196); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_197 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hC5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hC5 \| fixer_flight_197); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_198 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hC6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hC6 \| fixer_flight_198); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_199 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hC7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hC7 \| fixer_flight_199); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_200 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hC8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hC8 \| fixer_flight_200); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_201 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hC9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hC9 \| fixer_flight_201); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_202 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hCA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hCA \| fixer_flight_202); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_203 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hCB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hCB \| fixer_flight_203); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_204 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hCC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hCC \| fixer_flight_204); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_205 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hCD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hCD \| fixer_flight_205); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_206 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hCE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hCE \| fixer_flight_206); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_207 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hCF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hCF \| fixer_flight_207); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_208 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hD0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hD0 \| fixer_flight_208); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_209 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hD1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hD1 \| fixer_flight_209); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_210 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hD2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hD2 \| fixer_flight_210); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_211 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hD3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hD3 \| fixer_flight_211); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_212 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hD4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hD4 \| fixer_flight_212); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_213 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hD5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hD5 \| fixer_flight_213); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_214 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hD6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hD6 \| fixer_flight_214); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_215 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hD7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hD7 \| fixer_flight_215); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_216 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hD8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hD8 \| fixer_flight_216); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_217 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hD9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hD9 \| fixer_flight_217); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_218 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hDA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hDA \| fixer_flight_218); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_219 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hDB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hDB \| fixer_flight_219); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_220 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hDC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hDC \| fixer_flight_220); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_221 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hDD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hDD \| fixer_flight_221); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_222 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hDE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hDE \| fixer_flight_222); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_223 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hDF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hDF \| fixer_flight_223); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_224 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hE0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hE0 \| fixer_flight_224); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_225 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hE1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hE1 \| fixer_flight_225); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_226 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hE2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hE2 \| fixer_flight_226); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_227 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hE3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hE3 \| fixer_flight_227); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_228 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hE4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hE4 \| fixer_flight_228); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_229 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hE5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hE5 \| fixer_flight_229); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_230 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hE6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hE6 \| fixer_flight_230); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_231 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hE7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hE7 \| fixer_flight_231); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_232 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hE8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hE8 \| fixer_flight_232); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_233 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hE9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hE9 \| fixer_flight_233); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_234 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hEA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hEA \| fixer_flight_234); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_235 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hEB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hEB \| fixer_flight_235); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_236 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hEC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hEC \| fixer_flight_236); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_237 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hED) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hED \| fixer_flight_237); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_238 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hEE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hEE \| fixer_flight_238); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_239 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hEF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hEF \| fixer_flight_239); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_240 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hF0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hF0 \| fixer_flight_240); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_241 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hF1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hF1 \| fixer_flight_241); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_242 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hF2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hF2 \| fixer_flight_242); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_243 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hF3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hF3 \| fixer_flight_243); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_244 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hF4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hF4 \| fixer_flight_244); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_245 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hF5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hF5 \| fixer_flight_245); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_246 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hF6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hF6 \| fixer_flight_246); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_247 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hF7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hF7 \| fixer_flight_247); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_248 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hF8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hF8 \| fixer_flight_248); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_249 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hF9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hF9 \| fixer_flight_249); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_250 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hFA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hFA \| fixer_flight_250); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_251 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hFB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hFB \| fixer_flight_251); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_252 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hFC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hFC \| fixer_flight_252); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_253 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hFD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hFD \| fixer_flight_253); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_254 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hFE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hFE \| fixer_flight_254); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_255 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'hFF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'hFF \| fixer_flight_255); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_256 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h100) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h100 \| fixer_flight_256); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_257 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h101) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h101 \| fixer_flight_257); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_258 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h102) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h102 \| fixer_flight_258); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_259 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h103) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h103 \| fixer_flight_259); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_260 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h104) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h104 \| fixer_flight_260); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_261 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h105) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h105 \| fixer_flight_261); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_262 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h106) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h106 \| fixer_flight_262); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_263 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h107) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h107 \| fixer_flight_263); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_264 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h108) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h108 \| fixer_flight_264); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_265 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h109) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h109 \| fixer_flight_265); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_266 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h10A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h10A \| fixer_flight_266); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_267 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h10B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h10B \| fixer_flight_267); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_268 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h10C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h10C \| fixer_flight_268); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_269 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h10D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h10D \| fixer_flight_269); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_270 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h10E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h10E \| fixer_flight_270); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_271 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h10F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h10F \| fixer_flight_271); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_272 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h110) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h110 \| fixer_flight_272); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_273 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h111) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h111 \| fixer_flight_273); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_274 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h112) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h112 \| fixer_flight_274); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_275 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h113) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h113 \| fixer_flight_275); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_276 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h114) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h114 \| fixer_flight_276); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_277 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h115) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h115 \| fixer_flight_277); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_278 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h116) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h116 \| fixer_flight_278); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_279 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h117) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h117 \| fixer_flight_279); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_280 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h118) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h118 \| fixer_flight_280); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_281 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h119) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h119 \| fixer_flight_281); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_282 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h11A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h11A \| fixer_flight_282); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_283 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h11B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h11B \| fixer_flight_283); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_284 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h11C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h11C \| fixer_flight_284); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_285 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h11D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h11D \| fixer_flight_285); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_286 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h11E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h11E \| fixer_flight_286); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_287 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h11F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h11F \| fixer_flight_287); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_288 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h120) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h120 \| fixer_flight_288); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_289 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h121) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h121 \| fixer_flight_289); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_290 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h122) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h122 \| fixer_flight_290); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_291 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h123) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h123 \| fixer_flight_291); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_292 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h124) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h124 \| fixer_flight_292); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_293 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h125) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h125 \| fixer_flight_293); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_294 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h126) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h126 \| fixer_flight_294); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_295 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h127) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h127 \| fixer_flight_295); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_296 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h128) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h128 \| fixer_flight_296); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_297 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h129) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h129 \| fixer_flight_297); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_298 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h12A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h12A \| fixer_flight_298); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_299 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h12B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h12B \| fixer_flight_299); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_300 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h12C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h12C \| fixer_flight_300); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_301 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h12D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h12D \| fixer_flight_301); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_302 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h12E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h12E \| fixer_flight_302); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_303 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h12F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h12F \| fixer_flight_303); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_304 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h130) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h130 \| fixer_flight_304); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_305 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h131) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h131 \| fixer_flight_305); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_306 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h132) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h132 \| fixer_flight_306); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_307 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h133) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h133 \| fixer_flight_307); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_308 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h134) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h134 \| fixer_flight_308); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_309 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h135) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h135 \| fixer_flight_309); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_310 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h136) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h136 \| fixer_flight_310); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_311 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h137) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h137 \| fixer_flight_311); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_312 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h138) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h138 \| fixer_flight_312); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_313 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h139) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h139 \| fixer_flight_313); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_314 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h13A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h13A \| fixer_flight_314); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_315 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h13B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h13B \| fixer_flight_315); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_316 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h13C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h13C \| fixer_flight_316); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_317 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h13D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h13D \| fixer_flight_317); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_318 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h13E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h13E \| fixer_flight_318); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_319 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h13F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h13F \| fixer_flight_319); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_320 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h140) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h140 \| fixer_flight_320); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_321 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h141) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h141 \| fixer_flight_321); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_322 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h142) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h142 \| fixer_flight_322); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_323 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h143) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h143 \| fixer_flight_323); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_324 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h144) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h144 \| fixer_flight_324); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_325 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h145) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h145 \| fixer_flight_325); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_326 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h146) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h146 \| fixer_flight_326); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_327 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h147) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h147 \| fixer_flight_327); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_328 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h148) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h148 \| fixer_flight_328); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_329 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h149) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h149 \| fixer_flight_329); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_330 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h14A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h14A \| fixer_flight_330); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_331 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h14B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h14B \| fixer_flight_331); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_332 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h14C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h14C \| fixer_flight_332); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_333 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h14D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h14D \| fixer_flight_333); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_334 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h14E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h14E \| fixer_flight_334); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_335 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h14F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h14F \| fixer_flight_335); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_336 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h150) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h150 \| fixer_flight_336); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_337 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h151) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h151 \| fixer_flight_337); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_338 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h152) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h152 \| fixer_flight_338); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_339 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h153) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h153 \| fixer_flight_339); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_340 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h154) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h154 \| fixer_flight_340); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_341 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h155) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h155 \| fixer_flight_341); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_342 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h156) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h156 \| fixer_flight_342); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_343 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h157) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h157 \| fixer_flight_343); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_344 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h158) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h158 \| fixer_flight_344); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_345 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h159) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h159 \| fixer_flight_345); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_346 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h15A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h15A \| fixer_flight_346); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_347 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h15B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h15B \| fixer_flight_347); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_348 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h15C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h15C \| fixer_flight_348); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_349 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h15D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h15D \| fixer_flight_349); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_350 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h15E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h15E \| fixer_flight_350); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_351 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h15F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h15F \| fixer_flight_351); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_352 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h160) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h160 \| fixer_flight_352); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_353 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h161) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h161 \| fixer_flight_353); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_354 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h162) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h162 \| fixer_flight_354); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_355 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h163) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h163 \| fixer_flight_355); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_356 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h164) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h164 \| fixer_flight_356); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_357 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h165) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h165 \| fixer_flight_357); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_358 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h166) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h166 \| fixer_flight_358); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_359 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h167) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h167 \| fixer_flight_359); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_360 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h168) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h168 \| fixer_flight_360); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_361 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h169) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h169 \| fixer_flight_361); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_362 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h16A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h16A \| fixer_flight_362); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_363 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h16B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h16B \| fixer_flight_363); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_364 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h16C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h16C \| fixer_flight_364); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_365 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h16D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h16D \| fixer_flight_365); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_366 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h16E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h16E \| fixer_flight_366); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_367 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h16F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h16F \| fixer_flight_367); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_368 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h170) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h170 \| fixer_flight_368); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_369 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h171) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h171 \| fixer_flight_369); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_370 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h172) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h172 \| fixer_flight_370); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_371 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h173) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h173 \| fixer_flight_371); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_372 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h174) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h174 \| fixer_flight_372); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_373 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h175) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h175 \| fixer_flight_373); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_374 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h176) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h176 \| fixer_flight_374); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_375 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h177) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h177 \| fixer_flight_375); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_376 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h178) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h178 \| fixer_flight_376); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_377 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h179) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h179 \| fixer_flight_377); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_378 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h17A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h17A \| fixer_flight_378); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_379 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h17B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h17B \| fixer_flight_379); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_380 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h17C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h17C \| fixer_flight_380); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_381 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h17D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h17D \| fixer_flight_381); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_382 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h17E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h17E \| fixer_flight_382); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_383 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h17F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h17F \| fixer_flight_383); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_384 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h180) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h180 \| fixer_flight_384); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_385 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h181) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h181 \| fixer_flight_385); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_386 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h182) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h182 \| fixer_flight_386); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_387 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h183) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h183 \| fixer_flight_387); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_388 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h184) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h184 \| fixer_flight_388); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_389 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h185) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h185 \| fixer_flight_389); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_390 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h186) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h186 \| fixer_flight_390); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_391 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h187) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h187 \| fixer_flight_391); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_392 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h188) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h188 \| fixer_flight_392); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_393 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h189) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h189 \| fixer_flight_393); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_394 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h18A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h18A \| fixer_flight_394); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_395 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h18B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h18B \| fixer_flight_395); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_396 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h18C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h18C \| fixer_flight_396); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_397 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h18D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h18D \| fixer_flight_397); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_398 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h18E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h18E \| fixer_flight_398); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_399 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h18F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h18F \| fixer_flight_399); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_400 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h190) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h190 \| fixer_flight_400); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_401 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h191) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h191 \| fixer_flight_401); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_402 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h192) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h192 \| fixer_flight_402); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_403 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h193) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h193 \| fixer_flight_403); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_404 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h194) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h194 \| fixer_flight_404); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_405 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h195) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h195 \| fixer_flight_405); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_406 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h196) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h196 \| fixer_flight_406); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_407 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h197) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h197 \| fixer_flight_407); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_408 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h198) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h198 \| fixer_flight_408); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_409 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h199) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h199 \| fixer_flight_409); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_410 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h19A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h19A \| fixer_flight_410); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_411 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h19B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h19B \| fixer_flight_411); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_412 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h19C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h19C \| fixer_flight_412); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_413 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h19D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h19D \| fixer_flight_413); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_414 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h19E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h19E \| fixer_flight_414); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_415 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h19F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h19F \| fixer_flight_415); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_416 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1A0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1A0 \| fixer_flight_416); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_417 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1A1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1A1 \| fixer_flight_417); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_418 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1A2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1A2 \| fixer_flight_418); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_419 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1A3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1A3 \| fixer_flight_419); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_420 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1A4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1A4 \| fixer_flight_420); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_421 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1A5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1A5 \| fixer_flight_421); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_422 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1A6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1A6 \| fixer_flight_422); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_423 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1A7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1A7 \| fixer_flight_423); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_424 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1A8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1A8 \| fixer_flight_424); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_425 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1A9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1A9 \| fixer_flight_425); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_426 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1AA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1AA \| fixer_flight_426); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_427 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1AB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1AB \| fixer_flight_427); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_428 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1AC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1AC \| fixer_flight_428); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_429 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1AD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1AD \| fixer_flight_429); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_430 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1AE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1AE \| fixer_flight_430); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_431 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1AF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1AF \| fixer_flight_431); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_432 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1B0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1B0 \| fixer_flight_432); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_433 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1B1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1B1 \| fixer_flight_433); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_434 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1B2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1B2 \| fixer_flight_434); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_435 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1B3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1B3 \| fixer_flight_435); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_436 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1B4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1B4 \| fixer_flight_436); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_437 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1B5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1B5 \| fixer_flight_437); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_438 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1B6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1B6 \| fixer_flight_438); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_439 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1B7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1B7 \| fixer_flight_439); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_440 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1B8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1B8 \| fixer_flight_440); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_441 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1B9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1B9 \| fixer_flight_441); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_442 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1BA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1BA \| fixer_flight_442); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_443 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1BB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1BB \| fixer_flight_443); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_444 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1BC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1BC \| fixer_flight_444); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_445 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1BD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1BD \| fixer_flight_445); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_446 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1BE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1BE \| fixer_flight_446); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_447 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1BF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1BF \| fixer_flight_447); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_448 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1C0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1C0 \| fixer_flight_448); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_449 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1C1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1C1 \| fixer_flight_449); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_450 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1C2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1C2 \| fixer_flight_450); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_451 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1C3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1C3 \| fixer_flight_451); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_452 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1C4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1C4 \| fixer_flight_452); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_453 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1C5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1C5 \| fixer_flight_453); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_454 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1C6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1C6 \| fixer_flight_454); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_455 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1C7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1C7 \| fixer_flight_455); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_456 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1C8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1C8 \| fixer_flight_456); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_457 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1C9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1C9 \| fixer_flight_457); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_458 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1CA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1CA \| fixer_flight_458); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_459 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1CB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1CB \| fixer_flight_459); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_460 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1CC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1CC \| fixer_flight_460); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_461 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1CD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1CD \| fixer_flight_461); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_462 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1CE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1CE \| fixer_flight_462); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_463 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1CF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1CF \| fixer_flight_463); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_464 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1D0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1D0 \| fixer_flight_464); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_465 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1D1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1D1 \| fixer_flight_465); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_466 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1D2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1D2 \| fixer_flight_466); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_467 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1D3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1D3 \| fixer_flight_467); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_468 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1D4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1D4 \| fixer_flight_468); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_469 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1D5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1D5 \| fixer_flight_469); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_470 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1D6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1D6 \| fixer_flight_470); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_471 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1D7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1D7 \| fixer_flight_471); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_472 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1D8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1D8 \| fixer_flight_472); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_473 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1D9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1D9 \| fixer_flight_473); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_474 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1DA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1DA \| fixer_flight_474); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_475 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1DB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1DB \| fixer_flight_475); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_476 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1DC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1DC \| fixer_flight_476); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_477 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1DD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1DD \| fixer_flight_477); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_478 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1DE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1DE \| fixer_flight_478); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_479 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1DF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1DF \| fixer_flight_479); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_480 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1E0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1E0 \| fixer_flight_480); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_481 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1E1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1E1 \| fixer_flight_481); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_482 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1E2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1E2 \| fixer_flight_482); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_483 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1E3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1E3 \| fixer_flight_483); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_484 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1E4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1E4 \| fixer_flight_484); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_485 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1E5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1E5 \| fixer_flight_485); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_486 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1E6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1E6 \| fixer_flight_486); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_487 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1E7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1E7 \| fixer_flight_487); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_488 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1E8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1E8 \| fixer_flight_488); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_489 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1E9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1E9 \| fixer_flight_489); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_490 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1EA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1EA \| fixer_flight_490); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_491 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1EB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1EB \| fixer_flight_491); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_492 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1EC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1EC \| fixer_flight_492); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_493 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1ED) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1ED \| fixer_flight_493); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_494 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1EE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1EE \| fixer_flight_494); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_495 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1EF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1EF \| fixer_flight_495); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_496 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1F0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1F0 \| fixer_flight_496); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_497 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1F1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1F1 \| fixer_flight_497); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_498 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1F2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1F2 \| fixer_flight_498); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_499 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1F3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1F3 \| fixer_flight_499); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_500 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1F4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1F4 \| fixer_flight_500); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_501 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1F5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1F5 \| fixer_flight_501); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_502 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1F6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1F6 \| fixer_flight_502); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_503 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1F7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1F7 \| fixer_flight_503); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_504 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1F8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1F8 \| fixer_flight_504); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_505 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1F9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1F9 \| fixer_flight_505); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_506 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1FA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1FA \| fixer_flight_506); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_507 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1FB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1FB \| fixer_flight_507); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_508 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1FC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1FC \| fixer_flight_508); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_509 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1FD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1FD \| fixer_flight_509); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_510 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1FE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1FE \| fixer_flight_510); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_511 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h1FF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h1FF \| fixer_flight_511); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_flight_512 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 10'h200) & (fixer__T_1 & fixer_anonIn_a_bits_source == 10'h200 \| fixer_flight_512); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] if (valids_0 \| valids_1 \| valids_2 \| valids_3 \| valids_4 \| valids_5 \| valids_6 \| valids_7) // @[RegField.scala:153:29, :154:27] bootAddrReg <= _bootAddrReg_T; // @[BootAddrReg.scala:27:34] end always @(posedge) FixedClockBroadcast_2 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_pbus_out_i1_o2_a29d64s10k1z3u out_xbar ( // @[PeripheryBus.scala:57:30] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (fixer_auto_anon_out_a_ready), .auto_anon_in_a_valid (fixer_auto_anon_out_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_opcode (fixer_auto_anon_out_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_param (fixer_auto_anon_out_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_size (fixer_auto_anon_out_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_source (fixer_auto_anon_out_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_address (fixer_auto_anon_out_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_mask (fixer_auto_anon_out_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_data (fixer_auto_anon_out_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_a_bits_corrupt (fixer_auto_anon_out_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_ready (fixer_auto_anon_out_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_d_valid (fixer_auto_anon_out_d_valid), .auto_anon_in_d_bits_opcode (fixer_auto_anon_out_d_bits_opcode), .auto_anon_in_d_bits_size (fixer_auto_anon_out_d_bits_size), .auto_anon_in_d_bits_source (fixer_auto_anon_out_d_bits_source), .auto_anon_in_d_bits_data (fixer_auto_anon_out_d_bits_data), .auto_anon_out_1_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_1_a_valid (_out_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_out_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_valid (_out_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_out_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data) // @[LazyScope.scala:98:27] ); // @[PeripheryBus.scala:57:30] TLBuffer_a29d64s10k1z3u buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_atomics_auto_out_a_valid), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_opcode (_atomics_auto_out_a_bits_opcode), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_param (_atomics_auto_out_a_bits_param), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_size (_atomics_auto_out_a_bits_size), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_source (_atomics_auto_out_a_bits_source), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_address (_atomics_auto_out_a_bits_address), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_mask (_atomics_auto_out_a_bits_mask), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_data (_atomics_auto_out_a_bits_data), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), // @[AtomicAutomata.scala:289:29] .auto_in_d_ready (_atomics_auto_out_d_ready), // @[AtomicAutomata.scala:289:29] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:50:9] .auto_out_a_valid (fixer_auto_anon_in_a_valid), .auto_out_a_bits_opcode (fixer_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (fixer_auto_anon_in_a_bits_param), .auto_out_a_bits_size (fixer_auto_anon_in_a_bits_size), .auto_out_a_bits_source (fixer_auto_anon_in_a_bits_source), .auto_out_a_bits_address (fixer_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (fixer_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (fixer_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (fixer_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (fixer_auto_anon_in_d_ready), .auto_out_d_valid (fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_opcode (fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_size (fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_source (fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:50:9] .auto_out_d_bits_data (fixer_auto_anon_in_d_bits_data) // @[FIFOFixer.scala:50:9] ); // @[Buffer.scala:75:28] TLAtomicAutomata_pbus atomics ( // @[AtomicAutomata.scala:289:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (in_xbar_auto_anon_out_a_ready), .auto_in_a_valid (in_xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9] .auto_in_a_bits_opcode (in_xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9] .auto_in_a_bits_param (in_xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9] .auto_in_a_bits_size (in_xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9] .auto_in_a_bits_source (in_xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9] .auto_in_a_bits_address (in_xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9] .auto_in_a_bits_mask (in_xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9] .auto_in_a_bits_data (in_xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9] .auto_in_a_bits_corrupt (in_xbar_auto_anon_out_a_bits_corrupt), // @[Xbar.scala:74:9] .auto_in_d_ready (in_xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9] .auto_in_d_valid (in_xbar_auto_anon_out_d_valid), .auto_in_d_bits_opcode (in_xbar_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (in_xbar_auto_anon_out_d_bits_param), .auto_in_d_bits_size (in_xbar_auto_anon_out_d_bits_size), .auto_in_d_bits_source (in_xbar_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (in_xbar_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (in_xbar_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (in_xbar_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (in_xbar_auto_anon_out_d_bits_corrupt), .auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_out_a_valid (_atomics_auto_out_a_valid), .auto_out_a_bits_opcode (_atomics_auto_out_a_bits_opcode), .auto_out_a_bits_param (_atomics_auto_out_a_bits_param), .auto_out_a_bits_size (_atomics_auto_out_a_bits_size), .auto_out_a_bits_source (_atomics_auto_out_a_bits_source), .auto_out_a_bits_address (_atomics_auto_out_a_bits_address), .auto_out_a_bits_mask (_atomics_auto_out_a_bits_mask), .auto_out_a_bits_data (_atomics_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), .auto_out_d_ready (_atomics_auto_out_d_ready), .auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[AtomicAutomata.scala:289:29] TLBuffer_a29d64s10k1z3u_1 buffer_1 ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (bus_xingOut_a_ready), .auto_in_a_valid (bus_xingOut_a_valid), // @[MixedNode.scala:542:17] .auto_in_a_bits_opcode (bus_xingOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_in_a_bits_param (bus_xingOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_in_a_bits_size (bus_xingOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_in_a_bits_source (bus_xingOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_in_a_bits_address (bus_xingOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_in_a_bits_mask (bus_xingOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_in_a_bits_data (bus_xingOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_in_a_bits_corrupt (bus_xingOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_in_d_ready (bus_xingOut_d_ready), // @[MixedNode.scala:542:17] .auto_in_d_valid (bus_xingOut_d_valid), .auto_in_d_bits_opcode (bus_xingOut_d_bits_opcode), .auto_in_d_bits_param (bus_xingOut_d_bits_param), .auto_in_d_bits_size (bus_xingOut_d_bits_size), .auto_in_d_bits_source (bus_xingOut_d_bits_source), .auto_in_d_bits_sink (bus_xingOut_d_bits_sink), .auto_in_d_bits_denied (bus_xingOut_d_bits_denied), .auto_in_d_bits_data (bus_xingOut_d_bits_data), .auto_in_d_bits_corrupt (bus_xingOut_d_bits_corrupt), .auto_out_a_ready (in_xbar_auto_anon_in_a_ready), // @[Xbar.scala:74:9] .auto_out_a_valid (in_xbar_auto_anon_in_a_valid), .auto_out_a_bits_opcode (in_xbar_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (in_xbar_auto_anon_in_a_bits_param), .auto_out_a_bits_size (in_xbar_auto_anon_in_a_bits_size), .auto_out_a_bits_source (in_xbar_auto_anon_in_a_bits_source), .auto_out_a_bits_address (in_xbar_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (in_xbar_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (in_xbar_auto_anon_in_a_bits_data), .auto_out_a_bits_corrupt (in_xbar_auto_anon_in_a_bits_corrupt), .auto_out_d_ready (in_xbar_auto_anon_in_d_ready), .auto_out_d_valid (in_xbar_auto_anon_in_d_valid), // @[Xbar.scala:74:9] .auto_out_d_bits_opcode (in_xbar_auto_anon_in_d_bits_opcode), // @[Xbar.scala:74:9] .auto_out_d_bits_param (in_xbar_auto_anon_in_d_bits_param), // @[Xbar.scala:74:9] .auto_out_d_bits_size (in_xbar_auto_anon_in_d_bits_size), // @[Xbar.scala:74:9] .auto_out_d_bits_source (in_xbar_auto_anon_in_d_bits_source), // @[Xbar.scala:74:9] .auto_out_d_bits_sink (in_xbar_auto_anon_in_d_bits_sink), // @[Xbar.scala:74:9] .auto_out_d_bits_denied (in_xbar_auto_anon_in_d_bits_denied), // @[Xbar.scala:74:9] .auto_out_d_bits_data (in_xbar_auto_anon_in_d_bits_data), // @[Xbar.scala:74:9] .auto_out_d_bits_corrupt (in_xbar_auto_anon_in_d_bits_corrupt) // @[Xbar.scala:74:9] ); // @[Buffer.scala:75:28] TLInterconnectCoupler_pbus_to_bootaddressreg coupler_to_bootaddressreg ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_a_valid (nodeIn_a_valid), .auto_fragmenter_anon_out_a_bits_opcode (nodeIn_a_bits_opcode), .auto_fragmenter_anon_out_a_bits_param (nodeIn_a_bits_param), .auto_fragmenter_anon_out_a_bits_size (nodeIn_a_bits_size), .auto_fragmenter_anon_out_a_bits_source (nodeIn_a_bits_source), .auto_fragmenter_anon_out_a_bits_address (nodeIn_a_bits_address), .auto_fragmenter_anon_out_a_bits_mask (nodeIn_a_bits_mask), .auto_fragmenter_anon_out_a_bits_data (nodeIn_a_bits_data), .auto_fragmenter_anon_out_a_bits_corrupt (nodeIn_a_bits_corrupt), .auto_fragmenter_anon_out_d_ready (nodeIn_d_ready), .auto_fragmenter_anon_out_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_fragmenter_anon_out_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_in_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_0_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_0_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_pbus_to_device_named_uart_0 coupler_to_device_named_uart_0 ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_control_xing_out_a_ready (auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_a_valid (auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0), .auto_control_xing_out_a_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0), .auto_control_xing_out_a_bits_param (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0), .auto_control_xing_out_a_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0), .auto_control_xing_out_a_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0), .auto_control_xing_out_a_bits_address (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0), .auto_control_xing_out_a_bits_mask (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0), .auto_control_xing_out_a_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0), .auto_control_xing_out_a_bits_corrupt (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0), .auto_control_xing_out_d_ready (auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0), .auto_control_xing_out_d_valid (auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_control_xing_out_d_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_1_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_1_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLMonitor_26 monitor ( // @[Nodes.scala:27:25] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_valid = auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_device_named_uart_0_control_xing_out_d_ready = auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_clock = auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_reset = auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_52 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData_52( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ShiftQueue_4 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, count : UInt<3>, mask : UInt<5>} wire _valid_WIRE : UInt<1>[5] connect _valid_WIRE[0], UInt<1>(0h0) connect _valid_WIRE[1], UInt<1>(0h0) connect _valid_WIRE[2], UInt<1>(0h0) connect _valid_WIRE[3], UInt<1>(0h0) connect _valid_WIRE[4], UInt<1>(0h0) regreset valid : UInt<1>[5], clock, reset, _valid_WIRE reg elts : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}[5], clock node wdata = mux(valid[1], elts[1], io.enq.bits) node _wen_T = and(io.enq.ready, io.enq.valid) node _wen_T_1 = or(UInt<1>(0h0), valid[0]) node _wen_T_2 = and(_wen_T, _wen_T_1) node _wen_T_3 = or(valid[1], _wen_T_2) node _wen_T_4 = and(io.enq.ready, io.enq.valid) node _wen_T_5 = and(_wen_T_4, UInt<1>(0h1)) node _wen_T_6 = eq(valid[0], UInt<1>(0h0)) node _wen_T_7 = and(_wen_T_5, _wen_T_6) node wen = mux(io.deq.ready, _wen_T_3, _wen_T_7) when wen : connect elts[0], wdata node _valid_0_T = and(io.enq.ready, io.enq.valid) node _valid_0_T_1 = or(UInt<1>(0h0), valid[0]) node _valid_0_T_2 = and(_valid_0_T, _valid_0_T_1) node _valid_0_T_3 = or(valid[1], _valid_0_T_2) node _valid_0_T_4 = and(io.enq.ready, io.enq.valid) node _valid_0_T_5 = and(_valid_0_T_4, UInt<1>(0h1)) node _valid_0_T_6 = or(_valid_0_T_5, valid[0]) node _valid_0_T_7 = mux(io.deq.ready, _valid_0_T_3, _valid_0_T_6) connect valid[0], _valid_0_T_7 node wdata_1 = mux(valid[2], elts[2], io.enq.bits) node _wen_T_8 = and(io.enq.ready, io.enq.valid) node _wen_T_9 = or(UInt<1>(0h0), valid[1]) node _wen_T_10 = and(_wen_T_8, _wen_T_9) node _wen_T_11 = or(valid[2], _wen_T_10) node _wen_T_12 = and(io.enq.ready, io.enq.valid) node _wen_T_13 = and(_wen_T_12, valid[0]) node _wen_T_14 = eq(valid[1], UInt<1>(0h0)) node _wen_T_15 = and(_wen_T_13, _wen_T_14) node wen_1 = mux(io.deq.ready, _wen_T_11, _wen_T_15) when wen_1 : connect elts[1], wdata_1 node _valid_1_T = and(io.enq.ready, io.enq.valid) node _valid_1_T_1 = or(UInt<1>(0h0), valid[1]) node _valid_1_T_2 = and(_valid_1_T, _valid_1_T_1) node _valid_1_T_3 = or(valid[2], _valid_1_T_2) node _valid_1_T_4 = and(io.enq.ready, io.enq.valid) node _valid_1_T_5 = and(_valid_1_T_4, valid[0]) node _valid_1_T_6 = or(_valid_1_T_5, valid[1]) node _valid_1_T_7 = mux(io.deq.ready, _valid_1_T_3, _valid_1_T_6) connect valid[1], _valid_1_T_7 node wdata_2 = mux(valid[3], elts[3], io.enq.bits) node _wen_T_16 = and(io.enq.ready, io.enq.valid) node _wen_T_17 = or(UInt<1>(0h0), valid[2]) node _wen_T_18 = and(_wen_T_16, _wen_T_17) node _wen_T_19 = or(valid[3], _wen_T_18) node _wen_T_20 = and(io.enq.ready, io.enq.valid) node _wen_T_21 = and(_wen_T_20, valid[1]) node _wen_T_22 = eq(valid[2], UInt<1>(0h0)) node _wen_T_23 = and(_wen_T_21, _wen_T_22) node wen_2 = mux(io.deq.ready, _wen_T_19, _wen_T_23) when wen_2 : connect elts[2], wdata_2 node _valid_2_T = and(io.enq.ready, io.enq.valid) node _valid_2_T_1 = or(UInt<1>(0h0), valid[2]) node _valid_2_T_2 = and(_valid_2_T, _valid_2_T_1) node _valid_2_T_3 = or(valid[3], _valid_2_T_2) node _valid_2_T_4 = and(io.enq.ready, io.enq.valid) node _valid_2_T_5 = and(_valid_2_T_4, valid[1]) node _valid_2_T_6 = or(_valid_2_T_5, valid[2]) node _valid_2_T_7 = mux(io.deq.ready, _valid_2_T_3, _valid_2_T_6) connect valid[2], _valid_2_T_7 node wdata_3 = mux(valid[4], elts[4], io.enq.bits) node _wen_T_24 = and(io.enq.ready, io.enq.valid) node _wen_T_25 = or(UInt<1>(0h0), valid[3]) node _wen_T_26 = and(_wen_T_24, _wen_T_25) node _wen_T_27 = or(valid[4], _wen_T_26) node _wen_T_28 = and(io.enq.ready, io.enq.valid) node _wen_T_29 = and(_wen_T_28, valid[2]) node _wen_T_30 = eq(valid[3], UInt<1>(0h0)) node _wen_T_31 = and(_wen_T_29, _wen_T_30) node wen_3 = mux(io.deq.ready, _wen_T_27, _wen_T_31) when wen_3 : connect elts[3], wdata_3 node _valid_3_T = and(io.enq.ready, io.enq.valid) node _valid_3_T_1 = or(UInt<1>(0h0), valid[3]) node _valid_3_T_2 = and(_valid_3_T, _valid_3_T_1) node _valid_3_T_3 = or(valid[4], _valid_3_T_2) node _valid_3_T_4 = and(io.enq.ready, io.enq.valid) node _valid_3_T_5 = and(_valid_3_T_4, valid[2]) node _valid_3_T_6 = or(_valid_3_T_5, valid[3]) node _valid_3_T_7 = mux(io.deq.ready, _valid_3_T_3, _valid_3_T_6) connect valid[3], _valid_3_T_7 node _wen_T_32 = and(io.enq.ready, io.enq.valid) node _wen_T_33 = or(UInt<1>(0h0), valid[4]) node _wen_T_34 = and(_wen_T_32, _wen_T_33) node _wen_T_35 = or(UInt<1>(0h0), _wen_T_34) node _wen_T_36 = and(io.enq.ready, io.enq.valid) node _wen_T_37 = and(_wen_T_36, valid[3]) node _wen_T_38 = eq(valid[4], UInt<1>(0h0)) node _wen_T_39 = and(_wen_T_37, _wen_T_38) node wen_4 = mux(io.deq.ready, _wen_T_35, _wen_T_39) when wen_4 : connect elts[4], io.enq.bits node _valid_4_T = and(io.enq.ready, io.enq.valid) node _valid_4_T_1 = or(UInt<1>(0h0), valid[4]) node _valid_4_T_2 = and(_valid_4_T, _valid_4_T_1) node _valid_4_T_3 = or(UInt<1>(0h0), _valid_4_T_2) node _valid_4_T_4 = and(io.enq.ready, io.enq.valid) node _valid_4_T_5 = and(_valid_4_T_4, valid[3]) node _valid_4_T_6 = or(_valid_4_T_5, valid[4]) node _valid_4_T_7 = mux(io.deq.ready, _valid_4_T_3, _valid_4_T_6) connect valid[4], _valid_4_T_7 node _io_enq_ready_T = eq(valid[4], UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T connect io.deq.valid, valid[0] connect io.deq.bits, elts[0] when io.enq.valid : connect io.deq.valid, UInt<1>(0h1) node _T = eq(valid[0], UInt<1>(0h0)) when _T : connect io.deq.bits, io.enq.bits node io_mask_lo = cat(valid[1], valid[0]) node io_mask_hi_hi = cat(valid[4], valid[3]) node io_mask_hi = cat(io_mask_hi_hi, valid[2]) node _io_mask_T = cat(io_mask_hi, io_mask_lo) connect io.mask, _io_mask_T node _io_count_T = bits(io.mask, 0, 0) node _io_count_T_1 = bits(io.mask, 1, 1) node _io_count_T_2 = bits(io.mask, 2, 2) node _io_count_T_3 = bits(io.mask, 3, 3) node _io_count_T_4 = bits(io.mask, 4, 4) node _io_count_T_5 = add(_io_count_T, _io_count_T_1) node _io_count_T_6 = bits(_io_count_T_5, 1, 0) node _io_count_T_7 = add(_io_count_T_3, _io_count_T_4) node _io_count_T_8 = bits(_io_count_T_7, 1, 0) node _io_count_T_9 = add(_io_count_T_2, _io_count_T_8) node _io_count_T_10 = bits(_io_count_T_9, 1, 0) node _io_count_T_11 = add(_io_count_T_6, _io_count_T_10) node _io_count_T_12 = bits(_io_count_T_11, 2, 0) connect io.count, _io_count_T_12	module ShiftQueue_4( // @[ShiftQueue.scala:12:7] input clock, // @[ShiftQueue.scala:12:7] input reset, // @[ShiftQueue.scala:12:7] output io_enq_ready, // @[ShiftQueue.scala:17:14] input io_enq_valid, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_taken, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] input [38:0] io_enq_bits_btb_target, // @[ShiftQueue.scala:17:14] input [4:0] io_enq_bits_btb_entry, // @[ShiftQueue.scala:17:14] input [7:0] io_enq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] input [39:0] io_enq_bits_pc, // @[ShiftQueue.scala:17:14] input [31:0] io_enq_bits_data, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_replay, // @[ShiftQueue.scala:17:14] input io_deq_ready, // @[ShiftQueue.scala:17:14] output io_deq_valid, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_taken, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] output [38:0] io_deq_bits_btb_target, // @[ShiftQueue.scala:17:14] output [4:0] io_deq_bits_btb_entry, // @[ShiftQueue.scala:17:14] output [7:0] io_deq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] output [39:0] io_deq_bits_pc, // @[ShiftQueue.scala:17:14] output [31:0] io_deq_bits_data, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_gf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_replay, // @[ShiftQueue.scala:17:14] output [4:0] io_mask // @[ShiftQueue.scala:17:14] ); wire io_enq_valid_0 = io_enq_valid; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_cfiType_0 = io_enq_bits_btb_cfiType; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_taken_0 = io_enq_bits_btb_taken; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_mask_0 = io_enq_bits_btb_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bridx_0 = io_enq_bits_btb_bridx; // @[ShiftQueue.scala:12:7] wire [38:0] io_enq_bits_btb_target_0 = io_enq_bits_btb_target; // @[ShiftQueue.scala:12:7] wire [4:0] io_enq_bits_btb_entry_0 = io_enq_bits_btb_entry; // @[ShiftQueue.scala:12:7] wire [7:0] io_enq_bits_btb_bht_history_0 = io_enq_bits_btb_bht_history; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bht_value_0 = io_enq_bits_btb_bht_value; // @[ShiftQueue.scala:12:7] wire [39:0] io_enq_bits_pc_0 = io_enq_bits_pc; // @[ShiftQueue.scala:12:7] wire [31:0] io_enq_bits_data_0 = io_enq_bits_data; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_pf_inst_0 = io_enq_bits_xcpt_pf_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_ae_inst_0 = io_enq_bits_xcpt_ae_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_replay_0 = io_enq_bits_replay; // @[ShiftQueue.scala:12:7] wire io_deq_ready_0 = io_deq_ready; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_gf_inst = 1'h0; // @[ShiftQueue.scala:12:7] wire _valid_WIRE_0 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_1 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_2 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_3 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_4 = 1'h0; // @[ShiftQueue.scala:21:38] wire _io_enq_ready_T; // @[ShiftQueue.scala:40:19] wire [2:0] _io_count_T_12; // @[ShiftQueue.scala:54:23] wire [4:0] _io_mask_T; // @[ShiftQueue.scala:53:20] wire io_enq_ready_0; // @[ShiftQueue.scala:12:7] wire [7:0] io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] wire [38:0] io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] wire [4:0] io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] wire [39:0] io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] wire [31:0] io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] wire io_deq_valid_0; // @[ShiftQueue.scala:12:7] wire [2:0] io_count; // @[ShiftQueue.scala:12:7] wire [4:0] io_mask_0; // @[ShiftQueue.scala:12:7] reg valid_0; // @[ShiftQueue.scala:21:30] wire _wen_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_0_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :36:67] reg valid_1; // @[ShiftQueue.scala:21:30] wire _wen_T_9 = valid_1; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_1_T_1 = valid_1; // @[ShiftQueue.scala:21:30, :36:67] reg valid_2; // @[ShiftQueue.scala:21:30] wire _wen_T_17 = valid_2; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_2_T_1 = valid_2; // @[ShiftQueue.scala:21:30, :36:67] reg valid_3; // @[ShiftQueue.scala:21:30] wire _wen_T_25 = valid_3; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_3_T_1 = valid_3; // @[ShiftQueue.scala:21:30, :36:67] reg valid_4; // @[ShiftQueue.scala:21:30] wire _wen_T_33 = valid_4; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_4_T_1 = valid_4; // @[ShiftQueue.scala:21:30, :36:67] reg [1:0] elts_0_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_0_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_0_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_0_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_0_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_0_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_0_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_mask; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_0_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_1_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_1_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_1_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_1_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_1_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_1_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_mask; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_1_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_2_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_2_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_2_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_2_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_2_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_2_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_mask; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_2_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_3_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_3_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_3_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_3_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_3_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_3_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_mask; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_3_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_4_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_4_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_4_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_4_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_4_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_4_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_mask; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_4_replay; // @[ShiftQueue.scala:22:25] wire [1:0] wdata_btb_cfiType = valid_1 ? elts_1_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_taken = valid_1 ? elts_1_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_btb_mask = valid_1 ? elts_1_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bridx = valid_1 ? elts_1_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_btb_target = valid_1 ? elts_1_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_btb_entry = valid_1 ? elts_1_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_btb_bht_history = valid_1 ? elts_1_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bht_value = valid_1 ? elts_1_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_pc = valid_1 ? elts_1_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_data = valid_1 ? elts_1_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_mask = valid_1 ? elts_1_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_pf_inst = valid_1 ? elts_1_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_gf_inst = valid_1 & elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_xcpt_ae_inst = valid_1 ? elts_1_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_replay = valid_1 ? elts_1_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _GEN = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _wen_T; // @[Decoupled.scala:51:35] assign _wen_T = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_4; // @[Decoupled.scala:51:35] assign _wen_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T; // @[Decoupled.scala:51:35] assign _valid_0_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T_4; // @[Decoupled.scala:51:35] assign _valid_0_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_8; // @[Decoupled.scala:51:35] assign _wen_T_8 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_12; // @[Decoupled.scala:51:35] assign _wen_T_12 = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T; // @[Decoupled.scala:51:35] assign _valid_1_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T_4; // @[Decoupled.scala:51:35] assign _valid_1_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_16; // @[Decoupled.scala:51:35] assign _wen_T_16 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_20; // @[Decoupled.scala:51:35] assign _wen_T_20 = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T; // @[Decoupled.scala:51:35] assign _valid_2_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T_4; // @[Decoupled.scala:51:35] assign _valid_2_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_24; // @[Decoupled.scala:51:35] assign _wen_T_24 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_28; // @[Decoupled.scala:51:35] assign _wen_T_28 = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T; // @[Decoupled.scala:51:35] assign _valid_3_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T_4; // @[Decoupled.scala:51:35] assign _valid_3_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_32; // @[Decoupled.scala:51:35] assign _wen_T_32 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_36; // @[Decoupled.scala:51:35] assign _wen_T_36 = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T; // @[Decoupled.scala:51:35] assign _valid_4_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T_4; // @[Decoupled.scala:51:35] assign _valid_4_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_2 = _wen_T & _wen_T_1; // @[Decoupled.scala:51:35] wire _wen_T_3 = valid_1 \| _wen_T_2; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_5 = _wen_T_4; // @[Decoupled.scala:51:35] wire _wen_T_6 = ~valid_0; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_7 = _wen_T_5 & _wen_T_6; // @[ShiftQueue.scala:31:{23,43,46}] wire wen = io_deq_ready_0 ? _wen_T_3 : _wen_T_7; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_0_T_2 = _valid_0_T & _valid_0_T_1; // @[Decoupled.scala:51:35] wire _valid_0_T_3 = valid_1 \| _valid_0_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_0_T_5 = _valid_0_T_4; // @[Decoupled.scala:51:35] wire _valid_0_T_6 = _valid_0_T_5 \| valid_0; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_0_T_7 = io_deq_ready_0 ? _valid_0_T_3 : _valid_0_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_1_btb_cfiType = valid_2 ? elts_2_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_taken = valid_2 ? elts_2_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_1_btb_mask = valid_2 ? elts_2_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bridx = valid_2 ? elts_2_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_1_btb_target = valid_2 ? elts_2_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_1_btb_entry = valid_2 ? elts_2_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_1_btb_bht_history = valid_2 ? elts_2_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bht_value = valid_2 ? elts_2_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_1_pc = valid_2 ? elts_2_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_1_data = valid_2 ? elts_2_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_1_mask = valid_2 ? elts_2_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_pf_inst = valid_2 ? elts_2_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_gf_inst = valid_2 & elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_1_xcpt_ae_inst = valid_2 ? elts_2_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_replay = valid_2 ? elts_2_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_10 = _wen_T_8 & _wen_T_9; // @[Decoupled.scala:51:35] wire _wen_T_11 = valid_2 \| _wen_T_10; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_13 = _wen_T_12 & valid_0; // @[Decoupled.scala:51:35] wire _wen_T_14 = ~valid_1; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_15 = _wen_T_13 & _wen_T_14; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_1 = io_deq_ready_0 ? _wen_T_11 : _wen_T_15; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_1_T_2 = _valid_1_T & _valid_1_T_1; // @[Decoupled.scala:51:35] wire _valid_1_T_3 = valid_2 \| _valid_1_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_1_T_5 = _valid_1_T_4 & valid_0; // @[Decoupled.scala:51:35] wire _valid_1_T_6 = _valid_1_T_5 \| valid_1; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_1_T_7 = io_deq_ready_0 ? _valid_1_T_3 : _valid_1_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_2_btb_cfiType = valid_3 ? elts_3_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_taken = valid_3 ? elts_3_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_2_btb_mask = valid_3 ? elts_3_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bridx = valid_3 ? elts_3_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_2_btb_target = valid_3 ? elts_3_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_2_btb_entry = valid_3 ? elts_3_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_2_btb_bht_history = valid_3 ? elts_3_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bht_value = valid_3 ? elts_3_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_2_pc = valid_3 ? elts_3_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_2_data = valid_3 ? elts_3_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_2_mask = valid_3 ? elts_3_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_pf_inst = valid_3 ? elts_3_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_gf_inst = valid_3 & elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_2_xcpt_ae_inst = valid_3 ? elts_3_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_replay = valid_3 ? elts_3_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_18 = _wen_T_16 & _wen_T_17; // @[Decoupled.scala:51:35] wire _wen_T_19 = valid_3 \| _wen_T_18; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_21 = _wen_T_20 & valid_1; // @[Decoupled.scala:51:35] wire _wen_T_22 = ~valid_2; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_23 = _wen_T_21 & _wen_T_22; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_2 = io_deq_ready_0 ? _wen_T_19 : _wen_T_23; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_2_T_2 = _valid_2_T & _valid_2_T_1; // @[Decoupled.scala:51:35] wire _valid_2_T_3 = valid_3 \| _valid_2_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_2_T_5 = _valid_2_T_4 & valid_1; // @[Decoupled.scala:51:35] wire _valid_2_T_6 = _valid_2_T_5 \| valid_2; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_2_T_7 = io_deq_ready_0 ? _valid_2_T_3 : _valid_2_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_3_btb_cfiType = valid_4 ? elts_4_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_taken = valid_4 ? elts_4_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_btb_mask = valid_4 ? elts_4_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bridx = valid_4 ? elts_4_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_3_btb_target = valid_4 ? elts_4_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_3_btb_entry = valid_4 ? elts_4_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_3_btb_bht_history = valid_4 ? elts_4_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bht_value = valid_4 ? elts_4_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_3_pc = valid_4 ? elts_4_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_3_data = valid_4 ? elts_4_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_mask = valid_4 ? elts_4_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_pf_inst = valid_4 ? elts_4_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_gf_inst = valid_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_3_xcpt_ae_inst = valid_4 ? elts_4_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_replay = valid_4 ? elts_4_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_26 = _wen_T_24 & _wen_T_25; // @[Decoupled.scala:51:35] wire _wen_T_27 = valid_4 \| _wen_T_26; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_29 = _wen_T_28 & valid_2; // @[Decoupled.scala:51:35] wire _wen_T_30 = ~valid_3; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_31 = _wen_T_29 & _wen_T_30; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_3 = io_deq_ready_0 ? _wen_T_27 : _wen_T_31; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_3_T_2 = _valid_3_T & _valid_3_T_1; // @[Decoupled.scala:51:35] wire _valid_3_T_3 = valid_4 \| _valid_3_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_3_T_5 = _valid_3_T_4 & valid_2; // @[Decoupled.scala:51:35] wire _valid_3_T_6 = _valid_3_T_5 \| valid_3; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_3_T_7 = io_deq_ready_0 ? _valid_3_T_3 : _valid_3_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire _wen_T_34 = _wen_T_32 & _wen_T_33; // @[Decoupled.scala:51:35] wire _wen_T_35 = _wen_T_34; // @[ShiftQueue.scala:30:{28,43}] wire _wen_T_37 = _wen_T_36 & valid_3; // @[Decoupled.scala:51:35] wire _wen_T_38 = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_39 = _wen_T_37 & _wen_T_38; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_4 = io_deq_ready_0 ? _wen_T_35 : _wen_T_39; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_4_T_2 = _valid_4_T & _valid_4_T_1; // @[Decoupled.scala:51:35] wire _valid_4_T_3 = _valid_4_T_2; // @[ShiftQueue.scala:36:{28,43}] wire _valid_4_T_5 = _valid_4_T_4 & valid_3; // @[Decoupled.scala:51:35] wire _valid_4_T_6 = _valid_4_T_5 \| valid_4; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_4_T_7 = io_deq_ready_0 ? _valid_4_T_3 : _valid_4_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] assign _io_enq_ready_T = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46, :40:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[ShiftQueue.scala:12:7, :40:19] assign io_deq_valid_0 = io_enq_valid_0 \| valid_0; // @[ShiftQueue.scala:12:7, :21:30, :41:16, :45:{25,40}] assign io_deq_bits_btb_cfiType_0 = valid_0 ? elts_0_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_taken_0 = valid_0 ? elts_0_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_mask_0 = valid_0 ? elts_0_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bridx_0 = valid_0 ? elts_0_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_target_0 = valid_0 ? elts_0_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_entry_0 = valid_0 ? elts_0_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_history_0 = valid_0 ? elts_0_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_value_0 = valid_0 ? elts_0_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_pc_0 = valid_0 ? elts_0_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_data_0 = valid_0 ? elts_0_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_mask_0 = valid_0 ? elts_0_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_pf_inst_0 = valid_0 ? elts_0_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_gf_inst_0 = valid_0 & elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_ae_inst_0 = valid_0 ? elts_0_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_replay_0 = valid_0 ? elts_0_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] wire [1:0] io_mask_lo = {valid_1, valid_0}; // @[ShiftQueue.scala:21:30, :53:20] wire [1:0] io_mask_hi_hi = {valid_4, valid_3}; // @[ShiftQueue.scala:21:30, :53:20] wire [2:0] io_mask_hi = {io_mask_hi_hi, valid_2}; // @[ShiftQueue.scala:21:30, :53:20] assign _io_mask_T = {io_mask_hi, io_mask_lo}; // @[ShiftQueue.scala:53:20] assign io_mask_0 = _io_mask_T; // @[ShiftQueue.scala:12:7, :53:20] wire _io_count_T = io_mask_0[0]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_1 = io_mask_0[1]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_2 = io_mask_0[2]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_3 = io_mask_0[3]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_4 = io_mask_0[4]; // @[ShiftQueue.scala:12:7, :54:23] wire [1:0] _io_count_T_5 = {1'h0, _io_count_T} + {1'h0, _io_count_T_1}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_6 = _io_count_T_5; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_7 = {1'h0, _io_count_T_3} + {1'h0, _io_count_T_4}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_8 = _io_count_T_7; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_9 = {2'h0, _io_count_T_2} + {1'h0, _io_count_T_8}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_10 = _io_count_T_9[1:0]; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_11 = {1'h0, _io_count_T_6} + {1'h0, _io_count_T_10}; // @[ShiftQueue.scala:54:23] assign _io_count_T_12 = _io_count_T_11; // @[ShiftQueue.scala:54:23] assign io_count = _io_count_T_12; // @[ShiftQueue.scala:12:7, :54:23] always @(posedge clock) begin // @[ShiftQueue.scala:12:7] if (reset) begin // @[ShiftQueue.scala:12:7] valid_0 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_1 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_2 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_3 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_4 <= 1'h0; // @[ShiftQueue.scala:21:30] end else begin // @[ShiftQueue.scala:12:7] valid_0 <= _valid_0_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_1 <= _valid_1_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_2 <= _valid_2_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_3 <= _valid_3_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_4 <= _valid_4_T_7; // @[ShiftQueue.scala:21:30, :35:10] end if (wen) begin // @[ShiftQueue.scala:29:10] elts_0_btb_cfiType <= wdata_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_taken <= wdata_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_mask <= wdata_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bridx <= wdata_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_target <= wdata_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_entry <= wdata_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_history <= wdata_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_value <= wdata_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_0_pc <= wdata_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_0_data <= wdata_data; // @[ShiftQueue.scala:22:25, :27:57] elts_0_mask <= wdata_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_pf_inst <= wdata_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_gf_inst <= wdata_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_ae_inst <= wdata_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_replay <= wdata_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_1) begin // @[ShiftQueue.scala:29:10] elts_1_btb_cfiType <= wdata_1_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_taken <= wdata_1_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_mask <= wdata_1_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bridx <= wdata_1_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_target <= wdata_1_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_entry <= wdata_1_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_history <= wdata_1_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_value <= wdata_1_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_1_pc <= wdata_1_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_1_data <= wdata_1_data; // @[ShiftQueue.scala:22:25, :27:57] elts_1_mask <= wdata_1_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_pf_inst <= wdata_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_gf_inst <= wdata_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_ae_inst <= wdata_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_replay <= wdata_1_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_2) begin // @[ShiftQueue.scala:29:10] elts_2_btb_cfiType <= wdata_2_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_taken <= wdata_2_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_mask <= wdata_2_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bridx <= wdata_2_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_target <= wdata_2_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_entry <= wdata_2_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_history <= wdata_2_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_value <= wdata_2_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_2_pc <= wdata_2_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_2_data <= wdata_2_data; // @[ShiftQueue.scala:22:25, :27:57] elts_2_mask <= wdata_2_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_pf_inst <= wdata_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_gf_inst <= wdata_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_ae_inst <= wdata_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_replay <= wdata_2_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_3) begin // @[ShiftQueue.scala:29:10] elts_3_btb_cfiType <= wdata_3_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_taken <= wdata_3_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_mask <= wdata_3_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bridx <= wdata_3_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_target <= wdata_3_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_entry <= wdata_3_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_history <= wdata_3_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_value <= wdata_3_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_3_pc <= wdata_3_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_3_data <= wdata_3_data; // @[ShiftQueue.scala:22:25, :27:57] elts_3_mask <= wdata_3_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_pf_inst <= wdata_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_gf_inst <= wdata_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_ae_inst <= wdata_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_replay <= wdata_3_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_4) begin // @[ShiftQueue.scala:29:10] elts_4_btb_cfiType <= io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_taken <= io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_mask <= io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bridx <= io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_target <= io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_entry <= io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_history <= io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_value <= io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_pc <= io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_data <= io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_mask <= io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_pf_inst <= io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_replay <= io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :22:25] end elts_4_xcpt_gf_inst <= ~wen_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :29:10, :32:{16,26}] always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[ShiftQueue.scala:12:7] assign io_deq_valid = io_deq_valid_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_cfiType = io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_taken = io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_mask = io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bridx = io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_target = io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_entry = io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_history = io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_value = io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_pc = io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_pf_inst = io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_gf_inst = io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_ae_inst = io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_replay = io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] assign io_mask = io_mask_0; // @[ShiftQueue.scala:12:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_18 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) when io.en : connect reg, io.d connect io.q, reg	module AsyncResetRegVec_w1_i0_18( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module ALU_3 : input clock : Clock input reset : Reset output io : { flip dw : UInt<1>, flip fn : UInt<5>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>} node _in2_inv_T = bits(io.fn, 3, 3) node _in2_inv_T_1 = not(io.in2) node in2_inv = mux(_in2_inv_T, _in2_inv_T_1, io.in2) node in1_xor_in2 = xor(io.in1, in2_inv) node in1_and_in2 = and(io.in1, in2_inv) node _io_adder_out_T = add(io.in1, in2_inv) node _io_adder_out_T_1 = tail(_io_adder_out_T, 1) node _io_adder_out_T_2 = bits(io.fn, 3, 3) node _io_adder_out_T_3 = add(_io_adder_out_T_1, _io_adder_out_T_2) node _io_adder_out_T_4 = tail(_io_adder_out_T_3, 1) connect io.adder_out, _io_adder_out_T_4 node _slt_T = bits(io.in1, 63, 63) node _slt_T_1 = bits(io.in2, 63, 63) node _slt_T_2 = eq(_slt_T, _slt_T_1) node _slt_T_3 = bits(io.adder_out, 63, 63) node _slt_T_4 = bits(io.fn, 1, 1) node _slt_T_5 = bits(io.in2, 63, 63) node _slt_T_6 = bits(io.in1, 63, 63) node _slt_T_7 = mux(_slt_T_4, _slt_T_5, _slt_T_6) node slt = mux(_slt_T_2, _slt_T_3, _slt_T_7) node _io_cmp_out_T = bits(io.fn, 0, 0) node _io_cmp_out_T_1 = bits(io.fn, 3, 3) node _io_cmp_out_T_2 = eq(_io_cmp_out_T_1, UInt<1>(0h0)) node _io_cmp_out_T_3 = eq(in1_xor_in2, UInt<1>(0h0)) node _io_cmp_out_T_4 = mux(_io_cmp_out_T_2, _io_cmp_out_T_3, slt) node _io_cmp_out_T_5 = xor(_io_cmp_out_T, _io_cmp_out_T_4) connect io.cmp_out, _io_cmp_out_T_5 node _shin_hi_32_T = bits(io.fn, 3, 3) node _shin_hi_32_T_1 = bits(io.in1, 31, 31) node _shin_hi_32_T_2 = and(_shin_hi_32_T, _shin_hi_32_T_1) node shin_hi_32 = mux(_shin_hi_32_T_2, UInt<32>(0hffffffff), UInt<32>(0h0)) node _shin_hi_T = eq(io.dw, UInt<1>(0h1)) node _shin_hi_T_1 = bits(io.in1, 63, 32) node shin_hi = mux(_shin_hi_T, _shin_hi_T_1, shin_hi_32) node _shamt_T = bits(io.in2, 5, 5) node _shamt_T_1 = eq(io.dw, UInt<1>(0h1)) node _shamt_T_2 = and(_shamt_T, _shamt_T_1) node _shamt_T_3 = bits(io.in2, 4, 0) node shamt = cat(_shamt_T_2, _shamt_T_3) node _T = bits(io.in1, 31, 0) node shin_r = cat(shin_hi, _T) node _shin_T = eq(io.fn, UInt<3>(0h5)) node _shin_T_1 = eq(io.fn, UInt<4>(0hb)) node _shin_T_2 = eq(io.fn, UInt<5>(0h12)) node _shin_T_3 = eq(io.fn, UInt<5>(0h13)) node _shin_T_4 = or(_shin_T, _shin_T_1) node _shin_T_5 = or(_shin_T_4, _shin_T_2) node _shin_T_6 = or(_shin_T_5, _shin_T_3) node _shin_T_7 = eq(_shin_T_6, UInt<1>(0h0)) node _shin_T_8 = shl(UInt<32>(0hffffffff), 32) node _shin_T_9 = xor(UInt<64>(0hffffffffffffffff), _shin_T_8) node _shin_T_10 = shr(shin_r, 32) node _shin_T_11 = and(_shin_T_10, _shin_T_9) node _shin_T_12 = bits(shin_r, 31, 0) node _shin_T_13 = shl(_shin_T_12, 32) node _shin_T_14 = not(_shin_T_9) node _shin_T_15 = and(_shin_T_13, _shin_T_14) node _shin_T_16 = or(_shin_T_11, _shin_T_15) node _shin_T_17 = bits(_shin_T_9, 47, 0) node _shin_T_18 = shl(_shin_T_17, 16) node _shin_T_19 = xor(_shin_T_9, _shin_T_18) node _shin_T_20 = shr(_shin_T_16, 16) node _shin_T_21 = and(_shin_T_20, _shin_T_19) node _shin_T_22 = bits(_shin_T_16, 47, 0) node _shin_T_23 = shl(_shin_T_22, 16) node _shin_T_24 = not(_shin_T_19) node _shin_T_25 = and(_shin_T_23, _shin_T_24) node _shin_T_26 = or(_shin_T_21, _shin_T_25) node _shin_T_27 = bits(_shin_T_19, 55, 0) node _shin_T_28 = shl(_shin_T_27, 8) node _shin_T_29 = xor(_shin_T_19, _shin_T_28) node _shin_T_30 = shr(_shin_T_26, 8) node _shin_T_31 = and(_shin_T_30, _shin_T_29) node _shin_T_32 = bits(_shin_T_26, 55, 0) node _shin_T_33 = shl(_shin_T_32, 8) node _shin_T_34 = not(_shin_T_29) node _shin_T_35 = and(_shin_T_33, _shin_T_34) node _shin_T_36 = or(_shin_T_31, _shin_T_35) node _shin_T_37 = bits(_shin_T_29, 59, 0) node _shin_T_38 = shl(_shin_T_37, 4) node _shin_T_39 = xor(_shin_T_29, _shin_T_38) node _shin_T_40 = shr(_shin_T_36, 4) node _shin_T_41 = and(_shin_T_40, _shin_T_39) node _shin_T_42 = bits(_shin_T_36, 59, 0) node _shin_T_43 = shl(_shin_T_42, 4) node _shin_T_44 = not(_shin_T_39) node _shin_T_45 = and(_shin_T_43, _shin_T_44) node _shin_T_46 = or(_shin_T_41, _shin_T_45) node _shin_T_47 = bits(_shin_T_39, 61, 0) node _shin_T_48 = shl(_shin_T_47, 2) node _shin_T_49 = xor(_shin_T_39, _shin_T_48) node _shin_T_50 = shr(_shin_T_46, 2) node _shin_T_51 = and(_shin_T_50, _shin_T_49) node _shin_T_52 = bits(_shin_T_46, 61, 0) node _shin_T_53 = shl(_shin_T_52, 2) node _shin_T_54 = not(_shin_T_49) node _shin_T_55 = and(_shin_T_53, _shin_T_54) node _shin_T_56 = or(_shin_T_51, _shin_T_55) node _shin_T_57 = bits(_shin_T_49, 62, 0) node _shin_T_58 = shl(_shin_T_57, 1) node _shin_T_59 = xor(_shin_T_49, _shin_T_58) node _shin_T_60 = shr(_shin_T_56, 1) node _shin_T_61 = and(_shin_T_60, _shin_T_59) node _shin_T_62 = bits(_shin_T_56, 62, 0) node _shin_T_63 = shl(_shin_T_62, 1) node _shin_T_64 = not(_shin_T_59) node _shin_T_65 = and(_shin_T_63, _shin_T_64) node _shin_T_66 = or(_shin_T_61, _shin_T_65) node shin = mux(_shin_T_7, _shin_T_66, shin_r) node _shout_r_T = bits(io.fn, 3, 3) node _shout_r_T_1 = bits(shin, 63, 63) node _shout_r_T_2 = and(_shout_r_T, _shout_r_T_1) node _shout_r_T_3 = cat(_shout_r_T_2, shin) node _shout_r_T_4 = asSInt(_shout_r_T_3) node _shout_r_T_5 = dshr(_shout_r_T_4, shamt) node shout_r = bits(_shout_r_T_5, 63, 0) node _shout_l_T = shl(UInt<32>(0hffffffff), 32) node _shout_l_T_1 = xor(UInt<64>(0hffffffffffffffff), _shout_l_T) node _shout_l_T_2 = shr(shout_r, 32) node _shout_l_T_3 = and(_shout_l_T_2, _shout_l_T_1) node _shout_l_T_4 = bits(shout_r, 31, 0) node _shout_l_T_5 = shl(_shout_l_T_4, 32) node _shout_l_T_6 = not(_shout_l_T_1) node _shout_l_T_7 = and(_shout_l_T_5, _shout_l_T_6) node _shout_l_T_8 = or(_shout_l_T_3, _shout_l_T_7) node _shout_l_T_9 = bits(_shout_l_T_1, 47, 0) node _shout_l_T_10 = shl(_shout_l_T_9, 16) node _shout_l_T_11 = xor(_shout_l_T_1, _shout_l_T_10) node _shout_l_T_12 = shr(_shout_l_T_8, 16) node _shout_l_T_13 = and(_shout_l_T_12, _shout_l_T_11) node _shout_l_T_14 = bits(_shout_l_T_8, 47, 0) node _shout_l_T_15 = shl(_shout_l_T_14, 16) node _shout_l_T_16 = not(_shout_l_T_11) node _shout_l_T_17 = and(_shout_l_T_15, _shout_l_T_16) node _shout_l_T_18 = or(_shout_l_T_13, _shout_l_T_17) node _shout_l_T_19 = bits(_shout_l_T_11, 55, 0) node _shout_l_T_20 = shl(_shout_l_T_19, 8) node _shout_l_T_21 = xor(_shout_l_T_11, _shout_l_T_20) node _shout_l_T_22 = shr(_shout_l_T_18, 8) node _shout_l_T_23 = and(_shout_l_T_22, _shout_l_T_21) node _shout_l_T_24 = bits(_shout_l_T_18, 55, 0) node _shout_l_T_25 = shl(_shout_l_T_24, 8) node _shout_l_T_26 = not(_shout_l_T_21) node _shout_l_T_27 = and(_shout_l_T_25, _shout_l_T_26) node _shout_l_T_28 = or(_shout_l_T_23, _shout_l_T_27) node _shout_l_T_29 = bits(_shout_l_T_21, 59, 0) node _shout_l_T_30 = shl(_shout_l_T_29, 4) node _shout_l_T_31 = xor(_shout_l_T_21, _shout_l_T_30) node _shout_l_T_32 = shr(_shout_l_T_28, 4) node _shout_l_T_33 = and(_shout_l_T_32, _shout_l_T_31) node _shout_l_T_34 = bits(_shout_l_T_28, 59, 0) node _shout_l_T_35 = shl(_shout_l_T_34, 4) node _shout_l_T_36 = not(_shout_l_T_31) node _shout_l_T_37 = and(_shout_l_T_35, _shout_l_T_36) node _shout_l_T_38 = or(_shout_l_T_33, _shout_l_T_37) node _shout_l_T_39 = bits(_shout_l_T_31, 61, 0) node _shout_l_T_40 = shl(_shout_l_T_39, 2) node _shout_l_T_41 = xor(_shout_l_T_31, _shout_l_T_40) node _shout_l_T_42 = shr(_shout_l_T_38, 2) node _shout_l_T_43 = and(_shout_l_T_42, _shout_l_T_41) node _shout_l_T_44 = bits(_shout_l_T_38, 61, 0) node _shout_l_T_45 = shl(_shout_l_T_44, 2) node _shout_l_T_46 = not(_shout_l_T_41) node _shout_l_T_47 = and(_shout_l_T_45, _shout_l_T_46) node _shout_l_T_48 = or(_shout_l_T_43, _shout_l_T_47) node _shout_l_T_49 = bits(_shout_l_T_41, 62, 0) node _shout_l_T_50 = shl(_shout_l_T_49, 1) node _shout_l_T_51 = xor(_shout_l_T_41, _shout_l_T_50) node _shout_l_T_52 = shr(_shout_l_T_48, 1) node _shout_l_T_53 = and(_shout_l_T_52, _shout_l_T_51) node _shout_l_T_54 = bits(_shout_l_T_48, 62, 0) node _shout_l_T_55 = shl(_shout_l_T_54, 1) node _shout_l_T_56 = not(_shout_l_T_51) node _shout_l_T_57 = and(_shout_l_T_55, _shout_l_T_56) node shout_l = or(_shout_l_T_53, _shout_l_T_57) node _shout_T = eq(io.fn, UInt<3>(0h5)) node _shout_T_1 = eq(io.fn, UInt<4>(0hb)) node _shout_T_2 = or(_shout_T, _shout_T_1) node _shout_T_3 = eq(io.fn, UInt<5>(0h13)) node _shout_T_4 = or(_shout_T_2, _shout_T_3) node _shout_T_5 = mux(_shout_T_4, shout_r, UInt<1>(0h0)) node _shout_T_6 = eq(io.fn, UInt<1>(0h1)) node _shout_T_7 = mux(_shout_T_6, shout_l, UInt<1>(0h0)) node shout = or(_shout_T_5, _shout_T_7) node in2_not_zero = orr(io.in2) node _logic_T = eq(io.fn, UInt<3>(0h4)) node _logic_T_1 = eq(io.fn, UInt<3>(0h6)) node _logic_T_2 = or(_logic_T, _logic_T_1) node _logic_T_3 = eq(io.fn, UInt<5>(0h19)) node _logic_T_4 = or(_logic_T_2, _logic_T_3) node _logic_T_5 = eq(io.fn, UInt<5>(0h1a)) node _logic_T_6 = or(_logic_T_4, _logic_T_5) node _logic_T_7 = mux(_logic_T_6, in1_xor_in2, UInt<1>(0h0)) node _logic_T_8 = eq(io.fn, UInt<3>(0h6)) node _logic_T_9 = eq(io.fn, UInt<3>(0h7)) node _logic_T_10 = or(_logic_T_8, _logic_T_9) node _logic_T_11 = eq(io.fn, UInt<5>(0h19)) node _logic_T_12 = or(_logic_T_10, _logic_T_11) node _logic_T_13 = eq(io.fn, UInt<5>(0h18)) node _logic_T_14 = or(_logic_T_12, _logic_T_13) node _logic_T_15 = mux(_logic_T_14, in1_and_in2, UInt<1>(0h0)) node logic = or(_logic_T_7, _logic_T_15) node _bext_mask_T = eq(io.fn, UInt<5>(0h13)) node _bext_mask_T_1 = and(UInt<1>(0h0), _bext_mask_T) node _bext_mask_T_2 = not(UInt<64>(0h0)) node bext_mask = mux(_bext_mask_T_1, UInt<1>(0h1), _bext_mask_T_2) node _shift_logic_T = geq(io.fn, UInt<4>(0hc)) node _shift_logic_T_1 = leq(io.fn, UInt<4>(0hf)) node _shift_logic_T_2 = and(_shift_logic_T, _shift_logic_T_1) node _shift_logic_T_3 = and(_shift_logic_T_2, slt) node _shift_logic_T_4 = or(_shift_logic_T_3, logic) node _shift_logic_T_5 = and(shout, bext_mask) node shift_logic = or(_shift_logic_T_4, _shift_logic_T_5) node _tz_in_T = eq(io.dw, UInt<1>(0h0)) node _tz_in_T_1 = bits(io.in2, 0, 0) node _tz_in_T_2 = eq(_tz_in_T_1, UInt<1>(0h0)) node _tz_in_T_3 = cat(_tz_in_T, _tz_in_T_2) node _tz_in_T_4 = shl(UInt<32>(0hffffffff), 32) node _tz_in_T_5 = xor(UInt<64>(0hffffffffffffffff), _tz_in_T_4) node _tz_in_T_6 = shr(io.in1, 32) node _tz_in_T_7 = and(_tz_in_T_6, _tz_in_T_5) node _tz_in_T_8 = bits(io.in1, 31, 0) node _tz_in_T_9 = shl(_tz_in_T_8, 32) node _tz_in_T_10 = not(_tz_in_T_5) node _tz_in_T_11 = and(_tz_in_T_9, _tz_in_T_10) node _tz_in_T_12 = or(_tz_in_T_7, _tz_in_T_11) node _tz_in_T_13 = bits(_tz_in_T_5, 47, 0) node _tz_in_T_14 = shl(_tz_in_T_13, 16) node _tz_in_T_15 = xor(_tz_in_T_5, _tz_in_T_14) node _tz_in_T_16 = shr(_tz_in_T_12, 16) node _tz_in_T_17 = and(_tz_in_T_16, _tz_in_T_15) node _tz_in_T_18 = bits(_tz_in_T_12, 47, 0) node _tz_in_T_19 = shl(_tz_in_T_18, 16) node _tz_in_T_20 = not(_tz_in_T_15) node _tz_in_T_21 = and(_tz_in_T_19, _tz_in_T_20) node _tz_in_T_22 = or(_tz_in_T_17, _tz_in_T_21) node _tz_in_T_23 = bits(_tz_in_T_15, 55, 0) node _tz_in_T_24 = shl(_tz_in_T_23, 8) node _tz_in_T_25 = xor(_tz_in_T_15, _tz_in_T_24) node _tz_in_T_26 = shr(_tz_in_T_22, 8) node _tz_in_T_27 = and(_tz_in_T_26, _tz_in_T_25) node _tz_in_T_28 = bits(_tz_in_T_22, 55, 0) node _tz_in_T_29 = shl(_tz_in_T_28, 8) node _tz_in_T_30 = not(_tz_in_T_25) node _tz_in_T_31 = and(_tz_in_T_29, _tz_in_T_30) node _tz_in_T_32 = or(_tz_in_T_27, _tz_in_T_31) node _tz_in_T_33 = bits(_tz_in_T_25, 59, 0) node _tz_in_T_34 = shl(_tz_in_T_33, 4) node _tz_in_T_35 = xor(_tz_in_T_25, _tz_in_T_34) node _tz_in_T_36 = shr(_tz_in_T_32, 4) node _tz_in_T_37 = and(_tz_in_T_36, _tz_in_T_35) node _tz_in_T_38 = bits(_tz_in_T_32, 59, 0) node _tz_in_T_39 = shl(_tz_in_T_38, 4) node _tz_in_T_40 = not(_tz_in_T_35) node _tz_in_T_41 = and(_tz_in_T_39, _tz_in_T_40) node _tz_in_T_42 = or(_tz_in_T_37, _tz_in_T_41) node _tz_in_T_43 = bits(_tz_in_T_35, 61, 0) node _tz_in_T_44 = shl(_tz_in_T_43, 2) node _tz_in_T_45 = xor(_tz_in_T_35, _tz_in_T_44) node _tz_in_T_46 = shr(_tz_in_T_42, 2) node _tz_in_T_47 = and(_tz_in_T_46, _tz_in_T_45) node _tz_in_T_48 = bits(_tz_in_T_42, 61, 0) node _tz_in_T_49 = shl(_tz_in_T_48, 2) node _tz_in_T_50 = not(_tz_in_T_45) node _tz_in_T_51 = and(_tz_in_T_49, _tz_in_T_50) node _tz_in_T_52 = or(_tz_in_T_47, _tz_in_T_51) node _tz_in_T_53 = bits(_tz_in_T_45, 62, 0) node _tz_in_T_54 = shl(_tz_in_T_53, 1) node _tz_in_T_55 = xor(_tz_in_T_45, _tz_in_T_54) node _tz_in_T_56 = shr(_tz_in_T_52, 1) node _tz_in_T_57 = and(_tz_in_T_56, _tz_in_T_55) node _tz_in_T_58 = bits(_tz_in_T_52, 62, 0) node _tz_in_T_59 = shl(_tz_in_T_58, 1) node _tz_in_T_60 = not(_tz_in_T_55) node _tz_in_T_61 = and(_tz_in_T_59, _tz_in_T_60) node _tz_in_T_62 = or(_tz_in_T_57, _tz_in_T_61) node _tz_in_T_63 = bits(io.in1, 31, 0) node _tz_in_T_64 = cat(UInt<1>(0h1), _tz_in_T_63) node _tz_in_T_65 = bits(io.in1, 31, 0) node _tz_in_T_66 = shl(UInt<16>(0hffff), 16) node _tz_in_T_67 = xor(UInt<32>(0hffffffff), _tz_in_T_66) node _tz_in_T_68 = shr(_tz_in_T_65, 16) node _tz_in_T_69 = and(_tz_in_T_68, _tz_in_T_67) node _tz_in_T_70 = bits(_tz_in_T_65, 15, 0) node _tz_in_T_71 = shl(_tz_in_T_70, 16) node _tz_in_T_72 = not(_tz_in_T_67) node _tz_in_T_73 = and(_tz_in_T_71, _tz_in_T_72) node _tz_in_T_74 = or(_tz_in_T_69, _tz_in_T_73) node _tz_in_T_75 = bits(_tz_in_T_67, 23, 0) node _tz_in_T_76 = shl(_tz_in_T_75, 8) node _tz_in_T_77 = xor(_tz_in_T_67, _tz_in_T_76) node _tz_in_T_78 = shr(_tz_in_T_74, 8) node _tz_in_T_79 = and(_tz_in_T_78, _tz_in_T_77) node _tz_in_T_80 = bits(_tz_in_T_74, 23, 0) node _tz_in_T_81 = shl(_tz_in_T_80, 8) node _tz_in_T_82 = not(_tz_in_T_77) node _tz_in_T_83 = and(_tz_in_T_81, _tz_in_T_82) node _tz_in_T_84 = or(_tz_in_T_79, _tz_in_T_83) node _tz_in_T_85 = bits(_tz_in_T_77, 27, 0) node _tz_in_T_86 = shl(_tz_in_T_85, 4) node _tz_in_T_87 = xor(_tz_in_T_77, _tz_in_T_86) node _tz_in_T_88 = shr(_tz_in_T_84, 4) node _tz_in_T_89 = and(_tz_in_T_88, _tz_in_T_87) node _tz_in_T_90 = bits(_tz_in_T_84, 27, 0) node _tz_in_T_91 = shl(_tz_in_T_90, 4) node _tz_in_T_92 = not(_tz_in_T_87) node _tz_in_T_93 = and(_tz_in_T_91, _tz_in_T_92) node _tz_in_T_94 = or(_tz_in_T_89, _tz_in_T_93) node _tz_in_T_95 = bits(_tz_in_T_87, 29, 0) node _tz_in_T_96 = shl(_tz_in_T_95, 2) node _tz_in_T_97 = xor(_tz_in_T_87, _tz_in_T_96) node _tz_in_T_98 = shr(_tz_in_T_94, 2) node _tz_in_T_99 = and(_tz_in_T_98, _tz_in_T_97) node _tz_in_T_100 = bits(_tz_in_T_94, 29, 0) node _tz_in_T_101 = shl(_tz_in_T_100, 2) node _tz_in_T_102 = not(_tz_in_T_97) node _tz_in_T_103 = and(_tz_in_T_101, _tz_in_T_102) node _tz_in_T_104 = or(_tz_in_T_99, _tz_in_T_103) node _tz_in_T_105 = bits(_tz_in_T_97, 30, 0) node _tz_in_T_106 = shl(_tz_in_T_105, 1) node _tz_in_T_107 = xor(_tz_in_T_97, _tz_in_T_106) node _tz_in_T_108 = shr(_tz_in_T_104, 1) node _tz_in_T_109 = and(_tz_in_T_108, _tz_in_T_107) node _tz_in_T_110 = bits(_tz_in_T_104, 30, 0) node _tz_in_T_111 = shl(_tz_in_T_110, 1) node _tz_in_T_112 = not(_tz_in_T_107) node _tz_in_T_113 = and(_tz_in_T_111, _tz_in_T_112) node _tz_in_T_114 = or(_tz_in_T_109, _tz_in_T_113) node _tz_in_T_115 = cat(UInt<1>(0h1), _tz_in_T_114) node _tz_in_T_116 = eq(UInt<1>(0h1), _tz_in_T_3) node _tz_in_T_117 = mux(_tz_in_T_116, _tz_in_T_62, io.in1) node _tz_in_T_118 = eq(UInt<2>(0h2), _tz_in_T_3) node _tz_in_T_119 = mux(_tz_in_T_118, _tz_in_T_64, _tz_in_T_117) node _tz_in_T_120 = eq(UInt<2>(0h3), _tz_in_T_3) node tz_in = mux(_tz_in_T_120, _tz_in_T_115, _tz_in_T_119) node _popc_in_T = bits(io.in2, 1, 1) node _popc_in_T_1 = eq(io.dw, UInt<1>(0h0)) node _popc_in_T_2 = bits(io.in1, 31, 0) node _popc_in_T_3 = mux(_popc_in_T_1, _popc_in_T_2, io.in1) node _popc_in_T_4 = cat(UInt<1>(0h1), tz_in) node _popc_in_T_5 = bits(_popc_in_T_4, 0, 0) node _popc_in_T_6 = bits(_popc_in_T_4, 1, 1) node _popc_in_T_7 = bits(_popc_in_T_4, 2, 2) node _popc_in_T_8 = bits(_popc_in_T_4, 3, 3) node _popc_in_T_9 = bits(_popc_in_T_4, 4, 4) node _popc_in_T_10 = bits(_popc_in_T_4, 5, 5) node _popc_in_T_11 = bits(_popc_in_T_4, 6, 6) node _popc_in_T_12 = bits(_popc_in_T_4, 7, 7) node _popc_in_T_13 = bits(_popc_in_T_4, 8, 8) node _popc_in_T_14 = bits(_popc_in_T_4, 9, 9) node _popc_in_T_15 = bits(_popc_in_T_4, 10, 10) node _popc_in_T_16 = bits(_popc_in_T_4, 11, 11) node _popc_in_T_17 = bits(_popc_in_T_4, 12, 12) node _popc_in_T_18 = bits(_popc_in_T_4, 13, 13) node _popc_in_T_19 = bits(_popc_in_T_4, 14, 14) node _popc_in_T_20 = bits(_popc_in_T_4, 15, 15) node _popc_in_T_21 = bits(_popc_in_T_4, 16, 16) node _popc_in_T_22 = bits(_popc_in_T_4, 17, 17) node _popc_in_T_23 = bits(_popc_in_T_4, 18, 18) node _popc_in_T_24 = bits(_popc_in_T_4, 19, 19) node _popc_in_T_25 = bits(_popc_in_T_4, 20, 20) node _popc_in_T_26 = bits(_popc_in_T_4, 21, 21) node _popc_in_T_27 = bits(_popc_in_T_4, 22, 22) node _popc_in_T_28 = bits(_popc_in_T_4, 23, 23) node _popc_in_T_29 = bits(_popc_in_T_4, 24, 24) node _popc_in_T_30 = bits(_popc_in_T_4, 25, 25) node _popc_in_T_31 = bits(_popc_in_T_4, 26, 26) node _popc_in_T_32 = bits(_popc_in_T_4, 27, 27) node _popc_in_T_33 = bits(_popc_in_T_4, 28, 28) node _popc_in_T_34 = bits(_popc_in_T_4, 29, 29) node _popc_in_T_35 = bits(_popc_in_T_4, 30, 30) node _popc_in_T_36 = bits(_popc_in_T_4, 31, 31) node _popc_in_T_37 = bits(_popc_in_T_4, 32, 32) node _popc_in_T_38 = bits(_popc_in_T_4, 33, 33) node _popc_in_T_39 = bits(_popc_in_T_4, 34, 34) node _popc_in_T_40 = bits(_popc_in_T_4, 35, 35) node _popc_in_T_41 = bits(_popc_in_T_4, 36, 36) node _popc_in_T_42 = bits(_popc_in_T_4, 37, 37) node _popc_in_T_43 = bits(_popc_in_T_4, 38, 38) node _popc_in_T_44 = bits(_popc_in_T_4, 39, 39) node _popc_in_T_45 = bits(_popc_in_T_4, 40, 40) node _popc_in_T_46 = bits(_popc_in_T_4, 41, 41) node _popc_in_T_47 = bits(_popc_in_T_4, 42, 42) node _popc_in_T_48 = bits(_popc_in_T_4, 43, 43) node _popc_in_T_49 = bits(_popc_in_T_4, 44, 44) node _popc_in_T_50 = bits(_popc_in_T_4, 45, 45) node _popc_in_T_51 = bits(_popc_in_T_4, 46, 46) node _popc_in_T_52 = bits(_popc_in_T_4, 47, 47) node _popc_in_T_53 = bits(_popc_in_T_4, 48, 48) node _popc_in_T_54 = bits(_popc_in_T_4, 49, 49) node _popc_in_T_55 = bits(_popc_in_T_4, 50, 50) node _popc_in_T_56 = bits(_popc_in_T_4, 51, 51) node _popc_in_T_57 = bits(_popc_in_T_4, 52, 52) node _popc_in_T_58 = bits(_popc_in_T_4, 53, 53) node _popc_in_T_59 = bits(_popc_in_T_4, 54, 54) node _popc_in_T_60 = bits(_popc_in_T_4, 55, 55) node _popc_in_T_61 = bits(_popc_in_T_4, 56, 56) node _popc_in_T_62 = bits(_popc_in_T_4, 57, 57) node _popc_in_T_63 = bits(_popc_in_T_4, 58, 58) node _popc_in_T_64 = bits(_popc_in_T_4, 59, 59) node _popc_in_T_65 = bits(_popc_in_T_4, 60, 60) node _popc_in_T_66 = bits(_popc_in_T_4, 61, 61) node _popc_in_T_67 = bits(_popc_in_T_4, 62, 62) node _popc_in_T_68 = bits(_popc_in_T_4, 63, 63) node _popc_in_T_69 = bits(_popc_in_T_4, 64, 64) node _popc_in_T_70 = mux(_popc_in_T_69, UInt<65>(0h10000000000000000), UInt<65>(0h0)) node _popc_in_T_71 = mux(_popc_in_T_68, UInt<65>(0h8000000000000000), _popc_in_T_70) node _popc_in_T_72 = mux(_popc_in_T_67, UInt<65>(0h4000000000000000), _popc_in_T_71) node _popc_in_T_73 = mux(_popc_in_T_66, UInt<65>(0h2000000000000000), _popc_in_T_72) node _popc_in_T_74 = mux(_popc_in_T_65, UInt<65>(0h1000000000000000), _popc_in_T_73) node _popc_in_T_75 = mux(_popc_in_T_64, UInt<65>(0h800000000000000), _popc_in_T_74) node _popc_in_T_76 = mux(_popc_in_T_63, UInt<65>(0h400000000000000), _popc_in_T_75) node _popc_in_T_77 = mux(_popc_in_T_62, UInt<65>(0h200000000000000), _popc_in_T_76) node _popc_in_T_78 = mux(_popc_in_T_61, UInt<65>(0h100000000000000), _popc_in_T_77) node _popc_in_T_79 = mux(_popc_in_T_60, UInt<65>(0h80000000000000), _popc_in_T_78) node _popc_in_T_80 = mux(_popc_in_T_59, UInt<65>(0h40000000000000), _popc_in_T_79) node _popc_in_T_81 = mux(_popc_in_T_58, UInt<65>(0h20000000000000), _popc_in_T_80) node _popc_in_T_82 = mux(_popc_in_T_57, UInt<65>(0h10000000000000), _popc_in_T_81) node _popc_in_T_83 = mux(_popc_in_T_56, UInt<65>(0h8000000000000), _popc_in_T_82) node _popc_in_T_84 = mux(_popc_in_T_55, UInt<65>(0h4000000000000), _popc_in_T_83) node _popc_in_T_85 = mux(_popc_in_T_54, UInt<65>(0h2000000000000), _popc_in_T_84) node _popc_in_T_86 = mux(_popc_in_T_53, UInt<65>(0h1000000000000), _popc_in_T_85) node _popc_in_T_87 = mux(_popc_in_T_52, UInt<65>(0h800000000000), _popc_in_T_86) node _popc_in_T_88 = mux(_popc_in_T_51, UInt<65>(0h400000000000), _popc_in_T_87) node _popc_in_T_89 = mux(_popc_in_T_50, UInt<65>(0h200000000000), _popc_in_T_88) node _popc_in_T_90 = mux(_popc_in_T_49, UInt<65>(0h100000000000), _popc_in_T_89) node _popc_in_T_91 = mux(_popc_in_T_48, UInt<65>(0h80000000000), _popc_in_T_90) node _popc_in_T_92 = mux(_popc_in_T_47, UInt<65>(0h40000000000), _popc_in_T_91) node _popc_in_T_93 = mux(_popc_in_T_46, UInt<65>(0h20000000000), _popc_in_T_92) node _popc_in_T_94 = mux(_popc_in_T_45, UInt<65>(0h10000000000), _popc_in_T_93) node _popc_in_T_95 = mux(_popc_in_T_44, UInt<65>(0h8000000000), _popc_in_T_94) node _popc_in_T_96 = mux(_popc_in_T_43, UInt<65>(0h4000000000), _popc_in_T_95) node _popc_in_T_97 = mux(_popc_in_T_42, UInt<65>(0h2000000000), _popc_in_T_96) node _popc_in_T_98 = mux(_popc_in_T_41, UInt<65>(0h1000000000), _popc_in_T_97) node _popc_in_T_99 = mux(_popc_in_T_40, UInt<65>(0h800000000), _popc_in_T_98) node _popc_in_T_100 = mux(_popc_in_T_39, UInt<65>(0h400000000), _popc_in_T_99) node _popc_in_T_101 = mux(_popc_in_T_38, UInt<65>(0h200000000), _popc_in_T_100) node _popc_in_T_102 = mux(_popc_in_T_37, UInt<65>(0h100000000), _popc_in_T_101) node _popc_in_T_103 = mux(_popc_in_T_36, UInt<65>(0h80000000), _popc_in_T_102) node _popc_in_T_104 = mux(_popc_in_T_35, UInt<65>(0h40000000), _popc_in_T_103) node _popc_in_T_105 = mux(_popc_in_T_34, UInt<65>(0h20000000), _popc_in_T_104) node _popc_in_T_106 = mux(_popc_in_T_33, UInt<65>(0h10000000), _popc_in_T_105) node _popc_in_T_107 = mux(_popc_in_T_32, UInt<65>(0h8000000), _popc_in_T_106) node _popc_in_T_108 = mux(_popc_in_T_31, UInt<65>(0h4000000), _popc_in_T_107) node _popc_in_T_109 = mux(_popc_in_T_30, UInt<65>(0h2000000), _popc_in_T_108) node _popc_in_T_110 = mux(_popc_in_T_29, UInt<65>(0h1000000), _popc_in_T_109) node _popc_in_T_111 = mux(_popc_in_T_28, UInt<65>(0h800000), _popc_in_T_110) node _popc_in_T_112 = mux(_popc_in_T_27, UInt<65>(0h400000), _popc_in_T_111) node _popc_in_T_113 = mux(_popc_in_T_26, UInt<65>(0h200000), _popc_in_T_112) node _popc_in_T_114 = mux(_popc_in_T_25, UInt<65>(0h100000), _popc_in_T_113) node _popc_in_T_115 = mux(_popc_in_T_24, UInt<65>(0h80000), _popc_in_T_114) node _popc_in_T_116 = mux(_popc_in_T_23, UInt<65>(0h40000), _popc_in_T_115) node _popc_in_T_117 = mux(_popc_in_T_22, UInt<65>(0h20000), _popc_in_T_116) node _popc_in_T_118 = mux(_popc_in_T_21, UInt<65>(0h10000), _popc_in_T_117) node _popc_in_T_119 = mux(_popc_in_T_20, UInt<65>(0h8000), _popc_in_T_118) node _popc_in_T_120 = mux(_popc_in_T_19, UInt<65>(0h4000), _popc_in_T_119) node _popc_in_T_121 = mux(_popc_in_T_18, UInt<65>(0h2000), _popc_in_T_120) node _popc_in_T_122 = mux(_popc_in_T_17, UInt<65>(0h1000), _popc_in_T_121) node _popc_in_T_123 = mux(_popc_in_T_16, UInt<65>(0h800), _popc_in_T_122) node _popc_in_T_124 = mux(_popc_in_T_15, UInt<65>(0h400), _popc_in_T_123) node _popc_in_T_125 = mux(_popc_in_T_14, UInt<65>(0h200), _popc_in_T_124) node _popc_in_T_126 = mux(_popc_in_T_13, UInt<65>(0h100), _popc_in_T_125) node _popc_in_T_127 = mux(_popc_in_T_12, UInt<65>(0h80), _popc_in_T_126) node _popc_in_T_128 = mux(_popc_in_T_11, UInt<65>(0h40), _popc_in_T_127) node _popc_in_T_129 = mux(_popc_in_T_10, UInt<65>(0h20), _popc_in_T_128) node _popc_in_T_130 = mux(_popc_in_T_9, UInt<65>(0h10), _popc_in_T_129) node _popc_in_T_131 = mux(_popc_in_T_8, UInt<65>(0h8), _popc_in_T_130) node _popc_in_T_132 = mux(_popc_in_T_7, UInt<65>(0h4), _popc_in_T_131) node _popc_in_T_133 = mux(_popc_in_T_6, UInt<65>(0h2), _popc_in_T_132) node _popc_in_T_134 = mux(_popc_in_T_5, UInt<65>(0h1), _popc_in_T_133) node _popc_in_T_135 = sub(_popc_in_T_134, UInt<1>(0h1)) node _popc_in_T_136 = tail(_popc_in_T_135, 1) node _popc_in_T_137 = mux(_popc_in_T, _popc_in_T_3, _popc_in_T_136) node popc_in = bits(_popc_in_T_137, 63, 0) node _count_T = bits(popc_in, 0, 0) node _count_T_1 = bits(popc_in, 1, 1) node _count_T_2 = bits(popc_in, 2, 2) node _count_T_3 = bits(popc_in, 3, 3) node _count_T_4 = bits(popc_in, 4, 4) node _count_T_5 = bits(popc_in, 5, 5) node _count_T_6 = bits(popc_in, 6, 6) node _count_T_7 = bits(popc_in, 7, 7) node _count_T_8 = bits(popc_in, 8, 8) node _count_T_9 = bits(popc_in, 9, 9) node _count_T_10 = bits(popc_in, 10, 10) node _count_T_11 = bits(popc_in, 11, 11) node _count_T_12 = bits(popc_in, 12, 12) node _count_T_13 = bits(popc_in, 13, 13) node _count_T_14 = bits(popc_in, 14, 14) node _count_T_15 = bits(popc_in, 15, 15) node _count_T_16 = bits(popc_in, 16, 16) node _count_T_17 = bits(popc_in, 17, 17) node _count_T_18 = bits(popc_in, 18, 18) node _count_T_19 = bits(popc_in, 19, 19) node _count_T_20 = bits(popc_in, 20, 20) node _count_T_21 = bits(popc_in, 21, 21) node _count_T_22 = bits(popc_in, 22, 22) node _count_T_23 = bits(popc_in, 23, 23) node _count_T_24 = bits(popc_in, 24, 24) node _count_T_25 = bits(popc_in, 25, 25) node _count_T_26 = bits(popc_in, 26, 26) node _count_T_27 = bits(popc_in, 27, 27) node _count_T_28 = bits(popc_in, 28, 28) node _count_T_29 = bits(popc_in, 29, 29) node _count_T_30 = bits(popc_in, 30, 30) node _count_T_31 = bits(popc_in, 31, 31) node _count_T_32 = bits(popc_in, 32, 32) node _count_T_33 = bits(popc_in, 33, 33) node _count_T_34 = bits(popc_in, 34, 34) node _count_T_35 = bits(popc_in, 35, 35) node _count_T_36 = bits(popc_in, 36, 36) node _count_T_37 = bits(popc_in, 37, 37) node _count_T_38 = bits(popc_in, 38, 38) node _count_T_39 = bits(popc_in, 39, 39) node _count_T_40 = bits(popc_in, 40, 40) node _count_T_41 = bits(popc_in, 41, 41) node _count_T_42 = bits(popc_in, 42, 42) node _count_T_43 = bits(popc_in, 43, 43) node _count_T_44 = bits(popc_in, 44, 44) node _count_T_45 = bits(popc_in, 45, 45) node _count_T_46 = bits(popc_in, 46, 46) node _count_T_47 = bits(popc_in, 47, 47) node _count_T_48 = bits(popc_in, 48, 48) node _count_T_49 = bits(popc_in, 49, 49) node _count_T_50 = bits(popc_in, 50, 50) node _count_T_51 = bits(popc_in, 51, 51) node _count_T_52 = bits(popc_in, 52, 52) node _count_T_53 = bits(popc_in, 53, 53) node _count_T_54 = bits(popc_in, 54, 54) node _count_T_55 = bits(popc_in, 55, 55) node _count_T_56 = bits(popc_in, 56, 56) node _count_T_57 = bits(popc_in, 57, 57) node _count_T_58 = bits(popc_in, 58, 58) node _count_T_59 = bits(popc_in, 59, 59) node _count_T_60 = bits(popc_in, 60, 60) node _count_T_61 = bits(popc_in, 61, 61) node _count_T_62 = bits(popc_in, 62, 62) node _count_T_63 = bits(popc_in, 63, 63) node _count_T_64 = add(_count_T, _count_T_1) node _count_T_65 = bits(_count_T_64, 1, 0) node _count_T_66 = add(_count_T_2, _count_T_3) node _count_T_67 = bits(_count_T_66, 1, 0) node _count_T_68 = add(_count_T_65, _count_T_67) node _count_T_69 = bits(_count_T_68, 2, 0) node _count_T_70 = add(_count_T_4, _count_T_5) node _count_T_71 = bits(_count_T_70, 1, 0) node _count_T_72 = add(_count_T_6, _count_T_7) node _count_T_73 = bits(_count_T_72, 1, 0) node _count_T_74 = add(_count_T_71, _count_T_73) node _count_T_75 = bits(_count_T_74, 2, 0) node _count_T_76 = add(_count_T_69, _count_T_75) node _count_T_77 = bits(_count_T_76, 3, 0) node _count_T_78 = add(_count_T_8, _count_T_9) node _count_T_79 = bits(_count_T_78, 1, 0) node _count_T_80 = add(_count_T_10, _count_T_11) node _count_T_81 = bits(_count_T_80, 1, 0) node _count_T_82 = add(_count_T_79, _count_T_81) node _count_T_83 = bits(_count_T_82, 2, 0) node _count_T_84 = add(_count_T_12, _count_T_13) node _count_T_85 = bits(_count_T_84, 1, 0) node _count_T_86 = add(_count_T_14, _count_T_15) node _count_T_87 = bits(_count_T_86, 1, 0) node _count_T_88 = add(_count_T_85, _count_T_87) node _count_T_89 = bits(_count_T_88, 2, 0) node _count_T_90 = add(_count_T_83, _count_T_89) node _count_T_91 = bits(_count_T_90, 3, 0) node _count_T_92 = add(_count_T_77, _count_T_91) node _count_T_93 = bits(_count_T_92, 4, 0) node _count_T_94 = add(_count_T_16, _count_T_17) node _count_T_95 = bits(_count_T_94, 1, 0) node _count_T_96 = add(_count_T_18, _count_T_19) node _count_T_97 = bits(_count_T_96, 1, 0) node _count_T_98 = add(_count_T_95, _count_T_97) node _count_T_99 = bits(_count_T_98, 2, 0) node _count_T_100 = add(_count_T_20, _count_T_21) node _count_T_101 = bits(_count_T_100, 1, 0) node _count_T_102 = add(_count_T_22, _count_T_23) node _count_T_103 = bits(_count_T_102, 1, 0) node _count_T_104 = add(_count_T_101, _count_T_103) node _count_T_105 = bits(_count_T_104, 2, 0) node _count_T_106 = add(_count_T_99, _count_T_105) node _count_T_107 = bits(_count_T_106, 3, 0) node _count_T_108 = add(_count_T_24, _count_T_25) node _count_T_109 = bits(_count_T_108, 1, 0) node _count_T_110 = add(_count_T_26, _count_T_27) node _count_T_111 = bits(_count_T_110, 1, 0) node _count_T_112 = add(_count_T_109, _count_T_111) node _count_T_113 = bits(_count_T_112, 2, 0) node _count_T_114 = add(_count_T_28, _count_T_29) node _count_T_115 = bits(_count_T_114, 1, 0) node _count_T_116 = add(_count_T_30, _count_T_31) node _count_T_117 = bits(_count_T_116, 1, 0) node _count_T_118 = add(_count_T_115, _count_T_117) node _count_T_119 = bits(_count_T_118, 2, 0) node _count_T_120 = add(_count_T_113, _count_T_119) node _count_T_121 = bits(_count_T_120, 3, 0) node _count_T_122 = add(_count_T_107, _count_T_121) node _count_T_123 = bits(_count_T_122, 4, 0) node _count_T_124 = add(_count_T_93, _count_T_123) node _count_T_125 = bits(_count_T_124, 5, 0) node _count_T_126 = add(_count_T_32, _count_T_33) node _count_T_127 = bits(_count_T_126, 1, 0) node _count_T_128 = add(_count_T_34, _count_T_35) node _count_T_129 = bits(_count_T_128, 1, 0) node _count_T_130 = add(_count_T_127, _count_T_129) node _count_T_131 = bits(_count_T_130, 2, 0) node _count_T_132 = add(_count_T_36, _count_T_37) node _count_T_133 = bits(_count_T_132, 1, 0) node _count_T_134 = add(_count_T_38, _count_T_39) node _count_T_135 = bits(_count_T_134, 1, 0) node _count_T_136 = add(_count_T_133, _count_T_135) node _count_T_137 = bits(_count_T_136, 2, 0) node _count_T_138 = add(_count_T_131, _count_T_137) node _count_T_139 = bits(_count_T_138, 3, 0) node _count_T_140 = add(_count_T_40, _count_T_41) node _count_T_141 = bits(_count_T_140, 1, 0) node _count_T_142 = add(_count_T_42, _count_T_43) node _count_T_143 = bits(_count_T_142, 1, 0) node _count_T_144 = add(_count_T_141, _count_T_143) node _count_T_145 = bits(_count_T_144, 2, 0) node _count_T_146 = add(_count_T_44, _count_T_45) node _count_T_147 = bits(_count_T_146, 1, 0) node _count_T_148 = add(_count_T_46, _count_T_47) node _count_T_149 = bits(_count_T_148, 1, 0) node _count_T_150 = add(_count_T_147, _count_T_149) node _count_T_151 = bits(_count_T_150, 2, 0) node _count_T_152 = add(_count_T_145, _count_T_151) node _count_T_153 = bits(_count_T_152, 3, 0) node _count_T_154 = add(_count_T_139, _count_T_153) node _count_T_155 = bits(_count_T_154, 4, 0) node _count_T_156 = add(_count_T_48, _count_T_49) node _count_T_157 = bits(_count_T_156, 1, 0) node _count_T_158 = add(_count_T_50, _count_T_51) node _count_T_159 = bits(_count_T_158, 1, 0) node _count_T_160 = add(_count_T_157, _count_T_159) node _count_T_161 = bits(_count_T_160, 2, 0) node _count_T_162 = add(_count_T_52, _count_T_53) node _count_T_163 = bits(_count_T_162, 1, 0) node _count_T_164 = add(_count_T_54, _count_T_55) node _count_T_165 = bits(_count_T_164, 1, 0) node _count_T_166 = add(_count_T_163, _count_T_165) node _count_T_167 = bits(_count_T_166, 2, 0) node _count_T_168 = add(_count_T_161, _count_T_167) node _count_T_169 = bits(_count_T_168, 3, 0) node _count_T_170 = add(_count_T_56, _count_T_57) node _count_T_171 = bits(_count_T_170, 1, 0) node _count_T_172 = add(_count_T_58, _count_T_59) node _count_T_173 = bits(_count_T_172, 1, 0) node _count_T_174 = add(_count_T_171, _count_T_173) node _count_T_175 = bits(_count_T_174, 2, 0) node _count_T_176 = add(_count_T_60, _count_T_61) node _count_T_177 = bits(_count_T_176, 1, 0) node _count_T_178 = add(_count_T_62, _count_T_63) node _count_T_179 = bits(_count_T_178, 1, 0) node _count_T_180 = add(_count_T_177, _count_T_179) node _count_T_181 = bits(_count_T_180, 2, 0) node _count_T_182 = add(_count_T_175, _count_T_181) node _count_T_183 = bits(_count_T_182, 3, 0) node _count_T_184 = add(_count_T_169, _count_T_183) node _count_T_185 = bits(_count_T_184, 4, 0) node _count_T_186 = add(_count_T_155, _count_T_185) node _count_T_187 = bits(_count_T_186, 5, 0) node _count_T_188 = add(_count_T_125, _count_T_187) node count = bits(_count_T_188, 6, 0) wire in1_bytes : UInt<8>[8] wire _in1_bytes_WIRE : UInt<64> connect _in1_bytes_WIRE, io.in1 node _in1_bytes_T = bits(_in1_bytes_WIRE, 7, 0) connect in1_bytes[0], _in1_bytes_T node _in1_bytes_T_1 = bits(_in1_bytes_WIRE, 15, 8) connect in1_bytes[1], _in1_bytes_T_1 node _in1_bytes_T_2 = bits(_in1_bytes_WIRE, 23, 16) connect in1_bytes[2], _in1_bytes_T_2 node _in1_bytes_T_3 = bits(_in1_bytes_WIRE, 31, 24) connect in1_bytes[3], _in1_bytes_T_3 node _in1_bytes_T_4 = bits(_in1_bytes_WIRE, 39, 32) connect in1_bytes[4], _in1_bytes_T_4 node _in1_bytes_T_5 = bits(_in1_bytes_WIRE, 47, 40) connect in1_bytes[5], _in1_bytes_T_5 node _in1_bytes_T_6 = bits(_in1_bytes_WIRE, 55, 48) connect in1_bytes[6], _in1_bytes_T_6 node _in1_bytes_T_7 = bits(_in1_bytes_WIRE, 63, 56) connect in1_bytes[7], _in1_bytes_T_7 node _orcb_T = neq(in1_bytes[0], UInt<1>(0h0)) node _orcb_T_1 = mux(_orcb_T, UInt<8>(0hff), UInt<8>(0h0)) node _orcb_T_2 = neq(in1_bytes[1], UInt<1>(0h0)) node _orcb_T_3 = mux(_orcb_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _orcb_T_4 = neq(in1_bytes[2], UInt<1>(0h0)) node _orcb_T_5 = mux(_orcb_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _orcb_T_6 = neq(in1_bytes[3], UInt<1>(0h0)) node _orcb_T_7 = mux(_orcb_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _orcb_T_8 = neq(in1_bytes[4], UInt<1>(0h0)) node _orcb_T_9 = mux(_orcb_T_8, UInt<8>(0hff), UInt<8>(0h0)) node _orcb_T_10 = neq(in1_bytes[5], UInt<1>(0h0)) node _orcb_T_11 = mux(_orcb_T_10, UInt<8>(0hff), UInt<8>(0h0)) node _orcb_T_12 = neq(in1_bytes[6], UInt<1>(0h0)) node _orcb_T_13 = mux(_orcb_T_12, UInt<8>(0hff), UInt<8>(0h0)) node _orcb_T_14 = neq(in1_bytes[7], UInt<1>(0h0)) node _orcb_T_15 = mux(_orcb_T_14, UInt<8>(0hff), UInt<8>(0h0)) wire _orcb_WIRE : UInt<8>[8] connect _orcb_WIRE[0], _orcb_T_1 connect _orcb_WIRE[1], _orcb_T_3 connect _orcb_WIRE[2], _orcb_T_5 connect _orcb_WIRE[3], _orcb_T_7 connect _orcb_WIRE[4], _orcb_T_9 connect _orcb_WIRE[5], _orcb_T_11 connect _orcb_WIRE[6], _orcb_T_13 connect _orcb_WIRE[7], _orcb_T_15 node orcb_lo_lo = cat(_orcb_WIRE[1], _orcb_WIRE[0]) node orcb_lo_hi = cat(_orcb_WIRE[3], _orcb_WIRE[2]) node orcb_lo = cat(orcb_lo_hi, orcb_lo_lo) node orcb_hi_lo = cat(_orcb_WIRE[5], _orcb_WIRE[4]) node orcb_hi_hi = cat(_orcb_WIRE[7], _orcb_WIRE[6]) node orcb_hi = cat(orcb_hi_hi, orcb_hi_lo) node orcb = cat(orcb_hi, orcb_lo) wire _rev8_WIRE : UInt<8>[8] connect _rev8_WIRE[0], in1_bytes[7] connect _rev8_WIRE[1], in1_bytes[6] connect _rev8_WIRE[2], in1_bytes[5] connect _rev8_WIRE[3], in1_bytes[4] connect _rev8_WIRE[4], in1_bytes[3] connect _rev8_WIRE[5], in1_bytes[2] connect _rev8_WIRE[6], in1_bytes[1] connect _rev8_WIRE[7], in1_bytes[0] node rev8_lo_lo = cat(_rev8_WIRE[1], _rev8_WIRE[0]) node rev8_lo_hi = cat(_rev8_WIRE[3], _rev8_WIRE[2]) node rev8_lo = cat(rev8_lo_hi, rev8_lo_lo) node rev8_hi_lo = cat(_rev8_WIRE[5], _rev8_WIRE[4]) node rev8_hi_hi = cat(_rev8_WIRE[7], _rev8_WIRE[6]) node rev8_hi = cat(rev8_hi_hi, rev8_hi_lo) node rev8 = cat(rev8_hi, rev8_lo) node _unary_T = bits(io.in2, 11, 0) node _unary_T_1 = bits(io.in1, 15, 0) node _unary_T_2 = bits(io.in1, 7, 7) node _unary_T_3 = mux(_unary_T_2, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _unary_T_4 = bits(io.in1, 7, 0) node _unary_T_5 = cat(_unary_T_3, _unary_T_4) node _unary_T_6 = bits(io.in1, 15, 15) node _unary_T_7 = mux(_unary_T_6, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _unary_T_8 = bits(io.in1, 15, 0) node _unary_T_9 = cat(_unary_T_7, _unary_T_8) node _unary_T_10 = eq(UInt<10>(0h287), _unary_T) node _unary_T_11 = mux(_unary_T_10, orcb, count) node _unary_T_12 = eq(UInt<11>(0h6b8), _unary_T) node _unary_T_13 = mux(_unary_T_12, rev8, _unary_T_11) node _unary_T_14 = eq(UInt<8>(0h80), _unary_T) node _unary_T_15 = mux(_unary_T_14, _unary_T_1, _unary_T_13) node _unary_T_16 = eq(UInt<11>(0h604), _unary_T) node _unary_T_17 = mux(_unary_T_16, _unary_T_5, _unary_T_15) node _unary_T_18 = eq(UInt<11>(0h605), _unary_T) node unary = mux(_unary_T_18, _unary_T_9, _unary_T_17) node maxmin_out = mux(io.cmp_out, io.in2, io.in1) node _rot_shamt_T = eq(io.dw, UInt<1>(0h0)) node _rot_shamt_T_1 = mux(_rot_shamt_T, UInt<6>(0h20), UInt<7>(0h40)) node _rot_shamt_T_2 = sub(_rot_shamt_T_1, shamt) node rot_shamt = tail(_rot_shamt_T_2, 1) node _rotin_T = bits(io.fn, 0, 0) node _rotin_T_1 = shl(UInt<32>(0hffffffff), 32) node _rotin_T_2 = xor(UInt<64>(0hffffffffffffffff), _rotin_T_1) node _rotin_T_3 = shr(shin_r, 32) node _rotin_T_4 = and(_rotin_T_3, _rotin_T_2) node _rotin_T_5 = bits(shin_r, 31, 0) node _rotin_T_6 = shl(_rotin_T_5, 32) node _rotin_T_7 = not(_rotin_T_2) node _rotin_T_8 = and(_rotin_T_6, _rotin_T_7) node _rotin_T_9 = or(_rotin_T_4, _rotin_T_8) node _rotin_T_10 = bits(_rotin_T_2, 47, 0) node _rotin_T_11 = shl(_rotin_T_10, 16) node _rotin_T_12 = xor(_rotin_T_2, _rotin_T_11) node _rotin_T_13 = shr(_rotin_T_9, 16) node _rotin_T_14 = and(_rotin_T_13, _rotin_T_12) node _rotin_T_15 = bits(_rotin_T_9, 47, 0) node _rotin_T_16 = shl(_rotin_T_15, 16) node _rotin_T_17 = not(_rotin_T_12) node _rotin_T_18 = and(_rotin_T_16, _rotin_T_17) node _rotin_T_19 = or(_rotin_T_14, _rotin_T_18) node _rotin_T_20 = bits(_rotin_T_12, 55, 0) node _rotin_T_21 = shl(_rotin_T_20, 8) node _rotin_T_22 = xor(_rotin_T_12, _rotin_T_21) node _rotin_T_23 = shr(_rotin_T_19, 8) node _rotin_T_24 = and(_rotin_T_23, _rotin_T_22) node _rotin_T_25 = bits(_rotin_T_19, 55, 0) node _rotin_T_26 = shl(_rotin_T_25, 8) node _rotin_T_27 = not(_rotin_T_22) node _rotin_T_28 = and(_rotin_T_26, _rotin_T_27) node _rotin_T_29 = or(_rotin_T_24, _rotin_T_28) node _rotin_T_30 = bits(_rotin_T_22, 59, 0) node _rotin_T_31 = shl(_rotin_T_30, 4) node _rotin_T_32 = xor(_rotin_T_22, _rotin_T_31) node _rotin_T_33 = shr(_rotin_T_29, 4) node _rotin_T_34 = and(_rotin_T_33, _rotin_T_32) node _rotin_T_35 = bits(_rotin_T_29, 59, 0) node _rotin_T_36 = shl(_rotin_T_35, 4) node _rotin_T_37 = not(_rotin_T_32) node _rotin_T_38 = and(_rotin_T_36, _rotin_T_37) node _rotin_T_39 = or(_rotin_T_34, _rotin_T_38) node _rotin_T_40 = bits(_rotin_T_32, 61, 0) node _rotin_T_41 = shl(_rotin_T_40, 2) node _rotin_T_42 = xor(_rotin_T_32, _rotin_T_41) node _rotin_T_43 = shr(_rotin_T_39, 2) node _rotin_T_44 = and(_rotin_T_43, _rotin_T_42) node _rotin_T_45 = bits(_rotin_T_39, 61, 0) node _rotin_T_46 = shl(_rotin_T_45, 2) node _rotin_T_47 = not(_rotin_T_42) node _rotin_T_48 = and(_rotin_T_46, _rotin_T_47) node _rotin_T_49 = or(_rotin_T_44, _rotin_T_48) node _rotin_T_50 = bits(_rotin_T_42, 62, 0) node _rotin_T_51 = shl(_rotin_T_50, 1) node _rotin_T_52 = xor(_rotin_T_42, _rotin_T_51) node _rotin_T_53 = shr(_rotin_T_49, 1) node _rotin_T_54 = and(_rotin_T_53, _rotin_T_52) node _rotin_T_55 = bits(_rotin_T_49, 62, 0) node _rotin_T_56 = shl(_rotin_T_55, 1) node _rotin_T_57 = not(_rotin_T_52) node _rotin_T_58 = and(_rotin_T_56, _rotin_T_57) node _rotin_T_59 = or(_rotin_T_54, _rotin_T_58) node rotin = mux(_rotin_T, shin_r, _rotin_T_59) node _rotout_r_T = dshr(rotin, rot_shamt) node rotout_r = bits(_rotout_r_T, 63, 0) node _rotout_l_T = shl(UInt<32>(0hffffffff), 32) node _rotout_l_T_1 = xor(UInt<64>(0hffffffffffffffff), _rotout_l_T) node _rotout_l_T_2 = shr(rotout_r, 32) node _rotout_l_T_3 = and(_rotout_l_T_2, _rotout_l_T_1) node _rotout_l_T_4 = bits(rotout_r, 31, 0) node _rotout_l_T_5 = shl(_rotout_l_T_4, 32) node _rotout_l_T_6 = not(_rotout_l_T_1) node _rotout_l_T_7 = and(_rotout_l_T_5, _rotout_l_T_6) node _rotout_l_T_8 = or(_rotout_l_T_3, _rotout_l_T_7) node _rotout_l_T_9 = bits(_rotout_l_T_1, 47, 0) node _rotout_l_T_10 = shl(_rotout_l_T_9, 16) node _rotout_l_T_11 = xor(_rotout_l_T_1, _rotout_l_T_10) node _rotout_l_T_12 = shr(_rotout_l_T_8, 16) node _rotout_l_T_13 = and(_rotout_l_T_12, _rotout_l_T_11) node _rotout_l_T_14 = bits(_rotout_l_T_8, 47, 0) node _rotout_l_T_15 = shl(_rotout_l_T_14, 16) node _rotout_l_T_16 = not(_rotout_l_T_11) node _rotout_l_T_17 = and(_rotout_l_T_15, _rotout_l_T_16) node _rotout_l_T_18 = or(_rotout_l_T_13, _rotout_l_T_17) node _rotout_l_T_19 = bits(_rotout_l_T_11, 55, 0) node _rotout_l_T_20 = shl(_rotout_l_T_19, 8) node _rotout_l_T_21 = xor(_rotout_l_T_11, _rotout_l_T_20) node _rotout_l_T_22 = shr(_rotout_l_T_18, 8) node _rotout_l_T_23 = and(_rotout_l_T_22, _rotout_l_T_21) node _rotout_l_T_24 = bits(_rotout_l_T_18, 55, 0) node _rotout_l_T_25 = shl(_rotout_l_T_24, 8) node _rotout_l_T_26 = not(_rotout_l_T_21) node _rotout_l_T_27 = and(_rotout_l_T_25, _rotout_l_T_26) node _rotout_l_T_28 = or(_rotout_l_T_23, _rotout_l_T_27) node _rotout_l_T_29 = bits(_rotout_l_T_21, 59, 0) node _rotout_l_T_30 = shl(_rotout_l_T_29, 4) node _rotout_l_T_31 = xor(_rotout_l_T_21, _rotout_l_T_30) node _rotout_l_T_32 = shr(_rotout_l_T_28, 4) node _rotout_l_T_33 = and(_rotout_l_T_32, _rotout_l_T_31) node _rotout_l_T_34 = bits(_rotout_l_T_28, 59, 0) node _rotout_l_T_35 = shl(_rotout_l_T_34, 4) node _rotout_l_T_36 = not(_rotout_l_T_31) node _rotout_l_T_37 = and(_rotout_l_T_35, _rotout_l_T_36) node _rotout_l_T_38 = or(_rotout_l_T_33, _rotout_l_T_37) node _rotout_l_T_39 = bits(_rotout_l_T_31, 61, 0) node _rotout_l_T_40 = shl(_rotout_l_T_39, 2) node _rotout_l_T_41 = xor(_rotout_l_T_31, _rotout_l_T_40) node _rotout_l_T_42 = shr(_rotout_l_T_38, 2) node _rotout_l_T_43 = and(_rotout_l_T_42, _rotout_l_T_41) node _rotout_l_T_44 = bits(_rotout_l_T_38, 61, 0) node _rotout_l_T_45 = shl(_rotout_l_T_44, 2) node _rotout_l_T_46 = not(_rotout_l_T_41) node _rotout_l_T_47 = and(_rotout_l_T_45, _rotout_l_T_46) node _rotout_l_T_48 = or(_rotout_l_T_43, _rotout_l_T_47) node _rotout_l_T_49 = bits(_rotout_l_T_41, 62, 0) node _rotout_l_T_50 = shl(_rotout_l_T_49, 1) node _rotout_l_T_51 = xor(_rotout_l_T_41, _rotout_l_T_50) node _rotout_l_T_52 = shr(_rotout_l_T_48, 1) node _rotout_l_T_53 = and(_rotout_l_T_52, _rotout_l_T_51) node _rotout_l_T_54 = bits(_rotout_l_T_48, 62, 0) node _rotout_l_T_55 = shl(_rotout_l_T_54, 1) node _rotout_l_T_56 = not(_rotout_l_T_51) node _rotout_l_T_57 = and(_rotout_l_T_55, _rotout_l_T_56) node rotout_l = or(_rotout_l_T_53, _rotout_l_T_57) node _rotout_T = bits(io.fn, 0, 0) node _rotout_T_1 = mux(_rotout_T, rotout_r, rotout_l) node _rotout_T_2 = bits(io.fn, 0, 0) node _rotout_T_3 = mux(_rotout_T_2, shout_l, shout_r) node rotout = or(_rotout_T_1, _rotout_T_3) node _out_T = eq(UInt<1>(0h0), io.fn) node _out_T_1 = mux(_out_T, io.adder_out, shift_logic) node _out_T_2 = eq(UInt<4>(0ha), io.fn) node out = mux(_out_T_2, io.adder_out, _out_T_1) connect io.out, out node _T_1 = eq(io.dw, UInt<1>(0h0)) when _T_1 : node _io_out_T = bits(out, 31, 31) node _io_out_T_1 = mux(_io_out_T, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_out_T_2 = bits(out, 31, 0) node _io_out_T_3 = cat(_io_out_T_1, _io_out_T_2) connect io.out, _io_out_T_3	module ALU_3( // @[ALU.scala:83:7] input clock, // @[ALU.scala:83:7] input reset, // @[ALU.scala:83:7] input io_dw, // @[ALU.scala:72:14] input [4:0] io_fn, // @[ALU.scala:72:14] input [63:0] io_in2, // @[ALU.scala:72:14] input [63:0] io_in1, // @[ALU.scala:72:14] output [63:0] io_out // @[ALU.scala:72:14] ); wire [7:0] in1_bytes_6; // @[ALU.scala:140:34] wire [7:0] in1_bytes_5; // @[ALU.scala:140:34] wire [7:0] in1_bytes_4; // @[ALU.scala:140:34] wire [7:0] in1_bytes_3; // @[ALU.scala:140:34] wire [7:0] in1_bytes_2; // @[ALU.scala:140:34] wire [7:0] in1_bytes_1; // @[ALU.scala:140:34] wire [7:0] in1_bytes_0; // @[ALU.scala:140:34] wire io_dw_0 = io_dw; // @[ALU.scala:83:7] wire [4:0] io_fn_0 = io_fn; // @[ALU.scala:83:7] wire [63:0] io_in2_0 = io_in2; // @[ALU.scala:83:7] wire [63:0] io_in1_0 = io_in1; // @[ALU.scala:83:7] wire _bext_mask_T_1 = 1'h0; // @[ALU.scala:122:43] wire [63:0] _bext_mask_T_2 = 64'hFFFFFFFFFFFFFFFF; // @[ALU.scala:122:70] wire [63:0] bext_mask = 64'hFFFFFFFFFFFFFFFF; // @[ALU.scala:122:22] wire [31:0] _tz_in_T_67 = 32'hFFFF; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_66 = 32'hFFFF0000; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_72 = 32'hFFFF0000; // @[ALU.scala:134:26] wire [23:0] _tz_in_T_75 = 24'hFFFF; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_76 = 32'hFFFF00; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_77 = 32'hFF00FF; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_82 = 32'hFF00FF00; // @[ALU.scala:134:26] wire [27:0] _tz_in_T_85 = 28'hFF00FF; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_86 = 32'hFF00FF0; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_87 = 32'hF0F0F0F; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_92 = 32'hF0F0F0F0; // @[ALU.scala:134:26] wire [29:0] _tz_in_T_95 = 30'hF0F0F0F; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_96 = 32'h3C3C3C3C; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_97 = 32'h33333333; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_102 = 32'hCCCCCCCC; // @[ALU.scala:134:26] wire [30:0] _tz_in_T_105 = 31'h33333333; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_106 = 32'h66666666; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_107 = 32'h55555555; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_112 = 32'hAAAAAAAA; // @[ALU.scala:134:26] wire [63:0] _shin_T_9 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_1 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_5 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_2 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_1 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_8 = 64'hFFFFFFFF00000000; // @[ALU.scala:106:46] wire [63:0] _shin_T_14 = 64'hFFFFFFFF00000000; // @[ALU.scala:106:46] wire [63:0] _shout_l_T = 64'hFFFFFFFF00000000; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_6 = 64'hFFFFFFFF00000000; // @[ALU.scala:108:24] wire [63:0] _tz_in_T_4 = 64'hFFFFFFFF00000000; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_10 = 64'hFFFFFFFF00000000; // @[ALU.scala:132:19] wire [63:0] _rotin_T_1 = 64'hFFFFFFFF00000000; // @[ALU.scala:156:44] wire [63:0] _rotin_T_7 = 64'hFFFFFFFF00000000; // @[ALU.scala:156:44] wire [63:0] _rotout_l_T = 64'hFFFFFFFF00000000; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_6 = 64'hFFFFFFFF00000000; // @[ALU.scala:158:25] wire [47:0] _shin_T_17 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _shout_l_T_9 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _tz_in_T_13 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _rotin_T_10 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _rotout_l_T_9 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_18 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_10 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_14 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_11 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_10 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_19 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_11 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_15 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_12 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_11 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_24 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_16 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_20 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_17 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_16 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _shin_T_27 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _shout_l_T_19 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _tz_in_T_23 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _rotin_T_20 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _rotout_l_T_19 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_28 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_20 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_24 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_21 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_20 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_29 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_21 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_25 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_22 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_21 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_34 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_26 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_30 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_27 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_26 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _shin_T_37 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _shout_l_T_29 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _tz_in_T_33 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _rotin_T_30 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _rotout_l_T_29 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_38 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_30 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_34 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_31 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_30 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_39 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_31 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_35 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_32 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_31 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_44 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_36 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_40 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_37 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_36 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [61:0] _shin_T_47 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [61:0] _shout_l_T_39 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [61:0] _tz_in_T_43 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [61:0] _rotin_T_40 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [61:0] _rotout_l_T_39 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_48 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_40 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_44 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_41 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_40 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_49 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_41 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_45 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_42 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_41 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_54 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_46 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_50 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_47 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_46 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _shin_T_57 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _shout_l_T_49 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _tz_in_T_53 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _rotin_T_50 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _rotout_l_T_49 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_58 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_50 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_54 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_51 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_50 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_59 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_51 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_55 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_52 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_51 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_64 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_56 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_60 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_57 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_56 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire _shin_hi_T = io_dw_0; // @[ALU.scala:83:7, :102:31] wire _shamt_T_1 = io_dw_0; // @[ALU.scala:83:7, :103:42] wire [63:0] _in1_bytes_WIRE = io_in1_0; // @[ALU.scala:83:7, :140:34] wire [63:0] _io_adder_out_T_4; // @[ALU.scala:88:36] wire _io_cmp_out_T_5; // @[ALU.scala:94:36] wire [63:0] io_out_0; // @[ALU.scala:83:7] wire [63:0] io_adder_out; // @[ALU.scala:83:7] wire io_cmp_out; // @[ALU.scala:83:7] wire _in2_inv_T = io_fn_0[3]; // @[ALU.scala:58:29, :83:7] wire _io_adder_out_T_2 = io_fn_0[3]; // @[ALU.scala:58:29, :83:7] wire _io_cmp_out_T_1 = io_fn_0[3]; // @[ALU.scala:58:29, :63:30, :83:7] wire _shin_hi_32_T = io_fn_0[3]; // @[ALU.scala:58:29, :83:7] wire _shout_r_T = io_fn_0[3]; // @[ALU.scala:58:29, :83:7] wire [63:0] _in2_inv_T_1 = ~io_in2_0; // @[ALU.scala:83:7, :85:35] wire [63:0] in2_inv = _in2_inv_T ? _in2_inv_T_1 : io_in2_0; // @[ALU.scala:58:29, :83:7, :85:{20,35}] wire [63:0] in1_xor_in2 = io_in1_0 ^ in2_inv; // @[ALU.scala:83:7, :85:20, :86:28] wire [63:0] in1_and_in2 = io_in1_0 & in2_inv; // @[ALU.scala:83:7, :85:20, :87:28] wire [64:0] _io_adder_out_T = {1'h0, io_in1_0} + {1'h0, in2_inv}; // @[ALU.scala:83:7, :85:20, :88:26] wire [63:0] _io_adder_out_T_1 = _io_adder_out_T[63:0]; // @[ALU.scala:88:26] wire [64:0] _io_adder_out_T_3 = {1'h0, _io_adder_out_T_1} + {64'h0, _io_adder_out_T_2}; // @[ALU.scala:58:29, :88:{26,36}] assign _io_adder_out_T_4 = _io_adder_out_T_3[63:0]; // @[ALU.scala:88:36] assign io_adder_out = _io_adder_out_T_4; // @[ALU.scala:83:7, :88:36] wire _slt_T = io_in1_0[63]; // @[ALU.scala:83:7, :92:15] wire _slt_T_6 = io_in1_0[63]; // @[ALU.scala:83:7, :92:15, :93:51] wire _slt_T_1 = io_in2_0[63]; // @[ALU.scala:83:7, :92:34] wire _slt_T_5 = io_in2_0[63]; // @[ALU.scala:83:7, :92:34, :93:35] wire _slt_T_2 = _slt_T == _slt_T_1; // @[ALU.scala:92:{15,24,34}] wire _slt_T_3 = io_adder_out[63]; // @[ALU.scala:83:7, :92:56] wire _slt_T_4 = io_fn_0[1]; // @[ALU.scala:61:35, :83:7] wire _slt_T_7 = _slt_T_4 ? _slt_T_5 : _slt_T_6; // @[ALU.scala:61:35, :93:{8,35,51}] wire slt = _slt_T_2 ? _slt_T_3 : _slt_T_7; // @[ALU.scala:92:{8,24,56}, :93:8] wire _io_cmp_out_T = io_fn_0[0]; // @[ALU.scala:62:35, :83:7] wire _rotin_T = io_fn_0[0]; // @[ALU.scala:62:35, :83:7, :156:24] wire _rotout_T = io_fn_0[0]; // @[ALU.scala:62:35, :83:7, :159:25] wire _rotout_T_2 = io_fn_0[0]; // @[ALU.scala:62:35, :83:7, :159:61] wire _io_cmp_out_T_2 = ~_io_cmp_out_T_1; // @[ALU.scala:63:{26,30}] wire _io_cmp_out_T_3 = in1_xor_in2 == 64'h0; // @[ALU.scala:86:28, :94:68] wire _io_cmp_out_T_4 = _io_cmp_out_T_2 ? _io_cmp_out_T_3 : slt; // @[ALU.scala:63:26, :92:8, :94:{41,68}] assign _io_cmp_out_T_5 = _io_cmp_out_T ^ _io_cmp_out_T_4; // @[ALU.scala:62:35, :94:{36,41}] assign io_cmp_out = _io_cmp_out_T_5; // @[ALU.scala:83:7, :94:36] wire _shin_hi_32_T_1 = io_in1_0[31]; // @[ALU.scala:83:7, :101:55] wire _shin_hi_32_T_2 = _shin_hi_32_T & _shin_hi_32_T_1; // @[ALU.scala:58:29, :101:{46,55}] wire [31:0] shin_hi_32 = {32{_shin_hi_32_T_2}}; // @[ALU.scala:101:{28,46}] wire [31:0] _shin_hi_T_1 = io_in1_0[63:32]; // @[ALU.scala:83:7, :102:48] wire [31:0] _tz_in_T_6 = io_in1_0[63:32]; // @[ALU.scala:83:7, :102:48, :132:19] wire [31:0] shin_hi = _shin_hi_T ? _shin_hi_T_1 : shin_hi_32; // @[ALU.scala:101:28, :102:{24,31,48}] wire _shamt_T = io_in2_0[5]; // @[ALU.scala:83:7, :103:29] wire _shamt_T_2 = _shamt_T & _shamt_T_1; // @[ALU.scala:103:{29,33,42}] wire [4:0] _shamt_T_3 = io_in2_0[4:0]; // @[ALU.scala:83:7, :103:60] wire [5:0] shamt = {_shamt_T_2, _shamt_T_3}; // @[ALU.scala:103:{22,33,60}] wire [31:0] _tz_in_T_8 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :132:19] wire [31:0] _tz_in_T_63 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :133:25] wire [31:0] _tz_in_T_65 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :134:33] wire [31:0] _popc_in_T_2 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :137:32] wire [63:0] shin_r = {shin_hi, io_in1_0[31:0]}; // @[ALU.scala:83:7, :102:24, :104:{18,34}] wire _GEN = io_fn_0 == 5'h5; // @[package.scala:16:47] wire _shin_T; // @[package.scala:16:47] assign _shin_T = _GEN; // @[package.scala:16:47] wire _shout_T; // @[ALU.scala:109:25] assign _shout_T = _GEN; // @[package.scala:16:47] wire _GEN_0 = io_fn_0 == 5'hB; // @[package.scala:16:47] wire _shin_T_1; // @[package.scala:16:47] assign _shin_T_1 = _GEN_0; // @[package.scala:16:47] wire _shout_T_1; // @[ALU.scala:109:44] assign _shout_T_1 = _GEN_0; // @[package.scala:16:47] wire _shin_T_2 = io_fn_0 == 5'h12; // @[package.scala:16:47] wire _GEN_1 = io_fn_0 == 5'h13; // @[package.scala:16:47] wire _shin_T_3; // @[package.scala:16:47] assign _shin_T_3 = _GEN_1; // @[package.scala:16:47] wire _shout_T_3; // @[ALU.scala:109:64] assign _shout_T_3 = _GEN_1; // @[package.scala:16:47] wire _bext_mask_T; // @[ALU.scala:122:52] assign _bext_mask_T = _GEN_1; // @[package.scala:16:47] wire _shin_T_4 = _shin_T \| _shin_T_1; // @[package.scala:16:47, :81:59] wire _shin_T_5 = _shin_T_4 \| _shin_T_2; // @[package.scala:16:47, :81:59] wire _shin_T_6 = _shin_T_5 \| _shin_T_3; // @[package.scala:16:47, :81:59] wire _shin_T_7 = ~_shin_T_6; // @[package.scala:81:59] wire [31:0] _shin_T_10 = shin_r[63:32]; // @[ALU.scala:104:18, :106:46] wire [31:0] _rotin_T_3 = shin_r[63:32]; // @[ALU.scala:104:18, :106:46, :156:44] wire [63:0] _shin_T_11 = {32'h0, _shin_T_10}; // @[ALU.scala:106:46] wire [31:0] _shin_T_12 = shin_r[31:0]; // @[ALU.scala:104:18, :106:46] wire [31:0] _rotin_T_5 = shin_r[31:0]; // @[ALU.scala:104:18, :106:46, :156:44] wire [63:0] _shin_T_13 = {_shin_T_12, 32'h0}; // @[ALU.scala:106:46] wire [63:0] _shin_T_15 = _shin_T_13 & 64'hFFFFFFFF00000000; // @[ALU.scala:106:46] wire [63:0] _shin_T_16 = _shin_T_11 \| _shin_T_15; // @[ALU.scala:106:46] wire [47:0] _shin_T_20 = _shin_T_16[63:16]; // @[ALU.scala:106:46] wire [63:0] _shin_T_21 = {16'h0, _shin_T_20 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _shin_T_22 = _shin_T_16[47:0]; // @[ALU.scala:106:46] wire [63:0] _shin_T_23 = {_shin_T_22, 16'h0}; // @[ALU.scala:106:46] wire [63:0] _shin_T_25 = _shin_T_23 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_26 = _shin_T_21 \| _shin_T_25; // @[ALU.scala:106:46] wire [55:0] _shin_T_30 = _shin_T_26[63:8]; // @[ALU.scala:106:46] wire [63:0] _shin_T_31 = {8'h0, _shin_T_30 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _shin_T_32 = _shin_T_26[55:0]; // @[ALU.scala:106:46] wire [63:0] _shin_T_33 = {_shin_T_32, 8'h0}; // @[ALU.scala:106:46] wire [63:0] _shin_T_35 = _shin_T_33 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_36 = _shin_T_31 \| _shin_T_35; // @[ALU.scala:106:46] wire [59:0] _shin_T_40 = _shin_T_36[63:4]; // @[ALU.scala:106:46] wire [63:0] _shin_T_41 = {4'h0, _shin_T_40 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _shin_T_42 = _shin_T_36[59:0]; // @[ALU.scala:106:46] wire [63:0] _shin_T_43 = {_shin_T_42, 4'h0}; // @[ALU.scala:106:46] wire [63:0] _shin_T_45 = _shin_T_43 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_46 = _shin_T_41 \| _shin_T_45; // @[ALU.scala:106:46] wire [61:0] _shin_T_50 = _shin_T_46[63:2]; // @[ALU.scala:106:46] wire [63:0] _shin_T_51 = {2'h0, _shin_T_50 & 62'h3333333333333333}; // @[package.scala:16:47] wire [61:0] _shin_T_52 = _shin_T_46[61:0]; // @[ALU.scala:106:46] wire [63:0] _shin_T_53 = {_shin_T_52, 2'h0}; // @[package.scala:16:47] wire [63:0] _shin_T_55 = _shin_T_53 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_56 = _shin_T_51 \| _shin_T_55; // @[ALU.scala:106:46] wire [62:0] _shin_T_60 = _shin_T_56[63:1]; // @[ALU.scala:106:46] wire [63:0] _shin_T_61 = {1'h0, _shin_T_60 & 63'h5555555555555555}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _shin_T_62 = _shin_T_56[62:0]; // @[ALU.scala:106:46] wire [63:0] _shin_T_63 = {_shin_T_62, 1'h0}; // @[ALU.scala:106:46] wire [63:0] _shin_T_65 = _shin_T_63 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_66 = _shin_T_61 \| _shin_T_65; // @[ALU.scala:106:46] wire [63:0] shin = _shin_T_7 ? _shin_T_66 : shin_r; // @[ALU.scala:64:33, :104:18, :106:{17,46}] wire _shout_r_T_1 = shin[63]; // @[ALU.scala:106:17, :107:41] wire _shout_r_T_2 = _shout_r_T & _shout_r_T_1; // @[ALU.scala:58:29, :107:{35,41}] wire [64:0] _shout_r_T_3 = {_shout_r_T_2, shin}; // @[ALU.scala:106:17, :107:{21,35}] wire [64:0] _shout_r_T_4 = _shout_r_T_3; // @[ALU.scala:107:{21,57}] wire [64:0] _shout_r_T_5 = $signed($signed(_shout_r_T_4) >>> shamt); // @[ALU.scala:103:22, :107:{57,64}] wire [63:0] shout_r = _shout_r_T_5[63:0]; // @[ALU.scala:107:{64,73}] wire [31:0] _shout_l_T_2 = shout_r[63:32]; // @[ALU.scala:107:73, :108:24] wire [63:0] _shout_l_T_3 = {32'h0, _shout_l_T_2}; // @[ALU.scala:108:24] wire [31:0] _shout_l_T_4 = shout_r[31:0]; // @[ALU.scala:107:73, :108:24] wire [63:0] _shout_l_T_5 = {_shout_l_T_4, 32'h0}; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_7 = _shout_l_T_5 & 64'hFFFFFFFF00000000; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_8 = _shout_l_T_3 \| _shout_l_T_7; // @[ALU.scala:108:24] wire [47:0] _shout_l_T_12 = _shout_l_T_8[63:16]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_13 = {16'h0, _shout_l_T_12 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _shout_l_T_14 = _shout_l_T_8[47:0]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_15 = {_shout_l_T_14, 16'h0}; // @[ALU.scala:106:46, :108:24] wire [63:0] _shout_l_T_17 = _shout_l_T_15 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_18 = _shout_l_T_13 \| _shout_l_T_17; // @[ALU.scala:108:24] wire [55:0] _shout_l_T_22 = _shout_l_T_18[63:8]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_23 = {8'h0, _shout_l_T_22 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _shout_l_T_24 = _shout_l_T_18[55:0]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_25 = {_shout_l_T_24, 8'h0}; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_27 = _shout_l_T_25 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_28 = _shout_l_T_23 \| _shout_l_T_27; // @[ALU.scala:108:24] wire [59:0] _shout_l_T_32 = _shout_l_T_28[63:4]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_33 = {4'h0, _shout_l_T_32 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _shout_l_T_34 = _shout_l_T_28[59:0]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_35 = {_shout_l_T_34, 4'h0}; // @[ALU.scala:106:46, :108:24] wire [63:0] _shout_l_T_37 = _shout_l_T_35 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_38 = _shout_l_T_33 \| _shout_l_T_37; // @[ALU.scala:108:24] wire [61:0] _shout_l_T_42 = _shout_l_T_38[63:2]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_43 = {2'h0, _shout_l_T_42 & 62'h3333333333333333}; // @[package.scala:16:47] wire [61:0] _shout_l_T_44 = _shout_l_T_38[61:0]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_45 = {_shout_l_T_44, 2'h0}; // @[package.scala:16:47] wire [63:0] _shout_l_T_47 = _shout_l_T_45 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_48 = _shout_l_T_43 \| _shout_l_T_47; // @[ALU.scala:108:24] wire [62:0] _shout_l_T_52 = _shout_l_T_48[63:1]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_53 = {1'h0, _shout_l_T_52 & 63'h5555555555555555}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _shout_l_T_54 = _shout_l_T_48[62:0]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_55 = {_shout_l_T_54, 1'h0}; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_57 = _shout_l_T_55 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] shout_l = _shout_l_T_53 \| _shout_l_T_57; // @[ALU.scala:108:24] wire _shout_T_2 = _shout_T \| _shout_T_1; // @[ALU.scala:109:{25,35,44}] wire _shout_T_4 = _shout_T_2 \| _shout_T_3; // @[ALU.scala:109:{35,55,64}] wire [63:0] _shout_T_5 = _shout_T_4 ? shout_r : 64'h0; // @[ALU.scala:107:73, :109:{18,55}] wire _shout_T_6 = io_fn_0 == 5'h1; // @[ALU.scala:83:7, :110:25] wire [63:0] _shout_T_7 = _shout_T_6 ? shout_l : 64'h0; // @[ALU.scala:108:24, :110:{18,25}] wire [63:0] shout = _shout_T_5 \| _shout_T_7; // @[ALU.scala:109:{18,91}, :110:18] wire [63:0] _shift_logic_T_5 = shout; // @[ALU.scala:109:91, :123:61] wire in2_not_zero = \|io_in2_0; // @[ALU.scala:83:7, :113:29] wire _logic_T = io_fn_0 == 5'h4; // @[ALU.scala:83:7, :119:25] wire _GEN_2 = io_fn_0 == 5'h6; // @[ALU.scala:83:7, :119:45] wire _logic_T_1; // @[ALU.scala:119:45] assign _logic_T_1 = _GEN_2; // @[ALU.scala:119:45] wire _logic_T_8; // @[ALU.scala:120:25] assign _logic_T_8 = _GEN_2; // @[ALU.scala:119:45, :120:25] wire _logic_T_2 = _logic_T \| _logic_T_1; // @[ALU.scala:119:{25,36,45}] wire _GEN_3 = io_fn_0 == 5'h19; // @[ALU.scala:83:7, :119:64] wire _logic_T_3; // @[ALU.scala:119:64] assign _logic_T_3 = _GEN_3; // @[ALU.scala:119:64] wire _logic_T_11; // @[ALU.scala:120:64] assign _logic_T_11 = _GEN_3; // @[ALU.scala:119:64, :120:64] wire _logic_T_4 = _logic_T_2 \| _logic_T_3; // @[ALU.scala:119:{36,55,64}] wire _logic_T_5 = io_fn_0 == 5'h1A; // @[ALU.scala:83:7, :119:84] wire _logic_T_6 = _logic_T_4 \| _logic_T_5; // @[ALU.scala:119:{55,75,84}] wire [63:0] _logic_T_7 = _logic_T_6 ? in1_xor_in2 : 64'h0; // @[ALU.scala:86:28, :119:{18,75}] wire _logic_T_9 = io_fn_0 == 5'h7; // @[ALU.scala:83:7, :120:44] wire _logic_T_10 = _logic_T_8 \| _logic_T_9; // @[ALU.scala:120:{25,35,44}] wire _logic_T_12 = _logic_T_10 \| _logic_T_11; // @[ALU.scala:120:{35,55,64}] wire _logic_T_13 = io_fn_0 == 5'h18; // @[ALU.scala:83:7, :120:84] wire _logic_T_14 = _logic_T_12 \| _logic_T_13; // @[ALU.scala:120:{55,75,84}] wire [63:0] _logic_T_15 = _logic_T_14 ? in1_and_in2 : 64'h0; // @[ALU.scala:87:28, :120:{18,75}] wire [63:0] logic_0 = _logic_T_7 \| _logic_T_15; // @[ALU.scala:119:{18,115}, :120:18] wire _shift_logic_T = io_fn_0 > 5'hB; // @[ALU.scala:59:31, :83:7] wire _shift_logic_T_1 = ~(io_fn_0[4]); // @[ALU.scala:59:48, :83:7] wire _shift_logic_T_2 = _shift_logic_T & _shift_logic_T_1; // @[ALU.scala:59:{31,41,48}] wire _shift_logic_T_3 = _shift_logic_T_2 & slt; // @[ALU.scala:59:41, :92:8, :123:36] wire [63:0] _shift_logic_T_4 = {63'h0, _shift_logic_T_3} \| logic_0; // @[ALU.scala:119:115, :123:{36,44}] wire [63:0] shift_logic = _shift_logic_T_4 \| _shift_logic_T_5; // @[ALU.scala:123:{44,52,61}] wire _tz_in_T = ~io_dw_0; // @[ALU.scala:83:7, :130:32] wire _tz_in_T_1 = io_in2_0[0]; // @[ALU.scala:83:7, :130:53] wire _tz_in_T_2 = ~_tz_in_T_1; // @[ALU.scala:130:{46,53}] wire [1:0] _tz_in_T_3 = {_tz_in_T, _tz_in_T_2}; // @[ALU.scala:130:{32,43,46}] wire [63:0] _tz_in_T_7 = {32'h0, _tz_in_T_6}; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_9 = {_tz_in_T_8, 32'h0}; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_11 = _tz_in_T_9 & 64'hFFFFFFFF00000000; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_12 = _tz_in_T_7 \| _tz_in_T_11; // @[ALU.scala:132:19] wire [47:0] _tz_in_T_16 = _tz_in_T_12[63:16]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_17 = {16'h0, _tz_in_T_16 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _tz_in_T_18 = _tz_in_T_12[47:0]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_19 = {_tz_in_T_18, 16'h0}; // @[ALU.scala:106:46, :132:19] wire [63:0] _tz_in_T_21 = _tz_in_T_19 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_22 = _tz_in_T_17 \| _tz_in_T_21; // @[ALU.scala:132:19] wire [55:0] _tz_in_T_26 = _tz_in_T_22[63:8]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_27 = {8'h0, _tz_in_T_26 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _tz_in_T_28 = _tz_in_T_22[55:0]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_29 = {_tz_in_T_28, 8'h0}; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_31 = _tz_in_T_29 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_32 = _tz_in_T_27 \| _tz_in_T_31; // @[ALU.scala:132:19] wire [59:0] _tz_in_T_36 = _tz_in_T_32[63:4]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_37 = {4'h0, _tz_in_T_36 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _tz_in_T_38 = _tz_in_T_32[59:0]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_39 = {_tz_in_T_38, 4'h0}; // @[ALU.scala:106:46, :132:19] wire [63:0] _tz_in_T_41 = _tz_in_T_39 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_42 = _tz_in_T_37 \| _tz_in_T_41; // @[ALU.scala:132:19] wire [61:0] _tz_in_T_46 = _tz_in_T_42[63:2]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_47 = {2'h0, _tz_in_T_46 & 62'h3333333333333333}; // @[package.scala:16:47] wire [61:0] _tz_in_T_48 = _tz_in_T_42[61:0]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_49 = {_tz_in_T_48, 2'h0}; // @[package.scala:16:47] wire [63:0] _tz_in_T_51 = _tz_in_T_49 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_52 = _tz_in_T_47 \| _tz_in_T_51; // @[ALU.scala:132:19] wire [62:0] _tz_in_T_56 = _tz_in_T_52[63:1]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_57 = {1'h0, _tz_in_T_56 & 63'h5555555555555555}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _tz_in_T_58 = _tz_in_T_52[62:0]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_59 = {_tz_in_T_58, 1'h0}; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_61 = _tz_in_T_59 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_62 = _tz_in_T_57 \| _tz_in_T_61; // @[ALU.scala:132:19] wire [32:0] _tz_in_T_64 = {1'h1, _tz_in_T_63}; // @[ALU.scala:133:{16,25}] wire [15:0] _tz_in_T_68 = _tz_in_T_65[31:16]; // @[ALU.scala:134:{26,33}] wire [31:0] _tz_in_T_69 = {16'h0, _tz_in_T_68}; // @[ALU.scala:106:46, :134:26] wire [15:0] _tz_in_T_70 = _tz_in_T_65[15:0]; // @[ALU.scala:134:{26,33}] wire [31:0] _tz_in_T_71 = {_tz_in_T_70, 16'h0}; // @[ALU.scala:106:46, :134:26] wire [31:0] _tz_in_T_73 = _tz_in_T_71 & 32'hFFFF0000; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_74 = _tz_in_T_69 \| _tz_in_T_73; // @[ALU.scala:134:26] wire [23:0] _tz_in_T_78 = _tz_in_T_74[31:8]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_79 = {8'h0, _tz_in_T_78 & 24'hFF00FF}; // @[ALU.scala:134:26] wire [23:0] _tz_in_T_80 = _tz_in_T_74[23:0]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_81 = {_tz_in_T_80, 8'h0}; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_83 = _tz_in_T_81 & 32'hFF00FF00; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_84 = _tz_in_T_79 \| _tz_in_T_83; // @[ALU.scala:134:26] wire [27:0] _tz_in_T_88 = _tz_in_T_84[31:4]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_89 = {4'h0, _tz_in_T_88 & 28'hF0F0F0F}; // @[ALU.scala:106:46, :134:26] wire [27:0] _tz_in_T_90 = _tz_in_T_84[27:0]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_91 = {_tz_in_T_90, 4'h0}; // @[ALU.scala:106:46, :134:26] wire [31:0] _tz_in_T_93 = _tz_in_T_91 & 32'hF0F0F0F0; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_94 = _tz_in_T_89 \| _tz_in_T_93; // @[ALU.scala:134:26] wire [29:0] _tz_in_T_98 = _tz_in_T_94[31:2]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_99 = {2'h0, _tz_in_T_98 & 30'h33333333}; // @[package.scala:16:47] wire [29:0] _tz_in_T_100 = _tz_in_T_94[29:0]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_101 = {_tz_in_T_100, 2'h0}; // @[package.scala:16:47] wire [31:0] _tz_in_T_103 = _tz_in_T_101 & 32'hCCCCCCCC; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_104 = _tz_in_T_99 \| _tz_in_T_103; // @[ALU.scala:134:26] wire [30:0] _tz_in_T_108 = _tz_in_T_104[31:1]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_109 = {1'h0, _tz_in_T_108 & 31'h55555555}; // @[ALU.scala:134:26] wire [30:0] _tz_in_T_110 = _tz_in_T_104[30:0]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_111 = {_tz_in_T_110, 1'h0}; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_113 = _tz_in_T_111 & 32'hAAAAAAAA; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_114 = _tz_in_T_109 \| _tz_in_T_113; // @[ALU.scala:134:26] wire [32:0] _tz_in_T_115 = {1'h1, _tz_in_T_114}; // @[ALU.scala:134:{16,26}] wire _tz_in_T_116 = _tz_in_T_3 == 2'h1; // @[ALU.scala:130:{43,62}] wire [63:0] _tz_in_T_117 = _tz_in_T_116 ? _tz_in_T_62 : io_in1_0; // @[ALU.scala:83:7, :130:62, :132:19] wire _tz_in_T_118 = _tz_in_T_3 == 2'h2; // @[ALU.scala:130:{43,62}] wire [63:0] _tz_in_T_119 = _tz_in_T_118 ? {31'h0, _tz_in_T_64} : _tz_in_T_117; // @[ALU.scala:130:62, :133:16] wire _tz_in_T_120 = &_tz_in_T_3; // @[ALU.scala:130:{43,62}] wire [63:0] tz_in = _tz_in_T_120 ? {31'h0, _tz_in_T_115} : _tz_in_T_119; // @[ALU.scala:130:62, :134:16] wire _popc_in_T = io_in2_0[1]; // @[ALU.scala:83:7, :136:27] wire _popc_in_T_1 = ~io_dw_0; // @[ALU.scala:83:7, :130:32, :137:15] wire [63:0] _popc_in_T_3 = _popc_in_T_1 ? {32'h0, _popc_in_T_2} : io_in1_0; // @[ALU.scala:83:7, :137:{8,15,32}] wire [64:0] _popc_in_T_4 = {1'h1, tz_in}; // @[ALU.scala:130:62, :138:27] wire _popc_in_T_5 = _popc_in_T_4[0]; // @[OneHot.scala:85:71] wire _popc_in_T_6 = _popc_in_T_4[1]; // @[OneHot.scala:85:71] wire _popc_in_T_7 = _popc_in_T_4[2]; // @[OneHot.scala:85:71] wire _popc_in_T_8 = _popc_in_T_4[3]; // @[OneHot.scala:85:71] wire _popc_in_T_9 = _popc_in_T_4[4]; // @[OneHot.scala:85:71] wire _popc_in_T_10 = _popc_in_T_4[5]; // @[OneHot.scala:85:71] wire _popc_in_T_11 = _popc_in_T_4[6]; // @[OneHot.scala:85:71] wire _popc_in_T_12 = _popc_in_T_4[7]; // @[OneHot.scala:85:71] wire _popc_in_T_13 = _popc_in_T_4[8]; // @[OneHot.scala:85:71] wire _popc_in_T_14 = _popc_in_T_4[9]; // @[OneHot.scala:85:71] wire _popc_in_T_15 = _popc_in_T_4[10]; // @[OneHot.scala:85:71] wire _popc_in_T_16 = _popc_in_T_4[11]; // @[OneHot.scala:85:71] wire _popc_in_T_17 = _popc_in_T_4[12]; // @[OneHot.scala:85:71] wire _popc_in_T_18 = _popc_in_T_4[13]; // @[OneHot.scala:85:71] wire _popc_in_T_19 = _popc_in_T_4[14]; // @[OneHot.scala:85:71] wire _popc_in_T_20 = _popc_in_T_4[15]; // @[OneHot.scala:85:71] wire _popc_in_T_21 = _popc_in_T_4[16]; // @[OneHot.scala:85:71] wire _popc_in_T_22 = _popc_in_T_4[17]; // @[OneHot.scala:85:71] wire _popc_in_T_23 = _popc_in_T_4[18]; // @[OneHot.scala:85:71] wire _popc_in_T_24 = _popc_in_T_4[19]; // @[OneHot.scala:85:71] wire _popc_in_T_25 = _popc_in_T_4[20]; // @[OneHot.scala:85:71] wire _popc_in_T_26 = _popc_in_T_4[21]; // @[OneHot.scala:85:71] wire _popc_in_T_27 = _popc_in_T_4[22]; // @[OneHot.scala:85:71] wire _popc_in_T_28 = _popc_in_T_4[23]; // @[OneHot.scala:85:71] wire _popc_in_T_29 = _popc_in_T_4[24]; // @[OneHot.scala:85:71] wire _popc_in_T_30 = _popc_in_T_4[25]; // @[OneHot.scala:85:71] wire _popc_in_T_31 = _popc_in_T_4[26]; // @[OneHot.scala:85:71] wire _popc_in_T_32 = _popc_in_T_4[27]; // @[OneHot.scala:85:71] wire _popc_in_T_33 = _popc_in_T_4[28]; // @[OneHot.scala:85:71] wire _popc_in_T_34 = _popc_in_T_4[29]; // @[OneHot.scala:85:71] wire _popc_in_T_35 = _popc_in_T_4[30]; // @[OneHot.scala:85:71] wire _popc_in_T_36 = _popc_in_T_4[31]; // @[OneHot.scala:85:71] wire _popc_in_T_37 = _popc_in_T_4[32]; // @[OneHot.scala:85:71] wire _popc_in_T_38 = _popc_in_T_4[33]; // @[OneHot.scala:85:71] wire _popc_in_T_39 = _popc_in_T_4[34]; // @[OneHot.scala:85:71] wire _popc_in_T_40 = _popc_in_T_4[35]; // @[OneHot.scala:85:71] wire _popc_in_T_41 = _popc_in_T_4[36]; // @[OneHot.scala:85:71] wire _popc_in_T_42 = _popc_in_T_4[37]; // @[OneHot.scala:85:71] wire _popc_in_T_43 = _popc_in_T_4[38]; // @[OneHot.scala:85:71] wire _popc_in_T_44 = _popc_in_T_4[39]; // @[OneHot.scala:85:71] wire _popc_in_T_45 = _popc_in_T_4[40]; // @[OneHot.scala:85:71] wire _popc_in_T_46 = _popc_in_T_4[41]; // @[OneHot.scala:85:71] wire _popc_in_T_47 = _popc_in_T_4[42]; // @[OneHot.scala:85:71] wire _popc_in_T_48 = _popc_in_T_4[43]; // @[OneHot.scala:85:71] wire _popc_in_T_49 = _popc_in_T_4[44]; // @[OneHot.scala:85:71] wire _popc_in_T_50 = _popc_in_T_4[45]; // @[OneHot.scala:85:71] wire _popc_in_T_51 = _popc_in_T_4[46]; // @[OneHot.scala:85:71] wire _popc_in_T_52 = _popc_in_T_4[47]; // @[OneHot.scala:85:71] wire _popc_in_T_53 = _popc_in_T_4[48]; // @[OneHot.scala:85:71] wire _popc_in_T_54 = _popc_in_T_4[49]; // @[OneHot.scala:85:71] wire _popc_in_T_55 = _popc_in_T_4[50]; // @[OneHot.scala:85:71] wire _popc_in_T_56 = _popc_in_T_4[51]; // @[OneHot.scala:85:71] wire _popc_in_T_57 = _popc_in_T_4[52]; // @[OneHot.scala:85:71] wire _popc_in_T_58 = _popc_in_T_4[53]; // @[OneHot.scala:85:71] wire _popc_in_T_59 = _popc_in_T_4[54]; // @[OneHot.scala:85:71] wire _popc_in_T_60 = _popc_in_T_4[55]; // @[OneHot.scala:85:71] wire _popc_in_T_61 = _popc_in_T_4[56]; // @[OneHot.scala:85:71] wire _popc_in_T_62 = _popc_in_T_4[57]; // @[OneHot.scala:85:71] wire _popc_in_T_63 = _popc_in_T_4[58]; // @[OneHot.scala:85:71] wire _popc_in_T_64 = _popc_in_T_4[59]; // @[OneHot.scala:85:71] wire _popc_in_T_65 = _popc_in_T_4[60]; // @[OneHot.scala:85:71] wire _popc_in_T_66 = _popc_in_T_4[61]; // @[OneHot.scala:85:71] wire _popc_in_T_67 = _popc_in_T_4[62]; // @[OneHot.scala:85:71] wire _popc_in_T_68 = _popc_in_T_4[63]; // @[OneHot.scala:85:71] wire _popc_in_T_69 = _popc_in_T_4[64]; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_70 = {_popc_in_T_69, 64'h0}; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_71 = _popc_in_T_68 ? 65'h8000000000000000 : _popc_in_T_70; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_72 = _popc_in_T_67 ? 65'h4000000000000000 : _popc_in_T_71; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_73 = _popc_in_T_66 ? 65'h2000000000000000 : _popc_in_T_72; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_74 = _popc_in_T_65 ? 65'h1000000000000000 : _popc_in_T_73; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_75 = _popc_in_T_64 ? 65'h800000000000000 : _popc_in_T_74; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_76 = _popc_in_T_63 ? 65'h400000000000000 : _popc_in_T_75; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_77 = _popc_in_T_62 ? 65'h200000000000000 : _popc_in_T_76; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_78 = _popc_in_T_61 ? 65'h100000000000000 : _popc_in_T_77; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_79 = _popc_in_T_60 ? 65'h80000000000000 : _popc_in_T_78; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_80 = _popc_in_T_59 ? 65'h40000000000000 : _popc_in_T_79; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_81 = _popc_in_T_58 ? 65'h20000000000000 : _popc_in_T_80; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_82 = _popc_in_T_57 ? 65'h10000000000000 : _popc_in_T_81; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_83 = _popc_in_T_56 ? 65'h8000000000000 : _popc_in_T_82; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_84 = _popc_in_T_55 ? 65'h4000000000000 : _popc_in_T_83; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_85 = _popc_in_T_54 ? 65'h2000000000000 : _popc_in_T_84; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_86 = _popc_in_T_53 ? 65'h1000000000000 : _popc_in_T_85; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_87 = _popc_in_T_52 ? 65'h800000000000 : _popc_in_T_86; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_88 = _popc_in_T_51 ? 65'h400000000000 : _popc_in_T_87; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_89 = _popc_in_T_50 ? 65'h200000000000 : _popc_in_T_88; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_90 = _popc_in_T_49 ? 65'h100000000000 : _popc_in_T_89; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_91 = _popc_in_T_48 ? 65'h80000000000 : _popc_in_T_90; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_92 = _popc_in_T_47 ? 65'h40000000000 : _popc_in_T_91; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_93 = _popc_in_T_46 ? 65'h20000000000 : _popc_in_T_92; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_94 = _popc_in_T_45 ? 65'h10000000000 : _popc_in_T_93; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_95 = _popc_in_T_44 ? 65'h8000000000 : _popc_in_T_94; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_96 = _popc_in_T_43 ? 65'h4000000000 : _popc_in_T_95; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_97 = _popc_in_T_42 ? 65'h2000000000 : _popc_in_T_96; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_98 = _popc_in_T_41 ? 65'h1000000000 : _popc_in_T_97; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_99 = _popc_in_T_40 ? 65'h800000000 : _popc_in_T_98; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_100 = _popc_in_T_39 ? 65'h400000000 : _popc_in_T_99; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_101 = _popc_in_T_38 ? 65'h200000000 : _popc_in_T_100; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_102 = _popc_in_T_37 ? 65'h100000000 : _popc_in_T_101; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_103 = _popc_in_T_36 ? 65'h80000000 : _popc_in_T_102; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_104 = _popc_in_T_35 ? 65'h40000000 : _popc_in_T_103; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_105 = _popc_in_T_34 ? 65'h20000000 : _popc_in_T_104; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_106 = _popc_in_T_33 ? 65'h10000000 : _popc_in_T_105; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_107 = _popc_in_T_32 ? 65'h8000000 : _popc_in_T_106; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_108 = _popc_in_T_31 ? 65'h4000000 : _popc_in_T_107; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_109 = _popc_in_T_30 ? 65'h2000000 : _popc_in_T_108; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_110 = _popc_in_T_29 ? 65'h1000000 : _popc_in_T_109; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_111 = _popc_in_T_28 ? 65'h800000 : _popc_in_T_110; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_112 = _popc_in_T_27 ? 65'h400000 : _popc_in_T_111; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_113 = _popc_in_T_26 ? 65'h200000 : _popc_in_T_112; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_114 = _popc_in_T_25 ? 65'h100000 : _popc_in_T_113; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_115 = _popc_in_T_24 ? 65'h80000 : _popc_in_T_114; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_116 = _popc_in_T_23 ? 65'h40000 : _popc_in_T_115; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_117 = _popc_in_T_22 ? 65'h20000 : _popc_in_T_116; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_118 = _popc_in_T_21 ? 65'h10000 : _popc_in_T_117; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_119 = _popc_in_T_20 ? 65'h8000 : _popc_in_T_118; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_120 = _popc_in_T_19 ? 65'h4000 : _popc_in_T_119; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_121 = _popc_in_T_18 ? 65'h2000 : _popc_in_T_120; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_122 = _popc_in_T_17 ? 65'h1000 : _popc_in_T_121; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_123 = _popc_in_T_16 ? 65'h800 : _popc_in_T_122; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_124 = _popc_in_T_15 ? 65'h400 : _popc_in_T_123; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_125 = _popc_in_T_14 ? 65'h200 : _popc_in_T_124; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_126 = _popc_in_T_13 ? 65'h100 : _popc_in_T_125; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_127 = _popc_in_T_12 ? 65'h80 : _popc_in_T_126; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_128 = _popc_in_T_11 ? 65'h40 : _popc_in_T_127; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_129 = _popc_in_T_10 ? 65'h20 : _popc_in_T_128; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_130 = _popc_in_T_9 ? 65'h10 : _popc_in_T_129; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_131 = _popc_in_T_8 ? 65'h8 : _popc_in_T_130; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_132 = _popc_in_T_7 ? 65'h4 : _popc_in_T_131; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_133 = _popc_in_T_6 ? 65'h2 : _popc_in_T_132; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_134 = _popc_in_T_5 ? 65'h1 : _popc_in_T_133; // @[OneHot.scala:85:71] wire [65:0] _popc_in_T_135 = {1'h0, _popc_in_T_134} - 66'h1; // @[Mux.scala:50:70] wire [64:0] _popc_in_T_136 = _popc_in_T_135[64:0]; // @[ALU.scala:138:37] wire [64:0] _popc_in_T_137 = _popc_in_T ? {1'h0, _popc_in_T_3} : _popc_in_T_136; // @[ALU.scala:136:{20,27}, :137:8, :138:37] wire [63:0] popc_in = _popc_in_T_137[63:0]; // @[ALU.scala:136:20, :138:43] wire _count_T = popc_in[0]; // @[ALU.scala:138:43, :139:23] wire _count_T_1 = popc_in[1]; // @[ALU.scala:138:43, :139:23] wire _count_T_2 = popc_in[2]; // @[ALU.scala:138:43, :139:23] wire _count_T_3 = popc_in[3]; // @[ALU.scala:138:43, :139:23] wire _count_T_4 = popc_in[4]; // @[ALU.scala:138:43, :139:23] wire _count_T_5 = popc_in[5]; // @[ALU.scala:138:43, :139:23] wire _count_T_6 = popc_in[6]; // @[ALU.scala:138:43, :139:23] wire _count_T_7 = popc_in[7]; // @[ALU.scala:138:43, :139:23] wire _count_T_8 = popc_in[8]; // @[ALU.scala:138:43, :139:23] wire _count_T_9 = popc_in[9]; // @[ALU.scala:138:43, :139:23] wire _count_T_10 = popc_in[10]; // @[ALU.scala:138:43, :139:23] wire _count_T_11 = popc_in[11]; // @[ALU.scala:138:43, :139:23] wire _count_T_12 = popc_in[12]; // @[ALU.scala:138:43, :139:23] wire _count_T_13 = popc_in[13]; // @[ALU.scala:138:43, :139:23] wire _count_T_14 = popc_in[14]; // @[ALU.scala:138:43, :139:23] wire _count_T_15 = popc_in[15]; // @[ALU.scala:138:43, :139:23] wire _count_T_16 = popc_in[16]; // @[ALU.scala:138:43, :139:23] wire _count_T_17 = popc_in[17]; // @[ALU.scala:138:43, :139:23] wire _count_T_18 = popc_in[18]; // @[ALU.scala:138:43, :139:23] wire _count_T_19 = popc_in[19]; // @[ALU.scala:138:43, :139:23] wire _count_T_20 = popc_in[20]; // @[ALU.scala:138:43, :139:23] wire _count_T_21 = popc_in[21]; // @[ALU.scala:138:43, :139:23] wire _count_T_22 = popc_in[22]; // @[ALU.scala:138:43, :139:23] wire _count_T_23 = popc_in[23]; // @[ALU.scala:138:43, :139:23] wire _count_T_24 = popc_in[24]; // @[ALU.scala:138:43, :139:23] wire _count_T_25 = popc_in[25]; // @[ALU.scala:138:43, :139:23] wire _count_T_26 = popc_in[26]; // @[ALU.scala:138:43, :139:23] wire _count_T_27 = popc_in[27]; // @[ALU.scala:138:43, :139:23] wire _count_T_28 = popc_in[28]; // @[ALU.scala:138:43, :139:23] wire _count_T_29 = popc_in[29]; // @[ALU.scala:138:43, :139:23] wire _count_T_30 = popc_in[30]; // @[ALU.scala:138:43, :139:23] wire _count_T_31 = popc_in[31]; // @[ALU.scala:138:43, :139:23] wire _count_T_32 = popc_in[32]; // @[ALU.scala:138:43, :139:23] wire _count_T_33 = popc_in[33]; // @[ALU.scala:138:43, :139:23] wire _count_T_34 = popc_in[34]; // @[ALU.scala:138:43, :139:23] wire _count_T_35 = popc_in[35]; // @[ALU.scala:138:43, :139:23] wire _count_T_36 = popc_in[36]; // @[ALU.scala:138:43, :139:23] wire _count_T_37 = popc_in[37]; // @[ALU.scala:138:43, :139:23] wire _count_T_38 = popc_in[38]; // @[ALU.scala:138:43, :139:23] wire _count_T_39 = popc_in[39]; // @[ALU.scala:138:43, :139:23] wire _count_T_40 = popc_in[40]; // @[ALU.scala:138:43, :139:23] wire _count_T_41 = popc_in[41]; // @[ALU.scala:138:43, :139:23] wire _count_T_42 = popc_in[42]; // @[ALU.scala:138:43, :139:23] wire _count_T_43 = popc_in[43]; // @[ALU.scala:138:43, :139:23] wire _count_T_44 = popc_in[44]; // @[ALU.scala:138:43, :139:23] wire _count_T_45 = popc_in[45]; // @[ALU.scala:138:43, :139:23] wire _count_T_46 = popc_in[46]; // @[ALU.scala:138:43, :139:23] wire _count_T_47 = popc_in[47]; // @[ALU.scala:138:43, :139:23] wire _count_T_48 = popc_in[48]; // @[ALU.scala:138:43, :139:23] wire _count_T_49 = popc_in[49]; // @[ALU.scala:138:43, :139:23] wire _count_T_50 = popc_in[50]; // @[ALU.scala:138:43, :139:23] wire _count_T_51 = popc_in[51]; // @[ALU.scala:138:43, :139:23] wire _count_T_52 = popc_in[52]; // @[ALU.scala:138:43, :139:23] wire _count_T_53 = popc_in[53]; // @[ALU.scala:138:43, :139:23] wire _count_T_54 = popc_in[54]; // @[ALU.scala:138:43, :139:23] wire _count_T_55 = popc_in[55]; // @[ALU.scala:138:43, :139:23] wire _count_T_56 = popc_in[56]; // @[ALU.scala:138:43, :139:23] wire _count_T_57 = popc_in[57]; // @[ALU.scala:138:43, :139:23] wire _count_T_58 = popc_in[58]; // @[ALU.scala:138:43, :139:23] wire _count_T_59 = popc_in[59]; // @[ALU.scala:138:43, :139:23] wire _count_T_60 = popc_in[60]; // @[ALU.scala:138:43, :139:23] wire _count_T_61 = popc_in[61]; // @[ALU.scala:138:43, :139:23] wire _count_T_62 = popc_in[62]; // @[ALU.scala:138:43, :139:23] wire _count_T_63 = popc_in[63]; // @[ALU.scala:138:43, :139:23] wire [1:0] _count_T_64 = {1'h0, _count_T} + {1'h0, _count_T_1}; // @[ALU.scala:139:23] wire [1:0] _count_T_65 = _count_T_64; // @[ALU.scala:139:23] wire [1:0] _count_T_66 = {1'h0, _count_T_2} + {1'h0, _count_T_3}; // @[ALU.scala:139:23] wire [1:0] _count_T_67 = _count_T_66; // @[ALU.scala:139:23] wire [2:0] _count_T_68 = {1'h0, _count_T_65} + {1'h0, _count_T_67}; // @[ALU.scala:139:23] wire [2:0] _count_T_69 = _count_T_68; // @[ALU.scala:139:23] wire [1:0] _count_T_70 = {1'h0, _count_T_4} + {1'h0, _count_T_5}; // @[ALU.scala:139:23] wire [1:0] _count_T_71 = _count_T_70; // @[ALU.scala:139:23] wire [1:0] _count_T_72 = {1'h0, _count_T_6} + {1'h0, _count_T_7}; // @[ALU.scala:139:23] wire [1:0] _count_T_73 = _count_T_72; // @[ALU.scala:139:23] wire [2:0] _count_T_74 = {1'h0, _count_T_71} + {1'h0, _count_T_73}; // @[ALU.scala:139:23] wire [2:0] _count_T_75 = _count_T_74; // @[ALU.scala:139:23] wire [3:0] _count_T_76 = {1'h0, _count_T_69} + {1'h0, _count_T_75}; // @[ALU.scala:139:23] wire [3:0] _count_T_77 = _count_T_76; // @[ALU.scala:139:23] wire [1:0] _count_T_78 = {1'h0, _count_T_8} + {1'h0, _count_T_9}; // @[ALU.scala:139:23] wire [1:0] _count_T_79 = _count_T_78; // @[ALU.scala:139:23] wire [1:0] _count_T_80 = {1'h0, _count_T_10} + {1'h0, _count_T_11}; // @[ALU.scala:139:23] wire [1:0] _count_T_81 = _count_T_80; // @[ALU.scala:139:23] wire [2:0] _count_T_82 = {1'h0, _count_T_79} + {1'h0, _count_T_81}; // @[ALU.scala:139:23] wire [2:0] _count_T_83 = _count_T_82; // @[ALU.scala:139:23] wire [1:0] _count_T_84 = {1'h0, _count_T_12} + {1'h0, _count_T_13}; // @[ALU.scala:139:23] wire [1:0] _count_T_85 = _count_T_84; // @[ALU.scala:139:23] wire [1:0] _count_T_86 = {1'h0, _count_T_14} + {1'h0, _count_T_15}; // @[ALU.scala:139:23] wire [1:0] _count_T_87 = _count_T_86; // @[ALU.scala:139:23] wire [2:0] _count_T_88 = {1'h0, _count_T_85} + {1'h0, _count_T_87}; // @[ALU.scala:139:23] wire [2:0] _count_T_89 = _count_T_88; // @[ALU.scala:139:23] wire [3:0] _count_T_90 = {1'h0, _count_T_83} + {1'h0, _count_T_89}; // @[ALU.scala:139:23] wire [3:0] _count_T_91 = _count_T_90; // @[ALU.scala:139:23] wire [4:0] _count_T_92 = {1'h0, _count_T_77} + {1'h0, _count_T_91}; // @[ALU.scala:139:23] wire [4:0] _count_T_93 = _count_T_92; // @[ALU.scala:139:23] wire [1:0] _count_T_94 = {1'h0, _count_T_16} + {1'h0, _count_T_17}; // @[ALU.scala:139:23] wire [1:0] _count_T_95 = _count_T_94; // @[ALU.scala:139:23] wire [1:0] _count_T_96 = {1'h0, _count_T_18} + {1'h0, _count_T_19}; // @[ALU.scala:139:23] wire [1:0] _count_T_97 = _count_T_96; // @[ALU.scala:139:23] wire [2:0] _count_T_98 = {1'h0, _count_T_95} + {1'h0, _count_T_97}; // @[ALU.scala:139:23] wire [2:0] _count_T_99 = _count_T_98; // @[ALU.scala:139:23] wire [1:0] _count_T_100 = {1'h0, _count_T_20} + {1'h0, _count_T_21}; // @[ALU.scala:139:23] wire [1:0] _count_T_101 = _count_T_100; // @[ALU.scala:139:23] wire [1:0] _count_T_102 = {1'h0, _count_T_22} + {1'h0, _count_T_23}; // @[ALU.scala:139:23] wire [1:0] _count_T_103 = _count_T_102; // @[ALU.scala:139:23] wire [2:0] _count_T_104 = {1'h0, _count_T_101} + {1'h0, _count_T_103}; // @[ALU.scala:139:23] wire [2:0] _count_T_105 = _count_T_104; // @[ALU.scala:139:23] wire [3:0] _count_T_106 = {1'h0, _count_T_99} + {1'h0, _count_T_105}; // @[ALU.scala:139:23] wire [3:0] _count_T_107 = _count_T_106; // @[ALU.scala:139:23] wire [1:0] _count_T_108 = {1'h0, _count_T_24} + {1'h0, _count_T_25}; // @[ALU.scala:139:23] wire [1:0] _count_T_109 = _count_T_108; // @[ALU.scala:139:23] wire [1:0] _count_T_110 = {1'h0, _count_T_26} + {1'h0, _count_T_27}; // @[ALU.scala:139:23] wire [1:0] _count_T_111 = _count_T_110; // @[ALU.scala:139:23] wire [2:0] _count_T_112 = {1'h0, _count_T_109} + {1'h0, _count_T_111}; // @[ALU.scala:139:23] wire [2:0] _count_T_113 = _count_T_112; // @[ALU.scala:139:23] wire [1:0] _count_T_114 = {1'h0, _count_T_28} + {1'h0, _count_T_29}; // @[ALU.scala:139:23] wire [1:0] _count_T_115 = _count_T_114; // @[ALU.scala:139:23] wire [1:0] _count_T_116 = {1'h0, _count_T_30} + {1'h0, _count_T_31}; // @[ALU.scala:139:23] wire [1:0] _count_T_117 = _count_T_116; // @[ALU.scala:139:23] wire [2:0] _count_T_118 = {1'h0, _count_T_115} + {1'h0, _count_T_117}; // @[ALU.scala:139:23] wire [2:0] _count_T_119 = _count_T_118; // @[ALU.scala:139:23] wire [3:0] _count_T_120 = {1'h0, _count_T_113} + {1'h0, _count_T_119}; // @[ALU.scala:139:23] wire [3:0] _count_T_121 = _count_T_120; // @[ALU.scala:139:23] wire [4:0] _count_T_122 = {1'h0, _count_T_107} + {1'h0, _count_T_121}; // @[ALU.scala:139:23] wire [4:0] _count_T_123 = _count_T_122; // @[ALU.scala:139:23] wire [5:0] _count_T_124 = {1'h0, _count_T_93} + {1'h0, _count_T_123}; // @[ALU.scala:139:23] wire [5:0] _count_T_125 = _count_T_124; // @[ALU.scala:139:23] wire [1:0] _count_T_126 = {1'h0, _count_T_32} + {1'h0, _count_T_33}; // @[ALU.scala:139:23] wire [1:0] _count_T_127 = _count_T_126; // @[ALU.scala:139:23] wire [1:0] _count_T_128 = {1'h0, _count_T_34} + {1'h0, _count_T_35}; // @[ALU.scala:139:23] wire [1:0] _count_T_129 = _count_T_128; // @[ALU.scala:139:23] wire [2:0] _count_T_130 = {1'h0, _count_T_127} + {1'h0, _count_T_129}; // @[ALU.scala:139:23] wire [2:0] _count_T_131 = _count_T_130; // @[ALU.scala:139:23] wire [1:0] _count_T_132 = {1'h0, _count_T_36} + {1'h0, _count_T_37}; // @[ALU.scala:139:23] wire [1:0] _count_T_133 = _count_T_132; // @[ALU.scala:139:23] wire [1:0] _count_T_134 = {1'h0, _count_T_38} + {1'h0, _count_T_39}; // @[ALU.scala:139:23] wire [1:0] _count_T_135 = _count_T_134; // @[ALU.scala:139:23] wire [2:0] _count_T_136 = {1'h0, _count_T_133} + {1'h0, _count_T_135}; // @[ALU.scala:139:23] wire [2:0] _count_T_137 = _count_T_136; // @[ALU.scala:139:23] wire [3:0] _count_T_138 = {1'h0, _count_T_131} + {1'h0, _count_T_137}; // @[ALU.scala:139:23] wire [3:0] _count_T_139 = _count_T_138; // @[ALU.scala:139:23] wire [1:0] _count_T_140 = {1'h0, _count_T_40} + {1'h0, _count_T_41}; // @[ALU.scala:139:23] wire [1:0] _count_T_141 = _count_T_140; // @[ALU.scala:139:23] wire [1:0] _count_T_142 = {1'h0, _count_T_42} + {1'h0, _count_T_43}; // @[ALU.scala:139:23] wire [1:0] _count_T_143 = _count_T_142; // @[ALU.scala:139:23] wire [2:0] _count_T_144 = {1'h0, _count_T_141} + {1'h0, _count_T_143}; // @[ALU.scala:139:23] wire [2:0] _count_T_145 = _count_T_144; // @[ALU.scala:139:23] wire [1:0] _count_T_146 = {1'h0, _count_T_44} + {1'h0, _count_T_45}; // @[ALU.scala:139:23] wire [1:0] _count_T_147 = _count_T_146; // @[ALU.scala:139:23] wire [1:0] _count_T_148 = {1'h0, _count_T_46} + {1'h0, _count_T_47}; // @[ALU.scala:139:23] wire [1:0] _count_T_149 = _count_T_148; // @[ALU.scala:139:23] wire [2:0] _count_T_150 = {1'h0, _count_T_147} + {1'h0, _count_T_149}; // @[ALU.scala:139:23] wire [2:0] _count_T_151 = _count_T_150; // @[ALU.scala:139:23] wire [3:0] _count_T_152 = {1'h0, _count_T_145} + {1'h0, _count_T_151}; // @[ALU.scala:139:23] wire [3:0] _count_T_153 = _count_T_152; // @[ALU.scala:139:23] wire [4:0] _count_T_154 = {1'h0, _count_T_139} + {1'h0, _count_T_153}; // @[ALU.scala:139:23] wire [4:0] _count_T_155 = _count_T_154; // @[ALU.scala:139:23] wire [1:0] _count_T_156 = {1'h0, _count_T_48} + {1'h0, _count_T_49}; // @[ALU.scala:139:23] wire [1:0] _count_T_157 = _count_T_156; // @[ALU.scala:139:23] wire [1:0] _count_T_158 = {1'h0, _count_T_50} + {1'h0, _count_T_51}; // @[ALU.scala:139:23] wire [1:0] _count_T_159 = _count_T_158; // @[ALU.scala:139:23] wire [2:0] _count_T_160 = {1'h0, _count_T_157} + {1'h0, _count_T_159}; // @[ALU.scala:139:23] wire [2:0] _count_T_161 = _count_T_160; // @[ALU.scala:139:23] wire [1:0] _count_T_162 = {1'h0, _count_T_52} + {1'h0, _count_T_53}; // @[ALU.scala:139:23] wire [1:0] _count_T_163 = _count_T_162; // @[ALU.scala:139:23] wire [1:0] _count_T_164 = {1'h0, _count_T_54} + {1'h0, _count_T_55}; // @[ALU.scala:139:23] wire [1:0] _count_T_165 = _count_T_164; // @[ALU.scala:139:23] wire [2:0] _count_T_166 = {1'h0, _count_T_163} + {1'h0, _count_T_165}; // @[ALU.scala:139:23] wire [2:0] _count_T_167 = _count_T_166; // @[ALU.scala:139:23] wire [3:0] _count_T_168 = {1'h0, _count_T_161} + {1'h0, _count_T_167}; // @[ALU.scala:139:23] wire [3:0] _count_T_169 = _count_T_168; // @[ALU.scala:139:23] wire [1:0] _count_T_170 = {1'h0, _count_T_56} + {1'h0, _count_T_57}; // @[ALU.scala:139:23] wire [1:0] _count_T_171 = _count_T_170; // @[ALU.scala:139:23] wire [1:0] _count_T_172 = {1'h0, _count_T_58} + {1'h0, _count_T_59}; // @[ALU.scala:139:23] wire [1:0] _count_T_173 = _count_T_172; // @[ALU.scala:139:23] wire [2:0] _count_T_174 = {1'h0, _count_T_171} + {1'h0, _count_T_173}; // @[ALU.scala:139:23] wire [2:0] _count_T_175 = _count_T_174; // @[ALU.scala:139:23] wire [1:0] _count_T_176 = {1'h0, _count_T_60} + {1'h0, _count_T_61}; // @[ALU.scala:139:23] wire [1:0] _count_T_177 = _count_T_176; // @[ALU.scala:139:23] wire [1:0] _count_T_178 = {1'h0, _count_T_62} + {1'h0, _count_T_63}; // @[ALU.scala:139:23] wire [1:0] _count_T_179 = _count_T_178; // @[ALU.scala:139:23] wire [2:0] _count_T_180 = {1'h0, _count_T_177} + {1'h0, _count_T_179}; // @[ALU.scala:139:23] wire [2:0] _count_T_181 = _count_T_180; // @[ALU.scala:139:23] wire [3:0] _count_T_182 = {1'h0, _count_T_175} + {1'h0, _count_T_181}; // @[ALU.scala:139:23] wire [3:0] _count_T_183 = _count_T_182; // @[ALU.scala:139:23] wire [4:0] _count_T_184 = {1'h0, _count_T_169} + {1'h0, _count_T_183}; // @[ALU.scala:139:23] wire [4:0] _count_T_185 = _count_T_184; // @[ALU.scala:139:23] wire [5:0] _count_T_186 = {1'h0, _count_T_155} + {1'h0, _count_T_185}; // @[ALU.scala:139:23] wire [5:0] _count_T_187 = _count_T_186; // @[ALU.scala:139:23] wire [6:0] _count_T_188 = {1'h0, _count_T_125} + {1'h0, _count_T_187}; // @[ALU.scala:139:23] wire [6:0] count = _count_T_188; // @[ALU.scala:139:23] wire [7:0] _in1_bytes_T; // @[ALU.scala:140:34] wire [7:0] _in1_bytes_T_1; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_7 = in1_bytes_0; // @[ALU.scala:140:34, :142:21] wire [7:0] _in1_bytes_T_2; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_6 = in1_bytes_1; // @[ALU.scala:140:34, :142:21] wire [7:0] _in1_bytes_T_3; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_5 = in1_bytes_2; // @[ALU.scala:140:34, :142:21] wire [7:0] _in1_bytes_T_4; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_4 = in1_bytes_3; // @[ALU.scala:140:34, :142:21] wire [7:0] _in1_bytes_T_5; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_3 = in1_bytes_4; // @[ALU.scala:140:34, :142:21] wire [7:0] _in1_bytes_T_6; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_2 = in1_bytes_5; // @[ALU.scala:140:34, :142:21] wire [7:0] _in1_bytes_T_7; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_1 = in1_bytes_6; // @[ALU.scala:140:34, :142:21] wire [7:0] in1_bytes_7; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_0 = in1_bytes_7; // @[ALU.scala:140:34, :142:21] assign _in1_bytes_T = _in1_bytes_WIRE[7:0]; // @[ALU.scala:140:34] assign in1_bytes_0 = _in1_bytes_T; // @[ALU.scala:140:34] assign _in1_bytes_T_1 = _in1_bytes_WIRE[15:8]; // @[ALU.scala:140:34] assign in1_bytes_1 = _in1_bytes_T_1; // @[ALU.scala:140:34] assign _in1_bytes_T_2 = _in1_bytes_WIRE[23:16]; // @[ALU.scala:140:34] assign in1_bytes_2 = _in1_bytes_T_2; // @[ALU.scala:140:34] assign _in1_bytes_T_3 = _in1_bytes_WIRE[31:24]; // @[ALU.scala:140:34] assign in1_bytes_3 = _in1_bytes_T_3; // @[ALU.scala:140:34] assign _in1_bytes_T_4 = _in1_bytes_WIRE[39:32]; // @[ALU.scala:140:34] assign in1_bytes_4 = _in1_bytes_T_4; // @[ALU.scala:140:34] assign _in1_bytes_T_5 = _in1_bytes_WIRE[47:40]; // @[ALU.scala:140:34] assign in1_bytes_5 = _in1_bytes_T_5; // @[ALU.scala:140:34] assign _in1_bytes_T_6 = _in1_bytes_WIRE[55:48]; // @[ALU.scala:140:34] assign in1_bytes_6 = _in1_bytes_T_6; // @[ALU.scala:140:34] assign _in1_bytes_T_7 = _in1_bytes_WIRE[63:56]; // @[ALU.scala:140:34] assign in1_bytes_7 = _in1_bytes_T_7; // @[ALU.scala:140:34] wire _orcb_T = \|in1_bytes_0; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_1 = {8{_orcb_T}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_0 = _orcb_T_1; // @[ALU.scala:141:{21,45}] wire _orcb_T_2 = \|in1_bytes_1; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_3 = {8{_orcb_T_2}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_1 = _orcb_T_3; // @[ALU.scala:141:{21,45}] wire _orcb_T_4 = \|in1_bytes_2; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_5 = {8{_orcb_T_4}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_2 = _orcb_T_5; // @[ALU.scala:141:{21,45}] wire _orcb_T_6 = \|in1_bytes_3; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_7 = {8{_orcb_T_6}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_3 = _orcb_T_7; // @[ALU.scala:141:{21,45}] wire _orcb_T_8 = \|in1_bytes_4; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_9 = {8{_orcb_T_8}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_4 = _orcb_T_9; // @[ALU.scala:141:{21,45}] wire _orcb_T_10 = \|in1_bytes_5; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_11 = {8{_orcb_T_10}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_5 = _orcb_T_11; // @[ALU.scala:141:{21,45}] wire _orcb_T_12 = \|in1_bytes_6; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_13 = {8{_orcb_T_12}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_6 = _orcb_T_13; // @[ALU.scala:141:{21,45}] wire _orcb_T_14 = \|in1_bytes_7; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_15 = {8{_orcb_T_14}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_7 = _orcb_T_15; // @[ALU.scala:141:{21,45}] wire [15:0] orcb_lo_lo = {_orcb_WIRE_1, _orcb_WIRE_0}; // @[ALU.scala:141:{21,62}] wire [15:0] orcb_lo_hi = {_orcb_WIRE_3, _orcb_WIRE_2}; // @[ALU.scala:141:{21,62}] wire [31:0] orcb_lo = {orcb_lo_hi, orcb_lo_lo}; // @[ALU.scala:141:62] wire [15:0] orcb_hi_lo = {_orcb_WIRE_5, _orcb_WIRE_4}; // @[ALU.scala:141:{21,62}] wire [15:0] orcb_hi_hi = {_orcb_WIRE_7, _orcb_WIRE_6}; // @[ALU.scala:141:{21,62}] wire [31:0] orcb_hi = {orcb_hi_hi, orcb_hi_lo}; // @[ALU.scala:141:62] wire [63:0] orcb = {orcb_hi, orcb_lo}; // @[ALU.scala:141:62] wire [15:0] rev8_lo_lo = {_rev8_WIRE_1, _rev8_WIRE_0}; // @[ALU.scala:142:{21,41}] wire [15:0] rev8_lo_hi = {_rev8_WIRE_3, _rev8_WIRE_2}; // @[ALU.scala:142:{21,41}] wire [31:0] rev8_lo = {rev8_lo_hi, rev8_lo_lo}; // @[ALU.scala:142:41] wire [15:0] rev8_hi_lo = {_rev8_WIRE_5, _rev8_WIRE_4}; // @[ALU.scala:142:{21,41}] wire [15:0] rev8_hi_hi = {_rev8_WIRE_7, _rev8_WIRE_6}; // @[ALU.scala:142:{21,41}] wire [31:0] rev8_hi = {rev8_hi_hi, rev8_hi_lo}; // @[ALU.scala:142:41] wire [63:0] rev8 = {rev8_hi, rev8_lo}; // @[ALU.scala:142:41] wire [11:0] _unary_T = io_in2_0[11:0]; // @[ALU.scala:83:7, :143:31] wire [15:0] _unary_T_1 = io_in1_0[15:0]; // @[ALU.scala:83:7, :146:22] wire [15:0] _unary_T_8 = io_in1_0[15:0]; // @[ALU.scala:83:7, :146:22, :148:51] wire _unary_T_2 = io_in1_0[7]; // @[ALU.scala:83:7, :147:35] wire [55:0] _unary_T_3 = {56{_unary_T_2}}; // @[ALU.scala:147:{20,35}] wire [7:0] _unary_T_4 = io_in1_0[7:0]; // @[ALU.scala:83:7, :147:49] wire [63:0] _unary_T_5 = {_unary_T_3, _unary_T_4}; // @[ALU.scala:147:{20,40,49}] wire _unary_T_6 = io_in1_0[15]; // @[ALU.scala:83:7, :148:36] wire [47:0] _unary_T_7 = {48{_unary_T_6}}; // @[ALU.scala:148:{20,36}] wire [63:0] _unary_T_9 = {_unary_T_7, _unary_T_8}; // @[ALU.scala:148:{20,42,51}] wire _unary_T_10 = _unary_T == 12'h287; // @[ALU.scala:143:{31,45}] wire [63:0] _unary_T_11 = _unary_T_10 ? orcb : {57'h0, count}; // @[ALU.scala:139:23, :141:62, :143:45] wire _unary_T_12 = _unary_T == 12'h6B8; // @[ALU.scala:143:{31,45}] wire [63:0] _unary_T_13 = _unary_T_12 ? rev8 : _unary_T_11; // @[ALU.scala:142:41, :143:45] wire _unary_T_14 = _unary_T == 12'h80; // @[ALU.scala:143:{31,45}] wire [63:0] _unary_T_15 = _unary_T_14 ? {48'h0, _unary_T_1} : _unary_T_13; // @[ALU.scala:143:45, :146:22] wire _unary_T_16 = _unary_T == 12'h604; // @[ALU.scala:143:{31,45}] wire [63:0] _unary_T_17 = _unary_T_16 ? _unary_T_5 : _unary_T_15; // @[ALU.scala:143:45, :147:40] wire _unary_T_18 = _unary_T == 12'h605; // @[ALU.scala:143:{31,45}] wire [63:0] unary = _unary_T_18 ? _unary_T_9 : _unary_T_17; // @[ALU.scala:143:45, :148:42] wire [63:0] maxmin_out = io_cmp_out ? io_in2_0 : io_in1_0; // @[ALU.scala:83:7, :152:23] wire _rot_shamt_T = ~io_dw_0; // @[ALU.scala:83:7, :130:32, :155:29] wire [6:0] _rot_shamt_T_1 = _rot_shamt_T ? 7'h20 : 7'h40; // @[ALU.scala:155:{22,29}] wire [7:0] _rot_shamt_T_2 = {1'h0, _rot_shamt_T_1} - {2'h0, shamt}; // @[package.scala:16:47] wire [6:0] rot_shamt = _rot_shamt_T_2[6:0]; // @[ALU.scala:155:54] wire [63:0] _rotin_T_4 = {32'h0, _rotin_T_3}; // @[ALU.scala:156:44] wire [63:0] _rotin_T_6 = {_rotin_T_5, 32'h0}; // @[ALU.scala:156:44] wire [63:0] _rotin_T_8 = _rotin_T_6 & 64'hFFFFFFFF00000000; // @[ALU.scala:156:44] wire [63:0] _rotin_T_9 = _rotin_T_4 \| _rotin_T_8; // @[ALU.scala:156:44] wire [47:0] _rotin_T_13 = _rotin_T_9[63:16]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_14 = {16'h0, _rotin_T_13 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _rotin_T_15 = _rotin_T_9[47:0]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_16 = {_rotin_T_15, 16'h0}; // @[ALU.scala:106:46, :156:44] wire [63:0] _rotin_T_18 = _rotin_T_16 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_19 = _rotin_T_14 \| _rotin_T_18; // @[ALU.scala:156:44] wire [55:0] _rotin_T_23 = _rotin_T_19[63:8]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_24 = {8'h0, _rotin_T_23 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _rotin_T_25 = _rotin_T_19[55:0]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_26 = {_rotin_T_25, 8'h0}; // @[ALU.scala:156:44] wire [63:0] _rotin_T_28 = _rotin_T_26 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_29 = _rotin_T_24 \| _rotin_T_28; // @[ALU.scala:156:44] wire [59:0] _rotin_T_33 = _rotin_T_29[63:4]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_34 = {4'h0, _rotin_T_33 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _rotin_T_35 = _rotin_T_29[59:0]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_36 = {_rotin_T_35, 4'h0}; // @[ALU.scala:106:46, :156:44] wire [63:0] _rotin_T_38 = _rotin_T_36 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_39 = _rotin_T_34 \| _rotin_T_38; // @[ALU.scala:156:44] wire [61:0] _rotin_T_43 = _rotin_T_39[63:2]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_44 = {2'h0, _rotin_T_43 & 62'h3333333333333333}; // @[package.scala:16:47] wire [61:0] _rotin_T_45 = _rotin_T_39[61:0]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_46 = {_rotin_T_45, 2'h0}; // @[package.scala:16:47] wire [63:0] _rotin_T_48 = _rotin_T_46 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_49 = _rotin_T_44 \| _rotin_T_48; // @[ALU.scala:156:44] wire [62:0] _rotin_T_53 = _rotin_T_49[63:1]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_54 = {1'h0, _rotin_T_53 & 63'h5555555555555555}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _rotin_T_55 = _rotin_T_49[62:0]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_56 = {_rotin_T_55, 1'h0}; // @[ALU.scala:156:44] wire [63:0] _rotin_T_58 = _rotin_T_56 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_59 = _rotin_T_54 \| _rotin_T_58; // @[ALU.scala:156:44] wire [63:0] rotin = _rotin_T ? shin_r : _rotin_T_59; // @[ALU.scala:104:18, :156:{18,24,44}] wire [63:0] _rotout_r_T = rotin >> rot_shamt; // @[ALU.scala:155:54, :156:18, :157:25] wire [63:0] rotout_r = _rotout_r_T; // @[ALU.scala:157:{25,38}] wire [31:0] _rotout_l_T_2 = rotout_r[63:32]; // @[ALU.scala:157:38, :158:25] wire [63:0] _rotout_l_T_3 = {32'h0, _rotout_l_T_2}; // @[ALU.scala:158:25] wire [31:0] _rotout_l_T_4 = rotout_r[31:0]; // @[ALU.scala:157:38, :158:25] wire [63:0] _rotout_l_T_5 = {_rotout_l_T_4, 32'h0}; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_7 = _rotout_l_T_5 & 64'hFFFFFFFF00000000; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_8 = _rotout_l_T_3 \| _rotout_l_T_7; // @[ALU.scala:158:25] wire [47:0] _rotout_l_T_12 = _rotout_l_T_8[63:16]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_13 = {16'h0, _rotout_l_T_12 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _rotout_l_T_14 = _rotout_l_T_8[47:0]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_15 = {_rotout_l_T_14, 16'h0}; // @[ALU.scala:106:46, :158:25] wire [63:0] _rotout_l_T_17 = _rotout_l_T_15 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_18 = _rotout_l_T_13 \| _rotout_l_T_17; // @[ALU.scala:158:25] wire [55:0] _rotout_l_T_22 = _rotout_l_T_18[63:8]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_23 = {8'h0, _rotout_l_T_22 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _rotout_l_T_24 = _rotout_l_T_18[55:0]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_25 = {_rotout_l_T_24, 8'h0}; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_27 = _rotout_l_T_25 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_28 = _rotout_l_T_23 \| _rotout_l_T_27; // @[ALU.scala:158:25] wire [59:0] _rotout_l_T_32 = _rotout_l_T_28[63:4]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_33 = {4'h0, _rotout_l_T_32 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _rotout_l_T_34 = _rotout_l_T_28[59:0]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_35 = {_rotout_l_T_34, 4'h0}; // @[ALU.scala:106:46, :158:25] wire [63:0] _rotout_l_T_37 = _rotout_l_T_35 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_38 = _rotout_l_T_33 \| _rotout_l_T_37; // @[ALU.scala:158:25] wire [61:0] _rotout_l_T_42 = _rotout_l_T_38[63:2]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_43 = {2'h0, _rotout_l_T_42 & 62'h3333333333333333}; // @[package.scala:16:47] wire [61:0] _rotout_l_T_44 = _rotout_l_T_38[61:0]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_45 = {_rotout_l_T_44, 2'h0}; // @[package.scala:16:47] wire [63:0] _rotout_l_T_47 = _rotout_l_T_45 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_48 = _rotout_l_T_43 \| _rotout_l_T_47; // @[ALU.scala:158:25] wire [62:0] _rotout_l_T_52 = _rotout_l_T_48[63:1]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_53 = {1'h0, _rotout_l_T_52 & 63'h5555555555555555}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _rotout_l_T_54 = _rotout_l_T_48[62:0]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_55 = {_rotout_l_T_54, 1'h0}; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_57 = _rotout_l_T_55 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] rotout_l = _rotout_l_T_53 \| _rotout_l_T_57; // @[ALU.scala:158:25] wire [63:0] _rotout_T_1 = _rotout_T ? rotout_r : rotout_l; // @[ALU.scala:157:38, :158:25, :159:{19,25}] wire [63:0] _rotout_T_3 = _rotout_T_2 ? shout_l : shout_r; // @[ALU.scala:107:73, :108:24, :159:{55,61}] wire [63:0] rotout = _rotout_T_1 \| _rotout_T_3; // @[ALU.scala:159:{19,50,55}] wire _out_T = io_fn_0 == 5'h0; // @[ALU.scala:83:7, :161:47] wire [63:0] _out_T_1 = _out_T ? io_adder_out : shift_logic; // @[ALU.scala:83:7, :123:52, :161:47] wire _out_T_2 = io_fn_0 == 5'hA; // @[ALU.scala:83:7, :161:47] wire [63:0] out = _out_T_2 ? io_adder_out : _out_T_1; // @[ALU.scala:83:7, :161:47] wire _io_out_T = out[31]; // @[ALU.scala:161:47, :178:56] wire [31:0] _io_out_T_1 = {32{_io_out_T}}; // @[ALU.scala:178:{48,56}] wire [31:0] _io_out_T_2 = out[31:0]; // @[ALU.scala:161:47, :178:66] wire [63:0] _io_out_T_3 = {_io_out_T_1, _io_out_T_2}; // @[ALU.scala:178:{43,48,66}] assign io_out_0 = io_dw_0 ? out : _io_out_T_3; // @[ALU.scala:83:7, :161:47, :175:10, :178:{28,37,43}] assign io_out = io_out_0; // @[ALU.scala:83:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_47 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_57 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_47( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_57 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_119 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_140 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_119( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_140 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_be_router_10ClockSinkDomain : output auto : { egress_width_widget_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, ingress_id : UInt}}}, flip ingress_width_widget_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, egress_id : UInt}}}, routers_debug_out : { va_stall : UInt[5], sa_stall : UInt[5]}, routers_source_nodes_out_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_26 connect routers.clock, childClock connect routers.reset, childReset inst ingress_width_widget of IngressWidthWidget_12 connect ingress_width_widget.clock, childClock connect ingress_width_widget.reset, childReset inst egress_width_widget of EgressWidthWidget_12 connect egress_width_widget.clock, childClock connect egress_width_widget.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect egress_width_widget.auto.in, routers.auto.egress_nodes_out connect routers.auto.ingress_nodes_in, ingress_width_widget.auto.out connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0 connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1 connect routers.auto.dest_nodes_in_2, auto.routers_dest_nodes_in_2 connect routers.auto.dest_nodes_in_3, auto.routers_dest_nodes_in_3 connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit connect routers.auto.source_nodes_out_3.vc_free, auto.routers_source_nodes_out_3.vc_free connect routers.auto.source_nodes_out_3.credit_return, auto.routers_source_nodes_out_3.credit_return connect auto.routers_source_nodes_out_3.flit, routers.auto.source_nodes_out_3.flit connect auto.routers_debug_out, routers.auto.debug_out connect ingress_width_widget.auto.in, auto.ingress_width_widget_in connect auto.egress_width_widget_out.flit.bits, egress_width_widget.auto.out.flit.bits connect auto.egress_width_widget_out.flit.valid, egress_width_widget.auto.out.flit.valid connect egress_width_widget.auto.out.flit.ready, auto.egress_width_widget_out.flit.ready connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset	module TLSplitACDxBENoC_be_router_10ClockSinkDomain( // @[ClockDomain.scala:14:9] output auto_egress_width_widget_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [147:0] auto_egress_width_widget_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_width_widget_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [147:0] auto_ingress_width_widget_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_ingress_width_widget_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_3_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_3_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_3_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_3_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _egress_width_widget_auto_in_flit_ready; // @[WidthWidget.scala:111:43] wire _ingress_width_widget_auto_out_flit_valid; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_auto_out_flit_bits_head; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_auto_out_flit_bits_tail; // @[WidthWidget.scala:88:44] wire [36:0] _ingress_width_widget_auto_out_flit_bits_payload; // @[WidthWidget.scala:88:44] wire [3:0] _ingress_width_widget_auto_out_flit_bits_egress_id; // @[WidthWidget.scala:88:44] wire _routers_auto_egress_nodes_out_flit_valid; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_flit_bits_head; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_flit_bits_tail; // @[NoC.scala:67:22] wire [36:0] _routers_auto_egress_nodes_out_flit_bits_payload; // @[NoC.scala:67:22] wire _routers_auto_ingress_nodes_in_flit_ready; // @[NoC.scala:67:22] Router_26 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3), .auto_debug_out_va_stall_4 (auto_routers_debug_out_va_stall_4), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3), .auto_debug_out_sa_stall_4 (auto_routers_debug_out_sa_stall_4), .auto_egress_nodes_out_flit_ready (_egress_width_widget_auto_in_flit_ready), // @[WidthWidget.scala:111:43] .auto_egress_nodes_out_flit_valid (_routers_auto_egress_nodes_out_flit_valid), .auto_egress_nodes_out_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), .auto_egress_nodes_out_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), .auto_egress_nodes_out_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), .auto_ingress_nodes_in_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), .auto_ingress_nodes_in_flit_valid (_ingress_width_widget_auto_out_flit_valid), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id), // @[WidthWidget.scala:88:44] .auto_source_nodes_out_3_flit_0_valid (auto_routers_source_nodes_out_3_flit_0_valid), .auto_source_nodes_out_3_flit_0_bits_head (auto_routers_source_nodes_out_3_flit_0_bits_head), .auto_source_nodes_out_3_flit_0_bits_tail (auto_routers_source_nodes_out_3_flit_0_bits_tail), .auto_source_nodes_out_3_flit_0_bits_payload (auto_routers_source_nodes_out_3_flit_0_bits_payload), .auto_source_nodes_out_3_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_3_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_3_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_3_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node), .auto_source_nodes_out_3_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_3_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id), .auto_source_nodes_out_3_credit_return (auto_routers_source_nodes_out_3_credit_return), .auto_source_nodes_out_3_vc_free (auto_routers_source_nodes_out_3_vc_free), .auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid), .auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head), .auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail), .auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload), .auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id), .auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return), .auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free), .auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid), .auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head), .auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail), .auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload), .auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id), .auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return), .auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free), .auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid), .auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head), .auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail), .auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload), .auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id), .auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return), .auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free), .auto_dest_nodes_in_3_flit_0_valid (auto_routers_dest_nodes_in_3_flit_0_valid), .auto_dest_nodes_in_3_flit_0_bits_head (auto_routers_dest_nodes_in_3_flit_0_bits_head), .auto_dest_nodes_in_3_flit_0_bits_tail (auto_routers_dest_nodes_in_3_flit_0_bits_tail), .auto_dest_nodes_in_3_flit_0_bits_payload (auto_routers_dest_nodes_in_3_flit_0_bits_payload), .auto_dest_nodes_in_3_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_3_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_3_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_3_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_3_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_3_credit_return (auto_routers_dest_nodes_in_3_credit_return), .auto_dest_nodes_in_3_vc_free (auto_routers_dest_nodes_in_3_vc_free), .auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid), .auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head), .auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail), .auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload), .auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return), .auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free), .auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid), .auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head), .auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail), .auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload), .auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return), .auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free), .auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid), .auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head), .auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail), .auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload), .auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return), .auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free) ); // @[NoC.scala:67:22] IngressWidthWidget_2 ingress_width_widget ( // @[WidthWidget.scala:88:44] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (auto_ingress_width_widget_in_flit_ready), .auto_in_flit_valid (auto_ingress_width_widget_in_flit_valid), .auto_in_flit_bits_head (auto_ingress_width_widget_in_flit_bits_head), .auto_in_flit_bits_tail (auto_ingress_width_widget_in_flit_bits_tail), .auto_in_flit_bits_payload (auto_ingress_width_widget_in_flit_bits_payload), .auto_in_flit_bits_egress_id (auto_ingress_width_widget_in_flit_bits_egress_id), .auto_out_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), // @[NoC.scala:67:22] .auto_out_flit_valid (_ingress_width_widget_auto_out_flit_valid), .auto_out_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), .auto_out_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), .auto_out_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), .auto_out_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id) ); // @[WidthWidget.scala:88:44] EgressWidthWidget_1 egress_width_widget ( // @[WidthWidget.scala:111:43] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (_egress_width_widget_auto_in_flit_ready), .auto_in_flit_valid (_routers_auto_egress_nodes_out_flit_valid), // @[NoC.scala:67:22] .auto_in_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), // @[NoC.scala:67:22] .auto_in_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), // @[NoC.scala:67:22] .auto_in_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), // @[NoC.scala:67:22] .auto_out_flit_ready (1'h1), // @[LazyModuleImp.scala:107:25] .auto_out_flit_valid (auto_egress_width_widget_out_flit_valid), .auto_out_flit_bits_head (auto_egress_width_widget_out_flit_bits_head), .auto_out_flit_bits_tail (auto_egress_width_widget_out_flit_bits_tail), .auto_out_flit_bits_payload (auto_egress_width_widget_out_flit_bits_payload) ); // @[WidthWidget.scala:111:43] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_75 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_86 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_75( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_86 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_59 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[12] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 node _source_ok_T_32 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[2]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[3]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[4]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[5]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[6]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[7]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[8]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[9]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[10]) node source_ok = or(_source_ok_T_41, _source_ok_WIRE[11]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = and(_T_11, _T_24) node _T_121 = and(_T_120, _T_37) node _T_122 = and(_T_121, _T_50) node _T_123 = and(_T_122, _T_63) node _T_124 = and(_T_123, _T_71) node _T_125 = and(_T_124, _T_79) node _T_126 = and(_T_125, _T_87) node _T_127 = and(_T_126, _T_95) node _T_128 = and(_T_127, _T_103) node _T_129 = and(_T_128, _T_111) node _T_130 = and(_T_129, _T_119) node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(_T_130, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_130, UInt<1>(0h1), "") : assert_1 node _T_134 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_134 : node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_136 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_139 = shr(io.in.a.bits.source, 2) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = leq(UInt<1>(0h0), uncommonBits_4) node _T_142 = and(_T_140, _T_141) node _T_143 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_144 = and(_T_142, _T_143) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_145 = shr(io.in.a.bits.source, 2) node _T_146 = eq(_T_145, UInt<1>(0h1)) node _T_147 = leq(UInt<1>(0h0), uncommonBits_5) node _T_148 = and(_T_146, _T_147) node _T_149 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_150 = and(_T_148, _T_149) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_151 = shr(io.in.a.bits.source, 2) node _T_152 = eq(_T_151, UInt<2>(0h2)) node _T_153 = leq(UInt<1>(0h0), uncommonBits_6) node _T_154 = and(_T_152, _T_153) node _T_155 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_156 = and(_T_154, _T_155) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_157 = shr(io.in.a.bits.source, 2) node _T_158 = eq(_T_157, UInt<2>(0h3)) node _T_159 = leq(UInt<1>(0h0), uncommonBits_7) node _T_160 = and(_T_158, _T_159) node _T_161 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_166 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_167 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_169 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_170 = or(_T_138, _T_144) node _T_171 = or(_T_170, _T_150) node _T_172 = or(_T_171, _T_156) node _T_173 = or(_T_172, _T_162) node _T_174 = or(_T_173, _T_163) node _T_175 = or(_T_174, _T_164) node _T_176 = or(_T_175, _T_165) node _T_177 = or(_T_176, _T_166) node _T_178 = or(_T_177, _T_167) node _T_179 = or(_T_178, _T_168) node _T_180 = or(_T_179, _T_169) node _T_181 = and(_T_137, _T_180) node _T_182 = or(UInt<1>(0h0), _T_181) node _T_183 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_184 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<18>(0h2f000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = and(_T_183, _T_188) node _T_190 = or(UInt<1>(0h0), _T_189) node _T_191 = and(_T_182, _T_190) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_191, UInt<1>(0h1), "") : assert_2 node _T_195 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_196 = shr(io.in.a.bits.source, 2) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = leq(UInt<1>(0h0), uncommonBits_8) node _T_199 = and(_T_197, _T_198) node _T_200 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_201 = and(_T_199, _T_200) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_202 = shr(io.in.a.bits.source, 2) node _T_203 = eq(_T_202, UInt<1>(0h1)) node _T_204 = leq(UInt<1>(0h0), uncommonBits_9) node _T_205 = and(_T_203, _T_204) node _T_206 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_207 = and(_T_205, _T_206) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_208 = shr(io.in.a.bits.source, 2) node _T_209 = eq(_T_208, UInt<2>(0h2)) node _T_210 = leq(UInt<1>(0h0), uncommonBits_10) node _T_211 = and(_T_209, _T_210) node _T_212 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_213 = and(_T_211, _T_212) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_214 = shr(io.in.a.bits.source, 2) node _T_215 = eq(_T_214, UInt<2>(0h3)) node _T_216 = leq(UInt<1>(0h0), uncommonBits_11) node _T_217 = and(_T_215, _T_216) node _T_218 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_219 = and(_T_217, _T_218) node _T_220 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_221 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_222 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_223 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_225 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_226 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[12] connect _WIRE[0], _T_195 connect _WIRE[1], _T_201 connect _WIRE[2], _T_207 connect _WIRE[3], _T_213 connect _WIRE[4], _T_219 connect _WIRE[5], _T_220 connect _WIRE[6], _T_221 connect _WIRE[7], _T_222 connect _WIRE[8], _T_223 connect _WIRE[9], _T_224 connect _WIRE[10], _T_225 connect _WIRE[11], _T_226 node _T_227 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_228 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_229 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_230 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_231 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_232 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_233 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_234 = mux(_WIRE[5], _T_227, UInt<1>(0h0)) node _T_235 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_236 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_237 = mux(_WIRE[8], _T_228, UInt<1>(0h0)) node _T_238 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_239 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_240 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_241 = or(_T_229, _T_230) node _T_242 = or(_T_241, _T_231) node _T_243 = or(_T_242, _T_232) node _T_244 = or(_T_243, _T_233) node _T_245 = or(_T_244, _T_234) node _T_246 = or(_T_245, _T_235) node _T_247 = or(_T_246, _T_236) node _T_248 = or(_T_247, _T_237) node _T_249 = or(_T_248, _T_238) node _T_250 = or(_T_249, _T_239) node _T_251 = or(_T_250, _T_240) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_251 node _T_252 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_253 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_254 = and(_T_252, _T_253) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<18>(0h2f000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = and(_T_255, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = and(_WIRE_1, _T_262) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_263, UInt<1>(0h1), "") : assert_3 node _T_267 = asUInt(reset) node _T_268 = eq(_T_267, UInt<1>(0h0)) when _T_268 : node _T_269 = eq(source_ok, UInt<1>(0h0)) when _T_269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_270 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_270, UInt<1>(0h1), "") : assert_5 node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(is_aligned, UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_277 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_278 = asUInt(reset) node _T_279 = eq(_T_278, UInt<1>(0h0)) when _T_279 : node _T_280 = eq(_T_277, UInt<1>(0h0)) when _T_280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_277, UInt<1>(0h1), "") : assert_7 node _T_281 = not(io.in.a.bits.mask) node _T_282 = eq(_T_281, UInt<1>(0h0)) node _T_283 = asUInt(reset) node _T_284 = eq(_T_283, UInt<1>(0h0)) when _T_284 : node _T_285 = eq(_T_282, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_282, UInt<1>(0h1), "") : assert_8 node _T_286 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_287 = asUInt(reset) node _T_288 = eq(_T_287, UInt<1>(0h0)) when _T_288 : node _T_289 = eq(_T_286, UInt<1>(0h0)) when _T_289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_286, UInt<1>(0h1), "") : assert_9 node _T_290 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_290 : node _T_291 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_292 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_295 = shr(io.in.a.bits.source, 2) node _T_296 = eq(_T_295, UInt<1>(0h0)) node _T_297 = leq(UInt<1>(0h0), uncommonBits_12) node _T_298 = and(_T_296, _T_297) node _T_299 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_300 = and(_T_298, _T_299) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<1>(0h1)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_13) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<2>(0h2)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_14) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_313 = shr(io.in.a.bits.source, 2) node _T_314 = eq(_T_313, UInt<2>(0h3)) node _T_315 = leq(UInt<1>(0h0), uncommonBits_15) node _T_316 = and(_T_314, _T_315) node _T_317 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_318 = and(_T_316, _T_317) node _T_319 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_321 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_322 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_323 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_324 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_325 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_326 = or(_T_294, _T_300) node _T_327 = or(_T_326, _T_306) node _T_328 = or(_T_327, _T_312) node _T_329 = or(_T_328, _T_318) node _T_330 = or(_T_329, _T_319) node _T_331 = or(_T_330, _T_320) node _T_332 = or(_T_331, _T_321) node _T_333 = or(_T_332, _T_322) node _T_334 = or(_T_333, _T_323) node _T_335 = or(_T_334, _T_324) node _T_336 = or(_T_335, _T_325) node _T_337 = and(_T_293, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<18>(0h2f000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = and(_T_339, _T_344) node _T_346 = or(UInt<1>(0h0), _T_345) node _T_347 = and(_T_338, _T_346) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_347, UInt<1>(0h1), "") : assert_10 node _T_351 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_352 = shr(io.in.a.bits.source, 2) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = leq(UInt<1>(0h0), uncommonBits_16) node _T_355 = and(_T_353, _T_354) node _T_356 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_357 = and(_T_355, _T_356) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_358 = shr(io.in.a.bits.source, 2) node _T_359 = eq(_T_358, UInt<1>(0h1)) node _T_360 = leq(UInt<1>(0h0), uncommonBits_17) node _T_361 = and(_T_359, _T_360) node _T_362 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_363 = and(_T_361, _T_362) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_364 = shr(io.in.a.bits.source, 2) node _T_365 = eq(_T_364, UInt<2>(0h2)) node _T_366 = leq(UInt<1>(0h0), uncommonBits_18) node _T_367 = and(_T_365, _T_366) node _T_368 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_369 = and(_T_367, _T_368) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_370 = shr(io.in.a.bits.source, 2) node _T_371 = eq(_T_370, UInt<2>(0h3)) node _T_372 = leq(UInt<1>(0h0), uncommonBits_19) node _T_373 = and(_T_371, _T_372) node _T_374 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_375 = and(_T_373, _T_374) node _T_376 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_377 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_378 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_379 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_380 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_381 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_382 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[12] connect _WIRE_2[0], _T_351 connect _WIRE_2[1], _T_357 connect _WIRE_2[2], _T_363 connect _WIRE_2[3], _T_369 connect _WIRE_2[4], _T_375 connect _WIRE_2[5], _T_376 connect _WIRE_2[6], _T_377 connect _WIRE_2[7], _T_378 connect _WIRE_2[8], _T_379 connect _WIRE_2[9], _T_380 connect _WIRE_2[10], _T_381 connect _WIRE_2[11], _T_382 node _T_383 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_384 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_385 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_386 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_387 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_388 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_389 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_390 = mux(_WIRE_2[5], _T_383, UInt<1>(0h0)) node _T_391 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_392 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_393 = mux(_WIRE_2[8], _T_384, UInt<1>(0h0)) node _T_394 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_395 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_396 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_397 = or(_T_385, _T_386) node _T_398 = or(_T_397, _T_387) node _T_399 = or(_T_398, _T_388) node _T_400 = or(_T_399, _T_389) node _T_401 = or(_T_400, _T_390) node _T_402 = or(_T_401, _T_391) node _T_403 = or(_T_402, _T_392) node _T_404 = or(_T_403, _T_393) node _T_405 = or(_T_404, _T_394) node _T_406 = or(_T_405, _T_395) node _T_407 = or(_T_406, _T_396) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_407 node _T_408 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_409 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_410 = and(_T_408, _T_409) node _T_411 = or(UInt<1>(0h0), _T_410) node _T_412 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_413 = cvt(_T_412) node _T_414 = and(_T_413, asSInt(UInt<18>(0h2f000))) node _T_415 = asSInt(_T_414) node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0))) node _T_417 = and(_T_411, _T_416) node _T_418 = or(UInt<1>(0h0), _T_417) node _T_419 = and(_WIRE_3, _T_418) node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(_T_419, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_419, UInt<1>(0h1), "") : assert_11 node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(source_ok, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_426 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_426, UInt<1>(0h1), "") : assert_13 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(is_aligned, UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_433 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_433, UInt<1>(0h1), "") : assert_15 node _T_437 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_T_437, UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_437, UInt<1>(0h1), "") : assert_16 node _T_441 = not(io.in.a.bits.mask) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_442, UInt<1>(0h1), "") : assert_17 node _T_446 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_446, UInt<1>(0h1), "") : assert_18 node _T_450 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_450 : node _T_451 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_452 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_453 = and(_T_451, _T_452) node _T_454 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_455 = shr(io.in.a.bits.source, 2) node _T_456 = eq(_T_455, UInt<1>(0h0)) node _T_457 = leq(UInt<1>(0h0), uncommonBits_20) node _T_458 = and(_T_456, _T_457) node _T_459 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_460 = and(_T_458, _T_459) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_461 = shr(io.in.a.bits.source, 2) node _T_462 = eq(_T_461, UInt<1>(0h1)) node _T_463 = leq(UInt<1>(0h0), uncommonBits_21) node _T_464 = and(_T_462, _T_463) node _T_465 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_466 = and(_T_464, _T_465) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_467 = shr(io.in.a.bits.source, 2) node _T_468 = eq(_T_467, UInt<2>(0h2)) node _T_469 = leq(UInt<1>(0h0), uncommonBits_22) node _T_470 = and(_T_468, _T_469) node _T_471 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_472 = and(_T_470, _T_471) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_473 = shr(io.in.a.bits.source, 2) node _T_474 = eq(_T_473, UInt<2>(0h3)) node _T_475 = leq(UInt<1>(0h0), uncommonBits_23) node _T_476 = and(_T_474, _T_475) node _T_477 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_478 = and(_T_476, _T_477) node _T_479 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_480 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_482 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_483 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_484 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_485 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_486 = or(_T_454, _T_460) node _T_487 = or(_T_486, _T_466) node _T_488 = or(_T_487, _T_472) node _T_489 = or(_T_488, _T_478) node _T_490 = or(_T_489, _T_479) node _T_491 = or(_T_490, _T_480) node _T_492 = or(_T_491, _T_481) node _T_493 = or(_T_492, _T_482) node _T_494 = or(_T_493, _T_483) node _T_495 = or(_T_494, _T_484) node _T_496 = or(_T_495, _T_485) node _T_497 = and(_T_453, _T_496) node _T_498 = or(UInt<1>(0h0), _T_497) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_498, UInt<1>(0h1), "") : assert_19 node _T_502 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_503 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_504 = and(_T_502, _T_503) node _T_505 = or(UInt<1>(0h0), _T_504) node _T_506 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<18>(0h2f000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = and(_T_505, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_512, UInt<1>(0h1), "") : assert_20 node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(source_ok, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(is_aligned, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_522, UInt<1>(0h1), "") : assert_23 node _T_526 = eq(io.in.a.bits.mask, mask) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_526, UInt<1>(0h1), "") : assert_24 node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_530, UInt<1>(0h1), "") : assert_25 node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_534 : node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_537 = and(_T_535, _T_536) node _T_538 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_539 = shr(io.in.a.bits.source, 2) node _T_540 = eq(_T_539, UInt<1>(0h0)) node _T_541 = leq(UInt<1>(0h0), uncommonBits_24) node _T_542 = and(_T_540, _T_541) node _T_543 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_544 = and(_T_542, _T_543) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_545 = shr(io.in.a.bits.source, 2) node _T_546 = eq(_T_545, UInt<1>(0h1)) node _T_547 = leq(UInt<1>(0h0), uncommonBits_25) node _T_548 = and(_T_546, _T_547) node _T_549 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_550 = and(_T_548, _T_549) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_551 = shr(io.in.a.bits.source, 2) node _T_552 = eq(_T_551, UInt<2>(0h2)) node _T_553 = leq(UInt<1>(0h0), uncommonBits_26) node _T_554 = and(_T_552, _T_553) node _T_555 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_556 = and(_T_554, _T_555) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_557 = shr(io.in.a.bits.source, 2) node _T_558 = eq(_T_557, UInt<2>(0h3)) node _T_559 = leq(UInt<1>(0h0), uncommonBits_27) node _T_560 = and(_T_558, _T_559) node _T_561 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_562 = and(_T_560, _T_561) node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_566 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_567 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_569 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_570 = or(_T_538, _T_544) node _T_571 = or(_T_570, _T_550) node _T_572 = or(_T_571, _T_556) node _T_573 = or(_T_572, _T_562) node _T_574 = or(_T_573, _T_563) node _T_575 = or(_T_574, _T_564) node _T_576 = or(_T_575, _T_565) node _T_577 = or(_T_576, _T_566) node _T_578 = or(_T_577, _T_567) node _T_579 = or(_T_578, _T_568) node _T_580 = or(_T_579, _T_569) node _T_581 = and(_T_537, _T_580) node _T_582 = or(UInt<1>(0h0), _T_581) node _T_583 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_584 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_585 = and(_T_583, _T_584) node _T_586 = or(UInt<1>(0h0), _T_585) node _T_587 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_588 = cvt(_T_587) node _T_589 = and(_T_588, asSInt(UInt<18>(0h2f000))) node _T_590 = asSInt(_T_589) node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0))) node _T_592 = and(_T_586, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = and(_T_582, _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_594, UInt<1>(0h1), "") : assert_26 node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(source_ok, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_601 = asUInt(reset) node _T_602 = eq(_T_601, UInt<1>(0h0)) when _T_602 : node _T_603 = eq(is_aligned, UInt<1>(0h0)) when _T_603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_604 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(_T_604, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_604, UInt<1>(0h1), "") : assert_29 node _T_608 = eq(io.in.a.bits.mask, mask) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_608, UInt<1>(0h1), "") : assert_30 node _T_612 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_612 : node _T_613 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_614 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_615 = and(_T_613, _T_614) node _T_616 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_617 = shr(io.in.a.bits.source, 2) node _T_618 = eq(_T_617, UInt<1>(0h0)) node _T_619 = leq(UInt<1>(0h0), uncommonBits_28) node _T_620 = and(_T_618, _T_619) node _T_621 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_622 = and(_T_620, _T_621) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_623 = shr(io.in.a.bits.source, 2) node _T_624 = eq(_T_623, UInt<1>(0h1)) node _T_625 = leq(UInt<1>(0h0), uncommonBits_29) node _T_626 = and(_T_624, _T_625) node _T_627 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_628 = and(_T_626, _T_627) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_629 = shr(io.in.a.bits.source, 2) node _T_630 = eq(_T_629, UInt<2>(0h2)) node _T_631 = leq(UInt<1>(0h0), uncommonBits_30) node _T_632 = and(_T_630, _T_631) node _T_633 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_634 = and(_T_632, _T_633) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_635 = shr(io.in.a.bits.source, 2) node _T_636 = eq(_T_635, UInt<2>(0h3)) node _T_637 = leq(UInt<1>(0h0), uncommonBits_31) node _T_638 = and(_T_636, _T_637) node _T_639 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_640 = and(_T_638, _T_639) node _T_641 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_642 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_643 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_616, _T_622) node _T_649 = or(_T_648, _T_628) node _T_650 = or(_T_649, _T_634) node _T_651 = or(_T_650, _T_640) node _T_652 = or(_T_651, _T_641) node _T_653 = or(_T_652, _T_642) node _T_654 = or(_T_653, _T_643) node _T_655 = or(_T_654, _T_644) node _T_656 = or(_T_655, _T_645) node _T_657 = or(_T_656, _T_646) node _T_658 = or(_T_657, _T_647) node _T_659 = and(_T_615, _T_658) node _T_660 = or(UInt<1>(0h0), _T_659) node _T_661 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_662 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_663 = and(_T_661, _T_662) node _T_664 = or(UInt<1>(0h0), _T_663) node _T_665 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<18>(0h2f000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = and(_T_664, _T_669) node _T_671 = or(UInt<1>(0h0), _T_670) node _T_672 = and(_T_660, _T_671) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_672, UInt<1>(0h1), "") : assert_31 node _T_676 = asUInt(reset) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(source_ok, UInt<1>(0h0)) when _T_678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(is_aligned, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_682 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_T_682, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_682, UInt<1>(0h1), "") : assert_34 node _T_686 = not(mask) node _T_687 = and(io.in.a.bits.mask, _T_686) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_688, UInt<1>(0h1), "") : assert_35 node _T_692 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_692 : node _T_693 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_694 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_695 = and(_T_693, _T_694) node _T_696 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_697 = shr(io.in.a.bits.source, 2) node _T_698 = eq(_T_697, UInt<1>(0h0)) node _T_699 = leq(UInt<1>(0h0), uncommonBits_32) node _T_700 = and(_T_698, _T_699) node _T_701 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_702 = and(_T_700, _T_701) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_703 = shr(io.in.a.bits.source, 2) node _T_704 = eq(_T_703, UInt<1>(0h1)) node _T_705 = leq(UInt<1>(0h0), uncommonBits_33) node _T_706 = and(_T_704, _T_705) node _T_707 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_708 = and(_T_706, _T_707) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_709 = shr(io.in.a.bits.source, 2) node _T_710 = eq(_T_709, UInt<2>(0h2)) node _T_711 = leq(UInt<1>(0h0), uncommonBits_34) node _T_712 = and(_T_710, _T_711) node _T_713 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_714 = and(_T_712, _T_713) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_715 = shr(io.in.a.bits.source, 2) node _T_716 = eq(_T_715, UInt<2>(0h3)) node _T_717 = leq(UInt<1>(0h0), uncommonBits_35) node _T_718 = and(_T_716, _T_717) node _T_719 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_720 = and(_T_718, _T_719) node _T_721 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_722 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_723 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_724 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_725 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_726 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_727 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_728 = or(_T_696, _T_702) node _T_729 = or(_T_728, _T_708) node _T_730 = or(_T_729, _T_714) node _T_731 = or(_T_730, _T_720) node _T_732 = or(_T_731, _T_721) node _T_733 = or(_T_732, _T_722) node _T_734 = or(_T_733, _T_723) node _T_735 = or(_T_734, _T_724) node _T_736 = or(_T_735, _T_725) node _T_737 = or(_T_736, _T_726) node _T_738 = or(_T_737, _T_727) node _T_739 = and(_T_695, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_742 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_743 = cvt(_T_742) node _T_744 = and(_T_743, asSInt(UInt<18>(0h2f000))) node _T_745 = asSInt(_T_744) node _T_746 = eq(_T_745, asSInt(UInt<1>(0h0))) node _T_747 = and(_T_741, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = and(_T_740, _T_748) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_749, UInt<1>(0h1), "") : assert_36 node _T_753 = asUInt(reset) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : node _T_755 = eq(source_ok, UInt<1>(0h0)) when _T_755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(is_aligned, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_759 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_759, UInt<1>(0h1), "") : assert_39 node _T_763 = eq(io.in.a.bits.mask, mask) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_763, UInt<1>(0h1), "") : assert_40 node _T_767 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_767 : node _T_768 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_769 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_770 = and(_T_768, _T_769) node _T_771 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<1>(0h0)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_36) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_778 = shr(io.in.a.bits.source, 2) node _T_779 = eq(_T_778, UInt<1>(0h1)) node _T_780 = leq(UInt<1>(0h0), uncommonBits_37) node _T_781 = and(_T_779, _T_780) node _T_782 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_783 = and(_T_781, _T_782) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_784 = shr(io.in.a.bits.source, 2) node _T_785 = eq(_T_784, UInt<2>(0h2)) node _T_786 = leq(UInt<1>(0h0), uncommonBits_38) node _T_787 = and(_T_785, _T_786) node _T_788 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_789 = and(_T_787, _T_788) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_790 = shr(io.in.a.bits.source, 2) node _T_791 = eq(_T_790, UInt<2>(0h3)) node _T_792 = leq(UInt<1>(0h0), uncommonBits_39) node _T_793 = and(_T_791, _T_792) node _T_794 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_795 = and(_T_793, _T_794) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_802 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_803 = or(_T_771, _T_777) node _T_804 = or(_T_803, _T_783) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_795) node _T_807 = or(_T_806, _T_796) node _T_808 = or(_T_807, _T_797) node _T_809 = or(_T_808, _T_798) node _T_810 = or(_T_809, _T_799) node _T_811 = or(_T_810, _T_800) node _T_812 = or(_T_811, _T_801) node _T_813 = or(_T_812, _T_802) node _T_814 = and(_T_770, _T_813) node _T_815 = or(UInt<1>(0h0), _T_814) node _T_816 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_817 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_818 = cvt(_T_817) node _T_819 = and(_T_818, asSInt(UInt<18>(0h2f000))) node _T_820 = asSInt(_T_819) node _T_821 = eq(_T_820, asSInt(UInt<1>(0h0))) node _T_822 = and(_T_816, _T_821) node _T_823 = or(UInt<1>(0h0), _T_822) node _T_824 = and(_T_815, _T_823) node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(_T_824, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_824, UInt<1>(0h1), "") : assert_41 node _T_828 = asUInt(reset) node _T_829 = eq(_T_828, UInt<1>(0h0)) when _T_829 : node _T_830 = eq(source_ok, UInt<1>(0h0)) when _T_830 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(is_aligned, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_834 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_834, UInt<1>(0h1), "") : assert_44 node _T_838 = eq(io.in.a.bits.mask, mask) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_838, UInt<1>(0h1), "") : assert_45 node _T_842 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_842 : node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_847 = shr(io.in.a.bits.source, 2) node _T_848 = eq(_T_847, UInt<1>(0h0)) node _T_849 = leq(UInt<1>(0h0), uncommonBits_40) node _T_850 = and(_T_848, _T_849) node _T_851 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_852 = and(_T_850, _T_851) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<1>(0h1)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_41) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_859 = shr(io.in.a.bits.source, 2) node _T_860 = eq(_T_859, UInt<2>(0h2)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_42) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_865 = shr(io.in.a.bits.source, 2) node _T_866 = eq(_T_865, UInt<2>(0h3)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_43) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_870 = and(_T_868, _T_869) node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_872 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_873 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_874 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_875 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_876 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_877 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_878 = or(_T_846, _T_852) node _T_879 = or(_T_878, _T_858) node _T_880 = or(_T_879, _T_864) node _T_881 = or(_T_880, _T_870) node _T_882 = or(_T_881, _T_871) node _T_883 = or(_T_882, _T_872) node _T_884 = or(_T_883, _T_873) node _T_885 = or(_T_884, _T_874) node _T_886 = or(_T_885, _T_875) node _T_887 = or(_T_886, _T_876) node _T_888 = or(_T_887, _T_877) node _T_889 = and(_T_845, _T_888) node _T_890 = or(UInt<1>(0h0), _T_889) node _T_891 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_892 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<18>(0h2f000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), _T_897) node _T_899 = and(_T_890, _T_898) node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(_T_899, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_899, UInt<1>(0h1), "") : assert_46 node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(source_ok, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(is_aligned, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_909 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(_T_909, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_909, UInt<1>(0h1), "") : assert_49 node _T_913 = eq(io.in.a.bits.mask, mask) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_913, UInt<1>(0h1), "") : assert_50 node _T_917 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_917, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_921 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_921, UInt<1>(0h1), "") : assert_52 node _source_ok_T_42 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h0)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<1>(0h1)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h2)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_61 = shr(io.in.d.bits.source, 2) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<2>(0h3)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_68 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_69 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[12] connect _source_ok_WIRE_1[0], _source_ok_T_42 connect _source_ok_WIRE_1[1], _source_ok_T_48 connect _source_ok_WIRE_1[2], _source_ok_T_54 connect _source_ok_WIRE_1[3], _source_ok_T_60 connect _source_ok_WIRE_1[4], _source_ok_T_66 connect _source_ok_WIRE_1[5], _source_ok_T_67 connect _source_ok_WIRE_1[6], _source_ok_T_68 connect _source_ok_WIRE_1[7], _source_ok_T_69 connect _source_ok_WIRE_1[8], _source_ok_T_70 connect _source_ok_WIRE_1[9], _source_ok_T_71 connect _source_ok_WIRE_1[10], _source_ok_T_72 connect _source_ok_WIRE_1[11], _source_ok_T_73 node _source_ok_T_74 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[2]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[3]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[4]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[5]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[6]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[7]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[8]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[9]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[10]) node source_ok_1 = or(_source_ok_T_83, _source_ok_WIRE_1[11]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_925 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_925 : node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(source_ok_1, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_929 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_929, UInt<1>(0h1), "") : assert_54 node _T_933 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_933, UInt<1>(0h1), "") : assert_55 node _T_937 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_937, UInt<1>(0h1), "") : assert_56 node _T_941 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_941, UInt<1>(0h1), "") : assert_57 node _T_945 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_945 : node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok_1, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(sink_ok, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_952 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_952, UInt<1>(0h1), "") : assert_60 node _T_956 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_956, UInt<1>(0h1), "") : assert_61 node _T_960 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_960, UInt<1>(0h1), "") : assert_62 node _T_964 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_964, UInt<1>(0h1), "") : assert_63 node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_969, UInt<1>(0h1), "") : assert_64 node _T_973 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_973 : node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok_1, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(sink_ok, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_980 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_980, UInt<1>(0h1), "") : assert_67 node _T_984 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_984, UInt<1>(0h1), "") : assert_68 node _T_988 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_988, UInt<1>(0h1), "") : assert_69 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(_T_992, io.in.d.bits.corrupt) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_993, UInt<1>(0h1), "") : assert_70 node _T_997 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_998 = or(UInt<1>(0h0), _T_997) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_998, UInt<1>(0h1), "") : assert_71 node _T_1002 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1002 : node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(source_ok_1, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1006 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_73 node _T_1010 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_74 node _T_1014 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1015 = or(UInt<1>(0h0), _T_1014) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_75 node _T_1019 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1019 : node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(source_ok_1, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1023 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_77 node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1028 = or(_T_1027, io.in.d.bits.corrupt) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_78 node _T_1032 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1033 = or(UInt<1>(0h0), _T_1032) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_79 node _T_1037 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1037 : node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(source_ok_1, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_81 node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_82 node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1050 = or(UInt<1>(0h0), _T_1049) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1054 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1058 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1062 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1066 = eq(a_first, UInt<1>(0h0)) node _T_1067 = and(io.in.a.valid, _T_1066) when _T_1067 : node _T_1068 = eq(io.in.a.bits.opcode, opcode) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_87 node _T_1072 = eq(io.in.a.bits.param, param) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_88 node _T_1076 = eq(io.in.a.bits.size, size) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_89 node _T_1080 = eq(io.in.a.bits.source, source) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_90 node _T_1084 = eq(io.in.a.bits.address, address) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_91 node _T_1088 = and(io.in.a.ready, io.in.a.valid) node _T_1089 = and(_T_1088, a_first) when _T_1089 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1090 = eq(d_first, UInt<1>(0h0)) node _T_1091 = and(io.in.d.valid, _T_1090) when _T_1091 : node _T_1092 = eq(io.in.d.bits.opcode, opcode_1) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_92 node _T_1096 = eq(io.in.d.bits.param, param_1) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_93 node _T_1100 = eq(io.in.d.bits.size, size_1) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_94 node _T_1104 = eq(io.in.d.bits.source, source_1) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_95 node _T_1108 = eq(io.in.d.bits.sink, sink) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_96 node _T_1112 = eq(io.in.d.bits.denied, denied) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_97 node _T_1116 = and(io.in.d.ready, io.in.d.valid) node _T_1117 = and(_T_1116, d_first) when _T_1117 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1118 = and(io.in.a.valid, a_first_1) node _T_1119 = and(_T_1118, UInt<1>(0h1)) when _T_1119 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1120 = and(io.in.a.ready, io.in.a.valid) node _T_1121 = and(_T_1120, a_first_1) node _T_1122 = and(_T_1121, UInt<1>(0h1)) when _T_1122 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1123 = dshr(inflight, io.in.a.bits.source) node _T_1124 = bits(_T_1123, 0, 0) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1129 = and(io.in.d.valid, d_first_1) node _T_1130 = and(_T_1129, UInt<1>(0h1)) node _T_1131 = eq(d_release_ack, UInt<1>(0h0)) node _T_1132 = and(_T_1130, _T_1131) when _T_1132 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1133 = and(io.in.d.ready, io.in.d.valid) node _T_1134 = and(_T_1133, d_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) node _T_1136 = eq(d_release_ack, UInt<1>(0h0)) node _T_1137 = and(_T_1135, _T_1136) when _T_1137 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1138 = and(io.in.d.valid, d_first_1) node _T_1139 = and(_T_1138, UInt<1>(0h1)) node _T_1140 = eq(d_release_ack, UInt<1>(0h0)) node _T_1141 = and(_T_1139, _T_1140) when _T_1141 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1142 = dshr(inflight, io.in.d.bits.source) node _T_1143 = bits(_T_1142, 0, 0) node _T_1144 = or(_T_1143, same_cycle_resp) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1148 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1149 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1150 = or(_T_1148, _T_1149) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_100 node _T_1154 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_101 else : node _T_1158 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1159 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1160 = or(_T_1158, _T_1159) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_102 node _T_1164 = eq(io.in.d.bits.size, a_size_lookup) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_103 node _T_1168 = and(io.in.d.valid, d_first_1) node _T_1169 = and(_T_1168, a_first_1) node _T_1170 = and(_T_1169, io.in.a.valid) node _T_1171 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1172 = and(_T_1170, _T_1171) node _T_1173 = eq(d_release_ack, UInt<1>(0h0)) node _T_1174 = and(_T_1172, _T_1173) when _T_1174 : node _T_1175 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1176 = or(_T_1175, io.in.a.ready) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_122 node _T_1180 = orr(inflight) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) node _T_1182 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1183 = or(_T_1181, _T_1182) node _T_1184 = lt(watchdog, plusarg_reader.out) node _T_1185 = or(_T_1183, _T_1184) node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(_T_1185, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1185, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1189 = and(io.in.a.ready, io.in.a.valid) node _T_1190 = and(io.in.d.ready, io.in.d.valid) node _T_1191 = or(_T_1189, _T_1190) when _T_1191 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1192 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1193 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1194 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1195 = and(_T_1193, _T_1194) node _T_1196 = and(_T_1192, _T_1195) when _T_1196 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1197 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1198 = and(_T_1197, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1199 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1200 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = and(_T_1198, _T_1201) when _T_1202 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1203 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1209 = and(io.in.d.valid, d_first_2) node _T_1210 = and(_T_1209, UInt<1>(0h1)) node _T_1211 = and(_T_1210, d_release_ack_1) when _T_1211 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1212 = and(io.in.d.ready, io.in.d.valid) node _T_1213 = and(_T_1212, d_first_2) node _T_1214 = and(_T_1213, UInt<1>(0h1)) node _T_1215 = and(_T_1214, d_release_ack_1) when _T_1215 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1216 = and(io.in.d.valid, d_first_2) node _T_1217 = and(_T_1216, UInt<1>(0h1)) node _T_1218 = and(_T_1217, d_release_ack_1) when _T_1218 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1219 = dshr(inflight_1, io.in.d.bits.source) node _T_1220 = bits(_T_1219, 0, 0) node _T_1221 = or(_T_1220, same_cycle_resp_1) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1225 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_108 else : node _T_1229 = eq(io.in.d.bits.size, c_size_lookup) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_109 node _T_1233 = and(io.in.d.valid, d_first_2) node _T_1234 = and(_T_1233, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1235 = and(_T_1234, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1236 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1237 = and(_T_1235, _T_1236) node _T_1238 = and(_T_1237, d_release_ack_1) node _T_1239 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1240 = and(_T_1238, _T_1239) when _T_1240 : node _T_1241 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1242 = or(_T_1241, _WIRE_27.ready) node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(_T_1242, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1242, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_123 node _T_1246 = orr(inflight_1) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) node _T_1248 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1249 = or(_T_1247, _T_1248) node _T_1250 = lt(watchdog_1, plusarg_reader_1.out) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1255 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1256 = and(io.in.d.ready, io.in.d.valid) node _T_1257 = or(_T_1255, _T_1256) when _T_1257 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_59( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_41 \| _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_61 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_44 = _source_ok_T_43 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_62 = _source_ok_T_61 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire _source_ok_T_67 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire _source_ok_T_68 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire _source_ok_T_69 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_82 = _source_ok_T_81 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_83 = _source_ok_T_82 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_83 \| _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _T_1189 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1189; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1189; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1257 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1257; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1122 = _T_1189 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1122 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1122 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1122 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1122 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1122 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1168 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1168 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1137 = _T_1257 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1137 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1137 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1137 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1233 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1233 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1215 = _T_1257 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1215 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1215 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1215 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_182 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_203 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_182( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_203 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a14d64s7k1z4u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_23 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a14d64s7k1z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a14d64s7k1z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<14>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<14>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<14>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLBuffer_a14d64s7k1z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [13:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [13:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [63:0] nodeOut_d_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h1; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h1; // @[Decoupled.scala:362:21] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [13:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [13:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [13:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_23 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a14d64s7k1z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a14d64s7k1z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_344 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_88 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_344( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_88 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a21d64s7k1z3u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_28 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a21d64s7k1z3u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a21d64s7k1z3u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLBuffer_a21d64s7k1z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [6:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_28 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a21d64s7k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a21d64s7k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_data (auto_out_d_bits_data), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_8 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h110)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h40)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h41)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h42)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h43)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0) node _source_ok_T_28 = shr(io.in.a.bits.source, 5) node _source_ok_T_29 = eq(_source_ok_T_28, UInt<1>(0h0)) node _source_ok_T_30 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) node _source_ok_T_32 = leq(source_ok_uncommonBits_4, UInt<5>(0h1f)) node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0) node _source_ok_T_34 = shr(io.in.a.bits.source, 5) node _source_ok_T_35 = eq(_source_ok_T_34, UInt<1>(0h1)) node _source_ok_T_36 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) node _source_ok_T_38 = leq(source_ok_uncommonBits_5, UInt<5>(0h1f)) node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_40 = shr(io.in.a.bits.source, 5) node _source_ok_T_41 = eq(_source_ok_T_40, UInt<2>(0h2)) node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_T_44 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f)) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_46 = shr(io.in.a.bits.source, 5) node _source_ok_T_47 = eq(_source_ok_T_46, UInt<2>(0h3)) node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_T_50 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f)) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_52 = shr(io.in.a.bits.source, 5) node _source_ok_T_53 = eq(_source_ok_T_52, UInt<3>(0h4)) node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_T_56 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f)) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_58 = shr(io.in.a.bits.source, 5) node _source_ok_T_59 = eq(_source_ok_T_58, UInt<3>(0h5)) node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_T_62 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f)) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_64 = shr(io.in.a.bits.source, 5) node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h6)) node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_T_68 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f)) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_70 = shr(io.in.a.bits.source, 5) node _source_ok_T_71 = eq(_source_ok_T_70, UInt<3>(0h7)) node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_T_74 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f)) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_T_76 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE : UInt<1>[17] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_33 connect _source_ok_WIRE[9], _source_ok_T_39 connect _source_ok_WIRE[10], _source_ok_T_45 connect _source_ok_WIRE[11], _source_ok_T_51 connect _source_ok_WIRE[12], _source_ok_T_57 connect _source_ok_WIRE[13], _source_ok_T_63 connect _source_ok_WIRE[14], _source_ok_T_69 connect _source_ok_WIRE[15], _source_ok_T_75 connect _source_ok_WIRE[16], _source_ok_T_76 node _source_ok_T_77 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[2]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[3]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[4]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[5]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[6]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[7]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[8]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[9]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[10]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[11]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[12]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[13]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[14]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[15]) node source_ok = or(_source_ok_T_91, _source_ok_WIRE[16]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<7>(0h40)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<7>(0h41)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<7>(0h42)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<7>(0h43)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_88 = shr(io.in.a.bits.source, 5) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = leq(UInt<1>(0h0), uncommonBits_4) node _T_91 = and(_T_89, _T_90) node _T_92 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_93 = and(_T_91, _T_92) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_101 = shr(io.in.a.bits.source, 5) node _T_102 = eq(_T_101, UInt<1>(0h1)) node _T_103 = leq(UInt<1>(0h0), uncommonBits_5) node _T_104 = and(_T_102, _T_103) node _T_105 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_114 = shr(io.in.a.bits.source, 5) node _T_115 = eq(_T_114, UInt<2>(0h2)) node _T_116 = leq(UInt<1>(0h0), uncommonBits_6) node _T_117 = and(_T_115, _T_116) node _T_118 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = or(_T_120, _T_125) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_127 = shr(io.in.a.bits.source, 5) node _T_128 = eq(_T_127, UInt<2>(0h3)) node _T_129 = leq(UInt<1>(0h0), uncommonBits_7) node _T_130 = and(_T_128, _T_129) node _T_131 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_132 = and(_T_130, _T_131) node _T_133 = eq(_T_132, UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = or(_T_133, _T_138) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_140 = shr(io.in.a.bits.source, 5) node _T_141 = eq(_T_140, UInt<3>(0h4)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_8) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_145 = and(_T_143, _T_144) node _T_146 = eq(_T_145, UInt<1>(0h0)) node _T_147 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = or(_T_146, _T_151) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_153 = shr(io.in.a.bits.source, 5) node _T_154 = eq(_T_153, UInt<3>(0h5)) node _T_155 = leq(UInt<1>(0h0), uncommonBits_9) node _T_156 = and(_T_154, _T_155) node _T_157 = leq(uncommonBits_9, UInt<5>(0h1f)) node _T_158 = and(_T_156, _T_157) node _T_159 = eq(_T_158, UInt<1>(0h0)) node _T_160 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<1>(0h0))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = or(_T_159, _T_164) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_166 = shr(io.in.a.bits.source, 5) node _T_167 = eq(_T_166, UInt<3>(0h6)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_10) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_10, UInt<5>(0h1f)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(_T_171, UInt<1>(0h0)) node _T_173 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_174 = cvt(_T_173) node _T_175 = and(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = asSInt(_T_175) node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = or(_T_172, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_179 = shr(io.in.a.bits.source, 5) node _T_180 = eq(_T_179, UInt<3>(0h7)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<5>(0h1f)) node _T_184 = and(_T_182, _T_183) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = and(_T_11, _T_24) node _T_201 = and(_T_200, _T_37) node _T_202 = and(_T_201, _T_50) node _T_203 = and(_T_202, _T_63) node _T_204 = and(_T_203, _T_71) node _T_205 = and(_T_204, _T_79) node _T_206 = and(_T_205, _T_87) node _T_207 = and(_T_206, _T_100) node _T_208 = and(_T_207, _T_113) node _T_209 = and(_T_208, _T_126) node _T_210 = and(_T_209, _T_139) node _T_211 = and(_T_210, _T_152) node _T_212 = and(_T_211, _T_165) node _T_213 = and(_T_212, _T_178) node _T_214 = and(_T_213, _T_191) node _T_215 = and(_T_214, _T_199) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_215, UInt<1>(0h1), "") : assert_1 node _T_219 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_219 : node _T_220 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_221 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_222 = and(_T_220, _T_221) node _T_223 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_224 = shr(io.in.a.bits.source, 2) node _T_225 = eq(_T_224, UInt<7>(0h40)) node _T_226 = leq(UInt<1>(0h0), uncommonBits_12) node _T_227 = and(_T_225, _T_226) node _T_228 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_229 = and(_T_227, _T_228) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_230 = shr(io.in.a.bits.source, 2) node _T_231 = eq(_T_230, UInt<7>(0h41)) node _T_232 = leq(UInt<1>(0h0), uncommonBits_13) node _T_233 = and(_T_231, _T_232) node _T_234 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_235 = and(_T_233, _T_234) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_236 = shr(io.in.a.bits.source, 2) node _T_237 = eq(_T_236, UInt<7>(0h42)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_14) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_242 = shr(io.in.a.bits.source, 2) node _T_243 = eq(_T_242, UInt<7>(0h43)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_15) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_247 = and(_T_245, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_249 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_250 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_251 = shr(io.in.a.bits.source, 5) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_16) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_16, UInt<5>(0h1f)) node _T_256 = and(_T_254, _T_255) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_257 = shr(io.in.a.bits.source, 5) node _T_258 = eq(_T_257, UInt<1>(0h1)) node _T_259 = leq(UInt<1>(0h0), uncommonBits_17) node _T_260 = and(_T_258, _T_259) node _T_261 = leq(uncommonBits_17, UInt<5>(0h1f)) node _T_262 = and(_T_260, _T_261) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_263 = shr(io.in.a.bits.source, 5) node _T_264 = eq(_T_263, UInt<2>(0h2)) node _T_265 = leq(UInt<1>(0h0), uncommonBits_18) node _T_266 = and(_T_264, _T_265) node _T_267 = leq(uncommonBits_18, UInt<5>(0h1f)) node _T_268 = and(_T_266, _T_267) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_269 = shr(io.in.a.bits.source, 5) node _T_270 = eq(_T_269, UInt<2>(0h3)) node _T_271 = leq(UInt<1>(0h0), uncommonBits_19) node _T_272 = and(_T_270, _T_271) node _T_273 = leq(uncommonBits_19, UInt<5>(0h1f)) node _T_274 = and(_T_272, _T_273) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_275 = shr(io.in.a.bits.source, 5) node _T_276 = eq(_T_275, UInt<3>(0h4)) node _T_277 = leq(UInt<1>(0h0), uncommonBits_20) node _T_278 = and(_T_276, _T_277) node _T_279 = leq(uncommonBits_20, UInt<5>(0h1f)) node _T_280 = and(_T_278, _T_279) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_281 = shr(io.in.a.bits.source, 5) node _T_282 = eq(_T_281, UInt<3>(0h5)) node _T_283 = leq(UInt<1>(0h0), uncommonBits_21) node _T_284 = and(_T_282, _T_283) node _T_285 = leq(uncommonBits_21, UInt<5>(0h1f)) node _T_286 = and(_T_284, _T_285) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0) node _T_287 = shr(io.in.a.bits.source, 5) node _T_288 = eq(_T_287, UInt<3>(0h6)) node _T_289 = leq(UInt<1>(0h0), uncommonBits_22) node _T_290 = and(_T_288, _T_289) node _T_291 = leq(uncommonBits_22, UInt<5>(0h1f)) node _T_292 = and(_T_290, _T_291) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0) node _T_293 = shr(io.in.a.bits.source, 5) node _T_294 = eq(_T_293, UInt<3>(0h7)) node _T_295 = leq(UInt<1>(0h0), uncommonBits_23) node _T_296 = and(_T_294, _T_295) node _T_297 = leq(uncommonBits_23, UInt<5>(0h1f)) node _T_298 = and(_T_296, _T_297) node _T_299 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_300 = or(_T_223, _T_229) node _T_301 = or(_T_300, _T_235) node _T_302 = or(_T_301, _T_241) node _T_303 = or(_T_302, _T_247) node _T_304 = or(_T_303, _T_248) node _T_305 = or(_T_304, _T_249) node _T_306 = or(_T_305, _T_250) node _T_307 = or(_T_306, _T_256) node _T_308 = or(_T_307, _T_262) node _T_309 = or(_T_308, _T_268) node _T_310 = or(_T_309, _T_274) node _T_311 = or(_T_310, _T_280) node _T_312 = or(_T_311, _T_286) node _T_313 = or(_T_312, _T_292) node _T_314 = or(_T_313, _T_298) node _T_315 = or(_T_314, _T_299) node _T_316 = and(_T_222, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<13>(0h1000))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<13>(0h1000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_330 = cvt(_T_329) node _T_331 = and(_T_330, asSInt(UInt<19>(0h40000))) node _T_332 = asSInt(_T_331) node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0))) node _T_334 = or(_T_323, _T_328) node _T_335 = or(_T_334, _T_333) node _T_336 = and(_T_318, _T_335) node _T_337 = or(UInt<1>(0h0), _T_336) node _T_338 = and(_T_317, _T_337) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_338, UInt<1>(0h1), "") : assert_2 node _T_342 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_343 = shr(io.in.a.bits.source, 2) node _T_344 = eq(_T_343, UInt<7>(0h40)) node _T_345 = leq(UInt<1>(0h0), uncommonBits_24) node _T_346 = and(_T_344, _T_345) node _T_347 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_348 = and(_T_346, _T_347) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_349 = shr(io.in.a.bits.source, 2) node _T_350 = eq(_T_349, UInt<7>(0h41)) node _T_351 = leq(UInt<1>(0h0), uncommonBits_25) node _T_352 = and(_T_350, _T_351) node _T_353 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_354 = and(_T_352, _T_353) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_355 = shr(io.in.a.bits.source, 2) node _T_356 = eq(_T_355, UInt<7>(0h42)) node _T_357 = leq(UInt<1>(0h0), uncommonBits_26) node _T_358 = and(_T_356, _T_357) node _T_359 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_360 = and(_T_358, _T_359) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_361 = shr(io.in.a.bits.source, 2) node _T_362 = eq(_T_361, UInt<7>(0h43)) node _T_363 = leq(UInt<1>(0h0), uncommonBits_27) node _T_364 = and(_T_362, _T_363) node _T_365 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_366 = and(_T_364, _T_365) node _T_367 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_368 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_369 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_370 = shr(io.in.a.bits.source, 5) node _T_371 = eq(_T_370, UInt<1>(0h0)) node _T_372 = leq(UInt<1>(0h0), uncommonBits_28) node _T_373 = and(_T_371, _T_372) node _T_374 = leq(uncommonBits_28, UInt<5>(0h1f)) node _T_375 = and(_T_373, _T_374) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_376 = shr(io.in.a.bits.source, 5) node _T_377 = eq(_T_376, UInt<1>(0h1)) node _T_378 = leq(UInt<1>(0h0), uncommonBits_29) node _T_379 = and(_T_377, _T_378) node _T_380 = leq(uncommonBits_29, UInt<5>(0h1f)) node _T_381 = and(_T_379, _T_380) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_382 = shr(io.in.a.bits.source, 5) node _T_383 = eq(_T_382, UInt<2>(0h2)) node _T_384 = leq(UInt<1>(0h0), uncommonBits_30) node _T_385 = and(_T_383, _T_384) node _T_386 = leq(uncommonBits_30, UInt<5>(0h1f)) node _T_387 = and(_T_385, _T_386) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_388 = shr(io.in.a.bits.source, 5) node _T_389 = eq(_T_388, UInt<2>(0h3)) node _T_390 = leq(UInt<1>(0h0), uncommonBits_31) node _T_391 = and(_T_389, _T_390) node _T_392 = leq(uncommonBits_31, UInt<5>(0h1f)) node _T_393 = and(_T_391, _T_392) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_394 = shr(io.in.a.bits.source, 5) node _T_395 = eq(_T_394, UInt<3>(0h4)) node _T_396 = leq(UInt<1>(0h0), uncommonBits_32) node _T_397 = and(_T_395, _T_396) node _T_398 = leq(uncommonBits_32, UInt<5>(0h1f)) node _T_399 = and(_T_397, _T_398) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_400 = shr(io.in.a.bits.source, 5) node _T_401 = eq(_T_400, UInt<3>(0h5)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_33) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_33, UInt<5>(0h1f)) node _T_405 = and(_T_403, _T_404) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0) node _T_406 = shr(io.in.a.bits.source, 5) node _T_407 = eq(_T_406, UInt<3>(0h6)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_34) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_34, UInt<5>(0h1f)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0) node _T_412 = shr(io.in.a.bits.source, 5) node _T_413 = eq(_T_412, UInt<3>(0h7)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_35) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_35, UInt<5>(0h1f)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE : UInt<1>[17] connect _WIRE[0], _T_342 connect _WIRE[1], _T_348 connect _WIRE[2], _T_354 connect _WIRE[3], _T_360 connect _WIRE[4], _T_366 connect _WIRE[5], _T_367 connect _WIRE[6], _T_368 connect _WIRE[7], _T_369 connect _WIRE[8], _T_375 connect _WIRE[9], _T_381 connect _WIRE[10], _T_387 connect _WIRE[11], _T_393 connect _WIRE[12], _T_399 connect _WIRE[13], _T_405 connect _WIRE[14], _T_411 connect _WIRE[15], _T_417 connect _WIRE[16], _T_418 node _T_419 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_420 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_421 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_422 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_423 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_424 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_425 = mux(_WIRE[5], _T_419, UInt<1>(0h0)) node _T_426 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_427 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_428 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_429 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_430 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_431 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_432 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_433 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_434 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_435 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_436 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_437 = or(_T_420, _T_421) node _T_438 = or(_T_437, _T_422) node _T_439 = or(_T_438, _T_423) node _T_440 = or(_T_439, _T_424) node _T_441 = or(_T_440, _T_425) node _T_442 = or(_T_441, _T_426) node _T_443 = or(_T_442, _T_427) node _T_444 = or(_T_443, _T_428) node _T_445 = or(_T_444, _T_429) node _T_446 = or(_T_445, _T_430) node _T_447 = or(_T_446, _T_431) node _T_448 = or(_T_447, _T_432) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_434) node _T_451 = or(_T_450, _T_435) node _T_452 = or(_T_451, _T_436) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_452 node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_454 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_455 = and(_T_453, _T_454) node _T_456 = or(UInt<1>(0h0), _T_455) node _T_457 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<13>(0h1000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<19>(0h40000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = or(_T_461, _T_466) node _T_473 = or(_T_472, _T_471) node _T_474 = and(_T_456, _T_473) node _T_475 = or(UInt<1>(0h0), _T_474) node _T_476 = and(_WIRE_1, _T_475) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_476, UInt<1>(0h1), "") : assert_3 node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(source_ok, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_483 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(_T_483, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_483, UInt<1>(0h1), "") : assert_5 node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(is_aligned, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_490 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_491 = asUInt(reset) node _T_492 = eq(_T_491, UInt<1>(0h0)) when _T_492 : node _T_493 = eq(_T_490, UInt<1>(0h0)) when _T_493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_490, UInt<1>(0h1), "") : assert_7 node _T_494 = not(io.in.a.bits.mask) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_495, UInt<1>(0h1), "") : assert_8 node _T_499 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_499, UInt<1>(0h1), "") : assert_9 node _T_503 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_503 : node _T_504 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_505 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_506 = and(_T_504, _T_505) node _T_507 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_508 = shr(io.in.a.bits.source, 2) node _T_509 = eq(_T_508, UInt<7>(0h40)) node _T_510 = leq(UInt<1>(0h0), uncommonBits_36) node _T_511 = and(_T_509, _T_510) node _T_512 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_513 = and(_T_511, _T_512) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_514 = shr(io.in.a.bits.source, 2) node _T_515 = eq(_T_514, UInt<7>(0h41)) node _T_516 = leq(UInt<1>(0h0), uncommonBits_37) node _T_517 = and(_T_515, _T_516) node _T_518 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_519 = and(_T_517, _T_518) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_520 = shr(io.in.a.bits.source, 2) node _T_521 = eq(_T_520, UInt<7>(0h42)) node _T_522 = leq(UInt<1>(0h0), uncommonBits_38) node _T_523 = and(_T_521, _T_522) node _T_524 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_525 = and(_T_523, _T_524) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<7>(0h43)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_39) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _T_532 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_533 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_534 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_535 = shr(io.in.a.bits.source, 5) node _T_536 = eq(_T_535, UInt<1>(0h0)) node _T_537 = leq(UInt<1>(0h0), uncommonBits_40) node _T_538 = and(_T_536, _T_537) node _T_539 = leq(uncommonBits_40, UInt<5>(0h1f)) node _T_540 = and(_T_538, _T_539) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_541 = shr(io.in.a.bits.source, 5) node _T_542 = eq(_T_541, UInt<1>(0h1)) node _T_543 = leq(UInt<1>(0h0), uncommonBits_41) node _T_544 = and(_T_542, _T_543) node _T_545 = leq(uncommonBits_41, UInt<5>(0h1f)) node _T_546 = and(_T_544, _T_545) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_547 = shr(io.in.a.bits.source, 5) node _T_548 = eq(_T_547, UInt<2>(0h2)) node _T_549 = leq(UInt<1>(0h0), uncommonBits_42) node _T_550 = and(_T_548, _T_549) node _T_551 = leq(uncommonBits_42, UInt<5>(0h1f)) node _T_552 = and(_T_550, _T_551) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_553 = shr(io.in.a.bits.source, 5) node _T_554 = eq(_T_553, UInt<2>(0h3)) node _T_555 = leq(UInt<1>(0h0), uncommonBits_43) node _T_556 = and(_T_554, _T_555) node _T_557 = leq(uncommonBits_43, UInt<5>(0h1f)) node _T_558 = and(_T_556, _T_557) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0) node _T_559 = shr(io.in.a.bits.source, 5) node _T_560 = eq(_T_559, UInt<3>(0h4)) node _T_561 = leq(UInt<1>(0h0), uncommonBits_44) node _T_562 = and(_T_560, _T_561) node _T_563 = leq(uncommonBits_44, UInt<5>(0h1f)) node _T_564 = and(_T_562, _T_563) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0) node _T_565 = shr(io.in.a.bits.source, 5) node _T_566 = eq(_T_565, UInt<3>(0h5)) node _T_567 = leq(UInt<1>(0h0), uncommonBits_45) node _T_568 = and(_T_566, _T_567) node _T_569 = leq(uncommonBits_45, UInt<5>(0h1f)) node _T_570 = and(_T_568, _T_569) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0) node _T_571 = shr(io.in.a.bits.source, 5) node _T_572 = eq(_T_571, UInt<3>(0h6)) node _T_573 = leq(UInt<1>(0h0), uncommonBits_46) node _T_574 = and(_T_572, _T_573) node _T_575 = leq(uncommonBits_46, UInt<5>(0h1f)) node _T_576 = and(_T_574, _T_575) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0) node _T_577 = shr(io.in.a.bits.source, 5) node _T_578 = eq(_T_577, UInt<3>(0h7)) node _T_579 = leq(UInt<1>(0h0), uncommonBits_47) node _T_580 = and(_T_578, _T_579) node _T_581 = leq(uncommonBits_47, UInt<5>(0h1f)) node _T_582 = and(_T_580, _T_581) node _T_583 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_584 = or(_T_507, _T_513) node _T_585 = or(_T_584, _T_519) node _T_586 = or(_T_585, _T_525) node _T_587 = or(_T_586, _T_531) node _T_588 = or(_T_587, _T_532) node _T_589 = or(_T_588, _T_533) node _T_590 = or(_T_589, _T_534) node _T_591 = or(_T_590, _T_540) node _T_592 = or(_T_591, _T_546) node _T_593 = or(_T_592, _T_552) node _T_594 = or(_T_593, _T_558) node _T_595 = or(_T_594, _T_564) node _T_596 = or(_T_595, _T_570) node _T_597 = or(_T_596, _T_576) node _T_598 = or(_T_597, _T_582) node _T_599 = or(_T_598, _T_583) node _T_600 = and(_T_506, _T_599) node _T_601 = or(UInt<1>(0h0), _T_600) node _T_602 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_603 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_604 = cvt(_T_603) node _T_605 = and(_T_604, asSInt(UInt<13>(0h1000))) node _T_606 = asSInt(_T_605) node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0))) node _T_608 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_609 = cvt(_T_608) node _T_610 = and(_T_609, asSInt(UInt<13>(0h1000))) node _T_611 = asSInt(_T_610) node _T_612 = eq(_T_611, asSInt(UInt<1>(0h0))) node _T_613 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_614 = cvt(_T_613) node _T_615 = and(_T_614, asSInt(UInt<19>(0h40000))) node _T_616 = asSInt(_T_615) node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) node _T_618 = or(_T_607, _T_612) node _T_619 = or(_T_618, _T_617) node _T_620 = and(_T_602, _T_619) node _T_621 = or(UInt<1>(0h0), _T_620) node _T_622 = and(_T_601, _T_621) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_622, UInt<1>(0h1), "") : assert_10 node _T_626 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_627 = shr(io.in.a.bits.source, 2) node _T_628 = eq(_T_627, UInt<7>(0h40)) node _T_629 = leq(UInt<1>(0h0), uncommonBits_48) node _T_630 = and(_T_628, _T_629) node _T_631 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_632 = and(_T_630, _T_631) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_633 = shr(io.in.a.bits.source, 2) node _T_634 = eq(_T_633, UInt<7>(0h41)) node _T_635 = leq(UInt<1>(0h0), uncommonBits_49) node _T_636 = and(_T_634, _T_635) node _T_637 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_638 = and(_T_636, _T_637) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_639 = shr(io.in.a.bits.source, 2) node _T_640 = eq(_T_639, UInt<7>(0h42)) node _T_641 = leq(UInt<1>(0h0), uncommonBits_50) node _T_642 = and(_T_640, _T_641) node _T_643 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_644 = and(_T_642, _T_643) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_645 = shr(io.in.a.bits.source, 2) node _T_646 = eq(_T_645, UInt<7>(0h43)) node _T_647 = leq(UInt<1>(0h0), uncommonBits_51) node _T_648 = and(_T_646, _T_647) node _T_649 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_650 = and(_T_648, _T_649) node _T_651 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_652 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_653 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_654 = shr(io.in.a.bits.source, 5) node _T_655 = eq(_T_654, UInt<1>(0h0)) node _T_656 = leq(UInt<1>(0h0), uncommonBits_52) node _T_657 = and(_T_655, _T_656) node _T_658 = leq(uncommonBits_52, UInt<5>(0h1f)) node _T_659 = and(_T_657, _T_658) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_660 = shr(io.in.a.bits.source, 5) node _T_661 = eq(_T_660, UInt<1>(0h1)) node _T_662 = leq(UInt<1>(0h0), uncommonBits_53) node _T_663 = and(_T_661, _T_662) node _T_664 = leq(uncommonBits_53, UInt<5>(0h1f)) node _T_665 = and(_T_663, _T_664) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_666 = shr(io.in.a.bits.source, 5) node _T_667 = eq(_T_666, UInt<2>(0h2)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_54) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_54, UInt<5>(0h1f)) node _T_671 = and(_T_669, _T_670) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_672 = shr(io.in.a.bits.source, 5) node _T_673 = eq(_T_672, UInt<2>(0h3)) node _T_674 = leq(UInt<1>(0h0), uncommonBits_55) node _T_675 = and(_T_673, _T_674) node _T_676 = leq(uncommonBits_55, UInt<5>(0h1f)) node _T_677 = and(_T_675, _T_676) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0) node _T_678 = shr(io.in.a.bits.source, 5) node _T_679 = eq(_T_678, UInt<3>(0h4)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_56) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_56, UInt<5>(0h1f)) node _T_683 = and(_T_681, _T_682) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0) node _T_684 = shr(io.in.a.bits.source, 5) node _T_685 = eq(_T_684, UInt<3>(0h5)) node _T_686 = leq(UInt<1>(0h0), uncommonBits_57) node _T_687 = and(_T_685, _T_686) node _T_688 = leq(uncommonBits_57, UInt<5>(0h1f)) node _T_689 = and(_T_687, _T_688) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_690 = shr(io.in.a.bits.source, 5) node _T_691 = eq(_T_690, UInt<3>(0h6)) node _T_692 = leq(UInt<1>(0h0), uncommonBits_58) node _T_693 = and(_T_691, _T_692) node _T_694 = leq(uncommonBits_58, UInt<5>(0h1f)) node _T_695 = and(_T_693, _T_694) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_696 = shr(io.in.a.bits.source, 5) node _T_697 = eq(_T_696, UInt<3>(0h7)) node _T_698 = leq(UInt<1>(0h0), uncommonBits_59) node _T_699 = and(_T_697, _T_698) node _T_700 = leq(uncommonBits_59, UInt<5>(0h1f)) node _T_701 = and(_T_699, _T_700) node _T_702 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE_2 : UInt<1>[17] connect _WIRE_2[0], _T_626 connect _WIRE_2[1], _T_632 connect _WIRE_2[2], _T_638 connect _WIRE_2[3], _T_644 connect _WIRE_2[4], _T_650 connect _WIRE_2[5], _T_651 connect _WIRE_2[6], _T_652 connect _WIRE_2[7], _T_653 connect _WIRE_2[8], _T_659 connect _WIRE_2[9], _T_665 connect _WIRE_2[10], _T_671 connect _WIRE_2[11], _T_677 connect _WIRE_2[12], _T_683 connect _WIRE_2[13], _T_689 connect _WIRE_2[14], _T_695 connect _WIRE_2[15], _T_701 connect _WIRE_2[16], _T_702 node _T_703 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_704 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_705 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_707 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_708 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_709 = mux(_WIRE_2[5], _T_703, UInt<1>(0h0)) node _T_710 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_711 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_712 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_713 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_714 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_715 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_716 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_717 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_719 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_720 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_721 = or(_T_704, _T_705) node _T_722 = or(_T_721, _T_706) node _T_723 = or(_T_722, _T_707) node _T_724 = or(_T_723, _T_708) node _T_725 = or(_T_724, _T_709) node _T_726 = or(_T_725, _T_710) node _T_727 = or(_T_726, _T_711) node _T_728 = or(_T_727, _T_712) node _T_729 = or(_T_728, _T_713) node _T_730 = or(_T_729, _T_714) node _T_731 = or(_T_730, _T_715) node _T_732 = or(_T_731, _T_716) node _T_733 = or(_T_732, _T_717) node _T_734 = or(_T_733, _T_718) node _T_735 = or(_T_734, _T_719) node _T_736 = or(_T_735, _T_720) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_736 node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_738 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_739 = and(_T_737, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<13>(0h1000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<19>(0h40000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = or(_T_745, _T_750) node _T_757 = or(_T_756, _T_755) node _T_758 = and(_T_740, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = and(_WIRE_3, _T_759) node _T_761 = asUInt(reset) node _T_762 = eq(_T_761, UInt<1>(0h0)) when _T_762 : node _T_763 = eq(_T_760, UInt<1>(0h0)) when _T_763 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_760, UInt<1>(0h1), "") : assert_11 node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(source_ok, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_767 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_767, UInt<1>(0h1), "") : assert_13 node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(is_aligned, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_774 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_775 = asUInt(reset) node _T_776 = eq(_T_775, UInt<1>(0h0)) when _T_776 : node _T_777 = eq(_T_774, UInt<1>(0h0)) when _T_777 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_774, UInt<1>(0h1), "") : assert_15 node _T_778 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_778, UInt<1>(0h1), "") : assert_16 node _T_782 = not(io.in.a.bits.mask) node _T_783 = eq(_T_782, UInt<1>(0h0)) node _T_784 = asUInt(reset) node _T_785 = eq(_T_784, UInt<1>(0h0)) when _T_785 : node _T_786 = eq(_T_783, UInt<1>(0h0)) when _T_786 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_783, UInt<1>(0h1), "") : assert_17 node _T_787 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_788 = asUInt(reset) node _T_789 = eq(_T_788, UInt<1>(0h0)) when _T_789 : node _T_790 = eq(_T_787, UInt<1>(0h0)) when _T_790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_787, UInt<1>(0h1), "") : assert_18 node _T_791 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_791 : node _T_792 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_793 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_794 = and(_T_792, _T_793) node _T_795 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_796 = shr(io.in.a.bits.source, 2) node _T_797 = eq(_T_796, UInt<7>(0h40)) node _T_798 = leq(UInt<1>(0h0), uncommonBits_60) node _T_799 = and(_T_797, _T_798) node _T_800 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_801 = and(_T_799, _T_800) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_802 = shr(io.in.a.bits.source, 2) node _T_803 = eq(_T_802, UInt<7>(0h41)) node _T_804 = leq(UInt<1>(0h0), uncommonBits_61) node _T_805 = and(_T_803, _T_804) node _T_806 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_807 = and(_T_805, _T_806) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_808 = shr(io.in.a.bits.source, 2) node _T_809 = eq(_T_808, UInt<7>(0h42)) node _T_810 = leq(UInt<1>(0h0), uncommonBits_62) node _T_811 = and(_T_809, _T_810) node _T_812 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_813 = and(_T_811, _T_812) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_814 = shr(io.in.a.bits.source, 2) node _T_815 = eq(_T_814, UInt<7>(0h43)) node _T_816 = leq(UInt<1>(0h0), uncommonBits_63) node _T_817 = and(_T_815, _T_816) node _T_818 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_819 = and(_T_817, _T_818) node _T_820 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_821 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_822 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_823 = shr(io.in.a.bits.source, 5) node _T_824 = eq(_T_823, UInt<1>(0h0)) node _T_825 = leq(UInt<1>(0h0), uncommonBits_64) node _T_826 = and(_T_824, _T_825) node _T_827 = leq(uncommonBits_64, UInt<5>(0h1f)) node _T_828 = and(_T_826, _T_827) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_829 = shr(io.in.a.bits.source, 5) node _T_830 = eq(_T_829, UInt<1>(0h1)) node _T_831 = leq(UInt<1>(0h0), uncommonBits_65) node _T_832 = and(_T_830, _T_831) node _T_833 = leq(uncommonBits_65, UInt<5>(0h1f)) node _T_834 = and(_T_832, _T_833) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0) node _T_835 = shr(io.in.a.bits.source, 5) node _T_836 = eq(_T_835, UInt<2>(0h2)) node _T_837 = leq(UInt<1>(0h0), uncommonBits_66) node _T_838 = and(_T_836, _T_837) node _T_839 = leq(uncommonBits_66, UInt<5>(0h1f)) node _T_840 = and(_T_838, _T_839) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0) node _T_841 = shr(io.in.a.bits.source, 5) node _T_842 = eq(_T_841, UInt<2>(0h3)) node _T_843 = leq(UInt<1>(0h0), uncommonBits_67) node _T_844 = and(_T_842, _T_843) node _T_845 = leq(uncommonBits_67, UInt<5>(0h1f)) node _T_846 = and(_T_844, _T_845) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0) node _T_847 = shr(io.in.a.bits.source, 5) node _T_848 = eq(_T_847, UInt<3>(0h4)) node _T_849 = leq(UInt<1>(0h0), uncommonBits_68) node _T_850 = and(_T_848, _T_849) node _T_851 = leq(uncommonBits_68, UInt<5>(0h1f)) node _T_852 = and(_T_850, _T_851) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0) node _T_853 = shr(io.in.a.bits.source, 5) node _T_854 = eq(_T_853, UInt<3>(0h5)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_69) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_69, UInt<5>(0h1f)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0) node _T_859 = shr(io.in.a.bits.source, 5) node _T_860 = eq(_T_859, UInt<3>(0h6)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_70) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_70, UInt<5>(0h1f)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0) node _T_865 = shr(io.in.a.bits.source, 5) node _T_866 = eq(_T_865, UInt<3>(0h7)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_71) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_71, UInt<5>(0h1f)) node _T_870 = and(_T_868, _T_869) node _T_871 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_872 = or(_T_795, _T_801) node _T_873 = or(_T_872, _T_807) node _T_874 = or(_T_873, _T_813) node _T_875 = or(_T_874, _T_819) node _T_876 = or(_T_875, _T_820) node _T_877 = or(_T_876, _T_821) node _T_878 = or(_T_877, _T_822) node _T_879 = or(_T_878, _T_828) node _T_880 = or(_T_879, _T_834) node _T_881 = or(_T_880, _T_840) node _T_882 = or(_T_881, _T_846) node _T_883 = or(_T_882, _T_852) node _T_884 = or(_T_883, _T_858) node _T_885 = or(_T_884, _T_864) node _T_886 = or(_T_885, _T_870) node _T_887 = or(_T_886, _T_871) node _T_888 = and(_T_794, _T_887) node _T_889 = or(UInt<1>(0h0), _T_888) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_889, UInt<1>(0h1), "") : assert_19 node _T_893 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_894 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_895 = and(_T_893, _T_894) node _T_896 = or(UInt<1>(0h0), _T_895) node _T_897 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_898 = cvt(_T_897) node _T_899 = and(_T_898, asSInt(UInt<13>(0h1000))) node _T_900 = asSInt(_T_899) node _T_901 = eq(_T_900, asSInt(UInt<1>(0h0))) node _T_902 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_903 = cvt(_T_902) node _T_904 = and(_T_903, asSInt(UInt<13>(0h1000))) node _T_905 = asSInt(_T_904) node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0))) node _T_907 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_908 = cvt(_T_907) node _T_909 = and(_T_908, asSInt(UInt<19>(0h40000))) node _T_910 = asSInt(_T_909) node _T_911 = eq(_T_910, asSInt(UInt<1>(0h0))) node _T_912 = or(_T_901, _T_906) node _T_913 = or(_T_912, _T_911) node _T_914 = and(_T_896, _T_913) node _T_915 = or(UInt<1>(0h0), _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_915, UInt<1>(0h1), "") : assert_20 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(source_ok, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_925 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_925, UInt<1>(0h1), "") : assert_23 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_929, UInt<1>(0h1), "") : assert_24 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_933, UInt<1>(0h1), "") : assert_25 node _T_937 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_937 : node _T_938 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_939 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_940 = and(_T_938, _T_939) node _T_941 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_942 = shr(io.in.a.bits.source, 2) node _T_943 = eq(_T_942, UInt<7>(0h40)) node _T_944 = leq(UInt<1>(0h0), uncommonBits_72) node _T_945 = and(_T_943, _T_944) node _T_946 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_947 = and(_T_945, _T_946) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_948 = shr(io.in.a.bits.source, 2) node _T_949 = eq(_T_948, UInt<7>(0h41)) node _T_950 = leq(UInt<1>(0h0), uncommonBits_73) node _T_951 = and(_T_949, _T_950) node _T_952 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_953 = and(_T_951, _T_952) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 1, 0) node _T_954 = shr(io.in.a.bits.source, 2) node _T_955 = eq(_T_954, UInt<7>(0h42)) node _T_956 = leq(UInt<1>(0h0), uncommonBits_74) node _T_957 = and(_T_955, _T_956) node _T_958 = leq(uncommonBits_74, UInt<2>(0h3)) node _T_959 = and(_T_957, _T_958) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0) node _T_960 = shr(io.in.a.bits.source, 2) node _T_961 = eq(_T_960, UInt<7>(0h43)) node _T_962 = leq(UInt<1>(0h0), uncommonBits_75) node _T_963 = and(_T_961, _T_962) node _T_964 = leq(uncommonBits_75, UInt<2>(0h3)) node _T_965 = and(_T_963, _T_964) node _T_966 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_967 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_968 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0) node _T_969 = shr(io.in.a.bits.source, 5) node _T_970 = eq(_T_969, UInt<1>(0h0)) node _T_971 = leq(UInt<1>(0h0), uncommonBits_76) node _T_972 = and(_T_970, _T_971) node _T_973 = leq(uncommonBits_76, UInt<5>(0h1f)) node _T_974 = and(_T_972, _T_973) node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0) node _T_975 = shr(io.in.a.bits.source, 5) node _T_976 = eq(_T_975, UInt<1>(0h1)) node _T_977 = leq(UInt<1>(0h0), uncommonBits_77) node _T_978 = and(_T_976, _T_977) node _T_979 = leq(uncommonBits_77, UInt<5>(0h1f)) node _T_980 = and(_T_978, _T_979) node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 4, 0) node _T_981 = shr(io.in.a.bits.source, 5) node _T_982 = eq(_T_981, UInt<2>(0h2)) node _T_983 = leq(UInt<1>(0h0), uncommonBits_78) node _T_984 = and(_T_982, _T_983) node _T_985 = leq(uncommonBits_78, UInt<5>(0h1f)) node _T_986 = and(_T_984, _T_985) node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 4, 0) node _T_987 = shr(io.in.a.bits.source, 5) node _T_988 = eq(_T_987, UInt<2>(0h3)) node _T_989 = leq(UInt<1>(0h0), uncommonBits_79) node _T_990 = and(_T_988, _T_989) node _T_991 = leq(uncommonBits_79, UInt<5>(0h1f)) node _T_992 = and(_T_990, _T_991) node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0) node _T_993 = shr(io.in.a.bits.source, 5) node _T_994 = eq(_T_993, UInt<3>(0h4)) node _T_995 = leq(UInt<1>(0h0), uncommonBits_80) node _T_996 = and(_T_994, _T_995) node _T_997 = leq(uncommonBits_80, UInt<5>(0h1f)) node _T_998 = and(_T_996, _T_997) node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0) node _T_999 = shr(io.in.a.bits.source, 5) node _T_1000 = eq(_T_999, UInt<3>(0h5)) node _T_1001 = leq(UInt<1>(0h0), uncommonBits_81) node _T_1002 = and(_T_1000, _T_1001) node _T_1003 = leq(uncommonBits_81, UInt<5>(0h1f)) node _T_1004 = and(_T_1002, _T_1003) node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0) node _T_1005 = shr(io.in.a.bits.source, 5) node _T_1006 = eq(_T_1005, UInt<3>(0h6)) node _T_1007 = leq(UInt<1>(0h0), uncommonBits_82) node _T_1008 = and(_T_1006, _T_1007) node _T_1009 = leq(uncommonBits_82, UInt<5>(0h1f)) node _T_1010 = and(_T_1008, _T_1009) node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0) node _T_1011 = shr(io.in.a.bits.source, 5) node _T_1012 = eq(_T_1011, UInt<3>(0h7)) node _T_1013 = leq(UInt<1>(0h0), uncommonBits_83) node _T_1014 = and(_T_1012, _T_1013) node _T_1015 = leq(uncommonBits_83, UInt<5>(0h1f)) node _T_1016 = and(_T_1014, _T_1015) node _T_1017 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1018 = or(_T_941, _T_947) node _T_1019 = or(_T_1018, _T_953) node _T_1020 = or(_T_1019, _T_959) node _T_1021 = or(_T_1020, _T_965) node _T_1022 = or(_T_1021, _T_966) node _T_1023 = or(_T_1022, _T_967) node _T_1024 = or(_T_1023, _T_968) node _T_1025 = or(_T_1024, _T_974) node _T_1026 = or(_T_1025, _T_980) node _T_1027 = or(_T_1026, _T_986) node _T_1028 = or(_T_1027, _T_992) node _T_1029 = or(_T_1028, _T_998) node _T_1030 = or(_T_1029, _T_1004) node _T_1031 = or(_T_1030, _T_1010) node _T_1032 = or(_T_1031, _T_1016) node _T_1033 = or(_T_1032, _T_1017) node _T_1034 = and(_T_940, _T_1033) node _T_1035 = or(UInt<1>(0h0), _T_1034) node _T_1036 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1037 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1038 = and(_T_1036, _T_1037) node _T_1039 = or(UInt<1>(0h0), _T_1038) node _T_1040 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1041 = cvt(_T_1040) node _T_1042 = and(_T_1041, asSInt(UInt<13>(0h1000))) node _T_1043 = asSInt(_T_1042) node _T_1044 = eq(_T_1043, asSInt(UInt<1>(0h0))) node _T_1045 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1046 = cvt(_T_1045) node _T_1047 = and(_T_1046, asSInt(UInt<13>(0h1000))) node _T_1048 = asSInt(_T_1047) node _T_1049 = eq(_T_1048, asSInt(UInt<1>(0h0))) node _T_1050 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1051 = cvt(_T_1050) node _T_1052 = and(_T_1051, asSInt(UInt<19>(0h40000))) node _T_1053 = asSInt(_T_1052) node _T_1054 = eq(_T_1053, asSInt(UInt<1>(0h0))) node _T_1055 = or(_T_1044, _T_1049) node _T_1056 = or(_T_1055, _T_1054) node _T_1057 = and(_T_1039, _T_1056) node _T_1058 = or(UInt<1>(0h0), _T_1057) node _T_1059 = and(_T_1035, _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_26 node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(source_ok, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(is_aligned, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1069 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_29 node _T_1073 = eq(io.in.a.bits.mask, mask) node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(_T_1073, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1073, UInt<1>(0h1), "") : assert_30 node _T_1077 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1077 : node _T_1078 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1079 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1080 = and(_T_1078, _T_1079) node _T_1081 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 1, 0) node _T_1082 = shr(io.in.a.bits.source, 2) node _T_1083 = eq(_T_1082, UInt<7>(0h40)) node _T_1084 = leq(UInt<1>(0h0), uncommonBits_84) node _T_1085 = and(_T_1083, _T_1084) node _T_1086 = leq(uncommonBits_84, UInt<2>(0h3)) node _T_1087 = and(_T_1085, _T_1086) node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0) node _T_1088 = shr(io.in.a.bits.source, 2) node _T_1089 = eq(_T_1088, UInt<7>(0h41)) node _T_1090 = leq(UInt<1>(0h0), uncommonBits_85) node _T_1091 = and(_T_1089, _T_1090) node _T_1092 = leq(uncommonBits_85, UInt<2>(0h3)) node _T_1093 = and(_T_1091, _T_1092) node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0) node _T_1094 = shr(io.in.a.bits.source, 2) node _T_1095 = eq(_T_1094, UInt<7>(0h42)) node _T_1096 = leq(UInt<1>(0h0), uncommonBits_86) node _T_1097 = and(_T_1095, _T_1096) node _T_1098 = leq(uncommonBits_86, UInt<2>(0h3)) node _T_1099 = and(_T_1097, _T_1098) node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0) node _T_1100 = shr(io.in.a.bits.source, 2) node _T_1101 = eq(_T_1100, UInt<7>(0h43)) node _T_1102 = leq(UInt<1>(0h0), uncommonBits_87) node _T_1103 = and(_T_1101, _T_1102) node _T_1104 = leq(uncommonBits_87, UInt<2>(0h3)) node _T_1105 = and(_T_1103, _T_1104) node _T_1106 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1107 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1108 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 4, 0) node _T_1109 = shr(io.in.a.bits.source, 5) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) node _T_1111 = leq(UInt<1>(0h0), uncommonBits_88) node _T_1112 = and(_T_1110, _T_1111) node _T_1113 = leq(uncommonBits_88, UInt<5>(0h1f)) node _T_1114 = and(_T_1112, _T_1113) node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 4, 0) node _T_1115 = shr(io.in.a.bits.source, 5) node _T_1116 = eq(_T_1115, UInt<1>(0h1)) node _T_1117 = leq(UInt<1>(0h0), uncommonBits_89) node _T_1118 = and(_T_1116, _T_1117) node _T_1119 = leq(uncommonBits_89, UInt<5>(0h1f)) node _T_1120 = and(_T_1118, _T_1119) node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_90 = bits(_uncommonBits_T_90, 4, 0) node _T_1121 = shr(io.in.a.bits.source, 5) node _T_1122 = eq(_T_1121, UInt<2>(0h2)) node _T_1123 = leq(UInt<1>(0h0), uncommonBits_90) node _T_1124 = and(_T_1122, _T_1123) node _T_1125 = leq(uncommonBits_90, UInt<5>(0h1f)) node _T_1126 = and(_T_1124, _T_1125) node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_91 = bits(_uncommonBits_T_91, 4, 0) node _T_1127 = shr(io.in.a.bits.source, 5) node _T_1128 = eq(_T_1127, UInt<2>(0h3)) node _T_1129 = leq(UInt<1>(0h0), uncommonBits_91) node _T_1130 = and(_T_1128, _T_1129) node _T_1131 = leq(uncommonBits_91, UInt<5>(0h1f)) node _T_1132 = and(_T_1130, _T_1131) node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_92 = bits(_uncommonBits_T_92, 4, 0) node _T_1133 = shr(io.in.a.bits.source, 5) node _T_1134 = eq(_T_1133, UInt<3>(0h4)) node _T_1135 = leq(UInt<1>(0h0), uncommonBits_92) node _T_1136 = and(_T_1134, _T_1135) node _T_1137 = leq(uncommonBits_92, UInt<5>(0h1f)) node _T_1138 = and(_T_1136, _T_1137) node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_93 = bits(_uncommonBits_T_93, 4, 0) node _T_1139 = shr(io.in.a.bits.source, 5) node _T_1140 = eq(_T_1139, UInt<3>(0h5)) node _T_1141 = leq(UInt<1>(0h0), uncommonBits_93) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = leq(uncommonBits_93, UInt<5>(0h1f)) node _T_1144 = and(_T_1142, _T_1143) node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0) node _T_1145 = shr(io.in.a.bits.source, 5) node _T_1146 = eq(_T_1145, UInt<3>(0h6)) node _T_1147 = leq(UInt<1>(0h0), uncommonBits_94) node _T_1148 = and(_T_1146, _T_1147) node _T_1149 = leq(uncommonBits_94, UInt<5>(0h1f)) node _T_1150 = and(_T_1148, _T_1149) node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0) node _T_1151 = shr(io.in.a.bits.source, 5) node _T_1152 = eq(_T_1151, UInt<3>(0h7)) node _T_1153 = leq(UInt<1>(0h0), uncommonBits_95) node _T_1154 = and(_T_1152, _T_1153) node _T_1155 = leq(uncommonBits_95, UInt<5>(0h1f)) node _T_1156 = and(_T_1154, _T_1155) node _T_1157 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1158 = or(_T_1081, _T_1087) node _T_1159 = or(_T_1158, _T_1093) node _T_1160 = or(_T_1159, _T_1099) node _T_1161 = or(_T_1160, _T_1105) node _T_1162 = or(_T_1161, _T_1106) node _T_1163 = or(_T_1162, _T_1107) node _T_1164 = or(_T_1163, _T_1108) node _T_1165 = or(_T_1164, _T_1114) node _T_1166 = or(_T_1165, _T_1120) node _T_1167 = or(_T_1166, _T_1126) node _T_1168 = or(_T_1167, _T_1132) node _T_1169 = or(_T_1168, _T_1138) node _T_1170 = or(_T_1169, _T_1144) node _T_1171 = or(_T_1170, _T_1150) node _T_1172 = or(_T_1171, _T_1156) node _T_1173 = or(_T_1172, _T_1157) node _T_1174 = and(_T_1080, _T_1173) node _T_1175 = or(UInt<1>(0h0), _T_1174) node _T_1176 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1177 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1178 = and(_T_1176, _T_1177) node _T_1179 = or(UInt<1>(0h0), _T_1178) node _T_1180 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1181 = cvt(_T_1180) node _T_1182 = and(_T_1181, asSInt(UInt<13>(0h1000))) node _T_1183 = asSInt(_T_1182) node _T_1184 = eq(_T_1183, asSInt(UInt<1>(0h0))) node _T_1185 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1186 = cvt(_T_1185) node _T_1187 = and(_T_1186, asSInt(UInt<13>(0h1000))) node _T_1188 = asSInt(_T_1187) node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0))) node _T_1190 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1191 = cvt(_T_1190) node _T_1192 = and(_T_1191, asSInt(UInt<19>(0h40000))) node _T_1193 = asSInt(_T_1192) node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = or(_T_1184, _T_1189) node _T_1196 = or(_T_1195, _T_1194) node _T_1197 = and(_T_1179, _T_1196) node _T_1198 = or(UInt<1>(0h0), _T_1197) node _T_1199 = and(_T_1175, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_31 node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(source_ok, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(is_aligned, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1209 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_34 node _T_1213 = not(mask) node _T_1214 = and(io.in.a.bits.mask, _T_1213) node _T_1215 = eq(_T_1214, UInt<1>(0h0)) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_35 node _T_1219 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1219 : node _T_1220 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1221 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1222 = and(_T_1220, _T_1221) node _T_1223 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_96 = bits(_uncommonBits_T_96, 1, 0) node _T_1224 = shr(io.in.a.bits.source, 2) node _T_1225 = eq(_T_1224, UInt<7>(0h40)) node _T_1226 = leq(UInt<1>(0h0), uncommonBits_96) node _T_1227 = and(_T_1225, _T_1226) node _T_1228 = leq(uncommonBits_96, UInt<2>(0h3)) node _T_1229 = and(_T_1227, _T_1228) node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_97 = bits(_uncommonBits_T_97, 1, 0) node _T_1230 = shr(io.in.a.bits.source, 2) node _T_1231 = eq(_T_1230, UInt<7>(0h41)) node _T_1232 = leq(UInt<1>(0h0), uncommonBits_97) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = leq(uncommonBits_97, UInt<2>(0h3)) node _T_1235 = and(_T_1233, _T_1234) node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_98 = bits(_uncommonBits_T_98, 1, 0) node _T_1236 = shr(io.in.a.bits.source, 2) node _T_1237 = eq(_T_1236, UInt<7>(0h42)) node _T_1238 = leq(UInt<1>(0h0), uncommonBits_98) node _T_1239 = and(_T_1237, _T_1238) node _T_1240 = leq(uncommonBits_98, UInt<2>(0h3)) node _T_1241 = and(_T_1239, _T_1240) node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_99 = bits(_uncommonBits_T_99, 1, 0) node _T_1242 = shr(io.in.a.bits.source, 2) node _T_1243 = eq(_T_1242, UInt<7>(0h43)) node _T_1244 = leq(UInt<1>(0h0), uncommonBits_99) node _T_1245 = and(_T_1243, _T_1244) node _T_1246 = leq(uncommonBits_99, UInt<2>(0h3)) node _T_1247 = and(_T_1245, _T_1246) node _T_1248 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1249 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1250 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_100 = bits(_uncommonBits_T_100, 4, 0) node _T_1251 = shr(io.in.a.bits.source, 5) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) node _T_1253 = leq(UInt<1>(0h0), uncommonBits_100) node _T_1254 = and(_T_1252, _T_1253) node _T_1255 = leq(uncommonBits_100, UInt<5>(0h1f)) node _T_1256 = and(_T_1254, _T_1255) node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_101 = bits(_uncommonBits_T_101, 4, 0) node _T_1257 = shr(io.in.a.bits.source, 5) node _T_1258 = eq(_T_1257, UInt<1>(0h1)) node _T_1259 = leq(UInt<1>(0h0), uncommonBits_101) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = leq(uncommonBits_101, UInt<5>(0h1f)) node _T_1262 = and(_T_1260, _T_1261) node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0) node _T_1263 = shr(io.in.a.bits.source, 5) node _T_1264 = eq(_T_1263, UInt<2>(0h2)) node _T_1265 = leq(UInt<1>(0h0), uncommonBits_102) node _T_1266 = and(_T_1264, _T_1265) node _T_1267 = leq(uncommonBits_102, UInt<5>(0h1f)) node _T_1268 = and(_T_1266, _T_1267) node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0) node _T_1269 = shr(io.in.a.bits.source, 5) node _T_1270 = eq(_T_1269, UInt<2>(0h3)) node _T_1271 = leq(UInt<1>(0h0), uncommonBits_103) node _T_1272 = and(_T_1270, _T_1271) node _T_1273 = leq(uncommonBits_103, UInt<5>(0h1f)) node _T_1274 = and(_T_1272, _T_1273) node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0) node _T_1275 = shr(io.in.a.bits.source, 5) node _T_1276 = eq(_T_1275, UInt<3>(0h4)) node _T_1277 = leq(UInt<1>(0h0), uncommonBits_104) node _T_1278 = and(_T_1276, _T_1277) node _T_1279 = leq(uncommonBits_104, UInt<5>(0h1f)) node _T_1280 = and(_T_1278, _T_1279) node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0) node _T_1281 = shr(io.in.a.bits.source, 5) node _T_1282 = eq(_T_1281, UInt<3>(0h5)) node _T_1283 = leq(UInt<1>(0h0), uncommonBits_105) node _T_1284 = and(_T_1282, _T_1283) node _T_1285 = leq(uncommonBits_105, UInt<5>(0h1f)) node _T_1286 = and(_T_1284, _T_1285) node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0) node _T_1287 = shr(io.in.a.bits.source, 5) node _T_1288 = eq(_T_1287, UInt<3>(0h6)) node _T_1289 = leq(UInt<1>(0h0), uncommonBits_106) node _T_1290 = and(_T_1288, _T_1289) node _T_1291 = leq(uncommonBits_106, UInt<5>(0h1f)) node _T_1292 = and(_T_1290, _T_1291) node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0) node _T_1293 = shr(io.in.a.bits.source, 5) node _T_1294 = eq(_T_1293, UInt<3>(0h7)) node _T_1295 = leq(UInt<1>(0h0), uncommonBits_107) node _T_1296 = and(_T_1294, _T_1295) node _T_1297 = leq(uncommonBits_107, UInt<5>(0h1f)) node _T_1298 = and(_T_1296, _T_1297) node _T_1299 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1300 = or(_T_1223, _T_1229) node _T_1301 = or(_T_1300, _T_1235) node _T_1302 = or(_T_1301, _T_1241) node _T_1303 = or(_T_1302, _T_1247) node _T_1304 = or(_T_1303, _T_1248) node _T_1305 = or(_T_1304, _T_1249) node _T_1306 = or(_T_1305, _T_1250) node _T_1307 = or(_T_1306, _T_1256) node _T_1308 = or(_T_1307, _T_1262) node _T_1309 = or(_T_1308, _T_1268) node _T_1310 = or(_T_1309, _T_1274) node _T_1311 = or(_T_1310, _T_1280) node _T_1312 = or(_T_1311, _T_1286) node _T_1313 = or(_T_1312, _T_1292) node _T_1314 = or(_T_1313, _T_1298) node _T_1315 = or(_T_1314, _T_1299) node _T_1316 = and(_T_1222, _T_1315) node _T_1317 = or(UInt<1>(0h0), _T_1316) node _T_1318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1319 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1320 = cvt(_T_1319) node _T_1321 = and(_T_1320, asSInt(UInt<13>(0h1000))) node _T_1322 = asSInt(_T_1321) node _T_1323 = eq(_T_1322, asSInt(UInt<1>(0h0))) node _T_1324 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1325 = cvt(_T_1324) node _T_1326 = and(_T_1325, asSInt(UInt<13>(0h1000))) node _T_1327 = asSInt(_T_1326) node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0))) node _T_1329 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1330 = cvt(_T_1329) node _T_1331 = and(_T_1330, asSInt(UInt<19>(0h40000))) node _T_1332 = asSInt(_T_1331) node _T_1333 = eq(_T_1332, asSInt(UInt<1>(0h0))) node _T_1334 = or(_T_1323, _T_1328) node _T_1335 = or(_T_1334, _T_1333) node _T_1336 = and(_T_1318, _T_1335) node _T_1337 = or(UInt<1>(0h0), _T_1336) node _T_1338 = and(_T_1317, _T_1337) node _T_1339 = asUInt(reset) node _T_1340 = eq(_T_1339, UInt<1>(0h0)) when _T_1340 : node _T_1341 = eq(_T_1338, UInt<1>(0h0)) when _T_1341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1338, UInt<1>(0h1), "") : assert_36 node _T_1342 = asUInt(reset) node _T_1343 = eq(_T_1342, UInt<1>(0h0)) when _T_1343 : node _T_1344 = eq(source_ok, UInt<1>(0h0)) when _T_1344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1345 = asUInt(reset) node _T_1346 = eq(_T_1345, UInt<1>(0h0)) when _T_1346 : node _T_1347 = eq(is_aligned, UInt<1>(0h0)) when _T_1347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1348 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1349 = asUInt(reset) node _T_1350 = eq(_T_1349, UInt<1>(0h0)) when _T_1350 : node _T_1351 = eq(_T_1348, UInt<1>(0h0)) when _T_1351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1348, UInt<1>(0h1), "") : assert_39 node _T_1352 = eq(io.in.a.bits.mask, mask) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_40 node _T_1356 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1356 : node _T_1357 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1358 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1359 = and(_T_1357, _T_1358) node _T_1360 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_108 = bits(_uncommonBits_T_108, 1, 0) node _T_1361 = shr(io.in.a.bits.source, 2) node _T_1362 = eq(_T_1361, UInt<7>(0h40)) node _T_1363 = leq(UInt<1>(0h0), uncommonBits_108) node _T_1364 = and(_T_1362, _T_1363) node _T_1365 = leq(uncommonBits_108, UInt<2>(0h3)) node _T_1366 = and(_T_1364, _T_1365) node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_109 = bits(_uncommonBits_T_109, 1, 0) node _T_1367 = shr(io.in.a.bits.source, 2) node _T_1368 = eq(_T_1367, UInt<7>(0h41)) node _T_1369 = leq(UInt<1>(0h0), uncommonBits_109) node _T_1370 = and(_T_1368, _T_1369) node _T_1371 = leq(uncommonBits_109, UInt<2>(0h3)) node _T_1372 = and(_T_1370, _T_1371) node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0) node _T_1373 = shr(io.in.a.bits.source, 2) node _T_1374 = eq(_T_1373, UInt<7>(0h42)) node _T_1375 = leq(UInt<1>(0h0), uncommonBits_110) node _T_1376 = and(_T_1374, _T_1375) node _T_1377 = leq(uncommonBits_110, UInt<2>(0h3)) node _T_1378 = and(_T_1376, _T_1377) node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0) node _T_1379 = shr(io.in.a.bits.source, 2) node _T_1380 = eq(_T_1379, UInt<7>(0h43)) node _T_1381 = leq(UInt<1>(0h0), uncommonBits_111) node _T_1382 = and(_T_1380, _T_1381) node _T_1383 = leq(uncommonBits_111, UInt<2>(0h3)) node _T_1384 = and(_T_1382, _T_1383) node _T_1385 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1386 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1387 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_112 = bits(_uncommonBits_T_112, 4, 0) node _T_1388 = shr(io.in.a.bits.source, 5) node _T_1389 = eq(_T_1388, UInt<1>(0h0)) node _T_1390 = leq(UInt<1>(0h0), uncommonBits_112) node _T_1391 = and(_T_1389, _T_1390) node _T_1392 = leq(uncommonBits_112, UInt<5>(0h1f)) node _T_1393 = and(_T_1391, _T_1392) node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_113 = bits(_uncommonBits_T_113, 4, 0) node _T_1394 = shr(io.in.a.bits.source, 5) node _T_1395 = eq(_T_1394, UInt<1>(0h1)) node _T_1396 = leq(UInt<1>(0h0), uncommonBits_113) node _T_1397 = and(_T_1395, _T_1396) node _T_1398 = leq(uncommonBits_113, UInt<5>(0h1f)) node _T_1399 = and(_T_1397, _T_1398) node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_114 = bits(_uncommonBits_T_114, 4, 0) node _T_1400 = shr(io.in.a.bits.source, 5) node _T_1401 = eq(_T_1400, UInt<2>(0h2)) node _T_1402 = leq(UInt<1>(0h0), uncommonBits_114) node _T_1403 = and(_T_1401, _T_1402) node _T_1404 = leq(uncommonBits_114, UInt<5>(0h1f)) node _T_1405 = and(_T_1403, _T_1404) node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_115 = bits(_uncommonBits_T_115, 4, 0) node _T_1406 = shr(io.in.a.bits.source, 5) node _T_1407 = eq(_T_1406, UInt<2>(0h3)) node _T_1408 = leq(UInt<1>(0h0), uncommonBits_115) node _T_1409 = and(_T_1407, _T_1408) node _T_1410 = leq(uncommonBits_115, UInt<5>(0h1f)) node _T_1411 = and(_T_1409, _T_1410) node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0) node _T_1412 = shr(io.in.a.bits.source, 5) node _T_1413 = eq(_T_1412, UInt<3>(0h4)) node _T_1414 = leq(UInt<1>(0h0), uncommonBits_116) node _T_1415 = and(_T_1413, _T_1414) node _T_1416 = leq(uncommonBits_116, UInt<5>(0h1f)) node _T_1417 = and(_T_1415, _T_1416) node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0) node _T_1418 = shr(io.in.a.bits.source, 5) node _T_1419 = eq(_T_1418, UInt<3>(0h5)) node _T_1420 = leq(UInt<1>(0h0), uncommonBits_117) node _T_1421 = and(_T_1419, _T_1420) node _T_1422 = leq(uncommonBits_117, UInt<5>(0h1f)) node _T_1423 = and(_T_1421, _T_1422) node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0) node _T_1424 = shr(io.in.a.bits.source, 5) node _T_1425 = eq(_T_1424, UInt<3>(0h6)) node _T_1426 = leq(UInt<1>(0h0), uncommonBits_118) node _T_1427 = and(_T_1425, _T_1426) node _T_1428 = leq(uncommonBits_118, UInt<5>(0h1f)) node _T_1429 = and(_T_1427, _T_1428) node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0) node _T_1430 = shr(io.in.a.bits.source, 5) node _T_1431 = eq(_T_1430, UInt<3>(0h7)) node _T_1432 = leq(UInt<1>(0h0), uncommonBits_119) node _T_1433 = and(_T_1431, _T_1432) node _T_1434 = leq(uncommonBits_119, UInt<5>(0h1f)) node _T_1435 = and(_T_1433, _T_1434) node _T_1436 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1437 = or(_T_1360, _T_1366) node _T_1438 = or(_T_1437, _T_1372) node _T_1439 = or(_T_1438, _T_1378) node _T_1440 = or(_T_1439, _T_1384) node _T_1441 = or(_T_1440, _T_1385) node _T_1442 = or(_T_1441, _T_1386) node _T_1443 = or(_T_1442, _T_1387) node _T_1444 = or(_T_1443, _T_1393) node _T_1445 = or(_T_1444, _T_1399) node _T_1446 = or(_T_1445, _T_1405) node _T_1447 = or(_T_1446, _T_1411) node _T_1448 = or(_T_1447, _T_1417) node _T_1449 = or(_T_1448, _T_1423) node _T_1450 = or(_T_1449, _T_1429) node _T_1451 = or(_T_1450, _T_1435) node _T_1452 = or(_T_1451, _T_1436) node _T_1453 = and(_T_1359, _T_1452) node _T_1454 = or(UInt<1>(0h0), _T_1453) node _T_1455 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1456 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1457 = cvt(_T_1456) node _T_1458 = and(_T_1457, asSInt(UInt<13>(0h1000))) node _T_1459 = asSInt(_T_1458) node _T_1460 = eq(_T_1459, asSInt(UInt<1>(0h0))) node _T_1461 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1462 = cvt(_T_1461) node _T_1463 = and(_T_1462, asSInt(UInt<13>(0h1000))) node _T_1464 = asSInt(_T_1463) node _T_1465 = eq(_T_1464, asSInt(UInt<1>(0h0))) node _T_1466 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1467 = cvt(_T_1466) node _T_1468 = and(_T_1467, asSInt(UInt<19>(0h40000))) node _T_1469 = asSInt(_T_1468) node _T_1470 = eq(_T_1469, asSInt(UInt<1>(0h0))) node _T_1471 = or(_T_1460, _T_1465) node _T_1472 = or(_T_1471, _T_1470) node _T_1473 = and(_T_1455, _T_1472) node _T_1474 = or(UInt<1>(0h0), _T_1473) node _T_1475 = and(_T_1454, _T_1474) node _T_1476 = asUInt(reset) node _T_1477 = eq(_T_1476, UInt<1>(0h0)) when _T_1477 : node _T_1478 = eq(_T_1475, UInt<1>(0h0)) when _T_1478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1475, UInt<1>(0h1), "") : assert_41 node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(source_ok, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(is_aligned, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1485 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1486 = asUInt(reset) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) when _T_1487 : node _T_1488 = eq(_T_1485, UInt<1>(0h0)) when _T_1488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1485, UInt<1>(0h1), "") : assert_44 node _T_1489 = eq(io.in.a.bits.mask, mask) node _T_1490 = asUInt(reset) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) when _T_1491 : node _T_1492 = eq(_T_1489, UInt<1>(0h0)) when _T_1492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1489, UInt<1>(0h1), "") : assert_45 node _T_1493 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1493 : node _T_1494 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1495 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1496 = and(_T_1494, _T_1495) node _T_1497 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_120 = bits(_uncommonBits_T_120, 1, 0) node _T_1498 = shr(io.in.a.bits.source, 2) node _T_1499 = eq(_T_1498, UInt<7>(0h40)) node _T_1500 = leq(UInt<1>(0h0), uncommonBits_120) node _T_1501 = and(_T_1499, _T_1500) node _T_1502 = leq(uncommonBits_120, UInt<2>(0h3)) node _T_1503 = and(_T_1501, _T_1502) node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_121 = bits(_uncommonBits_T_121, 1, 0) node _T_1504 = shr(io.in.a.bits.source, 2) node _T_1505 = eq(_T_1504, UInt<7>(0h41)) node _T_1506 = leq(UInt<1>(0h0), uncommonBits_121) node _T_1507 = and(_T_1505, _T_1506) node _T_1508 = leq(uncommonBits_121, UInt<2>(0h3)) node _T_1509 = and(_T_1507, _T_1508) node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0) node _T_1510 = shr(io.in.a.bits.source, 2) node _T_1511 = eq(_T_1510, UInt<7>(0h42)) node _T_1512 = leq(UInt<1>(0h0), uncommonBits_122) node _T_1513 = and(_T_1511, _T_1512) node _T_1514 = leq(uncommonBits_122, UInt<2>(0h3)) node _T_1515 = and(_T_1513, _T_1514) node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0) node _T_1516 = shr(io.in.a.bits.source, 2) node _T_1517 = eq(_T_1516, UInt<7>(0h43)) node _T_1518 = leq(UInt<1>(0h0), uncommonBits_123) node _T_1519 = and(_T_1517, _T_1518) node _T_1520 = leq(uncommonBits_123, UInt<2>(0h3)) node _T_1521 = and(_T_1519, _T_1520) node _T_1522 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1523 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1524 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0) node _T_1525 = shr(io.in.a.bits.source, 5) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) node _T_1527 = leq(UInt<1>(0h0), uncommonBits_124) node _T_1528 = and(_T_1526, _T_1527) node _T_1529 = leq(uncommonBits_124, UInt<5>(0h1f)) node _T_1530 = and(_T_1528, _T_1529) node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0) node _T_1531 = shr(io.in.a.bits.source, 5) node _T_1532 = eq(_T_1531, UInt<1>(0h1)) node _T_1533 = leq(UInt<1>(0h0), uncommonBits_125) node _T_1534 = and(_T_1532, _T_1533) node _T_1535 = leq(uncommonBits_125, UInt<5>(0h1f)) node _T_1536 = and(_T_1534, _T_1535) node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0) node _T_1537 = shr(io.in.a.bits.source, 5) node _T_1538 = eq(_T_1537, UInt<2>(0h2)) node _T_1539 = leq(UInt<1>(0h0), uncommonBits_126) node _T_1540 = and(_T_1538, _T_1539) node _T_1541 = leq(uncommonBits_126, UInt<5>(0h1f)) node _T_1542 = and(_T_1540, _T_1541) node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0) node _T_1543 = shr(io.in.a.bits.source, 5) node _T_1544 = eq(_T_1543, UInt<2>(0h3)) node _T_1545 = leq(UInt<1>(0h0), uncommonBits_127) node _T_1546 = and(_T_1544, _T_1545) node _T_1547 = leq(uncommonBits_127, UInt<5>(0h1f)) node _T_1548 = and(_T_1546, _T_1547) node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0) node _T_1549 = shr(io.in.a.bits.source, 5) node _T_1550 = eq(_T_1549, UInt<3>(0h4)) node _T_1551 = leq(UInt<1>(0h0), uncommonBits_128) node _T_1552 = and(_T_1550, _T_1551) node _T_1553 = leq(uncommonBits_128, UInt<5>(0h1f)) node _T_1554 = and(_T_1552, _T_1553) node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0) node _T_1555 = shr(io.in.a.bits.source, 5) node _T_1556 = eq(_T_1555, UInt<3>(0h5)) node _T_1557 = leq(UInt<1>(0h0), uncommonBits_129) node _T_1558 = and(_T_1556, _T_1557) node _T_1559 = leq(uncommonBits_129, UInt<5>(0h1f)) node _T_1560 = and(_T_1558, _T_1559) node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0) node _T_1561 = shr(io.in.a.bits.source, 5) node _T_1562 = eq(_T_1561, UInt<3>(0h6)) node _T_1563 = leq(UInt<1>(0h0), uncommonBits_130) node _T_1564 = and(_T_1562, _T_1563) node _T_1565 = leq(uncommonBits_130, UInt<5>(0h1f)) node _T_1566 = and(_T_1564, _T_1565) node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0) node _T_1567 = shr(io.in.a.bits.source, 5) node _T_1568 = eq(_T_1567, UInt<3>(0h7)) node _T_1569 = leq(UInt<1>(0h0), uncommonBits_131) node _T_1570 = and(_T_1568, _T_1569) node _T_1571 = leq(uncommonBits_131, UInt<5>(0h1f)) node _T_1572 = and(_T_1570, _T_1571) node _T_1573 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1574 = or(_T_1497, _T_1503) node _T_1575 = or(_T_1574, _T_1509) node _T_1576 = or(_T_1575, _T_1515) node _T_1577 = or(_T_1576, _T_1521) node _T_1578 = or(_T_1577, _T_1522) node _T_1579 = or(_T_1578, _T_1523) node _T_1580 = or(_T_1579, _T_1524) node _T_1581 = or(_T_1580, _T_1530) node _T_1582 = or(_T_1581, _T_1536) node _T_1583 = or(_T_1582, _T_1542) node _T_1584 = or(_T_1583, _T_1548) node _T_1585 = or(_T_1584, _T_1554) node _T_1586 = or(_T_1585, _T_1560) node _T_1587 = or(_T_1586, _T_1566) node _T_1588 = or(_T_1587, _T_1572) node _T_1589 = or(_T_1588, _T_1573) node _T_1590 = and(_T_1496, _T_1589) node _T_1591 = or(UInt<1>(0h0), _T_1590) node _T_1592 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1593 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1594 = cvt(_T_1593) node _T_1595 = and(_T_1594, asSInt(UInt<13>(0h1000))) node _T_1596 = asSInt(_T_1595) node _T_1597 = eq(_T_1596, asSInt(UInt<1>(0h0))) node _T_1598 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1599 = cvt(_T_1598) node _T_1600 = and(_T_1599, asSInt(UInt<13>(0h1000))) node _T_1601 = asSInt(_T_1600) node _T_1602 = eq(_T_1601, asSInt(UInt<1>(0h0))) node _T_1603 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_1604 = cvt(_T_1603) node _T_1605 = and(_T_1604, asSInt(UInt<19>(0h40000))) node _T_1606 = asSInt(_T_1605) node _T_1607 = eq(_T_1606, asSInt(UInt<1>(0h0))) node _T_1608 = or(_T_1597, _T_1602) node _T_1609 = or(_T_1608, _T_1607) node _T_1610 = and(_T_1592, _T_1609) node _T_1611 = or(UInt<1>(0h0), _T_1610) node _T_1612 = and(_T_1591, _T_1611) node _T_1613 = asUInt(reset) node _T_1614 = eq(_T_1613, UInt<1>(0h0)) when _T_1614 : node _T_1615 = eq(_T_1612, UInt<1>(0h0)) when _T_1615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1612, UInt<1>(0h1), "") : assert_46 node _T_1616 = asUInt(reset) node _T_1617 = eq(_T_1616, UInt<1>(0h0)) when _T_1617 : node _T_1618 = eq(source_ok, UInt<1>(0h0)) when _T_1618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1619 = asUInt(reset) node _T_1620 = eq(_T_1619, UInt<1>(0h0)) when _T_1620 : node _T_1621 = eq(is_aligned, UInt<1>(0h0)) when _T_1621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1622 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1623 = asUInt(reset) node _T_1624 = eq(_T_1623, UInt<1>(0h0)) when _T_1624 : node _T_1625 = eq(_T_1622, UInt<1>(0h0)) when _T_1625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1622, UInt<1>(0h1), "") : assert_49 node _T_1626 = eq(io.in.a.bits.mask, mask) node _T_1627 = asUInt(reset) node _T_1628 = eq(_T_1627, UInt<1>(0h0)) when _T_1628 : node _T_1629 = eq(_T_1626, UInt<1>(0h0)) when _T_1629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1626, UInt<1>(0h1), "") : assert_50 node _T_1630 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1631 = asUInt(reset) node _T_1632 = eq(_T_1631, UInt<1>(0h0)) when _T_1632 : node _T_1633 = eq(_T_1630, UInt<1>(0h0)) when _T_1633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1630, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1634 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1635 = asUInt(reset) node _T_1636 = eq(_T_1635, UInt<1>(0h0)) when _T_1636 : node _T_1637 = eq(_T_1634, UInt<1>(0h0)) when _T_1637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1634, UInt<1>(0h1), "") : assert_52 node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<9>(0h110)) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_93 = shr(io.in.d.bits.source, 2) node _source_ok_T_94 = eq(_source_ok_T_93, UInt<7>(0h40)) node _source_ok_T_95 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_T_97 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_99 = shr(io.in.d.bits.source, 2) node _source_ok_T_100 = eq(_source_ok_T_99, UInt<7>(0h41)) node _source_ok_T_101 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_T_103 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103) node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 1, 0) node _source_ok_T_105 = shr(io.in.d.bits.source, 2) node _source_ok_T_106 = eq(_source_ok_T_105, UInt<7>(0h42)) node _source_ok_T_107 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_T_109 = leq(source_ok_uncommonBits_14, UInt<2>(0h3)) node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109) node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 1, 0) node _source_ok_T_111 = shr(io.in.d.bits.source, 2) node _source_ok_T_112 = eq(_source_ok_T_111, UInt<7>(0h43)) node _source_ok_T_113 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_T_115 = leq(source_ok_uncommonBits_15, UInt<2>(0h3)) node _source_ok_T_116 = and(_source_ok_T_114, _source_ok_T_115) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<9>(0h120)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<9>(0h121)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<9>(0h122)) node _source_ok_uncommonBits_T_16 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0) node _source_ok_T_120 = shr(io.in.d.bits.source, 5) node _source_ok_T_121 = eq(_source_ok_T_120, UInt<1>(0h0)) node _source_ok_T_122 = leq(UInt<1>(0h0), source_ok_uncommonBits_16) node _source_ok_T_123 = and(_source_ok_T_121, _source_ok_T_122) node _source_ok_T_124 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f)) node _source_ok_T_125 = and(_source_ok_T_123, _source_ok_T_124) node _source_ok_uncommonBits_T_17 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0) node _source_ok_T_126 = shr(io.in.d.bits.source, 5) node _source_ok_T_127 = eq(_source_ok_T_126, UInt<1>(0h1)) node _source_ok_T_128 = leq(UInt<1>(0h0), source_ok_uncommonBits_17) node _source_ok_T_129 = and(_source_ok_T_127, _source_ok_T_128) node _source_ok_T_130 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f)) node _source_ok_T_131 = and(_source_ok_T_129, _source_ok_T_130) node _source_ok_uncommonBits_T_18 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0) node _source_ok_T_132 = shr(io.in.d.bits.source, 5) node _source_ok_T_133 = eq(_source_ok_T_132, UInt<2>(0h2)) node _source_ok_T_134 = leq(UInt<1>(0h0), source_ok_uncommonBits_18) node _source_ok_T_135 = and(_source_ok_T_133, _source_ok_T_134) node _source_ok_T_136 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f)) node _source_ok_T_137 = and(_source_ok_T_135, _source_ok_T_136) node _source_ok_uncommonBits_T_19 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0) node _source_ok_T_138 = shr(io.in.d.bits.source, 5) node _source_ok_T_139 = eq(_source_ok_T_138, UInt<2>(0h3)) node _source_ok_T_140 = leq(UInt<1>(0h0), source_ok_uncommonBits_19) node _source_ok_T_141 = and(_source_ok_T_139, _source_ok_T_140) node _source_ok_T_142 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f)) node _source_ok_T_143 = and(_source_ok_T_141, _source_ok_T_142) node _source_ok_uncommonBits_T_20 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0) node _source_ok_T_144 = shr(io.in.d.bits.source, 5) node _source_ok_T_145 = eq(_source_ok_T_144, UInt<3>(0h4)) node _source_ok_T_146 = leq(UInt<1>(0h0), source_ok_uncommonBits_20) node _source_ok_T_147 = and(_source_ok_T_145, _source_ok_T_146) node _source_ok_T_148 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f)) node _source_ok_T_149 = and(_source_ok_T_147, _source_ok_T_148) node _source_ok_uncommonBits_T_21 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0) node _source_ok_T_150 = shr(io.in.d.bits.source, 5) node _source_ok_T_151 = eq(_source_ok_T_150, UInt<3>(0h5)) node _source_ok_T_152 = leq(UInt<1>(0h0), source_ok_uncommonBits_21) node _source_ok_T_153 = and(_source_ok_T_151, _source_ok_T_152) node _source_ok_T_154 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f)) node _source_ok_T_155 = and(_source_ok_T_153, _source_ok_T_154) node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 4, 0) node _source_ok_T_156 = shr(io.in.d.bits.source, 5) node _source_ok_T_157 = eq(_source_ok_T_156, UInt<3>(0h6)) node _source_ok_T_158 = leq(UInt<1>(0h0), source_ok_uncommonBits_22) node _source_ok_T_159 = and(_source_ok_T_157, _source_ok_T_158) node _source_ok_T_160 = leq(source_ok_uncommonBits_22, UInt<5>(0h1f)) node _source_ok_T_161 = and(_source_ok_T_159, _source_ok_T_160) node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 4, 0) node _source_ok_T_162 = shr(io.in.d.bits.source, 5) node _source_ok_T_163 = eq(_source_ok_T_162, UInt<3>(0h7)) node _source_ok_T_164 = leq(UInt<1>(0h0), source_ok_uncommonBits_23) node _source_ok_T_165 = and(_source_ok_T_163, _source_ok_T_164) node _source_ok_T_166 = leq(source_ok_uncommonBits_23, UInt<5>(0h1f)) node _source_ok_T_167 = and(_source_ok_T_165, _source_ok_T_166) node _source_ok_T_168 = eq(io.in.d.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE_1 : UInt<1>[17] connect _source_ok_WIRE_1[0], _source_ok_T_92 connect _source_ok_WIRE_1[1], _source_ok_T_98 connect _source_ok_WIRE_1[2], _source_ok_T_104 connect _source_ok_WIRE_1[3], _source_ok_T_110 connect _source_ok_WIRE_1[4], _source_ok_T_116 connect _source_ok_WIRE_1[5], _source_ok_T_117 connect _source_ok_WIRE_1[6], _source_ok_T_118 connect _source_ok_WIRE_1[7], _source_ok_T_119 connect _source_ok_WIRE_1[8], _source_ok_T_125 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_137 connect _source_ok_WIRE_1[11], _source_ok_T_143 connect _source_ok_WIRE_1[12], _source_ok_T_149 connect _source_ok_WIRE_1[13], _source_ok_T_155 connect _source_ok_WIRE_1[14], _source_ok_T_161 connect _source_ok_WIRE_1[15], _source_ok_T_167 connect _source_ok_WIRE_1[16], _source_ok_T_168 node _source_ok_T_169 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[2]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[3]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[4]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[5]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[6]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[7]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[8]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[9]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[10]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[11]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[12]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[13]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[14]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[15]) node source_ok_1 = or(_source_ok_T_183, _source_ok_WIRE_1[16]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1638 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1638 : node _T_1639 = asUInt(reset) node _T_1640 = eq(_T_1639, UInt<1>(0h0)) when _T_1640 : node _T_1641 = eq(source_ok_1, UInt<1>(0h0)) when _T_1641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1642 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1643 = asUInt(reset) node _T_1644 = eq(_T_1643, UInt<1>(0h0)) when _T_1644 : node _T_1645 = eq(_T_1642, UInt<1>(0h0)) when _T_1645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1642, UInt<1>(0h1), "") : assert_54 node _T_1646 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1647 = asUInt(reset) node _T_1648 = eq(_T_1647, UInt<1>(0h0)) when _T_1648 : node _T_1649 = eq(_T_1646, UInt<1>(0h0)) when _T_1649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1646, UInt<1>(0h1), "") : assert_55 node _T_1650 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1651 = asUInt(reset) node _T_1652 = eq(_T_1651, UInt<1>(0h0)) when _T_1652 : node _T_1653 = eq(_T_1650, UInt<1>(0h0)) when _T_1653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1650, UInt<1>(0h1), "") : assert_56 node _T_1654 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1655 = asUInt(reset) node _T_1656 = eq(_T_1655, UInt<1>(0h0)) when _T_1656 : node _T_1657 = eq(_T_1654, UInt<1>(0h0)) when _T_1657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1654, UInt<1>(0h1), "") : assert_57 node _T_1658 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1658 : node _T_1659 = asUInt(reset) node _T_1660 = eq(_T_1659, UInt<1>(0h0)) when _T_1660 : node _T_1661 = eq(source_ok_1, UInt<1>(0h0)) when _T_1661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1662 = asUInt(reset) node _T_1663 = eq(_T_1662, UInt<1>(0h0)) when _T_1663 : node _T_1664 = eq(sink_ok, UInt<1>(0h0)) when _T_1664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1665 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1666 = asUInt(reset) node _T_1667 = eq(_T_1666, UInt<1>(0h0)) when _T_1667 : node _T_1668 = eq(_T_1665, UInt<1>(0h0)) when _T_1668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1665, UInt<1>(0h1), "") : assert_60 node _T_1669 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1670 = asUInt(reset) node _T_1671 = eq(_T_1670, UInt<1>(0h0)) when _T_1671 : node _T_1672 = eq(_T_1669, UInt<1>(0h0)) when _T_1672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1669, UInt<1>(0h1), "") : assert_61 node _T_1673 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1674 = asUInt(reset) node _T_1675 = eq(_T_1674, UInt<1>(0h0)) when _T_1675 : node _T_1676 = eq(_T_1673, UInt<1>(0h0)) when _T_1676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1673, UInt<1>(0h1), "") : assert_62 node _T_1677 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1678 = asUInt(reset) node _T_1679 = eq(_T_1678, UInt<1>(0h0)) when _T_1679 : node _T_1680 = eq(_T_1677, UInt<1>(0h0)) when _T_1680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1677, UInt<1>(0h1), "") : assert_63 node _T_1681 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1682 = or(UInt<1>(0h1), _T_1681) node _T_1683 = asUInt(reset) node _T_1684 = eq(_T_1683, UInt<1>(0h0)) when _T_1684 : node _T_1685 = eq(_T_1682, UInt<1>(0h0)) when _T_1685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1682, UInt<1>(0h1), "") : assert_64 node _T_1686 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1686 : node _T_1687 = asUInt(reset) node _T_1688 = eq(_T_1687, UInt<1>(0h0)) when _T_1688 : node _T_1689 = eq(source_ok_1, UInt<1>(0h0)) when _T_1689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1690 = asUInt(reset) node _T_1691 = eq(_T_1690, UInt<1>(0h0)) when _T_1691 : node _T_1692 = eq(sink_ok, UInt<1>(0h0)) when _T_1692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1693 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1694 = asUInt(reset) node _T_1695 = eq(_T_1694, UInt<1>(0h0)) when _T_1695 : node _T_1696 = eq(_T_1693, UInt<1>(0h0)) when _T_1696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1693, UInt<1>(0h1), "") : assert_67 node _T_1697 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1698 = asUInt(reset) node _T_1699 = eq(_T_1698, UInt<1>(0h0)) when _T_1699 : node _T_1700 = eq(_T_1697, UInt<1>(0h0)) when _T_1700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1697, UInt<1>(0h1), "") : assert_68 node _T_1701 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1702 = asUInt(reset) node _T_1703 = eq(_T_1702, UInt<1>(0h0)) when _T_1703 : node _T_1704 = eq(_T_1701, UInt<1>(0h0)) when _T_1704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1701, UInt<1>(0h1), "") : assert_69 node _T_1705 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1706 = or(_T_1705, io.in.d.bits.corrupt) node _T_1707 = asUInt(reset) node _T_1708 = eq(_T_1707, UInt<1>(0h0)) when _T_1708 : node _T_1709 = eq(_T_1706, UInt<1>(0h0)) when _T_1709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1706, UInt<1>(0h1), "") : assert_70 node _T_1710 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1711 = or(UInt<1>(0h0), _T_1710) node _T_1712 = asUInt(reset) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) when _T_1713 : node _T_1714 = eq(_T_1711, UInt<1>(0h0)) when _T_1714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1711, UInt<1>(0h1), "") : assert_71 node _T_1715 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1715 : node _T_1716 = asUInt(reset) node _T_1717 = eq(_T_1716, UInt<1>(0h0)) when _T_1717 : node _T_1718 = eq(source_ok_1, UInt<1>(0h0)) when _T_1718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1719 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1720 = asUInt(reset) node _T_1721 = eq(_T_1720, UInt<1>(0h0)) when _T_1721 : node _T_1722 = eq(_T_1719, UInt<1>(0h0)) when _T_1722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1719, UInt<1>(0h1), "") : assert_73 node _T_1723 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(_T_1723, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1723, UInt<1>(0h1), "") : assert_74 node _T_1727 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1728 = or(UInt<1>(0h1), _T_1727) node _T_1729 = asUInt(reset) node _T_1730 = eq(_T_1729, UInt<1>(0h0)) when _T_1730 : node _T_1731 = eq(_T_1728, UInt<1>(0h0)) when _T_1731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1728, UInt<1>(0h1), "") : assert_75 node _T_1732 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1732 : node _T_1733 = asUInt(reset) node _T_1734 = eq(_T_1733, UInt<1>(0h0)) when _T_1734 : node _T_1735 = eq(source_ok_1, UInt<1>(0h0)) when _T_1735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1736 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1737 = asUInt(reset) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) when _T_1738 : node _T_1739 = eq(_T_1736, UInt<1>(0h0)) when _T_1739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1736, UInt<1>(0h1), "") : assert_77 node _T_1740 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1741 = or(_T_1740, io.in.d.bits.corrupt) node _T_1742 = asUInt(reset) node _T_1743 = eq(_T_1742, UInt<1>(0h0)) when _T_1743 : node _T_1744 = eq(_T_1741, UInt<1>(0h0)) when _T_1744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1741, UInt<1>(0h1), "") : assert_78 node _T_1745 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1746 = or(UInt<1>(0h0), _T_1745) node _T_1747 = asUInt(reset) node _T_1748 = eq(_T_1747, UInt<1>(0h0)) when _T_1748 : node _T_1749 = eq(_T_1746, UInt<1>(0h0)) when _T_1749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1746, UInt<1>(0h1), "") : assert_79 node _T_1750 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1750 : node _T_1751 = asUInt(reset) node _T_1752 = eq(_T_1751, UInt<1>(0h0)) when _T_1752 : node _T_1753 = eq(source_ok_1, UInt<1>(0h0)) when _T_1753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1754 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1755 = asUInt(reset) node _T_1756 = eq(_T_1755, UInt<1>(0h0)) when _T_1756 : node _T_1757 = eq(_T_1754, UInt<1>(0h0)) when _T_1757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1754, UInt<1>(0h1), "") : assert_81 node _T_1758 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1759 = asUInt(reset) node _T_1760 = eq(_T_1759, UInt<1>(0h0)) when _T_1760 : node _T_1761 = eq(_T_1758, UInt<1>(0h0)) when _T_1761 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1758, UInt<1>(0h1), "") : assert_82 node _T_1762 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1763 = or(UInt<1>(0h1), _T_1762) node _T_1764 = asUInt(reset) node _T_1765 = eq(_T_1764, UInt<1>(0h0)) when _T_1765 : node _T_1766 = eq(_T_1763, UInt<1>(0h0)) when _T_1766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1763, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<10>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1767 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1768 = asUInt(reset) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) when _T_1769 : node _T_1770 = eq(_T_1767, UInt<1>(0h0)) when _T_1770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1767, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<10>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1771 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1772 = asUInt(reset) node _T_1773 = eq(_T_1772, UInt<1>(0h0)) when _T_1773 : node _T_1774 = eq(_T_1771, UInt<1>(0h0)) when _T_1774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1771, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1775 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(_T_1775, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1775, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1779 = eq(a_first, UInt<1>(0h0)) node _T_1780 = and(io.in.a.valid, _T_1779) when _T_1780 : node _T_1781 = eq(io.in.a.bits.opcode, opcode) node _T_1782 = asUInt(reset) node _T_1783 = eq(_T_1782, UInt<1>(0h0)) when _T_1783 : node _T_1784 = eq(_T_1781, UInt<1>(0h0)) when _T_1784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1781, UInt<1>(0h1), "") : assert_87 node _T_1785 = eq(io.in.a.bits.param, param) node _T_1786 = asUInt(reset) node _T_1787 = eq(_T_1786, UInt<1>(0h0)) when _T_1787 : node _T_1788 = eq(_T_1785, UInt<1>(0h0)) when _T_1788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1785, UInt<1>(0h1), "") : assert_88 node _T_1789 = eq(io.in.a.bits.size, size) node _T_1790 = asUInt(reset) node _T_1791 = eq(_T_1790, UInt<1>(0h0)) when _T_1791 : node _T_1792 = eq(_T_1789, UInt<1>(0h0)) when _T_1792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1789, UInt<1>(0h1), "") : assert_89 node _T_1793 = eq(io.in.a.bits.source, source) node _T_1794 = asUInt(reset) node _T_1795 = eq(_T_1794, UInt<1>(0h0)) when _T_1795 : node _T_1796 = eq(_T_1793, UInt<1>(0h0)) when _T_1796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1793, UInt<1>(0h1), "") : assert_90 node _T_1797 = eq(io.in.a.bits.address, address) node _T_1798 = asUInt(reset) node _T_1799 = eq(_T_1798, UInt<1>(0h0)) when _T_1799 : node _T_1800 = eq(_T_1797, UInt<1>(0h0)) when _T_1800 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1797, UInt<1>(0h1), "") : assert_91 node _T_1801 = and(io.in.a.ready, io.in.a.valid) node _T_1802 = and(_T_1801, a_first) when _T_1802 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1803 = eq(d_first, UInt<1>(0h0)) node _T_1804 = and(io.in.d.valid, _T_1803) when _T_1804 : node _T_1805 = eq(io.in.d.bits.opcode, opcode_1) node _T_1806 = asUInt(reset) node _T_1807 = eq(_T_1806, UInt<1>(0h0)) when _T_1807 : node _T_1808 = eq(_T_1805, UInt<1>(0h0)) when _T_1808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1805, UInt<1>(0h1), "") : assert_92 node _T_1809 = eq(io.in.d.bits.param, param_1) node _T_1810 = asUInt(reset) node _T_1811 = eq(_T_1810, UInt<1>(0h0)) when _T_1811 : node _T_1812 = eq(_T_1809, UInt<1>(0h0)) when _T_1812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1809, UInt<1>(0h1), "") : assert_93 node _T_1813 = eq(io.in.d.bits.size, size_1) node _T_1814 = asUInt(reset) node _T_1815 = eq(_T_1814, UInt<1>(0h0)) when _T_1815 : node _T_1816 = eq(_T_1813, UInt<1>(0h0)) when _T_1816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1813, UInt<1>(0h1), "") : assert_94 node _T_1817 = eq(io.in.d.bits.source, source_1) node _T_1818 = asUInt(reset) node _T_1819 = eq(_T_1818, UInt<1>(0h0)) when _T_1819 : node _T_1820 = eq(_T_1817, UInt<1>(0h0)) when _T_1820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1817, UInt<1>(0h1), "") : assert_95 node _T_1821 = eq(io.in.d.bits.sink, sink) node _T_1822 = asUInt(reset) node _T_1823 = eq(_T_1822, UInt<1>(0h0)) when _T_1823 : node _T_1824 = eq(_T_1821, UInt<1>(0h0)) when _T_1824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1821, UInt<1>(0h1), "") : assert_96 node _T_1825 = eq(io.in.d.bits.denied, denied) node _T_1826 = asUInt(reset) node _T_1827 = eq(_T_1826, UInt<1>(0h0)) when _T_1827 : node _T_1828 = eq(_T_1825, UInt<1>(0h0)) when _T_1828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1825, UInt<1>(0h1), "") : assert_97 node _T_1829 = and(io.in.d.ready, io.in.d.valid) node _T_1830 = and(_T_1829, d_first) when _T_1830 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes : UInt<2052>, clock, reset, UInt<2052>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<513> connect a_set, UInt<513>(0h0) wire a_set_wo_ready : UInt<513> connect a_set_wo_ready, UInt<513>(0h0) wire a_opcodes_set : UInt<2052> connect a_opcodes_set, UInt<2052>(0h0) wire a_sizes_set : UInt<2052> connect a_sizes_set, UInt<2052>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1831 = and(io.in.a.valid, a_first_1) node _T_1832 = and(_T_1831, UInt<1>(0h1)) when _T_1832 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1833 = and(io.in.a.ready, io.in.a.valid) node _T_1834 = and(_T_1833, a_first_1) node _T_1835 = and(_T_1834, UInt<1>(0h1)) when _T_1835 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1836 = dshr(inflight, io.in.a.bits.source) node _T_1837 = bits(_T_1836, 0, 0) node _T_1838 = eq(_T_1837, UInt<1>(0h0)) node _T_1839 = asUInt(reset) node _T_1840 = eq(_T_1839, UInt<1>(0h0)) when _T_1840 : node _T_1841 = eq(_T_1838, UInt<1>(0h0)) when _T_1841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1838, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<513> connect d_clr, UInt<513>(0h0) wire d_clr_wo_ready : UInt<513> connect d_clr_wo_ready, UInt<513>(0h0) wire d_opcodes_clr : UInt<2052> connect d_opcodes_clr, UInt<2052>(0h0) wire d_sizes_clr : UInt<2052> connect d_sizes_clr, UInt<2052>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1842 = and(io.in.d.valid, d_first_1) node _T_1843 = and(_T_1842, UInt<1>(0h1)) node _T_1844 = eq(d_release_ack, UInt<1>(0h0)) node _T_1845 = and(_T_1843, _T_1844) when _T_1845 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1846 = and(io.in.d.ready, io.in.d.valid) node _T_1847 = and(_T_1846, d_first_1) node _T_1848 = and(_T_1847, UInt<1>(0h1)) node _T_1849 = eq(d_release_ack, UInt<1>(0h0)) node _T_1850 = and(_T_1848, _T_1849) when _T_1850 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1851 = and(io.in.d.valid, d_first_1) node _T_1852 = and(_T_1851, UInt<1>(0h1)) node _T_1853 = eq(d_release_ack, UInt<1>(0h0)) node _T_1854 = and(_T_1852, _T_1853) when _T_1854 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1855 = dshr(inflight, io.in.d.bits.source) node _T_1856 = bits(_T_1855, 0, 0) node _T_1857 = or(_T_1856, same_cycle_resp) node _T_1858 = asUInt(reset) node _T_1859 = eq(_T_1858, UInt<1>(0h0)) when _T_1859 : node _T_1860 = eq(_T_1857, UInt<1>(0h0)) when _T_1860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1857, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1861 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1862 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1863 = or(_T_1861, _T_1862) node _T_1864 = asUInt(reset) node _T_1865 = eq(_T_1864, UInt<1>(0h0)) when _T_1865 : node _T_1866 = eq(_T_1863, UInt<1>(0h0)) when _T_1866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1863, UInt<1>(0h1), "") : assert_100 node _T_1867 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1868 = asUInt(reset) node _T_1869 = eq(_T_1868, UInt<1>(0h0)) when _T_1869 : node _T_1870 = eq(_T_1867, UInt<1>(0h0)) when _T_1870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1867, UInt<1>(0h1), "") : assert_101 else : node _T_1871 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1872 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1873 = or(_T_1871, _T_1872) node _T_1874 = asUInt(reset) node _T_1875 = eq(_T_1874, UInt<1>(0h0)) when _T_1875 : node _T_1876 = eq(_T_1873, UInt<1>(0h0)) when _T_1876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1873, UInt<1>(0h1), "") : assert_102 node _T_1877 = eq(io.in.d.bits.size, a_size_lookup) node _T_1878 = asUInt(reset) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) when _T_1879 : node _T_1880 = eq(_T_1877, UInt<1>(0h0)) when _T_1880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1877, UInt<1>(0h1), "") : assert_103 node _T_1881 = and(io.in.d.valid, d_first_1) node _T_1882 = and(_T_1881, a_first_1) node _T_1883 = and(_T_1882, io.in.a.valid) node _T_1884 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1885 = and(_T_1883, _T_1884) node _T_1886 = eq(d_release_ack, UInt<1>(0h0)) node _T_1887 = and(_T_1885, _T_1886) when _T_1887 : node _T_1888 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1889 = or(_T_1888, io.in.a.ready) node _T_1890 = asUInt(reset) node _T_1891 = eq(_T_1890, UInt<1>(0h0)) when _T_1891 : node _T_1892 = eq(_T_1889, UInt<1>(0h0)) when _T_1892 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1889, UInt<1>(0h1), "") : assert_104 node _T_1893 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1894 = orr(a_set_wo_ready) node _T_1895 = eq(_T_1894, UInt<1>(0h0)) node _T_1896 = or(_T_1893, _T_1895) node _T_1897 = asUInt(reset) node _T_1898 = eq(_T_1897, UInt<1>(0h0)) when _T_1898 : node _T_1899 = eq(_T_1896, UInt<1>(0h0)) when _T_1899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1896, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_16 node _T_1900 = orr(inflight) node _T_1901 = eq(_T_1900, UInt<1>(0h0)) node _T_1902 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1903 = or(_T_1901, _T_1902) node _T_1904 = lt(watchdog, plusarg_reader.out) node _T_1905 = or(_T_1903, _T_1904) node _T_1906 = asUInt(reset) node _T_1907 = eq(_T_1906, UInt<1>(0h0)) when _T_1907 : node _T_1908 = eq(_T_1905, UInt<1>(0h0)) when _T_1908 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1905, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1909 = and(io.in.a.ready, io.in.a.valid) node _T_1910 = and(io.in.d.ready, io.in.d.valid) node _T_1911 = or(_T_1909, _T_1910) when _T_1911 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<10>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<10>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<513> connect c_set, UInt<513>(0h0) wire c_set_wo_ready : UInt<513> connect c_set_wo_ready, UInt<513>(0h0) wire c_opcodes_set : UInt<2052> connect c_opcodes_set, UInt<2052>(0h0) wire c_sizes_set : UInt<2052> connect c_sizes_set, UInt<2052>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<10>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1912 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<10>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1913 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1914 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1915 = and(_T_1913, _T_1914) node _T_1916 = and(_T_1912, _T_1915) when _T_1916 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<10>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<10>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1917 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1918 = and(_T_1917, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<10>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1919 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1920 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1921 = and(_T_1919, _T_1920) node _T_1922 = and(_T_1918, _T_1921) when _T_1922 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<10>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<10>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1923 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1924 = bits(_T_1923, 0, 0) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) node _T_1926 = asUInt(reset) node _T_1927 = eq(_T_1926, UInt<1>(0h0)) when _T_1927 : node _T_1928 = eq(_T_1925, UInt<1>(0h0)) when _T_1928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1925, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<513> connect d_clr_1, UInt<513>(0h0) wire d_clr_wo_ready_1 : UInt<513> connect d_clr_wo_ready_1, UInt<513>(0h0) wire d_opcodes_clr_1 : UInt<2052> connect d_opcodes_clr_1, UInt<2052>(0h0) wire d_sizes_clr_1 : UInt<2052> connect d_sizes_clr_1, UInt<2052>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1929 = and(io.in.d.valid, d_first_2) node _T_1930 = and(_T_1929, UInt<1>(0h1)) node _T_1931 = and(_T_1930, d_release_ack_1) when _T_1931 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1932 = and(io.in.d.ready, io.in.d.valid) node _T_1933 = and(_T_1932, d_first_2) node _T_1934 = and(_T_1933, UInt<1>(0h1)) node _T_1935 = and(_T_1934, d_release_ack_1) when _T_1935 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1936 = and(io.in.d.valid, d_first_2) node _T_1937 = and(_T_1936, UInt<1>(0h1)) node _T_1938 = and(_T_1937, d_release_ack_1) when _T_1938 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1939 = dshr(inflight_1, io.in.d.bits.source) node _T_1940 = bits(_T_1939, 0, 0) node _T_1941 = or(_T_1940, same_cycle_resp_1) node _T_1942 = asUInt(reset) node _T_1943 = eq(_T_1942, UInt<1>(0h0)) when _T_1943 : node _T_1944 = eq(_T_1941, UInt<1>(0h0)) when _T_1944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1941, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<10>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1945 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1946 = asUInt(reset) node _T_1947 = eq(_T_1946, UInt<1>(0h0)) when _T_1947 : node _T_1948 = eq(_T_1945, UInt<1>(0h0)) when _T_1948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1945, UInt<1>(0h1), "") : assert_109 else : node _T_1949 = eq(io.in.d.bits.size, c_size_lookup) node _T_1950 = asUInt(reset) node _T_1951 = eq(_T_1950, UInt<1>(0h0)) when _T_1951 : node _T_1952 = eq(_T_1949, UInt<1>(0h0)) when _T_1952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1949, UInt<1>(0h1), "") : assert_110 node _T_1953 = and(io.in.d.valid, d_first_2) node _T_1954 = and(_T_1953, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<10>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1955 = and(_T_1954, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<10>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1956 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1957 = and(_T_1955, _T_1956) node _T_1958 = and(_T_1957, d_release_ack_1) node _T_1959 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1960 = and(_T_1958, _T_1959) when _T_1960 : node _T_1961 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_26.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<10>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1962 = or(_T_1961, _WIRE_27.ready) node _T_1963 = asUInt(reset) node _T_1964 = eq(_T_1963, UInt<1>(0h0)) when _T_1964 : node _T_1965 = eq(_T_1962, UInt<1>(0h0)) when _T_1965 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1962, UInt<1>(0h1), "") : assert_111 node _T_1966 = orr(c_set_wo_ready) when _T_1966 : node _T_1967 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1968 = asUInt(reset) node _T_1969 = eq(_T_1968, UInt<1>(0h0)) when _T_1969 : node _T_1970 = eq(_T_1967, UInt<1>(0h0)) when _T_1970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1967, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_17 node _T_1971 = orr(inflight_1) node _T_1972 = eq(_T_1971, UInt<1>(0h0)) node _T_1973 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1974 = or(_T_1972, _T_1973) node _T_1975 = lt(watchdog_1, plusarg_reader_1.out) node _T_1976 = or(_T_1974, _T_1975) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<10>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1980 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1981 = and(io.in.d.ready, io.in.d.valid) node _T_1982 = or(_T_1980, _T_1981) when _T_1982 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_8( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [9:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [9:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [512:0] inflight; // @[Monitor.scala:614:27] reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [2051:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [1023:0] _GEN_0 = {1014'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [1023:0] _GEN_3 = {1014'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [512:0] inflight_1; // @[Monitor.scala:726:35] reg [2051:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_19 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T	module MulAddRecFNToRaw_preMul_e8_s24_19( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [8:0] rawC_exp = 9'h0; // @[rawFloatFromRecFN.scala:51:21] wire [9:0] rawC_sExp = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawC_out_sExp_T = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25] wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30] wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20] wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68] wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9] wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23] wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30] wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57] wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11] wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46] wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _sNatCAlignDist_T = {sExpAlignedProd[10], sExpAlignedProd}; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero \| rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T \| _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign \| _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}] wire _alignedSigC_T_6 = \|_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 \| _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN \| rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _sNatCAlignDist_T - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_1 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} inst main of BranchKillableQueue connect main.clock, clock connect main.reset, reset reg out_reg : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock regreset out_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock connect main.io.enq, io.enq connect main.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect main.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect main.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect main.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect main.io.brupdate.b2.taken, io.brupdate.b2.taken connect main.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect main.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect main.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect main.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect main.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect main.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect main.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect main.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect main.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect main.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect main.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect main.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect main.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect main.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect main.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect main.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect main.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect main.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect main.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect main.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect main.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect main.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect main.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect main.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect main.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect main.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect main.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect main.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect main.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect main.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect main.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect main.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect main.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect main.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect main.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect main.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect main.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect main.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect main.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect main.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect main.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect main.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect main.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect main.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect main.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect main.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect main.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect main.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect main.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect main.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect main.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect main.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect main.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect main.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect main.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect main.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect main.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect main.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect main.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect main.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect main.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect main.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect main.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect main.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect main.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect main.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect main.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect main.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect main.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect main.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect main.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect main.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect main.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect main.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect main.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect main.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect main.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect main.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect main.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect main.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect main.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect main.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect main.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect main.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect main.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect main.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect main.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect main.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect main.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect main.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect main.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect main.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect main.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect main.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect main.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect main.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect main.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect main.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect main.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect main.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect main.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect main.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect main.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect main.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect main.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect main.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect main.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect main.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect main.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect main.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect main.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect main.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect main.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect main.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect main.io.flush, io.flush node _io_empty_T = eq(out_valid, UInt<1>(0h0)) node _io_empty_T_1 = and(main.io.empty, _io_empty_T) connect io.empty, _io_empty_T_1 node _io_count_T = add(main.io.count, out_valid) node _io_count_T_1 = tail(_io_count_T, 1) connect io.count, _io_count_T_1 connect io.deq.valid, out_valid connect io.deq.bits, out_reg connect io.deq.bits.uop, out_uop wire out_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect out_uop_out, out_uop node _out_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _out_uop_out_br_mask_T_1 = and(out_uop.br_mask, _out_uop_out_br_mask_T) connect out_uop_out.br_mask, _out_uop_out_br_mask_T_1 connect out_uop, out_uop_out node _out_valid_T = and(io.brupdate.b1.mispredict_mask, out_uop.br_mask) node _out_valid_T_1 = neq(_out_valid_T, UInt<1>(0h0)) node _out_valid_T_2 = or(_out_valid_T_1, UInt<1>(0h0)) node _out_valid_T_3 = eq(_out_valid_T_2, UInt<1>(0h0)) node _out_valid_T_4 = and(out_valid, _out_valid_T_3) node _out_valid_T_5 = and(io.flush, out_uop.uses_ldq) node _out_valid_T_6 = eq(_out_valid_T_5, UInt<1>(0h0)) node _out_valid_T_7 = and(_out_valid_T_4, _out_valid_T_6) connect out_valid, _out_valid_T_7 connect main.io.deq.ready, UInt<1>(0h0) node _T = and(io.deq.ready, io.deq.valid) node _T_1 = eq(out_valid, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) when _T_2 : node _out_valid_T_8 = and(io.brupdate.b1.mispredict_mask, main.io.deq.bits.uop.br_mask) node _out_valid_T_9 = neq(_out_valid_T_8, UInt<1>(0h0)) node _out_valid_T_10 = or(_out_valid_T_9, UInt<1>(0h0)) node _out_valid_T_11 = eq(_out_valid_T_10, UInt<1>(0h0)) node _out_valid_T_12 = and(main.io.deq.valid, _out_valid_T_11) node _out_valid_T_13 = and(io.flush, main.io.deq.bits.uop.uses_ldq) node _out_valid_T_14 = eq(_out_valid_T_13, UInt<1>(0h0)) node _out_valid_T_15 = and(_out_valid_T_12, _out_valid_T_14) connect out_valid, _out_valid_T_15 connect out_reg, main.io.deq.bits wire out_uop_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect out_uop_out_1, main.io.deq.bits.uop node _out_uop_out_br_mask_T_2 = not(io.brupdate.b1.resolve_mask) node _out_uop_out_br_mask_T_3 = and(main.io.deq.bits.uop.br_mask, _out_uop_out_br_mask_T_2) connect out_uop_out_1.br_mask, _out_uop_out_br_mask_T_3 connect out_uop, out_uop_out_1 connect main.io.deq.ready, UInt<1>(0h1)	module BranchKillableQueue_1( // @[util.scala:458:7] input clock, // @[util.scala:458:7] input reset, // @[util.scala:458:7] output io_enq_ready, // @[util.scala:463:14] input io_enq_valid, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14] input io_enq_bits_uop_is_rvc, // @[util.scala:463:14] input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14] input io_enq_bits_uop_is_sfb, // @[util.scala:463:14] input io_enq_bits_uop_is_fence, // @[util.scala:463:14] input io_enq_bits_uop_is_fencei, // @[util.scala:463:14] input io_enq_bits_uop_is_sfence, // @[util.scala:463:14] input io_enq_bits_uop_is_amo, // @[util.scala:463:14] input io_enq_bits_uop_is_eret, // @[util.scala:463:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_enq_bits_uop_is_rocc, // @[util.scala:463:14] input io_enq_bits_uop_is_mov, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14] input io_enq_bits_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14] input io_enq_bits_uop_taken, // @[util.scala:463:14] input io_enq_bits_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14] input io_enq_bits_uop_exception, // @[util.scala:463:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14] input io_enq_bits_uop_mem_signed, // @[util.scala:463:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14] input io_enq_bits_uop_uses_stq, // @[util.scala:463:14] input io_enq_bits_uop_is_unique, // @[util.scala:463:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14] input io_enq_bits_uop_frs3_en, // @[util.scala:463:14] input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14] input io_enq_bits_uop_fp_val, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14] input [33:0] io_enq_bits_addr, // @[util.scala:463:14] input [63:0] io_enq_bits_data, // @[util.scala:463:14] input io_enq_bits_is_hella, // @[util.scala:463:14] input io_enq_bits_tag_match, // @[util.scala:463:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14] input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14] input [1:0] io_enq_bits_way_en, // @[util.scala:463:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14] input io_deq_ready, // @[util.scala:463:14] output io_deq_valid, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14] output io_deq_bits_uop_is_rvc, // @[util.scala:463:14] output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14] output io_deq_bits_uop_is_sfb, // @[util.scala:463:14] output io_deq_bits_uop_is_fence, // @[util.scala:463:14] output io_deq_bits_uop_is_fencei, // @[util.scala:463:14] output io_deq_bits_uop_is_sfence, // @[util.scala:463:14] output io_deq_bits_uop_is_amo, // @[util.scala:463:14] output io_deq_bits_uop_is_eret, // @[util.scala:463:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] output io_deq_bits_uop_is_rocc, // @[util.scala:463:14] output io_deq_bits_uop_is_mov, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14] output io_deq_bits_uop_edge_inst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14] output io_deq_bits_uop_taken, // @[util.scala:463:14] output io_deq_bits_uop_imm_rename, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14] output io_deq_bits_uop_exception, // @[util.scala:463:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14] output io_deq_bits_uop_mem_signed, // @[util.scala:463:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14] output io_deq_bits_uop_uses_stq, // @[util.scala:463:14] output io_deq_bits_uop_is_unique, // @[util.scala:463:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14] output io_deq_bits_uop_frs3_en, // @[util.scala:463:14] output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14] output io_deq_bits_uop_fp_val, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14] output [33:0] io_deq_bits_addr, // @[util.scala:463:14] output [63:0] io_deq_bits_data, // @[util.scala:463:14] output io_deq_bits_is_hella, // @[util.scala:463:14] output io_deq_bits_tag_match, // @[util.scala:463:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14] output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14] output [1:0] io_deq_bits_way_en, // @[util.scala:463:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14] output io_empty // @[util.scala:463:14] ); wire _out_valid_T_12; // @[util.scala:496:38] wire [31:0] _main_io_deq_bits_uop_inst; // @[util.scala:476:22] wire [31:0] _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22] wire [33:0] _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_br_type; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22] wire _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22] wire _main_io_deq_bits_uop_taken; // @[util.scala:476:22] wire _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_pimm; // @[util.scala:476:22] wire [19:0] _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_pdst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_prs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_prs2; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_prs3; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_ppred; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_exception; // @[util.scala:476:22] wire [63:0] _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22] wire _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22] wire _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22] wire _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22] wire _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22] wire _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_ldst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22] wire _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22] wire [33:0] _main_io_deq_bits_addr; // @[util.scala:476:22] wire [63:0] _main_io_deq_bits_data; // @[util.scala:476:22] wire _main_io_deq_bits_is_hella; // @[util.scala:476:22] wire _main_io_deq_bits_tag_match; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22] wire [21:0] _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_way_en; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_sdq_id; // @[util.scala:476:22] wire _main_io_empty; // @[util.scala:476:22] wire [3:0] _main_io_count; // @[util.scala:476:22] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7] wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7] wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7] wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7] wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7] wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7] wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7] wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7] wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7] wire _out_valid_T_3 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire _out_valid_T_6 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire _out_valid_T_11 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire _out_valid_T_14 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire [3:0] _out_uop_out_br_mask_T = 4'hF; // @[util.scala:93:27] wire [3:0] _out_uop_out_br_mask_T_2 = 4'hF; // @[util.scala:93:27] wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14, :476:22] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14, :476:22] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14, :476:22] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14, :476:22] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7] wire io_flush = 1'h0; // @[util.scala:458:7] wire _out_valid_T_1 = 1'h0; // @[util.scala:126:59] wire _out_valid_T_2 = 1'h0; // @[util.scala:61:61] wire _out_valid_T_5 = 1'h0; // @[util.scala:492:94] wire _out_valid_T_9 = 1'h0; // @[util.scala:126:59] wire _out_valid_T_10 = 1'h0; // @[util.scala:61:61] wire _out_valid_T_13 = 1'h0; // @[util.scala:496:117] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] _out_valid_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] _out_valid_T_8 = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire _io_empty_T_1; // @[util.scala:484:31] wire [3:0] _io_count_T_1; // @[util.scala:485:31] wire io_enq_ready_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] wire io_deq_bits_uop_taken_0; // @[util.scala:458:7] wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] wire io_deq_bits_uop_exception_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7] wire io_deq_bits_is_hella_0; // @[util.scala:458:7] wire io_deq_bits_tag_match_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7] wire io_deq_valid_0; // @[util.scala:458:7] wire io_empty_0; // @[util.scala:458:7] wire [3:0] io_count; // @[util.scala:458:7] reg [31:0] out_reg_uop_inst; // @[util.scala:477:22] reg [31:0] out_reg_uop_debug_inst; // @[util.scala:477:22] reg out_reg_uop_is_rvc; // @[util.scala:477:22] reg [33:0] out_reg_uop_debug_pc; // @[util.scala:477:22] reg out_reg_uop_iq_type_0; // @[util.scala:477:22] reg out_reg_uop_iq_type_1; // @[util.scala:477:22] reg out_reg_uop_iq_type_2; // @[util.scala:477:22] reg out_reg_uop_iq_type_3; // @[util.scala:477:22] reg out_reg_uop_fu_code_0; // @[util.scala:477:22] reg out_reg_uop_fu_code_1; // @[util.scala:477:22] reg out_reg_uop_fu_code_2; // @[util.scala:477:22] reg out_reg_uop_fu_code_3; // @[util.scala:477:22] reg out_reg_uop_fu_code_4; // @[util.scala:477:22] reg out_reg_uop_fu_code_5; // @[util.scala:477:22] reg out_reg_uop_fu_code_6; // @[util.scala:477:22] reg out_reg_uop_fu_code_7; // @[util.scala:477:22] reg out_reg_uop_fu_code_8; // @[util.scala:477:22] reg out_reg_uop_fu_code_9; // @[util.scala:477:22] reg out_reg_uop_iw_issued; // @[util.scala:477:22] reg out_reg_uop_iw_issued_partial_agen; // @[util.scala:477:22] reg out_reg_uop_iw_issued_partial_dgen; // @[util.scala:477:22] reg out_reg_uop_iw_p1_speculative_child; // @[util.scala:477:22] reg out_reg_uop_iw_p2_speculative_child; // @[util.scala:477:22] reg out_reg_uop_iw_p1_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_iw_p2_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_iw_p3_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_dis_col_sel; // @[util.scala:477:22] reg [3:0] out_reg_uop_br_mask; // @[util.scala:477:22] reg [1:0] out_reg_uop_br_tag; // @[util.scala:477:22] reg [3:0] out_reg_uop_br_type; // @[util.scala:477:22] reg out_reg_uop_is_sfb; // @[util.scala:477:22] reg out_reg_uop_is_fence; // @[util.scala:477:22] reg out_reg_uop_is_fencei; // @[util.scala:477:22] reg out_reg_uop_is_sfence; // @[util.scala:477:22] reg out_reg_uop_is_amo; // @[util.scala:477:22] reg out_reg_uop_is_eret; // @[util.scala:477:22] reg out_reg_uop_is_sys_pc2epc; // @[util.scala:477:22] reg out_reg_uop_is_rocc; // @[util.scala:477:22] reg out_reg_uop_is_mov; // @[util.scala:477:22] reg [3:0] out_reg_uop_ftq_idx; // @[util.scala:477:22] reg out_reg_uop_edge_inst; // @[util.scala:477:22] reg [5:0] out_reg_uop_pc_lob; // @[util.scala:477:22] reg out_reg_uop_taken; // @[util.scala:477:22] reg out_reg_uop_imm_rename; // @[util.scala:477:22] reg [2:0] out_reg_uop_imm_sel; // @[util.scala:477:22] reg [4:0] out_reg_uop_pimm; // @[util.scala:477:22] reg [19:0] out_reg_uop_imm_packed; // @[util.scala:477:22] reg [1:0] out_reg_uop_op1_sel; // @[util.scala:477:22] reg [2:0] out_reg_uop_op2_sel; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ldst; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_wen; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren1; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren2; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren3; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_swap12; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_swap23; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_ctrl_typeTagIn; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_ctrl_typeTagOut; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fromint; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_toint; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fastpipe; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fma; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_div; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_sqrt; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_wflags; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_vec; // @[util.scala:477:22] reg [4:0] out_reg_uop_rob_idx; // @[util.scala:477:22] reg [3:0] out_reg_uop_ldq_idx; // @[util.scala:477:22] reg [3:0] out_reg_uop_stq_idx; // @[util.scala:477:22] reg [1:0] out_reg_uop_rxq_idx; // @[util.scala:477:22] reg [5:0] out_reg_uop_pdst; // @[util.scala:477:22] reg [5:0] out_reg_uop_prs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_prs2; // @[util.scala:477:22] reg [5:0] out_reg_uop_prs3; // @[util.scala:477:22] reg [3:0] out_reg_uop_ppred; // @[util.scala:477:22] reg out_reg_uop_prs1_busy; // @[util.scala:477:22] reg out_reg_uop_prs2_busy; // @[util.scala:477:22] reg out_reg_uop_prs3_busy; // @[util.scala:477:22] reg out_reg_uop_ppred_busy; // @[util.scala:477:22] reg [5:0] out_reg_uop_stale_pdst; // @[util.scala:477:22] reg out_reg_uop_exception; // @[util.scala:477:22] reg [63:0] out_reg_uop_exc_cause; // @[util.scala:477:22] reg [4:0] out_reg_uop_mem_cmd; // @[util.scala:477:22] reg [1:0] out_reg_uop_mem_size; // @[util.scala:477:22] reg out_reg_uop_mem_signed; // @[util.scala:477:22] reg out_reg_uop_uses_ldq; // @[util.scala:477:22] reg out_reg_uop_uses_stq; // @[util.scala:477:22] reg out_reg_uop_is_unique; // @[util.scala:477:22] reg out_reg_uop_flush_on_commit; // @[util.scala:477:22] reg [2:0] out_reg_uop_csr_cmd; // @[util.scala:477:22] reg out_reg_uop_ldst_is_rs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_ldst; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs2; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs3; // @[util.scala:477:22] reg [1:0] out_reg_uop_dst_rtype; // @[util.scala:477:22] reg [1:0] out_reg_uop_lrs1_rtype; // @[util.scala:477:22] reg [1:0] out_reg_uop_lrs2_rtype; // @[util.scala:477:22] reg out_reg_uop_frs3_en; // @[util.scala:477:22] reg out_reg_uop_fcn_dw; // @[util.scala:477:22] reg [4:0] out_reg_uop_fcn_op; // @[util.scala:477:22] reg out_reg_uop_fp_val; // @[util.scala:477:22] reg [2:0] out_reg_uop_fp_rm; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_typ; // @[util.scala:477:22] reg out_reg_uop_xcpt_pf_if; // @[util.scala:477:22] reg out_reg_uop_xcpt_ae_if; // @[util.scala:477:22] reg out_reg_uop_xcpt_ma_if; // @[util.scala:477:22] reg out_reg_uop_bp_debug_if; // @[util.scala:477:22] reg out_reg_uop_bp_xcpt_if; // @[util.scala:477:22] reg [2:0] out_reg_uop_debug_fsrc; // @[util.scala:477:22] reg [2:0] out_reg_uop_debug_tsrc; // @[util.scala:477:22] reg [33:0] out_reg_addr; // @[util.scala:477:22] assign io_deq_bits_addr_0 = out_reg_addr; // @[util.scala:458:7, :477:22] reg [63:0] out_reg_data; // @[util.scala:477:22] assign io_deq_bits_data_0 = out_reg_data; // @[util.scala:458:7, :477:22] reg out_reg_is_hella; // @[util.scala:477:22] assign io_deq_bits_is_hella_0 = out_reg_is_hella; // @[util.scala:458:7, :477:22] reg out_reg_tag_match; // @[util.scala:477:22] assign io_deq_bits_tag_match_0 = out_reg_tag_match; // @[util.scala:458:7, :477:22] reg [1:0] out_reg_old_meta_coh_state; // @[util.scala:477:22] assign io_deq_bits_old_meta_coh_state_0 = out_reg_old_meta_coh_state; // @[util.scala:458:7, :477:22] reg [21:0] out_reg_old_meta_tag; // @[util.scala:477:22] assign io_deq_bits_old_meta_tag_0 = out_reg_old_meta_tag; // @[util.scala:458:7, :477:22] reg [1:0] out_reg_way_en; // @[util.scala:477:22] assign io_deq_bits_way_en_0 = out_reg_way_en; // @[util.scala:458:7, :477:22] reg [4:0] out_reg_sdq_id; // @[util.scala:477:22] assign io_deq_bits_sdq_id_0 = out_reg_sdq_id; // @[util.scala:458:7, :477:22] reg out_valid; // @[util.scala:478:28] assign io_deq_valid_0 = out_valid; // @[util.scala:458:7, :478:28] wire _out_valid_T_4 = out_valid; // @[util.scala:478:28, :492:28] reg [31:0] out_uop_inst; // @[util.scala:479:22] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :479:22] wire [31:0] out_uop_out_inst = out_uop_inst; // @[util.scala:104:23, :479:22] reg [31:0] out_uop_debug_inst; // @[util.scala:479:22] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :479:22] wire [31:0] out_uop_out_debug_inst = out_uop_debug_inst; // @[util.scala:104:23, :479:22] reg out_uop_is_rvc; // @[util.scala:479:22] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_rvc = out_uop_is_rvc; // @[util.scala:104:23, :479:22] reg [33:0] out_uop_debug_pc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :479:22] wire [33:0] out_uop_out_debug_pc = out_uop_debug_pc; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_0; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_0 = out_uop_iq_type_0; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_1; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_1 = out_uop_iq_type_1; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_2; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_2 = out_uop_iq_type_2; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_3; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_3 = out_uop_iq_type_3; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_0; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_0 = out_uop_fu_code_0; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_1; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_1 = out_uop_fu_code_1; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_2; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_2 = out_uop_fu_code_2; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_3; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_3 = out_uop_fu_code_3; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_4; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_4 = out_uop_fu_code_4; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_5; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_5 = out_uop_fu_code_5; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_6; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_6 = out_uop_fu_code_6; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_7; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_7 = out_uop_fu_code_7; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_8; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_8 = out_uop_fu_code_8; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_9; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_9 = out_uop_fu_code_9; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued = out_uop_iw_issued; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued_partial_agen; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued_partial_agen = out_uop_iw_issued_partial_agen; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued_partial_dgen; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued_partial_dgen = out_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22] reg out_uop_iw_p1_speculative_child; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p1_speculative_child = out_uop_iw_p1_speculative_child; // @[util.scala:104:23, :479:22] reg out_uop_iw_p2_speculative_child; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p2_speculative_child = out_uop_iw_p2_speculative_child; // @[util.scala:104:23, :479:22] reg out_uop_iw_p1_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p1_bypass_hint = out_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_iw_p2_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p2_bypass_hint = out_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_iw_p3_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p3_bypass_hint = out_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_dis_col_sel; // @[util.scala:479:22] assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :479:22] wire out_uop_out_dis_col_sel = out_uop_dis_col_sel; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_br_mask; // @[util.scala:479:22] assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :479:22] wire [3:0] _out_uop_out_br_mask_T_1 = out_uop_br_mask; // @[util.scala:93:25, :479:22] reg [1:0] out_uop_br_tag; // @[util.scala:479:22] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_br_tag = out_uop_br_tag; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_br_type; // @[util.scala:479:22] assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_br_type = out_uop_br_type; // @[util.scala:104:23, :479:22] reg out_uop_is_sfb; // @[util.scala:479:22] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sfb = out_uop_is_sfb; // @[util.scala:104:23, :479:22] reg out_uop_is_fence; // @[util.scala:479:22] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :479:22] wire out_uop_out_is_fence = out_uop_is_fence; // @[util.scala:104:23, :479:22] reg out_uop_is_fencei; // @[util.scala:479:22] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :479:22] wire out_uop_out_is_fencei = out_uop_is_fencei; // @[util.scala:104:23, :479:22] reg out_uop_is_sfence; // @[util.scala:479:22] assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sfence = out_uop_is_sfence; // @[util.scala:104:23, :479:22] reg out_uop_is_amo; // @[util.scala:479:22] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :479:22] wire out_uop_out_is_amo = out_uop_is_amo; // @[util.scala:104:23, :479:22] reg out_uop_is_eret; // @[util.scala:479:22] assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :479:22] wire out_uop_out_is_eret = out_uop_is_eret; // @[util.scala:104:23, :479:22] reg out_uop_is_sys_pc2epc; // @[util.scala:479:22] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sys_pc2epc = out_uop_is_sys_pc2epc; // @[util.scala:104:23, :479:22] reg out_uop_is_rocc; // @[util.scala:479:22] assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_rocc = out_uop_is_rocc; // @[util.scala:104:23, :479:22] reg out_uop_is_mov; // @[util.scala:479:22] assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :479:22] wire out_uop_out_is_mov = out_uop_is_mov; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_ftq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_ftq_idx = out_uop_ftq_idx; // @[util.scala:104:23, :479:22] reg out_uop_edge_inst; // @[util.scala:479:22] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :479:22] wire out_uop_out_edge_inst = out_uop_edge_inst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_pc_lob; // @[util.scala:479:22] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_pc_lob = out_uop_pc_lob; // @[util.scala:104:23, :479:22] reg out_uop_taken; // @[util.scala:479:22] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :479:22] wire out_uop_out_taken = out_uop_taken; // @[util.scala:104:23, :479:22] reg out_uop_imm_rename; // @[util.scala:479:22] assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :479:22] wire out_uop_out_imm_rename = out_uop_imm_rename; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_imm_sel; // @[util.scala:479:22] assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_imm_sel = out_uop_imm_sel; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_pimm; // @[util.scala:479:22] assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_pimm = out_uop_pimm; // @[util.scala:104:23, :479:22] reg [19:0] out_uop_imm_packed; // @[util.scala:479:22] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :479:22] wire [19:0] out_uop_out_imm_packed = out_uop_imm_packed; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_op1_sel; // @[util.scala:479:22] assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_op1_sel = out_uop_op1_sel; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_op2_sel; // @[util.scala:479:22] assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_op2_sel = out_uop_op2_sel; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ldst; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ldst = out_uop_fp_ctrl_ldst; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_wen; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_wen = out_uop_fp_ctrl_wen; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren1; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren1 = out_uop_fp_ctrl_ren1; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren2; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren2 = out_uop_fp_ctrl_ren2; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren3; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren3 = out_uop_fp_ctrl_ren3; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_swap12; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_swap12 = out_uop_fp_ctrl_swap12; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_swap23; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_swap23 = out_uop_fp_ctrl_swap23; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_ctrl_typeTagIn = out_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_ctrl_typeTagOut = out_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fromint; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fromint = out_uop_fp_ctrl_fromint; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_toint; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_toint = out_uop_fp_ctrl_toint; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fastpipe; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fastpipe = out_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fma; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fma = out_uop_fp_ctrl_fma; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_div; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_div = out_uop_fp_ctrl_div; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_sqrt; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_sqrt = out_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_wflags; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_wflags = out_uop_fp_ctrl_wflags; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_vec; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_vec = out_uop_fp_ctrl_vec; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_rob_idx; // @[util.scala:479:22] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_rob_idx = out_uop_rob_idx; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_ldq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_ldq_idx = out_uop_ldq_idx; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_stq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_stq_idx = out_uop_stq_idx; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_rxq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_rxq_idx = out_uop_rxq_idx; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_pdst; // @[util.scala:479:22] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_pdst = out_uop_pdst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_prs1; // @[util.scala:479:22] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_prs1 = out_uop_prs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_prs2; // @[util.scala:479:22] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_prs2 = out_uop_prs2; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_prs3; // @[util.scala:479:22] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_prs3 = out_uop_prs3; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_ppred; // @[util.scala:479:22] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_ppred = out_uop_ppred; // @[util.scala:104:23, :479:22] reg out_uop_prs1_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs1_busy = out_uop_prs1_busy; // @[util.scala:104:23, :479:22] reg out_uop_prs2_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs2_busy = out_uop_prs2_busy; // @[util.scala:104:23, :479:22] reg out_uop_prs3_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs3_busy = out_uop_prs3_busy; // @[util.scala:104:23, :479:22] reg out_uop_ppred_busy; // @[util.scala:479:22] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_ppred_busy = out_uop_ppred_busy; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_stale_pdst; // @[util.scala:479:22] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_stale_pdst = out_uop_stale_pdst; // @[util.scala:104:23, :479:22] reg out_uop_exception; // @[util.scala:479:22] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :479:22] wire out_uop_out_exception = out_uop_exception; // @[util.scala:104:23, :479:22] reg [63:0] out_uop_exc_cause; // @[util.scala:479:22] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :479:22] wire [63:0] out_uop_out_exc_cause = out_uop_exc_cause; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_mem_cmd; // @[util.scala:479:22] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_mem_cmd = out_uop_mem_cmd; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_mem_size; // @[util.scala:479:22] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_mem_size = out_uop_mem_size; // @[util.scala:104:23, :479:22] reg out_uop_mem_signed; // @[util.scala:479:22] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :479:22] wire out_uop_out_mem_signed = out_uop_mem_signed; // @[util.scala:104:23, :479:22] reg out_uop_uses_ldq; // @[util.scala:479:22] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :479:22] wire out_uop_out_uses_ldq = out_uop_uses_ldq; // @[util.scala:104:23, :479:22] reg out_uop_uses_stq; // @[util.scala:479:22] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :479:22] wire out_uop_out_uses_stq = out_uop_uses_stq; // @[util.scala:104:23, :479:22] reg out_uop_is_unique; // @[util.scala:479:22] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :479:22] wire out_uop_out_is_unique = out_uop_is_unique; // @[util.scala:104:23, :479:22] reg out_uop_flush_on_commit; // @[util.scala:479:22] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :479:22] wire out_uop_out_flush_on_commit = out_uop_flush_on_commit; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_csr_cmd; // @[util.scala:479:22] assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_csr_cmd = out_uop_csr_cmd; // @[util.scala:104:23, :479:22] reg out_uop_ldst_is_rs1; // @[util.scala:479:22] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :479:22] wire out_uop_out_ldst_is_rs1 = out_uop_ldst_is_rs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_ldst; // @[util.scala:479:22] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_ldst = out_uop_ldst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs1; // @[util.scala:479:22] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs1 = out_uop_lrs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs2; // @[util.scala:479:22] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs2 = out_uop_lrs2; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs3; // @[util.scala:479:22] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs3 = out_uop_lrs3; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_dst_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_dst_rtype = out_uop_dst_rtype; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_lrs1_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_lrs1_rtype = out_uop_lrs1_rtype; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_lrs2_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_lrs2_rtype = out_uop_lrs2_rtype; // @[util.scala:104:23, :479:22] reg out_uop_frs3_en; // @[util.scala:479:22] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :479:22] wire out_uop_out_frs3_en = out_uop_frs3_en; // @[util.scala:104:23, :479:22] reg out_uop_fcn_dw; // @[util.scala:479:22] assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :479:22] wire out_uop_out_fcn_dw = out_uop_fcn_dw; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_fcn_op; // @[util.scala:479:22] assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_fcn_op = out_uop_fcn_op; // @[util.scala:104:23, :479:22] reg out_uop_fp_val; // @[util.scala:479:22] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_val = out_uop_fp_val; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_fp_rm; // @[util.scala:479:22] assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_fp_rm = out_uop_fp_rm; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_typ; // @[util.scala:479:22] assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_typ = out_uop_fp_typ; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_pf_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_pf_if = out_uop_xcpt_pf_if; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_ae_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_ae_if = out_uop_xcpt_ae_if; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_ma_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_ma_if = out_uop_xcpt_ma_if; // @[util.scala:104:23, :479:22] reg out_uop_bp_debug_if; // @[util.scala:479:22] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :479:22] wire out_uop_out_bp_debug_if = out_uop_bp_debug_if; // @[util.scala:104:23, :479:22] reg out_uop_bp_xcpt_if; // @[util.scala:479:22] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :479:22] wire out_uop_out_bp_xcpt_if = out_uop_bp_xcpt_if; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_debug_fsrc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_debug_fsrc = out_uop_debug_fsrc; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_debug_tsrc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_debug_tsrc = out_uop_debug_tsrc; // @[util.scala:104:23, :479:22] wire _io_empty_T = ~out_valid; // @[util.scala:478:28, :484:34] assign _io_empty_T_1 = _main_io_empty & _io_empty_T; // @[util.scala:476:22, :484:{31,34}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :484:31] wire [4:0] _io_count_T = {1'h0, _main_io_count} + {4'h0, out_valid}; // @[util.scala:126:51, :458:7, :463:14, :476:22, :478:28, :485:31] assign _io_count_T_1 = _io_count_T[3:0]; // @[util.scala:485:31] assign io_count = _io_count_T_1; // @[util.scala:458:7, :485:31] wire [3:0] out_uop_out_br_mask; // @[util.scala:104:23] assign out_uop_out_br_mask = _out_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire _out_valid_T_7 = _out_valid_T_4; // @[util.scala:492:{28,80}] wire main_io_deq_ready = io_deq_ready_0 & io_deq_valid_0 \| ~out_valid; // @[Decoupled.scala:51:35] wire _out_valid_T_15 = _out_valid_T_12; // @[util.scala:496:{38,103}] wire [3:0] _out_uop_out_br_mask_T_3; // @[util.scala:93:25] wire out_uop_out_1_iq_type_0; // @[util.scala:104:23] wire out_uop_out_1_iq_type_1; // @[util.scala:104:23] wire out_uop_out_1_iq_type_2; // @[util.scala:104:23] wire out_uop_out_1_iq_type_3; // @[util.scala:104:23] wire out_uop_out_1_fu_code_0; // @[util.scala:104:23] wire out_uop_out_1_fu_code_1; // @[util.scala:104:23] wire out_uop_out_1_fu_code_2; // @[util.scala:104:23] wire out_uop_out_1_fu_code_3; // @[util.scala:104:23] wire out_uop_out_1_fu_code_4; // @[util.scala:104:23] wire out_uop_out_1_fu_code_5; // @[util.scala:104:23] wire out_uop_out_1_fu_code_6; // @[util.scala:104:23] wire out_uop_out_1_fu_code_7; // @[util.scala:104:23] wire out_uop_out_1_fu_code_8; // @[util.scala:104:23] wire out_uop_out_1_fu_code_9; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ldst; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_wen; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren1; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren2; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren3; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_swap12; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fromint; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_toint; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fastpipe; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fma; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_div; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_sqrt; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_wflags; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_vec; // @[util.scala:104:23] wire [31:0] out_uop_out_1_inst; // @[util.scala:104:23] wire [31:0] out_uop_out_1_debug_inst; // @[util.scala:104:23] wire out_uop_out_1_is_rvc; // @[util.scala:104:23] wire [33:0] out_uop_out_1_debug_pc; // @[util.scala:104:23] wire out_uop_out_1_iw_issued; // @[util.scala:104:23] wire out_uop_out_1_iw_issued_partial_agen; // @[util.scala:104:23] wire out_uop_out_1_iw_issued_partial_dgen; // @[util.scala:104:23] wire out_uop_out_1_iw_p1_speculative_child; // @[util.scala:104:23] wire out_uop_out_1_iw_p2_speculative_child; // @[util.scala:104:23] wire out_uop_out_1_iw_p1_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_iw_p2_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_iw_p3_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_dis_col_sel; // @[util.scala:104:23] wire [3:0] out_uop_out_1_br_mask; // @[util.scala:104:23] wire [1:0] out_uop_out_1_br_tag; // @[util.scala:104:23] wire [3:0] out_uop_out_1_br_type; // @[util.scala:104:23] wire out_uop_out_1_is_sfb; // @[util.scala:104:23] wire out_uop_out_1_is_fence; // @[util.scala:104:23] wire out_uop_out_1_is_fencei; // @[util.scala:104:23] wire out_uop_out_1_is_sfence; // @[util.scala:104:23] wire out_uop_out_1_is_amo; // @[util.scala:104:23] wire out_uop_out_1_is_eret; // @[util.scala:104:23] wire out_uop_out_1_is_sys_pc2epc; // @[util.scala:104:23] wire out_uop_out_1_is_rocc; // @[util.scala:104:23] wire out_uop_out_1_is_mov; // @[util.scala:104:23] wire [3:0] out_uop_out_1_ftq_idx; // @[util.scala:104:23] wire out_uop_out_1_edge_inst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_pc_lob; // @[util.scala:104:23] wire out_uop_out_1_taken; // @[util.scala:104:23] wire out_uop_out_1_imm_rename; // @[util.scala:104:23] wire [2:0] out_uop_out_1_imm_sel; // @[util.scala:104:23] wire [4:0] out_uop_out_1_pimm; // @[util.scala:104:23] wire [19:0] out_uop_out_1_imm_packed; // @[util.scala:104:23] wire [1:0] out_uop_out_1_op1_sel; // @[util.scala:104:23] wire [2:0] out_uop_out_1_op2_sel; // @[util.scala:104:23] wire [4:0] out_uop_out_1_rob_idx; // @[util.scala:104:23] wire [3:0] out_uop_out_1_ldq_idx; // @[util.scala:104:23] wire [3:0] out_uop_out_1_stq_idx; // @[util.scala:104:23] wire [1:0] out_uop_out_1_rxq_idx; // @[util.scala:104:23] wire [5:0] out_uop_out_1_pdst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_prs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_prs2; // @[util.scala:104:23] wire [5:0] out_uop_out_1_prs3; // @[util.scala:104:23] wire [3:0] out_uop_out_1_ppred; // @[util.scala:104:23] wire out_uop_out_1_prs1_busy; // @[util.scala:104:23] wire out_uop_out_1_prs2_busy; // @[util.scala:104:23] wire out_uop_out_1_prs3_busy; // @[util.scala:104:23] wire out_uop_out_1_ppred_busy; // @[util.scala:104:23] wire [5:0] out_uop_out_1_stale_pdst; // @[util.scala:104:23] wire out_uop_out_1_exception; // @[util.scala:104:23] wire [63:0] out_uop_out_1_exc_cause; // @[util.scala:104:23] wire [4:0] out_uop_out_1_mem_cmd; // @[util.scala:104:23] wire [1:0] out_uop_out_1_mem_size; // @[util.scala:104:23] wire out_uop_out_1_mem_signed; // @[util.scala:104:23] wire out_uop_out_1_uses_ldq; // @[util.scala:104:23] wire out_uop_out_1_uses_stq; // @[util.scala:104:23] wire out_uop_out_1_is_unique; // @[util.scala:104:23] wire out_uop_out_1_flush_on_commit; // @[util.scala:104:23] wire [2:0] out_uop_out_1_csr_cmd; // @[util.scala:104:23] wire out_uop_out_1_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_ldst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs2; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs3; // @[util.scala:104:23] wire [1:0] out_uop_out_1_dst_rtype; // @[util.scala:104:23] wire [1:0] out_uop_out_1_lrs1_rtype; // @[util.scala:104:23] wire [1:0] out_uop_out_1_lrs2_rtype; // @[util.scala:104:23] wire out_uop_out_1_frs3_en; // @[util.scala:104:23] wire out_uop_out_1_fcn_dw; // @[util.scala:104:23] wire [4:0] out_uop_out_1_fcn_op; // @[util.scala:104:23] wire out_uop_out_1_fp_val; // @[util.scala:104:23] wire [2:0] out_uop_out_1_fp_rm; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_typ; // @[util.scala:104:23] wire out_uop_out_1_xcpt_pf_if; // @[util.scala:104:23] wire out_uop_out_1_xcpt_ae_if; // @[util.scala:104:23] wire out_uop_out_1_xcpt_ma_if; // @[util.scala:104:23] wire out_uop_out_1_bp_debug_if; // @[util.scala:104:23] wire out_uop_out_1_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] out_uop_out_1_debug_fsrc; // @[util.scala:104:23] wire [2:0] out_uop_out_1_debug_tsrc; // @[util.scala:104:23] assign out_uop_out_1_br_mask = _out_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] always @(posedge clock) begin // @[util.scala:458:7] if (main_io_deq_ready) begin // @[util.scala:495:23] out_reg_uop_inst <= _main_io_deq_bits_uop_inst; // @[util.scala:476:22, :477:22] out_reg_uop_debug_inst <= _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22, :477:22] out_reg_uop_is_rvc <= _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22, :477:22] out_reg_uop_debug_pc <= _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_0 <= _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_1 <= _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_2 <= _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_3 <= _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_0 <= _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_1 <= _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_2 <= _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_3 <= _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_4 <= _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_5 <= _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_6 <= _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_7 <= _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_8 <= _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_9 <= _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued <= _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued_partial_agen <= _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued_partial_dgen <= _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p1_speculative_child <= _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p2_speculative_child <= _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p1_bypass_hint <= _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p2_bypass_hint <= _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p3_bypass_hint <= _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_dis_col_sel <= _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22, :477:22] out_reg_uop_br_mask <= _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22, :477:22] out_reg_uop_br_tag <= _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22, :477:22] out_reg_uop_br_type <= _main_io_deq_bits_uop_br_type; // @[util.scala:476:22, :477:22] out_reg_uop_is_sfb <= _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22, :477:22] out_reg_uop_is_fence <= _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22, :477:22] out_reg_uop_is_fencei <= _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22, :477:22] out_reg_uop_is_sfence <= _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22, :477:22] out_reg_uop_is_amo <= _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22, :477:22] out_reg_uop_is_eret <= _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22, :477:22] out_reg_uop_is_sys_pc2epc <= _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22, :477:22] out_reg_uop_is_rocc <= _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22, :477:22] out_reg_uop_is_mov <= _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22, :477:22] out_reg_uop_ftq_idx <= _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_edge_inst <= _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22, :477:22] out_reg_uop_pc_lob <= _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22, :477:22] out_reg_uop_taken <= _main_io_deq_bits_uop_taken; // @[util.scala:476:22, :477:22] out_reg_uop_imm_rename <= _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22, :477:22] out_reg_uop_imm_sel <= _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22, :477:22] out_reg_uop_pimm <= _main_io_deq_bits_uop_pimm; // @[util.scala:476:22, :477:22] out_reg_uop_imm_packed <= _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22, :477:22] out_reg_uop_op1_sel <= _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22, :477:22] out_reg_uop_op2_sel <= _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ldst <= _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_wen <= _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren1 <= _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren2 <= _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren3 <= _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_swap12 <= _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_swap23 <= _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_typeTagIn <= _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_typeTagOut <= _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fromint <= _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_toint <= _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fastpipe <= _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fma <= _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_div <= _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_sqrt <= _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_wflags <= _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_vec <= _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22, :477:22] out_reg_uop_rob_idx <= _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22, :477:22] out_reg_uop_ldq_idx <= _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_stq_idx <= _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_rxq_idx <= _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_pdst <= _main_io_deq_bits_uop_pdst; // @[util.scala:476:22, :477:22] out_reg_uop_prs1 <= _main_io_deq_bits_uop_prs1; // @[util.scala:476:22, :477:22] out_reg_uop_prs2 <= _main_io_deq_bits_uop_prs2; // @[util.scala:476:22, :477:22] out_reg_uop_prs3 <= _main_io_deq_bits_uop_prs3; // @[util.scala:476:22, :477:22] out_reg_uop_ppred <= _main_io_deq_bits_uop_ppred; // @[util.scala:476:22, :477:22] out_reg_uop_prs1_busy <= _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22, :477:22] out_reg_uop_prs2_busy <= _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22, :477:22] out_reg_uop_prs3_busy <= _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22, :477:22] out_reg_uop_ppred_busy <= _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22, :477:22] out_reg_uop_stale_pdst <= _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22, :477:22] out_reg_uop_exception <= _main_io_deq_bits_uop_exception; // @[util.scala:476:22, :477:22] out_reg_uop_exc_cause <= _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22, :477:22] out_reg_uop_mem_cmd <= _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22, :477:22] out_reg_uop_mem_size <= _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22, :477:22] out_reg_uop_mem_signed <= _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22, :477:22] out_reg_uop_uses_ldq <= _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22, :477:22] out_reg_uop_uses_stq <= _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22, :477:22] out_reg_uop_is_unique <= _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22, :477:22] out_reg_uop_flush_on_commit <= _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22, :477:22] out_reg_uop_csr_cmd <= _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22, :477:22] out_reg_uop_ldst_is_rs1 <= _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22, :477:22] out_reg_uop_ldst <= _main_io_deq_bits_uop_ldst; // @[util.scala:476:22, :477:22] out_reg_uop_lrs1 <= _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22, :477:22] out_reg_uop_lrs2 <= _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22, :477:22] out_reg_uop_lrs3 <= _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22, :477:22] out_reg_uop_dst_rtype <= _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_lrs1_rtype <= _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_lrs2_rtype <= _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_frs3_en <= _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22, :477:22] out_reg_uop_fcn_dw <= _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22, :477:22] out_reg_uop_fcn_op <= _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22, :477:22] out_reg_uop_fp_val <= _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22, :477:22] out_reg_uop_fp_rm <= _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22, :477:22] out_reg_uop_fp_typ <= _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_pf_if <= _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_ae_if <= _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_ma_if <= _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22, :477:22] out_reg_uop_bp_debug_if <= _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22, :477:22] out_reg_uop_bp_xcpt_if <= _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22, :477:22] out_reg_uop_debug_fsrc <= _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22, :477:22] out_reg_uop_debug_tsrc <= _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22, :477:22] out_reg_addr <= _main_io_deq_bits_addr; // @[util.scala:476:22, :477:22] out_reg_data <= _main_io_deq_bits_data; // @[util.scala:476:22, :477:22] out_reg_is_hella <= _main_io_deq_bits_is_hella; // @[util.scala:476:22, :477:22] out_reg_tag_match <= _main_io_deq_bits_tag_match; // @[util.scala:476:22, :477:22] out_reg_old_meta_coh_state <= _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22, :477:22] out_reg_old_meta_tag <= _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22, :477:22] out_reg_way_en <= _main_io_deq_bits_way_en; // @[util.scala:476:22, :477:22] out_reg_sdq_id <= _main_io_deq_bits_sdq_id; // @[util.scala:476:22, :477:22] end out_uop_inst <= main_io_deq_ready ? out_uop_out_1_inst : out_uop_out_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_inst <= main_io_deq_ready ? out_uop_out_1_debug_inst : out_uop_out_debug_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_rvc <= main_io_deq_ready ? out_uop_out_1_is_rvc : out_uop_out_is_rvc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_pc <= main_io_deq_ready ? out_uop_out_1_debug_pc : out_uop_out_debug_pc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_0 <= main_io_deq_ready ? out_uop_out_1_iq_type_0 : out_uop_out_iq_type_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_1 <= main_io_deq_ready ? out_uop_out_1_iq_type_1 : out_uop_out_iq_type_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_2 <= main_io_deq_ready ? out_uop_out_1_iq_type_2 : out_uop_out_iq_type_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_3 <= main_io_deq_ready ? out_uop_out_1_iq_type_3 : out_uop_out_iq_type_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_0 <= main_io_deq_ready ? out_uop_out_1_fu_code_0 : out_uop_out_fu_code_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_1 <= main_io_deq_ready ? out_uop_out_1_fu_code_1 : out_uop_out_fu_code_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_2 <= main_io_deq_ready ? out_uop_out_1_fu_code_2 : out_uop_out_fu_code_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_3 <= main_io_deq_ready ? out_uop_out_1_fu_code_3 : out_uop_out_fu_code_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_4 <= main_io_deq_ready ? out_uop_out_1_fu_code_4 : out_uop_out_fu_code_4; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_5 <= main_io_deq_ready ? out_uop_out_1_fu_code_5 : out_uop_out_fu_code_5; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_6 <= main_io_deq_ready ? out_uop_out_1_fu_code_6 : out_uop_out_fu_code_6; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_7 <= main_io_deq_ready ? out_uop_out_1_fu_code_7 : out_uop_out_fu_code_7; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_8 <= main_io_deq_ready ? out_uop_out_1_fu_code_8 : out_uop_out_fu_code_8; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_9 <= main_io_deq_ready ? out_uop_out_1_fu_code_9 : out_uop_out_fu_code_9; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued <= main_io_deq_ready ? out_uop_out_1_iw_issued : out_uop_out_iw_issued; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued_partial_agen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_agen : out_uop_out_iw_issued_partial_agen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued_partial_dgen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_dgen : out_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p1_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p1_speculative_child : out_uop_out_iw_p1_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p2_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p2_speculative_child : out_uop_out_iw_p2_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p1_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p1_bypass_hint : out_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p2_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p2_bypass_hint : out_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p3_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p3_bypass_hint : out_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_dis_col_sel <= main_io_deq_ready ? out_uop_out_1_dis_col_sel : out_uop_out_dis_col_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_mask <= main_io_deq_ready ? out_uop_out_1_br_mask : out_uop_out_br_mask; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_tag <= main_io_deq_ready ? out_uop_out_1_br_tag : out_uop_out_br_tag; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_type <= main_io_deq_ready ? out_uop_out_1_br_type : out_uop_out_br_type; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sfb <= main_io_deq_ready ? out_uop_out_1_is_sfb : out_uop_out_is_sfb; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_fence <= main_io_deq_ready ? out_uop_out_1_is_fence : out_uop_out_is_fence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_fencei <= main_io_deq_ready ? out_uop_out_1_is_fencei : out_uop_out_is_fencei; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sfence <= main_io_deq_ready ? out_uop_out_1_is_sfence : out_uop_out_is_sfence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_amo <= main_io_deq_ready ? out_uop_out_1_is_amo : out_uop_out_is_amo; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_eret <= main_io_deq_ready ? out_uop_out_1_is_eret : out_uop_out_is_eret; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sys_pc2epc <= main_io_deq_ready ? out_uop_out_1_is_sys_pc2epc : out_uop_out_is_sys_pc2epc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_rocc <= main_io_deq_ready ? out_uop_out_1_is_rocc : out_uop_out_is_rocc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_mov <= main_io_deq_ready ? out_uop_out_1_is_mov : out_uop_out_is_mov; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ftq_idx <= main_io_deq_ready ? out_uop_out_1_ftq_idx : out_uop_out_ftq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_edge_inst <= main_io_deq_ready ? out_uop_out_1_edge_inst : out_uop_out_edge_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pc_lob <= main_io_deq_ready ? out_uop_out_1_pc_lob : out_uop_out_pc_lob; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_taken <= main_io_deq_ready ? out_uop_out_1_taken : out_uop_out_taken; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_rename <= main_io_deq_ready ? out_uop_out_1_imm_rename : out_uop_out_imm_rename; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_sel <= main_io_deq_ready ? out_uop_out_1_imm_sel : out_uop_out_imm_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pimm <= main_io_deq_ready ? out_uop_out_1_pimm : out_uop_out_pimm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_packed <= main_io_deq_ready ? out_uop_out_1_imm_packed : out_uop_out_imm_packed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_op1_sel <= main_io_deq_ready ? out_uop_out_1_op1_sel : out_uop_out_op1_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_op2_sel <= main_io_deq_ready ? out_uop_out_1_op2_sel : out_uop_out_op2_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ldst <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ldst : out_uop_out_fp_ctrl_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_wen <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wen : out_uop_out_fp_ctrl_wen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren1 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren1 : out_uop_out_fp_ctrl_ren1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren2 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren2 : out_uop_out_fp_ctrl_ren2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren3 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren3 : out_uop_out_fp_ctrl_ren3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_swap12 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap12 : out_uop_out_fp_ctrl_swap12; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_swap23 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap23 : out_uop_out_fp_ctrl_swap23; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_typeTagIn <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagIn : out_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_typeTagOut <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagOut : out_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fromint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fromint : out_uop_out_fp_ctrl_fromint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_toint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_toint : out_uop_out_fp_ctrl_toint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fastpipe <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fastpipe : out_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fma <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fma : out_uop_out_fp_ctrl_fma; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_div <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_div : out_uop_out_fp_ctrl_div; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_sqrt <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_sqrt : out_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_wflags <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wflags : out_uop_out_fp_ctrl_wflags; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_vec <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_vec : out_uop_out_fp_ctrl_vec; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_rob_idx <= main_io_deq_ready ? out_uop_out_1_rob_idx : out_uop_out_rob_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldq_idx <= main_io_deq_ready ? out_uop_out_1_ldq_idx : out_uop_out_ldq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_stq_idx <= main_io_deq_ready ? out_uop_out_1_stq_idx : out_uop_out_stq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_rxq_idx <= main_io_deq_ready ? out_uop_out_1_rxq_idx : out_uop_out_rxq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pdst <= main_io_deq_ready ? out_uop_out_1_pdst : out_uop_out_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs1 <= main_io_deq_ready ? out_uop_out_1_prs1 : out_uop_out_prs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs2 <= main_io_deq_ready ? out_uop_out_1_prs2 : out_uop_out_prs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs3 <= main_io_deq_ready ? out_uop_out_1_prs3 : out_uop_out_prs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ppred <= main_io_deq_ready ? out_uop_out_1_ppred : out_uop_out_ppred; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs1_busy <= main_io_deq_ready ? out_uop_out_1_prs1_busy : out_uop_out_prs1_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs2_busy <= main_io_deq_ready ? out_uop_out_1_prs2_busy : out_uop_out_prs2_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs3_busy <= main_io_deq_ready ? out_uop_out_1_prs3_busy : out_uop_out_prs3_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ppred_busy <= main_io_deq_ready ? out_uop_out_1_ppred_busy : out_uop_out_ppred_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_stale_pdst <= main_io_deq_ready ? out_uop_out_1_stale_pdst : out_uop_out_stale_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_exception <= main_io_deq_ready ? out_uop_out_1_exception : out_uop_out_exception; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_exc_cause <= main_io_deq_ready ? out_uop_out_1_exc_cause : out_uop_out_exc_cause; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_cmd <= main_io_deq_ready ? out_uop_out_1_mem_cmd : out_uop_out_mem_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_size <= main_io_deq_ready ? out_uop_out_1_mem_size : out_uop_out_mem_size; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_signed <= main_io_deq_ready ? out_uop_out_1_mem_signed : out_uop_out_mem_signed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_uses_ldq <= main_io_deq_ready ? out_uop_out_1_uses_ldq : out_uop_out_uses_ldq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_uses_stq <= main_io_deq_ready ? out_uop_out_1_uses_stq : out_uop_out_uses_stq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_unique <= main_io_deq_ready ? out_uop_out_1_is_unique : out_uop_out_is_unique; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_flush_on_commit <= main_io_deq_ready ? out_uop_out_1_flush_on_commit : out_uop_out_flush_on_commit; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_csr_cmd <= main_io_deq_ready ? out_uop_out_1_csr_cmd : out_uop_out_csr_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldst_is_rs1 <= main_io_deq_ready ? out_uop_out_1_ldst_is_rs1 : out_uop_out_ldst_is_rs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldst <= main_io_deq_ready ? out_uop_out_1_ldst : out_uop_out_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs1 <= main_io_deq_ready ? out_uop_out_1_lrs1 : out_uop_out_lrs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs2 <= main_io_deq_ready ? out_uop_out_1_lrs2 : out_uop_out_lrs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs3 <= main_io_deq_ready ? out_uop_out_1_lrs3 : out_uop_out_lrs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_dst_rtype <= main_io_deq_ready ? out_uop_out_1_dst_rtype : out_uop_out_dst_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs1_rtype <= main_io_deq_ready ? out_uop_out_1_lrs1_rtype : out_uop_out_lrs1_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs2_rtype <= main_io_deq_ready ? out_uop_out_1_lrs2_rtype : out_uop_out_lrs2_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_frs3_en <= main_io_deq_ready ? out_uop_out_1_frs3_en : out_uop_out_frs3_en; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fcn_dw <= main_io_deq_ready ? out_uop_out_1_fcn_dw : out_uop_out_fcn_dw; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fcn_op <= main_io_deq_ready ? out_uop_out_1_fcn_op : out_uop_out_fcn_op; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_val <= main_io_deq_ready ? out_uop_out_1_fp_val : out_uop_out_fp_val; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_rm <= main_io_deq_ready ? out_uop_out_1_fp_rm : out_uop_out_fp_rm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_typ <= main_io_deq_ready ? out_uop_out_1_fp_typ : out_uop_out_fp_typ; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_pf_if <= main_io_deq_ready ? out_uop_out_1_xcpt_pf_if : out_uop_out_xcpt_pf_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_ae_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ae_if : out_uop_out_xcpt_ae_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_ma_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ma_if : out_uop_out_xcpt_ma_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_bp_debug_if <= main_io_deq_ready ? out_uop_out_1_bp_debug_if : out_uop_out_bp_debug_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_bp_xcpt_if <= main_io_deq_ready ? out_uop_out_1_bp_xcpt_if : out_uop_out_bp_xcpt_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_fsrc <= main_io_deq_ready ? out_uop_out_1_debug_fsrc : out_uop_out_debug_fsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_tsrc <= main_io_deq_ready ? out_uop_out_1_debug_tsrc : out_uop_out_debug_tsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] if (reset) // @[util.scala:458:7] out_valid <= 1'h0; // @[util.scala:478:28] else // @[util.scala:458:7] out_valid <= main_io_deq_ready ? _out_valid_T_15 : _out_valid_T_7; // @[util.scala:478:28, :492:{15,80}, :495:{23,38}, :496:{17,103}] always @(posedge) BranchKillableQueue main ( // @[util.scala:476:22] .clock (clock), .reset (reset), .io_enq_ready (io_enq_ready_0), .io_enq_valid (io_enq_valid_0), // @[util.scala:458:7] .io_enq_bits_uop_inst (io_enq_bits_uop_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_inst (io_enq_bits_uop_debug_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_is_rvc (io_enq_bits_uop_is_rvc_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_pc (io_enq_bits_uop_debug_pc_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_0 (io_enq_bits_uop_iq_type_0_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_1 (io_enq_bits_uop_iq_type_1_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_2 (io_enq_bits_uop_iq_type_2_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_3 (io_enq_bits_uop_iq_type_3_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_0 (io_enq_bits_uop_fu_code_0_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_1 (io_enq_bits_uop_fu_code_1_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_2 (io_enq_bits_uop_fu_code_2_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_3 (io_enq_bits_uop_fu_code_3_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_4 (io_enq_bits_uop_fu_code_4_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_5 (io_enq_bits_uop_fu_code_5_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_6 (io_enq_bits_uop_fu_code_6_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_7 (io_enq_bits_uop_fu_code_7_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_8 (io_enq_bits_uop_fu_code_8_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_9 (io_enq_bits_uop_fu_code_9_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued (io_enq_bits_uop_iw_issued_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued_partial_agen (io_enq_bits_uop_iw_issued_partial_agen_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued_partial_dgen (io_enq_bits_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p1_speculative_child (io_enq_bits_uop_iw_p1_speculative_child_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p2_speculative_child (io_enq_bits_uop_iw_p2_speculative_child_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p1_bypass_hint (io_enq_bits_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p2_bypass_hint (io_enq_bits_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p3_bypass_hint (io_enq_bits_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_dis_col_sel (io_enq_bits_uop_dis_col_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_br_mask (io_enq_bits_uop_br_mask_0), // @[util.scala:458:7] .io_enq_bits_uop_br_tag (io_enq_bits_uop_br_tag_0), // @[util.scala:458:7] .io_enq_bits_uop_br_type (io_enq_bits_uop_br_type_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sfb (io_enq_bits_uop_is_sfb_0), // @[util.scala:458:7] .io_enq_bits_uop_is_fence (io_enq_bits_uop_is_fence_0), // @[util.scala:458:7] .io_enq_bits_uop_is_fencei (io_enq_bits_uop_is_fencei_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sfence (io_enq_bits_uop_is_sfence_0), // @[util.scala:458:7] .io_enq_bits_uop_is_amo (io_enq_bits_uop_is_amo_0), // @[util.scala:458:7] .io_enq_bits_uop_is_eret (io_enq_bits_uop_is_eret_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sys_pc2epc (io_enq_bits_uop_is_sys_pc2epc_0), // @[util.scala:458:7] .io_enq_bits_uop_is_rocc (io_enq_bits_uop_is_rocc_0), // @[util.scala:458:7] .io_enq_bits_uop_is_mov (io_enq_bits_uop_is_mov_0), // @[util.scala:458:7] .io_enq_bits_uop_ftq_idx (io_enq_bits_uop_ftq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_edge_inst (io_enq_bits_uop_edge_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_pc_lob (io_enq_bits_uop_pc_lob_0), // @[util.scala:458:7] .io_enq_bits_uop_taken (io_enq_bits_uop_taken_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_rename (io_enq_bits_uop_imm_rename_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_sel (io_enq_bits_uop_imm_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_pimm (io_enq_bits_uop_pimm_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_packed (io_enq_bits_uop_imm_packed_0), // @[util.scala:458:7] .io_enq_bits_uop_op1_sel (io_enq_bits_uop_op1_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_op2_sel (io_enq_bits_uop_op2_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ldst (io_enq_bits_uop_fp_ctrl_ldst_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_wen (io_enq_bits_uop_fp_ctrl_wen_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren1 (io_enq_bits_uop_fp_ctrl_ren1_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren2 (io_enq_bits_uop_fp_ctrl_ren2_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren3 (io_enq_bits_uop_fp_ctrl_ren3_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_swap12 (io_enq_bits_uop_fp_ctrl_swap12_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_swap23 (io_enq_bits_uop_fp_ctrl_swap23_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_typeTagIn (io_enq_bits_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_typeTagOut (io_enq_bits_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fromint (io_enq_bits_uop_fp_ctrl_fromint_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_toint (io_enq_bits_uop_fp_ctrl_toint_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fastpipe (io_enq_bits_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fma (io_enq_bits_uop_fp_ctrl_fma_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_div (io_enq_bits_uop_fp_ctrl_div_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_sqrt (io_enq_bits_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_wflags (io_enq_bits_uop_fp_ctrl_wflags_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_vec (io_enq_bits_uop_fp_ctrl_vec_0), // @[util.scala:458:7] .io_enq_bits_uop_rob_idx (io_enq_bits_uop_rob_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_ldq_idx (io_enq_bits_uop_ldq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_stq_idx (io_enq_bits_uop_stq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_rxq_idx (io_enq_bits_uop_rxq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_pdst (io_enq_bits_uop_pdst_0), // @[util.scala:458:7] .io_enq_bits_uop_prs1 (io_enq_bits_uop_prs1_0), // @[util.scala:458:7] .io_enq_bits_uop_prs2 (io_enq_bits_uop_prs2_0), // @[util.scala:458:7] .io_enq_bits_uop_prs3 (io_enq_bits_uop_prs3_0), // @[util.scala:458:7] .io_enq_bits_uop_ppred (io_enq_bits_uop_ppred_0), // @[util.scala:458:7] .io_enq_bits_uop_prs1_busy (io_enq_bits_uop_prs1_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_prs2_busy (io_enq_bits_uop_prs2_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_prs3_busy (io_enq_bits_uop_prs3_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_ppred_busy (io_enq_bits_uop_ppred_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_stale_pdst (io_enq_bits_uop_stale_pdst_0), // @[util.scala:458:7] .io_enq_bits_uop_exception (io_enq_bits_uop_exception_0), // @[util.scala:458:7] .io_enq_bits_uop_exc_cause (io_enq_bits_uop_exc_cause_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_cmd (io_enq_bits_uop_mem_cmd_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_size (io_enq_bits_uop_mem_size_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_signed (io_enq_bits_uop_mem_signed_0), // @[util.scala:458:7] .io_enq_bits_uop_uses_ldq (io_enq_bits_uop_uses_ldq_0), // @[util.scala:458:7] .io_enq_bits_uop_uses_stq (io_enq_bits_uop_uses_stq_0), // @[util.scala:458:7] .io_enq_bits_uop_is_unique (io_enq_bits_uop_is_unique_0), // @[util.scala:458:7] .io_enq_bits_uop_flush_on_commit (io_enq_bits_uop_flush_on_commit_0), // @[util.scala:458:7] .io_enq_bits_uop_csr_cmd (io_enq_bits_uop_csr_cmd_0), // @[util.scala:458:7] .io_enq_bits_uop_ldst_is_rs1 (io_enq_bits_uop_ldst_is_rs1_0), // @[util.scala:458:7] .io_enq_bits_uop_ldst (io_enq_bits_uop_ldst_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs1 (io_enq_bits_uop_lrs1_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs2 (io_enq_bits_uop_lrs2_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs3 (io_enq_bits_uop_lrs3_0), // @[util.scala:458:7] .io_enq_bits_uop_dst_rtype (io_enq_bits_uop_dst_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs1_rtype (io_enq_bits_uop_lrs1_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs2_rtype (io_enq_bits_uop_lrs2_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_frs3_en (io_enq_bits_uop_frs3_en_0), // @[util.scala:458:7] .io_enq_bits_uop_fcn_dw (io_enq_bits_uop_fcn_dw_0), // @[util.scala:458:7] .io_enq_bits_uop_fcn_op (io_enq_bits_uop_fcn_op_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_val (io_enq_bits_uop_fp_val_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_rm (io_enq_bits_uop_fp_rm_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_typ (io_enq_bits_uop_fp_typ_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_pf_if (io_enq_bits_uop_xcpt_pf_if_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_ae_if (io_enq_bits_uop_xcpt_ae_if_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_ma_if (io_enq_bits_uop_xcpt_ma_if_0), // @[util.scala:458:7] .io_enq_bits_uop_bp_debug_if (io_enq_bits_uop_bp_debug_if_0), // @[util.scala:458:7] .io_enq_bits_uop_bp_xcpt_if (io_enq_bits_uop_bp_xcpt_if_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_fsrc (io_enq_bits_uop_debug_fsrc_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_tsrc (io_enq_bits_uop_debug_tsrc_0), // @[util.scala:458:7] .io_enq_bits_addr (io_enq_bits_addr_0), // @[util.scala:458:7] .io_enq_bits_data (io_enq_bits_data_0), // @[util.scala:458:7] .io_enq_bits_is_hella (io_enq_bits_is_hella_0), // @[util.scala:458:7] .io_enq_bits_tag_match (io_enq_bits_tag_match_0), // @[util.scala:458:7] .io_enq_bits_old_meta_coh_state (io_enq_bits_old_meta_coh_state_0), // @[util.scala:458:7] .io_enq_bits_old_meta_tag (io_enq_bits_old_meta_tag_0), // @[util.scala:458:7] .io_enq_bits_way_en (io_enq_bits_way_en_0), // @[util.scala:458:7] .io_enq_bits_sdq_id (io_enq_bits_sdq_id_0), // @[util.scala:458:7] .io_deq_ready (main_io_deq_ready), // @[util.scala:495:23] .io_deq_valid (_out_valid_T_12), .io_deq_bits_uop_inst (_main_io_deq_bits_uop_inst), .io_deq_bits_uop_debug_inst (_main_io_deq_bits_uop_debug_inst), .io_deq_bits_uop_is_rvc (_main_io_deq_bits_uop_is_rvc), .io_deq_bits_uop_debug_pc (_main_io_deq_bits_uop_debug_pc), .io_deq_bits_uop_iq_type_0 (_main_io_deq_bits_uop_iq_type_0), .io_deq_bits_uop_iq_type_1 (_main_io_deq_bits_uop_iq_type_1), .io_deq_bits_uop_iq_type_2 (_main_io_deq_bits_uop_iq_type_2), .io_deq_bits_uop_iq_type_3 (_main_io_deq_bits_uop_iq_type_3), .io_deq_bits_uop_fu_code_0 (_main_io_deq_bits_uop_fu_code_0), .io_deq_bits_uop_fu_code_1 (_main_io_deq_bits_uop_fu_code_1), .io_deq_bits_uop_fu_code_2 (_main_io_deq_bits_uop_fu_code_2), .io_deq_bits_uop_fu_code_3 (_main_io_deq_bits_uop_fu_code_3), .io_deq_bits_uop_fu_code_4 (_main_io_deq_bits_uop_fu_code_4), .io_deq_bits_uop_fu_code_5 (_main_io_deq_bits_uop_fu_code_5), .io_deq_bits_uop_fu_code_6 (_main_io_deq_bits_uop_fu_code_6), .io_deq_bits_uop_fu_code_7 (_main_io_deq_bits_uop_fu_code_7), .io_deq_bits_uop_fu_code_8 (_main_io_deq_bits_uop_fu_code_8), .io_deq_bits_uop_fu_code_9 (_main_io_deq_bits_uop_fu_code_9), .io_deq_bits_uop_iw_issued (_main_io_deq_bits_uop_iw_issued), .io_deq_bits_uop_iw_issued_partial_agen (_main_io_deq_bits_uop_iw_issued_partial_agen), .io_deq_bits_uop_iw_issued_partial_dgen (_main_io_deq_bits_uop_iw_issued_partial_dgen), .io_deq_bits_uop_iw_p1_speculative_child (_main_io_deq_bits_uop_iw_p1_speculative_child), .io_deq_bits_uop_iw_p2_speculative_child (_main_io_deq_bits_uop_iw_p2_speculative_child), .io_deq_bits_uop_iw_p1_bypass_hint (_main_io_deq_bits_uop_iw_p1_bypass_hint), .io_deq_bits_uop_iw_p2_bypass_hint (_main_io_deq_bits_uop_iw_p2_bypass_hint), .io_deq_bits_uop_iw_p3_bypass_hint (_main_io_deq_bits_uop_iw_p3_bypass_hint), .io_deq_bits_uop_dis_col_sel (_main_io_deq_bits_uop_dis_col_sel), .io_deq_bits_uop_br_mask (_main_io_deq_bits_uop_br_mask), .io_deq_bits_uop_br_tag (_main_io_deq_bits_uop_br_tag), .io_deq_bits_uop_br_type (_main_io_deq_bits_uop_br_type), .io_deq_bits_uop_is_sfb (_main_io_deq_bits_uop_is_sfb), .io_deq_bits_uop_is_fence (_main_io_deq_bits_uop_is_fence), .io_deq_bits_uop_is_fencei (_main_io_deq_bits_uop_is_fencei), .io_deq_bits_uop_is_sfence (_main_io_deq_bits_uop_is_sfence), .io_deq_bits_uop_is_amo (_main_io_deq_bits_uop_is_amo), .io_deq_bits_uop_is_eret (_main_io_deq_bits_uop_is_eret), .io_deq_bits_uop_is_sys_pc2epc (_main_io_deq_bits_uop_is_sys_pc2epc), .io_deq_bits_uop_is_rocc (_main_io_deq_bits_uop_is_rocc), .io_deq_bits_uop_is_mov (_main_io_deq_bits_uop_is_mov), .io_deq_bits_uop_ftq_idx (_main_io_deq_bits_uop_ftq_idx), .io_deq_bits_uop_edge_inst (_main_io_deq_bits_uop_edge_inst), .io_deq_bits_uop_pc_lob (_main_io_deq_bits_uop_pc_lob), .io_deq_bits_uop_taken (_main_io_deq_bits_uop_taken), .io_deq_bits_uop_imm_rename (_main_io_deq_bits_uop_imm_rename), .io_deq_bits_uop_imm_sel (_main_io_deq_bits_uop_imm_sel), .io_deq_bits_uop_pimm (_main_io_deq_bits_uop_pimm), .io_deq_bits_uop_imm_packed (_main_io_deq_bits_uop_imm_packed), .io_deq_bits_uop_op1_sel (_main_io_deq_bits_uop_op1_sel), .io_deq_bits_uop_op2_sel (_main_io_deq_bits_uop_op2_sel), .io_deq_bits_uop_fp_ctrl_ldst (_main_io_deq_bits_uop_fp_ctrl_ldst), .io_deq_bits_uop_fp_ctrl_wen (_main_io_deq_bits_uop_fp_ctrl_wen), .io_deq_bits_uop_fp_ctrl_ren1 (_main_io_deq_bits_uop_fp_ctrl_ren1), .io_deq_bits_uop_fp_ctrl_ren2 (_main_io_deq_bits_uop_fp_ctrl_ren2), .io_deq_bits_uop_fp_ctrl_ren3 (_main_io_deq_bits_uop_fp_ctrl_ren3), .io_deq_bits_uop_fp_ctrl_swap12 (_main_io_deq_bits_uop_fp_ctrl_swap12), .io_deq_bits_uop_fp_ctrl_swap23 (_main_io_deq_bits_uop_fp_ctrl_swap23), .io_deq_bits_uop_fp_ctrl_typeTagIn (_main_io_deq_bits_uop_fp_ctrl_typeTagIn), .io_deq_bits_uop_fp_ctrl_typeTagOut (_main_io_deq_bits_uop_fp_ctrl_typeTagOut), .io_deq_bits_uop_fp_ctrl_fromint (_main_io_deq_bits_uop_fp_ctrl_fromint), .io_deq_bits_uop_fp_ctrl_toint (_main_io_deq_bits_uop_fp_ctrl_toint), .io_deq_bits_uop_fp_ctrl_fastpipe (_main_io_deq_bits_uop_fp_ctrl_fastpipe), .io_deq_bits_uop_fp_ctrl_fma (_main_io_deq_bits_uop_fp_ctrl_fma), .io_deq_bits_uop_fp_ctrl_div (_main_io_deq_bits_uop_fp_ctrl_div), .io_deq_bits_uop_fp_ctrl_sqrt (_main_io_deq_bits_uop_fp_ctrl_sqrt), .io_deq_bits_uop_fp_ctrl_wflags (_main_io_deq_bits_uop_fp_ctrl_wflags), .io_deq_bits_uop_fp_ctrl_vec (_main_io_deq_bits_uop_fp_ctrl_vec), .io_deq_bits_uop_rob_idx (_main_io_deq_bits_uop_rob_idx), .io_deq_bits_uop_ldq_idx (_main_io_deq_bits_uop_ldq_idx), .io_deq_bits_uop_stq_idx (_main_io_deq_bits_uop_stq_idx), .io_deq_bits_uop_rxq_idx (_main_io_deq_bits_uop_rxq_idx), .io_deq_bits_uop_pdst (_main_io_deq_bits_uop_pdst), .io_deq_bits_uop_prs1 (_main_io_deq_bits_uop_prs1), .io_deq_bits_uop_prs2 (_main_io_deq_bits_uop_prs2), .io_deq_bits_uop_prs3 (_main_io_deq_bits_uop_prs3), .io_deq_bits_uop_ppred (_main_io_deq_bits_uop_ppred), .io_deq_bits_uop_prs1_busy (_main_io_deq_bits_uop_prs1_busy), .io_deq_bits_uop_prs2_busy (_main_io_deq_bits_uop_prs2_busy), .io_deq_bits_uop_prs3_busy (_main_io_deq_bits_uop_prs3_busy), .io_deq_bits_uop_ppred_busy (_main_io_deq_bits_uop_ppred_busy), .io_deq_bits_uop_stale_pdst (_main_io_deq_bits_uop_stale_pdst), .io_deq_bits_uop_exception (_main_io_deq_bits_uop_exception), .io_deq_bits_uop_exc_cause (_main_io_deq_bits_uop_exc_cause), .io_deq_bits_uop_mem_cmd (_main_io_deq_bits_uop_mem_cmd), .io_deq_bits_uop_mem_size (_main_io_deq_bits_uop_mem_size), .io_deq_bits_uop_mem_signed (_main_io_deq_bits_uop_mem_signed), .io_deq_bits_uop_uses_ldq (_main_io_deq_bits_uop_uses_ldq), .io_deq_bits_uop_uses_stq (_main_io_deq_bits_uop_uses_stq), .io_deq_bits_uop_is_unique (_main_io_deq_bits_uop_is_unique), .io_deq_bits_uop_flush_on_commit (_main_io_deq_bits_uop_flush_on_commit), .io_deq_bits_uop_csr_cmd (_main_io_deq_bits_uop_csr_cmd), .io_deq_bits_uop_ldst_is_rs1 (_main_io_deq_bits_uop_ldst_is_rs1), .io_deq_bits_uop_ldst (_main_io_deq_bits_uop_ldst), .io_deq_bits_uop_lrs1 (_main_io_deq_bits_uop_lrs1), .io_deq_bits_uop_lrs2 (_main_io_deq_bits_uop_lrs2), .io_deq_bits_uop_lrs3 (_main_io_deq_bits_uop_lrs3), .io_deq_bits_uop_dst_rtype (_main_io_deq_bits_uop_dst_rtype), .io_deq_bits_uop_lrs1_rtype (_main_io_deq_bits_uop_lrs1_rtype), .io_deq_bits_uop_lrs2_rtype (_main_io_deq_bits_uop_lrs2_rtype), .io_deq_bits_uop_frs3_en (_main_io_deq_bits_uop_frs3_en), .io_deq_bits_uop_fcn_dw (_main_io_deq_bits_uop_fcn_dw), .io_deq_bits_uop_fcn_op (_main_io_deq_bits_uop_fcn_op), .io_deq_bits_uop_fp_val (_main_io_deq_bits_uop_fp_val), .io_deq_bits_uop_fp_rm (_main_io_deq_bits_uop_fp_rm), .io_deq_bits_uop_fp_typ (_main_io_deq_bits_uop_fp_typ), .io_deq_bits_uop_xcpt_pf_if (_main_io_deq_bits_uop_xcpt_pf_if), .io_deq_bits_uop_xcpt_ae_if (_main_io_deq_bits_uop_xcpt_ae_if), .io_deq_bits_uop_xcpt_ma_if (_main_io_deq_bits_uop_xcpt_ma_if), .io_deq_bits_uop_bp_debug_if (_main_io_deq_bits_uop_bp_debug_if), .io_deq_bits_uop_bp_xcpt_if (_main_io_deq_bits_uop_bp_xcpt_if), .io_deq_bits_uop_debug_fsrc (_main_io_deq_bits_uop_debug_fsrc), .io_deq_bits_uop_debug_tsrc (_main_io_deq_bits_uop_debug_tsrc), .io_deq_bits_addr (_main_io_deq_bits_addr), .io_deq_bits_data (_main_io_deq_bits_data), .io_deq_bits_is_hella (_main_io_deq_bits_is_hella), .io_deq_bits_tag_match (_main_io_deq_bits_tag_match), .io_deq_bits_old_meta_coh_state (_main_io_deq_bits_old_meta_coh_state), .io_deq_bits_old_meta_tag (_main_io_deq_bits_old_meta_tag), .io_deq_bits_way_en (_main_io_deq_bits_way_en), .io_deq_bits_sdq_id (_main_io_deq_bits_sdq_id), .io_empty (_main_io_empty), .io_count (_main_io_count) ); // @[util.scala:476:22] assign out_uop_out_1_inst = _main_io_deq_bits_uop_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_inst = _main_io_deq_bits_uop_debug_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_rvc = _main_io_deq_bits_uop_is_rvc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_pc = _main_io_deq_bits_uop_debug_pc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_0 = _main_io_deq_bits_uop_iq_type_0; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_1 = _main_io_deq_bits_uop_iq_type_1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_2 = _main_io_deq_bits_uop_iq_type_2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_3 = _main_io_deq_bits_uop_iq_type_3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_0 = _main_io_deq_bits_uop_fu_code_0; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_1 = _main_io_deq_bits_uop_fu_code_1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_2 = _main_io_deq_bits_uop_fu_code_2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_3 = _main_io_deq_bits_uop_fu_code_3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_4 = _main_io_deq_bits_uop_fu_code_4; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_5 = _main_io_deq_bits_uop_fu_code_5; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_6 = _main_io_deq_bits_uop_fu_code_6; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_7 = _main_io_deq_bits_uop_fu_code_7; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_8 = _main_io_deq_bits_uop_fu_code_8; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_9 = _main_io_deq_bits_uop_fu_code_9; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued = _main_io_deq_bits_uop_iw_issued; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued_partial_agen = _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued_partial_dgen = _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p1_speculative_child = _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p2_speculative_child = _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p1_bypass_hint = _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p2_bypass_hint = _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p3_bypass_hint = _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_dis_col_sel = _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_br_tag = _main_io_deq_bits_uop_br_tag; // @[util.scala:104:23, :476:22] assign out_uop_out_1_br_type = _main_io_deq_bits_uop_br_type; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sfb = _main_io_deq_bits_uop_is_sfb; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_fence = _main_io_deq_bits_uop_is_fence; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_fencei = _main_io_deq_bits_uop_is_fencei; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sfence = _main_io_deq_bits_uop_is_sfence; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_amo = _main_io_deq_bits_uop_is_amo; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_eret = _main_io_deq_bits_uop_is_eret; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sys_pc2epc = _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_rocc = _main_io_deq_bits_uop_is_rocc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_mov = _main_io_deq_bits_uop_is_mov; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ftq_idx = _main_io_deq_bits_uop_ftq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_edge_inst = _main_io_deq_bits_uop_edge_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pc_lob = _main_io_deq_bits_uop_pc_lob; // @[util.scala:104:23, :476:22] assign out_uop_out_1_taken = _main_io_deq_bits_uop_taken; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_rename = _main_io_deq_bits_uop_imm_rename; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_sel = _main_io_deq_bits_uop_imm_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pimm = _main_io_deq_bits_uop_pimm; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_packed = _main_io_deq_bits_uop_imm_packed; // @[util.scala:104:23, :476:22] assign out_uop_out_1_op1_sel = _main_io_deq_bits_uop_op1_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_op2_sel = _main_io_deq_bits_uop_op2_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ldst = _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_wen = _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren1 = _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren2 = _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren3 = _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_swap12 = _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_swap23 = _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_typeTagIn = _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_typeTagOut = _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fromint = _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_toint = _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fastpipe = _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fma = _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_div = _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_sqrt = _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_wflags = _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_vec = _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:104:23, :476:22] assign out_uop_out_1_rob_idx = _main_io_deq_bits_uop_rob_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldq_idx = _main_io_deq_bits_uop_ldq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_stq_idx = _main_io_deq_bits_uop_stq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_rxq_idx = _main_io_deq_bits_uop_rxq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pdst = _main_io_deq_bits_uop_pdst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs1 = _main_io_deq_bits_uop_prs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs2 = _main_io_deq_bits_uop_prs2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs3 = _main_io_deq_bits_uop_prs3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ppred = _main_io_deq_bits_uop_ppred; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs1_busy = _main_io_deq_bits_uop_prs1_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs2_busy = _main_io_deq_bits_uop_prs2_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs3_busy = _main_io_deq_bits_uop_prs3_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ppred_busy = _main_io_deq_bits_uop_ppred_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_stale_pdst = _main_io_deq_bits_uop_stale_pdst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_exception = _main_io_deq_bits_uop_exception; // @[util.scala:104:23, :476:22] assign out_uop_out_1_exc_cause = _main_io_deq_bits_uop_exc_cause; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_cmd = _main_io_deq_bits_uop_mem_cmd; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_size = _main_io_deq_bits_uop_mem_size; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_signed = _main_io_deq_bits_uop_mem_signed; // @[util.scala:104:23, :476:22] assign out_uop_out_1_uses_ldq = _main_io_deq_bits_uop_uses_ldq; // @[util.scala:104:23, :476:22] assign out_uop_out_1_uses_stq = _main_io_deq_bits_uop_uses_stq; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_unique = _main_io_deq_bits_uop_is_unique; // @[util.scala:104:23, :476:22] assign out_uop_out_1_flush_on_commit = _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:104:23, :476:22] assign out_uop_out_1_csr_cmd = _main_io_deq_bits_uop_csr_cmd; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldst_is_rs1 = _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldst = _main_io_deq_bits_uop_ldst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs1 = _main_io_deq_bits_uop_lrs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs2 = _main_io_deq_bits_uop_lrs2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs3 = _main_io_deq_bits_uop_lrs3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_dst_rtype = _main_io_deq_bits_uop_dst_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs1_rtype = _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs2_rtype = _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_frs3_en = _main_io_deq_bits_uop_frs3_en; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fcn_dw = _main_io_deq_bits_uop_fcn_dw; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fcn_op = _main_io_deq_bits_uop_fcn_op; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_val = _main_io_deq_bits_uop_fp_val; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_rm = _main_io_deq_bits_uop_fp_rm; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_typ = _main_io_deq_bits_uop_fp_typ; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_pf_if = _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_ae_if = _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_ma_if = _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_bp_debug_if = _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_bp_xcpt_if = _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_fsrc = _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_tsrc = _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:104:23, :476:22] assign _out_uop_out_br_mask_T_3 = _main_io_deq_bits_uop_br_mask; // @[util.scala:93:25, :476:22] assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7] assign io_empty = io_empty_0; // @[util.scala:458:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_49 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_49( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_acd_router_4ClockSinkDomain : output auto : { routers_debug_out : { va_stall : UInt[5], sa_stall : UInt[5]}, routers_egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}, flip routers_ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, flip routers_ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip routers_dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_4 connect routers.clock, childClock connect routers.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0 connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1 connect routers.auto.dest_nodes_in_2, auto.routers_dest_nodes_in_2 connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit connect routers.auto.ingress_nodes_in_0, auto.routers_ingress_nodes_in_0 connect routers.auto.ingress_nodes_in_1, auto.routers_ingress_nodes_in_1 connect auto.routers_egress_nodes_out.flit.bits, routers.auto.egress_nodes_out.flit.bits connect auto.routers_egress_nodes_out.flit.valid, routers.auto.egress_nodes_out.flit.valid connect routers.auto.egress_nodes_out.flit.ready, auto.routers_egress_nodes_out.flit.ready connect auto.routers_debug_out, routers.auto.debug_out connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset	module TLSplitACDxBENoC_acd_router_4ClockSinkDomain( // @[ClockDomain.scala:14:9] output [1:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [144:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [144:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_4 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3), .auto_debug_out_va_stall_4 (auto_routers_debug_out_va_stall_4), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3), .auto_debug_out_sa_stall_4 (auto_routers_debug_out_sa_stall_4), .auto_egress_nodes_out_flit_ready (auto_routers_egress_nodes_out_flit_ready), .auto_egress_nodes_out_flit_valid (auto_routers_egress_nodes_out_flit_valid), .auto_egress_nodes_out_flit_bits_head (auto_routers_egress_nodes_out_flit_bits_head), .auto_egress_nodes_out_flit_bits_tail (auto_routers_egress_nodes_out_flit_bits_tail), .auto_egress_nodes_out_flit_bits_payload (auto_routers_egress_nodes_out_flit_bits_payload), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid), .auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head), .auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail), .auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload), .auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id), .auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return), .auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free), .auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid), .auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head), .auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail), .auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload), .auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id), .auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return), .auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free), .auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid), .auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head), .auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail), .auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload), .auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id), .auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return), .auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free), .auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid), .auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head), .auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail), .auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload), .auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return), .auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free), .auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid), .auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head), .auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail), .auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload), .auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return), .auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free), .auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid), .auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head), .auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail), .auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload), .auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return), .auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SourceB : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset remain : UInt<1>, clock, reset, UInt<1>(0h0) wire remain_set : UInt<1> connect remain_set, UInt<1>(0h0) wire remain_clr : UInt<1> connect remain_clr, UInt<1>(0h0) node _remain_T = or(remain, remain_set) node _remain_T_1 = not(remain_clr) node _remain_T_2 = and(_remain_T, _remain_T_1) connect remain, _remain_T_2 node busy = orr(remain) node todo = mux(busy, remain, io.req.bits.clients) node _next_T = bits(todo, 0, 0) node _next_T_1 = shl(_next_T, 1) node _next_T_2 = not(_next_T_1) node next = and(_next_T_2, todo) node _T = eq(io.req.valid, UInt<1>(0h0)) node _T_1 = neq(io.req.bits.clients, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceB.scala:59 assert (!io.req.valid \|\| io.req.bits.clients =/= 0.U)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _T_6 = and(io.req.ready, io.req.valid) when _T_6 : connect remain_set, io.req.bits.clients wire b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect io.b, b node _b_valid_T = or(busy, io.req.valid) connect b.valid, _b_valid_T node _T_7 = and(b.ready, b.valid) when _T_7 : connect remain_clr, next node _T_8 = eq(b.ready, UInt<1>(0h0)) node _T_9 = and(b.valid, _T_8) node _tag_T = eq(busy, UInt<1>(0h0)) node _tag_T_1 = and(io.req.ready, io.req.valid) reg tag_r : UInt<13>, clock when _tag_T_1 : connect tag_r, io.req.bits.tag node tag = mux(_tag_T, io.req.bits.tag, tag_r) node _set_T = eq(busy, UInt<1>(0h0)) node _set_T_1 = and(io.req.ready, io.req.valid) reg set_r : UInt<10>, clock when _set_T_1 : connect set_r, io.req.bits.set node set = mux(_set_T, io.req.bits.set, set_r) node _param_T = eq(busy, UInt<1>(0h0)) node _param_T_1 = and(io.req.ready, io.req.valid) reg param_r : UInt<3>, clock when _param_T_1 : connect param_r, io.req.bits.param node param = mux(_param_T, io.req.bits.param, param_r) connect b.bits.opcode, UInt<3>(0h6) connect b.bits.param, param connect b.bits.size, UInt<3>(0h6) node _b_bits_source_T = bits(next, 0, 0) connect b.bits.source, UInt<6>(0h20) node b_bits_address_base_y = or(tag, UInt<13>(0h0)) node _b_bits_address_base_T = shr(b_bits_address_base_y, 13) node _b_bits_address_base_T_1 = eq(_b_bits_address_base_T, UInt<1>(0h0)) node _b_bits_address_base_T_2 = asUInt(reset) node _b_bits_address_base_T_3 = eq(_b_bits_address_base_T_2, UInt<1>(0h0)) when _b_bits_address_base_T_3 : node _b_bits_address_base_T_4 = eq(_b_bits_address_base_T_1, UInt<1>(0h0)) when _b_bits_address_base_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf assert(clock, _b_bits_address_base_T_1, UInt<1>(0h1), "") : b_bits_address_base_assert node _b_bits_address_base_T_5 = bits(b_bits_address_base_y, 12, 0) node b_bits_address_base_y_1 = or(set, UInt<10>(0h0)) node _b_bits_address_base_T_6 = shr(b_bits_address_base_y_1, 10) node _b_bits_address_base_T_7 = eq(_b_bits_address_base_T_6, UInt<1>(0h0)) node _b_bits_address_base_T_8 = asUInt(reset) node _b_bits_address_base_T_9 = eq(_b_bits_address_base_T_8, UInt<1>(0h0)) when _b_bits_address_base_T_9 : node _b_bits_address_base_T_10 = eq(_b_bits_address_base_T_7, UInt<1>(0h0)) when _b_bits_address_base_T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_1 assert(clock, _b_bits_address_base_T_7, UInt<1>(0h1), "") : b_bits_address_base_assert_1 node _b_bits_address_base_T_11 = bits(b_bits_address_base_y_1, 9, 0) node b_bits_address_base_y_2 = or(UInt<1>(0h0), UInt<6>(0h0)) node _b_bits_address_base_T_12 = shr(b_bits_address_base_y_2, 6) node _b_bits_address_base_T_13 = eq(_b_bits_address_base_T_12, UInt<1>(0h0)) node _b_bits_address_base_T_14 = asUInt(reset) node _b_bits_address_base_T_15 = eq(_b_bits_address_base_T_14, UInt<1>(0h0)) when _b_bits_address_base_T_15 : node _b_bits_address_base_T_16 = eq(_b_bits_address_base_T_13, UInt<1>(0h0)) when _b_bits_address_base_T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_2 assert(clock, _b_bits_address_base_T_13, UInt<1>(0h1), "") : b_bits_address_base_assert_2 node _b_bits_address_base_T_17 = bits(b_bits_address_base_y_2, 5, 0) node b_bits_address_base_hi = cat(_b_bits_address_base_T_5, _b_bits_address_base_T_11) node b_bits_address_base = cat(b_bits_address_base_hi, _b_bits_address_base_T_17) node _b_bits_address_T = bits(b_bits_address_base, 0, 0) node _b_bits_address_T_1 = bits(b_bits_address_base, 1, 1) node _b_bits_address_T_2 = bits(b_bits_address_base, 2, 2) node _b_bits_address_T_3 = bits(b_bits_address_base, 3, 3) node _b_bits_address_T_4 = bits(b_bits_address_base, 4, 4) node _b_bits_address_T_5 = bits(b_bits_address_base, 5, 5) node _b_bits_address_T_6 = bits(b_bits_address_base, 6, 6) node _b_bits_address_T_7 = bits(b_bits_address_base, 7, 7) node _b_bits_address_T_8 = bits(b_bits_address_base, 8, 8) node _b_bits_address_T_9 = bits(b_bits_address_base, 9, 9) node _b_bits_address_T_10 = bits(b_bits_address_base, 10, 10) node _b_bits_address_T_11 = bits(b_bits_address_base, 11, 11) node _b_bits_address_T_12 = bits(b_bits_address_base, 12, 12) node _b_bits_address_T_13 = bits(b_bits_address_base, 13, 13) node _b_bits_address_T_14 = bits(b_bits_address_base, 14, 14) node _b_bits_address_T_15 = bits(b_bits_address_base, 15, 15) node _b_bits_address_T_16 = bits(b_bits_address_base, 16, 16) node _b_bits_address_T_17 = bits(b_bits_address_base, 17, 17) node _b_bits_address_T_18 = bits(b_bits_address_base, 18, 18) node _b_bits_address_T_19 = bits(b_bits_address_base, 19, 19) node _b_bits_address_T_20 = bits(b_bits_address_base, 20, 20) node _b_bits_address_T_21 = bits(b_bits_address_base, 21, 21) node _b_bits_address_T_22 = bits(b_bits_address_base, 22, 22) node _b_bits_address_T_23 = bits(b_bits_address_base, 23, 23) node _b_bits_address_T_24 = bits(b_bits_address_base, 24, 24) node _b_bits_address_T_25 = bits(b_bits_address_base, 25, 25) node _b_bits_address_T_26 = bits(b_bits_address_base, 26, 26) node _b_bits_address_T_27 = bits(b_bits_address_base, 27, 27) node _b_bits_address_T_28 = bits(b_bits_address_base, 28, 28) node b_bits_address_lo_lo_lo_lo = cat(_b_bits_address_T_1, _b_bits_address_T) node b_bits_address_lo_lo_lo_hi = cat(_b_bits_address_T_3, _b_bits_address_T_2) node b_bits_address_lo_lo_lo = cat(b_bits_address_lo_lo_lo_hi, b_bits_address_lo_lo_lo_lo) node b_bits_address_lo_lo_hi_lo = cat(_b_bits_address_T_5, _b_bits_address_T_4) node b_bits_address_lo_lo_hi_hi = cat(_b_bits_address_T_7, _b_bits_address_T_6) node b_bits_address_lo_lo_hi = cat(b_bits_address_lo_lo_hi_hi, b_bits_address_lo_lo_hi_lo) node b_bits_address_lo_lo = cat(b_bits_address_lo_lo_hi, b_bits_address_lo_lo_lo) node b_bits_address_lo_hi_lo_lo = cat(_b_bits_address_T_9, _b_bits_address_T_8) node b_bits_address_lo_hi_lo_hi = cat(_b_bits_address_T_11, _b_bits_address_T_10) node b_bits_address_lo_hi_lo = cat(b_bits_address_lo_hi_lo_hi, b_bits_address_lo_hi_lo_lo) node b_bits_address_lo_hi_hi_lo = cat(_b_bits_address_T_13, _b_bits_address_T_12) node b_bits_address_lo_hi_hi_hi = cat(_b_bits_address_T_15, _b_bits_address_T_14) node b_bits_address_lo_hi_hi = cat(b_bits_address_lo_hi_hi_hi, b_bits_address_lo_hi_hi_lo) node b_bits_address_lo_hi = cat(b_bits_address_lo_hi_hi, b_bits_address_lo_hi_lo) node b_bits_address_lo = cat(b_bits_address_lo_hi, b_bits_address_lo_lo) node b_bits_address_hi_lo_lo_lo = cat(_b_bits_address_T_17, _b_bits_address_T_16) node b_bits_address_hi_lo_lo_hi = cat(_b_bits_address_T_19, _b_bits_address_T_18) node b_bits_address_hi_lo_lo = cat(b_bits_address_hi_lo_lo_hi, b_bits_address_hi_lo_lo_lo) node b_bits_address_hi_lo_hi_lo = cat(_b_bits_address_T_21, _b_bits_address_T_20) node b_bits_address_hi_lo_hi_hi = cat(_b_bits_address_T_23, _b_bits_address_T_22) node b_bits_address_hi_lo_hi = cat(b_bits_address_hi_lo_hi_hi, b_bits_address_hi_lo_hi_lo) node b_bits_address_hi_lo = cat(b_bits_address_hi_lo_hi, b_bits_address_hi_lo_lo) node b_bits_address_hi_hi_lo_lo = cat(_b_bits_address_T_25, _b_bits_address_T_24) node b_bits_address_hi_hi_lo_hi = cat(_b_bits_address_T_27, _b_bits_address_T_26) node b_bits_address_hi_hi_lo = cat(b_bits_address_hi_hi_lo_hi, b_bits_address_hi_hi_lo_lo) node b_bits_address_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node b_bits_address_hi_hi_hi_hi = cat(_b_bits_address_T_28, UInt<1>(0h0)) node b_bits_address_hi_hi_hi = cat(b_bits_address_hi_hi_hi_hi, b_bits_address_hi_hi_hi_lo) node b_bits_address_hi_hi = cat(b_bits_address_hi_hi_hi, b_bits_address_hi_hi_lo) node b_bits_address_hi = cat(b_bits_address_hi_hi, b_bits_address_hi_lo) node _b_bits_address_T_29 = cat(b_bits_address_hi, b_bits_address_lo) connect b.bits.address, _b_bits_address_T_29 node _b_bits_mask_T = not(UInt<8>(0h0)) connect b.bits.mask, _b_bits_mask_T connect b.bits.data, UInt<1>(0h0) connect b.bits.corrupt, UInt<1>(0h0)	module SourceB( // @[SourceB.scala:33:7] input clock, // @[SourceB.scala:33:7] input reset, // @[SourceB.scala:33:7] output io_req_ready, // @[SourceB.scala:35:14] input io_req_valid, // @[SourceB.scala:35:14] input [2:0] io_req_bits_param, // @[SourceB.scala:35:14] input [12:0] io_req_bits_tag, // @[SourceB.scala:35:14] input [9:0] io_req_bits_set, // @[SourceB.scala:35:14] input io_req_bits_clients, // @[SourceB.scala:35:14] input io_b_ready, // @[SourceB.scala:35:14] output io_b_valid, // @[SourceB.scala:35:14] output [1:0] io_b_bits_param, // @[SourceB.scala:35:14] output [31:0] io_b_bits_address // @[SourceB.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceB.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7] wire io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7] wire io_b_ready_0 = io_b_ready; // @[SourceB.scala:33:7] wire _b_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] io_b_bits_opcode = 3'h6; // @[SourceB.scala:33:7] wire [2:0] io_b_bits_size = 3'h6; // @[SourceB.scala:33:7] wire [2:0] b_bits_opcode = 3'h6; // @[SourceB.scala:65:17] wire [2:0] b_bits_size = 3'h6; // @[SourceB.scala:65:17] wire [5:0] io_b_bits_source = 6'h20; // @[SourceB.scala:33:7] wire [5:0] b_bits_source = 6'h20; // @[SourceB.scala:65:17] wire [7:0] io_b_bits_mask = 8'hFF; // @[SourceB.scala:33:7] wire [7:0] b_bits_mask = 8'hFF; // @[SourceB.scala:65:17] wire [7:0] _b_bits_mask_T = 8'hFF; // @[SourceB.scala:81:23] wire [63:0] io_b_bits_data = 64'h0; // @[SourceB.scala:33:7] wire [63:0] b_bits_data = 64'h0; // @[SourceB.scala:65:17] wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7] wire b_bits_corrupt = 1'h0; // @[SourceB.scala:65:17] wire _b_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire [1:0] b_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] b_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _b_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire _b_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire _io_req_ready_T; // @[SourceB.scala:61:21] wire b_ready = io_b_ready_0; // @[SourceB.scala:33:7, :65:17] wire b_valid; // @[SourceB.scala:65:17] wire [1:0] b_bits_param; // @[SourceB.scala:65:17] wire [31:0] b_bits_address; // @[SourceB.scala:65:17] wire io_req_ready_0; // @[SourceB.scala:33:7] wire [1:0] io_b_bits_param_0; // @[SourceB.scala:33:7] wire [31:0] io_b_bits_address_0; // @[SourceB.scala:33:7] wire io_b_valid_0; // @[SourceB.scala:33:7] reg remain; // @[SourceB.scala:46:25] wire busy = remain; // @[SourceB.scala:46:25, :51:23] wire remain_set; // @[SourceB.scala:47:30] wire remain_clr; // @[SourceB.scala:48:30] wire _remain_T = remain \| remain_set; // @[SourceB.scala:46:25, :47:30, :49:23] wire _remain_T_1 = ~remain_clr; // @[SourceB.scala:48:30, :49:39] wire _remain_T_2 = _remain_T & _remain_T_1; // @[SourceB.scala:49:{23,37,39}] wire todo = busy ? remain : io_req_bits_clients_0; // @[SourceB.scala:33:7, :46:25, :51:23, :52:19] wire _next_T = todo; // @[package.scala:254:17] wire [1:0] _next_T_1 = {_next_T, 1'h0}; // @[package.scala:254:17] wire [1:0] _next_T_2 = ~_next_T_1; // @[SourceB.scala:53:{16,31}] wire [1:0] next = {1'h0, _next_T_2[0] & todo}; // @[SourceB.scala:52:19, :53:{16,37}]
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_159 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_159( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DecodeUnit_2 : input clock : Clock input reset : Reset output io : { enq : { flip uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, deq : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip csr_decode : { flip inst : UInt<32>, fp_illegal : UInt<1>, vector_illegal : UInt<1>, fp_csr : UInt<1>, vector_csr : UInt<1>, rocc_illegal : UInt<1>, read_illegal : UInt<1>, write_illegal : UInt<1>, write_flush : UInt<1>, system_illegal : UInt<1>, virtual_access_illegal : UInt<1>, virtual_system_illegal : UInt<1>}, flip fcsr_rm : UInt<3>, flip interrupt : UInt<1>, flip interrupt_cause : UInt<64>} wire uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop, io.enq.uop node LDST = bits(uop.inst, 11, 7) node LRS1 = bits(uop.inst, 19, 15) node LRS2 = bits(uop.inst, 24, 20) node LRS3 = bits(uop.inst, 31, 27) wire cs : { legal : UInt<1>, fp_val : UInt<1>, fu_code : UInt<10>, dst_type : UInt<2>, rs1_type : UInt<2>, rs2_type : UInt<2>, frs3_en : UInt<1>, imm_sel : UInt<3>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_amo : UInt<1>, mem_cmd : UInt<5>, inst_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}} wire cs_decoder_decoded_plaInput : UInt<32> node cs_decoder_decoded_invInputs = not(cs_decoder_decoded_plaInput) wire cs_decoder_decoded : UInt<57> node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5) node cs_decoder_decoded_andMatrixOutputs_lo = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6) node cs_decoder_decoded_andMatrixOutputs_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3) node cs_decoder_decoded_andMatrixOutputs_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1) node cs_decoder_decoded_andMatrixOutputs_hi = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo) node _cs_decoder_decoded_andMatrixOutputs_T = cat(cs_decoder_decoded_andMatrixOutputs_hi, cs_decoder_decoded_andMatrixOutputs_lo) node cs_decoder_decoded_andMatrixOutputs_81_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7) node cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1) node cs_decoder_decoded_andMatrixOutputs_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo) node cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1) node cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1) node cs_decoder_decoded_andMatrixOutputs_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_1) node _cs_decoder_decoded_andMatrixOutputs_T_1 = cat(cs_decoder_decoded_andMatrixOutputs_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_1) node cs_decoder_decoded_andMatrixOutputs_85_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1) node cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2) node cs_decoder_decoded_andMatrixOutputs_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_1) node cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2) node cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2) node cs_decoder_decoded_andMatrixOutputs_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_2) node _cs_decoder_decoded_andMatrixOutputs_T_2 = cat(cs_decoder_decoded_andMatrixOutputs_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_2) node cs_decoder_decoded_andMatrixOutputs_10_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3) node cs_decoder_decoded_andMatrixOutputs_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3) node cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3) node cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3) node cs_decoder_decoded_andMatrixOutputs_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_3) node _cs_decoder_decoded_andMatrixOutputs_T_3 = cat(cs_decoder_decoded_andMatrixOutputs_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_3) node cs_decoder_decoded_andMatrixOutputs_26_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8) node cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4) node cs_decoder_decoded_andMatrixOutputs_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_2) node cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4) node cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4) node cs_decoder_decoded_andMatrixOutputs_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_4) node _cs_decoder_decoded_andMatrixOutputs_T_4 = cat(cs_decoder_decoded_andMatrixOutputs_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_4) node cs_decoder_decoded_andMatrixOutputs_100_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5) node cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3) node cs_decoder_decoded_andMatrixOutputs_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_3) node cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5) node cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5) node cs_decoder_decoded_andMatrixOutputs_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_5) node _cs_decoder_decoded_andMatrixOutputs_T_5 = cat(cs_decoder_decoded_andMatrixOutputs_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_5) node cs_decoder_decoded_andMatrixOutputs_88_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_lo_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4) node cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6) node cs_decoder_decoded_andMatrixOutputs_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_4) node cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6) node cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6) node cs_decoder_decoded_andMatrixOutputs_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_6) node _cs_decoder_decoded_andMatrixOutputs_T_6 = cat(cs_decoder_decoded_andMatrixOutputs_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_6) node cs_decoder_decoded_andMatrixOutputs_62_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2) node cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7) node cs_decoder_decoded_andMatrixOutputs_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_5) node cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7) node cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7) node cs_decoder_decoded_andMatrixOutputs_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_7) node _cs_decoder_decoded_andMatrixOutputs_T_7 = cat(cs_decoder_decoded_andMatrixOutputs_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_7) node cs_decoder_decoded_andMatrixOutputs_77_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8) node cs_decoder_decoded_andMatrixOutputs_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8) node cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8) node cs_decoder_decoded_andMatrixOutputs_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8) node _cs_decoder_decoded_andMatrixOutputs_T_8 = cat(cs_decoder_decoded_andMatrixOutputs_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_8) node cs_decoder_decoded_andMatrixOutputs_29_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6) node cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9) node cs_decoder_decoded_andMatrixOutputs_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_6) node cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9) node cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9) node cs_decoder_decoded_andMatrixOutputs_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_lo_8) node _cs_decoder_decoded_andMatrixOutputs_T_9 = cat(cs_decoder_decoded_andMatrixOutputs_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_9) node cs_decoder_decoded_andMatrixOutputs_110_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13) node cs_decoder_decoded_andMatrixOutputs_lo_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1) node cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo) node cs_decoder_decoded_andMatrixOutputs_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_lo_7) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10) node cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10) node cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo) node cs_decoder_decoded_andMatrixOutputs_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_lo_9) node _cs_decoder_decoded_andMatrixOutputs_T_10 = cat(cs_decoder_decoded_andMatrixOutputs_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_10) node cs_decoder_decoded_andMatrixOutputs_61_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_10) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1) node cs_decoder_decoded_andMatrixOutputs_lo_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2) node cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1) node cs_decoder_decoded_andMatrixOutputs_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_lo_8) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11) node cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11) node cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1) node cs_decoder_decoded_andMatrixOutputs_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_10) node _cs_decoder_decoded_andMatrixOutputs_T_11 = cat(cs_decoder_decoded_andMatrixOutputs_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_11) node cs_decoder_decoded_andMatrixOutputs_166_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_11) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2) node cs_decoder_decoded_andMatrixOutputs_lo_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5) node cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3) node cs_decoder_decoded_andMatrixOutputs_lo_12 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_lo_9) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12) node cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12) node cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2) node cs_decoder_decoded_andMatrixOutputs_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_lo_11) node _cs_decoder_decoded_andMatrixOutputs_T_12 = cat(cs_decoder_decoded_andMatrixOutputs_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_12) node cs_decoder_decoded_andMatrixOutputs_8_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2) node cs_decoder_decoded_andMatrixOutputs_lo_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4) node cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2) node cs_decoder_decoded_andMatrixOutputs_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_lo_10) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13) node cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13) node cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3) node cs_decoder_decoded_andMatrixOutputs_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_lo_12) node _cs_decoder_decoded_andMatrixOutputs_T_13 = cat(cs_decoder_decoded_andMatrixOutputs_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_13) node cs_decoder_decoded_andMatrixOutputs_80_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4) node cs_decoder_decoded_andMatrixOutputs_lo_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7) node cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3) node cs_decoder_decoded_andMatrixOutputs_lo_14 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_lo_11) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14) node cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14) node cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4) node cs_decoder_decoded_andMatrixOutputs_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_13) node _cs_decoder_decoded_andMatrixOutputs_T_14 = cat(cs_decoder_decoded_andMatrixOutputs_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_14) node cs_decoder_decoded_andMatrixOutputs_14_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4) node cs_decoder_decoded_andMatrixOutputs_lo_lo_12 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6) node cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4) node cs_decoder_decoded_andMatrixOutputs_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_lo_12) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15) node cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15) node cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5) node cs_decoder_decoded_andMatrixOutputs_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_14) node _cs_decoder_decoded_andMatrixOutputs_T_15 = cat(cs_decoder_decoded_andMatrixOutputs_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_15) node cs_decoder_decoded_andMatrixOutputs_56_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_15) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(cs_decoder_decoded_invInputs, 7, 7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(cs_decoder_decoded_invInputs, 8, 8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(cs_decoder_decoded_invInputs, 9, 9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(cs_decoder_decoded_invInputs, 10, 10) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(cs_decoder_decoded_invInputs, 11, 11) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(cs_decoder_decoded_invInputs, 15, 15) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(cs_decoder_decoded_invInputs, 16, 16) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(cs_decoder_decoded_invInputs, 17, 17) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(cs_decoder_decoded_invInputs, 18, 18) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(cs_decoder_decoded_invInputs, 19, 19) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22) node cs_decoder_decoded_andMatrixOutputs_lo_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo) node cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5) node cs_decoder_decoded_andMatrixOutputs_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_lo_13) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7) node cs_decoder_decoded_andMatrixOutputs_hi_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo) node cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6) node cs_decoder_decoded_andMatrixOutputs_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_lo_15) node _cs_decoder_decoded_andMatrixOutputs_T_16 = cat(cs_decoder_decoded_andMatrixOutputs_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_16) node cs_decoder_decoded_andMatrixOutputs_43_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_16) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17) node cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17) node cs_decoder_decoded_andMatrixOutputs_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17) node _cs_decoder_decoded_andMatrixOutputs_T_17 = cat(cs_decoder_decoded_andMatrixOutputs_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_17) node cs_decoder_decoded_andMatrixOutputs_157_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_17) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18) node cs_decoder_decoded_andMatrixOutputs_lo_18 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17) node cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18) node cs_decoder_decoded_andMatrixOutputs_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18) node _cs_decoder_decoded_andMatrixOutputs_T_18 = cat(cs_decoder_decoded_andMatrixOutputs_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_18) node cs_decoder_decoded_andMatrixOutputs_123_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_18) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18) node cs_decoder_decoded_andMatrixOutputs_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16) node cs_decoder_decoded_andMatrixOutputs_hi_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19) node cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19) node cs_decoder_decoded_andMatrixOutputs_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_16) node _cs_decoder_decoded_andMatrixOutputs_T_19 = cat(cs_decoder_decoded_andMatrixOutputs_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_19) node cs_decoder_decoded_andMatrixOutputs_102_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_19) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19) node cs_decoder_decoded_andMatrixOutputs_lo_20 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17) node cs_decoder_decoded_andMatrixOutputs_hi_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20) node cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20) node cs_decoder_decoded_andMatrixOutputs_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_17) node _cs_decoder_decoded_andMatrixOutputs_T_20 = cat(cs_decoder_decoded_andMatrixOutputs_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_20) node cs_decoder_decoded_andMatrixOutputs_140_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14) node cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10) node cs_decoder_decoded_andMatrixOutputs_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_lo_14) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21) node cs_decoder_decoded_andMatrixOutputs_hi_lo_18 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21) node cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21) node cs_decoder_decoded_andMatrixOutputs_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_lo_18) node _cs_decoder_decoded_andMatrixOutputs_T_21 = cat(cs_decoder_decoded_andMatrixOutputs_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_21) node cs_decoder_decoded_andMatrixOutputs_21_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8) node cs_decoder_decoded_andMatrixOutputs_lo_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15) node cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11) node cs_decoder_decoded_andMatrixOutputs_lo_22 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_lo_15) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22) node cs_decoder_decoded_andMatrixOutputs_hi_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22) node cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22) node cs_decoder_decoded_andMatrixOutputs_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_19) node _cs_decoder_decoded_andMatrixOutputs_T_22 = cat(cs_decoder_decoded_andMatrixOutputs_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_22) node cs_decoder_decoded_andMatrixOutputs_145_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9) node cs_decoder_decoded_andMatrixOutputs_lo_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16) node cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12) node cs_decoder_decoded_andMatrixOutputs_lo_23 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_lo_16) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23) node cs_decoder_decoded_andMatrixOutputs_hi_lo_20 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23) node cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23) node cs_decoder_decoded_andMatrixOutputs_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_20) node _cs_decoder_decoded_andMatrixOutputs_T_23 = cat(cs_decoder_decoded_andMatrixOutputs_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_23) node cs_decoder_decoded_andMatrixOutputs_161_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_lo_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17) node cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23) node cs_decoder_decoded_andMatrixOutputs_lo_24 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_lo_17) node cs_decoder_decoded_andMatrixOutputs_hi_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24) node cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24) node cs_decoder_decoded_andMatrixOutputs_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_21) node _cs_decoder_decoded_andMatrixOutputs_T_24 = cat(cs_decoder_decoded_andMatrixOutputs_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_24) node cs_decoder_decoded_andMatrixOutputs_79_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13) node cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22) node cs_decoder_decoded_andMatrixOutputs_lo_25 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_lo_18) node cs_decoder_decoded_andMatrixOutputs_hi_lo_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25) node cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25) node cs_decoder_decoded_andMatrixOutputs_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_hi_lo_22) node _cs_decoder_decoded_andMatrixOutputs_T_25 = cat(cs_decoder_decoded_andMatrixOutputs_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_25) node cs_decoder_decoded_andMatrixOutputs_33_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14) node cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23) node cs_decoder_decoded_andMatrixOutputs_lo_26 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_lo_19) node cs_decoder_decoded_andMatrixOutputs_hi_lo_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26) node cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26) node cs_decoder_decoded_andMatrixOutputs_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_lo_23) node _cs_decoder_decoded_andMatrixOutputs_T_26 = cat(cs_decoder_decoded_andMatrixOutputs_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_26) node cs_decoder_decoded_andMatrixOutputs_112_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24) node cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20) node cs_decoder_decoded_andMatrixOutputs_lo_27 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_lo_20) node cs_decoder_decoded_andMatrixOutputs_hi_lo_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27) node cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27) node cs_decoder_decoded_andMatrixOutputs_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_lo_24) node _cs_decoder_decoded_andMatrixOutputs_T_27 = cat(cs_decoder_decoded_andMatrixOutputs_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_27) node cs_decoder_decoded_andMatrixOutputs_168_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27) node cs_decoder_decoded_andMatrixOutputs_lo_28 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25) node cs_decoder_decoded_andMatrixOutputs_hi_lo_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28) node cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28) node cs_decoder_decoded_andMatrixOutputs_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_25) node _cs_decoder_decoded_andMatrixOutputs_T_28 = cat(cs_decoder_decoded_andMatrixOutputs_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_28) node cs_decoder_decoded_andMatrixOutputs_138_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(cs_decoder_decoded_invInputs, 7, 7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(cs_decoder_decoded_invInputs, 8, 8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(cs_decoder_decoded_invInputs, 9, 9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(cs_decoder_decoded_invInputs, 10, 10) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(cs_decoder_decoded_invInputs, 11, 11) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(cs_decoder_decoded_invInputs, 15, 15) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(cs_decoder_decoded_invInputs, 16, 16) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(cs_decoder_decoded_invInputs, 17, 17) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(cs_decoder_decoded_invInputs, 18, 18) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(cs_decoder_decoded_invInputs, 19, 19) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo) node cs_decoder_decoded_andMatrixOutputs_lo_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1) node cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6) node cs_decoder_decoded_andMatrixOutputs_lo_29 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_lo_21) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo) node cs_decoder_decoded_andMatrixOutputs_hi_lo_26 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1) node cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7) node cs_decoder_decoded_andMatrixOutputs_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_lo_26) node _cs_decoder_decoded_andMatrixOutputs_T_29 = cat(cs_decoder_decoded_andMatrixOutputs_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_29) node cs_decoder_decoded_andMatrixOutputs_47_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(cs_decoder_decoded_invInputs, 7, 7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(cs_decoder_decoded_invInputs, 8, 8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(cs_decoder_decoded_invInputs, 9, 9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(cs_decoder_decoded_invInputs, 10, 10) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(cs_decoder_decoded_invInputs, 11, 11) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(cs_decoder_decoded_invInputs, 15, 15) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = bits(cs_decoder_decoded_invInputs, 16, 16) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = bits(cs_decoder_decoded_invInputs, 17, 17) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = bits(cs_decoder_decoded_invInputs, 18, 18) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = bits(cs_decoder_decoded_invInputs, 19, 19) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1) node cs_decoder_decoded_andMatrixOutputs_lo_lo_22 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2) node cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7) node cs_decoder_decoded_andMatrixOutputs_lo_30 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_lo_22) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1) node cs_decoder_decoded_andMatrixOutputs_hi_lo_27 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2) node cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8) node cs_decoder_decoded_andMatrixOutputs_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_27) node _cs_decoder_decoded_andMatrixOutputs_T_30 = cat(cs_decoder_decoded_andMatrixOutputs_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_30) node cs_decoder_decoded_andMatrixOutputs_71_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9) node cs_decoder_decoded_andMatrixOutputs_lo_lo_23 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18) node cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8) node cs_decoder_decoded_andMatrixOutputs_lo_31 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_lo_23) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30) node cs_decoder_decoded_andMatrixOutputs_hi_lo_28 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31) node cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9) node cs_decoder_decoded_andMatrixOutputs_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_lo_28) node _cs_decoder_decoded_andMatrixOutputs_T_31 = cat(cs_decoder_decoded_andMatrixOutputs_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_31) node cs_decoder_decoded_andMatrixOutputs_105_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_31) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9) node cs_decoder_decoded_andMatrixOutputs_lo_lo_24 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15) node cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9) node cs_decoder_decoded_andMatrixOutputs_lo_32 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_lo_24) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31) node cs_decoder_decoded_andMatrixOutputs_hi_lo_29 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32) node cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10) node cs_decoder_decoded_andMatrixOutputs_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_29) node _cs_decoder_decoded_andMatrixOutputs_T_32 = cat(cs_decoder_decoded_andMatrixOutputs_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_32) node cs_decoder_decoded_andMatrixOutputs_52_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_32) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10) node cs_decoder_decoded_andMatrixOutputs_lo_lo_25 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16) node cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10) node cs_decoder_decoded_andMatrixOutputs_lo_33 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_lo_25) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32) node cs_decoder_decoded_andMatrixOutputs_hi_lo_30 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33) node cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11) node cs_decoder_decoded_andMatrixOutputs_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_30) node _cs_decoder_decoded_andMatrixOutputs_T_33 = cat(cs_decoder_decoded_andMatrixOutputs_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_33) node cs_decoder_decoded_andMatrixOutputs_86_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_33) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11) node cs_decoder_decoded_andMatrixOutputs_lo_lo_26 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17) node cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11) node cs_decoder_decoded_andMatrixOutputs_lo_34 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_lo_26) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33) node cs_decoder_decoded_andMatrixOutputs_hi_lo_31 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34) node cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12) node cs_decoder_decoded_andMatrixOutputs_hi_34 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_lo_31) node _cs_decoder_decoded_andMatrixOutputs_T_34 = cat(cs_decoder_decoded_andMatrixOutputs_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_34) node cs_decoder_decoded_andMatrixOutputs_0_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_34) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_lo_lo_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27) node cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34) node cs_decoder_decoded_andMatrixOutputs_lo_35 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_lo_27) node cs_decoder_decoded_andMatrixOutputs_hi_lo_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35) node cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35) node cs_decoder_decoded_andMatrixOutputs_hi_35 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_lo_32) node _cs_decoder_decoded_andMatrixOutputs_T_35 = cat(cs_decoder_decoded_andMatrixOutputs_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_35) node cs_decoder_decoded_andMatrixOutputs_76_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_35) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_lo_lo_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28) node cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35) node cs_decoder_decoded_andMatrixOutputs_lo_36 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_lo_28) node cs_decoder_decoded_andMatrixOutputs_hi_lo_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36) node cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36) node cs_decoder_decoded_andMatrixOutputs_hi_36 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_33) node _cs_decoder_decoded_andMatrixOutputs_T_36 = cat(cs_decoder_decoded_andMatrixOutputs_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_36) node cs_decoder_decoded_andMatrixOutputs_160_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_36) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36) node cs_decoder_decoded_andMatrixOutputs_lo_37 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34) node cs_decoder_decoded_andMatrixOutputs_hi_lo_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37) node cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37) node cs_decoder_decoded_andMatrixOutputs_hi_37 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_34) node _cs_decoder_decoded_andMatrixOutputs_T_37 = cat(cs_decoder_decoded_andMatrixOutputs_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_37) node cs_decoder_decoded_andMatrixOutputs_120_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_37) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29) node cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37) node cs_decoder_decoded_andMatrixOutputs_lo_38 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_lo_29) node cs_decoder_decoded_andMatrixOutputs_hi_lo_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38) node cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38) node cs_decoder_decoded_andMatrixOutputs_hi_38 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_35) node _cs_decoder_decoded_andMatrixOutputs_T_38 = cat(cs_decoder_decoded_andMatrixOutputs_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_38) node cs_decoder_decoded_andMatrixOutputs_45_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_38) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30) node cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38) node cs_decoder_decoded_andMatrixOutputs_lo_39 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_lo_30) node cs_decoder_decoded_andMatrixOutputs_hi_lo_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39) node cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39) node cs_decoder_decoded_andMatrixOutputs_hi_39 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_hi_lo_36) node _cs_decoder_decoded_andMatrixOutputs_T_39 = cat(cs_decoder_decoded_andMatrixOutputs_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_39) node cs_decoder_decoded_andMatrixOutputs_162_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_39) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22) node cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37) node cs_decoder_decoded_andMatrixOutputs_lo_40 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_lo_31) node cs_decoder_decoded_andMatrixOutputs_hi_lo_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40) node cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40) node cs_decoder_decoded_andMatrixOutputs_hi_40 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_37) node _cs_decoder_decoded_andMatrixOutputs_T_40 = cat(cs_decoder_decoded_andMatrixOutputs_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_40) node cs_decoder_decoded_andMatrixOutputs_73_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_40) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_lo_lo_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32) node cs_decoder_decoded_andMatrixOutputs_lo_hi_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40) node cs_decoder_decoded_andMatrixOutputs_lo_41 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_32) node cs_decoder_decoded_andMatrixOutputs_hi_lo_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41) node cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41) node cs_decoder_decoded_andMatrixOutputs_hi_41 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_lo_38) node _cs_decoder_decoded_andMatrixOutputs_T_41 = cat(cs_decoder_decoded_andMatrixOutputs_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_41) node cs_decoder_decoded_andMatrixOutputs_18_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_41) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23) node cs_decoder_decoded_andMatrixOutputs_lo_hi_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39) node cs_decoder_decoded_andMatrixOutputs_lo_42 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_lo_33) node cs_decoder_decoded_andMatrixOutputs_hi_lo_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42) node cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42) node cs_decoder_decoded_andMatrixOutputs_hi_42 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_39) node _cs_decoder_decoded_andMatrixOutputs_T_42 = cat(cs_decoder_decoded_andMatrixOutputs_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_42) node cs_decoder_decoded_andMatrixOutputs_111_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_42) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34) node cs_decoder_decoded_andMatrixOutputs_lo_hi_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42) node cs_decoder_decoded_andMatrixOutputs_lo_43 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_lo_34) node cs_decoder_decoded_andMatrixOutputs_hi_lo_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43) node cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43) node cs_decoder_decoded_andMatrixOutputs_hi_43 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_lo_40) node _cs_decoder_decoded_andMatrixOutputs_T_43 = cat(cs_decoder_decoded_andMatrixOutputs_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_43) node cs_decoder_decoded_andMatrixOutputs_153_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_43) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24) node cs_decoder_decoded_andMatrixOutputs_lo_hi_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41) node cs_decoder_decoded_andMatrixOutputs_lo_44 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_35) node cs_decoder_decoded_andMatrixOutputs_hi_lo_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44) node cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44) node cs_decoder_decoded_andMatrixOutputs_hi_44 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_41) node _cs_decoder_decoded_andMatrixOutputs_T_44 = cat(cs_decoder_decoded_andMatrixOutputs_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_44) node cs_decoder_decoded_andMatrixOutputs_107_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_44) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_lo_lo_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36) node cs_decoder_decoded_andMatrixOutputs_lo_hi_44 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25) node cs_decoder_decoded_andMatrixOutputs_lo_45 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_36) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45) node cs_decoder_decoded_andMatrixOutputs_hi_lo_42 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45) node cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45) node cs_decoder_decoded_andMatrixOutputs_hi_45 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_42) node _cs_decoder_decoded_andMatrixOutputs_T_45 = cat(cs_decoder_decoded_andMatrixOutputs_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_45) node cs_decoder_decoded_andMatrixOutputs_17_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_45) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12) node cs_decoder_decoded_andMatrixOutputs_lo_lo_37 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19) node cs_decoder_decoded_andMatrixOutputs_lo_hi_45 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12) node cs_decoder_decoded_andMatrixOutputs_lo_46 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_lo_37) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45) node cs_decoder_decoded_andMatrixOutputs_hi_lo_43 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46) node cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13) node cs_decoder_decoded_andMatrixOutputs_hi_46 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_43) node _cs_decoder_decoded_andMatrixOutputs_T_46 = cat(cs_decoder_decoded_andMatrixOutputs_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_46) node cs_decoder_decoded_andMatrixOutputs_167_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_46) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13) node cs_decoder_decoded_andMatrixOutputs_lo_lo_38 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20) node cs_decoder_decoded_andMatrixOutputs_lo_hi_46 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13) node cs_decoder_decoded_andMatrixOutputs_lo_47 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_lo_38) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46) node cs_decoder_decoded_andMatrixOutputs_hi_lo_44 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47) node cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14) node cs_decoder_decoded_andMatrixOutputs_hi_47 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_hi_lo_44) node _cs_decoder_decoded_andMatrixOutputs_T_47 = cat(cs_decoder_decoded_andMatrixOutputs_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_47) node cs_decoder_decoded_andMatrixOutputs_113_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_47) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_39 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21) node cs_decoder_decoded_andMatrixOutputs_lo_hi_47 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14) node cs_decoder_decoded_andMatrixOutputs_lo_48 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_lo_39) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47) node cs_decoder_decoded_andMatrixOutputs_hi_lo_45 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48) node cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15) node cs_decoder_decoded_andMatrixOutputs_hi_48 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_45) node _cs_decoder_decoded_andMatrixOutputs_T_48 = cat(cs_decoder_decoded_andMatrixOutputs_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_48) node cs_decoder_decoded_andMatrixOutputs_42_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_48) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_lo_lo_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40) node cs_decoder_decoded_andMatrixOutputs_lo_hi_48 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48) node cs_decoder_decoded_andMatrixOutputs_lo_49 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_lo_40) node cs_decoder_decoded_andMatrixOutputs_hi_lo_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49) node cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49) node cs_decoder_decoded_andMatrixOutputs_hi_49 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_46) node _cs_decoder_decoded_andMatrixOutputs_T_49 = cat(cs_decoder_decoded_andMatrixOutputs_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_49) node cs_decoder_decoded_andMatrixOutputs_131_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_49) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_lo_lo_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29) node cs_decoder_decoded_andMatrixOutputs_lo_hi_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47) node cs_decoder_decoded_andMatrixOutputs_lo_50 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_41) node cs_decoder_decoded_andMatrixOutputs_hi_lo_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50) node cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50) node cs_decoder_decoded_andMatrixOutputs_hi_50 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_47) node _cs_decoder_decoded_andMatrixOutputs_T_50 = cat(cs_decoder_decoded_andMatrixOutputs_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_50) node cs_decoder_decoded_andMatrixOutputs_1_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_50) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15) node cs_decoder_decoded_andMatrixOutputs_lo_lo_42 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22) node cs_decoder_decoded_andMatrixOutputs_lo_hi_50 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15) node cs_decoder_decoded_andMatrixOutputs_lo_51 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_42) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50) node cs_decoder_decoded_andMatrixOutputs_hi_lo_48 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51) node cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16) node cs_decoder_decoded_andMatrixOutputs_hi_51 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_48) node _cs_decoder_decoded_andMatrixOutputs_T_51 = cat(cs_decoder_decoded_andMatrixOutputs_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_51) node cs_decoder_decoded_andMatrixOutputs_136_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_51) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31) node cs_decoder_decoded_andMatrixOutputs_lo_hi_51 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49) node cs_decoder_decoded_andMatrixOutputs_lo_52 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_43) node cs_decoder_decoded_andMatrixOutputs_hi_lo_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52) node cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52) node cs_decoder_decoded_andMatrixOutputs_hi_52 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_49) node _cs_decoder_decoded_andMatrixOutputs_T_52 = cat(cs_decoder_decoded_andMatrixOutputs_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_52) node cs_decoder_decoded_andMatrixOutputs_39_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_52) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17) node cs_decoder_decoded_andMatrixOutputs_lo_lo_44 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32) node cs_decoder_decoded_andMatrixOutputs_lo_hi_52 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16) node cs_decoder_decoded_andMatrixOutputs_lo_53 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_44) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52) node cs_decoder_decoded_andMatrixOutputs_hi_lo_50 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53) node cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17) node cs_decoder_decoded_andMatrixOutputs_hi_53 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_50) node _cs_decoder_decoded_andMatrixOutputs_T_53 = cat(cs_decoder_decoded_andMatrixOutputs_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_53) node cs_decoder_decoded_andMatrixOutputs_108_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_53) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17) node cs_decoder_decoded_andMatrixOutputs_lo_lo_45 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24) node cs_decoder_decoded_andMatrixOutputs_lo_hi_53 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17) node cs_decoder_decoded_andMatrixOutputs_lo_54 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_lo_45) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53) node cs_decoder_decoded_andMatrixOutputs_hi_lo_51 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54) node cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18) node cs_decoder_decoded_andMatrixOutputs_hi_54 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_51) node _cs_decoder_decoded_andMatrixOutputs_T_54 = cat(cs_decoder_decoded_andMatrixOutputs_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_54) node cs_decoder_decoded_andMatrixOutputs_165_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_54) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19) node cs_decoder_decoded_andMatrixOutputs_lo_lo_46 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34) node cs_decoder_decoded_andMatrixOutputs_lo_hi_54 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18) node cs_decoder_decoded_andMatrixOutputs_lo_55 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_lo_46) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54) node cs_decoder_decoded_andMatrixOutputs_hi_lo_52 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55) node cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19) node cs_decoder_decoded_andMatrixOutputs_hi_55 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_lo_52) node _cs_decoder_decoded_andMatrixOutputs_T_55 = cat(cs_decoder_decoded_andMatrixOutputs_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_55) node cs_decoder_decoded_andMatrixOutputs_127_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_55) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47) node cs_decoder_decoded_andMatrixOutputs_lo_hi_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55) node cs_decoder_decoded_andMatrixOutputs_lo_56 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_lo_47) node cs_decoder_decoded_andMatrixOutputs_hi_lo_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56) node cs_decoder_decoded_andMatrixOutputs_hi_hi_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56) node cs_decoder_decoded_andMatrixOutputs_hi_56 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_lo_53) node _cs_decoder_decoded_andMatrixOutputs_T_56 = cat(cs_decoder_decoded_andMatrixOutputs_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_56) node cs_decoder_decoded_andMatrixOutputs_135_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_56) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19) node cs_decoder_decoded_andMatrixOutputs_lo_lo_48 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26) node cs_decoder_decoded_andMatrixOutputs_lo_hi_56 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19) node cs_decoder_decoded_andMatrixOutputs_lo_57 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_lo_48) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56) node cs_decoder_decoded_andMatrixOutputs_hi_lo_54 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57) node cs_decoder_decoded_andMatrixOutputs_hi_hi_57 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20) node cs_decoder_decoded_andMatrixOutputs_hi_57 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_lo_54) node _cs_decoder_decoded_andMatrixOutputs_T_57 = cat(cs_decoder_decoded_andMatrixOutputs_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_57) node cs_decoder_decoded_andMatrixOutputs_114_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_57) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20) node cs_decoder_decoded_andMatrixOutputs_lo_lo_49 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27) node cs_decoder_decoded_andMatrixOutputs_lo_hi_57 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20) node cs_decoder_decoded_andMatrixOutputs_lo_58 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_lo_49) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57) node cs_decoder_decoded_andMatrixOutputs_hi_lo_55 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58) node cs_decoder_decoded_andMatrixOutputs_hi_hi_58 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21) node cs_decoder_decoded_andMatrixOutputs_hi_58 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_lo_55) node _cs_decoder_decoded_andMatrixOutputs_T_58 = cat(cs_decoder_decoded_andMatrixOutputs_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_58) node cs_decoder_decoded_andMatrixOutputs_155_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_58) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21) node cs_decoder_decoded_andMatrixOutputs_lo_lo_50 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28) node cs_decoder_decoded_andMatrixOutputs_lo_hi_58 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21) node cs_decoder_decoded_andMatrixOutputs_lo_59 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_lo_50) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58) node cs_decoder_decoded_andMatrixOutputs_hi_lo_56 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59) node cs_decoder_decoded_andMatrixOutputs_hi_hi_59 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22) node cs_decoder_decoded_andMatrixOutputs_hi_59 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_lo_56) node _cs_decoder_decoded_andMatrixOutputs_T_59 = cat(cs_decoder_decoded_andMatrixOutputs_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_59) node cs_decoder_decoded_andMatrixOutputs_6_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_59) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22) node cs_decoder_decoded_andMatrixOutputs_lo_lo_51 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29) node cs_decoder_decoded_andMatrixOutputs_lo_hi_59 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22) node cs_decoder_decoded_andMatrixOutputs_lo_60 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_lo_51) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59) node cs_decoder_decoded_andMatrixOutputs_hi_lo_57 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60) node cs_decoder_decoded_andMatrixOutputs_hi_hi_60 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23) node cs_decoder_decoded_andMatrixOutputs_hi_60 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_hi_lo_57) node _cs_decoder_decoded_andMatrixOutputs_T_60 = cat(cs_decoder_decoded_andMatrixOutputs_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_60) node cs_decoder_decoded_andMatrixOutputs_75_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_60) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39) node cs_decoder_decoded_andMatrixOutputs_lo_hi_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58) node cs_decoder_decoded_andMatrixOutputs_lo_61 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_lo_52) node cs_decoder_decoded_andMatrixOutputs_hi_lo_58 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61) node cs_decoder_decoded_andMatrixOutputs_hi_hi_61 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61) node cs_decoder_decoded_andMatrixOutputs_hi_61 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_hi_lo_58) node _cs_decoder_decoded_andMatrixOutputs_T_61 = cat(cs_decoder_decoded_andMatrixOutputs_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_61) node cs_decoder_decoded_andMatrixOutputs_72_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_61) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40) node cs_decoder_decoded_andMatrixOutputs_lo_hi_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59) node cs_decoder_decoded_andMatrixOutputs_lo_62 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_lo_53) node cs_decoder_decoded_andMatrixOutputs_hi_lo_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62) node cs_decoder_decoded_andMatrixOutputs_hi_hi_62 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62) node cs_decoder_decoded_andMatrixOutputs_hi_62 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_59) node _cs_decoder_decoded_andMatrixOutputs_T_62 = cat(cs_decoder_decoded_andMatrixOutputs_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_62) node cs_decoder_decoded_andMatrixOutputs_96_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_62) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23) node cs_decoder_decoded_andMatrixOutputs_lo_lo_54 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30) node cs_decoder_decoded_andMatrixOutputs_lo_hi_62 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23) node cs_decoder_decoded_andMatrixOutputs_lo_63 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_lo_54) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62) node cs_decoder_decoded_andMatrixOutputs_hi_lo_60 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63) node cs_decoder_decoded_andMatrixOutputs_hi_hi_63 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24) node cs_decoder_decoded_andMatrixOutputs_hi_63 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_lo_60) node _cs_decoder_decoded_andMatrixOutputs_T_63 = cat(cs_decoder_decoded_andMatrixOutputs_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_63) node cs_decoder_decoded_andMatrixOutputs_149_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_63) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42) node cs_decoder_decoded_andMatrixOutputs_lo_hi_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61) node cs_decoder_decoded_andMatrixOutputs_lo_64 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_lo_55) node cs_decoder_decoded_andMatrixOutputs_hi_lo_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64) node cs_decoder_decoded_andMatrixOutputs_hi_hi_64 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64) node cs_decoder_decoded_andMatrixOutputs_hi_64 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_61) node _cs_decoder_decoded_andMatrixOutputs_T_64 = cat(cs_decoder_decoded_andMatrixOutputs_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_64) node cs_decoder_decoded_andMatrixOutputs_144_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_64) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43) node cs_decoder_decoded_andMatrixOutputs_lo_hi_64 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62) node cs_decoder_decoded_andMatrixOutputs_lo_65 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_lo_56) node cs_decoder_decoded_andMatrixOutputs_hi_lo_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65) node cs_decoder_decoded_andMatrixOutputs_hi_hi_65 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65) node cs_decoder_decoded_andMatrixOutputs_hi_65 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_62) node _cs_decoder_decoded_andMatrixOutputs_T_65 = cat(cs_decoder_decoded_andMatrixOutputs_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_65) node cs_decoder_decoded_andMatrixOutputs_3_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_65) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63) node cs_decoder_decoded_andMatrixOutputs_lo_hi_65 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57) node cs_decoder_decoded_andMatrixOutputs_lo_66 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_lo_57) node cs_decoder_decoded_andMatrixOutputs_hi_lo_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66) node cs_decoder_decoded_andMatrixOutputs_hi_hi_66 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66) node cs_decoder_decoded_andMatrixOutputs_hi_66 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_63) node _cs_decoder_decoded_andMatrixOutputs_T_66 = cat(cs_decoder_decoded_andMatrixOutputs_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_66) node cs_decoder_decoded_andMatrixOutputs_13_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_66) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24) node cs_decoder_decoded_andMatrixOutputs_lo_lo_58 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32) node cs_decoder_decoded_andMatrixOutputs_lo_hi_66 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24) node cs_decoder_decoded_andMatrixOutputs_lo_67 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_lo_58) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66) node cs_decoder_decoded_andMatrixOutputs_hi_lo_64 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67) node cs_decoder_decoded_andMatrixOutputs_hi_hi_67 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25) node cs_decoder_decoded_andMatrixOutputs_hi_67 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_lo_64) node _cs_decoder_decoded_andMatrixOutputs_T_67 = cat(cs_decoder_decoded_andMatrixOutputs_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_67) node cs_decoder_decoded_andMatrixOutputs_141_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_67) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25) node cs_decoder_decoded_andMatrixOutputs_lo_lo_59 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33) node cs_decoder_decoded_andMatrixOutputs_lo_hi_67 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25) node cs_decoder_decoded_andMatrixOutputs_lo_68 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_lo_59) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67) node cs_decoder_decoded_andMatrixOutputs_hi_lo_65 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68) node cs_decoder_decoded_andMatrixOutputs_hi_hi_68 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26) node cs_decoder_decoded_andMatrixOutputs_hi_68 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_65) node _cs_decoder_decoded_andMatrixOutputs_T_68 = cat(cs_decoder_decoded_andMatrixOutputs_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_68) node cs_decoder_decoded_andMatrixOutputs_93_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_68) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_lo_hi_68 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68) node cs_decoder_decoded_andMatrixOutputs_lo_69 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66) node cs_decoder_decoded_andMatrixOutputs_hi_lo_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69) node cs_decoder_decoded_andMatrixOutputs_hi_hi_69 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69) node cs_decoder_decoded_andMatrixOutputs_hi_69 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_66) node _cs_decoder_decoded_andMatrixOutputs_T_69 = cat(cs_decoder_decoded_andMatrixOutputs_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_69) node cs_decoder_decoded_andMatrixOutputs_60_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_69) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_60 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60) node cs_decoder_decoded_andMatrixOutputs_lo_hi_69 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47) node cs_decoder_decoded_andMatrixOutputs_lo_70 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_60) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70) node cs_decoder_decoded_andMatrixOutputs_hi_lo_67 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70) node cs_decoder_decoded_andMatrixOutputs_hi_hi_70 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70) node cs_decoder_decoded_andMatrixOutputs_hi_70 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_67) node _cs_decoder_decoded_andMatrixOutputs_T_70 = cat(cs_decoder_decoded_andMatrixOutputs_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_70) node cs_decoder_decoded_andMatrixOutputs_69_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_70) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26) node cs_decoder_decoded_andMatrixOutputs_lo_lo_61 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35) node cs_decoder_decoded_andMatrixOutputs_lo_hi_70 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26) node cs_decoder_decoded_andMatrixOutputs_lo_71 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_lo_61) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70) node cs_decoder_decoded_andMatrixOutputs_hi_lo_68 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71) node cs_decoder_decoded_andMatrixOutputs_hi_hi_71 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27) node cs_decoder_decoded_andMatrixOutputs_hi_71 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_68) node _cs_decoder_decoded_andMatrixOutputs_T_71 = cat(cs_decoder_decoded_andMatrixOutputs_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_71) node cs_decoder_decoded_andMatrixOutputs_124_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_71) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27) node cs_decoder_decoded_andMatrixOutputs_lo_lo_62 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36) node cs_decoder_decoded_andMatrixOutputs_lo_hi_71 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27) node cs_decoder_decoded_andMatrixOutputs_lo_72 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_lo_62) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71) node cs_decoder_decoded_andMatrixOutputs_hi_lo_69 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72) node cs_decoder_decoded_andMatrixOutputs_hi_hi_72 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28) node cs_decoder_decoded_andMatrixOutputs_hi_72 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_lo_69) node _cs_decoder_decoded_andMatrixOutputs_T_72 = cat(cs_decoder_decoded_andMatrixOutputs_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_72) node cs_decoder_decoded_andMatrixOutputs_30_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_72) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29) node cs_decoder_decoded_andMatrixOutputs_lo_lo_63 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50) node cs_decoder_decoded_andMatrixOutputs_lo_hi_72 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28) node cs_decoder_decoded_andMatrixOutputs_lo_73 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_lo_63) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72) node cs_decoder_decoded_andMatrixOutputs_hi_lo_70 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73) node cs_decoder_decoded_andMatrixOutputs_hi_hi_73 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29) node cs_decoder_decoded_andMatrixOutputs_hi_73 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_lo_70) node _cs_decoder_decoded_andMatrixOutputs_T_73 = cat(cs_decoder_decoded_andMatrixOutputs_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_73) node cs_decoder_decoded_andMatrixOutputs_35_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_73) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30) node cs_decoder_decoded_andMatrixOutputs_lo_lo_64 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51) node cs_decoder_decoded_andMatrixOutputs_lo_hi_73 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29) node cs_decoder_decoded_andMatrixOutputs_lo_74 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_lo_64) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73) node cs_decoder_decoded_andMatrixOutputs_hi_lo_71 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74) node cs_decoder_decoded_andMatrixOutputs_hi_hi_74 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30) node cs_decoder_decoded_andMatrixOutputs_hi_74 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_lo_71) node _cs_decoder_decoded_andMatrixOutputs_T_74 = cat(cs_decoder_decoded_andMatrixOutputs_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_74) node cs_decoder_decoded_andMatrixOutputs_9_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_74) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30) node cs_decoder_decoded_andMatrixOutputs_lo_lo_65 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39) node cs_decoder_decoded_andMatrixOutputs_lo_hi_74 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30) node cs_decoder_decoded_andMatrixOutputs_lo_75 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_lo_65) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74) node cs_decoder_decoded_andMatrixOutputs_hi_lo_72 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75) node cs_decoder_decoded_andMatrixOutputs_hi_hi_75 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31) node cs_decoder_decoded_andMatrixOutputs_hi_75 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_lo_72) node _cs_decoder_decoded_andMatrixOutputs_T_75 = cat(cs_decoder_decoded_andMatrixOutputs_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_75) node cs_decoder_decoded_andMatrixOutputs_89_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_75) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_66 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40) node cs_decoder_decoded_andMatrixOutputs_lo_hi_75 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31) node cs_decoder_decoded_andMatrixOutputs_lo_76 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_lo_66) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75) node cs_decoder_decoded_andMatrixOutputs_hi_lo_73 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76) node cs_decoder_decoded_andMatrixOutputs_hi_hi_76 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32) node cs_decoder_decoded_andMatrixOutputs_hi_76 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_73) node _cs_decoder_decoded_andMatrixOutputs_T_76 = cat(cs_decoder_decoded_andMatrixOutputs_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_76) node cs_decoder_decoded_andMatrixOutputs_57_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_76) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26) node cs_decoder_decoded_andMatrixOutputs_lo_lo_67 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38) node cs_decoder_decoded_andMatrixOutputs_lo_hi_76 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32) node cs_decoder_decoded_andMatrixOutputs_lo_77 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_lo_67) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74) node cs_decoder_decoded_andMatrixOutputs_hi_lo_74 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77) node cs_decoder_decoded_andMatrixOutputs_hi_hi_77 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33) node cs_decoder_decoded_andMatrixOutputs_hi_77 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_lo_74) node _cs_decoder_decoded_andMatrixOutputs_T_77 = cat(cs_decoder_decoded_andMatrixOutputs_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_77) node cs_decoder_decoded_andMatrixOutputs_164_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_77) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37) node cs_decoder_decoded_andMatrixOutputs_lo_lo_68 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55) node cs_decoder_decoded_andMatrixOutputs_lo_hi_77 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42) node cs_decoder_decoded_andMatrixOutputs_lo_78 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_lo_68) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77) node cs_decoder_decoded_andMatrixOutputs_hi_lo_75 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78) node cs_decoder_decoded_andMatrixOutputs_hi_hi_78 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34) node cs_decoder_decoded_andMatrixOutputs_hi_78 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_lo_75) node _cs_decoder_decoded_andMatrixOutputs_T_78 = cat(cs_decoder_decoded_andMatrixOutputs_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_78) node cs_decoder_decoded_andMatrixOutputs_121_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_78) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33) node cs_decoder_decoded_andMatrixOutputs_lo_lo_69 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43) node cs_decoder_decoded_andMatrixOutputs_lo_hi_78 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33) node cs_decoder_decoded_andMatrixOutputs_lo_79 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_lo_69) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78) node cs_decoder_decoded_andMatrixOutputs_hi_lo_76 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79) node cs_decoder_decoded_andMatrixOutputs_hi_hi_79 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35) node cs_decoder_decoded_andMatrixOutputs_hi_79 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_76) node _cs_decoder_decoded_andMatrixOutputs_T_79 = cat(cs_decoder_decoded_andMatrixOutputs_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_79) node cs_decoder_decoded_andMatrixOutputs_25_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_79) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39) node cs_decoder_decoded_andMatrixOutputs_lo_lo_70 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57) node cs_decoder_decoded_andMatrixOutputs_lo_hi_79 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44) node cs_decoder_decoded_andMatrixOutputs_lo_80 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_lo_70) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79) node cs_decoder_decoded_andMatrixOutputs_hi_lo_77 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80) node cs_decoder_decoded_andMatrixOutputs_hi_hi_80 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36) node cs_decoder_decoded_andMatrixOutputs_hi_80 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_77) node _cs_decoder_decoded_andMatrixOutputs_T_80 = cat(cs_decoder_decoded_andMatrixOutputs_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_80) node cs_decoder_decoded_andMatrixOutputs_99_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_80) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3) node cs_decoder_decoded_andMatrixOutputs_lo_lo_71 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34) node cs_decoder_decoded_andMatrixOutputs_lo_hi_80 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34) node cs_decoder_decoded_andMatrixOutputs_lo_81 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_lo_71) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58) node cs_decoder_decoded_andMatrixOutputs_hi_lo_78 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81) node cs_decoder_decoded_andMatrixOutputs_hi_hi_81 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37) node cs_decoder_decoded_andMatrixOutputs_hi_81 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_78) node _cs_decoder_decoded_andMatrixOutputs_T_81 = cat(cs_decoder_decoded_andMatrixOutputs_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_81) node cs_decoder_decoded_andMatrixOutputs_51_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_81) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35) node cs_decoder_decoded_andMatrixOutputs_lo_lo_72 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46) node cs_decoder_decoded_andMatrixOutputs_lo_hi_81 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35) node cs_decoder_decoded_andMatrixOutputs_lo_82 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_lo_72) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81) node cs_decoder_decoded_andMatrixOutputs_hi_lo_79 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82) node cs_decoder_decoded_andMatrixOutputs_hi_hi_82 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38) node cs_decoder_decoded_andMatrixOutputs_hi_82 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_lo_79) node _cs_decoder_decoded_andMatrixOutputs_T_82 = cat(cs_decoder_decoded_andMatrixOutputs_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_82) node cs_decoder_decoded_andMatrixOutputs_37_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_82) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36) node cs_decoder_decoded_andMatrixOutputs_lo_lo_73 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47) node cs_decoder_decoded_andMatrixOutputs_lo_hi_82 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36) node cs_decoder_decoded_andMatrixOutputs_lo_83 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_lo_73) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82) node cs_decoder_decoded_andMatrixOutputs_hi_lo_80 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83) node cs_decoder_decoded_andMatrixOutputs_hi_hi_83 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39) node cs_decoder_decoded_andMatrixOutputs_hi_83 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_80) node _cs_decoder_decoded_andMatrixOutputs_T_83 = cat(cs_decoder_decoded_andMatrixOutputs_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_83) node cs_decoder_decoded_andMatrixOutputs_143_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_83) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37) node cs_decoder_decoded_andMatrixOutputs_lo_lo_74 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48) node cs_decoder_decoded_andMatrixOutputs_lo_hi_83 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37) node cs_decoder_decoded_andMatrixOutputs_lo_84 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_lo_74) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83) node cs_decoder_decoded_andMatrixOutputs_hi_lo_81 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84) node cs_decoder_decoded_andMatrixOutputs_hi_hi_84 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40) node cs_decoder_decoded_andMatrixOutputs_hi_84 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_81) node _cs_decoder_decoded_andMatrixOutputs_T_84 = cat(cs_decoder_decoded_andMatrixOutputs_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_84) node cs_decoder_decoded_andMatrixOutputs_137_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_84) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32) node cs_decoder_decoded_andMatrixOutputs_lo_lo_75 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46) node cs_decoder_decoded_andMatrixOutputs_lo_hi_84 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38) node cs_decoder_decoded_andMatrixOutputs_lo_85 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_lo_75) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82) node cs_decoder_decoded_andMatrixOutputs_hi_lo_82 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85) node cs_decoder_decoded_andMatrixOutputs_hi_hi_85 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41) node cs_decoder_decoded_andMatrixOutputs_hi_85 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_82) node _cs_decoder_decoded_andMatrixOutputs_T_85 = cat(cs_decoder_decoded_andMatrixOutputs_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_85) node cs_decoder_decoded_andMatrixOutputs_118_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_85) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6) node cs_decoder_decoded_andMatrixOutputs_lo_lo_76 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42) node cs_decoder_decoded_andMatrixOutputs_lo_hi_85 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39) node cs_decoder_decoded_andMatrixOutputs_lo_86 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_76) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76) node cs_decoder_decoded_andMatrixOutputs_hi_lo_83 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86) node cs_decoder_decoded_andMatrixOutputs_hi_hi_86 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42) node cs_decoder_decoded_andMatrixOutputs_hi_86 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_83) node _cs_decoder_decoded_andMatrixOutputs_T_86 = cat(cs_decoder_decoded_andMatrixOutputs_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_86) node cs_decoder_decoded_andMatrixOutputs_58_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_86) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(cs_decoder_decoded_invInputs, 7, 7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(cs_decoder_decoded_invInputs, 8, 8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(cs_decoder_decoded_invInputs, 9, 9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(cs_decoder_decoded_invInputs, 10, 10) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(cs_decoder_decoded_invInputs, 11, 11) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(cs_decoder_decoded_invInputs, 15, 15) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(cs_decoder_decoded_invInputs, 16, 16) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = bits(cs_decoder_decoded_invInputs, 17, 17) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = bits(cs_decoder_decoded_invInputs, 18, 18) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = bits(cs_decoder_decoded_invInputs, 19, 19) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = bits(cs_decoder_decoded_plaInput, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3) node cs_decoder_decoded_andMatrixOutputs_lo_lo_77 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3) node cs_decoder_decoded_andMatrixOutputs_lo_hi_86 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40) node cs_decoder_decoded_andMatrixOutputs_lo_87 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_77) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51) node cs_decoder_decoded_andMatrixOutputs_hi_lo_84 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3) node cs_decoder_decoded_andMatrixOutputs_hi_hi_87 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43) node cs_decoder_decoded_andMatrixOutputs_hi_87 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_84) node _cs_decoder_decoded_andMatrixOutputs_T_87 = cat(cs_decoder_decoded_andMatrixOutputs_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_87) node cs_decoder_decoded_andMatrixOutputs_146_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_87) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(cs_decoder_decoded_invInputs, 7, 7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(cs_decoder_decoded_invInputs, 8, 8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(cs_decoder_decoded_invInputs, 9, 9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(cs_decoder_decoded_invInputs, 10, 10) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(cs_decoder_decoded_invInputs, 11, 11) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = bits(cs_decoder_decoded_invInputs, 15, 15) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = bits(cs_decoder_decoded_invInputs, 16, 16) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = bits(cs_decoder_decoded_invInputs, 17, 17) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = bits(cs_decoder_decoded_invInputs, 18, 18) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = bits(cs_decoder_decoded_invInputs, 19, 19) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = bits(cs_decoder_decoded_plaInput, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2) node cs_decoder_decoded_andMatrixOutputs_lo_lo_78 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4) node cs_decoder_decoded_andMatrixOutputs_lo_hi_87 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41) node cs_decoder_decoded_andMatrixOutputs_lo_88 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_lo_78) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2) node cs_decoder_decoded_andMatrixOutputs_hi_lo_85 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4) node cs_decoder_decoded_andMatrixOutputs_hi_hi_88 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44) node cs_decoder_decoded_andMatrixOutputs_hi_88 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_85) node _cs_decoder_decoded_andMatrixOutputs_T_88 = cat(cs_decoder_decoded_andMatrixOutputs_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_88) node cs_decoder_decoded_andMatrixOutputs_50_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_88) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(cs_decoder_decoded_invInputs, 7, 7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(cs_decoder_decoded_invInputs, 8, 8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(cs_decoder_decoded_invInputs, 9, 9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(cs_decoder_decoded_invInputs, 10, 10) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(cs_decoder_decoded_invInputs, 11, 11) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = bits(cs_decoder_decoded_invInputs, 15, 15) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = bits(cs_decoder_decoded_invInputs, 16, 16) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = bits(cs_decoder_decoded_invInputs, 17, 17) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = bits(cs_decoder_decoded_invInputs, 18, 18) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = bits(cs_decoder_decoded_invInputs, 19, 19) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = bits(cs_decoder_decoded_plaInput, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3) node cs_decoder_decoded_andMatrixOutputs_lo_lo_79 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5) node cs_decoder_decoded_andMatrixOutputs_lo_hi_88 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42) node cs_decoder_decoded_andMatrixOutputs_lo_89 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_79) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3) node cs_decoder_decoded_andMatrixOutputs_hi_lo_86 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5) node cs_decoder_decoded_andMatrixOutputs_hi_hi_89 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45) node cs_decoder_decoded_andMatrixOutputs_hi_89 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_lo_86) node _cs_decoder_decoded_andMatrixOutputs_T_89 = cat(cs_decoder_decoded_andMatrixOutputs_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_89) node cs_decoder_decoded_andMatrixOutputs_129_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_89) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(cs_decoder_decoded_invInputs, 7, 7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(cs_decoder_decoded_invInputs, 8, 8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(cs_decoder_decoded_invInputs, 9, 9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(cs_decoder_decoded_invInputs, 10, 10) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(cs_decoder_decoded_invInputs, 11, 11) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(cs_decoder_decoded_invInputs, 15, 15) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(cs_decoder_decoded_invInputs, 16, 16) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(cs_decoder_decoded_invInputs, 17, 17) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = bits(cs_decoder_decoded_invInputs, 18, 18) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = bits(cs_decoder_decoded_invInputs, 19, 19) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = bits(cs_decoder_decoded_plaInput, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = bits(cs_decoder_decoded_plaInput, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6) node cs_decoder_decoded_andMatrixOutputs_lo_lo_80 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6) node cs_decoder_decoded_andMatrixOutputs_lo_hi_89 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43) node cs_decoder_decoded_andMatrixOutputs_lo_90 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_80) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54) node cs_decoder_decoded_andMatrixOutputs_hi_lo_87 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6) node cs_decoder_decoded_andMatrixOutputs_hi_hi_90 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46) node cs_decoder_decoded_andMatrixOutputs_hi_90 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_87) node _cs_decoder_decoded_andMatrixOutputs_T_90 = cat(cs_decoder_decoded_andMatrixOutputs_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_90) node cs_decoder_decoded_andMatrixOutputs_66_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_90) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(cs_decoder_decoded_invInputs, 7, 7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(cs_decoder_decoded_invInputs, 8, 8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(cs_decoder_decoded_invInputs, 9, 9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(cs_decoder_decoded_invInputs, 10, 10) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(cs_decoder_decoded_invInputs, 11, 11) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(cs_decoder_decoded_invInputs, 15, 15) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = bits(cs_decoder_decoded_invInputs, 16, 16) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = bits(cs_decoder_decoded_invInputs, 17, 17) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = bits(cs_decoder_decoded_invInputs, 18, 18) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = bits(cs_decoder_decoded_invInputs, 19, 19) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = bits(cs_decoder_decoded_plaInput, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = bits(cs_decoder_decoded_plaInput, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4) node cs_decoder_decoded_andMatrixOutputs_lo_lo_81 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7) node cs_decoder_decoded_andMatrixOutputs_lo_hi_90 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44) node cs_decoder_decoded_andMatrixOutputs_lo_91 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_81) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4) node cs_decoder_decoded_andMatrixOutputs_hi_lo_88 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7) node cs_decoder_decoded_andMatrixOutputs_hi_hi_91 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47) node cs_decoder_decoded_andMatrixOutputs_hi_91 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_88) node _cs_decoder_decoded_andMatrixOutputs_T_91 = cat(cs_decoder_decoded_andMatrixOutputs_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_91) node cs_decoder_decoded_andMatrixOutputs_134_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_91) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(cs_decoder_decoded_invInputs, 7, 7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(cs_decoder_decoded_invInputs, 8, 8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(cs_decoder_decoded_invInputs, 9, 9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(cs_decoder_decoded_invInputs, 10, 10) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(cs_decoder_decoded_invInputs, 11, 11) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = bits(cs_decoder_decoded_invInputs, 15, 15) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = bits(cs_decoder_decoded_invInputs, 16, 16) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = bits(cs_decoder_decoded_invInputs, 17, 17) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = bits(cs_decoder_decoded_invInputs, 18, 18) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = bits(cs_decoder_decoded_invInputs, 19, 19) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = bits(cs_decoder_decoded_plaInput, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_8 = bits(cs_decoder_decoded_plaInput, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_8 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_8 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_8 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_8) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5) node cs_decoder_decoded_andMatrixOutputs_lo_lo_82 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_8) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_8) node cs_decoder_decoded_andMatrixOutputs_lo_hi_91 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45) node cs_decoder_decoded_andMatrixOutputs_lo_92 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_82) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5) node cs_decoder_decoded_andMatrixOutputs_hi_lo_89 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_8) node cs_decoder_decoded_andMatrixOutputs_hi_hi_92 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48) node cs_decoder_decoded_andMatrixOutputs_hi_92 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_89) node _cs_decoder_decoded_andMatrixOutputs_T_92 = cat(cs_decoder_decoded_andMatrixOutputs_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_92) node cs_decoder_decoded_andMatrixOutputs_97_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_92) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(cs_decoder_decoded_invInputs, 7, 7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(cs_decoder_decoded_invInputs, 8, 8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(cs_decoder_decoded_invInputs, 9, 9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40) node cs_decoder_decoded_andMatrixOutputs_lo_lo_83 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54) node cs_decoder_decoded_andMatrixOutputs_lo_hi_92 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46) node cs_decoder_decoded_andMatrixOutputs_lo_93 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_lo_83) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90) node cs_decoder_decoded_andMatrixOutputs_hi_lo_90 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93) node cs_decoder_decoded_andMatrixOutputs_hi_hi_93 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49) node cs_decoder_decoded_andMatrixOutputs_hi_93 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_90) node _cs_decoder_decoded_andMatrixOutputs_T_93 = cat(cs_decoder_decoded_andMatrixOutputs_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_93) node cs_decoder_decoded_andMatrixOutputs_65_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_93) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(cs_decoder_decoded_invInputs, 7, 7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(cs_decoder_decoded_invInputs, 8, 8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(cs_decoder_decoded_invInputs, 9, 9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11) node cs_decoder_decoded_andMatrixOutputs_lo_lo_84 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50) node cs_decoder_decoded_andMatrixOutputs_lo_hi_93 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47) node cs_decoder_decoded_andMatrixOutputs_lo_94 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_84) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84) node cs_decoder_decoded_andMatrixOutputs_hi_lo_91 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94) node cs_decoder_decoded_andMatrixOutputs_hi_hi_94 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50) node cs_decoder_decoded_andMatrixOutputs_hi_94 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_91) node _cs_decoder_decoded_andMatrixOutputs_T_94 = cat(cs_decoder_decoded_andMatrixOutputs_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_94) node cs_decoder_decoded_andMatrixOutputs_16_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_94) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(cs_decoder_decoded_invInputs, 7, 7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(cs_decoder_decoded_invInputs, 8, 8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(cs_decoder_decoded_invInputs, 9, 9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(cs_decoder_decoded_invInputs, 10, 10) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(cs_decoder_decoded_invInputs, 11, 11) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11) node cs_decoder_decoded_andMatrixOutputs_lo_lo_85 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48) node cs_decoder_decoded_andMatrixOutputs_lo_hi_94 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48) node cs_decoder_decoded_andMatrixOutputs_lo_95 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_85) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72) node cs_decoder_decoded_andMatrixOutputs_hi_lo_92 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95) node cs_decoder_decoded_andMatrixOutputs_hi_hi_95 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51) node cs_decoder_decoded_andMatrixOutputs_hi_95 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_92) node _cs_decoder_decoded_andMatrixOutputs_T_95 = cat(cs_decoder_decoded_andMatrixOutputs_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_95) node cs_decoder_decoded_andMatrixOutputs_95_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_95) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55) node cs_decoder_decoded_andMatrixOutputs_lo_lo_86 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73) node cs_decoder_decoded_andMatrixOutputs_lo_hi_95 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60) node cs_decoder_decoded_andMatrixOutputs_lo_96 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_86) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95) node cs_decoder_decoded_andMatrixOutputs_hi_lo_93 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96) node cs_decoder_decoded_andMatrixOutputs_hi_hi_96 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52) node cs_decoder_decoded_andMatrixOutputs_hi_96 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_93) node _cs_decoder_decoded_andMatrixOutputs_T_96 = cat(cs_decoder_decoded_andMatrixOutputs_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_96) node cs_decoder_decoded_andMatrixOutputs_82_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_96) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53) node cs_decoder_decoded_andMatrixOutputs_lo_lo_87 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74) node cs_decoder_decoded_andMatrixOutputs_lo_hi_96 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49) node cs_decoder_decoded_andMatrixOutputs_lo_97 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_87) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96) node cs_decoder_decoded_andMatrixOutputs_hi_lo_94 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97) node cs_decoder_decoded_andMatrixOutputs_hi_hi_97 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53) node cs_decoder_decoded_andMatrixOutputs_hi_97 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_94) node _cs_decoder_decoded_andMatrixOutputs_T_97 = cat(cs_decoder_decoded_andMatrixOutputs_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_97) node cs_decoder_decoded_andMatrixOutputs_54_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_97) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54) node cs_decoder_decoded_andMatrixOutputs_lo_lo_88 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75) node cs_decoder_decoded_andMatrixOutputs_lo_hi_97 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50) node cs_decoder_decoded_andMatrixOutputs_lo_98 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_lo_88) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97) node cs_decoder_decoded_andMatrixOutputs_hi_lo_95 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98) node cs_decoder_decoded_andMatrixOutputs_hi_hi_98 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54) node cs_decoder_decoded_andMatrixOutputs_hi_98 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_95) node _cs_decoder_decoded_andMatrixOutputs_T_98 = cat(cs_decoder_decoded_andMatrixOutputs_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_98) node cs_decoder_decoded_andMatrixOutputs_7_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_98) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55) node cs_decoder_decoded_andMatrixOutputs_lo_lo_89 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76) node cs_decoder_decoded_andMatrixOutputs_lo_hi_98 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51) node cs_decoder_decoded_andMatrixOutputs_lo_99 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_lo_89) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98) node cs_decoder_decoded_andMatrixOutputs_hi_lo_96 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99) node cs_decoder_decoded_andMatrixOutputs_hi_hi_99 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55) node cs_decoder_decoded_andMatrixOutputs_hi_99 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_lo_96) node _cs_decoder_decoded_andMatrixOutputs_T_99 = cat(cs_decoder_decoded_andMatrixOutputs_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_99) node cs_decoder_decoded_andMatrixOutputs_115_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_99) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56) node cs_decoder_decoded_andMatrixOutputs_lo_lo_90 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77) node cs_decoder_decoded_andMatrixOutputs_lo_hi_99 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52) node cs_decoder_decoded_andMatrixOutputs_lo_100 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_lo_90) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99) node cs_decoder_decoded_andMatrixOutputs_hi_lo_97 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100) node cs_decoder_decoded_andMatrixOutputs_hi_hi_100 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56) node cs_decoder_decoded_andMatrixOutputs_hi_100 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_97) node _cs_decoder_decoded_andMatrixOutputs_T_100 = cat(cs_decoder_decoded_andMatrixOutputs_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_100) node cs_decoder_decoded_andMatrixOutputs_92_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_100) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53) node cs_decoder_decoded_andMatrixOutputs_lo_lo_91 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65) node cs_decoder_decoded_andMatrixOutputs_lo_hi_100 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53) node cs_decoder_decoded_andMatrixOutputs_lo_101 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_91) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100) node cs_decoder_decoded_andMatrixOutputs_hi_lo_98 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101) node cs_decoder_decoded_andMatrixOutputs_hi_hi_101 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57) node cs_decoder_decoded_andMatrixOutputs_hi_101 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_98) node _cs_decoder_decoded_andMatrixOutputs_T_101 = cat(cs_decoder_decoded_andMatrixOutputs_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_101) node cs_decoder_decoded_andMatrixOutputs_40_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_101) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63) node cs_decoder_decoded_andMatrixOutputs_lo_lo_92 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92) node cs_decoder_decoded_andMatrixOutputs_lo_hi_101 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79) node cs_decoder_decoded_andMatrixOutputs_lo_102 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_lo_92) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102) node cs_decoder_decoded_andMatrixOutputs_hi_lo_99 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102) node cs_decoder_decoded_andMatrixOutputs_hi_hi_102 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102) node cs_decoder_decoded_andMatrixOutputs_hi_102 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_99) node _cs_decoder_decoded_andMatrixOutputs_T_102 = cat(cs_decoder_decoded_andMatrixOutputs_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_102) node cs_decoder_decoded_andMatrixOutputs_63_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_102) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54) node cs_decoder_decoded_andMatrixOutputs_lo_lo_93 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67) node cs_decoder_decoded_andMatrixOutputs_lo_hi_102 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54) node cs_decoder_decoded_andMatrixOutputs_lo_103 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_93) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102) node cs_decoder_decoded_andMatrixOutputs_hi_lo_100 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103) node cs_decoder_decoded_andMatrixOutputs_hi_hi_103 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58) node cs_decoder_decoded_andMatrixOutputs_hi_103 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_100) node _cs_decoder_decoded_andMatrixOutputs_T_103 = cat(cs_decoder_decoded_andMatrixOutputs_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_103) node cs_decoder_decoded_andMatrixOutputs_133_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_103) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55) node cs_decoder_decoded_andMatrixOutputs_lo_lo_94 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68) node cs_decoder_decoded_andMatrixOutputs_lo_hi_103 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55) node cs_decoder_decoded_andMatrixOutputs_lo_104 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_94) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103) node cs_decoder_decoded_andMatrixOutputs_hi_lo_101 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104) node cs_decoder_decoded_andMatrixOutputs_hi_hi_104 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59) node cs_decoder_decoded_andMatrixOutputs_hi_104 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_101) node _cs_decoder_decoded_andMatrixOutputs_T_104 = cat(cs_decoder_decoded_andMatrixOutputs_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_104) node cs_decoder_decoded_andMatrixOutputs_28_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_104) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56) node cs_decoder_decoded_andMatrixOutputs_lo_lo_95 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69) node cs_decoder_decoded_andMatrixOutputs_lo_hi_104 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56) node cs_decoder_decoded_andMatrixOutputs_lo_105 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_95) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104) node cs_decoder_decoded_andMatrixOutputs_hi_lo_102 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105) node cs_decoder_decoded_andMatrixOutputs_hi_hi_105 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60) node cs_decoder_decoded_andMatrixOutputs_hi_105 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_102) node _cs_decoder_decoded_andMatrixOutputs_T_105 = cat(cs_decoder_decoded_andMatrixOutputs_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_105) node cs_decoder_decoded_andMatrixOutputs_68_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_105) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57) node cs_decoder_decoded_andMatrixOutputs_lo_lo_96 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70) node cs_decoder_decoded_andMatrixOutputs_lo_hi_105 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57) node cs_decoder_decoded_andMatrixOutputs_lo_106 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_lo_96) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105) node cs_decoder_decoded_andMatrixOutputs_hi_lo_103 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106) node cs_decoder_decoded_andMatrixOutputs_hi_hi_106 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61) node cs_decoder_decoded_andMatrixOutputs_hi_106 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_103) node _cs_decoder_decoded_andMatrixOutputs_T_106 = cat(cs_decoder_decoded_andMatrixOutputs_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_106) node cs_decoder_decoded_andMatrixOutputs_11_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_106) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58) node cs_decoder_decoded_andMatrixOutputs_lo_lo_97 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71) node cs_decoder_decoded_andMatrixOutputs_lo_hi_106 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58) node cs_decoder_decoded_andMatrixOutputs_lo_107 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_97) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106) node cs_decoder_decoded_andMatrixOutputs_hi_lo_104 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107) node cs_decoder_decoded_andMatrixOutputs_hi_hi_107 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62) node cs_decoder_decoded_andMatrixOutputs_hi_107 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_104) node _cs_decoder_decoded_andMatrixOutputs_T_107 = cat(cs_decoder_decoded_andMatrixOutputs_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_107) node cs_decoder_decoded_andMatrixOutputs_74_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_107) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59) node cs_decoder_decoded_andMatrixOutputs_lo_lo_98 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72) node cs_decoder_decoded_andMatrixOutputs_lo_hi_107 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59) node cs_decoder_decoded_andMatrixOutputs_lo_108 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_98) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107) node cs_decoder_decoded_andMatrixOutputs_hi_lo_105 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108) node cs_decoder_decoded_andMatrixOutputs_hi_hi_108 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63) node cs_decoder_decoded_andMatrixOutputs_hi_108 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_105) node _cs_decoder_decoded_andMatrixOutputs_T_108 = cat(cs_decoder_decoded_andMatrixOutputs_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_108) node cs_decoder_decoded_andMatrixOutputs_139_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_108) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60) node cs_decoder_decoded_andMatrixOutputs_lo_lo_99 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73) node cs_decoder_decoded_andMatrixOutputs_lo_hi_108 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60) node cs_decoder_decoded_andMatrixOutputs_lo_109 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_99) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108) node cs_decoder_decoded_andMatrixOutputs_hi_lo_106 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109) node cs_decoder_decoded_andMatrixOutputs_hi_hi_109 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64) node cs_decoder_decoded_andMatrixOutputs_hi_109 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_106) node _cs_decoder_decoded_andMatrixOutputs_T_109 = cat(cs_decoder_decoded_andMatrixOutputs_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_109) node cs_decoder_decoded_andMatrixOutputs_156_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_109) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61) node cs_decoder_decoded_andMatrixOutputs_lo_lo_100 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74) node cs_decoder_decoded_andMatrixOutputs_lo_hi_109 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61) node cs_decoder_decoded_andMatrixOutputs_lo_110 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_100) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109) node cs_decoder_decoded_andMatrixOutputs_hi_lo_107 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110) node cs_decoder_decoded_andMatrixOutputs_hi_hi_110 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65) node cs_decoder_decoded_andMatrixOutputs_hi_110 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_107) node _cs_decoder_decoded_andMatrixOutputs_T_110 = cat(cs_decoder_decoded_andMatrixOutputs_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_110) node cs_decoder_decoded_andMatrixOutputs_38_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_110) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62) node cs_decoder_decoded_andMatrixOutputs_lo_lo_101 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75) node cs_decoder_decoded_andMatrixOutputs_lo_hi_110 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62) node cs_decoder_decoded_andMatrixOutputs_lo_111 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_101) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110) node cs_decoder_decoded_andMatrixOutputs_hi_lo_108 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111) node cs_decoder_decoded_andMatrixOutputs_hi_hi_111 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66) node cs_decoder_decoded_andMatrixOutputs_hi_111 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_108) node _cs_decoder_decoded_andMatrixOutputs_T_111 = cat(cs_decoder_decoded_andMatrixOutputs_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_111) node cs_decoder_decoded_andMatrixOutputs_116_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_111) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53) node cs_decoder_decoded_andMatrixOutputs_lo_lo_102 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73) node cs_decoder_decoded_andMatrixOutputs_lo_hi_111 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63) node cs_decoder_decoded_andMatrixOutputs_lo_112 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_102) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109) node cs_decoder_decoded_andMatrixOutputs_hi_lo_109 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112) node cs_decoder_decoded_andMatrixOutputs_hi_hi_112 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67) node cs_decoder_decoded_andMatrixOutputs_hi_112 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_109) node _cs_decoder_decoded_andMatrixOutputs_T_112 = cat(cs_decoder_decoded_andMatrixOutputs_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_112) node cs_decoder_decoded_andMatrixOutputs_4_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_112) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(cs_decoder_decoded_plaInput, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(cs_decoder_decoded_plaInput, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = bits(cs_decoder_decoded_plaInput, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12) node cs_decoder_decoded_andMatrixOutputs_lo_lo_103 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64) node cs_decoder_decoded_andMatrixOutputs_lo_hi_112 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64) node cs_decoder_decoded_andMatrixOutputs_lo_113 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_103) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90) node cs_decoder_decoded_andMatrixOutputs_hi_lo_110 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113) node cs_decoder_decoded_andMatrixOutputs_hi_hi_113 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68) node cs_decoder_decoded_andMatrixOutputs_hi_113 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_110) node _cs_decoder_decoded_andMatrixOutputs_T_113 = cat(cs_decoder_decoded_andMatrixOutputs_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_113) node cs_decoder_decoded_andMatrixOutputs_163_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_113) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65) node cs_decoder_decoded_andMatrixOutputs_lo_lo_104 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78) node cs_decoder_decoded_andMatrixOutputs_lo_hi_113 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65) node cs_decoder_decoded_andMatrixOutputs_lo_114 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_104) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113) node cs_decoder_decoded_andMatrixOutputs_hi_lo_111 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114) node cs_decoder_decoded_andMatrixOutputs_hi_hi_114 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69) node cs_decoder_decoded_andMatrixOutputs_hi_114 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_111) node _cs_decoder_decoded_andMatrixOutputs_T_114 = cat(cs_decoder_decoded_andMatrixOutputs_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_114) node cs_decoder_decoded_andMatrixOutputs_5_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_114) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66) node cs_decoder_decoded_andMatrixOutputs_lo_lo_105 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79) node cs_decoder_decoded_andMatrixOutputs_lo_hi_114 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66) node cs_decoder_decoded_andMatrixOutputs_lo_115 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_lo_105) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114) node cs_decoder_decoded_andMatrixOutputs_hi_lo_112 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115) node cs_decoder_decoded_andMatrixOutputs_hi_hi_115 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70) node cs_decoder_decoded_andMatrixOutputs_hi_115 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_112) node _cs_decoder_decoded_andMatrixOutputs_T_115 = cat(cs_decoder_decoded_andMatrixOutputs_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_115) node cs_decoder_decoded_andMatrixOutputs_22_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_115) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77) node cs_decoder_decoded_andMatrixOutputs_lo_lo_106 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106) node cs_decoder_decoded_andMatrixOutputs_lo_hi_115 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93) node cs_decoder_decoded_andMatrixOutputs_lo_116 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_lo_106) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116) node cs_decoder_decoded_andMatrixOutputs_hi_lo_113 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116) node cs_decoder_decoded_andMatrixOutputs_hi_hi_116 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116) node cs_decoder_decoded_andMatrixOutputs_hi_116 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_hi_lo_113) node _cs_decoder_decoded_andMatrixOutputs_T_116 = cat(cs_decoder_decoded_andMatrixOutputs_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_116) node cs_decoder_decoded_andMatrixOutputs_48_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_116) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67) node cs_decoder_decoded_andMatrixOutputs_lo_lo_107 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81) node cs_decoder_decoded_andMatrixOutputs_lo_hi_116 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67) node cs_decoder_decoded_andMatrixOutputs_lo_117 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_lo_107) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116) node cs_decoder_decoded_andMatrixOutputs_hi_lo_114 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117) node cs_decoder_decoded_andMatrixOutputs_hi_hi_117 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71) node cs_decoder_decoded_andMatrixOutputs_hi_117 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_lo_114) node _cs_decoder_decoded_andMatrixOutputs_T_117 = cat(cs_decoder_decoded_andMatrixOutputs_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_117) node cs_decoder_decoded_andMatrixOutputs_125_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_117) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68) node cs_decoder_decoded_andMatrixOutputs_lo_lo_108 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82) node cs_decoder_decoded_andMatrixOutputs_lo_hi_117 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68) node cs_decoder_decoded_andMatrixOutputs_lo_118 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_lo_108) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117) node cs_decoder_decoded_andMatrixOutputs_hi_lo_115 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118) node cs_decoder_decoded_andMatrixOutputs_hi_hi_118 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72) node cs_decoder_decoded_andMatrixOutputs_hi_118 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_lo_115) node _cs_decoder_decoded_andMatrixOutputs_T_118 = cat(cs_decoder_decoded_andMatrixOutputs_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_118) node cs_decoder_decoded_andMatrixOutputs_24_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_118) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69) node cs_decoder_decoded_andMatrixOutputs_lo_lo_109 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83) node cs_decoder_decoded_andMatrixOutputs_lo_hi_118 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69) node cs_decoder_decoded_andMatrixOutputs_lo_119 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_lo_109) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118) node cs_decoder_decoded_andMatrixOutputs_hi_lo_116 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119) node cs_decoder_decoded_andMatrixOutputs_hi_hi_119 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73) node cs_decoder_decoded_andMatrixOutputs_hi_119 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_lo_116) node _cs_decoder_decoded_andMatrixOutputs_T_119 = cat(cs_decoder_decoded_andMatrixOutputs_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_119) node cs_decoder_decoded_andMatrixOutputs_44_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_119) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70) node cs_decoder_decoded_andMatrixOutputs_lo_lo_110 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84) node cs_decoder_decoded_andMatrixOutputs_lo_hi_119 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70) node cs_decoder_decoded_andMatrixOutputs_lo_120 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_lo_110) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119) node cs_decoder_decoded_andMatrixOutputs_hi_lo_117 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120) node cs_decoder_decoded_andMatrixOutputs_hi_hi_120 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74) node cs_decoder_decoded_andMatrixOutputs_hi_120 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_lo_117) node _cs_decoder_decoded_andMatrixOutputs_T_120 = cat(cs_decoder_decoded_andMatrixOutputs_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_120) node cs_decoder_decoded_andMatrixOutputs_119_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_120) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71) node cs_decoder_decoded_andMatrixOutputs_lo_lo_111 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85) node cs_decoder_decoded_andMatrixOutputs_lo_hi_120 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71) node cs_decoder_decoded_andMatrixOutputs_lo_121 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_lo_111) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120) node cs_decoder_decoded_andMatrixOutputs_hi_lo_118 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121) node cs_decoder_decoded_andMatrixOutputs_hi_hi_121 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75) node cs_decoder_decoded_andMatrixOutputs_hi_121 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_lo_118) node _cs_decoder_decoded_andMatrixOutputs_T_121 = cat(cs_decoder_decoded_andMatrixOutputs_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_121) node cs_decoder_decoded_andMatrixOutputs_154_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_121) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72) node cs_decoder_decoded_andMatrixOutputs_lo_lo_112 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86) node cs_decoder_decoded_andMatrixOutputs_lo_hi_121 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72) node cs_decoder_decoded_andMatrixOutputs_lo_122 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_lo_112) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121) node cs_decoder_decoded_andMatrixOutputs_hi_lo_119 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122) node cs_decoder_decoded_andMatrixOutputs_hi_hi_122 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76) node cs_decoder_decoded_andMatrixOutputs_hi_122 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_lo_119) node _cs_decoder_decoded_andMatrixOutputs_T_122 = cat(cs_decoder_decoded_andMatrixOutputs_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_122) node cs_decoder_decoded_andMatrixOutputs_151_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_122) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73) node cs_decoder_decoded_andMatrixOutputs_lo_lo_113 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87) node cs_decoder_decoded_andMatrixOutputs_lo_hi_122 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73) node cs_decoder_decoded_andMatrixOutputs_lo_123 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_lo_113) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122) node cs_decoder_decoded_andMatrixOutputs_hi_lo_120 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123) node cs_decoder_decoded_andMatrixOutputs_hi_hi_123 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77) node cs_decoder_decoded_andMatrixOutputs_hi_123 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_lo_120) node _cs_decoder_decoded_andMatrixOutputs_T_123 = cat(cs_decoder_decoded_andMatrixOutputs_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_123) node cs_decoder_decoded_andMatrixOutputs_104_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_123) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74) node cs_decoder_decoded_andMatrixOutputs_lo_lo_114 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88) node cs_decoder_decoded_andMatrixOutputs_lo_hi_123 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74) node cs_decoder_decoded_andMatrixOutputs_lo_124 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_lo_114) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123) node cs_decoder_decoded_andMatrixOutputs_hi_lo_121 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124) node cs_decoder_decoded_andMatrixOutputs_hi_hi_124 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78) node cs_decoder_decoded_andMatrixOutputs_hi_124 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_lo_121) node _cs_decoder_decoded_andMatrixOutputs_T_124 = cat(cs_decoder_decoded_andMatrixOutputs_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_124) node cs_decoder_decoded_andMatrixOutputs_20_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_124) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75) node cs_decoder_decoded_andMatrixOutputs_lo_lo_115 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89) node cs_decoder_decoded_andMatrixOutputs_lo_hi_124 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75) node cs_decoder_decoded_andMatrixOutputs_lo_125 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_lo_115) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124) node cs_decoder_decoded_andMatrixOutputs_hi_lo_122 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125) node cs_decoder_decoded_andMatrixOutputs_hi_hi_125 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79) node cs_decoder_decoded_andMatrixOutputs_hi_125 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_lo_122) node _cs_decoder_decoded_andMatrixOutputs_T_125 = cat(cs_decoder_decoded_andMatrixOutputs_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_125) node cs_decoder_decoded_andMatrixOutputs_49_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_125) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76) node cs_decoder_decoded_andMatrixOutputs_lo_lo_116 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90) node cs_decoder_decoded_andMatrixOutputs_lo_hi_125 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76) node cs_decoder_decoded_andMatrixOutputs_lo_126 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_lo_116) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125) node cs_decoder_decoded_andMatrixOutputs_hi_lo_123 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126) node cs_decoder_decoded_andMatrixOutputs_hi_hi_126 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80) node cs_decoder_decoded_andMatrixOutputs_hi_126 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_lo_123) node _cs_decoder_decoded_andMatrixOutputs_T_126 = cat(cs_decoder_decoded_andMatrixOutputs_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_126) node cs_decoder_decoded_andMatrixOutputs_122_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_126) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77) node cs_decoder_decoded_andMatrixOutputs_lo_lo_117 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91) node cs_decoder_decoded_andMatrixOutputs_lo_hi_126 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77) node cs_decoder_decoded_andMatrixOutputs_lo_127 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_lo_117) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126) node cs_decoder_decoded_andMatrixOutputs_hi_lo_124 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127) node cs_decoder_decoded_andMatrixOutputs_hi_hi_127 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81) node cs_decoder_decoded_andMatrixOutputs_hi_127 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_lo_124) node _cs_decoder_decoded_andMatrixOutputs_T_127 = cat(cs_decoder_decoded_andMatrixOutputs_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_127) node cs_decoder_decoded_andMatrixOutputs_12_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_127) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68) node cs_decoder_decoded_andMatrixOutputs_lo_lo_118 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89) node cs_decoder_decoded_andMatrixOutputs_lo_hi_127 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78) node cs_decoder_decoded_andMatrixOutputs_lo_128 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_lo_118) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125) node cs_decoder_decoded_andMatrixOutputs_hi_lo_125 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128) node cs_decoder_decoded_andMatrixOutputs_hi_hi_128 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82) node cs_decoder_decoded_andMatrixOutputs_hi_128 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_lo_125) node _cs_decoder_decoded_andMatrixOutputs_T_128 = cat(cs_decoder_decoded_andMatrixOutputs_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_128) node cs_decoder_decoded_andMatrixOutputs_41_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_128) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = bits(cs_decoder_decoded_plaInput, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37) node cs_decoder_decoded_andMatrixOutputs_lo_lo_119 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88) node cs_decoder_decoded_andMatrixOutputs_lo_hi_128 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79) node cs_decoder_decoded_andMatrixOutputs_lo_129 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_lo_119) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126) node cs_decoder_decoded_andMatrixOutputs_hi_lo_126 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129) node cs_decoder_decoded_andMatrixOutputs_hi_hi_129 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83) node cs_decoder_decoded_andMatrixOutputs_hi_129 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_lo_126) node _cs_decoder_decoded_andMatrixOutputs_T_129 = cat(cs_decoder_decoded_andMatrixOutputs_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_129) node cs_decoder_decoded_andMatrixOutputs_152_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_129) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = bits(cs_decoder_decoded_plaInput, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20) node cs_decoder_decoded_andMatrixOutputs_lo_lo_120 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84) node cs_decoder_decoded_andMatrixOutputs_lo_hi_129 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80) node cs_decoder_decoded_andMatrixOutputs_lo_130 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_lo_120) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120) node cs_decoder_decoded_andMatrixOutputs_hi_lo_127 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130) node cs_decoder_decoded_andMatrixOutputs_hi_hi_130 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84) node cs_decoder_decoded_andMatrixOutputs_hi_130 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_lo_127) node _cs_decoder_decoded_andMatrixOutputs_T_130 = cat(cs_decoder_decoded_andMatrixOutputs_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_130) node cs_decoder_decoded_andMatrixOutputs_23_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_130) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39) node cs_decoder_decoded_andMatrixOutputs_lo_lo_121 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90) node cs_decoder_decoded_andMatrixOutputs_lo_hi_130 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81) node cs_decoder_decoded_andMatrixOutputs_lo_131 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_lo_121) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128) node cs_decoder_decoded_andMatrixOutputs_hi_lo_128 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131) node cs_decoder_decoded_andMatrixOutputs_hi_hi_131 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85) node cs_decoder_decoded_andMatrixOutputs_hi_131 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_lo_128) node _cs_decoder_decoded_andMatrixOutputs_T_131 = cat(cs_decoder_decoded_andMatrixOutputs_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_131) node cs_decoder_decoded_andMatrixOutputs_98_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_131) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22) node cs_decoder_decoded_andMatrixOutputs_lo_lo_122 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86) node cs_decoder_decoded_andMatrixOutputs_lo_hi_131 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82) node cs_decoder_decoded_andMatrixOutputs_lo_132 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_lo_122) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122) node cs_decoder_decoded_andMatrixOutputs_hi_lo_129 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132) node cs_decoder_decoded_andMatrixOutputs_hi_hi_132 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86) node cs_decoder_decoded_andMatrixOutputs_hi_132 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_hi_lo_129) node _cs_decoder_decoded_andMatrixOutputs_T_132 = cat(cs_decoder_decoded_andMatrixOutputs_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_132) node cs_decoder_decoded_andMatrixOutputs_15_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_132) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83) node cs_decoder_decoded_andMatrixOutputs_lo_lo_123 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97) node cs_decoder_decoded_andMatrixOutputs_lo_hi_132 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83) node cs_decoder_decoded_andMatrixOutputs_lo_133 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_lo_123) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132) node cs_decoder_decoded_andMatrixOutputs_hi_lo_130 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133) node cs_decoder_decoded_andMatrixOutputs_hi_hi_133 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87) node cs_decoder_decoded_andMatrixOutputs_hi_133 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_lo_130) node _cs_decoder_decoded_andMatrixOutputs_T_133 = cat(cs_decoder_decoded_andMatrixOutputs_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_133) node cs_decoder_decoded_andMatrixOutputs_36_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_133) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84) node cs_decoder_decoded_andMatrixOutputs_lo_lo_124 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98) node cs_decoder_decoded_andMatrixOutputs_lo_hi_133 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84) node cs_decoder_decoded_andMatrixOutputs_lo_134 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_lo_124) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133) node cs_decoder_decoded_andMatrixOutputs_hi_lo_131 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134) node cs_decoder_decoded_andMatrixOutputs_hi_hi_134 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88) node cs_decoder_decoded_andMatrixOutputs_hi_134 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_lo_131) node _cs_decoder_decoded_andMatrixOutputs_T_134 = cat(cs_decoder_decoded_andMatrixOutputs_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_134) node cs_decoder_decoded_andMatrixOutputs_46_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_134) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85) node cs_decoder_decoded_andMatrixOutputs_lo_lo_125 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99) node cs_decoder_decoded_andMatrixOutputs_lo_hi_134 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85) node cs_decoder_decoded_andMatrixOutputs_lo_135 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_lo_125) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134) node cs_decoder_decoded_andMatrixOutputs_hi_lo_132 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135) node cs_decoder_decoded_andMatrixOutputs_hi_hi_135 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89) node cs_decoder_decoded_andMatrixOutputs_hi_135 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_lo_132) node _cs_decoder_decoded_andMatrixOutputs_T_135 = cat(cs_decoder_decoded_andMatrixOutputs_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_135) node cs_decoder_decoded_andMatrixOutputs_55_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_135) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76) node cs_decoder_decoded_andMatrixOutputs_lo_lo_126 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97) node cs_decoder_decoded_andMatrixOutputs_lo_hi_135 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86) node cs_decoder_decoded_andMatrixOutputs_lo_136 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_lo_126) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133) node cs_decoder_decoded_andMatrixOutputs_hi_lo_133 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136) node cs_decoder_decoded_andMatrixOutputs_hi_hi_136 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90) node cs_decoder_decoded_andMatrixOutputs_hi_136 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_lo_133) node _cs_decoder_decoded_andMatrixOutputs_T_136 = cat(cs_decoder_decoded_andMatrixOutputs_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_136) node cs_decoder_decoded_andMatrixOutputs_159_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_136) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44) node cs_decoder_decoded_andMatrixOutputs_lo_lo_127 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96) node cs_decoder_decoded_andMatrixOutputs_lo_hi_136 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87) node cs_decoder_decoded_andMatrixOutputs_lo_137 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_lo_127) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134) node cs_decoder_decoded_andMatrixOutputs_hi_lo_134 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137) node cs_decoder_decoded_andMatrixOutputs_hi_hi_137 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91) node cs_decoder_decoded_andMatrixOutputs_hi_137 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_lo_134) node _cs_decoder_decoded_andMatrixOutputs_T_137 = cat(cs_decoder_decoded_andMatrixOutputs_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_137) node cs_decoder_decoded_andMatrixOutputs_117_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_137) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25) node cs_decoder_decoded_andMatrixOutputs_lo_lo_128 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92) node cs_decoder_decoded_andMatrixOutputs_lo_hi_137 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88) node cs_decoder_decoded_andMatrixOutputs_lo_138 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_lo_128) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128) node cs_decoder_decoded_andMatrixOutputs_hi_lo_135 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138) node cs_decoder_decoded_andMatrixOutputs_hi_hi_138 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92) node cs_decoder_decoded_andMatrixOutputs_hi_138 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_lo_135) node _cs_decoder_decoded_andMatrixOutputs_T_138 = cat(cs_decoder_decoded_andMatrixOutputs_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_138) node cs_decoder_decoded_andMatrixOutputs_109_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_138) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79) node cs_decoder_decoded_andMatrixOutputs_lo_lo_129 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100) node cs_decoder_decoded_andMatrixOutputs_lo_hi_138 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89) node cs_decoder_decoded_andMatrixOutputs_lo_139 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_lo_129) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136) node cs_decoder_decoded_andMatrixOutputs_hi_lo_136 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139) node cs_decoder_decoded_andMatrixOutputs_hi_hi_139 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93) node cs_decoder_decoded_andMatrixOutputs_hi_139 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_lo_136) node _cs_decoder_decoded_andMatrixOutputs_T_139 = cat(cs_decoder_decoded_andMatrixOutputs_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_139) node cs_decoder_decoded_andMatrixOutputs_128_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_139) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80) node cs_decoder_decoded_andMatrixOutputs_lo_lo_130 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101) node cs_decoder_decoded_andMatrixOutputs_lo_hi_139 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90) node cs_decoder_decoded_andMatrixOutputs_lo_140 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_lo_130) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137) node cs_decoder_decoded_andMatrixOutputs_hi_lo_137 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140) node cs_decoder_decoded_andMatrixOutputs_hi_hi_140 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94) node cs_decoder_decoded_andMatrixOutputs_hi_140 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_lo_137) node _cs_decoder_decoded_andMatrixOutputs_T_140 = cat(cs_decoder_decoded_andMatrixOutputs_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_140) node cs_decoder_decoded_andMatrixOutputs_2_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_140) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81) node cs_decoder_decoded_andMatrixOutputs_lo_lo_131 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102) node cs_decoder_decoded_andMatrixOutputs_lo_hi_140 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91) node cs_decoder_decoded_andMatrixOutputs_lo_141 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_lo_131) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138) node cs_decoder_decoded_andMatrixOutputs_hi_lo_138 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141) node cs_decoder_decoded_andMatrixOutputs_hi_hi_141 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95) node cs_decoder_decoded_andMatrixOutputs_hi_141 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_lo_138) node _cs_decoder_decoded_andMatrixOutputs_T_141 = cat(cs_decoder_decoded_andMatrixOutputs_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_141) node cs_decoder_decoded_andMatrixOutputs_83_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_141) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20) node cs_decoder_decoded_andMatrixOutputs_lo_lo_132 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96) node cs_decoder_decoded_andMatrixOutputs_lo_hi_141 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92) node cs_decoder_decoded_andMatrixOutputs_lo_142 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_lo_132) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132) node cs_decoder_decoded_andMatrixOutputs_hi_lo_139 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142) node cs_decoder_decoded_andMatrixOutputs_hi_hi_142 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96) node cs_decoder_decoded_andMatrixOutputs_hi_142 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_lo_139) node _cs_decoder_decoded_andMatrixOutputs_T_142 = cat(cs_decoder_decoded_andMatrixOutputs_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_142) node cs_decoder_decoded_andMatrixOutputs_87_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_142) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21) node cs_decoder_decoded_andMatrixOutputs_lo_lo_133 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97) node cs_decoder_decoded_andMatrixOutputs_lo_hi_142 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93) node cs_decoder_decoded_andMatrixOutputs_lo_143 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_lo_133) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133) node cs_decoder_decoded_andMatrixOutputs_hi_lo_140 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143) node cs_decoder_decoded_andMatrixOutputs_hi_hi_143 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97) node cs_decoder_decoded_andMatrixOutputs_hi_143 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_143, cs_decoder_decoded_andMatrixOutputs_hi_lo_140) node _cs_decoder_decoded_andMatrixOutputs_T_143 = cat(cs_decoder_decoded_andMatrixOutputs_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_143) node cs_decoder_decoded_andMatrixOutputs_158_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_143) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19) node cs_decoder_decoded_andMatrixOutputs_lo_lo_134 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94) node cs_decoder_decoded_andMatrixOutputs_lo_hi_143 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94) node cs_decoder_decoded_andMatrixOutputs_lo_144 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_lo_134) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121) node cs_decoder_decoded_andMatrixOutputs_hi_lo_141 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144) node cs_decoder_decoded_andMatrixOutputs_hi_hi_144 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98) node cs_decoder_decoded_andMatrixOutputs_hi_144 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_144, cs_decoder_decoded_andMatrixOutputs_hi_lo_141) node _cs_decoder_decoded_andMatrixOutputs_T_144 = cat(cs_decoder_decoded_andMatrixOutputs_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_144) node cs_decoder_decoded_andMatrixOutputs_19_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_144) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23) node cs_decoder_decoded_andMatrixOutputs_lo_lo_135 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99) node cs_decoder_decoded_andMatrixOutputs_lo_hi_144 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95) node cs_decoder_decoded_andMatrixOutputs_lo_145 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_lo_135) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135) node cs_decoder_decoded_andMatrixOutputs_hi_lo_142 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_85) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145) node cs_decoder_decoded_andMatrixOutputs_hi_hi_145 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99) node cs_decoder_decoded_andMatrixOutputs_hi_145 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_145, cs_decoder_decoded_andMatrixOutputs_hi_lo_142) node _cs_decoder_decoded_andMatrixOutputs_T_145 = cat(cs_decoder_decoded_andMatrixOutputs_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_145) node cs_decoder_decoded_andMatrixOutputs_91_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_145) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96) node cs_decoder_decoded_andMatrixOutputs_lo_lo_136 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110) node cs_decoder_decoded_andMatrixOutputs_lo_hi_145 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96) node cs_decoder_decoded_andMatrixOutputs_lo_146 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_lo_136) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145) node cs_decoder_decoded_andMatrixOutputs_hi_lo_143 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_86) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146) node cs_decoder_decoded_andMatrixOutputs_hi_hi_146 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100) node cs_decoder_decoded_andMatrixOutputs_hi_146 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_146, cs_decoder_decoded_andMatrixOutputs_hi_lo_143) node _cs_decoder_decoded_andMatrixOutputs_T_146 = cat(cs_decoder_decoded_andMatrixOutputs_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_146) node cs_decoder_decoded_andMatrixOutputs_70_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_146) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97) node cs_decoder_decoded_andMatrixOutputs_lo_lo_137 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111) node cs_decoder_decoded_andMatrixOutputs_lo_hi_146 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_97) node cs_decoder_decoded_andMatrixOutputs_lo_147 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_lo_137) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146) node cs_decoder_decoded_andMatrixOutputs_hi_lo_144 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_87) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147) node cs_decoder_decoded_andMatrixOutputs_hi_hi_147 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101) node cs_decoder_decoded_andMatrixOutputs_hi_147 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_147, cs_decoder_decoded_andMatrixOutputs_hi_lo_144) node _cs_decoder_decoded_andMatrixOutputs_T_147 = cat(cs_decoder_decoded_andMatrixOutputs_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_147) node cs_decoder_decoded_andMatrixOutputs_53_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_147) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98) node cs_decoder_decoded_andMatrixOutputs_lo_lo_138 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112) node cs_decoder_decoded_andMatrixOutputs_lo_hi_147 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_98) node cs_decoder_decoded_andMatrixOutputs_lo_148 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_lo_138) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147) node cs_decoder_decoded_andMatrixOutputs_hi_lo_145 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_88) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148) node cs_decoder_decoded_andMatrixOutputs_hi_hi_148 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102) node cs_decoder_decoded_andMatrixOutputs_hi_148 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_148, cs_decoder_decoded_andMatrixOutputs_hi_lo_145) node _cs_decoder_decoded_andMatrixOutputs_T_148 = cat(cs_decoder_decoded_andMatrixOutputs_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_148) node cs_decoder_decoded_andMatrixOutputs_126_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_148) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99) node cs_decoder_decoded_andMatrixOutputs_lo_lo_139 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113) node cs_decoder_decoded_andMatrixOutputs_lo_hi_148 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_99) node cs_decoder_decoded_andMatrixOutputs_lo_149 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_lo_139) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148) node cs_decoder_decoded_andMatrixOutputs_hi_lo_146 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_89) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149) node cs_decoder_decoded_andMatrixOutputs_hi_hi_149 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103) node cs_decoder_decoded_andMatrixOutputs_hi_149 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_149, cs_decoder_decoded_andMatrixOutputs_hi_lo_146) node _cs_decoder_decoded_andMatrixOutputs_T_149 = cat(cs_decoder_decoded_andMatrixOutputs_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_149) node cs_decoder_decoded_andMatrixOutputs_150_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_149) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = bits(cs_decoder_decoded_invInputs, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100) node cs_decoder_decoded_andMatrixOutputs_lo_lo_140 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114) node cs_decoder_decoded_andMatrixOutputs_lo_hi_149 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_100) node cs_decoder_decoded_andMatrixOutputs_lo_150 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_lo_140) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149) node cs_decoder_decoded_andMatrixOutputs_hi_lo_147 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_90) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150) node cs_decoder_decoded_andMatrixOutputs_hi_hi_150 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104) node cs_decoder_decoded_andMatrixOutputs_hi_150 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_150, cs_decoder_decoded_andMatrixOutputs_hi_lo_147) node _cs_decoder_decoded_andMatrixOutputs_T_150 = cat(cs_decoder_decoded_andMatrixOutputs_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_150) node cs_decoder_decoded_andMatrixOutputs_31_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_150) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = bits(cs_decoder_decoded_plaInput, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = bits(cs_decoder_decoded_plaInput, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = bits(cs_decoder_decoded_plaInput, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = bits(cs_decoder_decoded_plaInput, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_12 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_12) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17) node cs_decoder_decoded_andMatrixOutputs_lo_lo_141 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101) node cs_decoder_decoded_andMatrixOutputs_lo_hi_150 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_101) node cs_decoder_decoded_andMatrixOutputs_lo_151 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_lo_141) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128) node cs_decoder_decoded_andMatrixOutputs_hi_lo_148 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_91) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151) node cs_decoder_decoded_andMatrixOutputs_hi_hi_151 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105) node cs_decoder_decoded_andMatrixOutputs_hi_151 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_151, cs_decoder_decoded_andMatrixOutputs_hi_lo_148) node _cs_decoder_decoded_andMatrixOutputs_T_151 = cat(cs_decoder_decoded_andMatrixOutputs_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_151) node cs_decoder_decoded_andMatrixOutputs_106_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_151) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = bits(cs_decoder_decoded_invInputs, 7, 7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = bits(cs_decoder_decoded_invInputs, 8, 8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = bits(cs_decoder_decoded_invInputs, 9, 9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = bits(cs_decoder_decoded_invInputs, 10, 10) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = bits(cs_decoder_decoded_invInputs, 11, 11) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = bits(cs_decoder_decoded_invInputs, 15, 15) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = bits(cs_decoder_decoded_invInputs, 16, 16) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = bits(cs_decoder_decoded_invInputs, 17, 17) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = bits(cs_decoder_decoded_invInputs, 18, 18) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = bits(cs_decoder_decoded_invInputs, 19, 19) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = bits(cs_decoder_decoded_plaInput, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = bits(cs_decoder_decoded_plaInput, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_13 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_9 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_9 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_9 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_9 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_9) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_9) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_13) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_9) node cs_decoder_decoded_andMatrixOutputs_lo_lo_142 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_58) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_9) node cs_decoder_decoded_andMatrixOutputs_lo_hi_151 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_102) node cs_decoder_decoded_andMatrixOutputs_lo_152 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_lo_142) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116) node cs_decoder_decoded_andMatrixOutputs_hi_lo_149 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_92) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_9) node cs_decoder_decoded_andMatrixOutputs_hi_hi_152 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106) node cs_decoder_decoded_andMatrixOutputs_hi_152 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_152, cs_decoder_decoded_andMatrixOutputs_hi_lo_149) node _cs_decoder_decoded_andMatrixOutputs_T_152 = cat(cs_decoder_decoded_andMatrixOutputs_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_152) node cs_decoder_decoded_andMatrixOutputs_78_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_152) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = bits(cs_decoder_decoded_invInputs, 7, 7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = bits(cs_decoder_decoded_invInputs, 8, 8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = bits(cs_decoder_decoded_invInputs, 9, 9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = bits(cs_decoder_decoded_invInputs, 10, 10) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = bits(cs_decoder_decoded_invInputs, 11, 11) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = bits(cs_decoder_decoded_invInputs, 15, 15) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = bits(cs_decoder_decoded_invInputs, 16, 16) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = bits(cs_decoder_decoded_invInputs, 17, 17) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = bits(cs_decoder_decoded_invInputs, 18, 18) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = bits(cs_decoder_decoded_invInputs, 19, 19) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = bits(cs_decoder_decoded_plaInput, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = bits(cs_decoder_decoded_plaInput, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_14 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_10 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_10 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_10 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_10 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_10) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_10) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6) node cs_decoder_decoded_andMatrixOutputs_lo_lo_143 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_59) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_10) node cs_decoder_decoded_andMatrixOutputs_lo_hi_152 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_103) node cs_decoder_decoded_andMatrixOutputs_lo_153 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_lo_143) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6) node cs_decoder_decoded_andMatrixOutputs_hi_lo_150 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_93) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_10) node cs_decoder_decoded_andMatrixOutputs_hi_hi_153 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107) node cs_decoder_decoded_andMatrixOutputs_hi_153 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_153, cs_decoder_decoded_andMatrixOutputs_hi_lo_150) node _cs_decoder_decoded_andMatrixOutputs_T_153 = cat(cs_decoder_decoded_andMatrixOutputs_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_153) node cs_decoder_decoded_andMatrixOutputs_64_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_153) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = bits(cs_decoder_decoded_invInputs, 7, 7) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = bits(cs_decoder_decoded_invInputs, 8, 8) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = bits(cs_decoder_decoded_invInputs, 9, 9) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = bits(cs_decoder_decoded_invInputs, 10, 10) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = bits(cs_decoder_decoded_invInputs, 11, 11) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = bits(cs_decoder_decoded_invInputs, 15, 15) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = bits(cs_decoder_decoded_invInputs, 16, 16) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = bits(cs_decoder_decoded_invInputs, 17, 17) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = bits(cs_decoder_decoded_invInputs, 18, 18) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = bits(cs_decoder_decoded_invInputs, 19, 19) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_15 = bits(cs_decoder_decoded_plaInput, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_11 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_11 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_11 = bits(cs_decoder_decoded_plaInput, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_11 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = bits(cs_decoder_decoded_plaInput, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1 = bits(cs_decoder_decoded_invInputs, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_11) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7) node cs_decoder_decoded_andMatrixOutputs_lo_lo_144 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_60) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_11) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_15) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_11) node cs_decoder_decoded_andMatrixOutputs_lo_hi_153 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_104) node cs_decoder_decoded_andMatrixOutputs_lo_154 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_lo_144) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7) node cs_decoder_decoded_andMatrixOutputs_hi_lo_151 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_94) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_11) node cs_decoder_decoded_andMatrixOutputs_hi_hi_154 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_108) node cs_decoder_decoded_andMatrixOutputs_hi_154 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_154, cs_decoder_decoded_andMatrixOutputs_hi_lo_151) node _cs_decoder_decoded_andMatrixOutputs_T_154 = cat(cs_decoder_decoded_andMatrixOutputs_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_154) node cs_decoder_decoded_andMatrixOutputs_103_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_154) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = bits(cs_decoder_decoded_plaInput, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = bits(cs_decoder_decoded_plaInput, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = bits(cs_decoder_decoded_invInputs, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = bits(cs_decoder_decoded_plaInput, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = bits(cs_decoder_decoded_invInputs, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = bits(cs_decoder_decoded_plaInput, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = bits(cs_decoder_decoded_plaInput, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116) node cs_decoder_decoded_andMatrixOutputs_lo_lo_145 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145) node cs_decoder_decoded_andMatrixOutputs_lo_hi_154 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132) node cs_decoder_decoded_andMatrixOutputs_lo_155 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_lo_145) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155) node cs_decoder_decoded_andMatrixOutputs_hi_lo_152 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155) node cs_decoder_decoded_andMatrixOutputs_hi_hi_155 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155) node cs_decoder_decoded_andMatrixOutputs_hi_155 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_155, cs_decoder_decoded_andMatrixOutputs_hi_lo_152) node _cs_decoder_decoded_andMatrixOutputs_T_155 = cat(cs_decoder_decoded_andMatrixOutputs_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_155) node cs_decoder_decoded_andMatrixOutputs_147_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_155) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = bits(cs_decoder_decoded_plaInput, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105) node cs_decoder_decoded_andMatrixOutputs_lo_lo_146 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120) node cs_decoder_decoded_andMatrixOutputs_lo_hi_155 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_105) node cs_decoder_decoded_andMatrixOutputs_lo_156 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_lo_146) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155) node cs_decoder_decoded_andMatrixOutputs_hi_lo_153 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_95) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156) node cs_decoder_decoded_andMatrixOutputs_hi_hi_156 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_109) node cs_decoder_decoded_andMatrixOutputs_hi_156 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_156, cs_decoder_decoded_andMatrixOutputs_hi_lo_153) node _cs_decoder_decoded_andMatrixOutputs_T_156 = cat(cs_decoder_decoded_andMatrixOutputs_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_156) node cs_decoder_decoded_andMatrixOutputs_142_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_156) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = bits(cs_decoder_decoded_invInputs, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = bits(cs_decoder_decoded_plaInput, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106) node cs_decoder_decoded_andMatrixOutputs_lo_lo_147 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121) node cs_decoder_decoded_andMatrixOutputs_lo_hi_156 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_106) node cs_decoder_decoded_andMatrixOutputs_lo_157 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_lo_147) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156) node cs_decoder_decoded_andMatrixOutputs_hi_lo_154 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_96) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157) node cs_decoder_decoded_andMatrixOutputs_hi_hi_157 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_110) node cs_decoder_decoded_andMatrixOutputs_hi_157 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_157, cs_decoder_decoded_andMatrixOutputs_hi_lo_154) node _cs_decoder_decoded_andMatrixOutputs_T_157 = cat(cs_decoder_decoded_andMatrixOutputs_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_157) node cs_decoder_decoded_andMatrixOutputs_130_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_157) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = bits(cs_decoder_decoded_plaInput, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107) node cs_decoder_decoded_andMatrixOutputs_lo_lo_148 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_61) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122) node cs_decoder_decoded_andMatrixOutputs_lo_hi_157 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_107) node cs_decoder_decoded_andMatrixOutputs_lo_158 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_lo_148) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157) node cs_decoder_decoded_andMatrixOutputs_hi_lo_155 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_97) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158) node cs_decoder_decoded_andMatrixOutputs_hi_hi_158 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_111) node cs_decoder_decoded_andMatrixOutputs_hi_158 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_158, cs_decoder_decoded_andMatrixOutputs_hi_lo_155) node _cs_decoder_decoded_andMatrixOutputs_T_158 = cat(cs_decoder_decoded_andMatrixOutputs_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_158) node cs_decoder_decoded_andMatrixOutputs_32_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_158) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = bits(cs_decoder_decoded_plaInput, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108) node cs_decoder_decoded_andMatrixOutputs_lo_lo_149 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123) node cs_decoder_decoded_andMatrixOutputs_lo_hi_158 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_108) node cs_decoder_decoded_andMatrixOutputs_lo_159 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_lo_149) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158) node cs_decoder_decoded_andMatrixOutputs_hi_lo_156 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_98) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159) node cs_decoder_decoded_andMatrixOutputs_hi_hi_159 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_112) node cs_decoder_decoded_andMatrixOutputs_hi_159 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_159, cs_decoder_decoded_andMatrixOutputs_hi_lo_156) node _cs_decoder_decoded_andMatrixOutputs_T_159 = cat(cs_decoder_decoded_andMatrixOutputs_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_159) node cs_decoder_decoded_andMatrixOutputs_94_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_159) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = bits(cs_decoder_decoded_plaInput, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109) node cs_decoder_decoded_andMatrixOutputs_lo_lo_150 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_62) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124) node cs_decoder_decoded_andMatrixOutputs_lo_hi_159 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_109) node cs_decoder_decoded_andMatrixOutputs_lo_160 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_lo_150) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159) node cs_decoder_decoded_andMatrixOutputs_hi_lo_157 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_99) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160) node cs_decoder_decoded_andMatrixOutputs_hi_hi_160 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_113) node cs_decoder_decoded_andMatrixOutputs_hi_160 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_160, cs_decoder_decoded_andMatrixOutputs_hi_lo_157) node _cs_decoder_decoded_andMatrixOutputs_T_160 = cat(cs_decoder_decoded_andMatrixOutputs_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_160) node cs_decoder_decoded_andMatrixOutputs_84_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_160) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = bits(cs_decoder_decoded_plaInput, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110) node cs_decoder_decoded_andMatrixOutputs_lo_lo_151 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_63) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125) node cs_decoder_decoded_andMatrixOutputs_lo_hi_160 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_110) node cs_decoder_decoded_andMatrixOutputs_lo_161 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_lo_151) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160) node cs_decoder_decoded_andMatrixOutputs_hi_lo_158 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_100) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161) node cs_decoder_decoded_andMatrixOutputs_hi_hi_161 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_114) node cs_decoder_decoded_andMatrixOutputs_hi_161 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_161, cs_decoder_decoded_andMatrixOutputs_hi_lo_158) node _cs_decoder_decoded_andMatrixOutputs_T_161 = cat(cs_decoder_decoded_andMatrixOutputs_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_161) node cs_decoder_decoded_andMatrixOutputs_101_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_161) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = bits(cs_decoder_decoded_invInputs, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = bits(cs_decoder_decoded_plaInput, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111) node cs_decoder_decoded_andMatrixOutputs_lo_lo_152 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_64) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126) node cs_decoder_decoded_andMatrixOutputs_lo_hi_161 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_111) node cs_decoder_decoded_andMatrixOutputs_lo_162 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_lo_152) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161) node cs_decoder_decoded_andMatrixOutputs_hi_lo_159 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_101) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162) node cs_decoder_decoded_andMatrixOutputs_hi_hi_162 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_115) node cs_decoder_decoded_andMatrixOutputs_hi_162 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_162, cs_decoder_decoded_andMatrixOutputs_hi_lo_159) node _cs_decoder_decoded_andMatrixOutputs_T_162 = cat(cs_decoder_decoded_andMatrixOutputs_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_162) node cs_decoder_decoded_andMatrixOutputs_132_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_162) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = bits(cs_decoder_decoded_plaInput, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28) node cs_decoder_decoded_andMatrixOutputs_lo_lo_153 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_65) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116) node cs_decoder_decoded_andMatrixOutputs_lo_hi_162 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_112) node cs_decoder_decoded_andMatrixOutputs_lo_163 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_lo_153) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153) node cs_decoder_decoded_andMatrixOutputs_hi_lo_160 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_102) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163) node cs_decoder_decoded_andMatrixOutputs_hi_hi_163 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_116) node cs_decoder_decoded_andMatrixOutputs_hi_163 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_163, cs_decoder_decoded_andMatrixOutputs_hi_lo_160) node _cs_decoder_decoded_andMatrixOutputs_T_163 = cat(cs_decoder_decoded_andMatrixOutputs_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_163) node cs_decoder_decoded_andMatrixOutputs_90_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_163) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = bits(cs_decoder_decoded_plaInput, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29) node cs_decoder_decoded_andMatrixOutputs_lo_lo_154 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_66) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117) node cs_decoder_decoded_andMatrixOutputs_lo_hi_163 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_113) node cs_decoder_decoded_andMatrixOutputs_lo_164 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_lo_154) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154) node cs_decoder_decoded_andMatrixOutputs_hi_lo_161 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_103) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164) node cs_decoder_decoded_andMatrixOutputs_hi_hi_164 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_117) node cs_decoder_decoded_andMatrixOutputs_hi_164 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_164, cs_decoder_decoded_andMatrixOutputs_hi_lo_161) node _cs_decoder_decoded_andMatrixOutputs_T_164 = cat(cs_decoder_decoded_andMatrixOutputs_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_164) node cs_decoder_decoded_andMatrixOutputs_27_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_164) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_27 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_17 = bits(cs_decoder_decoded_plaInput, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_17) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_27) node cs_decoder_decoded_andMatrixOutputs_lo_lo_155 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_67) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114) node cs_decoder_decoded_andMatrixOutputs_lo_hi_164 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_114) node cs_decoder_decoded_andMatrixOutputs_lo_165 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_lo_155) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142) node cs_decoder_decoded_andMatrixOutputs_hi_lo_162 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_104) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165) node cs_decoder_decoded_andMatrixOutputs_hi_hi_165 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_118) node cs_decoder_decoded_andMatrixOutputs_hi_165 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_165, cs_decoder_decoded_andMatrixOutputs_hi_lo_162) node _cs_decoder_decoded_andMatrixOutputs_T_165 = cat(cs_decoder_decoded_andMatrixOutputs_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_165) node cs_decoder_decoded_andMatrixOutputs_148_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_165) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_28 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_18 = bits(cs_decoder_decoded_plaInput, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_18) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_28) node cs_decoder_decoded_andMatrixOutputs_lo_lo_156 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_68) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115) node cs_decoder_decoded_andMatrixOutputs_lo_hi_165 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_115) node cs_decoder_decoded_andMatrixOutputs_lo_166 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_lo_156) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143) node cs_decoder_decoded_andMatrixOutputs_hi_lo_163 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_105) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166) node cs_decoder_decoded_andMatrixOutputs_hi_hi_166 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_119) node cs_decoder_decoded_andMatrixOutputs_hi_166 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_166, cs_decoder_decoded_andMatrixOutputs_hi_lo_163) node _cs_decoder_decoded_andMatrixOutputs_T_166 = cat(cs_decoder_decoded_andMatrixOutputs_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_166) node cs_decoder_decoded_andMatrixOutputs_67_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_166) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = bits(cs_decoder_decoded_plaInput, 25, 25) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = bits(cs_decoder_decoded_invInputs, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_29 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_25 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_19 = bits(cs_decoder_decoded_plaInput, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_19) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_29) node cs_decoder_decoded_andMatrixOutputs_lo_lo_157 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_69) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116) node cs_decoder_decoded_andMatrixOutputs_lo_hi_166 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_116) node cs_decoder_decoded_andMatrixOutputs_lo_167 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_lo_157) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144) node cs_decoder_decoded_andMatrixOutputs_hi_lo_164 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_106) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167) node cs_decoder_decoded_andMatrixOutputs_hi_hi_167 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_120) node cs_decoder_decoded_andMatrixOutputs_hi_167 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_167, cs_decoder_decoded_andMatrixOutputs_hi_lo_164) node _cs_decoder_decoded_andMatrixOutputs_T_167 = cat(cs_decoder_decoded_andMatrixOutputs_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_167) node cs_decoder_decoded_andMatrixOutputs_34_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_167) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = bits(cs_decoder_decoded_plaInput, 0, 0) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = bits(cs_decoder_decoded_plaInput, 1, 1) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = bits(cs_decoder_decoded_invInputs, 2, 2) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = bits(cs_decoder_decoded_invInputs, 3, 3) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = bits(cs_decoder_decoded_plaInput, 4, 4) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = bits(cs_decoder_decoded_invInputs, 5, 5) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = bits(cs_decoder_decoded_plaInput, 6, 6) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = bits(cs_decoder_decoded_invInputs, 12, 12) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = bits(cs_decoder_decoded_invInputs, 13, 13) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = bits(cs_decoder_decoded_invInputs, 14, 14) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = bits(cs_decoder_decoded_invInputs, 20, 20) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = bits(cs_decoder_decoded_invInputs, 21, 21) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = bits(cs_decoder_decoded_invInputs, 22, 22) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = bits(cs_decoder_decoded_invInputs, 23, 23) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = bits(cs_decoder_decoded_invInputs, 24, 24) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = bits(cs_decoder_decoded_invInputs, 26, 26) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = bits(cs_decoder_decoded_invInputs, 27, 27) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = bits(cs_decoder_decoded_plaInput, 28, 28) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_30 = bits(cs_decoder_decoded_plaInput, 29, 29) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_26 = bits(cs_decoder_decoded_plaInput, 30, 30) node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_20 = bits(cs_decoder_decoded_plaInput, 31, 31) node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_20) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33) node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_30) node cs_decoder_decoded_andMatrixOutputs_lo_lo_158 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_70) node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121) node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117) node cs_decoder_decoded_andMatrixOutputs_lo_hi_167 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_117) node cs_decoder_decoded_andMatrixOutputs_lo_168 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_lo_158) node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158) node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145) node cs_decoder_decoded_andMatrixOutputs_hi_lo_165 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_107) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168) node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168) node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168) node cs_decoder_decoded_andMatrixOutputs_hi_hi_168 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_121) node cs_decoder_decoded_andMatrixOutputs_hi_168 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_168, cs_decoder_decoded_andMatrixOutputs_hi_lo_165) node _cs_decoder_decoded_andMatrixOutputs_T_168 = cat(cs_decoder_decoded_andMatrixOutputs_hi_168, cs_decoder_decoded_andMatrixOutputs_lo_168) node cs_decoder_decoded_andMatrixOutputs_59_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_168) node cs_decoder_decoded_orMatrixOutputs_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_130_2, cs_decoder_decoded_andMatrixOutputs_94_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_142_2) node cs_decoder_decoded_orMatrixOutputs_lo = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi, cs_decoder_decoded_orMatrixOutputs_lo_lo) node cs_decoder_decoded_orMatrixOutputs_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_152_2, cs_decoder_decoded_andMatrixOutputs_98_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_21_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_139_2) node cs_decoder_decoded_orMatrixOutputs_hi = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi, cs_decoder_decoded_orMatrixOutputs_hi_lo) node _cs_decoder_decoded_orMatrixOutputs_T = cat(cs_decoder_decoded_orMatrixOutputs_hi, cs_decoder_decoded_orMatrixOutputs_lo) node _cs_decoder_decoded_orMatrixOutputs_T_1 = orr(_cs_decoder_decoded_orMatrixOutputs_T) node _cs_decoder_decoded_orMatrixOutputs_T_2 = orr(cs_decoder_decoded_andMatrixOutputs_117_2) node _cs_decoder_decoded_orMatrixOutputs_T_3 = orr(cs_decoder_decoded_andMatrixOutputs_82_2) node cs_decoder_decoded_orMatrixOutputs_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_145_2) node _cs_decoder_decoded_orMatrixOutputs_T_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_1, cs_decoder_decoded_andMatrixOutputs_161_2) node _cs_decoder_decoded_orMatrixOutputs_T_5 = orr(_cs_decoder_decoded_orMatrixOutputs_T_4) node cs_decoder_decoded_orMatrixOutputs_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_23_2, cs_decoder_decoded_andMatrixOutputs_15_2) node cs_decoder_decoded_orMatrixOutputs_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_40_2) node _cs_decoder_decoded_orMatrixOutputs_T_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_1) node _cs_decoder_decoded_orMatrixOutputs_T_7 = orr(_cs_decoder_decoded_orMatrixOutputs_T_6) node cs_decoder_decoded_orMatrixOutputs_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_27_2) node cs_decoder_decoded_orMatrixOutputs_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_130_2) node _cs_decoder_decoded_orMatrixOutputs_T_8 = cat(cs_decoder_decoded_orMatrixOutputs_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_2) node _cs_decoder_decoded_orMatrixOutputs_T_9 = orr(_cs_decoder_decoded_orMatrixOutputs_T_8) node _cs_decoder_decoded_orMatrixOutputs_T_10 = cat(cs_decoder_decoded_andMatrixOutputs_132_2, cs_decoder_decoded_andMatrixOutputs_59_2) node _cs_decoder_decoded_orMatrixOutputs_T_11 = orr(_cs_decoder_decoded_orMatrixOutputs_T_10) node cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_59_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_109_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_101_2) node cs_decoder_decoded_orMatrixOutputs_lo_3 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_1) node cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_11_2, cs_decoder_decoded_andMatrixOutputs_74_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_69_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_68_2) node cs_decoder_decoded_orMatrixOutputs_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_1) node _cs_decoder_decoded_orMatrixOutputs_T_12 = cat(cs_decoder_decoded_orMatrixOutputs_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_3) node _cs_decoder_decoded_orMatrixOutputs_T_13 = orr(_cs_decoder_decoded_orMatrixOutputs_T_12) node cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_67_2, cs_decoder_decoded_andMatrixOutputs_34_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_109_2, cs_decoder_decoded_andMatrixOutputs_101_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_148_2) node cs_decoder_decoded_orMatrixOutputs_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_11_2, cs_decoder_decoded_andMatrixOutputs_74_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_23_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_69_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_68_2) node cs_decoder_decoded_orMatrixOutputs_hi_5 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_2) node _cs_decoder_decoded_orMatrixOutputs_T_14 = cat(cs_decoder_decoded_orMatrixOutputs_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_4) node _cs_decoder_decoded_orMatrixOutputs_T_15 = orr(_cs_decoder_decoded_orMatrixOutputs_T_14) node _cs_decoder_decoded_orMatrixOutputs_T_16 = orr(cs_decoder_decoded_andMatrixOutputs_161_2) node _cs_decoder_decoded_orMatrixOutputs_T_17 = orr(cs_decoder_decoded_andMatrixOutputs_157_2) node cs_decoder_decoded_orMatrixOutputs_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_115_2, cs_decoder_decoded_andMatrixOutputs_92_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_21_2) node cs_decoder_decoded_orMatrixOutputs_hi_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_7_2) node _cs_decoder_decoded_orMatrixOutputs_T_18 = cat(cs_decoder_decoded_orMatrixOutputs_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_5) node _cs_decoder_decoded_orMatrixOutputs_T_19 = orr(_cs_decoder_decoded_orMatrixOutputs_T_18) node cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_27_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_152_2, cs_decoder_decoded_andMatrixOutputs_98_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_117_2) node cs_decoder_decoded_orMatrixOutputs_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_3) node cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_115_2, cs_decoder_decoded_andMatrixOutputs_92_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_21_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_7_2) node cs_decoder_decoded_orMatrixOutputs_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_3) node _cs_decoder_decoded_orMatrixOutputs_T_20 = cat(cs_decoder_decoded_orMatrixOutputs_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_6) node _cs_decoder_decoded_orMatrixOutputs_T_21 = orr(_cs_decoder_decoded_orMatrixOutputs_T_20) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_122_2, cs_decoder_decoded_andMatrixOutputs_41_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_126_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_143_2, cs_decoder_decoded_andMatrixOutputs_119_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_25_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo) node cs_decoder_decoded_orMatrixOutputs_lo_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_4) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_124_2, cs_decoder_decoded_andMatrixOutputs_89_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_75_2, cs_decoder_decoded_andMatrixOutputs_13_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_155_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_105_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo) node cs_decoder_decoded_orMatrixOutputs_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_4) node _cs_decoder_decoded_orMatrixOutputs_T_22 = cat(cs_decoder_decoded_orMatrixOutputs_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_7) node _cs_decoder_decoded_orMatrixOutputs_T_23 = orr(_cs_decoder_decoded_orMatrixOutputs_T_22) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_49_2, cs_decoder_decoded_andMatrixOutputs_122_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_119_2, cs_decoder_decoded_andMatrixOutputs_151_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_22_2, cs_decoder_decoded_andMatrixOutputs_44_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_38_2, cs_decoder_decoded_andMatrixOutputs_4_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_5_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1) node cs_decoder_decoded_orMatrixOutputs_lo_8 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_5) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_57_2, cs_decoder_decoded_andMatrixOutputs_137_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_149_2, cs_decoder_decoded_andMatrixOutputs_144_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_30_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_136_2, cs_decoder_decoded_andMatrixOutputs_96_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_33_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_1_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1) node cs_decoder_decoded_orMatrixOutputs_hi_9 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_5) node _cs_decoder_decoded_orMatrixOutputs_T_24 = cat(cs_decoder_decoded_orMatrixOutputs_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_8) node _cs_decoder_decoded_orMatrixOutputs_T_25 = orr(_cs_decoder_decoded_orMatrixOutputs_T_24) node cs_decoder_decoded_orMatrixOutputs_lo_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_156_2, cs_decoder_decoded_andMatrixOutputs_116_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_6_2, cs_decoder_decoded_andMatrixOutputs_35_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_9_2) node cs_decoder_decoded_orMatrixOutputs_lo_9 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_6) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_127_2, cs_decoder_decoded_andMatrixOutputs_135_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_114_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_113_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_39_2) node cs_decoder_decoded_orMatrixOutputs_hi_10 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_6) node _cs_decoder_decoded_orMatrixOutputs_T_26 = cat(cs_decoder_decoded_orMatrixOutputs_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_9) node _cs_decoder_decoded_orMatrixOutputs_T_27 = orr(_cs_decoder_decoded_orMatrixOutputs_T_26) node cs_decoder_decoded_orMatrixOutputs_lo_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_46_2, cs_decoder_decoded_andMatrixOutputs_159_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_125_2, cs_decoder_decoded_andMatrixOutputs_154_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_20_2) node cs_decoder_decoded_orMatrixOutputs_lo_10 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_7) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_135_2, cs_decoder_decoded_andMatrixOutputs_37_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_22_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_111_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_42_2) node cs_decoder_decoded_orMatrixOutputs_hi_11 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_7) node _cs_decoder_decoded_orMatrixOutputs_T_28 = cat(cs_decoder_decoded_orMatrixOutputs_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_10) node _cs_decoder_decoded_orMatrixOutputs_T_29 = orr(_cs_decoder_decoded_orMatrixOutputs_T_28) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_150_2, cs_decoder_decoded_andMatrixOutputs_31_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_8 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_106_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_91_2, cs_decoder_decoded_andMatrixOutputs_70_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_87_2, cs_decoder_decoded_andMatrixOutputs_158_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2) node cs_decoder_decoded_orMatrixOutputs_lo_11 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_8) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_12_2, cs_decoder_decoded_andMatrixOutputs_36_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_8 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_55_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_24_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_51_2, cs_decoder_decoded_andMatrixOutputs_37_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_9 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2) node cs_decoder_decoded_orMatrixOutputs_hi_12 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_8) node _cs_decoder_decoded_orMatrixOutputs_T_30 = cat(cs_decoder_decoded_orMatrixOutputs_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_11) node _cs_decoder_decoded_orMatrixOutputs_T_31 = orr(_cs_decoder_decoded_orMatrixOutputs_T_30) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_78_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_19_2, cs_decoder_decoded_andMatrixOutputs_53_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_55_2, cs_decoder_decoded_andMatrixOutputs_128_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_44_2, cs_decoder_decoded_andMatrixOutputs_36_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo) node cs_decoder_decoded_orMatrixOutputs_lo_lo_9 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_116_2, cs_decoder_decoded_andMatrixOutputs_163_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_156_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_146_2, cs_decoder_decoded_andMatrixOutputs_66_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_35_2, cs_decoder_decoded_andMatrixOutputs_51_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo) node cs_decoder_decoded_orMatrixOutputs_lo_hi_9 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3) node cs_decoder_decoded_orMatrixOutputs_lo_12 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_9) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_165_2, cs_decoder_decoded_andMatrixOutputs_135_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_108_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_167_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_105_2, cs_decoder_decoded_andMatrixOutputs_76_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo) node cs_decoder_decoded_orMatrixOutputs_hi_lo_9 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_112_2, cs_decoder_decoded_andMatrixOutputs_138_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_8_2, cs_decoder_decoded_andMatrixOutputs_43_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_61_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_62_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo) node cs_decoder_decoded_orMatrixOutputs_hi_hi_10 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3) node cs_decoder_decoded_orMatrixOutputs_hi_13 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_9) node _cs_decoder_decoded_orMatrixOutputs_T_32 = cat(cs_decoder_decoded_orMatrixOutputs_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_12) node _cs_decoder_decoded_orMatrixOutputs_T_33 = orr(_cs_decoder_decoded_orMatrixOutputs_T_32) node _cs_decoder_decoded_orMatrixOutputs_T_34 = orr(cs_decoder_decoded_andMatrixOutputs_160_2) node _cs_decoder_decoded_orMatrixOutputs_T_35 = cat(cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_16_2) node _cs_decoder_decoded_orMatrixOutputs_T_36 = orr(_cs_decoder_decoded_orMatrixOutputs_T_35) node cs_decoder_decoded_orMatrixOutputs_lo_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_134_2) node cs_decoder_decoded_orMatrixOutputs_lo_13 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_64_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_160_2) node cs_decoder_decoded_orMatrixOutputs_hi_14 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_131_2) node _cs_decoder_decoded_orMatrixOutputs_T_37 = cat(cs_decoder_decoded_orMatrixOutputs_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_13) node _cs_decoder_decoded_orMatrixOutputs_T_38 = orr(_cs_decoder_decoded_orMatrixOutputs_T_37) node cs_decoder_decoded_orMatrixOutputs_lo_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_64_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_118_2, cs_decoder_decoded_andMatrixOutputs_50_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_11 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_134_2) node cs_decoder_decoded_orMatrixOutputs_lo_14 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_10) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_17_2, cs_decoder_decoded_andMatrixOutputs_131_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_10 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_99_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_47_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_12 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_160_2) node cs_decoder_decoded_orMatrixOutputs_hi_15 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_10) node _cs_decoder_decoded_orMatrixOutputs_T_39 = cat(cs_decoder_decoded_orMatrixOutputs_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_14) node _cs_decoder_decoded_orMatrixOutputs_T_40 = orr(_cs_decoder_decoded_orMatrixOutputs_T_39) node cs_decoder_decoded_orMatrixOutputs_lo_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_95_2, cs_decoder_decoded_andMatrixOutputs_103_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_58_2, cs_decoder_decoded_andMatrixOutputs_129_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_12 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_97_2) node cs_decoder_decoded_orMatrixOutputs_lo_15 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_lo_11) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_17_2, cs_decoder_decoded_andMatrixOutputs_131_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_11 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_99_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_71_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_13 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_160_2) node cs_decoder_decoded_orMatrixOutputs_hi_16 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_11) node _cs_decoder_decoded_orMatrixOutputs_T_41 = cat(cs_decoder_decoded_orMatrixOutputs_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_15) node _cs_decoder_decoded_orMatrixOutputs_T_42 = orr(_cs_decoder_decoded_orMatrixOutputs_T_41) node cs_decoder_decoded_orMatrixOutputs_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_63_2) node cs_decoder_decoded_orMatrixOutputs_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_153_2) node _cs_decoder_decoded_orMatrixOutputs_T_43 = cat(cs_decoder_decoded_orMatrixOutputs_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_16) node _cs_decoder_decoded_orMatrixOutputs_T_44 = orr(_cs_decoder_decoded_orMatrixOutputs_T_43) node cs_decoder_decoded_orMatrixOutputs_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_118_2, cs_decoder_decoded_andMatrixOutputs_54_2) node _cs_decoder_decoded_orMatrixOutputs_T_45 = cat(cs_decoder_decoded_orMatrixOutputs_hi_18, cs_decoder_decoded_andMatrixOutputs_48_2) node _cs_decoder_decoded_orMatrixOutputs_T_46 = orr(_cs_decoder_decoded_orMatrixOutputs_T_45) node cs_decoder_decoded_orMatrixOutputs_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_147_2) node cs_decoder_decoded_orMatrixOutputs_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_99_2, cs_decoder_decoded_andMatrixOutputs_118_2) node _cs_decoder_decoded_orMatrixOutputs_T_47 = cat(cs_decoder_decoded_orMatrixOutputs_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_17) node _cs_decoder_decoded_orMatrixOutputs_T_48 = orr(_cs_decoder_decoded_orMatrixOutputs_T_47) node _cs_decoder_decoded_orMatrixOutputs_T_49 = orr(cs_decoder_decoded_andMatrixOutputs_17_2) node _cs_decoder_decoded_orMatrixOutputs_T_50 = orr(cs_decoder_decoded_andMatrixOutputs_65_2) node _cs_decoder_decoded_orMatrixOutputs_T_51 = cat(cs_decoder_decoded_andMatrixOutputs_17_2, cs_decoder_decoded_andMatrixOutputs_99_2) node _cs_decoder_decoded_orMatrixOutputs_T_52 = orr(_cs_decoder_decoded_orMatrixOutputs_T_51) node cs_decoder_decoded_orMatrixOutputs_lo_18 = cat(cs_decoder_decoded_andMatrixOutputs_17_2, cs_decoder_decoded_andMatrixOutputs_99_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_110_2) node cs_decoder_decoded_orMatrixOutputs_hi_20 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_153_2) node _cs_decoder_decoded_orMatrixOutputs_T_53 = cat(cs_decoder_decoded_orMatrixOutputs_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_18) node _cs_decoder_decoded_orMatrixOutputs_T_54 = orr(_cs_decoder_decoded_orMatrixOutputs_T_53) node cs_decoder_decoded_orMatrixOutputs_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_118_2) node cs_decoder_decoded_orMatrixOutputs_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_10_2) node _cs_decoder_decoded_orMatrixOutputs_T_55 = cat(cs_decoder_decoded_orMatrixOutputs_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_19) node _cs_decoder_decoded_orMatrixOutputs_T_56 = orr(_cs_decoder_decoded_orMatrixOutputs_T_55) node cs_decoder_decoded_orMatrixOutputs_lo_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_164_2, cs_decoder_decoded_andMatrixOutputs_133_2) node cs_decoder_decoded_orMatrixOutputs_lo_20 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_28_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_110_2) node cs_decoder_decoded_orMatrixOutputs_hi_22 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_153_2) node _cs_decoder_decoded_orMatrixOutputs_T_57 = cat(cs_decoder_decoded_orMatrixOutputs_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_20) node _cs_decoder_decoded_orMatrixOutputs_T_58 = orr(_cs_decoder_decoded_orMatrixOutputs_T_57) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_103_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_132_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_158_2, cs_decoder_decoded_andMatrixOutputs_91_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_36_2, cs_decoder_decoded_andMatrixOutputs_87_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1) node cs_decoder_decoded_orMatrixOutputs_lo_lo_12 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_44_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_104_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_97_2, cs_decoder_decoded_andMatrixOutputs_156_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_51_2, cs_decoder_decoded_andMatrixOutputs_129_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1) node cs_decoder_decoded_orMatrixOutputs_lo_hi_14 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4) node cs_decoder_decoded_orMatrixOutputs_lo_21 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_lo_12) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_131_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_25_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_160_2, cs_decoder_decoded_andMatrixOutputs_120_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_52_2, cs_decoder_decoded_andMatrixOutputs_0_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1) node cs_decoder_decoded_orMatrixOutputs_hi_lo_12 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_138_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_71_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_77_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_81_2, cs_decoder_decoded_andMatrixOutputs_10_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1) node cs_decoder_decoded_orMatrixOutputs_hi_hi_16 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4) node cs_decoder_decoded_orMatrixOutputs_hi_23 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_lo_12) node _cs_decoder_decoded_orMatrixOutputs_T_59 = cat(cs_decoder_decoded_orMatrixOutputs_hi_23, cs_decoder_decoded_orMatrixOutputs_lo_21) node _cs_decoder_decoded_orMatrixOutputs_T_60 = orr(_cs_decoder_decoded_orMatrixOutputs_T_59) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_103_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_132_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_158_2, cs_decoder_decoded_andMatrixOutputs_91_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_36_2, cs_decoder_decoded_andMatrixOutputs_87_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_13 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_44_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_104_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_97_2, cs_decoder_decoded_andMatrixOutputs_156_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_51_2, cs_decoder_decoded_andMatrixOutputs_129_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_15 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5) node cs_decoder_decoded_orMatrixOutputs_lo_22 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_lo_13) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_135_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_25_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_18_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_0_2, cs_decoder_decoded_andMatrixOutputs_76_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_13 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_71_2, cs_decoder_decoded_andMatrixOutputs_52_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_112_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_77_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_81_2, cs_decoder_decoded_andMatrixOutputs_10_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_17 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5) node cs_decoder_decoded_orMatrixOutputs_hi_24 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_hi_lo_13) node _cs_decoder_decoded_orMatrixOutputs_T_61 = cat(cs_decoder_decoded_orMatrixOutputs_hi_24, cs_decoder_decoded_orMatrixOutputs_lo_22) node _cs_decoder_decoded_orMatrixOutputs_T_62 = orr(_cs_decoder_decoded_orMatrixOutputs_T_61) node _cs_decoder_decoded_orMatrixOutputs_T_63 = orr(cs_decoder_decoded_andMatrixOutputs_157_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_7_2, cs_decoder_decoded_andMatrixOutputs_115_2) node cs_decoder_decoded_orMatrixOutputs_lo_23 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_92_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_21_2) node cs_decoder_decoded_orMatrixOutputs_hi_25 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_107_2) node _cs_decoder_decoded_orMatrixOutputs_T_64 = cat(cs_decoder_decoded_orMatrixOutputs_hi_25, cs_decoder_decoded_orMatrixOutputs_lo_23) node _cs_decoder_decoded_orMatrixOutputs_T_65 = orr(_cs_decoder_decoded_orMatrixOutputs_T_64) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_32_2, cs_decoder_decoded_andMatrixOutputs_94_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_64_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_83_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_128_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3) node cs_decoder_decoded_orMatrixOutputs_lo_lo_14 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_36_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_104_2, cs_decoder_decoded_andMatrixOutputs_152_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_44_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_134_2, cs_decoder_decoded_andMatrixOutputs_156_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3) node cs_decoder_decoded_orMatrixOutputs_lo_hi_17 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6) node cs_decoder_decoded_orMatrixOutputs_lo_24 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_lo_14) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_118_2, cs_decoder_decoded_andMatrixOutputs_50_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_51_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_18_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_0_2, cs_decoder_decoded_andMatrixOutputs_160_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3) node cs_decoder_decoded_orMatrixOutputs_hi_lo_14 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_52_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_138_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_77_2, cs_decoder_decoded_andMatrixOutputs_29_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_81_2, cs_decoder_decoded_andMatrixOutputs_10_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_100_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3) node cs_decoder_decoded_orMatrixOutputs_hi_hi_19 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6) node cs_decoder_decoded_orMatrixOutputs_hi_26 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_lo_14) node _cs_decoder_decoded_orMatrixOutputs_T_66 = cat(cs_decoder_decoded_orMatrixOutputs_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_24) node _cs_decoder_decoded_orMatrixOutputs_T_67 = orr(_cs_decoder_decoded_orMatrixOutputs_T_66) node cs_decoder_decoded_orMatrixOutputs_lo_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_27_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_152_2, cs_decoder_decoded_andMatrixOutputs_98_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_18 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_117_2) node cs_decoder_decoded_orMatrixOutputs_lo_25 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_18, cs_decoder_decoded_orMatrixOutputs_lo_lo_15) node cs_decoder_decoded_orMatrixOutputs_hi_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_115_2, cs_decoder_decoded_andMatrixOutputs_92_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_21_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_20 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_7_2) node cs_decoder_decoded_orMatrixOutputs_hi_27 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_hi_lo_15) node _cs_decoder_decoded_orMatrixOutputs_T_68 = cat(cs_decoder_decoded_orMatrixOutputs_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_25) node _cs_decoder_decoded_orMatrixOutputs_T_69 = orr(_cs_decoder_decoded_orMatrixOutputs_T_68) node cs_decoder_decoded_orMatrixOutputs_lo_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_134_2, cs_decoder_decoded_andMatrixOutputs_64_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_3_2, cs_decoder_decoded_andMatrixOutputs_50_2) node cs_decoder_decoded_orMatrixOutputs_lo_26 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_lo_16) node cs_decoder_decoded_orMatrixOutputs_hi_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_72_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_29_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_21 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_138_2) node cs_decoder_decoded_orMatrixOutputs_hi_28 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_hi_lo_16) node _cs_decoder_decoded_orMatrixOutputs_T_70 = cat(cs_decoder_decoded_orMatrixOutputs_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_26) node _cs_decoder_decoded_orMatrixOutputs_T_71 = orr(_cs_decoder_decoded_orMatrixOutputs_T_70) node cs_decoder_decoded_orMatrixOutputs_lo_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_132_2, cs_decoder_decoded_andMatrixOutputs_59_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_23_2, cs_decoder_decoded_andMatrixOutputs_15_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_20 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_117_2) node cs_decoder_decoded_orMatrixOutputs_lo_27 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_lo_17) node cs_decoder_decoded_orMatrixOutputs_hi_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_40_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_123_2, cs_decoder_decoded_andMatrixOutputs_21_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_22 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_73_2) node cs_decoder_decoded_orMatrixOutputs_hi_29 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_lo_17) node _cs_decoder_decoded_orMatrixOutputs_T_72 = cat(cs_decoder_decoded_orMatrixOutputs_hi_29, cs_decoder_decoded_orMatrixOutputs_lo_27) node _cs_decoder_decoded_orMatrixOutputs_T_73 = orr(_cs_decoder_decoded_orMatrixOutputs_T_72) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_90_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_27_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_91_2, cs_decoder_decoded_andMatrixOutputs_70_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_106_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_87_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_158_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_36_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_55_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4) node cs_decoder_decoded_orMatrixOutputs_lo_lo_18 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_44_2, cs_decoder_decoded_andMatrixOutputs_151_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_152_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_156_2, cs_decoder_decoded_andMatrixOutputs_116_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_163_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_133_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_28_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_58_2, cs_decoder_decoded_andMatrixOutputs_7_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_115_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4) node cs_decoder_decoded_orMatrixOutputs_lo_hi_21 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7) node cs_decoder_decoded_orMatrixOutputs_lo_28 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_lo_18) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_25_2, cs_decoder_decoded_andMatrixOutputs_99_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_51_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_35_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_9_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_17_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_131_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_160_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_45_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4) node cs_decoder_decoded_orMatrixOutputs_hi_lo_18 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_138_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_105_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_56_2, cs_decoder_decoded_andMatrixOutputs_123_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_21_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_166_2, cs_decoder_decoded_andMatrixOutputs_8_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_80_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_77_2, cs_decoder_decoded_andMatrixOutputs_29_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_81_2, cs_decoder_decoded_andMatrixOutputs_10_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4) node cs_decoder_decoded_orMatrixOutputs_hi_hi_23 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7) node cs_decoder_decoded_orMatrixOutputs_hi_30 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_23, cs_decoder_decoded_orMatrixOutputs_hi_lo_18) node _cs_decoder_decoded_orMatrixOutputs_T_74 = cat(cs_decoder_decoded_orMatrixOutputs_hi_30, cs_decoder_decoded_orMatrixOutputs_lo_28) node _cs_decoder_decoded_orMatrixOutputs_T_75 = orr(_cs_decoder_decoded_orMatrixOutputs_T_74) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_83_2, cs_decoder_decoded_andMatrixOutputs_70_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_106_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_128_2, cs_decoder_decoded_andMatrixOutputs_2_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_36_2, cs_decoder_decoded_andMatrixOutputs_55_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5) node cs_decoder_decoded_orMatrixOutputs_lo_lo_19 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_44_2, cs_decoder_decoded_andMatrixOutputs_151_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_116_2, cs_decoder_decoded_andMatrixOutputs_163_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_28_2, cs_decoder_decoded_andMatrixOutputs_156_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_37_2, cs_decoder_decoded_andMatrixOutputs_133_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5) node cs_decoder_decoded_orMatrixOutputs_lo_hi_22 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8) node cs_decoder_decoded_orMatrixOutputs_lo_29 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_lo_19) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_25_2, cs_decoder_decoded_andMatrixOutputs_51_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_135_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_18_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_138_2, cs_decoder_decoded_andMatrixOutputs_52_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5) node cs_decoder_decoded_orMatrixOutputs_hi_lo_19 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_112_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_14_2, cs_decoder_decoded_andMatrixOutputs_56_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_166_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_62_2, cs_decoder_decoded_andMatrixOutputs_77_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5) node cs_decoder_decoded_orMatrixOutputs_hi_hi_24 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8) node cs_decoder_decoded_orMatrixOutputs_hi_31 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_24, cs_decoder_decoded_orMatrixOutputs_hi_lo_19) node _cs_decoder_decoded_orMatrixOutputs_T_76 = cat(cs_decoder_decoded_orMatrixOutputs_hi_31, cs_decoder_decoded_orMatrixOutputs_lo_29) node _cs_decoder_decoded_orMatrixOutputs_T_77 = orr(_cs_decoder_decoded_orMatrixOutputs_T_76) node cs_decoder_decoded_orMatrixOutputs_lo_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_17_2, cs_decoder_decoded_andMatrixOutputs_99_2) node cs_decoder_decoded_orMatrixOutputs_lo_30 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_118_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_20 = cat(cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_120_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_10_2) node cs_decoder_decoded_orMatrixOutputs_hi_32 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_25, cs_decoder_decoded_orMatrixOutputs_hi_lo_20) node _cs_decoder_decoded_orMatrixOutputs_T_78 = cat(cs_decoder_decoded_orMatrixOutputs_hi_32, cs_decoder_decoded_orMatrixOutputs_lo_30) node _cs_decoder_decoded_orMatrixOutputs_T_79 = orr(_cs_decoder_decoded_orMatrixOutputs_T_78) node cs_decoder_decoded_orMatrixOutputs_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_17_2) node _cs_decoder_decoded_orMatrixOutputs_T_80 = cat(cs_decoder_decoded_orMatrixOutputs_hi_33, cs_decoder_decoded_andMatrixOutputs_99_2) node _cs_decoder_decoded_orMatrixOutputs_T_81 = orr(_cs_decoder_decoded_orMatrixOutputs_T_80) node _cs_decoder_decoded_orMatrixOutputs_T_82 = cat(cs_decoder_decoded_andMatrixOutputs_141_2, cs_decoder_decoded_andMatrixOutputs_93_2) node _cs_decoder_decoded_orMatrixOutputs_T_83 = orr(_cs_decoder_decoded_orMatrixOutputs_T_82) node _cs_decoder_decoded_orMatrixOutputs_T_84 = orr(cs_decoder_decoded_andMatrixOutputs_9_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_134_2, cs_decoder_decoded_andMatrixOutputs_65_2) node cs_decoder_decoded_orMatrixOutputs_lo_31 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_64_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_50_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_160_2) node cs_decoder_decoded_orMatrixOutputs_hi_34 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_26, cs_decoder_decoded_orMatrixOutputs_hi_lo_21) node _cs_decoder_decoded_orMatrixOutputs_T_85 = cat(cs_decoder_decoded_orMatrixOutputs_hi_34, cs_decoder_decoded_orMatrixOutputs_lo_31) node _cs_decoder_decoded_orMatrixOutputs_T_86 = orr(_cs_decoder_decoded_orMatrixOutputs_T_85) node cs_decoder_decoded_orMatrixOutputs_lo_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_40_2, cs_decoder_decoded_andMatrixOutputs_23_2) node cs_decoder_decoded_orMatrixOutputs_lo_32 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_15_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_22 = cat(cs_decoder_decoded_andMatrixOutputs_161_2, cs_decoder_decoded_andMatrixOutputs_92_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_145_2) node cs_decoder_decoded_orMatrixOutputs_hi_35 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_27, cs_decoder_decoded_orMatrixOutputs_hi_lo_22) node _cs_decoder_decoded_orMatrixOutputs_T_87 = cat(cs_decoder_decoded_orMatrixOutputs_hi_35, cs_decoder_decoded_orMatrixOutputs_lo_32) node _cs_decoder_decoded_orMatrixOutputs_T_88 = orr(_cs_decoder_decoded_orMatrixOutputs_T_87) node _cs_decoder_decoded_orMatrixOutputs_T_89 = cat(cs_decoder_decoded_andMatrixOutputs_82_2, cs_decoder_decoded_andMatrixOutputs_117_2) node _cs_decoder_decoded_orMatrixOutputs_T_90 = orr(_cs_decoder_decoded_orMatrixOutputs_T_89) node _cs_decoder_decoded_orMatrixOutputs_T_91 = cat(cs_decoder_decoded_andMatrixOutputs_132_2, cs_decoder_decoded_andMatrixOutputs_59_2) node _cs_decoder_decoded_orMatrixOutputs_T_92 = orr(_cs_decoder_decoded_orMatrixOutputs_T_91) node cs_decoder_decoded_orMatrixOutputs_lo_33 = cat(cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_27_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_107_2, cs_decoder_decoded_andMatrixOutputs_142_2) node cs_decoder_decoded_orMatrixOutputs_hi_36 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_130_2) node _cs_decoder_decoded_orMatrixOutputs_T_93 = cat(cs_decoder_decoded_orMatrixOutputs_hi_36, cs_decoder_decoded_orMatrixOutputs_lo_33) node _cs_decoder_decoded_orMatrixOutputs_T_94 = orr(_cs_decoder_decoded_orMatrixOutputs_T_93) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_90_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_20 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_27_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_152_2, cs_decoder_decoded_andMatrixOutputs_98_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_26 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_117_2) node cs_decoder_decoded_orMatrixOutputs_lo_34 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_lo_20) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_7_2, cs_decoder_decoded_andMatrixOutputs_115_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_23 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_92_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_123_2, cs_decoder_decoded_andMatrixOutputs_21_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_29 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_162_2) node cs_decoder_decoded_orMatrixOutputs_hi_37 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_29, cs_decoder_decoded_orMatrixOutputs_hi_lo_23) node _cs_decoder_decoded_orMatrixOutputs_T_95 = cat(cs_decoder_decoded_orMatrixOutputs_hi_37, cs_decoder_decoded_orMatrixOutputs_lo_34) node _cs_decoder_decoded_orMatrixOutputs_T_96 = orr(_cs_decoder_decoded_orMatrixOutputs_T_95) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_90_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_27_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_103_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_91_2, cs_decoder_decoded_andMatrixOutputs_70_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_87_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_158_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_36_2, cs_decoder_decoded_andMatrixOutputs_55_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_152_2, cs_decoder_decoded_andMatrixOutputs_98_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6) node cs_decoder_decoded_orMatrixOutputs_lo_lo_21 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_44_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_151_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_156_2, cs_decoder_decoded_andMatrixOutputs_116_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_133_2, cs_decoder_decoded_andMatrixOutputs_28_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_7_2, cs_decoder_decoded_andMatrixOutputs_115_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_92_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_97_2, cs_decoder_decoded_andMatrixOutputs_95_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_58_2, cs_decoder_decoded_andMatrixOutputs_129_2) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6) node cs_decoder_decoded_orMatrixOutputs_lo_hi_27 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9) node cs_decoder_decoded_orMatrixOutputs_lo_35 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_lo_21) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_25_2, cs_decoder_decoded_andMatrixOutputs_99_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_51_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_35_2, cs_decoder_decoded_andMatrixOutputs_9_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_135_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_17_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_131_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_76_2, cs_decoder_decoded_andMatrixOutputs_120_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_105_2, cs_decoder_decoded_andMatrixOutputs_86_2) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6) node cs_decoder_decoded_orMatrixOutputs_hi_lo_24 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_112_2, cs_decoder_decoded_andMatrixOutputs_138_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_71_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_123_2, cs_decoder_decoded_andMatrixOutputs_21_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_80_2, cs_decoder_decoded_andMatrixOutputs_56_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_166_2, cs_decoder_decoded_andMatrixOutputs_8_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_77_2, cs_decoder_decoded_andMatrixOutputs_29_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_100_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_81_2, cs_decoder_decoded_andMatrixOutputs_10_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6) node cs_decoder_decoded_orMatrixOutputs_hi_hi_30 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9) node cs_decoder_decoded_orMatrixOutputs_hi_38 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_30, cs_decoder_decoded_orMatrixOutputs_hi_lo_24) node _cs_decoder_decoded_orMatrixOutputs_T_97 = cat(cs_decoder_decoded_orMatrixOutputs_hi_38, cs_decoder_decoded_orMatrixOutputs_lo_35) node _cs_decoder_decoded_orMatrixOutputs_T_98 = orr(_cs_decoder_decoded_orMatrixOutputs_T_97) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_3, _cs_decoder_decoded_orMatrixOutputs_T_2) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_1) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_1 = cat(_cs_decoder_decoded_orMatrixOutputs_T_7, _cs_decoder_decoded_orMatrixOutputs_T_5) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_11, _cs_decoder_decoded_orMatrixOutputs_T_9) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_1) node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_16, _cs_decoder_decoded_orMatrixOutputs_T_15) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_13) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_1 = cat(_cs_decoder_decoded_orMatrixOutputs_T_17, UInt<1>(0h0)) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_21, _cs_decoder_decoded_orMatrixOutputs_T_19) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_1) node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_7) node cs_decoder_decoded_orMatrixOutputs_lo_lo_22 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_23, UInt<1>(0h0)) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2, UInt<1>(0h0)) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_1 = cat(_cs_decoder_decoded_orMatrixOutputs_T_27, _cs_decoder_decoded_orMatrixOutputs_T_25) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_31, _cs_decoder_decoded_orMatrixOutputs_T_29) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_1) node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_36, _cs_decoder_decoded_orMatrixOutputs_T_34) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_33) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_1 = cat(_cs_decoder_decoded_orMatrixOutputs_T_40, _cs_decoder_decoded_orMatrixOutputs_T_38) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_44, _cs_decoder_decoded_orMatrixOutputs_T_42) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_1) node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_7) node cs_decoder_decoded_orMatrixOutputs_lo_hi_28 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10) node cs_decoder_decoded_orMatrixOutputs_lo_36 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_lo_22) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_49, _cs_decoder_decoded_orMatrixOutputs_T_48) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_46) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_1 = cat(_cs_decoder_decoded_orMatrixOutputs_T_52, _cs_decoder_decoded_orMatrixOutputs_T_50) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_56, _cs_decoder_decoded_orMatrixOutputs_T_54) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_1) node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_62, _cs_decoder_decoded_orMatrixOutputs_T_60) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_58) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_1 = cat(_cs_decoder_decoded_orMatrixOutputs_T_65, _cs_decoder_decoded_orMatrixOutputs_T_63) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_69, _cs_decoder_decoded_orMatrixOutputs_T_67) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_1) node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_7) node cs_decoder_decoded_orMatrixOutputs_hi_lo_25 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_75, _cs_decoder_decoded_orMatrixOutputs_T_73) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_71) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_1 = cat(_cs_decoder_decoded_orMatrixOutputs_T_79, _cs_decoder_decoded_orMatrixOutputs_T_77) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_83, _cs_decoder_decoded_orMatrixOutputs_T_81) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_1) node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_1 = cat(_cs_decoder_decoded_orMatrixOutputs_T_86, _cs_decoder_decoded_orMatrixOutputs_T_84) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_90, _cs_decoder_decoded_orMatrixOutputs_T_88) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_1) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_94, _cs_decoder_decoded_orMatrixOutputs_T_92) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = cat(_cs_decoder_decoded_orMatrixOutputs_T_98, _cs_decoder_decoded_orMatrixOutputs_T_96) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_2) node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7) node cs_decoder_decoded_orMatrixOutputs_hi_hi_31 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10) node cs_decoder_decoded_orMatrixOutputs_hi_39 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_31, cs_decoder_decoded_orMatrixOutputs_hi_lo_25) node cs_decoder_decoded_orMatrixOutputs = cat(cs_decoder_decoded_orMatrixOutputs_hi_39, cs_decoder_decoded_orMatrixOutputs_lo_36) node _cs_decoder_decoded_invMatrixOutputs_T = bits(cs_decoder_decoded_orMatrixOutputs, 0, 0) node _cs_decoder_decoded_invMatrixOutputs_T_1 = bits(cs_decoder_decoded_orMatrixOutputs, 1, 1) node _cs_decoder_decoded_invMatrixOutputs_T_2 = bits(cs_decoder_decoded_orMatrixOutputs, 2, 2) node _cs_decoder_decoded_invMatrixOutputs_T_3 = bits(cs_decoder_decoded_orMatrixOutputs, 3, 3) node _cs_decoder_decoded_invMatrixOutputs_T_4 = bits(cs_decoder_decoded_orMatrixOutputs, 4, 4) node _cs_decoder_decoded_invMatrixOutputs_T_5 = bits(cs_decoder_decoded_orMatrixOutputs, 5, 5) node _cs_decoder_decoded_invMatrixOutputs_T_6 = bits(cs_decoder_decoded_orMatrixOutputs, 6, 6) node _cs_decoder_decoded_invMatrixOutputs_T_7 = bits(cs_decoder_decoded_orMatrixOutputs, 7, 7) node _cs_decoder_decoded_invMatrixOutputs_T_8 = bits(cs_decoder_decoded_orMatrixOutputs, 8, 8) node _cs_decoder_decoded_invMatrixOutputs_T_9 = bits(cs_decoder_decoded_orMatrixOutputs, 9, 9) node _cs_decoder_decoded_invMatrixOutputs_T_10 = bits(cs_decoder_decoded_orMatrixOutputs, 10, 10) node _cs_decoder_decoded_invMatrixOutputs_T_11 = bits(cs_decoder_decoded_orMatrixOutputs, 11, 11) node _cs_decoder_decoded_invMatrixOutputs_T_12 = bits(cs_decoder_decoded_orMatrixOutputs, 12, 12) node _cs_decoder_decoded_invMatrixOutputs_T_13 = bits(cs_decoder_decoded_orMatrixOutputs, 13, 13) node _cs_decoder_decoded_invMatrixOutputs_T_14 = bits(cs_decoder_decoded_orMatrixOutputs, 14, 14) node _cs_decoder_decoded_invMatrixOutputs_T_15 = bits(cs_decoder_decoded_orMatrixOutputs, 15, 15) node _cs_decoder_decoded_invMatrixOutputs_T_16 = bits(cs_decoder_decoded_orMatrixOutputs, 16, 16) node _cs_decoder_decoded_invMatrixOutputs_T_17 = bits(cs_decoder_decoded_orMatrixOutputs, 17, 17) node _cs_decoder_decoded_invMatrixOutputs_T_18 = bits(cs_decoder_decoded_orMatrixOutputs, 18, 18) node _cs_decoder_decoded_invMatrixOutputs_T_19 = bits(cs_decoder_decoded_orMatrixOutputs, 19, 19) node _cs_decoder_decoded_invMatrixOutputs_T_20 = bits(cs_decoder_decoded_orMatrixOutputs, 20, 20) node _cs_decoder_decoded_invMatrixOutputs_T_21 = bits(cs_decoder_decoded_orMatrixOutputs, 21, 21) node _cs_decoder_decoded_invMatrixOutputs_T_22 = bits(cs_decoder_decoded_orMatrixOutputs, 22, 22) node _cs_decoder_decoded_invMatrixOutputs_T_23 = bits(cs_decoder_decoded_orMatrixOutputs, 23, 23) node _cs_decoder_decoded_invMatrixOutputs_T_24 = bits(cs_decoder_decoded_orMatrixOutputs, 24, 24) node _cs_decoder_decoded_invMatrixOutputs_T_25 = bits(cs_decoder_decoded_orMatrixOutputs, 25, 25) node _cs_decoder_decoded_invMatrixOutputs_T_26 = bits(cs_decoder_decoded_orMatrixOutputs, 26, 26) node _cs_decoder_decoded_invMatrixOutputs_T_27 = bits(cs_decoder_decoded_orMatrixOutputs, 27, 27) node _cs_decoder_decoded_invMatrixOutputs_T_28 = bits(cs_decoder_decoded_orMatrixOutputs, 28, 28) node _cs_decoder_decoded_invMatrixOutputs_T_29 = bits(cs_decoder_decoded_orMatrixOutputs, 29, 29) node _cs_decoder_decoded_invMatrixOutputs_T_30 = bits(cs_decoder_decoded_orMatrixOutputs, 30, 30) node _cs_decoder_decoded_invMatrixOutputs_T_31 = bits(cs_decoder_decoded_orMatrixOutputs, 31, 31) node _cs_decoder_decoded_invMatrixOutputs_T_32 = bits(cs_decoder_decoded_orMatrixOutputs, 32, 32) node _cs_decoder_decoded_invMatrixOutputs_T_33 = bits(cs_decoder_decoded_orMatrixOutputs, 33, 33) node _cs_decoder_decoded_invMatrixOutputs_T_34 = bits(cs_decoder_decoded_orMatrixOutputs, 34, 34) node _cs_decoder_decoded_invMatrixOutputs_T_35 = bits(cs_decoder_decoded_orMatrixOutputs, 35, 35) node _cs_decoder_decoded_invMatrixOutputs_T_36 = bits(cs_decoder_decoded_orMatrixOutputs, 36, 36) node _cs_decoder_decoded_invMatrixOutputs_T_37 = not(_cs_decoder_decoded_invMatrixOutputs_T_36) node _cs_decoder_decoded_invMatrixOutputs_T_38 = bits(cs_decoder_decoded_orMatrixOutputs, 37, 37) node _cs_decoder_decoded_invMatrixOutputs_T_39 = not(_cs_decoder_decoded_invMatrixOutputs_T_38) node _cs_decoder_decoded_invMatrixOutputs_T_40 = bits(cs_decoder_decoded_orMatrixOutputs, 38, 38) node _cs_decoder_decoded_invMatrixOutputs_T_41 = bits(cs_decoder_decoded_orMatrixOutputs, 39, 39) node _cs_decoder_decoded_invMatrixOutputs_T_42 = bits(cs_decoder_decoded_orMatrixOutputs, 40, 40) node _cs_decoder_decoded_invMatrixOutputs_T_43 = bits(cs_decoder_decoded_orMatrixOutputs, 41, 41) node _cs_decoder_decoded_invMatrixOutputs_T_44 = bits(cs_decoder_decoded_orMatrixOutputs, 42, 42) node _cs_decoder_decoded_invMatrixOutputs_T_45 = bits(cs_decoder_decoded_orMatrixOutputs, 43, 43) node _cs_decoder_decoded_invMatrixOutputs_T_46 = bits(cs_decoder_decoded_orMatrixOutputs, 44, 44) node _cs_decoder_decoded_invMatrixOutputs_T_47 = not(_cs_decoder_decoded_invMatrixOutputs_T_46) node _cs_decoder_decoded_invMatrixOutputs_T_48 = bits(cs_decoder_decoded_orMatrixOutputs, 45, 45) node _cs_decoder_decoded_invMatrixOutputs_T_49 = bits(cs_decoder_decoded_orMatrixOutputs, 46, 46) node _cs_decoder_decoded_invMatrixOutputs_T_50 = bits(cs_decoder_decoded_orMatrixOutputs, 47, 47) node _cs_decoder_decoded_invMatrixOutputs_T_51 = bits(cs_decoder_decoded_orMatrixOutputs, 48, 48) node _cs_decoder_decoded_invMatrixOutputs_T_52 = bits(cs_decoder_decoded_orMatrixOutputs, 49, 49) node _cs_decoder_decoded_invMatrixOutputs_T_53 = bits(cs_decoder_decoded_orMatrixOutputs, 50, 50) node _cs_decoder_decoded_invMatrixOutputs_T_54 = bits(cs_decoder_decoded_orMatrixOutputs, 51, 51) node _cs_decoder_decoded_invMatrixOutputs_T_55 = bits(cs_decoder_decoded_orMatrixOutputs, 52, 52) node _cs_decoder_decoded_invMatrixOutputs_T_56 = bits(cs_decoder_decoded_orMatrixOutputs, 53, 53) node _cs_decoder_decoded_invMatrixOutputs_T_57 = bits(cs_decoder_decoded_orMatrixOutputs, 54, 54) node _cs_decoder_decoded_invMatrixOutputs_T_58 = bits(cs_decoder_decoded_orMatrixOutputs, 55, 55) node _cs_decoder_decoded_invMatrixOutputs_T_59 = bits(cs_decoder_decoded_orMatrixOutputs, 56, 56) node cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_2, _cs_decoder_decoded_invMatrixOutputs_T_1) node cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T) node cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = cat(_cs_decoder_decoded_invMatrixOutputs_T_4, _cs_decoder_decoded_invMatrixOutputs_T_3) node cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_6, _cs_decoder_decoded_invMatrixOutputs_T_5) node cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_lo) node cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo) node cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_9, _cs_decoder_decoded_invMatrixOutputs_T_8) node cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_7) node cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = cat(_cs_decoder_decoded_invMatrixOutputs_T_11, _cs_decoder_decoded_invMatrixOutputs_T_10) node cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_13, _cs_decoder_decoded_invMatrixOutputs_T_12) node cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo) node cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = cat(cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo) node cs_decoder_decoded_invMatrixOutputs_lo_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo) node cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_16, _cs_decoder_decoded_invMatrixOutputs_T_15) node cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_14) node cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = cat(_cs_decoder_decoded_invMatrixOutputs_T_18, _cs_decoder_decoded_invMatrixOutputs_T_17) node cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_20, _cs_decoder_decoded_invMatrixOutputs_T_19) node cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_lo) node cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo) node cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_23, _cs_decoder_decoded_invMatrixOutputs_T_22) node cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_21) node cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = cat(_cs_decoder_decoded_invMatrixOutputs_T_25, _cs_decoder_decoded_invMatrixOutputs_T_24) node cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_27, _cs_decoder_decoded_invMatrixOutputs_T_26) node cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo) node cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo) node cs_decoder_decoded_invMatrixOutputs_lo_hi = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo) node cs_decoder_decoded_invMatrixOutputs_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo) node cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_30, _cs_decoder_decoded_invMatrixOutputs_T_29) node cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = cat(cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_28) node cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = cat(_cs_decoder_decoded_invMatrixOutputs_T_32, _cs_decoder_decoded_invMatrixOutputs_T_31) node cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_34, _cs_decoder_decoded_invMatrixOutputs_T_33) node cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_lo) node cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = cat(cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo) node cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_39, _cs_decoder_decoded_invMatrixOutputs_T_37) node cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = cat(cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_35) node cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = cat(_cs_decoder_decoded_invMatrixOutputs_T_41, _cs_decoder_decoded_invMatrixOutputs_T_40) node cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_43, _cs_decoder_decoded_invMatrixOutputs_T_42) node cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo) node cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo) node cs_decoder_decoded_invMatrixOutputs_hi_lo = cat(cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo) node cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_47, _cs_decoder_decoded_invMatrixOutputs_T_45) node cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_44) node cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = cat(_cs_decoder_decoded_invMatrixOutputs_T_49, _cs_decoder_decoded_invMatrixOutputs_T_48) node cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_51, _cs_decoder_decoded_invMatrixOutputs_T_50) node cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo) node cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo) node cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = cat(_cs_decoder_decoded_invMatrixOutputs_T_53, _cs_decoder_decoded_invMatrixOutputs_T_52) node cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_55, _cs_decoder_decoded_invMatrixOutputs_T_54) node cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_lo) node cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = cat(_cs_decoder_decoded_invMatrixOutputs_T_57, _cs_decoder_decoded_invMatrixOutputs_T_56) node cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_59, _cs_decoder_decoded_invMatrixOutputs_T_58) node cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo) node cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo) node cs_decoder_decoded_invMatrixOutputs_hi_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo) node cs_decoder_decoded_invMatrixOutputs_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo) node cs_decoder_decoded_invMatrixOutputs = cat(cs_decoder_decoded_invMatrixOutputs_hi, cs_decoder_decoded_invMatrixOutputs_lo) connect cs_decoder_decoded, cs_decoder_decoded_invMatrixOutputs connect cs_decoder_decoded_plaInput, uop.inst node cs_decoder_0 = bits(cs_decoder_decoded, 56, 56) node cs_decoder_1 = bits(cs_decoder_decoded, 55, 55) node cs_decoder_2 = bits(cs_decoder_decoded, 54, 45) node cs_decoder_3 = bits(cs_decoder_decoded, 44, 43) node cs_decoder_4 = bits(cs_decoder_decoded, 42, 41) node cs_decoder_5 = bits(cs_decoder_decoded, 40, 39) node cs_decoder_6 = bits(cs_decoder_decoded, 38, 38) node cs_decoder_7 = bits(cs_decoder_decoded, 37, 35) node cs_decoder_8 = bits(cs_decoder_decoded, 34, 34) node cs_decoder_9 = bits(cs_decoder_decoded, 33, 33) node cs_decoder_10 = bits(cs_decoder_decoded, 32, 32) node cs_decoder_11 = bits(cs_decoder_decoded, 31, 27) node cs_decoder_12 = bits(cs_decoder_decoded, 26, 26) node cs_decoder_13 = bits(cs_decoder_decoded, 25, 25) node cs_decoder_14 = bits(cs_decoder_decoded, 24, 22) node cs_decoder_15 = bits(cs_decoder_decoded, 21, 21) node cs_decoder_16 = bits(cs_decoder_decoded, 20, 16) node cs_decoder_17 = bits(cs_decoder_decoded, 15, 15) node cs_decoder_18 = bits(cs_decoder_decoded, 14, 14) node cs_decoder_19 = bits(cs_decoder_decoded, 13, 13) node cs_decoder_20 = bits(cs_decoder_decoded, 12, 12) node cs_decoder_21 = bits(cs_decoder_decoded, 11, 11) node cs_decoder_22 = bits(cs_decoder_decoded, 10, 10) node cs_decoder_23 = bits(cs_decoder_decoded, 9, 9) node cs_decoder_24 = bits(cs_decoder_decoded, 8, 8) node cs_decoder_25 = bits(cs_decoder_decoded, 7, 7) node cs_decoder_26 = bits(cs_decoder_decoded, 6, 6) node cs_decoder_27 = bits(cs_decoder_decoded, 5, 5) node cs_decoder_28 = bits(cs_decoder_decoded, 4, 4) node cs_decoder_29 = bits(cs_decoder_decoded, 3, 3) node cs_decoder_30 = bits(cs_decoder_decoded, 2, 2) node cs_decoder_31 = bits(cs_decoder_decoded, 1, 1) node cs_decoder_32 = bits(cs_decoder_decoded, 0, 0) connect cs.legal, cs_decoder_0 connect cs.fp_val, cs_decoder_1 connect cs.fu_code, cs_decoder_2 connect cs.dst_type, cs_decoder_3 connect cs.rs1_type, cs_decoder_4 connect cs.rs2_type, cs_decoder_5 connect cs.frs3_en, cs_decoder_6 connect cs.imm_sel, cs_decoder_7 connect cs.uses_ldq, cs_decoder_8 connect cs.uses_stq, cs_decoder_9 connect cs.is_amo, cs_decoder_10 connect cs.mem_cmd, cs_decoder_11 connect cs.inst_unique, cs_decoder_12 connect cs.flush_on_commit, cs_decoder_13 connect cs.csr_cmd, cs_decoder_14 connect cs.fcn_dw, cs_decoder_15 connect cs.fcn_op, cs_decoder_16 connect cs.fp.ldst, cs_decoder_17 connect cs.fp.wen, cs_decoder_18 connect cs.fp.ren1, cs_decoder_19 connect cs.fp.ren2, cs_decoder_20 connect cs.fp.ren3, cs_decoder_21 connect cs.fp.swap12, cs_decoder_22 connect cs.fp.swap23, cs_decoder_23 connect cs.fp.typeTagIn, cs_decoder_24 connect cs.fp.typeTagOut, cs_decoder_25 connect cs.fp.fromint, cs_decoder_26 connect cs.fp.toint, cs_decoder_27 connect cs.fp.fastpipe, cs_decoder_28 connect cs.fp.fma, cs_decoder_29 connect cs.fp.div, cs_decoder_30 connect cs.fp.sqrt, cs_decoder_31 connect cs.fp.wflags, cs_decoder_32 connect cs.fp.vec, UInt<1>(0h0) connect io.csr_decode.inst, uop.inst node _csr_en_T = eq(cs.csr_cmd, UInt<3>(0h6)) node _csr_en_T_1 = eq(cs.csr_cmd, UInt<3>(0h7)) node _csr_en_T_2 = eq(cs.csr_cmd, UInt<3>(0h5)) node _csr_en_T_3 = or(_csr_en_T, _csr_en_T_1) node csr_en = or(_csr_en_T_3, _csr_en_T_2) node _csr_ren_T = eq(cs.csr_cmd, UInt<3>(0h6)) node _csr_ren_T_1 = eq(cs.csr_cmd, UInt<3>(0h7)) node _csr_ren_T_2 = or(_csr_ren_T, _csr_ren_T_1) node _csr_ren_T_3 = eq(uop.lrs1, UInt<1>(0h0)) node csr_ren = and(_csr_ren_T_2, _csr_ren_T_3) node system_insn = eq(cs.csr_cmd, UInt<3>(0h4)) node _sfence_T = and(uop.inst, UInt<32>(0hfe007fff)) node sfence = eq(UInt<29>(0h12000073), _sfence_T) node _illegal_rm_T = bits(uop.inst, 14, 12) node _illegal_rm_T_1 = eq(_illegal_rm_T, UInt<3>(0h5)) node _illegal_rm_T_2 = eq(_illegal_rm_T, UInt<3>(0h6)) node _illegal_rm_T_3 = or(_illegal_rm_T_1, _illegal_rm_T_2) node _illegal_rm_T_4 = bits(uop.inst, 14, 12) node _illegal_rm_T_5 = eq(_illegal_rm_T_4, UInt<3>(0h7)) node _illegal_rm_T_6 = geq(io.fcsr_rm, UInt<3>(0h5)) node _illegal_rm_T_7 = and(_illegal_rm_T_5, _illegal_rm_T_6) node illegal_rm = or(_illegal_rm_T_3, _illegal_rm_T_7) node _id_illegal_insn_T = eq(cs.legal, UInt<1>(0h0)) node _id_illegal_insn_T_1 = or(io.csr_decode.fp_illegal, illegal_rm) node _id_illegal_insn_T_2 = and(cs.fp_val, _id_illegal_insn_T_1) node _id_illegal_insn_T_3 = or(_id_illegal_insn_T, _id_illegal_insn_T_2) node _id_illegal_insn_T_4 = and(uop.is_rocc, io.csr_decode.rocc_illegal) node _id_illegal_insn_T_5 = or(_id_illegal_insn_T_3, _id_illegal_insn_T_4) node _id_illegal_insn_T_6 = bits(io.status.isa, 0, 0) node _id_illegal_insn_T_7 = eq(_id_illegal_insn_T_6, UInt<1>(0h0)) node _id_illegal_insn_T_8 = and(cs.is_amo, _id_illegal_insn_T_7) node _id_illegal_insn_T_9 = or(_id_illegal_insn_T_5, _id_illegal_insn_T_8) node _id_illegal_insn_T_10 = eq(csr_ren, UInt<1>(0h0)) node _id_illegal_insn_T_11 = and(_id_illegal_insn_T_10, io.csr_decode.write_illegal) node _id_illegal_insn_T_12 = or(io.csr_decode.read_illegal, _id_illegal_insn_T_11) node _id_illegal_insn_T_13 = and(csr_en, _id_illegal_insn_T_12) node _id_illegal_insn_T_14 = or(_id_illegal_insn_T_9, _id_illegal_insn_T_13) node _id_illegal_insn_T_15 = or(sfence, system_insn) node _id_illegal_insn_T_16 = and(_id_illegal_insn_T_15, io.csr_decode.system_illegal) node id_illegal_insn = or(_id_illegal_insn_T_14, _id_illegal_insn_T_16) node _T = eq(io.enq.uop.is_sfb, UInt<1>(0h0)) node _T_1 = and(io.interrupt, _T) node _T_2 = or(_T_1, uop.bp_debug_if) node _T_3 = or(_T_2, uop.bp_xcpt_if) node _T_4 = or(_T_3, uop.xcpt_pf_if) node _T_5 = or(_T_4, uop.xcpt_ae_if) node xcpt_valid = or(_T_5, id_illegal_insn) node _T_6 = mux(uop.xcpt_ae_if, UInt<1>(0h1), UInt<2>(0h2)) node _T_7 = mux(uop.xcpt_pf_if, UInt<4>(0hc), _T_6) node _T_8 = mux(uop.bp_xcpt_if, UInt<2>(0h3), _T_7) node _T_9 = mux(uop.bp_debug_if, UInt<4>(0he), _T_8) node xcpt_cause = mux(_T_1, io.interrupt_cause, _T_9) connect uop.exception, xcpt_valid connect uop.exc_cause, xcpt_cause node _uop_is_mov_T = and(uop.inst, UInt<32>(0hfe00707f)) node _uop_is_mov_T_1 = eq(UInt<6>(0h33), _uop_is_mov_T) node _uop_is_mov_T_2 = eq(LRS1, UInt<1>(0h0)) node _uop_is_mov_T_3 = and(_uop_is_mov_T_1, _uop_is_mov_T_2) connect uop.is_mov, _uop_is_mov_T_3 node _uop_iq_type_1_T = bits(cs.fu_code, 3, 3) node _uop_iq_type_1_T_1 = bits(cs.fu_code, 4, 4) node _uop_iq_type_1_T_2 = bits(cs.fu_code, 5, 5) node _uop_iq_type_1_T_3 = bits(cs.fu_code, 8, 8) node _uop_iq_type_1_T_4 = or(_uop_iq_type_1_T, _uop_iq_type_1_T_1) node _uop_iq_type_1_T_5 = or(_uop_iq_type_1_T_4, _uop_iq_type_1_T_2) node _uop_iq_type_1_T_6 = or(_uop_iq_type_1_T_5, _uop_iq_type_1_T_3) connect uop.iq_type[1], _uop_iq_type_1_T_6 node _uop_iq_type_2_T = bits(cs.fu_code, 0, 0) connect uop.iq_type[2], _uop_iq_type_2_T node _uop_iq_type_0_T = bits(cs.fu_code, 1, 1) node _uop_iq_type_0_T_1 = bits(cs.fu_code, 2, 2) node _uop_iq_type_0_T_2 = or(_uop_iq_type_0_T, _uop_iq_type_0_T_1) connect uop.iq_type[0], _uop_iq_type_0_T_2 node _uop_iq_type_3_T = bits(cs.fu_code, 6, 6) node _uop_iq_type_3_T_1 = bits(cs.fu_code, 7, 7) node _uop_iq_type_3_T_2 = bits(cs.fu_code, 9, 9) node _uop_iq_type_3_T_3 = or(_uop_iq_type_3_T, _uop_iq_type_3_T_1) node _uop_iq_type_3_T_4 = or(_uop_iq_type_3_T_3, _uop_iq_type_3_T_2) connect uop.iq_type[3], _uop_iq_type_3_T_4 node _T_10 = bits(cs.fu_code, 0, 0) node _T_11 = bits(cs.fu_code, 1, 1) node _T_12 = bits(cs.fu_code, 2, 2) node _T_13 = bits(cs.fu_code, 3, 3) node _T_14 = bits(cs.fu_code, 4, 4) node _T_15 = bits(cs.fu_code, 5, 5) node _T_16 = bits(cs.fu_code, 6, 6) node _T_17 = bits(cs.fu_code, 7, 7) node _T_18 = bits(cs.fu_code, 8, 8) node _T_19 = bits(cs.fu_code, 9, 9) connect uop.fu_code[0], _T_10 connect uop.fu_code[1], _T_11 connect uop.fu_code[2], _T_12 connect uop.fu_code[3], _T_13 connect uop.fu_code[4], _T_14 connect uop.fu_code[5], _T_15 connect uop.fu_code[6], _T_16 connect uop.fu_code[7], _T_17 connect uop.fu_code[8], _T_18 connect uop.fu_code[9], _T_19 connect uop.ldst, LDST connect uop.lrs1, LRS1 connect uop.lrs2, LRS2 connect uop.lrs3, LRS3 connect uop.dst_rtype, cs.dst_type node _uop_lrs1_rtype_T = eq(cs.rs1_type, UInt<2>(0h0)) node _uop_lrs1_rtype_T_1 = eq(LRS1, UInt<1>(0h0)) node _uop_lrs1_rtype_T_2 = and(_uop_lrs1_rtype_T, _uop_lrs1_rtype_T_1) node _uop_lrs1_rtype_T_3 = mux(_uop_lrs1_rtype_T_2, UInt<2>(0h3), cs.rs1_type) connect uop.lrs1_rtype, _uop_lrs1_rtype_T_3 node _uop_lrs2_rtype_T = eq(cs.rs2_type, UInt<2>(0h0)) node _uop_lrs2_rtype_T_1 = eq(LRS2, UInt<1>(0h0)) node _uop_lrs2_rtype_T_2 = and(_uop_lrs2_rtype_T, _uop_lrs2_rtype_T_1) node _uop_lrs2_rtype_T_3 = mux(_uop_lrs2_rtype_T_2, UInt<2>(0h3), cs.rs2_type) connect uop.lrs2_rtype, _uop_lrs2_rtype_T_3 connect uop.frs3_en, cs.frs3_en node _uop_ldst_is_rs1_T = eq(uop.br_type, UInt<4>(0h0)) node _uop_ldst_is_rs1_T_1 = and(_uop_ldst_is_rs1_T, uop.is_sfb) node _uop_ldst_is_rs1_T_2 = and(_uop_ldst_is_rs1_T_1, UInt<1>(0h1)) connect uop.ldst_is_rs1, _uop_ldst_is_rs1_T_2 node _T_20 = eq(uop.br_type, UInt<4>(0h0)) node _T_21 = and(_T_20, uop.is_sfb) node _T_22 = and(_T_21, UInt<1>(0h1)) node _T_23 = eq(cs.rs2_type, UInt<2>(0h2)) node _T_24 = and(_T_22, _T_23) when _T_24 : node _uop_lrs2_rtype_T_4 = eq(LDST, UInt<1>(0h0)) node _uop_lrs2_rtype_T_5 = mux(_uop_lrs2_rtype_T_4, UInt<2>(0h3), UInt<2>(0h0)) connect uop.lrs2_rtype, _uop_lrs2_rtype_T_5 connect uop.lrs2, LDST connect uop.ldst_is_rs1, UInt<1>(0h0) else : node _T_25 = eq(uop.br_type, UInt<4>(0h0)) node _T_26 = and(_T_25, uop.is_sfb) node _T_27 = and(_T_26, UInt<1>(0h1)) node _T_28 = and(_T_27, uop.is_mov) when _T_28 : connect uop.lrs1, LDST node _uop_lrs1_rtype_T_4 = eq(LDST, UInt<1>(0h0)) node _uop_lrs1_rtype_T_5 = mux(_uop_lrs1_rtype_T_4, UInt<2>(0h3), UInt<2>(0h0)) connect uop.lrs1_rtype, _uop_lrs1_rtype_T_5 connect uop.ldst_is_rs1, UInt<1>(0h1) connect uop.fp_val, cs.fp_val connect uop.fp_ctrl, cs.fp connect uop.mem_cmd, cs.mem_cmd node _uop_mem_size_T = eq(cs.mem_cmd, UInt<5>(0h14)) node _uop_mem_size_T_1 = eq(cs.mem_cmd, UInt<3>(0h5)) node _uop_mem_size_T_2 = or(_uop_mem_size_T, _uop_mem_size_T_1) node _uop_mem_size_T_3 = neq(LRS2, UInt<1>(0h0)) node _uop_mem_size_T_4 = neq(LRS1, UInt<1>(0h0)) node _uop_mem_size_T_5 = cat(_uop_mem_size_T_3, _uop_mem_size_T_4) node _uop_mem_size_T_6 = bits(uop.inst, 13, 12) node _uop_mem_size_T_7 = mux(_uop_mem_size_T_2, _uop_mem_size_T_5, _uop_mem_size_T_6) connect uop.mem_size, _uop_mem_size_T_7 node _uop_mem_signed_T = bits(uop.inst, 14, 14) node _uop_mem_signed_T_1 = eq(_uop_mem_signed_T, UInt<1>(0h0)) connect uop.mem_signed, _uop_mem_signed_T_1 connect uop.uses_ldq, cs.uses_ldq connect uop.uses_stq, cs.uses_stq connect uop.is_amo, cs.is_amo node _uop_is_fence_T = and(uop.inst, UInt<15>(0h707f)) node _uop_is_fence_T_1 = eq(UInt<4>(0hf), _uop_is_fence_T) connect uop.is_fence, _uop_is_fence_T_1 node _uop_is_fencei_T = and(uop.inst, UInt<15>(0h707f)) node _uop_is_fencei_T_1 = eq(UInt<13>(0h100f), _uop_is_fencei_T) connect uop.is_fencei, _uop_is_fencei_T_1 node _uop_is_sfence_T = and(uop.inst, UInt<32>(0hfe007fff)) node _uop_is_sfence_T_1 = eq(UInt<29>(0h12000073), _uop_is_sfence_T) connect uop.is_sfence, _uop_is_sfence_T_1 node _uop_is_sys_pc2epc_T = and(uop.inst, UInt<32>(0hffffffff)) node _uop_is_sys_pc2epc_T_1 = eq(UInt<21>(0h100073), _uop_is_sys_pc2epc_T) node _uop_is_sys_pc2epc_T_2 = and(uop.inst, UInt<32>(0hffffffff)) node _uop_is_sys_pc2epc_T_3 = eq(UInt<7>(0h73), _uop_is_sys_pc2epc_T_2) node _uop_is_sys_pc2epc_T_4 = or(_uop_is_sys_pc2epc_T_1, _uop_is_sys_pc2epc_T_3) connect uop.is_sys_pc2epc, _uop_is_sys_pc2epc_T_4 node _uop_is_eret_T = and(uop.inst, UInt<32>(0hffffffff)) node _uop_is_eret_T_1 = eq(UInt<7>(0h73), _uop_is_eret_T) node _uop_is_eret_T_2 = and(uop.inst, UInt<32>(0hffffffff)) node _uop_is_eret_T_3 = eq(UInt<21>(0h100073), _uop_is_eret_T_2) node _uop_is_eret_T_4 = or(_uop_is_eret_T_1, _uop_is_eret_T_3) node _uop_is_eret_T_5 = and(uop.inst, UInt<32>(0hffffffff)) node _uop_is_eret_T_6 = eq(UInt<29>(0h10200073), _uop_is_eret_T_5) node _uop_is_eret_T_7 = or(_uop_is_eret_T_4, _uop_is_eret_T_6) node _uop_is_eret_T_8 = and(uop.inst, UInt<32>(0hffffffff)) node _uop_is_eret_T_9 = eq(UInt<30>(0h30200073), _uop_is_eret_T_8) node _uop_is_eret_T_10 = or(_uop_is_eret_T_7, _uop_is_eret_T_9) node _uop_is_eret_T_11 = and(uop.inst, UInt<32>(0hffffffff)) node _uop_is_eret_T_12 = eq(UInt<31>(0h7b200073), _uop_is_eret_T_11) node _uop_is_eret_T_13 = or(_uop_is_eret_T_10, _uop_is_eret_T_12) connect uop.is_eret, _uop_is_eret_T_13 connect uop.is_unique, cs.inst_unique node _uop_is_rocc_T = bits(uop.inst, 6, 0) node _uop_is_rocc_T_1 = eq(_uop_is_rocc_T, UInt<4>(0hb)) node _uop_is_rocc_T_2 = eq(_uop_is_rocc_T, UInt<6>(0h2b)) node _uop_is_rocc_T_3 = eq(_uop_is_rocc_T, UInt<7>(0h7b)) node _uop_is_rocc_T_4 = or(_uop_is_rocc_T_1, _uop_is_rocc_T_2) node _uop_is_rocc_T_5 = or(_uop_is_rocc_T_4, _uop_is_rocc_T_3) node _uop_is_rocc_T_6 = bits(uop.inst, 14, 12) node _uop_is_rocc_T_7 = eq(_uop_is_rocc_T_6, UInt<1>(0h0)) node _uop_is_rocc_T_8 = eq(_uop_is_rocc_T_6, UInt<2>(0h2)) node _uop_is_rocc_T_9 = eq(_uop_is_rocc_T_6, UInt<2>(0h3)) node _uop_is_rocc_T_10 = eq(_uop_is_rocc_T_6, UInt<3>(0h4)) node _uop_is_rocc_T_11 = eq(_uop_is_rocc_T_6, UInt<3>(0h6)) node _uop_is_rocc_T_12 = eq(_uop_is_rocc_T_6, UInt<3>(0h7)) node _uop_is_rocc_T_13 = or(_uop_is_rocc_T_7, _uop_is_rocc_T_8) node _uop_is_rocc_T_14 = or(_uop_is_rocc_T_13, _uop_is_rocc_T_9) node _uop_is_rocc_T_15 = or(_uop_is_rocc_T_14, _uop_is_rocc_T_10) node _uop_is_rocc_T_16 = or(_uop_is_rocc_T_15, _uop_is_rocc_T_11) node _uop_is_rocc_T_17 = or(_uop_is_rocc_T_16, _uop_is_rocc_T_12) node _uop_is_rocc_T_18 = and(_uop_is_rocc_T_5, _uop_is_rocc_T_17) connect uop.is_rocc, _uop_is_rocc_T_18 node _uop_flush_on_commit_T = eq(csr_ren, UInt<1>(0h0)) node _uop_flush_on_commit_T_1 = and(csr_en, _uop_flush_on_commit_T) node _uop_flush_on_commit_T_2 = and(_uop_flush_on_commit_T_1, io.csr_decode.write_flush) node _uop_flush_on_commit_T_3 = or(cs.flush_on_commit, _uop_flush_on_commit_T_2) connect uop.flush_on_commit, _uop_flush_on_commit_T_3 node _di24_20_T = eq(cs.imm_sel, UInt<3>(0h2)) node _di24_20_T_1 = eq(cs.imm_sel, UInt<3>(0h1)) node _di24_20_T_2 = or(_di24_20_T, _di24_20_T_1) node _di24_20_T_3 = bits(uop.inst, 11, 7) node _di24_20_T_4 = bits(uop.inst, 24, 20) node di24_20 = mux(_di24_20_T_2, _di24_20_T_3, _di24_20_T_4) node _imm_packed_T = bits(uop.inst, 31, 25) node _imm_packed_T_1 = bits(uop.inst, 19, 12) node imm_packed_hi = cat(_imm_packed_T, di24_20) node imm_packed = cat(imm_packed_hi, _imm_packed_T_1) node _imm_ip_T = eq(cs.imm_sel, UInt<3>(0h6)) node imm_ip = mux(_imm_ip_T, UInt<20>(0h0), imm_packed) node _imm_sign_T = bits(imm_ip, 19, 19) node imm_sign = asSInt(_imm_sign_T) node _imm_i30_20_T = eq(cs.imm_sel, UInt<3>(0h3)) node _imm_i30_20_T_1 = bits(imm_ip, 18, 8) node _imm_i30_20_T_2 = asSInt(_imm_i30_20_T_1) node imm_i30_20 = mux(_imm_i30_20_T, _imm_i30_20_T_2, imm_sign) node _imm_i19_12_T = eq(cs.imm_sel, UInt<3>(0h3)) node _imm_i19_12_T_1 = eq(cs.imm_sel, UInt<3>(0h4)) node _imm_i19_12_T_2 = or(_imm_i19_12_T, _imm_i19_12_T_1) node _imm_i19_12_T_3 = bits(imm_ip, 7, 0) node _imm_i19_12_T_4 = asSInt(_imm_i19_12_T_3) node imm_i19_12 = mux(_imm_i19_12_T_2, _imm_i19_12_T_4, imm_sign) node _imm_i11_T = eq(cs.imm_sel, UInt<3>(0h3)) node _imm_i11_T_1 = eq(cs.imm_sel, UInt<3>(0h4)) node _imm_i11_T_2 = eq(cs.imm_sel, UInt<3>(0h2)) node _imm_i11_T_3 = or(_imm_i11_T_1, _imm_i11_T_2) node _imm_i11_T_4 = bits(imm_ip, 8, 8) node _imm_i11_T_5 = asSInt(_imm_i11_T_4) node _imm_i11_T_6 = mux(_imm_i11_T_3, _imm_i11_T_5, imm_sign) node imm_i11 = mux(_imm_i11_T, asSInt(UInt<1>(0h0)), _imm_i11_T_6) node _imm_i10_5_T = eq(cs.imm_sel, UInt<3>(0h3)) node _imm_i10_5_T_1 = bits(imm_ip, 18, 14) node _imm_i10_5_T_2 = asSInt(_imm_i10_5_T_1) node imm_i10_5 = mux(_imm_i10_5_T, asSInt(UInt<1>(0h0)), _imm_i10_5_T_2) node _imm_i4_1_T = eq(cs.imm_sel, UInt<3>(0h3)) node _imm_i4_1_T_1 = bits(imm_ip, 13, 9) node _imm_i4_1_T_2 = asSInt(_imm_i4_1_T_1) node imm_i4_1 = mux(_imm_i4_1_T, asSInt(UInt<1>(0h0)), _imm_i4_1_T_2) node _imm_i0_T = eq(cs.imm_sel, UInt<3>(0h1)) node _imm_i0_T_1 = eq(cs.imm_sel, UInt<3>(0h0)) node _imm_i0_T_2 = or(_imm_i0_T, _imm_i0_T_1) node _imm_i0_T_3 = bits(imm_ip, 8, 8) node _imm_i0_T_4 = asSInt(_imm_i0_T_3) node imm_i0 = mux(_imm_i0_T_2, _imm_i0_T_4, asSInt(UInt<1>(0h0))) node imm_lo_lo = asUInt(imm_i0) node imm_lo_hi_lo = asUInt(imm_i4_1) node imm_lo_hi_hi = asUInt(imm_i10_5) node imm_lo_hi = cat(imm_lo_hi_hi, imm_lo_hi_lo) node imm_lo = cat(imm_lo_hi, imm_lo_lo) node imm_hi_lo_lo = asUInt(imm_i11) node imm_hi_lo_hi = asUInt(imm_i19_12) node imm_hi_lo = cat(imm_hi_lo_hi, imm_hi_lo_lo) node imm_hi_hi_lo = asUInt(imm_i30_20) node imm_hi_hi_hi = asUInt(imm_sign) node imm_hi_hi = cat(imm_hi_hi_hi, imm_hi_hi_lo) node imm_hi = cat(imm_hi_hi, imm_hi_lo) node imm = cat(imm_hi, imm_lo) node imm_hi_1 = shr(imm, 4) node imm_lo_1 = bits(imm, 4, 0) node _short_imm_T = eq(imm_hi_1, UInt<1>(0h0)) node _short_imm_T_1 = not(imm_hi_1) node _short_imm_T_2 = eq(_short_imm_T_1, UInt<1>(0h0)) node _short_imm_T_3 = or(_short_imm_T, _short_imm_T_2) node _short_imm_T_4 = eq(cs.imm_sel, UInt<3>(0h7)) node short_imm = or(_short_imm_T_3, _short_imm_T_4) node _uop_imm_rename_T = neq(cs.imm_sel, UInt<3>(0h6)) node _uop_imm_rename_T_1 = neq(cs.imm_sel, UInt<3>(0h7)) node _uop_imm_rename_T_2 = and(_uop_imm_rename_T, _uop_imm_rename_T_1) connect uop.imm_rename, _uop_imm_rename_T_2 connect uop.imm_packed, imm_packed connect uop.imm_sel, cs.imm_sel when short_imm : connect uop.imm_rename, UInt<1>(0h0) connect uop.imm_sel, UInt<3>(0h5) node _uop_pimm_T = eq(cs.imm_sel, UInt<3>(0h7)) node _uop_pimm_T_1 = bits(uop.inst, 14, 12) node _uop_pimm_T_2 = mux(_uop_pimm_T, _uop_pimm_T_1, imm_lo_1) connect uop.pimm, _uop_pimm_T_2 node _uop_fp_rm_T = bits(uop.inst, 14, 12) node _uop_fp_rm_T_1 = eq(_uop_fp_rm_T, UInt<3>(0h7)) node _uop_fp_rm_T_2 = bits(uop.inst, 14, 12) node _uop_fp_rm_T_3 = mux(_uop_fp_rm_T_1, io.fcsr_rm, _uop_fp_rm_T_2) connect uop.fp_rm, _uop_fp_rm_T_3 node _uop_fp_typ_T = bits(uop.inst, 21, 20) connect uop.fp_typ, _uop_fp_typ_T connect uop.csr_cmd, cs.csr_cmd node _T_29 = eq(cs.csr_cmd, UInt<3>(0h6)) node _T_30 = eq(cs.csr_cmd, UInt<3>(0h7)) node _T_31 = or(_T_29, _T_30) node _T_32 = eq(LRS1, UInt<1>(0h0)) node _T_33 = and(_T_31, _T_32) when _T_33 : connect uop.csr_cmd, UInt<3>(0h2) connect uop.fcn_dw, cs.fcn_dw connect uop.fcn_op, cs.fcn_op connect uop.op1_sel, UInt<2>(0h0) node _T_34 = and(uop.inst, UInt<7>(0h7f)) node _T_35 = eq(UInt<6>(0h37), _T_34) node _T_36 = and(uop.inst, UInt<15>(0h707f)) node _T_37 = eq(UInt<15>(0h5073), _T_36) node _T_38 = or(_T_35, _T_37) node _T_39 = and(uop.inst, UInt<15>(0h707f)) node _T_40 = eq(UInt<15>(0h6073), _T_39) node _T_41 = or(_T_38, _T_40) node _T_42 = and(uop.inst, UInt<15>(0h707f)) node _T_43 = eq(UInt<15>(0h7073), _T_42) node _T_44 = or(_T_41, _T_43) node _T_45 = and(uop.inst, UInt<32>(0hffffffff)) node _T_46 = eq(UInt<29>(0h10500073), _T_45) node _T_47 = or(_T_44, _T_46) node _T_48 = and(uop.inst, UInt<32>(0hffffffff)) node _T_49 = eq(UInt<29>(0h10200073), _T_48) node _T_50 = or(_T_47, _T_49) node _T_51 = and(uop.inst, UInt<32>(0hffffffff)) node _T_52 = eq(UInt<30>(0h30200073), _T_51) node _T_53 = or(_T_50, _T_52) node _T_54 = and(uop.inst, UInt<32>(0hffffffff)) node _T_55 = eq(UInt<31>(0h7b200073), _T_54) node _T_56 = or(_T_53, _T_55) when _T_56 : connect uop.op1_sel, UInt<2>(0h1) else : node _T_57 = and(uop.inst, UInt<7>(0h7f)) node _T_58 = eq(UInt<7>(0h6f), _T_57) node _T_59 = and(uop.inst, UInt<15>(0h707f)) node _T_60 = eq(UInt<7>(0h67), _T_59) node _T_61 = or(_T_58, _T_60) node _T_62 = and(uop.inst, UInt<7>(0h7f)) node _T_63 = eq(UInt<5>(0h17), _T_62) node _T_64 = or(_T_61, _T_63) when _T_64 : connect uop.op1_sel, UInt<2>(0h2) else : node _T_65 = and(uop.inst, UInt<32>(0hfe00707f)) node _T_66 = eq(UInt<30>(0h20002033), _T_65) node _T_67 = and(uop.inst, UInt<32>(0hfe00707f)) node _T_68 = eq(UInt<30>(0h20004033), _T_67) node _T_69 = and(uop.inst, UInt<32>(0hfe00707f)) node _T_70 = eq(UInt<30>(0h20006033), _T_69) node _T_71 = and(uop.inst, UInt<32>(0hfe00707f)) node _T_72 = eq(UInt<30>(0h2000203b), _T_71) node _T_73 = and(uop.inst, UInt<32>(0hfe00707f)) node _T_74 = eq(UInt<30>(0h2000403b), _T_73) node _T_75 = and(uop.inst, UInt<32>(0hfe00707f)) node _T_76 = eq(UInt<30>(0h2000603b), _T_75) node _T_77 = and(uop.inst, UInt<32>(0hfe00707f)) node _T_78 = eq(UInt<28>(0h800003b), _T_77) node _T_79 = and(uop.inst, UInt<32>(0hfc00707f)) node _T_80 = eq(UInt<28>(0h800101b), _T_79) node _T_81 = or(_T_66, _T_68) node _T_82 = or(_T_81, _T_70) node _T_83 = or(_T_82, _T_72) node _T_84 = or(_T_83, _T_74) node _T_85 = or(_T_84, _T_76) node _T_86 = or(_T_85, _T_78) node _T_87 = or(_T_86, _T_80) when _T_87 : connect uop.op1_sel, UInt<2>(0h3) connect uop.op2_sel, UInt<3>(0h0) node _T_88 = and(uop.inst, UInt<15>(0h707f)) node _T_89 = eq(UInt<13>(0h1073), _T_88) node _T_90 = or(cs.is_amo, _T_89) node _T_91 = and(uop.inst, UInt<15>(0h707f)) node _T_92 = eq(UInt<14>(0h2073), _T_91) node _T_93 = or(_T_90, _T_92) node _T_94 = and(uop.inst, UInt<15>(0h707f)) node _T_95 = eq(UInt<14>(0h3073), _T_94) node _T_96 = or(_T_93, _T_95) when _T_96 : connect uop.op2_sel, UInt<3>(0h2) else : node _T_97 = and(uop.inst, UInt<15>(0h707f)) node _T_98 = eq(UInt<15>(0h5073), _T_97) node _T_99 = and(uop.inst, UInt<15>(0h707f)) node _T_100 = eq(UInt<15>(0h6073), _T_99) node _T_101 = or(_T_98, _T_100) node _T_102 = and(uop.inst, UInt<15>(0h707f)) node _T_103 = eq(UInt<15>(0h7073), _T_102) node _T_104 = or(_T_101, _T_103) node _T_105 = and(uop.inst, UInt<32>(0hffffffff)) node _T_106 = eq(UInt<29>(0h10500073), _T_105) node _T_107 = or(_T_104, _T_106) node _T_108 = and(uop.inst, UInt<32>(0hffffffff)) node _T_109 = eq(UInt<29>(0h10200073), _T_108) node _T_110 = or(_T_107, _T_109) node _T_111 = and(uop.inst, UInt<32>(0hffffffff)) node _T_112 = eq(UInt<31>(0h7b200073), _T_111) node _T_113 = or(_T_110, _T_112) node _T_114 = and(uop.inst, UInt<32>(0hffffffff)) node _T_115 = eq(UInt<30>(0h30200073), _T_114) node _T_116 = or(_T_113, _T_115) when _T_116 : connect uop.op2_sel, UInt<3>(0h4) else : node _T_117 = and(uop.inst, UInt<7>(0h7f)) node _T_118 = eq(UInt<7>(0h6f), _T_117) node _T_119 = and(uop.inst, UInt<15>(0h707f)) node _T_120 = eq(UInt<7>(0h67), _T_119) node _T_121 = or(_T_118, _T_120) when _T_121 : connect uop.op2_sel, UInt<3>(0h3) else : node _T_122 = and(uop.inst, UInt<32>(0hfe00707f)) node _T_123 = eq(UInt<31>(0h48001033), _T_122) node _T_124 = and(uop.inst, UInt<32>(0hfc00707f)) node _T_125 = eq(UInt<31>(0h48001013), _T_124) node _T_126 = and(uop.inst, UInt<32>(0hfe00707f)) node _T_127 = eq(UInt<31>(0h68001033), _T_126) node _T_128 = and(uop.inst, UInt<32>(0hfc00707f)) node _T_129 = eq(UInt<31>(0h68001013), _T_128) node _T_130 = and(uop.inst, UInt<32>(0hfe00707f)) node _T_131 = eq(UInt<30>(0h28001033), _T_130) node _T_132 = and(uop.inst, UInt<32>(0hfc00707f)) node _T_133 = eq(UInt<30>(0h28001013), _T_132) node _T_134 = or(_T_123, _T_125) node _T_135 = or(_T_134, _T_127) node _T_136 = or(_T_135, _T_129) node _T_137 = or(_T_136, _T_131) node _T_138 = or(_T_137, _T_133) when _T_138 : node _uop_op2_sel_T = eq(uop.lrs2_rtype, UInt<2>(0h0)) node _uop_op2_sel_T_1 = mux(_uop_op2_sel_T, UInt<3>(0h5), UInt<3>(0h6)) connect uop.op2_sel, _uop_op2_sel_T_1 else : node _T_139 = eq(cs.imm_sel, UInt<3>(0h3)) node _T_140 = eq(cs.imm_sel, UInt<3>(0h0)) node _T_141 = or(_T_139, _T_140) node _T_142 = eq(cs.imm_sel, UInt<3>(0h1)) node _T_143 = or(_T_141, _T_142) when _T_143 : connect uop.op2_sel, UInt<3>(0h1) node _uop_br_type_T = and(uop.inst, UInt<15>(0h707f)) node _uop_br_type_T_1 = eq(UInt<7>(0h63), _uop_br_type_T) node _uop_br_type_T_2 = mux(_uop_br_type_T_1, UInt<4>(0h2), UInt<1>(0h0)) node _uop_br_type_T_3 = and(uop.inst, UInt<15>(0h707f)) node _uop_br_type_T_4 = eq(UInt<13>(0h1063), _uop_br_type_T_3) node _uop_br_type_T_5 = mux(_uop_br_type_T_4, UInt<4>(0h1), UInt<1>(0h0)) node _uop_br_type_T_6 = and(uop.inst, UInt<15>(0h707f)) node _uop_br_type_T_7 = eq(UInt<15>(0h5063), _uop_br_type_T_6) node _uop_br_type_T_8 = mux(_uop_br_type_T_7, UInt<4>(0h3), UInt<1>(0h0)) node _uop_br_type_T_9 = and(uop.inst, UInt<15>(0h707f)) node _uop_br_type_T_10 = eq(UInt<15>(0h7063), _uop_br_type_T_9) node _uop_br_type_T_11 = mux(_uop_br_type_T_10, UInt<4>(0h4), UInt<1>(0h0)) node _uop_br_type_T_12 = and(uop.inst, UInt<15>(0h707f)) node _uop_br_type_T_13 = eq(UInt<15>(0h4063), _uop_br_type_T_12) node _uop_br_type_T_14 = mux(_uop_br_type_T_13, UInt<4>(0h5), UInt<1>(0h0)) node _uop_br_type_T_15 = and(uop.inst, UInt<15>(0h707f)) node _uop_br_type_T_16 = eq(UInt<15>(0h6063), _uop_br_type_T_15) node _uop_br_type_T_17 = mux(_uop_br_type_T_16, UInt<4>(0h6), UInt<1>(0h0)) node _uop_br_type_T_18 = and(uop.inst, UInt<7>(0h7f)) node _uop_br_type_T_19 = eq(UInt<7>(0h6f), _uop_br_type_T_18) node _uop_br_type_T_20 = mux(_uop_br_type_T_19, UInt<4>(0h7), UInt<1>(0h0)) node _uop_br_type_T_21 = and(uop.inst, UInt<15>(0h707f)) node _uop_br_type_T_22 = eq(UInt<7>(0h67), _uop_br_type_T_21) node _uop_br_type_T_23 = mux(_uop_br_type_T_22, UInt<4>(0h8), UInt<1>(0h0)) node _uop_br_type_T_24 = or(_uop_br_type_T_2, _uop_br_type_T_5) node _uop_br_type_T_25 = or(_uop_br_type_T_24, _uop_br_type_T_8) node _uop_br_type_T_26 = or(_uop_br_type_T_25, _uop_br_type_T_11) node _uop_br_type_T_27 = or(_uop_br_type_T_26, _uop_br_type_T_14) node _uop_br_type_T_28 = or(_uop_br_type_T_27, _uop_br_type_T_17) node _uop_br_type_T_29 = or(_uop_br_type_T_28, _uop_br_type_T_20) node _uop_br_type_T_30 = or(_uop_br_type_T_29, _uop_br_type_T_23) connect uop.br_type, _uop_br_type_T_30 connect io.deq.uop, uop	module DecodeUnit_2( // @[decode.scala:422:7] input clock, // @[decode.scala:422:7] input reset, // @[decode.scala:422:7] input [31:0] io_enq_uop_inst, // @[decode.scala:426:14] input [31:0] io_enq_uop_debug_inst, // @[decode.scala:426:14] input io_enq_uop_is_rvc, // @[decode.scala:426:14] input [39:0] io_enq_uop_debug_pc, // @[decode.scala:426:14] input io_enq_uop_is_sfb, // @[decode.scala:426:14] input [4:0] io_enq_uop_ftq_idx, // @[decode.scala:426:14] input io_enq_uop_edge_inst, // @[decode.scala:426:14] input [5:0] io_enq_uop_pc_lob, // @[decode.scala:426:14] input io_enq_uop_taken, // @[decode.scala:426:14] input io_enq_uop_xcpt_pf_if, // @[decode.scala:426:14] input io_enq_uop_xcpt_ae_if, // @[decode.scala:426:14] input io_enq_uop_bp_debug_if, // @[decode.scala:426:14] input io_enq_uop_bp_xcpt_if, // @[decode.scala:426:14] input [2:0] io_enq_uop_debug_fsrc, // @[decode.scala:426:14] output [31:0] io_deq_uop_inst, // @[decode.scala:426:14] output [31:0] io_deq_uop_debug_inst, // @[decode.scala:426:14] output io_deq_uop_is_rvc, // @[decode.scala:426:14] output [39:0] io_deq_uop_debug_pc, // @[decode.scala:426:14] output io_deq_uop_iq_type_0, // @[decode.scala:426:14] output io_deq_uop_iq_type_1, // @[decode.scala:426:14] output io_deq_uop_iq_type_2, // @[decode.scala:426:14] output io_deq_uop_iq_type_3, // @[decode.scala:426:14] output io_deq_uop_fu_code_0, // @[decode.scala:426:14] output io_deq_uop_fu_code_1, // @[decode.scala:426:14] output io_deq_uop_fu_code_2, // @[decode.scala:426:14] output io_deq_uop_fu_code_3, // @[decode.scala:426:14] output io_deq_uop_fu_code_4, // @[decode.scala:426:14] output io_deq_uop_fu_code_5, // @[decode.scala:426:14] output io_deq_uop_fu_code_6, // @[decode.scala:426:14] output io_deq_uop_fu_code_7, // @[decode.scala:426:14] output io_deq_uop_fu_code_8, // @[decode.scala:426:14] output io_deq_uop_fu_code_9, // @[decode.scala:426:14] output [3:0] io_deq_uop_br_type, // @[decode.scala:426:14] output io_deq_uop_is_sfb, // @[decode.scala:426:14] output io_deq_uop_is_fence, // @[decode.scala:426:14] output io_deq_uop_is_fencei, // @[decode.scala:426:14] output io_deq_uop_is_sfence, // @[decode.scala:426:14] output io_deq_uop_is_amo, // @[decode.scala:426:14] output io_deq_uop_is_eret, // @[decode.scala:426:14] output io_deq_uop_is_sys_pc2epc, // @[decode.scala:426:14] output io_deq_uop_is_rocc, // @[decode.scala:426:14] output io_deq_uop_is_mov, // @[decode.scala:426:14] output [4:0] io_deq_uop_ftq_idx, // @[decode.scala:426:14] output io_deq_uop_edge_inst, // @[decode.scala:426:14] output [5:0] io_deq_uop_pc_lob, // @[decode.scala:426:14] output io_deq_uop_taken, // @[decode.scala:426:14] output io_deq_uop_imm_rename, // @[decode.scala:426:14] output [2:0] io_deq_uop_imm_sel, // @[decode.scala:426:14] output [4:0] io_deq_uop_pimm, // @[decode.scala:426:14] output [19:0] io_deq_uop_imm_packed, // @[decode.scala:426:14] output [1:0] io_deq_uop_op1_sel, // @[decode.scala:426:14] output [2:0] io_deq_uop_op2_sel, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ldst, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_wen, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ren1, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ren2, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_ren3, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_swap12, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_swap23, // @[decode.scala:426:14] output [1:0] io_deq_uop_fp_ctrl_typeTagIn, // @[decode.scala:426:14] output [1:0] io_deq_uop_fp_ctrl_typeTagOut, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_fromint, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_toint, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_fastpipe, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_fma, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_div, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_sqrt, // @[decode.scala:426:14] output io_deq_uop_fp_ctrl_wflags, // @[decode.scala:426:14] output io_deq_uop_exception, // @[decode.scala:426:14] output [63:0] io_deq_uop_exc_cause, // @[decode.scala:426:14] output [4:0] io_deq_uop_mem_cmd, // @[decode.scala:426:14] output [1:0] io_deq_uop_mem_size, // @[decode.scala:426:14] output io_deq_uop_mem_signed, // @[decode.scala:426:14] output io_deq_uop_uses_ldq, // @[decode.scala:426:14] output io_deq_uop_uses_stq, // @[decode.scala:426:14] output io_deq_uop_is_unique, // @[decode.scala:426:14] output io_deq_uop_flush_on_commit, // @[decode.scala:426:14] output [2:0] io_deq_uop_csr_cmd, // @[decode.scala:426:14] output io_deq_uop_ldst_is_rs1, // @[decode.scala:426:14] output [5:0] io_deq_uop_ldst, // @[decode.scala:426:14] output [5:0] io_deq_uop_lrs1, // @[decode.scala:426:14] output [5:0] io_deq_uop_lrs2, // @[decode.scala:426:14] output [5:0] io_deq_uop_lrs3, // @[decode.scala:426:14] output [1:0] io_deq_uop_dst_rtype, // @[decode.scala:426:14] output [1:0] io_deq_uop_lrs1_rtype, // @[decode.scala:426:14] output [1:0] io_deq_uop_lrs2_rtype, // @[decode.scala:426:14] output io_deq_uop_frs3_en, // @[decode.scala:426:14] output io_deq_uop_fcn_dw, // @[decode.scala:426:14] output [4:0] io_deq_uop_fcn_op, // @[decode.scala:426:14] output io_deq_uop_fp_val, // @[decode.scala:426:14] output [2:0] io_deq_uop_fp_rm, // @[decode.scala:426:14] output [1:0] io_deq_uop_fp_typ, // @[decode.scala:426:14] output io_deq_uop_xcpt_pf_if, // @[decode.scala:426:14] output io_deq_uop_xcpt_ae_if, // @[decode.scala:426:14] output io_deq_uop_bp_debug_if, // @[decode.scala:426:14] output io_deq_uop_bp_xcpt_if, // @[decode.scala:426:14] output [2:0] io_deq_uop_debug_fsrc, // @[decode.scala:426:14] input io_status_debug, // @[decode.scala:426:14] input io_status_cease, // @[decode.scala:426:14] input io_status_wfi, // @[decode.scala:426:14] input [1:0] io_status_dprv, // @[decode.scala:426:14] input io_status_dv, // @[decode.scala:426:14] input [1:0] io_status_prv, // @[decode.scala:426:14] input io_status_v, // @[decode.scala:426:14] input io_status_sd, // @[decode.scala:426:14] input io_status_mpv, // @[decode.scala:426:14] input io_status_gva, // @[decode.scala:426:14] input io_status_tsr, // @[decode.scala:426:14] input io_status_tw, // @[decode.scala:426:14] input io_status_tvm, // @[decode.scala:426:14] input io_status_mxr, // @[decode.scala:426:14] input io_status_sum, // @[decode.scala:426:14] input io_status_mprv, // @[decode.scala:426:14] input [1:0] io_status_fs, // @[decode.scala:426:14] input [1:0] io_status_mpp, // @[decode.scala:426:14] input io_status_spp, // @[decode.scala:426:14] input io_status_mpie, // @[decode.scala:426:14] input io_status_spie, // @[decode.scala:426:14] input io_status_mie, // @[decode.scala:426:14] input io_status_sie, // @[decode.scala:426:14] output [31:0] io_csr_decode_inst, // @[decode.scala:426:14] input io_csr_decode_fp_illegal, // @[decode.scala:426:14] input io_csr_decode_fp_csr, // @[decode.scala:426:14] input io_csr_decode_read_illegal, // @[decode.scala:426:14] input io_csr_decode_write_illegal, // @[decode.scala:426:14] input io_csr_decode_write_flush, // @[decode.scala:426:14] input io_csr_decode_system_illegal, // @[decode.scala:426:14] input io_csr_decode_virtual_access_illegal, // @[decode.scala:426:14] input io_csr_decode_virtual_system_illegal, // @[decode.scala:426:14] input [2:0] io_fcsr_rm, // @[decode.scala:426:14] input io_interrupt, // @[decode.scala:426:14] input [63:0] io_interrupt_cause // @[decode.scala:426:14] ); wire [31:0] io_enq_uop_inst_0 = io_enq_uop_inst; // @[decode.scala:422:7] wire [31:0] io_enq_uop_debug_inst_0 = io_enq_uop_debug_inst; // @[decode.scala:422:7] wire io_enq_uop_is_rvc_0 = io_enq_uop_is_rvc; // @[decode.scala:422:7] wire [39:0] io_enq_uop_debug_pc_0 = io_enq_uop_debug_pc; // @[decode.scala:422:7] wire io_enq_uop_is_sfb_0 = io_enq_uop_is_sfb; // @[decode.scala:422:7] wire [4:0] io_enq_uop_ftq_idx_0 = io_enq_uop_ftq_idx; // @[decode.scala:422:7] wire io_enq_uop_edge_inst_0 = io_enq_uop_edge_inst; // @[decode.scala:422:7] wire [5:0] io_enq_uop_pc_lob_0 = io_enq_uop_pc_lob; // @[decode.scala:422:7] wire io_enq_uop_taken_0 = io_enq_uop_taken; // @[decode.scala:422:7] wire io_enq_uop_xcpt_pf_if_0 = io_enq_uop_xcpt_pf_if; // @[decode.scala:422:7] wire io_enq_uop_xcpt_ae_if_0 = io_enq_uop_xcpt_ae_if; // @[decode.scala:422:7] wire io_enq_uop_bp_debug_if_0 = io_enq_uop_bp_debug_if; // @[decode.scala:422:7] wire io_enq_uop_bp_xcpt_if_0 = io_enq_uop_bp_xcpt_if; // @[decode.scala:422:7] wire [2:0] io_enq_uop_debug_fsrc_0 = io_enq_uop_debug_fsrc; // @[decode.scala:422:7] wire io_status_debug_0 = io_status_debug; // @[decode.scala:422:7] wire io_status_cease_0 = io_status_cease; // @[decode.scala:422:7] wire io_status_wfi_0 = io_status_wfi; // @[decode.scala:422:7] wire [1:0] io_status_dprv_0 = io_status_dprv; // @[decode.scala:422:7] wire io_status_dv_0 = io_status_dv; // @[decode.scala:422:7] wire [1:0] io_status_prv_0 = io_status_prv; // @[decode.scala:422:7] wire io_status_v_0 = io_status_v; // @[decode.scala:422:7] wire io_status_sd_0 = io_status_sd; // @[decode.scala:422:7] wire io_status_mpv_0 = io_status_mpv; // @[decode.scala:422:7] wire io_status_gva_0 = io_status_gva; // @[decode.scala:422:7] wire io_status_tsr_0 = io_status_tsr; // @[decode.scala:422:7] wire io_status_tw_0 = io_status_tw; // @[decode.scala:422:7] wire io_status_tvm_0 = io_status_tvm; // @[decode.scala:422:7] wire io_status_mxr_0 = io_status_mxr; // @[decode.scala:422:7] wire io_status_sum_0 = io_status_sum; // @[decode.scala:422:7] wire io_status_mprv_0 = io_status_mprv; // @[decode.scala:422:7] wire [1:0] io_status_fs_0 = io_status_fs; // @[decode.scala:422:7] wire [1:0] io_status_mpp_0 = io_status_mpp; // @[decode.scala:422:7] wire io_status_spp_0 = io_status_spp; // @[decode.scala:422:7] wire io_status_mpie_0 = io_status_mpie; // @[decode.scala:422:7] wire io_status_spie_0 = io_status_spie; // @[decode.scala:422:7] wire io_status_mie_0 = io_status_mie; // @[decode.scala:422:7] wire io_status_sie_0 = io_status_sie; // @[decode.scala:422:7] wire io_csr_decode_fp_illegal_0 = io_csr_decode_fp_illegal; // @[decode.scala:422:7] wire io_csr_decode_fp_csr_0 = io_csr_decode_fp_csr; // @[decode.scala:422:7] wire io_csr_decode_read_illegal_0 = io_csr_decode_read_illegal; // @[decode.scala:422:7] wire io_csr_decode_write_illegal_0 = io_csr_decode_write_illegal; // @[decode.scala:422:7] wire io_csr_decode_write_flush_0 = io_csr_decode_write_flush; // @[decode.scala:422:7] wire io_csr_decode_system_illegal_0 = io_csr_decode_system_illegal; // @[decode.scala:422:7] wire io_csr_decode_virtual_access_illegal_0 = io_csr_decode_virtual_access_illegal; // @[decode.scala:422:7] wire io_csr_decode_virtual_system_illegal_0 = io_csr_decode_virtual_system_illegal; // @[decode.scala:422:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[decode.scala:422:7] wire io_interrupt_0 = io_interrupt; // @[decode.scala:422:7] wire [63:0] io_interrupt_cause_0 = io_interrupt_cause; // @[decode.scala:422:7] wire [1:0] io_status_sxl = 2'h2; // @[decode.scala:422:7] wire [1:0] io_status_uxl = 2'h2; // @[decode.scala:422:7] wire io_csr_decode_vector_illegal = 1'h1; // @[decode.scala:422:7] wire io_csr_decode_rocc_illegal = 1'h1; // @[decode.scala:422:7] wire _id_illegal_insn_T_6 = 1'h1; // @[decode.scala:464:33] wire [7:0] io_status_zero1 = 8'h0; // @[decode.scala:422:7, :426:14] wire [22:0] io_status_zero2 = 23'h0; // @[decode.scala:422:7, :426:14] wire [31:0] io_status_isa = 32'h14112D; // @[decode.scala:422:7, :426:14] wire [5:0] io_enq_uop_ldst = 6'h0; // @[decode.scala:422:7, :426:14] wire [5:0] io_enq_uop_lrs1 = 6'h0; // @[decode.scala:422:7, :426:14] wire [5:0] io_enq_uop_lrs2 = 6'h0; // @[decode.scala:422:7, :426:14] wire [5:0] io_enq_uop_lrs3 = 6'h0; // @[decode.scala:422:7, :426:14] wire [63:0] io_enq_uop_exc_cause = 64'h0; // @[decode.scala:422:7, :426:14] wire [6:0] io_enq_uop_rob_idx = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_prs1 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_prs2 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_prs3 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_enq_uop_stale_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_rob_idx = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_prs1 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_prs2 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_prs3 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] io_deq_uop_stale_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_rob_idx = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_prs1 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_prs2 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_prs3 = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [6:0] uop_stale_pdst = 7'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [1:0] io_enq_uop_op1_sel = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_fp_ctrl_typeTagIn = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_fp_ctrl_typeTagOut = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_rxq_idx = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_mem_size = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_dst_rtype = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_lrs1_rtype = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_lrs2_rtype = 2'h0; // @[decode.scala:422:7] wire [1:0] io_enq_uop_fp_typ = 2'h0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_rxq_idx = 2'h0; // @[decode.scala:422:7] wire [1:0] io_status_xs = 2'h0; // @[decode.scala:422:7] wire [1:0] io_status_vs = 2'h0; // @[decode.scala:422:7] wire [1:0] uop_rxq_idx = 2'h0; // @[decode.scala:428:17] wire [19:0] io_enq_uop_imm_packed = 20'h0; // @[decode.scala:422:7] wire [4:0] io_enq_uop_pimm = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_ldq_idx = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_stq_idx = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_ppred = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_mem_cmd = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_enq_uop_fcn_op = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_deq_uop_ldq_idx = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_deq_uop_stq_idx = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] io_deq_uop_ppred = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] uop_ldq_idx = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] uop_stq_idx = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [4:0] uop_ppred = 5'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [3:0] io_enq_uop_br_tag = 4'h0; // @[decode.scala:422:7] wire [3:0] io_enq_uop_br_type = 4'h0; // @[decode.scala:422:7] wire [3:0] io_deq_uop_br_tag = 4'h0; // @[decode.scala:422:7] wire [3:0] uop_br_tag = 4'h0; // @[decode.scala:428:17] wire [15:0] io_enq_uop_br_mask = 16'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [15:0] io_deq_uop_br_mask = 16'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [15:0] uop_br_mask = 16'h0; // @[decode.scala:422:7, :426:14, :428:17] wire [2:0] io_enq_uop_iw_p1_speculative_child = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_iw_p2_speculative_child = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_dis_col_sel = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_imm_sel = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_op2_sel = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_csr_cmd = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_fp_rm = 3'h0; // @[decode.scala:422:7] wire [2:0] io_enq_uop_debug_tsrc = 3'h0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_iw_p1_speculative_child = 3'h0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_iw_p2_speculative_child = 3'h0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_dis_col_sel = 3'h0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_debug_tsrc = 3'h0; // @[decode.scala:422:7] wire [2:0] uop_iw_p1_speculative_child = 3'h0; // @[decode.scala:428:17] wire [2:0] uop_iw_p2_speculative_child = 3'h0; // @[decode.scala:428:17] wire [2:0] uop_dis_col_sel = 3'h0; // @[decode.scala:428:17] wire [2:0] uop_debug_tsrc = 3'h0; // @[decode.scala:428:17] wire io_enq_uop_iq_type_0 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iq_type_1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iq_type_2 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iq_type_3 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_0 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_2 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_3 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_4 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_5 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_6 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_7 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_8 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fu_code_9 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_issued = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_issued_partial_agen = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_issued_partial_dgen = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_p1_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_p2_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_iw_p3_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_fence = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_fencei = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_sfence = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_amo = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_eret = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_sys_pc2epc = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_rocc = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_mov = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_imm_rename = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ldst = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_wen = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ren1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ren2 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_ren3 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_swap12 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_swap23 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_fromint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_toint = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_fastpipe = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_fma = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_div = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_sqrt = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_wflags = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_ctrl_vec = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_prs1_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_prs2_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_prs3_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_ppred_busy = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_exception = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_mem_signed = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_uses_ldq = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_uses_stq = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_is_unique = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_flush_on_commit = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_ldst_is_rs1 = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_frs3_en = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fcn_dw = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_fp_val = 1'h0; // @[decode.scala:422:7] wire io_enq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_issued = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_issued_partial_agen = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_issued_partial_dgen = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_p1_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_p2_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_iw_p3_bypass_hint = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_vec = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_prs1_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_prs2_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_prs3_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_ppred_busy = 1'h0; // @[decode.scala:422:7] wire io_deq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:422:7] wire io_status_mbe = 1'h0; // @[decode.scala:422:7] wire io_status_sbe = 1'h0; // @[decode.scala:422:7] wire io_status_sd_rv32 = 1'h0; // @[decode.scala:422:7] wire io_status_ube = 1'h0; // @[decode.scala:422:7] wire io_status_upie = 1'h0; // @[decode.scala:422:7] wire io_status_hie = 1'h0; // @[decode.scala:422:7] wire io_status_uie = 1'h0; // @[decode.scala:422:7] wire io_csr_decode_vector_csr = 1'h0; // @[decode.scala:422:7] wire uop_iw_issued = 1'h0; // @[decode.scala:428:17] wire uop_iw_issued_partial_agen = 1'h0; // @[decode.scala:428:17] wire uop_iw_issued_partial_dgen = 1'h0; // @[decode.scala:428:17] wire uop_iw_p1_bypass_hint = 1'h0; // @[decode.scala:428:17] wire uop_iw_p2_bypass_hint = 1'h0; // @[decode.scala:428:17] wire uop_iw_p3_bypass_hint = 1'h0; // @[decode.scala:428:17] wire uop_fp_ctrl_vec = 1'h0; // @[decode.scala:428:17] wire uop_prs1_busy = 1'h0; // @[decode.scala:428:17] wire uop_prs2_busy = 1'h0; // @[decode.scala:428:17] wire uop_prs3_busy = 1'h0; // @[decode.scala:428:17] wire uop_ppred_busy = 1'h0; // @[decode.scala:428:17] wire uop_xcpt_ma_if = 1'h0; // @[decode.scala:428:17] wire cs_fp_vec = 1'h0; // @[decode.scala:447:16] wire _id_illegal_insn_T_7 = 1'h0; // @[decode.scala:464:19] wire _id_illegal_insn_T_8 = 1'h0; // @[decode.scala:464:16] wire [31:0] uop_inst = io_enq_uop_inst_0; // @[decode.scala:422:7, :428:17] wire [31:0] uop_debug_inst = io_enq_uop_debug_inst_0; // @[decode.scala:422:7, :428:17] wire uop_is_rvc = io_enq_uop_is_rvc_0; // @[decode.scala:422:7, :428:17] wire [39:0] uop_debug_pc = io_enq_uop_debug_pc_0; // @[decode.scala:422:7, :428:17] wire uop_is_sfb = io_enq_uop_is_sfb_0; // @[decode.scala:422:7, :428:17] wire [4:0] uop_ftq_idx = io_enq_uop_ftq_idx_0; // @[decode.scala:422:7, :428:17] wire uop_edge_inst = io_enq_uop_edge_inst_0; // @[decode.scala:422:7, :428:17] wire [5:0] uop_pc_lob = io_enq_uop_pc_lob_0; // @[decode.scala:422:7, :428:17] wire uop_taken = io_enq_uop_taken_0; // @[decode.scala:422:7, :428:17] wire uop_xcpt_pf_if = io_enq_uop_xcpt_pf_if_0; // @[decode.scala:422:7, :428:17] wire uop_xcpt_ae_if = io_enq_uop_xcpt_ae_if_0; // @[decode.scala:422:7, :428:17] wire uop_bp_debug_if = io_enq_uop_bp_debug_if_0; // @[decode.scala:422:7, :428:17] wire uop_bp_xcpt_if = io_enq_uop_bp_xcpt_if_0; // @[decode.scala:422:7, :428:17] wire [2:0] uop_debug_fsrc = io_enq_uop_debug_fsrc_0; // @[decode.scala:422:7, :428:17] wire uop_iq_type_0; // @[decode.scala:428:17] wire uop_iq_type_1; // @[decode.scala:428:17] wire uop_iq_type_2; // @[decode.scala:428:17] wire uop_iq_type_3; // @[decode.scala:428:17] wire uop_fu_code_0; // @[decode.scala:428:17] wire uop_fu_code_1; // @[decode.scala:428:17] wire uop_fu_code_2; // @[decode.scala:428:17] wire uop_fu_code_3; // @[decode.scala:428:17] wire uop_fu_code_4; // @[decode.scala:428:17] wire uop_fu_code_5; // @[decode.scala:428:17] wire uop_fu_code_6; // @[decode.scala:428:17] wire uop_fu_code_7; // @[decode.scala:428:17] wire uop_fu_code_8; // @[decode.scala:428:17] wire uop_fu_code_9; // @[decode.scala:428:17] wire [3:0] uop_br_type; // @[decode.scala:428:17] wire uop_is_fence; // @[decode.scala:428:17] wire uop_is_fencei; // @[decode.scala:428:17] wire uop_is_sfence; // @[decode.scala:428:17] wire uop_is_amo; // @[decode.scala:428:17] wire uop_is_eret; // @[decode.scala:428:17] wire uop_is_sys_pc2epc; // @[decode.scala:428:17] wire uop_is_rocc; // @[decode.scala:428:17] wire uop_is_mov; // @[decode.scala:428:17] wire uop_imm_rename; // @[decode.scala:428:17] wire [2:0] uop_imm_sel; // @[decode.scala:428:17] wire [4:0] uop_pimm; // @[decode.scala:428:17] wire [19:0] uop_imm_packed; // @[decode.scala:428:17] wire [1:0] uop_op1_sel; // @[decode.scala:428:17] wire [2:0] uop_op2_sel; // @[decode.scala:428:17] wire uop_fp_ctrl_ldst; // @[decode.scala:428:17] wire uop_fp_ctrl_wen; // @[decode.scala:428:17] wire uop_fp_ctrl_ren1; // @[decode.scala:428:17] wire uop_fp_ctrl_ren2; // @[decode.scala:428:17] wire uop_fp_ctrl_ren3; // @[decode.scala:428:17] wire uop_fp_ctrl_swap12; // @[decode.scala:428:17] wire uop_fp_ctrl_swap23; // @[decode.scala:428:17] wire [1:0] uop_fp_ctrl_typeTagIn; // @[decode.scala:428:17] wire [1:0] uop_fp_ctrl_typeTagOut; // @[decode.scala:428:17] wire uop_fp_ctrl_fromint; // @[decode.scala:428:17] wire uop_fp_ctrl_toint; // @[decode.scala:428:17] wire uop_fp_ctrl_fastpipe; // @[decode.scala:428:17] wire uop_fp_ctrl_fma; // @[decode.scala:428:17] wire uop_fp_ctrl_div; // @[decode.scala:428:17] wire uop_fp_ctrl_sqrt; // @[decode.scala:428:17] wire uop_fp_ctrl_wflags; // @[decode.scala:428:17] wire uop_exception; // @[decode.scala:428:17] wire [63:0] uop_exc_cause; // @[decode.scala:428:17] wire [4:0] uop_mem_cmd; // @[decode.scala:428:17] wire [1:0] uop_mem_size; // @[decode.scala:428:17] wire uop_mem_signed; // @[decode.scala:428:17] wire uop_uses_ldq; // @[decode.scala:428:17] wire uop_uses_stq; // @[decode.scala:428:17] wire uop_is_unique; // @[decode.scala:428:17] wire uop_flush_on_commit; // @[decode.scala:428:17] wire [2:0] uop_csr_cmd; // @[decode.scala:428:17] wire uop_ldst_is_rs1; // @[decode.scala:428:17] wire [5:0] uop_ldst; // @[decode.scala:428:17] wire [5:0] uop_lrs1; // @[decode.scala:428:17] wire [5:0] uop_lrs2; // @[decode.scala:428:17] wire [5:0] uop_lrs3; // @[decode.scala:428:17] wire [1:0] uop_dst_rtype; // @[decode.scala:428:17] wire [1:0] uop_lrs1_rtype; // @[decode.scala:428:17] wire [1:0] uop_lrs2_rtype; // @[decode.scala:428:17] wire uop_frs3_en; // @[decode.scala:428:17] wire uop_fcn_dw; // @[decode.scala:428:17] wire [4:0] uop_fcn_op; // @[decode.scala:428:17] wire uop_fp_val; // @[decode.scala:428:17] wire [2:0] uop_fp_rm; // @[decode.scala:428:17] wire [1:0] uop_fp_typ; // @[decode.scala:428:17] wire io_deq_uop_iq_type_0_0; // @[decode.scala:422:7] wire io_deq_uop_iq_type_1_0; // @[decode.scala:422:7] wire io_deq_uop_iq_type_2_0; // @[decode.scala:422:7] wire io_deq_uop_iq_type_3_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_0_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_1_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_2_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_3_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_4_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_5_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_6_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_7_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_8_0; // @[decode.scala:422:7] wire io_deq_uop_fu_code_9_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ldst_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_wen_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ren1_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ren2_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_ren3_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_swap12_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_swap23_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_fp_ctrl_typeTagIn_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_fp_ctrl_typeTagOut_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_fromint_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_toint_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_fastpipe_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_fma_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_div_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_sqrt_0; // @[decode.scala:422:7] wire io_deq_uop_fp_ctrl_wflags_0; // @[decode.scala:422:7] wire [31:0] io_deq_uop_inst_0; // @[decode.scala:422:7] wire [31:0] io_deq_uop_debug_inst_0; // @[decode.scala:422:7] wire io_deq_uop_is_rvc_0; // @[decode.scala:422:7] wire [39:0] io_deq_uop_debug_pc_0; // @[decode.scala:422:7] wire [3:0] io_deq_uop_br_type_0; // @[decode.scala:422:7] wire io_deq_uop_is_sfb_0; // @[decode.scala:422:7] wire io_deq_uop_is_fence_0; // @[decode.scala:422:7] wire io_deq_uop_is_fencei_0; // @[decode.scala:422:7] wire io_deq_uop_is_sfence_0; // @[decode.scala:422:7] wire io_deq_uop_is_amo_0; // @[decode.scala:422:7] wire io_deq_uop_is_eret_0; // @[decode.scala:422:7] wire io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:422:7] wire io_deq_uop_is_rocc_0; // @[decode.scala:422:7] wire io_deq_uop_is_mov_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_ftq_idx_0; // @[decode.scala:422:7] wire io_deq_uop_edge_inst_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_pc_lob_0; // @[decode.scala:422:7] wire io_deq_uop_taken_0; // @[decode.scala:422:7] wire io_deq_uop_imm_rename_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_imm_sel_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_pimm_0; // @[decode.scala:422:7] wire [19:0] io_deq_uop_imm_packed_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_op1_sel_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_op2_sel_0; // @[decode.scala:422:7] wire io_deq_uop_exception_0; // @[decode.scala:422:7] wire [63:0] io_deq_uop_exc_cause_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_mem_cmd_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_mem_size_0; // @[decode.scala:422:7] wire io_deq_uop_mem_signed_0; // @[decode.scala:422:7] wire io_deq_uop_uses_ldq_0; // @[decode.scala:422:7] wire io_deq_uop_uses_stq_0; // @[decode.scala:422:7] wire io_deq_uop_is_unique_0; // @[decode.scala:422:7] wire io_deq_uop_flush_on_commit_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_csr_cmd_0; // @[decode.scala:422:7] wire io_deq_uop_ldst_is_rs1_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_ldst_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_lrs1_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_lrs2_0; // @[decode.scala:422:7] wire [5:0] io_deq_uop_lrs3_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_dst_rtype_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_lrs1_rtype_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_lrs2_rtype_0; // @[decode.scala:422:7] wire io_deq_uop_frs3_en_0; // @[decode.scala:422:7] wire io_deq_uop_fcn_dw_0; // @[decode.scala:422:7] wire [4:0] io_deq_uop_fcn_op_0; // @[decode.scala:422:7] wire io_deq_uop_fp_val_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_fp_rm_0; // @[decode.scala:422:7] wire [1:0] io_deq_uop_fp_typ_0; // @[decode.scala:422:7] wire io_deq_uop_xcpt_pf_if_0; // @[decode.scala:422:7] wire io_deq_uop_xcpt_ae_if_0; // @[decode.scala:422:7] wire io_deq_uop_bp_debug_if_0; // @[decode.scala:422:7] wire io_deq_uop_bp_xcpt_if_0; // @[decode.scala:422:7] wire [2:0] io_deq_uop_debug_fsrc_0; // @[decode.scala:422:7] wire [31:0] io_csr_decode_inst_0; // @[decode.scala:422:7] assign io_deq_uop_inst_0 = uop_inst; // @[decode.scala:422:7, :428:17] assign io_csr_decode_inst_0 = uop_inst; // @[decode.scala:422:7, :428:17] wire [31:0] cs_decoder_decoded_plaInput = uop_inst; // @[pla.scala:77:22] wire [31:0] _uop_is_sys_pc2epc_T = uop_inst; // @[decode.scala:428:17, :529:29] wire [31:0] _uop_is_sys_pc2epc_T_2 = uop_inst; // @[decode.scala:428:17, :529:48] wire [31:0] _uop_is_eret_T = uop_inst; // @[decode.scala:428:17, :530:26] wire [31:0] _uop_is_eret_T_2 = uop_inst; // @[decode.scala:428:17, :530:44] wire [31:0] _uop_is_eret_T_5 = uop_inst; // @[decode.scala:428:17, :530:63] wire [31:0] _uop_is_eret_T_8 = uop_inst; // @[decode.scala:428:17, :530:80] wire [31:0] _uop_is_eret_T_11 = uop_inst; // @[decode.scala:428:17, :530:97] assign io_deq_uop_debug_inst_0 = uop_debug_inst; // @[decode.scala:422:7, :428:17] assign io_deq_uop_is_rvc_0 = uop_is_rvc; // @[decode.scala:422:7, :428:17] assign io_deq_uop_debug_pc_0 = uop_debug_pc; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_0_T_2; // @[decode.scala:489:98] assign io_deq_uop_iq_type_0_0 = uop_iq_type_0; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_1_T_6; // @[decode.scala:487:98] assign io_deq_uop_iq_type_1_0 = uop_iq_type_1; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_2_T; // @[decode.scala:488:84] assign io_deq_uop_iq_type_2_0 = uop_iq_type_2; // @[decode.scala:422:7, :428:17] wire _uop_iq_type_3_T_4; // @[decode.scala:490:98] assign io_deq_uop_iq_type_3_0 = uop_iq_type_3; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_0_0 = uop_fu_code_0; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_1_0 = uop_fu_code_1; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_2_0 = uop_fu_code_2; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_3_0 = uop_fu_code_3; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_4_0 = uop_fu_code_4; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_5_0 = uop_fu_code_5; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_6_0 = uop_fu_code_6; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_7_0 = uop_fu_code_7; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_8_0 = uop_fu_code_8; // @[decode.scala:422:7, :428:17] assign io_deq_uop_fu_code_9_0 = uop_fu_code_9; // @[decode.scala:422:7, :428:17] wire [3:0] _uop_br_type_T_30; // @[decode.scala:604:62] assign io_deq_uop_br_type_0 = uop_br_type; // @[decode.scala:422:7, :428:17] assign io_deq_uop_is_sfb_0 = uop_is_sfb; // @[decode.scala:422:7, :428:17] wire _uop_is_fence_T_1; // @[decode.scala:526:26] assign io_deq_uop_is_fence_0 = uop_is_fence; // @[decode.scala:422:7, :428:17] wire _uop_is_fencei_T_1; // @[decode.scala:527:26] assign io_deq_uop_is_fencei_0 = uop_is_fencei; // @[decode.scala:422:7, :428:17] wire _uop_is_sfence_T_1; // @[decode.scala:528:26] assign io_deq_uop_is_sfence_0 = uop_is_sfence; // @[decode.scala:422:7, :428:17] wire cs_is_amo; // @[decode.scala:447:16] assign io_deq_uop_is_amo_0 = uop_is_amo; // @[decode.scala:422:7, :428:17] wire _uop_is_eret_T_13; // @[decode.scala:530:89] assign io_deq_uop_is_eret_0 = uop_is_eret; // @[decode.scala:422:7, :428:17] wire _uop_is_sys_pc2epc_T_4; // @[decode.scala:529:40] assign io_deq_uop_is_sys_pc2epc_0 = uop_is_sys_pc2epc; // @[decode.scala:422:7, :428:17] wire _uop_is_rocc_T_18; // @[decode.scala:532:81] assign io_deq_uop_is_rocc_0 = uop_is_rocc; // @[decode.scala:422:7, :428:17] wire _id_illegal_insn_T_4 = uop_is_rocc; // @[decode.scala:428:17, :463:18] wire _uop_is_mov_T_3; // @[decode.scala:485:34] assign io_deq_uop_is_mov_0 = uop_is_mov; // @[decode.scala:422:7, :428:17] assign io_deq_uop_ftq_idx_0 = uop_ftq_idx; // @[decode.scala:422:7, :428:17] assign io_deq_uop_edge_inst_0 = uop_edge_inst; // @[decode.scala:422:7, :428:17] assign io_deq_uop_pc_lob_0 = uop_pc_lob; // @[decode.scala:422:7, :428:17] assign io_deq_uop_taken_0 = uop_taken; // @[decode.scala:422:7, :428:17] assign io_deq_uop_imm_rename_0 = uop_imm_rename; // @[decode.scala:422:7, :428:17] assign io_deq_uop_imm_sel_0 = uop_imm_sel; // @[decode.scala:422:7, :428:17] assign io_deq_uop_pimm_0 = uop_pimm; // @[decode.scala:422:7, :428:17] wire [19:0] imm_packed; // @[decode.scala:541:23] assign io_deq_uop_imm_packed_0 = uop_imm_packed; // @[decode.scala:422:7, :428:17] assign io_deq_uop_op1_sel_0 = uop_op1_sel; // @[decode.scala:422:7, :428:17] assign io_deq_uop_op2_sel_0 = uop_op2_sel; // @[decode.scala:422:7, :428:17] wire cs_fp_ldst; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ldst_0 = uop_fp_ctrl_ldst; // @[decode.scala:422:7, :428:17] wire cs_fp_wen; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_wen_0 = uop_fp_ctrl_wen; // @[decode.scala:422:7, :428:17] wire cs_fp_ren1; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ren1_0 = uop_fp_ctrl_ren1; // @[decode.scala:422:7, :428:17] wire cs_fp_ren2; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ren2_0 = uop_fp_ctrl_ren2; // @[decode.scala:422:7, :428:17] wire cs_fp_ren3; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_ren3_0 = uop_fp_ctrl_ren3; // @[decode.scala:422:7, :428:17] wire cs_fp_swap12; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_swap12_0 = uop_fp_ctrl_swap12; // @[decode.scala:422:7, :428:17] wire cs_fp_swap23; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_swap23_0 = uop_fp_ctrl_swap23; // @[decode.scala:422:7, :428:17] wire [1:0] cs_fp_typeTagIn; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_typeTagIn_0 = uop_fp_ctrl_typeTagIn; // @[decode.scala:422:7, :428:17] wire [1:0] cs_fp_typeTagOut; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_typeTagOut_0 = uop_fp_ctrl_typeTagOut; // @[decode.scala:422:7, :428:17] wire cs_fp_fromint; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_fromint_0 = uop_fp_ctrl_fromint; // @[decode.scala:422:7, :428:17] wire cs_fp_toint; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_toint_0 = uop_fp_ctrl_toint; // @[decode.scala:422:7, :428:17] wire cs_fp_fastpipe; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_fastpipe_0 = uop_fp_ctrl_fastpipe; // @[decode.scala:422:7, :428:17] wire cs_fp_fma; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_fma_0 = uop_fp_ctrl_fma; // @[decode.scala:422:7, :428:17] wire cs_fp_div; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_div_0 = uop_fp_ctrl_div; // @[decode.scala:422:7, :428:17] wire cs_fp_sqrt; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_sqrt_0 = uop_fp_ctrl_sqrt; // @[decode.scala:422:7, :428:17] wire cs_fp_wflags; // @[decode.scala:447:16] assign io_deq_uop_fp_ctrl_wflags_0 = uop_fp_ctrl_wflags; // @[decode.scala:422:7, :428:17] wire xcpt_valid; // @[decode.scala:470:26] assign io_deq_uop_exception_0 = uop_exception; // @[decode.scala:422:7, :428:17] wire [63:0] xcpt_cause; // @[Mux.scala:50:70] assign io_deq_uop_exc_cause_0 = uop_exc_cause; // @[decode.scala:422:7, :428:17] wire [4:0] cs_mem_cmd; // @[decode.scala:447:16] assign io_deq_uop_mem_cmd_0 = uop_mem_cmd; // @[decode.scala:422:7, :428:17] wire [1:0] _uop_mem_size_T_7; // @[decode.scala:521:24] assign io_deq_uop_mem_size_0 = uop_mem_size; // @[decode.scala:422:7, :428:17] wire _uop_mem_signed_T_1; // @[decode.scala:522:21] assign io_deq_uop_mem_signed_0 = uop_mem_signed; // @[decode.scala:422:7, :428:17] wire cs_uses_ldq; // @[decode.scala:447:16] assign io_deq_uop_uses_ldq_0 = uop_uses_ldq; // @[decode.scala:422:7, :428:17] wire cs_uses_stq; // @[decode.scala:447:16] assign io_deq_uop_uses_stq_0 = uop_uses_stq; // @[decode.scala:422:7, :428:17] wire cs_inst_unique; // @[decode.scala:447:16] assign io_deq_uop_is_unique_0 = uop_is_unique; // @[decode.scala:422:7, :428:17] wire _uop_flush_on_commit_T_3; // @[decode.scala:533:45] assign io_deq_uop_flush_on_commit_0 = uop_flush_on_commit; // @[decode.scala:422:7, :428:17] assign io_deq_uop_csr_cmd_0 = uop_csr_cmd; // @[decode.scala:422:7, :428:17] assign io_deq_uop_ldst_is_rs1_0 = uop_ldst_is_rs1; // @[decode.scala:422:7, :428:17] assign io_deq_uop_ldst_0 = uop_ldst; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs1_0 = uop_lrs1; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs2_0 = uop_lrs2; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs3_0 = uop_lrs3; // @[decode.scala:422:7, :428:17] wire [1:0] cs_dst_type; // @[decode.scala:447:16] assign io_deq_uop_dst_rtype_0 = uop_dst_rtype; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs1_rtype_0 = uop_lrs1_rtype; // @[decode.scala:422:7, :428:17] assign io_deq_uop_lrs2_rtype_0 = uop_lrs2_rtype; // @[decode.scala:422:7, :428:17] wire cs_frs3_en; // @[decode.scala:447:16] assign io_deq_uop_frs3_en_0 = uop_frs3_en; // @[decode.scala:422:7, :428:17] wire cs_fcn_dw; // @[decode.scala:447:16] assign io_deq_uop_fcn_dw_0 = uop_fcn_dw; // @[decode.scala:422:7, :428:17] wire [4:0] cs_fcn_op; // @[decode.scala:447:16] assign io_deq_uop_fcn_op_0 = uop_fcn_op; // @[decode.scala:422:7, :428:17] wire cs_fp_val; // @[decode.scala:447:16] assign io_deq_uop_fp_val_0 = uop_fp_val; // @[decode.scala:422:7, :428:17] wire [2:0] _uop_fp_rm_T_3; // @[decode.scala:556:21] assign io_deq_uop_fp_rm_0 = uop_fp_rm; // @[decode.scala:422:7, :428:17] wire [1:0] _uop_fp_typ_T; // @[decode.scala:557:22] assign io_deq_uop_fp_typ_0 = uop_fp_typ; // @[decode.scala:422:7, :428:17] assign io_deq_uop_xcpt_pf_if_0 = uop_xcpt_pf_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_xcpt_ae_if_0 = uop_xcpt_ae_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_bp_debug_if_0 = uop_bp_debug_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_bp_xcpt_if_0 = uop_bp_xcpt_if; // @[decode.scala:422:7, :428:17] assign io_deq_uop_debug_fsrc_0 = uop_debug_fsrc; // @[decode.scala:422:7, :428:17] wire [4:0] LDST = uop_inst[11:7]; // @[decode.scala:428:17, :441:18] wire [4:0] _di24_20_T_3 = uop_inst[11:7]; // @[decode.scala:428:17, :441:18, :540:69] wire [4:0] LRS1 = uop_inst[19:15]; // @[decode.scala:428:17, :442:18] wire [4:0] LRS2 = uop_inst[24:20]; // @[decode.scala:428:17, :443:18] wire [4:0] _di24_20_T_4 = uop_inst[24:20]; // @[decode.scala:428:17, :443:18, :540:81] wire [4:0] LRS3 = uop_inst[31:27]; // @[decode.scala:428:17, :444:18] wire cs_decoder_0; // @[Decode.scala:50:77] wire cs_decoder_1; // @[Decode.scala:50:77] assign uop_fp_val = cs_fp_val; // @[decode.scala:428:17, :447:16] wire [9:0] cs_decoder_2; // @[Decode.scala:50:77] wire [1:0] cs_decoder_3; // @[Decode.scala:50:77] assign uop_dst_rtype = cs_dst_type; // @[decode.scala:428:17, :447:16] wire [1:0] cs_decoder_4; // @[Decode.scala:50:77] wire [1:0] cs_decoder_5; // @[Decode.scala:50:77] wire cs_decoder_6; // @[Decode.scala:50:77] assign uop_frs3_en = cs_frs3_en; // @[decode.scala:428:17, :447:16] wire [2:0] cs_decoder_7; // @[Decode.scala:50:77] wire cs_decoder_8; // @[Decode.scala:50:77] assign uop_uses_ldq = cs_uses_ldq; // @[decode.scala:428:17, :447:16] wire cs_decoder_9; // @[Decode.scala:50:77] assign uop_uses_stq = cs_uses_stq; // @[decode.scala:428:17, :447:16] wire cs_decoder_10; // @[Decode.scala:50:77] assign uop_is_amo = cs_is_amo; // @[decode.scala:428:17, :447:16] wire [4:0] cs_decoder_11; // @[Decode.scala:50:77] assign uop_mem_cmd = cs_mem_cmd; // @[decode.scala:428:17, :447:16] wire cs_decoder_12; // @[Decode.scala:50:77] assign uop_is_unique = cs_inst_unique; // @[decode.scala:428:17, :447:16] wire cs_decoder_13; // @[Decode.scala:50:77] wire [2:0] cs_decoder_14; // @[Decode.scala:50:77] wire cs_decoder_15; // @[Decode.scala:50:77] assign uop_fcn_dw = cs_fcn_dw; // @[decode.scala:428:17, :447:16] wire [4:0] cs_decoder_16; // @[Decode.scala:50:77] assign uop_fcn_op = cs_fcn_op; // @[decode.scala:428:17, :447:16] wire cs_decoder_17; // @[Decode.scala:50:77] assign uop_fp_ctrl_ldst = cs_fp_ldst; // @[decode.scala:428:17, :447:16] wire cs_decoder_18; // @[Decode.scala:50:77] assign uop_fp_ctrl_wen = cs_fp_wen; // @[decode.scala:428:17, :447:16] wire cs_decoder_19; // @[Decode.scala:50:77] assign uop_fp_ctrl_ren1 = cs_fp_ren1; // @[decode.scala:428:17, :447:16] wire cs_decoder_20; // @[Decode.scala:50:77] assign uop_fp_ctrl_ren2 = cs_fp_ren2; // @[decode.scala:428:17, :447:16] wire cs_decoder_21; // @[Decode.scala:50:77] assign uop_fp_ctrl_ren3 = cs_fp_ren3; // @[decode.scala:428:17, :447:16] wire cs_decoder_22; // @[Decode.scala:50:77] assign uop_fp_ctrl_swap12 = cs_fp_swap12; // @[decode.scala:428:17, :447:16] wire cs_decoder_23; // @[Decode.scala:50:77] assign uop_fp_ctrl_swap23 = cs_fp_swap23; // @[decode.scala:428:17, :447:16] assign uop_fp_ctrl_typeTagIn = cs_fp_typeTagIn; // @[decode.scala:428:17, :447:16] assign uop_fp_ctrl_typeTagOut = cs_fp_typeTagOut; // @[decode.scala:428:17, :447:16] wire cs_decoder_26; // @[Decode.scala:50:77] assign uop_fp_ctrl_fromint = cs_fp_fromint; // @[decode.scala:428:17, :447:16] wire cs_decoder_27; // @[Decode.scala:50:77] assign uop_fp_ctrl_toint = cs_fp_toint; // @[decode.scala:428:17, :447:16] wire cs_decoder_28; // @[Decode.scala:50:77] assign uop_fp_ctrl_fastpipe = cs_fp_fastpipe; // @[decode.scala:428:17, :447:16] wire cs_decoder_29; // @[Decode.scala:50:77] assign uop_fp_ctrl_fma = cs_fp_fma; // @[decode.scala:428:17, :447:16] wire cs_decoder_30; // @[Decode.scala:50:77] assign uop_fp_ctrl_div = cs_fp_div; // @[decode.scala:428:17, :447:16] wire cs_decoder_31; // @[Decode.scala:50:77] assign uop_fp_ctrl_sqrt = cs_fp_sqrt; // @[decode.scala:428:17, :447:16] wire cs_decoder_32; // @[Decode.scala:50:77] assign uop_fp_ctrl_wflags = cs_fp_wflags; // @[decode.scala:428:17, :447:16] wire cs_legal; // @[decode.scala:447:16] wire [9:0] cs_fu_code; // @[decode.scala:447:16] wire [1:0] cs_rs1_type; // @[decode.scala:447:16] wire [1:0] cs_rs2_type; // @[decode.scala:447:16] wire [2:0] cs_imm_sel; // @[decode.scala:447:16] wire cs_flush_on_commit; // @[decode.scala:447:16] wire [2:0] cs_csr_cmd; // @[decode.scala:447:16] wire [31:0] cs_decoder_decoded_invInputs = ~cs_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [56:0] cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [56:0] cs_decoder_decoded; // @[pla.scala:81:23] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo = {cs_decoder_decoded_andMatrixOutputs_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi = {cs_decoder_decoded_andMatrixOutputs_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T = {cs_decoder_decoded_andMatrixOutputs_hi, cs_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_81_2 = &_cs_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_1 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_1 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_1 = {cs_decoder_decoded_andMatrixOutputs_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_85_2 = &_cs_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_2 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_2 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_2 = {cs_decoder_decoded_andMatrixOutputs_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_10_2 = &_cs_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_3 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_3 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_3 = {cs_decoder_decoded_andMatrixOutputs_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_26_2 = &_cs_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_4 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_4 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_4 = {cs_decoder_decoded_andMatrixOutputs_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_100_2 = &_cs_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_5 = {cs_decoder_decoded_andMatrixOutputs_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_88_2 = &_cs_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_6 = {cs_decoder_decoded_andMatrixOutputs_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_62_2 = &_cs_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_7 = {cs_decoder_decoded_andMatrixOutputs_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_77_2 = &_cs_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_8 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:90:45, :98:53] wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_8 = {cs_decoder_decoded_andMatrixOutputs_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_29_2 = &_cs_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_9 = {cs_decoder_decoded_andMatrixOutputs_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_110_2 = &_cs_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_8 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_10 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_10 = {cs_decoder_decoded_andMatrixOutputs_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_61_2 = &_cs_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_11 = {cs_decoder_decoded_andMatrixOutputs_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_166_2 = &_cs_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_12 = {cs_decoder_decoded_andMatrixOutputs_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_8_2 = &_cs_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_13 = {cs_decoder_decoded_andMatrixOutputs_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_80_2 = &_cs_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_14 = {cs_decoder_decoded_andMatrixOutputs_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_14_2 = &_cs_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_15 = {cs_decoder_decoded_andMatrixOutputs_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_56_2 = &_cs_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_11 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_11 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_8 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_16 = {cs_decoder_decoded_andMatrixOutputs_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_43_2 = &_cs_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [4:0] _cs_decoder_decoded_andMatrixOutputs_T_17 = {cs_decoder_decoded_andMatrixOutputs_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_157_2 = &_cs_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_17 = cs_decoder_decoded_andMatrixOutputs_157_2; // @[pla.scala:98:70, :114:36] wire _cs_decoder_decoded_orMatrixOutputs_T_63 = cs_decoder_decoded_andMatrixOutputs_157_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_18 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_18 = {cs_decoder_decoded_andMatrixOutputs_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_123_2 = &_cs_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_19 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_19 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_19 = {cs_decoder_decoded_andMatrixOutputs_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_102_2 = &_cs_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_20 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_20 = {cs_decoder_decoded_andMatrixOutputs_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_140_2 = &_cs_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_21 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_21 = {cs_decoder_decoded_andMatrixOutputs_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_21_2 = &_cs_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_22 = {cs_decoder_decoded_andMatrixOutputs_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_145_2 = &_cs_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_23 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_23 = {cs_decoder_decoded_andMatrixOutputs_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_161_2 = &_cs_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_16 = cs_decoder_decoded_andMatrixOutputs_161_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_24 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_24 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_24 = {cs_decoder_decoded_andMatrixOutputs_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_79_2 = &_cs_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_25 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_25 = {cs_decoder_decoded_andMatrixOutputs_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_33_2 = &_cs_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_26 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_26 = {cs_decoder_decoded_andMatrixOutputs_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_112_2 = &_cs_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_27 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_27 = {cs_decoder_decoded_andMatrixOutputs_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_168_2 = &_cs_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_28 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_28 = {cs_decoder_decoded_andMatrixOutputs_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_138_2 = &_cs_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_29 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_29 = {cs_decoder_decoded_andMatrixOutputs_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_47_2 = &_cs_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_30 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_30 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_30 = {cs_decoder_decoded_andMatrixOutputs_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_71_2 = &_cs_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_31 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_31 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_31 = {cs_decoder_decoded_andMatrixOutputs_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_105_2 = &_cs_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_32 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_32 = {cs_decoder_decoded_andMatrixOutputs_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_52_2 = &_cs_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_33 = {cs_decoder_decoded_andMatrixOutputs_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_86_2 = &_cs_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_34 = {cs_decoder_decoded_andMatrixOutputs_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_0_2 = &_cs_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_35 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_35 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_35 = {cs_decoder_decoded_andMatrixOutputs_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_76_2 = &_cs_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_36 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_36 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_36 = {cs_decoder_decoded_andMatrixOutputs_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_160_2 = &_cs_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_34 = cs_decoder_decoded_andMatrixOutputs_160_2; // @[pla.scala:98:70, :114:36] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_37 = {cs_decoder_decoded_andMatrixOutputs_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_120_2 = &_cs_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_38 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_38 = {cs_decoder_decoded_andMatrixOutputs_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_45_2 = &_cs_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_39 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_39 = {cs_decoder_decoded_andMatrixOutputs_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_162_2 = &_cs_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_40 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_40 = {cs_decoder_decoded_andMatrixOutputs_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_73_2 = &_cs_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_41 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_41 = {cs_decoder_decoded_andMatrixOutputs_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_18_2 = &_cs_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_42 = {cs_decoder_decoded_andMatrixOutputs_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_111_2 = &_cs_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_43 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_43 = {cs_decoder_decoded_andMatrixOutputs_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_153_2 = &_cs_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_44 = {cs_decoder_decoded_andMatrixOutputs_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_107_2 = &_cs_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_45 = {cs_decoder_decoded_andMatrixOutputs_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_17_2 = &_cs_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_49 = cs_decoder_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_46 = {cs_decoder_decoded_andMatrixOutputs_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_167_2 = &_cs_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_47 = {cs_decoder_decoded_andMatrixOutputs_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_113_2 = &_cs_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_48 = {cs_decoder_decoded_andMatrixOutputs_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_42_2 = &_cs_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_49 = {cs_decoder_decoded_andMatrixOutputs_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_131_2 = &_cs_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_50 = {cs_decoder_decoded_andMatrixOutputs_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_1_2 = &_cs_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_51 = {cs_decoder_decoded_andMatrixOutputs_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_136_2 = &_cs_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_52 = {cs_decoder_decoded_andMatrixOutputs_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_39_2 = &_cs_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_53 = {cs_decoder_decoded_andMatrixOutputs_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_108_2 = &_cs_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_54 = {cs_decoder_decoded_andMatrixOutputs_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_165_2 = &_cs_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_55 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_55 = {cs_decoder_decoded_andMatrixOutputs_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_127_2 = &_cs_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_56 = {cs_decoder_decoded_andMatrixOutputs_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_135_2 = &_cs_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_57 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_57 = {cs_decoder_decoded_andMatrixOutputs_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_114_2 = &_cs_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_58 = {cs_decoder_decoded_andMatrixOutputs_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_155_2 = &_cs_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_59 = {cs_decoder_decoded_andMatrixOutputs_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_6_2 = &_cs_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_60 = {cs_decoder_decoded_andMatrixOutputs_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_75_2 = &_cs_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_61 = {cs_decoder_decoded_andMatrixOutputs_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_72_2 = &_cs_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_62 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_62 = {cs_decoder_decoded_andMatrixOutputs_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_96_2 = &_cs_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_63 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_63 = {cs_decoder_decoded_andMatrixOutputs_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_149_2 = &_cs_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_64 = {cs_decoder_decoded_andMatrixOutputs_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_144_2 = &_cs_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_65 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_65 = {cs_decoder_decoded_andMatrixOutputs_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_3_2 = &_cs_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_66 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_66 = {cs_decoder_decoded_andMatrixOutputs_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_13_2 = &_cs_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_14 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_11 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_67 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_67 = {cs_decoder_decoded_andMatrixOutputs_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_141_2 = &_cs_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_68 = {cs_decoder_decoded_andMatrixOutputs_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_93_2 = &_cs_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_69 = {cs_decoder_decoded_andMatrixOutputs_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_60_2 = &_cs_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_70 = {cs_decoder_decoded_andMatrixOutputs_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_69_2 = &_cs_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_71 = {cs_decoder_decoded_andMatrixOutputs_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_124_2 = &_cs_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_72 = {cs_decoder_decoded_andMatrixOutputs_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_30_2 = &_cs_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_73 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_73 = {cs_decoder_decoded_andMatrixOutputs_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_35_2 = &_cs_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_74 = {cs_decoder_decoded_andMatrixOutputs_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_9_2 = &_cs_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_84 = cs_decoder_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_75 = {cs_decoder_decoded_andMatrixOutputs_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_89_2 = &_cs_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_76 = {cs_decoder_decoded_andMatrixOutputs_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_57_2 = &_cs_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_13 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_10 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_77 = {cs_decoder_decoded_andMatrixOutputs_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_164_2 = &_cs_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_78 = {cs_decoder_decoded_andMatrixOutputs_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_121_2 = &_cs_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_79 = {cs_decoder_decoded_andMatrixOutputs_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_25_2 = &_cs_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_80 = {cs_decoder_decoded_andMatrixOutputs_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_99_2 = &_cs_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_81 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_81 = {cs_decoder_decoded_andMatrixOutputs_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_51_2 = &_cs_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_82 = {cs_decoder_decoded_andMatrixOutputs_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_37_2 = &_cs_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_83 = {cs_decoder_decoded_andMatrixOutputs_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_143_2 = &_cs_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_84 = {cs_decoder_decoded_andMatrixOutputs_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_137_2 = &_cs_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_9 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_10 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_85 = {cs_decoder_decoded_andMatrixOutputs_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_118_2 = &_cs_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_86 = {cs_decoder_decoded_andMatrixOutputs_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_58_2 = &_cs_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_15 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_87 = {cs_decoder_decoded_andMatrixOutputs_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_146_2 = &_cs_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_88 = {cs_decoder_decoded_andMatrixOutputs_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_50_2 = &_cs_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53] wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_89 = {cs_decoder_decoded_andMatrixOutputs_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_129_2 = &_cs_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_8 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_90 = {cs_decoder_decoded_andMatrixOutputs_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_66_2 = &_cs_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_91 = {cs_decoder_decoded_andMatrixOutputs_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_134_2 = &_cs_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_8}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_92 = {cs_decoder_decoded_andMatrixOutputs_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_97_2 = &_cs_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_93 = {cs_decoder_decoded_andMatrixOutputs_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_65_2 = &_cs_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_50 = cs_decoder_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_94 = {cs_decoder_decoded_andMatrixOutputs_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_16_2 = &_cs_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_95 = {cs_decoder_decoded_andMatrixOutputs_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_95_2 = &_cs_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_96 = {cs_decoder_decoded_andMatrixOutputs_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_82_2 = &_cs_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_3 = cs_decoder_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_97 = {cs_decoder_decoded_andMatrixOutputs_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_54_2 = &_cs_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_9 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_10 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_27 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_28 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_29 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_30 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_98 = {cs_decoder_decoded_andMatrixOutputs_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_7_2 = &_cs_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_89 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_99 = {cs_decoder_decoded_andMatrixOutputs_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_115_2 = &_cs_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_100 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_100 = {cs_decoder_decoded_andMatrixOutputs_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_92_2 = &_cs_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_101 = {cs_decoder_decoded_andMatrixOutputs_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_40_2 = &_cs_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_102 = {cs_decoder_decoded_andMatrixOutputs_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_63_2 = &_cs_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_103 = {cs_decoder_decoded_andMatrixOutputs_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_133_2 = &_cs_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_104 = {cs_decoder_decoded_andMatrixOutputs_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_28_2 = &_cs_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_105 = {cs_decoder_decoded_andMatrixOutputs_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_68_2 = &_cs_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_106 = {cs_decoder_decoded_andMatrixOutputs_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_11_2 = &_cs_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_107 = {cs_decoder_decoded_andMatrixOutputs_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_74_2 = &_cs_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_108 = {cs_decoder_decoded_andMatrixOutputs_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_139_2 = &_cs_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_109 = {cs_decoder_decoded_andMatrixOutputs_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_156_2 = &_cs_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_110 = {cs_decoder_decoded_andMatrixOutputs_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_38_2 = &_cs_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_111 = {cs_decoder_decoded_andMatrixOutputs_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_116_2 = &_cs_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_112 = {cs_decoder_decoded_andMatrixOutputs_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_4_2 = &_cs_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_113 = {cs_decoder_decoded_andMatrixOutputs_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_163_2 = &_cs_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_9 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_25 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_26 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_114 = {cs_decoder_decoded_andMatrixOutputs_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_5_2 = &_cs_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_115 = {cs_decoder_decoded_andMatrixOutputs_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_22_2 = &_cs_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_116 = {cs_decoder_decoded_andMatrixOutputs_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_48_2 = &_cs_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_117 = {cs_decoder_decoded_andMatrixOutputs_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_125_2 = &_cs_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_118 = {cs_decoder_decoded_andMatrixOutputs_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_24_2 = &_cs_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_119 = {cs_decoder_decoded_andMatrixOutputs_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_44_2 = &_cs_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_120 = {cs_decoder_decoded_andMatrixOutputs_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_119_2 = &_cs_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_118 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_121 = {cs_decoder_decoded_andMatrixOutputs_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_154_2 = &_cs_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_119 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_122 = {cs_decoder_decoded_andMatrixOutputs_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_151_2 = &_cs_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_120 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_123 = {cs_decoder_decoded_andMatrixOutputs_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_104_2 = &_cs_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_121 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_124 = {cs_decoder_decoded_andMatrixOutputs_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_20_2 = &_cs_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_122 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_125 = {cs_decoder_decoded_andMatrixOutputs_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_49_2 = &_cs_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_123 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_126 = {cs_decoder_decoded_andMatrixOutputs_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_122_2 = &_cs_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_124 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_127 = {cs_decoder_decoded_andMatrixOutputs_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_12_2 = &_cs_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_125 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_128 = {cs_decoder_decoded_andMatrixOutputs_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_41_2 = &_cs_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_126 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_129 = {cs_decoder_decoded_andMatrixOutputs_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_152_2 = &_cs_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_127 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_130 = {cs_decoder_decoded_andMatrixOutputs_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_23_2 = &_cs_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_128 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_131 = {cs_decoder_decoded_andMatrixOutputs_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_98_2 = &_cs_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_129 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_132 = {cs_decoder_decoded_andMatrixOutputs_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_15_2 = &_cs_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_130 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_133 = {cs_decoder_decoded_andMatrixOutputs_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_36_2 = &_cs_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_131 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_134 = {cs_decoder_decoded_andMatrixOutputs_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_46_2 = &_cs_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_132 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_135 = {cs_decoder_decoded_andMatrixOutputs_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_55_2 = &_cs_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_133 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_136 = {cs_decoder_decoded_andMatrixOutputs_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_159_2 = &_cs_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_134 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_137 = {cs_decoder_decoded_andMatrixOutputs_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_117_2 = &_cs_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_2 = cs_decoder_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_135 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_138 = {cs_decoder_decoded_andMatrixOutputs_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_109_2 = &_cs_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_136 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_139 = {cs_decoder_decoded_andMatrixOutputs_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_128_2 = &_cs_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_137 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_140 = {cs_decoder_decoded_andMatrixOutputs_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_2_2 = &_cs_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_138 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_141 = {cs_decoder_decoded_andMatrixOutputs_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_83_2 = &_cs_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_139 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_142 = {cs_decoder_decoded_andMatrixOutputs_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_87_2 = &_cs_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_140 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_143, cs_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_143 = {cs_decoder_decoded_andMatrixOutputs_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_158_2 = &_cs_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_141 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_144, cs_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_144 = {cs_decoder_decoded_andMatrixOutputs_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_19_2 = &_cs_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_142 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_145, cs_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_145 = {cs_decoder_decoded_andMatrixOutputs_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_91_2 = &_cs_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_143 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_146, cs_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_146 = {cs_decoder_decoded_andMatrixOutputs_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_70_2 = &_cs_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_97}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_144 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_147, cs_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_147 = {cs_decoder_decoded_andMatrixOutputs_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_53_2 = &_cs_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_98}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_145 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_148, cs_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_148 = {cs_decoder_decoded_andMatrixOutputs_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_126_2 = &_cs_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_99}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_146 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_149, cs_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_149 = {cs_decoder_decoded_andMatrixOutputs_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_150_2 = &_cs_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_100}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_147 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_150, cs_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_150 = {cs_decoder_decoded_andMatrixOutputs_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_31_2 = &_cs_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = cs_decoder_decoded_plaInput[23]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_11 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_101}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_148 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_151, cs_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_151 = {cs_decoder_decoded_andMatrixOutputs_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_106_2 = &_cs_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_9}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_9}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_102}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_149 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53] wire [12:0] cs_decoder_decoded_andMatrixOutputs_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_152, cs_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [25:0] _cs_decoder_decoded_andMatrixOutputs_T_152 = {cs_decoder_decoded_andMatrixOutputs_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_78_2 = &_cs_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_10}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_103}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_150 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_153, cs_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_153 = {cs_decoder_decoded_andMatrixOutputs_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_64_2 = &_cs_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_11}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_104}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_151 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_108}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_154, cs_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_154 = {cs_decoder_decoded_andMatrixOutputs_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_103_2 = &_cs_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_17 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_18 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_19 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_20 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_152 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_155, cs_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_155 = {cs_decoder_decoded_andMatrixOutputs_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_147_2 = &_cs_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_105}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_153 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_156, cs_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_156 = {cs_decoder_decoded_andMatrixOutputs_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_142_2 = &_cs_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_106}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_154 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_110}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_157, cs_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_157 = {cs_decoder_decoded_andMatrixOutputs_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_130_2 = &_cs_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_155 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_111}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_158, cs_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_158 = {cs_decoder_decoded_andMatrixOutputs_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_32_2 = &_cs_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_108}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_156 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_112}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_159, cs_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_159 = {cs_decoder_decoded_andMatrixOutputs_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_94_2 = &_cs_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_157 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_113}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_160, cs_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_160 = {cs_decoder_decoded_andMatrixOutputs_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_84_2 = &_cs_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_110}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_158 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_114}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_161, cs_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_161 = {cs_decoder_decoded_andMatrixOutputs_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_101_2 = &_cs_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_111}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_159 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_162, cs_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_162 = {cs_decoder_decoded_andMatrixOutputs_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_132_2 = &_cs_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_112}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_160 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_116}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_163, cs_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_163 = {cs_decoder_decoded_andMatrixOutputs_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_90_2 = &_cs_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_113}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_161 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_117}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_164, cs_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_164 = {cs_decoder_decoded_andMatrixOutputs_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_27_2 = &_cs_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_17}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_27}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_114}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_162 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_118}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_165, cs_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_165 = {cs_decoder_decoded_andMatrixOutputs_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_148_2 = &_cs_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_18}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_28}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_115}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_163 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_119}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_166, cs_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_166 = {cs_decoder_decoded_andMatrixOutputs_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_67_2 = &_cs_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_19}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_29}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_116}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_164 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_120}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_167, cs_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_167 = {cs_decoder_decoded_andMatrixOutputs_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_34_2 = &_cs_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_20}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_30}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_117}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_168 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_165 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_121}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_168, cs_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_168 = {cs_decoder_decoded_andMatrixOutputs_hi_168, cs_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_59_2 = &_cs_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_130_2, cs_decoder_decoded_andMatrixOutputs_94_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi = {cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo = {cs_decoder_decoded_orMatrixOutputs_lo_hi, cs_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN = {cs_decoder_decoded_andMatrixOutputs_152_2, cs_decoder_decoded_andMatrixOutputs_98_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = _GEN; // @[pla.scala:114:19] wire [1:0] _GEN_0 = {cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_18 = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = _GEN_0; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi = {cs_decoder_decoded_orMatrixOutputs_hi_hi, cs_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T = {cs_decoder_decoded_orMatrixOutputs_hi, cs_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_1 = \|_cs_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_1 = {cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_1 = _GEN_1; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_27; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_27 = _GEN_1; // @[pla.scala:114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_4 = {cs_decoder_decoded_orMatrixOutputs_hi_1, cs_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_5 = \|_cs_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_2 = {cs_decoder_decoded_andMatrixOutputs_23_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_1 = _GEN_2; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = _GEN_2; // @[pla.scala:114:19] wire [1:0] _GEN_3 = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_2 = _GEN_3; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_17; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_17 = _GEN_3; // @[pla.scala:114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_6 = {cs_decoder_decoded_orMatrixOutputs_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_7 = \|_cs_decoder_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_4 = {cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_2 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_15 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_33; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_33 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_3 = {cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_8 = {cs_decoder_decoded_orMatrixOutputs_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_9 = \|_cs_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_5 = {cs_decoder_decoded_andMatrixOutputs_132_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_10 = _GEN_5; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_17; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_17 = _GEN_5; // @[pla.scala:114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_91; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_91 = _GEN_5; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_11 = \|_cs_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_6 = {cs_decoder_decoded_andMatrixOutputs_11_2, cs_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = _GEN_6; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = _GEN_6; // @[pla.scala:114:19] wire [1:0] _GEN_7 = {cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = _GEN_7; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = _GEN_7; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_12 = {cs_decoder_decoded_orMatrixOutputs_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_13 = \|_cs_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_67_2, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_109_2, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_148_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_14 = {cs_decoder_decoded_orMatrixOutputs_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_15 = \|_cs_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_8 = {cs_decoder_decoded_andMatrixOutputs_115_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_5 = _GEN_8; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = _GEN_8; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_15; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_15 = _GEN_8; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_18 = {cs_decoder_decoded_orMatrixOutputs_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_19 = \|_cs_decoder_decoded_orMatrixOutputs_T_18; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_20 = {cs_decoder_decoded_orMatrixOutputs_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_21 = \|_cs_decoder_decoded_orMatrixOutputs_T_20; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_122_2, cs_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_143_2, cs_decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_124_2, cs_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_75_2, cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [14:0] _cs_decoder_decoded_orMatrixOutputs_T_22 = {cs_decoder_decoded_orMatrixOutputs_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_23 = \|_cs_decoder_decoded_orMatrixOutputs_T_22; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_49_2, cs_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_119_2, cs_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_22_2, cs_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_38_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_57_2, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_149_2, cs_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_136_2, cs_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] cs_decoder_decoded_orMatrixOutputs_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [18:0] _cs_decoder_decoded_orMatrixOutputs_T_24 = {cs_decoder_decoded_orMatrixOutputs_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_25 = \|_cs_decoder_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_9 = {cs_decoder_decoded_andMatrixOutputs_156_2, cs_decoder_decoded_andMatrixOutputs_116_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_6; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_6 = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_6_2, cs_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_127_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_114_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_113_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_26 = {cs_decoder_decoded_orMatrixOutputs_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_27 = \|_cs_decoder_decoded_orMatrixOutputs_T_26; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_46_2, cs_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_125_2, cs_decoder_decoded_andMatrixOutputs_154_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_135_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_111_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_28 = {cs_decoder_decoded_orMatrixOutputs_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_29 = \|_cs_decoder_decoded_orMatrixOutputs_T_28; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_150_2, cs_decoder_decoded_andMatrixOutputs_31_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_10 = {cs_decoder_decoded_andMatrixOutputs_91_2, cs_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_87_2, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_12_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_51_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19] wire [13:0] _cs_decoder_decoded_orMatrixOutputs_T_30 = {cs_decoder_decoded_orMatrixOutputs_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_31 = \|_cs_decoder_decoded_orMatrixOutputs_T_30; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_78_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_19_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_55_2, cs_decoder_decoded_andMatrixOutputs_128_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_44_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_11 = {cs_decoder_decoded_andMatrixOutputs_116_2, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_146_2, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_35_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_165_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_108_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_105_2, cs_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_12 = {cs_decoder_decoded_andMatrixOutputs_112_2, cs_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = _GEN_12; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = _GEN_12; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_8_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_62_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19] wire [31:0] _cs_decoder_decoded_orMatrixOutputs_T_32 = {cs_decoder_decoded_orMatrixOutputs_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_33 = \|_cs_decoder_decoded_orMatrixOutputs_T_32; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_35 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_36 = \|_cs_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_13 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_11; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_11 = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_26; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_26 = _GEN_13; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_37 = {cs_decoder_decoded_orMatrixOutputs_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_38 = \|_cs_decoder_decoded_orMatrixOutputs_T_37; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_14 = {cs_decoder_decoded_andMatrixOutputs_118_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = _GEN_14; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = _GEN_14; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] _GEN_15 = {cs_decoder_decoded_andMatrixOutputs_17_2, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = _GEN_15; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = _GEN_15; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_39 = {cs_decoder_decoded_orMatrixOutputs_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_40 = \|_cs_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_95_2, cs_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_16 = {cs_decoder_decoded_andMatrixOutputs_58_2, cs_decoder_decoded_andMatrixOutputs_129_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = _GEN_16; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = _GEN_16; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_41 = {cs_decoder_decoded_orMatrixOutputs_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_42 = \|_cs_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_16 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_17 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_43 = {cs_decoder_decoded_orMatrixOutputs_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_44 = \|_cs_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_18 = {cs_decoder_decoded_andMatrixOutputs_118_2, cs_decoder_decoded_andMatrixOutputs_54_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_45 = {cs_decoder_decoded_orMatrixOutputs_hi_18, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_46 = \|_cs_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_17 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_147_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_19 = {cs_decoder_decoded_andMatrixOutputs_99_2, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_47 = {cs_decoder_decoded_orMatrixOutputs_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_48 = \|_cs_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_17 = {cs_decoder_decoded_andMatrixOutputs_17_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_51 = _GEN_17; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_18 = _GEN_17; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_23; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_23 = _GEN_17; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_52 = \|_cs_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_53 = {cs_decoder_decoded_orMatrixOutputs_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_54 = \|_cs_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_19 = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_18 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_21; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_21 = _GEN_18; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_25; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_25 = _GEN_18; // @[pla.scala:114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_55 = {cs_decoder_decoded_orMatrixOutputs_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_56 = \|_cs_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_164_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_57 = {cs_decoder_decoded_orMatrixOutputs_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_58 = \|_cs_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_19 = {cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = _GEN_19; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_20 = {cs_decoder_decoded_andMatrixOutputs_158_2, cs_decoder_decoded_andMatrixOutputs_91_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = _GEN_20; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = _GEN_20; // @[pla.scala:114:19] wire [1:0] _GEN_21 = {cs_decoder_decoded_andMatrixOutputs_36_2, cs_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = _GEN_21; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_22 = {cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = _GEN_22; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = _GEN_22; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = _GEN_22; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = _GEN_22; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_104_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_23 = {cs_decoder_decoded_andMatrixOutputs_97_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = _GEN_23; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = _GEN_23; // @[pla.scala:114:19] wire [1:0] _GEN_24 = {cs_decoder_decoded_andMatrixOutputs_51_2, cs_decoder_decoded_andMatrixOutputs_129_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = _GEN_24; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = _GEN_24; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_160_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_52_2, cs_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] _GEN_25 = {cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = _GEN_25; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = _GEN_25; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = _GEN_25; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_26 = {cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_77_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = _GEN_26; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = _GEN_26; // @[pla.scala:114:19] wire [1:0] _GEN_27 = {cs_decoder_decoded_andMatrixOutputs_81_2, cs_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_27; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19] wire [27:0] _cs_decoder_decoded_orMatrixOutputs_T_59 = {cs_decoder_decoded_orMatrixOutputs_hi_23, cs_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_60 = \|_cs_decoder_decoded_orMatrixOutputs_T_59; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_13 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_104_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_0_2, cs_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_71_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_112_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19] wire [14:0] cs_decoder_decoded_orMatrixOutputs_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19] wire [28:0] _cs_decoder_decoded_orMatrixOutputs_T_61 = {cs_decoder_decoded_orMatrixOutputs_hi_24, cs_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_62 = \|_cs_decoder_decoded_orMatrixOutputs_T_61; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_28 = {cs_decoder_decoded_andMatrixOutputs_7_2, cs_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_16; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_16 = _GEN_28; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = _GEN_28; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = _GEN_28; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_23 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_25 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_107_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_64 = {cs_decoder_decoded_orMatrixOutputs_hi_25, cs_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_65 = \|_cs_decoder_decoded_orMatrixOutputs_T_64; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_32_2, cs_decoder_decoded_andMatrixOutputs_94_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_106_2, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_128_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] _GEN_29 = {cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = _GEN_29; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = _GEN_29; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_104_2, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_134_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_24 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_0_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_30 = {cs_decoder_decoded_andMatrixOutputs_77_2, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = _GEN_30; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = _GEN_30; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = _GEN_30; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19] wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_26 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19] wire [32:0] _cs_decoder_decoded_orMatrixOutputs_T_66 = {cs_decoder_decoded_orMatrixOutputs_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_67 = \|_cs_decoder_decoded_orMatrixOutputs_T_66; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_25 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_18, cs_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_27 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_68 = {cs_decoder_decoded_orMatrixOutputs_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_69 = \|_cs_decoder_decoded_orMatrixOutputs_T_68; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_134_2, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_3_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_72_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_28 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19] wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T_70 = {cs_decoder_decoded_orMatrixOutputs_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_71 = \|_cs_decoder_decoded_orMatrixOutputs_T_70; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] _GEN_31 = {cs_decoder_decoded_andMatrixOutputs_123_2, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = _GEN_31; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = _GEN_31; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = _GEN_31; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_73_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_72 = {cs_decoder_decoded_orMatrixOutputs_hi_29, cs_decoder_decoded_orMatrixOutputs_lo_27}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_73 = \|_cs_decoder_decoded_orMatrixOutputs_T_72; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_32 = {cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = _GEN_32; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = _GEN_32; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1 = _GEN_32; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_33 = {cs_decoder_decoded_andMatrixOutputs_117_2, cs_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = _GEN_33; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = _GEN_33; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] _GEN_34 = {cs_decoder_decoded_andMatrixOutputs_44_2, cs_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = _GEN_34; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN_34; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_58_2, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19] wire [23:0] cs_decoder_decoded_orMatrixOutputs_lo_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] _GEN_35 = {cs_decoder_decoded_andMatrixOutputs_25_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = _GEN_35; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1 = _GEN_35; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_36 = {cs_decoder_decoded_andMatrixOutputs_18_2, cs_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = _GEN_36; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = _GEN_36; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_56_2, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] _GEN_37 = {cs_decoder_decoded_andMatrixOutputs_166_2, cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_37; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = _GEN_37; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_80_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19] wire [12:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19] wire [24:0] cs_decoder_decoded_orMatrixOutputs_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_23, cs_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19] wire [48:0] _cs_decoder_decoded_orMatrixOutputs_T_74 = {cs_decoder_decoded_orMatrixOutputs_hi_30, cs_decoder_decoded_orMatrixOutputs_lo_28}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_75 = \|_cs_decoder_decoded_orMatrixOutputs_T_74; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_83_2, cs_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_128_2, cs_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_38 = {cs_decoder_decoded_andMatrixOutputs_36_2, cs_decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = _GEN_38; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = _GEN_38; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_28_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_37_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19] wire [14:0] cs_decoder_decoded_orMatrixOutputs_lo_29 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_25_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_39 = {cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = _GEN_39; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = _GEN_39; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_138_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_112_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_14_2, cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_62_2, cs_decoder_decoded_andMatrixOutputs_77_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_hi_31 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_24, cs_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19] wire [30:0] _cs_decoder_decoded_orMatrixOutputs_T_76 = {cs_decoder_decoded_orMatrixOutputs_hi_31, cs_decoder_decoded_orMatrixOutputs_lo_29}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_77 = \|_cs_decoder_decoded_orMatrixOutputs_T_76; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_30 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_32 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_25, cs_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19] wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_78 = {cs_decoder_decoded_orMatrixOutputs_hi_32, cs_decoder_decoded_orMatrixOutputs_lo_30}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_79 = \|_cs_decoder_decoded_orMatrixOutputs_T_78; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_33 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_80 = {cs_decoder_decoded_orMatrixOutputs_hi_33, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_81 = \|_cs_decoder_decoded_orMatrixOutputs_T_80; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_82 = {cs_decoder_decoded_andMatrixOutputs_141_2, cs_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_83 = \|_cs_decoder_decoded_orMatrixOutputs_T_82; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_134_2, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_31 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_34 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_26, cs_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:114:19] wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_85 = {cs_decoder_decoded_orMatrixOutputs_hi_34, cs_decoder_decoded_orMatrixOutputs_lo_31}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_86 = \|_cs_decoder_decoded_orMatrixOutputs_T_85; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_40_2, cs_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_32 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_161_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_35 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_27, cs_decoder_decoded_orMatrixOutputs_hi_lo_22}; // @[pla.scala:114:19] wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_87 = {cs_decoder_decoded_orMatrixOutputs_hi_35, cs_decoder_decoded_orMatrixOutputs_lo_32}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_88 = \|_cs_decoder_decoded_orMatrixOutputs_T_87; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_89 = {cs_decoder_decoded_andMatrixOutputs_82_2, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_90 = \|_cs_decoder_decoded_orMatrixOutputs_T_89; // @[pla.scala:114:{19,36}] wire _cs_decoder_decoded_orMatrixOutputs_T_92 = \|_cs_decoder_decoded_orMatrixOutputs_T_91; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_107_2, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_36 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_93 = {cs_decoder_decoded_orMatrixOutputs_hi_36, cs_decoder_decoded_orMatrixOutputs_lo_33}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_94 = \|_cs_decoder_decoded_orMatrixOutputs_T_93; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_34 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_37 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_29, cs_decoder_decoded_orMatrixOutputs_hi_lo_23}; // @[pla.scala:114:19] wire [11:0] _cs_decoder_decoded_orMatrixOutputs_T_95 = {cs_decoder_decoded_orMatrixOutputs_hi_37, cs_decoder_decoded_orMatrixOutputs_lo_34}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_96 = \|_cs_decoder_decoded_orMatrixOutputs_T_95; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_133_2, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_97_2, cs_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19] wire [27:0] cs_decoder_decoded_orMatrixOutputs_lo_35 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_lo_21}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_35_2, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_76_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_105_2, cs_decoder_decoded_andMatrixOutputs_86_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_80_2, cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_26_2, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19] wire [14:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19] wire [28:0] cs_decoder_decoded_orMatrixOutputs_hi_38 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_30, cs_decoder_decoded_orMatrixOutputs_hi_lo_24}; // @[pla.scala:114:19] wire [56:0] _cs_decoder_decoded_orMatrixOutputs_T_97 = {cs_decoder_decoded_orMatrixOutputs_hi_38, cs_decoder_decoded_orMatrixOutputs_lo_35}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_98 = \|_cs_decoder_decoded_orMatrixOutputs_T_97; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_3, _cs_decoder_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_7, _cs_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_11, _cs_decoder_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_16, _cs_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_17, 1'h0}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_21, _cs_decoder_decoded_orMatrixOutputs_T_19}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:102:36] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_23, 1'h0}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2, 1'h0}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_27, _cs_decoder_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_31, _cs_decoder_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_36, _cs_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_33}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_40, _cs_decoder_decoded_orMatrixOutputs_T_38}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_44, _cs_decoder_decoded_orMatrixOutputs_T_42}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:102:36] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:102:36] wire [27:0] cs_decoder_decoded_orMatrixOutputs_lo_36 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_lo_22}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_49, _cs_decoder_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_52, _cs_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_56, _cs_decoder_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_62, _cs_decoder_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_65, _cs_decoder_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_69, _cs_decoder_decoded_orMatrixOutputs_T_67}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:102:36] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_75, _cs_decoder_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2, _cs_decoder_decoded_orMatrixOutputs_T_71}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_79, _cs_decoder_decoded_orMatrixOutputs_T_77}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_83, _cs_decoder_decoded_orMatrixOutputs_T_81}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_1}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_1 = {_cs_decoder_decoded_orMatrixOutputs_T_86, _cs_decoder_decoded_orMatrixOutputs_T_84}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_90, _cs_decoder_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_1}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_2 = {_cs_decoder_decoded_orMatrixOutputs_T_94, _cs_decoder_decoded_orMatrixOutputs_T_92}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = {_cs_decoder_decoded_orMatrixOutputs_T_98, _cs_decoder_decoded_orMatrixOutputs_T_96}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_2}; // @[pla.scala:102:36] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36] wire [14:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_31 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:102:36] wire [28:0] cs_decoder_decoded_orMatrixOutputs_hi_39 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_31, cs_decoder_decoded_orMatrixOutputs_hi_lo_25}; // @[pla.scala:102:36] wire [56:0] cs_decoder_decoded_orMatrixOutputs = {cs_decoder_decoded_orMatrixOutputs_hi_39, cs_decoder_decoded_orMatrixOutputs_lo_36}; // @[pla.scala:102:36] wire _cs_decoder_decoded_invMatrixOutputs_T = cs_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_1 = cs_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_2 = cs_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_3 = cs_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_4 = cs_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_5 = cs_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_6 = cs_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_7 = cs_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_8 = cs_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_9 = cs_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_10 = cs_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_11 = cs_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_12 = cs_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_13 = cs_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_14 = cs_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_15 = cs_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_16 = cs_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_17 = cs_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_18 = cs_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_19 = cs_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_20 = cs_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_21 = cs_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_22 = cs_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_23 = cs_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_24 = cs_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_25 = cs_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_26 = cs_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_27 = cs_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_28 = cs_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_29 = cs_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_30 = cs_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_31 = cs_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_32 = cs_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_33 = cs_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_34 = cs_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_35 = cs_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_36 = cs_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_37 = ~_cs_decoder_decoded_invMatrixOutputs_T_36; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_38 = cs_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_39 = ~_cs_decoder_decoded_invMatrixOutputs_T_38; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_40 = cs_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_41 = cs_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_42 = cs_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_43 = cs_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_44 = cs_decoder_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_45 = cs_decoder_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_46 = cs_decoder_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_47 = ~_cs_decoder_decoded_invMatrixOutputs_T_46; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_48 = cs_decoder_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_49 = cs_decoder_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_50 = cs_decoder_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_51 = cs_decoder_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_52 = cs_decoder_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_53 = cs_decoder_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_54 = cs_decoder_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_55 = cs_decoder_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_56 = cs_decoder_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_57 = cs_decoder_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_58 = cs_decoder_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_59 = cs_decoder_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_2, _cs_decoder_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_4, _cs_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_6, _cs_decoder_decoded_invMatrixOutputs_T_5}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_9, _cs_decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_11, _cs_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_13, _cs_decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [13:0] cs_decoder_decoded_invMatrixOutputs_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_16, _cs_decoder_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_18, _cs_decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_20, _cs_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_23, _cs_decoder_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_25, _cs_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_27, _cs_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [13:0] cs_decoder_decoded_invMatrixOutputs_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [27:0] cs_decoder_decoded_invMatrixOutputs_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_30, _cs_decoder_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_32, _cs_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_34, _cs_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_39, _cs_decoder_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :123:40] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_35}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_41, _cs_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_43, _cs_decoder_decoded_invMatrixOutputs_T_42}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [13:0] cs_decoder_decoded_invMatrixOutputs_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_47, _cs_decoder_decoded_invMatrixOutputs_T_45}; // @[pla.scala:120:37, :123:40, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_49, _cs_decoder_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_51, _cs_decoder_decoded_invMatrixOutputs_T_50}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {_cs_decoder_decoded_invMatrixOutputs_T_53, _cs_decoder_decoded_invMatrixOutputs_T_52}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_55, _cs_decoder_decoded_invMatrixOutputs_T_54}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_57, _cs_decoder_decoded_invMatrixOutputs_T_56}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_59, _cs_decoder_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [7:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [14:0] cs_decoder_decoded_invMatrixOutputs_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [28:0] cs_decoder_decoded_invMatrixOutputs_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign cs_decoder_decoded_invMatrixOutputs = {cs_decoder_decoded_invMatrixOutputs_hi, cs_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign cs_decoder_decoded = cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign cs_decoder_0 = cs_decoder_decoded[56]; // @[pla.scala:81:23] assign cs_legal = cs_decoder_0; // @[Decode.scala:50:77] assign cs_decoder_1 = cs_decoder_decoded[55]; // @[pla.scala:81:23] assign cs_fp_val = cs_decoder_1; // @[Decode.scala:50:77] assign cs_decoder_2 = cs_decoder_decoded[54:45]; // @[pla.scala:81:23] assign cs_fu_code = cs_decoder_2; // @[Decode.scala:50:77] assign cs_decoder_3 = cs_decoder_decoded[44:43]; // @[pla.scala:81:23] assign cs_dst_type = cs_decoder_3; // @[Decode.scala:50:77] assign cs_decoder_4 = cs_decoder_decoded[42:41]; // @[pla.scala:81:23] assign cs_rs1_type = cs_decoder_4; // @[Decode.scala:50:77] assign cs_decoder_5 = cs_decoder_decoded[40:39]; // @[pla.scala:81:23] assign cs_rs2_type = cs_decoder_5; // @[Decode.scala:50:77] assign cs_decoder_6 = cs_decoder_decoded[38]; // @[pla.scala:81:23] assign cs_frs3_en = cs_decoder_6; // @[Decode.scala:50:77] assign cs_decoder_7 = cs_decoder_decoded[37:35]; // @[pla.scala:81:23] assign cs_imm_sel = cs_decoder_7; // @[Decode.scala:50:77] assign cs_decoder_8 = cs_decoder_decoded[34]; // @[pla.scala:81:23] assign cs_uses_ldq = cs_decoder_8; // @[Decode.scala:50:77] assign cs_decoder_9 = cs_decoder_decoded[33]; // @[pla.scala:81:23] assign cs_uses_stq = cs_decoder_9; // @[Decode.scala:50:77] assign cs_decoder_10 = cs_decoder_decoded[32]; // @[pla.scala:81:23] assign cs_is_amo = cs_decoder_10; // @[Decode.scala:50:77] assign cs_decoder_11 = cs_decoder_decoded[31:27]; // @[pla.scala:81:23] assign cs_mem_cmd = cs_decoder_11; // @[Decode.scala:50:77] assign cs_decoder_12 = cs_decoder_decoded[26]; // @[pla.scala:81:23] assign cs_inst_unique = cs_decoder_12; // @[Decode.scala:50:77] assign cs_decoder_13 = cs_decoder_decoded[25]; // @[pla.scala:81:23] assign cs_flush_on_commit = cs_decoder_13; // @[Decode.scala:50:77] assign cs_decoder_14 = cs_decoder_decoded[24:22]; // @[pla.scala:81:23] assign cs_csr_cmd = cs_decoder_14; // @[Decode.scala:50:77] assign cs_decoder_15 = cs_decoder_decoded[21]; // @[pla.scala:81:23] assign cs_fcn_dw = cs_decoder_15; // @[Decode.scala:50:77] assign cs_decoder_16 = cs_decoder_decoded[20:16]; // @[pla.scala:81:23] assign cs_fcn_op = cs_decoder_16; // @[Decode.scala:50:77] assign cs_decoder_17 = cs_decoder_decoded[15]; // @[pla.scala:81:23] assign cs_fp_ldst = cs_decoder_17; // @[Decode.scala:50:77] assign cs_decoder_18 = cs_decoder_decoded[14]; // @[pla.scala:81:23] assign cs_fp_wen = cs_decoder_18; // @[Decode.scala:50:77] assign cs_decoder_19 = cs_decoder_decoded[13]; // @[pla.scala:81:23] assign cs_fp_ren1 = cs_decoder_19; // @[Decode.scala:50:77] assign cs_decoder_20 = cs_decoder_decoded[12]; // @[pla.scala:81:23] assign cs_fp_ren2 = cs_decoder_20; // @[Decode.scala:50:77] assign cs_decoder_21 = cs_decoder_decoded[11]; // @[pla.scala:81:23] assign cs_fp_ren3 = cs_decoder_21; // @[Decode.scala:50:77] assign cs_decoder_22 = cs_decoder_decoded[10]; // @[pla.scala:81:23] assign cs_fp_swap12 = cs_decoder_22; // @[Decode.scala:50:77] assign cs_decoder_23 = cs_decoder_decoded[9]; // @[pla.scala:81:23] assign cs_fp_swap23 = cs_decoder_23; // @[Decode.scala:50:77] wire cs_decoder_24 = cs_decoder_decoded[8]; // @[pla.scala:81:23] wire cs_decoder_25 = cs_decoder_decoded[7]; // @[pla.scala:81:23] assign cs_decoder_26 = cs_decoder_decoded[6]; // @[pla.scala:81:23] assign cs_fp_fromint = cs_decoder_26; // @[Decode.scala:50:77] assign cs_decoder_27 = cs_decoder_decoded[5]; // @[pla.scala:81:23] assign cs_fp_toint = cs_decoder_27; // @[Decode.scala:50:77] assign cs_decoder_28 = cs_decoder_decoded[4]; // @[pla.scala:81:23] assign cs_fp_fastpipe = cs_decoder_28; // @[Decode.scala:50:77] assign cs_decoder_29 = cs_decoder_decoded[3]; // @[pla.scala:81:23] assign cs_fp_fma = cs_decoder_29; // @[Decode.scala:50:77] assign cs_decoder_30 = cs_decoder_decoded[2]; // @[pla.scala:81:23] assign cs_fp_div = cs_decoder_30; // @[Decode.scala:50:77] assign cs_decoder_31 = cs_decoder_decoded[1]; // @[pla.scala:81:23] assign cs_fp_sqrt = cs_decoder_31; // @[Decode.scala:50:77] assign cs_decoder_32 = cs_decoder_decoded[0]; // @[pla.scala:81:23] assign cs_fp_wflags = cs_decoder_32; // @[Decode.scala:50:77] assign cs_fp_typeTagIn = {1'h0, cs_decoder_24}; // @[Decode.scala:50:77] assign cs_fp_typeTagOut = {1'h0, cs_decoder_25}; // @[Decode.scala:50:77] wire _T_29 = cs_csr_cmd == 3'h6; // @[package.scala:16:47] wire _csr_en_T; // @[package.scala:16:47] assign _csr_en_T = _T_29; // @[package.scala:16:47] wire _csr_ren_T; // @[package.scala:16:47] assign _csr_ren_T = _T_29; // @[package.scala:16:47] wire _csr_en_T_1 = &cs_csr_cmd; // @[package.scala:16:47] wire _csr_en_T_2 = cs_csr_cmd == 3'h5; // @[package.scala:16:47] wire _csr_en_T_3 = _csr_en_T \| _csr_en_T_1; // @[package.scala:16:47, :81:59] wire csr_en = _csr_en_T_3 \| _csr_en_T_2; // @[package.scala:16:47, :81:59] wire _csr_ren_T_1 = &cs_csr_cmd; // @[package.scala:16:47] wire _csr_ren_T_2 = _csr_ren_T \| _csr_ren_T_1; // @[package.scala:16:47, :81:59] wire _csr_ren_T_3 = uop_lrs1 == 6'h0; // @[decode.scala:422:7, :426:14, :428:17, :452:62] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[package.scala:81:59] wire system_insn = cs_csr_cmd == 3'h4; // @[decode.scala:447:16, :453:32] wire [31:0] _GEN_40 = uop_inst & 32'hFE007FFF; // @[decode.scala:428:17, :454:21] wire [31:0] _sfence_T; // @[decode.scala:454:21] assign _sfence_T = _GEN_40; // @[decode.scala:454:21] wire [31:0] _uop_is_sfence_T; // @[decode.scala:528:26] assign _uop_is_sfence_T = _GEN_40; // @[decode.scala:454:21, :528:26] wire sfence = _sfence_T == 32'h12000073; // @[decode.scala:454:21] wire [2:0] _illegal_rm_T = uop_inst[14:12]; // @[decode.scala:428:17, :460:24] wire [2:0] _illegal_rm_T_4 = uop_inst[14:12]; // @[decode.scala:428:17, :460:{24,57}] wire [2:0] _uop_is_rocc_T_6 = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :532:88] wire [2:0] _uop_pimm_T_1 = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :553:47] wire [2:0] _uop_fp_rm_T = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :556:26] wire [2:0] _uop_fp_rm_T_2 = uop_inst[14:12]; // @[decode.scala:428:17, :460:24, :556:59] wire _illegal_rm_T_1 = _illegal_rm_T == 3'h5; // @[package.scala:16:47] wire _illegal_rm_T_2 = _illegal_rm_T == 3'h6; // @[package.scala:16:47] wire _illegal_rm_T_3 = _illegal_rm_T_1 \| _illegal_rm_T_2; // @[package.scala:16:47, :81:59] wire _illegal_rm_T_5 = &_illegal_rm_T_4; // @[decode.scala:460:{57,65}] wire _illegal_rm_T_6 = io_fcsr_rm_0 > 3'h4; // @[decode.scala:422:7, :460:87] wire _illegal_rm_T_7 = _illegal_rm_T_5 & _illegal_rm_T_6; // @[decode.scala:460:{65,73,87}] wire illegal_rm = _illegal_rm_T_3 \| _illegal_rm_T_7; // @[package.scala:81:59] wire _id_illegal_insn_T = ~cs_legal; // @[decode.scala:447:16, :461:26] wire _id_illegal_insn_T_1 = io_csr_decode_fp_illegal_0 \| illegal_rm; // @[decode.scala:422:7, :460:49, :462:45] wire _id_illegal_insn_T_2 = cs_fp_val & _id_illegal_insn_T_1; // @[decode.scala:447:16, :462:{16,45}] wire _id_illegal_insn_T_3 = _id_illegal_insn_T \| _id_illegal_insn_T_2; // @[decode.scala:461:{26,36}, :462:16] wire _id_illegal_insn_T_5 = _id_illegal_insn_T_3 \| _id_illegal_insn_T_4; // @[decode.scala:461:36, :462:61, :463:18] wire _id_illegal_insn_T_9 = _id_illegal_insn_T_5; // @[decode.scala:462:61, :463:49] wire _id_illegal_insn_T_10 = ~csr_ren; // @[decode.scala:452:50, :465:47] wire _id_illegal_insn_T_11 = _id_illegal_insn_T_10 & io_csr_decode_write_illegal_0; // @[decode.scala:422:7, :465:{47,56}] wire _id_illegal_insn_T_12 = io_csr_decode_read_illegal_0 \| _id_illegal_insn_T_11; // @[decode.scala:422:7, :465:{44,56}] wire _id_illegal_insn_T_13 = csr_en & _id_illegal_insn_T_12; // @[package.scala:81:59] wire _id_illegal_insn_T_14 = _id_illegal_insn_T_9 \| _id_illegal_insn_T_13; // @[decode.scala:463:49, :464:45, :465:13] wire _id_illegal_insn_T_15 = sfence \| system_insn; // @[decode.scala:453:32, :454:21, :466:14] wire _id_illegal_insn_T_16 = _id_illegal_insn_T_15 & io_csr_decode_system_illegal_0; // @[decode.scala:422:7, :466:{14,30}] wire id_illegal_insn = _id_illegal_insn_T_14 \| _id_illegal_insn_T_16; // @[decode.scala:464:45, :465:89, :466:30] wire _T_1 = io_interrupt_0 & ~io_enq_uop_is_sfb_0; // @[decode.scala:422:7, :473:{19,22}] assign xcpt_valid = _T_1 \| uop_bp_debug_if \| uop_bp_xcpt_if \| uop_xcpt_pf_if \| uop_xcpt_ae_if \| id_illegal_insn; // @[decode.scala:428:17, :465:89, :470:26, :473:19] assign uop_exception = xcpt_valid; // @[decode.scala:428:17, :470:26] assign xcpt_cause = _T_1 ? io_interrupt_cause_0 : {60'h0, uop_bp_debug_if ? 4'hE : uop_bp_xcpt_if ? 4'h3 : uop_xcpt_pf_if ? 4'hC : {2'h0, uop_xcpt_ae_if ? 2'h1 : 2'h2}}; // @[Mux.scala:50:70] assign uop_exc_cause = xcpt_cause; // @[Mux.scala:50:70] wire [31:0] _uop_is_mov_T = uop_inst & 32'hFE00707F; // @[decode.scala:428:17, :485:26] wire _uop_is_mov_T_1 = _uop_is_mov_T == 32'h33; // @[decode.scala:485:26] wire _uop_is_mov_T_2 = ~(\|LRS1); // @[decode.scala:442:18, :485:42] assign _uop_is_mov_T_3 = _uop_is_mov_T_1 & _uop_is_mov_T_2; // @[decode.scala:485:{26,34,42}] assign uop_is_mov = _uop_is_mov_T_3; // @[decode.scala:428:17, :485:34] assign uop_fu_code_3 = cs_fu_code[3]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T = cs_fu_code[3]; // @[decode.scala:447:16, :487:84] assign uop_fu_code_4 = cs_fu_code[4]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T_1 = cs_fu_code[4]; // @[decode.scala:447:16, :487:84] assign uop_fu_code_5 = cs_fu_code[5]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T_2 = cs_fu_code[5]; // @[decode.scala:447:16, :487:84] assign uop_fu_code_8 = cs_fu_code[8]; // @[decode.scala:428:17, :447:16, :487:84] wire _uop_iq_type_1_T_3 = cs_fu_code[8]; // @[decode.scala:447:16, :487:84] wire _uop_iq_type_1_T_4 = _uop_iq_type_1_T \| _uop_iq_type_1_T_1; // @[decode.scala:487:{84,98}] wire _uop_iq_type_1_T_5 = _uop_iq_type_1_T_4 \| _uop_iq_type_1_T_2; // @[decode.scala:487:{84,98}] assign _uop_iq_type_1_T_6 = _uop_iq_type_1_T_5 \| _uop_iq_type_1_T_3; // @[decode.scala:487:{84,98}] assign uop_iq_type_1 = _uop_iq_type_1_T_6; // @[decode.scala:428:17, :487:98] assign uop_fu_code_0 = cs_fu_code[0]; // @[decode.scala:428:17, :447:16, :488:84] assign _uop_iq_type_2_T = cs_fu_code[0]; // @[decode.scala:447:16, :488:84] assign uop_iq_type_2 = _uop_iq_type_2_T; // @[decode.scala:428:17, :488:84] assign uop_fu_code_1 = cs_fu_code[1]; // @[decode.scala:428:17, :447:16, :489:84] wire _uop_iq_type_0_T = cs_fu_code[1]; // @[decode.scala:447:16, :489:84] assign uop_fu_code_2 = cs_fu_code[2]; // @[decode.scala:428:17, :447:16, :489:84] wire _uop_iq_type_0_T_1 = cs_fu_code[2]; // @[decode.scala:447:16, :489:84] assign _uop_iq_type_0_T_2 = _uop_iq_type_0_T \| _uop_iq_type_0_T_1; // @[decode.scala:489:{84,98}] assign uop_iq_type_0 = _uop_iq_type_0_T_2; // @[decode.scala:428:17, :489:98] assign uop_fu_code_6 = cs_fu_code[6]; // @[decode.scala:428:17, :447:16, :490:84] wire _uop_iq_type_3_T = cs_fu_code[6]; // @[decode.scala:447:16, :490:84] assign uop_fu_code_7 = cs_fu_code[7]; // @[decode.scala:428:17, :447:16, :490:84] wire _uop_iq_type_3_T_1 = cs_fu_code[7]; // @[decode.scala:447:16, :490:84] assign uop_fu_code_9 = cs_fu_code[9]; // @[decode.scala:428:17, :447:16, :490:84] wire _uop_iq_type_3_T_2 = cs_fu_code[9]; // @[decode.scala:447:16, :490:84] wire _uop_iq_type_3_T_3 = _uop_iq_type_3_T \| _uop_iq_type_3_T_1; // @[decode.scala:490:{84,98}] assign _uop_iq_type_3_T_4 = _uop_iq_type_3_T_3 \| _uop_iq_type_3_T_2; // @[decode.scala:490:{84,98}] assign uop_iq_type_3 = _uop_iq_type_3_T_4; // @[decode.scala:428:17, :490:98] assign uop_ldst = {1'h0, LDST}; // @[decode.scala:428:17, :441:18, :494:18] assign uop_lrs3 = {1'h0, LRS3}; // @[decode.scala:428:17, :444:18, :497:18] wire _uop_lrs1_rtype_T = cs_rs1_type == 2'h0; // @[decode.scala:447:16, :500:37] wire _uop_lrs1_rtype_T_1 = ~(\|LRS1); // @[decode.scala:442:18, :485:42, :500:56] wire _uop_lrs1_rtype_T_2 = _uop_lrs1_rtype_T & _uop_lrs1_rtype_T_1; // @[decode.scala:500:{37,48,56}] wire [1:0] _uop_lrs1_rtype_T_3 = _uop_lrs1_rtype_T_2 ? 2'h3 : cs_rs1_type; // @[decode.scala:447:16, :500:{24,48}] wire _uop_lrs2_rtype_T = cs_rs2_type == 2'h0; // @[decode.scala:447:16, :501:37] wire _uop_lrs2_rtype_T_1 = ~(\|LRS2); // @[decode.scala:443:18, :501:56] wire _uop_lrs2_rtype_T_2 = _uop_lrs2_rtype_T & _uop_lrs2_rtype_T_1; // @[decode.scala:501:{37,48,56}] wire [1:0] _uop_lrs2_rtype_T_3 = _uop_lrs2_rtype_T_2 ? 2'h3 : cs_rs2_type; // @[decode.scala:447:16, :501:{24,48}] wire _uop_ldst_is_rs1_T = uop_br_type == 4'h0; // @[decode.scala:428:17] wire _uop_ldst_is_rs1_T_1 = _uop_ldst_is_rs1_T & uop_is_sfb; // @[decode.scala:428:17] wire _uop_ldst_is_rs1_T_2 = _uop_ldst_is_rs1_T_1; // @[micro-op.scala:121:{42,52}] wire _T_24 = _uop_ldst_is_rs1_T & uop_is_sfb & cs_rs2_type == 2'h2; // @[decode.scala:428:17, :447:16, :506:{27,42}] wire _GEN_41 = LDST == 5'h0; // @[decode.scala:422:7, :426:14, :428:17, :441:18, :507:33] wire _uop_lrs2_rtype_T_4; // @[decode.scala:507:33] assign _uop_lrs2_rtype_T_4 = _GEN_41; // @[decode.scala:507:33] wire _uop_lrs1_rtype_T_4; // @[decode.scala:512:33] assign _uop_lrs1_rtype_T_4 = _GEN_41; // @[decode.scala:507:33, :512:33] wire [1:0] _uop_lrs2_rtype_T_5 = {2{_uop_lrs2_rtype_T_4}}; // @[decode.scala:507:{27,33}] assign uop_lrs2_rtype = _T_24 ? _uop_lrs2_rtype_T_5 : _uop_lrs2_rtype_T_3; // @[decode.scala:428:17, :501:{18,24}, :506:{27,52}, :507:{21,27}] assign uop_lrs2 = {1'h0, _T_24 ? LDST : LRS2}; // @[decode.scala:428:17, :441:18, :443:18, :496:18, :506:{27,52}, :508:21] wire _T_28 = _uop_ldst_is_rs1_T & uop_is_sfb & uop_is_mov; // @[decode.scala:428:17, :510:34] wire _GEN_42 = _T_24 \| ~_T_28; // @[decode.scala:495:18, :506:{27,52}, :510:{34,49}] assign uop_lrs1 = {1'h0, _GEN_42 ? LRS1 : LDST}; // @[decode.scala:428:17, :441:18, :442:18, :495:18, :506:52, :510:49] wire [1:0] _uop_lrs1_rtype_T_5 = {2{_uop_lrs1_rtype_T_4}}; // @[decode.scala:512:{27,33}] assign uop_lrs1_rtype = _GEN_42 ? _uop_lrs1_rtype_T_3 : _uop_lrs1_rtype_T_5; // @[decode.scala:428:17, :495:18, :500:{18,24}, :506:52, :510:49, :512:27] assign uop_ldst_is_rs1 = ~_T_24 & (_T_28 \| _uop_ldst_is_rs1_T_2); // @[decode.scala:428:17, :504:19, :506:{27,52}, :509:21, :510:{34,49}, :513:21] wire _uop_mem_size_T = cs_mem_cmd == 5'h14; // @[package.scala:16:47] wire _uop_mem_size_T_1 = cs_mem_cmd == 5'h5; // @[package.scala:16:47] wire _uop_mem_size_T_2 = _uop_mem_size_T \| _uop_mem_size_T_1; // @[package.scala:16:47, :81:59] wire _uop_mem_size_T_3 = \|LRS2; // @[decode.scala:443:18, :501:56, :521:77] wire _uop_mem_size_T_4 = \|LRS1; // @[decode.scala:442:18, :485:42, :521:91] wire [1:0] _uop_mem_size_T_5 = {_uop_mem_size_T_3, _uop_mem_size_T_4}; // @[decode.scala:521:{71,77,91}] wire [1:0] _uop_mem_size_T_6 = uop_inst[13:12]; // @[decode.scala:428:17, :521:105] assign _uop_mem_size_T_7 = _uop_mem_size_T_2 ? _uop_mem_size_T_5 : _uop_mem_size_T_6; // @[package.scala:81:59] assign uop_mem_size = _uop_mem_size_T_7; // @[decode.scala:428:17, :521:24] wire _uop_mem_signed_T = uop_inst[14]; // @[decode.scala:428:17, :522:26] assign _uop_mem_signed_T_1 = ~_uop_mem_signed_T; // @[decode.scala:522:{21,26}] assign uop_mem_signed = _uop_mem_signed_T_1; // @[decode.scala:428:17, :522:21] wire [31:0] _GEN_43 = {17'h0, uop_inst[14:0] & 15'h707F}; // @[decode.scala:428:17, :526:26] wire [31:0] _uop_is_fence_T; // @[decode.scala:526:26] assign _uop_is_fence_T = _GEN_43; // @[decode.scala:526:26] wire [31:0] _uop_is_fencei_T; // @[decode.scala:527:26] assign _uop_is_fencei_T = _GEN_43; // @[decode.scala:526:26, :527:26] wire [31:0] _uop_br_type_T; // @[decode.scala:604:36] assign _uop_br_type_T = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_3; // @[decode.scala:604:36] assign _uop_br_type_T_3 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_6; // @[decode.scala:604:36] assign _uop_br_type_T_6 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_9; // @[decode.scala:604:36] assign _uop_br_type_T_9 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_12; // @[decode.scala:604:36] assign _uop_br_type_T_12 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_15; // @[decode.scala:604:36] assign _uop_br_type_T_15 = _GEN_43; // @[decode.scala:526:26, :604:36] wire [31:0] _uop_br_type_T_21; // @[decode.scala:604:36] assign _uop_br_type_T_21 = _GEN_43; // @[decode.scala:526:26, :604:36] assign _uop_is_fence_T_1 = _uop_is_fence_T == 32'hF; // @[decode.scala:526:26] assign uop_is_fence = _uop_is_fence_T_1; // @[decode.scala:428:17, :526:26] assign _uop_is_fencei_T_1 = _uop_is_fencei_T == 32'h100F; // @[decode.scala:527:26] assign uop_is_fencei = _uop_is_fencei_T_1; // @[decode.scala:428:17, :527:26] assign _uop_is_sfence_T_1 = _uop_is_sfence_T == 32'h12000073; // @[decode.scala:528:26] assign uop_is_sfence = _uop_is_sfence_T_1; // @[decode.scala:428:17, :528:26] wire _uop_is_sys_pc2epc_T_1 = _uop_is_sys_pc2epc_T == 32'h100073; // @[decode.scala:529:29] wire _uop_is_sys_pc2epc_T_3 = _uop_is_sys_pc2epc_T_2 == 32'h73; // @[decode.scala:529:48] assign _uop_is_sys_pc2epc_T_4 = _uop_is_sys_pc2epc_T_1 \| _uop_is_sys_pc2epc_T_3; // @[decode.scala:529:{29,40,48}] assign uop_is_sys_pc2epc = _uop_is_sys_pc2epc_T_4; // @[decode.scala:428:17, :529:40] wire _uop_is_eret_T_1 = _uop_is_eret_T == 32'h73; // @[decode.scala:530:26] wire _uop_is_eret_T_3 = _uop_is_eret_T_2 == 32'h100073; // @[decode.scala:530:44] wire _uop_is_eret_T_4 = _uop_is_eret_T_1 \| _uop_is_eret_T_3; // @[decode.scala:530:{26,36,44}] wire _uop_is_eret_T_6 = _uop_is_eret_T_5 == 32'h10200073; // @[decode.scala:530:63] wire _uop_is_eret_T_7 = _uop_is_eret_T_4 \| _uop_is_eret_T_6; // @[decode.scala:530:{36,55,63}] wire _uop_is_eret_T_9 = _uop_is_eret_T_8 == 32'h30200073; // @[decode.scala:530:80] wire _uop_is_eret_T_10 = _uop_is_eret_T_7 \| _uop_is_eret_T_9; // @[decode.scala:530:{55,72,80}] wire _uop_is_eret_T_12 = _uop_is_eret_T_11 == 32'h7B200073; // @[decode.scala:530:97] assign _uop_is_eret_T_13 = _uop_is_eret_T_10 \| _uop_is_eret_T_12; // @[decode.scala:530:{72,89,97}] assign uop_is_eret = _uop_is_eret_T_13; // @[decode.scala:428:17, :530:89] wire [6:0] _uop_is_rocc_T = uop_inst[6:0]; // @[decode.scala:428:17, :532:25] wire _uop_is_rocc_T_1 = _uop_is_rocc_T == 7'hB; // @[package.scala:16:47] wire _uop_is_rocc_T_2 = _uop_is_rocc_T == 7'h2B; // @[package.scala:16:47] wire _uop_is_rocc_T_3 = _uop_is_rocc_T == 7'h7B; // @[package.scala:16:47] wire _uop_is_rocc_T_4 = _uop_is_rocc_T_1 \| _uop_is_rocc_T_2; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_5 = _uop_is_rocc_T_4 \| _uop_is_rocc_T_3; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_7 = _uop_is_rocc_T_6 == 3'h0; // @[package.scala:16:47] wire _uop_is_rocc_T_8 = _uop_is_rocc_T_6 == 3'h2; // @[package.scala:16:47] wire _uop_is_rocc_T_9 = _uop_is_rocc_T_6 == 3'h3; // @[package.scala:16:47] wire _uop_is_rocc_T_10 = _uop_is_rocc_T_6 == 3'h4; // @[package.scala:16:47] wire _uop_is_rocc_T_11 = _uop_is_rocc_T_6 == 3'h6; // @[package.scala:16:47] wire _uop_is_rocc_T_12 = &_uop_is_rocc_T_6; // @[package.scala:16:47] wire _uop_is_rocc_T_13 = _uop_is_rocc_T_7 \| _uop_is_rocc_T_8; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_14 = _uop_is_rocc_T_13 \| _uop_is_rocc_T_9; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_15 = _uop_is_rocc_T_14 \| _uop_is_rocc_T_10; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_16 = _uop_is_rocc_T_15 \| _uop_is_rocc_T_11; // @[package.scala:16:47, :81:59] wire _uop_is_rocc_T_17 = _uop_is_rocc_T_16 \| _uop_is_rocc_T_12; // @[package.scala:16:47, :81:59] assign _uop_is_rocc_T_18 = _uop_is_rocc_T_5 & _uop_is_rocc_T_17; // @[package.scala:81:59] assign uop_is_rocc = _uop_is_rocc_T_18; // @[decode.scala:428:17, :532:81] wire _uop_flush_on_commit_T = ~csr_ren; // @[decode.scala:452:50, :465:47, :533:59] wire _uop_flush_on_commit_T_1 = csr_en & _uop_flush_on_commit_T; // @[package.scala:81:59] wire _uop_flush_on_commit_T_2 = _uop_flush_on_commit_T_1 & io_csr_decode_write_flush_0; // @[decode.scala:422:7, :533:{56,68}] assign _uop_flush_on_commit_T_3 = cs_flush_on_commit \| _uop_flush_on_commit_T_2; // @[decode.scala:447:16, :533:{45,68}] assign uop_flush_on_commit = _uop_flush_on_commit_T_3; // @[decode.scala:428:17, :533:45] wire _GEN_44 = cs_imm_sel == 3'h2; // @[package.scala:16:47] wire _di24_20_T; // @[decode.scala:540:32] assign _di24_20_T = _GEN_44; // @[decode.scala:540:32] wire _imm_i11_T_2; // @[util.scala:288:44] assign _imm_i11_T_2 = _GEN_44; // @[util.scala:288:44] wire _T_142 = cs_imm_sel == 3'h1; // @[decode.scala:447:16, :540:55] wire _di24_20_T_1; // @[decode.scala:540:55] assign _di24_20_T_1 = _T_142; // @[decode.scala:540:55] wire _imm_i0_T; // @[util.scala:291:27] assign _imm_i0_T = _T_142; // @[util.scala:291:27] wire _di24_20_T_2 = _di24_20_T \| _di24_20_T_1; // @[decode.scala:540:{32,41,55}] wire [4:0] di24_20 = _di24_20_T_2 ? _di24_20_T_3 : _di24_20_T_4; // @[decode.scala:540:{20,41,69,81}] wire [6:0] _imm_packed_T = uop_inst[31:25]; // @[decode.scala:428:17, :541:28] wire [7:0] _imm_packed_T_1 = uop_inst[19:12]; // @[decode.scala:428:17, :541:50] wire [11:0] imm_packed_hi = {_imm_packed_T, di24_20}; // @[decode.scala:540:20, :541:{23,28}] assign imm_packed = {imm_packed_hi, _imm_packed_T_1}; // @[decode.scala:541:{23,50}] assign uop_imm_packed = imm_packed; // @[decode.scala:428:17, :541:23] wire _imm_ip_T = cs_imm_sel == 3'h6; // @[util.scala:282:23] wire [19:0] imm_ip = _imm_ip_T ? 20'h0 : imm_packed; // @[util.scala:282:{17,23}] wire _imm_sign_T = imm_ip[19]; // @[util.scala:282:17, :284:18] wire imm_sign = _imm_sign_T; // @[util.scala:284:{18,37}] wire imm_hi_hi_hi = imm_sign; // @[util.scala:284:37, :294:15] wire _T_139 = cs_imm_sel == 3'h3; // @[package.scala:16:47] wire _imm_i30_20_T; // @[util.scala:285:27] assign _imm_i30_20_T = _T_139; // @[util.scala:285:27] wire _imm_i19_12_T; // @[util.scala:286:27] assign _imm_i19_12_T = _T_139; // @[util.scala:285:27, :286:27] wire _imm_i11_T; // @[util.scala:287:27] assign _imm_i11_T = _T_139; // @[util.scala:285:27, :287:27] wire _imm_i10_5_T; // @[util.scala:289:27] assign _imm_i10_5_T = _T_139; // @[util.scala:285:27, :289:27] wire _imm_i4_1_T; // @[util.scala:290:27] assign _imm_i4_1_T = _T_139; // @[util.scala:285:27, :290:27] wire [10:0] _imm_i30_20_T_1 = imm_ip[18:8]; // @[util.scala:282:17, :285:39] wire [10:0] _imm_i30_20_T_2 = _imm_i30_20_T_1; // @[util.scala:285:{39,46}] wire [10:0] imm_i30_20 = _imm_i30_20_T ? _imm_i30_20_T_2 : {11{imm_sign}}; // @[util.scala:284:37, :285:{21,27,46}] wire [10:0] imm_hi_hi_lo = imm_i30_20; // @[util.scala:285:21, :294:15] wire _GEN_45 = cs_imm_sel == 3'h4; // @[util.scala:286:44] wire _imm_i19_12_T_1; // @[util.scala:286:44] assign _imm_i19_12_T_1 = _GEN_45; // @[util.scala:286:44] wire _imm_i11_T_1; // @[util.scala:288:27] assign _imm_i11_T_1 = _GEN_45; // @[util.scala:286:44, :288:27] wire _imm_i19_12_T_2 = _imm_i19_12_T \| _imm_i19_12_T_1; // @[util.scala:286:{27,36,44}] wire [7:0] _imm_i19_12_T_3 = imm_ip[7:0]; // @[util.scala:282:17, :286:56] wire [7:0] _imm_i19_12_T_4 = _imm_i19_12_T_3; // @[util.scala:286:{56,62}] wire [7:0] imm_i19_12 = _imm_i19_12_T_2 ? _imm_i19_12_T_4 : {8{imm_sign}}; // @[util.scala:284:37, :286:{21,36,62}] wire [7:0] imm_hi_lo_hi = imm_i19_12; // @[util.scala:286:21, :294:15] wire _imm_i11_T_3 = _imm_i11_T_1 \| _imm_i11_T_2; // @[util.scala:288:{27,36,44}] wire _imm_i11_T_4 = imm_ip[8]; // @[util.scala:282:17, :288:56] wire _imm_i0_T_3 = imm_ip[8]; // @[util.scala:282:17, :288:56, :291:56] wire _imm_i11_T_5 = _imm_i11_T_4; // @[util.scala:288:{56,60}] wire _imm_i11_T_6 = _imm_i11_T_3 ? _imm_i11_T_5 : imm_sign; // @[util.scala:284:37, :288:{21,36,60}] wire imm_i11 = ~_imm_i11_T & _imm_i11_T_6; // @[util.scala:287:{21,27}, :288:21] wire imm_hi_lo_lo = imm_i11; // @[util.scala:287:21, :294:15] wire [4:0] _imm_i10_5_T_1 = imm_ip[18:14]; // @[util.scala:282:17, :289:44] wire [4:0] _imm_i10_5_T_2 = _imm_i10_5_T_1; // @[util.scala:289:{44,52}] wire [4:0] imm_i10_5 = _imm_i10_5_T ? 5'h0 : _imm_i10_5_T_2; // @[util.scala:289:{21,27,52}] wire [4:0] imm_lo_hi_hi = imm_i10_5; // @[util.scala:289:21, :294:15] wire [4:0] _imm_i4_1_T_1 = imm_ip[13:9]; // @[util.scala:282:17, :290:44] wire [4:0] _imm_i4_1_T_2 = _imm_i4_1_T_1; // @[util.scala:290:{44,51}] wire [4:0] imm_i4_1 = _imm_i4_1_T ? 5'h0 : _imm_i4_1_T_2; // @[util.scala:290:{21,27,51}] wire [4:0] imm_lo_hi_lo = imm_i4_1; // @[util.scala:290:21, :294:15] wire _imm_i0_T_1 = cs_imm_sel == 3'h0; // @[util.scala:291:44] wire _imm_i0_T_2 = _imm_i0_T \| _imm_i0_T_1; // @[util.scala:291:{27,36,44}] wire _imm_i0_T_4 = _imm_i0_T_3; // @[util.scala:291:{56,60}] wire imm_i0 = _imm_i0_T_2 & _imm_i0_T_4; // @[util.scala:291:{21,36,60}] wire imm_lo_lo = imm_i0; // @[util.scala:291:21, :294:15] wire [9:0] imm_lo_hi = {imm_lo_hi_hi, imm_lo_hi_lo}; // @[util.scala:294:15] wire [10:0] imm_lo = {imm_lo_hi, imm_lo_lo}; // @[util.scala:294:15] wire [8:0] imm_hi_lo = {imm_hi_lo_hi, imm_hi_lo_lo}; // @[util.scala:294:15] wire [11:0] imm_hi_hi = {imm_hi_hi_hi, imm_hi_hi_lo}; // @[util.scala:294:15] wire [20:0] imm_hi = {imm_hi_hi, imm_hi_lo}; // @[util.scala:294:15] wire [31:0] imm = {imm_hi, imm_lo}; // @[util.scala:294:15] wire [27:0] imm_hi_1 = imm[31:4]; // @[util.scala:294:15] wire [4:0] imm_lo_1 = imm[4:0]; // @[util.scala:294:15] wire _short_imm_T = imm_hi_1 == 28'h0; // @[pla.scala:114:36] wire [27:0] _short_imm_T_1 = ~imm_hi_1; // @[decode.scala:543:20, :545:37] wire _short_imm_T_2 = _short_imm_T_1 == 28'h0; // @[pla.scala:114:36] wire _short_imm_T_3 = _short_imm_T \| _short_imm_T_2; // @[decode.scala:545:{26,34,45}] wire _short_imm_T_4 = &cs_imm_sel; // @[decode.scala:447:16, :545:67] wire short_imm = _short_imm_T_3 \| _short_imm_T_4; // @[decode.scala:545:{34,53,67}] wire _uop_imm_rename_T = cs_imm_sel != 3'h6; // @[decode.scala:447:16, :547:32] wire _uop_imm_rename_T_1 = ~(&cs_imm_sel); // @[decode.scala:447:16, :545:67, :547:55] wire _uop_imm_rename_T_2 = _uop_imm_rename_T & _uop_imm_rename_T_1; // @[decode.scala:547:{32,41,55}] assign uop_imm_rename = ~short_imm & _uop_imm_rename_T_2; // @[decode.scala:428:17, :545:53, :547:{18,41}, :550:20, :551:20] assign uop_imm_sel = short_imm ? 3'h5 : cs_imm_sel; // @[decode.scala:428:17, :447:16, :545:53, :549:18, :550:20, :552:17] wire _uop_pimm_T = &cs_imm_sel; // @[decode.scala:447:16, :545:67, :553:32] wire [4:0] _uop_pimm_T_2 = _uop_pimm_T ? {2'h0, _uop_pimm_T_1} : imm_lo_1; // @[decode.scala:544:19, :553:{20,32,47}] assign uop_pimm = short_imm ? _uop_pimm_T_2 : 5'h0; // @[decode.scala:422:7, :426:14, :428:17, :429:7, :545:53, :550:20, :553:{14,20}] wire _uop_fp_rm_T_1 = &_uop_fp_rm_T; // @[decode.scala:556:{26,34}] assign _uop_fp_rm_T_3 = _uop_fp_rm_T_1 ? io_fcsr_rm_0 : _uop_fp_rm_T_2; // @[decode.scala:422:7, :556:{21,34,59}] assign uop_fp_rm = _uop_fp_rm_T_3; // @[decode.scala:428:17, :556:21] assign _uop_fp_typ_T = uop_inst[21:20]; // @[decode.scala:428:17, :557:22] assign uop_fp_typ = _uop_fp_typ_T; // @[decode.scala:428:17, :557:22] assign uop_csr_cmd = (_T_29 \| (&cs_csr_cmd)) & ~(\|LRS1) ? 3'h2 : cs_csr_cmd; // @[package.scala:16:47] wire [31:0] _uop_br_type_T_18 = {25'h0, _uop_is_rocc_T}; // @[decode.scala:529:48, :532:25, :572:14, :604:36] wire [9:0] _GEN_46 = {uop_inst[14:12], _uop_is_rocc_T}; // @[decode.scala:428:17, :460:24, :526:26, :532:25] wire [16:0] _GEN_47 = {_imm_packed_T, uop_inst[14:12], _uop_is_rocc_T}; // @[decode.scala:428:17, :460:24, :485:26, :532:25, :541:28] assign uop_op1_sel = _uop_is_rocc_T == 7'h37 \| _GEN_46 == 10'h2F3 \| _GEN_46 == 10'h373 \| _GEN_46 == 10'h3F3 \| uop_inst == 32'h10500073 \| uop_inst == 32'h10200073 \| uop_inst == 32'h30200073 \| uop_inst == 32'h7B200073 ? 2'h1 : _uop_is_rocc_T == 7'h6F \| _GEN_46 == 10'h67 \| _uop_is_rocc_T == 7'h17 ? 2'h2 : {2{_GEN_47 == 17'h4133 \| _GEN_47 == 17'h4233 \| _GEN_47 == 17'h4333 \| _GEN_47 == 17'h413B \| _GEN_47 == 17'h423B \| _GEN_47 == 17'h433B \| _GEN_47 == 17'h103B \| {uop_inst[31:26], uop_inst[14:12], _uop_is_rocc_T} == 16'h89B}}; // @[package.scala:81:59] wire [15:0] _GEN_48 = {uop_inst[31:26], uop_inst[14:12], _uop_is_rocc_T}; // @[decode.scala:428:17, :460:24, :532:25, :589:65] wire _uop_op2_sel_T = uop_lrs2_rtype == 2'h0; // @[decode.scala:428:17, :590:39] wire [2:0] _uop_op2_sel_T_1 = _uop_op2_sel_T ? 3'h5 : 3'h6; // @[decode.scala:590:{23,39}] assign uop_op2_sel = cs_is_amo \| _GEN_46 == 10'hF3 \| _GEN_46 == 10'h173 \| _GEN_46 == 10'h1F3 ? 3'h2 : _GEN_46 == 10'h2F3 \| _GEN_46 == 10'h373 \| _GEN_46 == 10'h3F3 \| uop_inst == 32'h10500073 \| uop_inst == 32'h10200073 \| uop_inst == 32'h7B200073 \| uop_inst == 32'h30200073 ? 3'h4 : _uop_is_rocc_T == 7'h6F \| _GEN_46 == 10'h67 ? 3'h3 : _GEN_47 == 17'h90B3 \| _GEN_48 == 16'h4893 \| _GEN_47 == 17'hD0B3 \| _GEN_48 == 16'h6893 \| _GEN_47 == 17'h50B3 \| {uop_inst[31:26], uop_inst[14:12], _uop_is_rocc_T} == 16'h2893 ? _uop_op2_sel_T_1 : {2'h0, _T_139 \| _imm_i0_T_1 \| _T_142}; // @[package.scala:16:47, :81:59] wire _uop_br_type_T_1 = _uop_br_type_T == 32'h63; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_2 = {2'h0, _uop_br_type_T_1, 1'h0}; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_4 = _uop_br_type_T_3 == 32'h1063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_5 = {3'h0, _uop_br_type_T_4}; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_7 = _uop_br_type_T_6 == 32'h5063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_8 = _uop_br_type_T_7 ? 4'h3 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_10 = _uop_br_type_T_9 == 32'h7063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_11 = {1'h0, _uop_br_type_T_10, 2'h0}; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_13 = _uop_br_type_T_12 == 32'h4063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_14 = _uop_br_type_T_13 ? 4'h5 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_16 = _uop_br_type_T_15 == 32'h6063; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_17 = _uop_br_type_T_16 ? 4'h6 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_19 = _uop_br_type_T_18 == 32'h6F; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_20 = _uop_br_type_T_19 ? 4'h7 : 4'h0; // @[decode.scala:604:{30,36}] wire _uop_br_type_T_22 = _uop_br_type_T_21 == 32'h67; // @[decode.scala:604:36] wire [3:0] _uop_br_type_T_23 = {_uop_br_type_T_22, 3'h0}; // @[decode.scala:604:{30,36}] wire [3:0] _uop_br_type_T_24 = _uop_br_type_T_2 \| _uop_br_type_T_5; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_25 = _uop_br_type_T_24 \| _uop_br_type_T_8; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_26 = _uop_br_type_T_25 \| _uop_br_type_T_11; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_27 = _uop_br_type_T_26 \| _uop_br_type_T_14; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_28 = _uop_br_type_T_27 \| _uop_br_type_T_17; // @[decode.scala:604:{30,62}] wire [3:0] _uop_br_type_T_29 = _uop_br_type_T_28 \| _uop_br_type_T_20; // @[decode.scala:604:{30,62}] assign _uop_br_type_T_30 = _uop_br_type_T_29 \| _uop_br_type_T_23; // @[decode.scala:604:{30,62}] assign uop_br_type = _uop_br_type_T_30; // @[decode.scala:428:17, :604:62] assign io_deq_uop_inst = io_deq_uop_inst_0; // @[decode.scala:422:7] assign io_deq_uop_debug_inst = io_deq_uop_debug_inst_0; // @[decode.scala:422:7] assign io_deq_uop_is_rvc = io_deq_uop_is_rvc_0; // @[decode.scala:422:7] assign io_deq_uop_debug_pc = io_deq_uop_debug_pc_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_0 = io_deq_uop_iq_type_0_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_1 = io_deq_uop_iq_type_1_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_2 = io_deq_uop_iq_type_2_0; // @[decode.scala:422:7] assign io_deq_uop_iq_type_3 = io_deq_uop_iq_type_3_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_0 = io_deq_uop_fu_code_0_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_1 = io_deq_uop_fu_code_1_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_2 = io_deq_uop_fu_code_2_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_3 = io_deq_uop_fu_code_3_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_4 = io_deq_uop_fu_code_4_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_5 = io_deq_uop_fu_code_5_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_6 = io_deq_uop_fu_code_6_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_7 = io_deq_uop_fu_code_7_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_8 = io_deq_uop_fu_code_8_0; // @[decode.scala:422:7] assign io_deq_uop_fu_code_9 = io_deq_uop_fu_code_9_0; // @[decode.scala:422:7] assign io_deq_uop_br_type = io_deq_uop_br_type_0; // @[decode.scala:422:7] assign io_deq_uop_is_sfb = io_deq_uop_is_sfb_0; // @[decode.scala:422:7] assign io_deq_uop_is_fence = io_deq_uop_is_fence_0; // @[decode.scala:422:7] assign io_deq_uop_is_fencei = io_deq_uop_is_fencei_0; // @[decode.scala:422:7] assign io_deq_uop_is_sfence = io_deq_uop_is_sfence_0; // @[decode.scala:422:7] assign io_deq_uop_is_amo = io_deq_uop_is_amo_0; // @[decode.scala:422:7] assign io_deq_uop_is_eret = io_deq_uop_is_eret_0; // @[decode.scala:422:7] assign io_deq_uop_is_sys_pc2epc = io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:422:7] assign io_deq_uop_is_rocc = io_deq_uop_is_rocc_0; // @[decode.scala:422:7] assign io_deq_uop_is_mov = io_deq_uop_is_mov_0; // @[decode.scala:422:7] assign io_deq_uop_ftq_idx = io_deq_uop_ftq_idx_0; // @[decode.scala:422:7] assign io_deq_uop_edge_inst = io_deq_uop_edge_inst_0; // @[decode.scala:422:7] assign io_deq_uop_pc_lob = io_deq_uop_pc_lob_0; // @[decode.scala:422:7] assign io_deq_uop_taken = io_deq_uop_taken_0; // @[decode.scala:422:7] assign io_deq_uop_imm_rename = io_deq_uop_imm_rename_0; // @[decode.scala:422:7] assign io_deq_uop_imm_sel = io_deq_uop_imm_sel_0; // @[decode.scala:422:7] assign io_deq_uop_pimm = io_deq_uop_pimm_0; // @[decode.scala:422:7] assign io_deq_uop_imm_packed = io_deq_uop_imm_packed_0; // @[decode.scala:422:7] assign io_deq_uop_op1_sel = io_deq_uop_op1_sel_0; // @[decode.scala:422:7] assign io_deq_uop_op2_sel = io_deq_uop_op2_sel_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ldst = io_deq_uop_fp_ctrl_ldst_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_wen = io_deq_uop_fp_ctrl_wen_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ren1 = io_deq_uop_fp_ctrl_ren1_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ren2 = io_deq_uop_fp_ctrl_ren2_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_ren3 = io_deq_uop_fp_ctrl_ren3_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_swap12 = io_deq_uop_fp_ctrl_swap12_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_swap23 = io_deq_uop_fp_ctrl_swap23_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_typeTagIn = io_deq_uop_fp_ctrl_typeTagIn_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_typeTagOut = io_deq_uop_fp_ctrl_typeTagOut_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_fromint = io_deq_uop_fp_ctrl_fromint_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_toint = io_deq_uop_fp_ctrl_toint_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_fastpipe = io_deq_uop_fp_ctrl_fastpipe_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_fma = io_deq_uop_fp_ctrl_fma_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_div = io_deq_uop_fp_ctrl_div_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_sqrt = io_deq_uop_fp_ctrl_sqrt_0; // @[decode.scala:422:7] assign io_deq_uop_fp_ctrl_wflags = io_deq_uop_fp_ctrl_wflags_0; // @[decode.scala:422:7] assign io_deq_uop_exception = io_deq_uop_exception_0; // @[decode.scala:422:7] assign io_deq_uop_exc_cause = io_deq_uop_exc_cause_0; // @[decode.scala:422:7] assign io_deq_uop_mem_cmd = io_deq_uop_mem_cmd_0; // @[decode.scala:422:7] assign io_deq_uop_mem_size = io_deq_uop_mem_size_0; // @[decode.scala:422:7] assign io_deq_uop_mem_signed = io_deq_uop_mem_signed_0; // @[decode.scala:422:7] assign io_deq_uop_uses_ldq = io_deq_uop_uses_ldq_0; // @[decode.scala:422:7] assign io_deq_uop_uses_stq = io_deq_uop_uses_stq_0; // @[decode.scala:422:7] assign io_deq_uop_is_unique = io_deq_uop_is_unique_0; // @[decode.scala:422:7] assign io_deq_uop_flush_on_commit = io_deq_uop_flush_on_commit_0; // @[decode.scala:422:7] assign io_deq_uop_csr_cmd = io_deq_uop_csr_cmd_0; // @[decode.scala:422:7] assign io_deq_uop_ldst_is_rs1 = io_deq_uop_ldst_is_rs1_0; // @[decode.scala:422:7] assign io_deq_uop_ldst = io_deq_uop_ldst_0; // @[decode.scala:422:7] assign io_deq_uop_lrs1 = io_deq_uop_lrs1_0; // @[decode.scala:422:7] assign io_deq_uop_lrs2 = io_deq_uop_lrs2_0; // @[decode.scala:422:7] assign io_deq_uop_lrs3 = io_deq_uop_lrs3_0; // @[decode.scala:422:7] assign io_deq_uop_dst_rtype = io_deq_uop_dst_rtype_0; // @[decode.scala:422:7] assign io_deq_uop_lrs1_rtype = io_deq_uop_lrs1_rtype_0; // @[decode.scala:422:7] assign io_deq_uop_lrs2_rtype = io_deq_uop_lrs2_rtype_0; // @[decode.scala:422:7] assign io_deq_uop_frs3_en = io_deq_uop_frs3_en_0; // @[decode.scala:422:7] assign io_deq_uop_fcn_dw = io_deq_uop_fcn_dw_0; // @[decode.scala:422:7] assign io_deq_uop_fcn_op = io_deq_uop_fcn_op_0; // @[decode.scala:422:7] assign io_deq_uop_fp_val = io_deq_uop_fp_val_0; // @[decode.scala:422:7] assign io_deq_uop_fp_rm = io_deq_uop_fp_rm_0; // @[decode.scala:422:7] assign io_deq_uop_fp_typ = io_deq_uop_fp_typ_0; // @[decode.scala:422:7] assign io_deq_uop_xcpt_pf_if = io_deq_uop_xcpt_pf_if_0; // @[decode.scala:422:7] assign io_deq_uop_xcpt_ae_if = io_deq_uop_xcpt_ae_if_0; // @[decode.scala:422:7] assign io_deq_uop_bp_debug_if = io_deq_uop_bp_debug_if_0; // @[decode.scala:422:7] assign io_deq_uop_bp_xcpt_if = io_deq_uop_bp_xcpt_if_0; // @[decode.scala:422:7] assign io_deq_uop_debug_fsrc = io_deq_uop_debug_fsrc_0; // @[decode.scala:422:7] assign io_csr_decode_inst = io_csr_decode_inst_0; // @[decode.scala:422:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_5 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_5( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire _common_underflow_T_7 = io_detectTininess_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :222:49] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T \| _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even \| roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 \| _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} \| _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 \| _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_7 & _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:{49,77}, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T \| roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp \| roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_5 = pegMinNonzeroMagOut ? 9'h194 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [8:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [8:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [8:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 7'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [8:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [8:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_14 = pegMinNonzeroMagOut ? 9'h6B : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [8:0] _expOut_T_15 = _expOut_T_13 \| _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [8:0] _expOut_T_16 = pegMaxFiniteMagOut ? 9'h17F : 9'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [8:0] _expOut_T_17 = _expOut_T_15 \| _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] _fractOut_T_4 = {23{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [22:0] fractOut = _fractOut_T_3 \| _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_25 : input clock : Clock input reset : Reset output io : { req : { flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}}, resp : { `1` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, `0` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<13> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<4> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_andMatrixInput_6) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2, decoded_andMatrixOutputs_andMatrixInput_3) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T_1 = orr(decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_lo = cat(_decoded_orMatrixOutputs_T, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi = cat(_decoded_orMatrixOutputs_T_1, UInt<1>(0h0)) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node decoded_invMatrixOutputs_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 1, 0) node _decoded_T_1 = bits(_decoded_T, 0, 0) node _decoded_T_2 = bits(_decoded_T, 1, 1) node _decoded_T_3 = cat(_decoded_T_1, _decoded_T_2) node _decoded_T_4 = bits(decoded_plaOutput, 3, 2) node _decoded_T_5 = bits(_decoded_T_4, 0, 0) node _decoded_T_6 = bits(_decoded_T_4, 1, 1) node _decoded_T_7 = cat(_decoded_T_5, _decoded_T_6) node decoded = cat(_decoded_T_3, _decoded_T_7) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T connect io.resp.`0`.vc_sel.`1`[0], UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<13> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<4> node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_plaInput_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_8, decoded_andMatrixOutputs_andMatrixInput_9) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_1) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T_2 = orr(decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_lo_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_2) node decoded_orMatrixOutputs_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs_1, 3, 3) node decoded_invMatrixOutputs_lo_1 = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi_1 = cat(_decoded_invMatrixOutputs_T_7, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_8 = bits(decoded_plaOutput_1, 1, 0) node _decoded_T_9 = bits(_decoded_T_8, 0, 0) node _decoded_T_10 = bits(_decoded_T_8, 1, 1) node _decoded_T_11 = cat(_decoded_T_9, _decoded_T_10) node _decoded_T_12 = bits(decoded_plaOutput_1, 3, 2) node _decoded_T_13 = bits(_decoded_T_12, 0, 0) node _decoded_T_14 = bits(_decoded_T_12, 1, 1) node _decoded_T_15 = cat(_decoded_T_13, _decoded_T_14) node decoded_1 = cat(_decoded_T_11, _decoded_T_15) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T connect io.resp.`1`.vc_sel.`1`[0], UInt<1>(0h0) extmodule plusarg_reader_43 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20	module RouteComputer_25( // @[RouteComputer.scala:29:7] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_2 // @[RouteComputer.scala:40:14] ); wire [10:0] decoded_invInputs = ~{io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] assign io_resp_1_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_3 = ~(io_req_1_bits_flow_egress_node[3]); // @[pla.scala:78:21] assign io_resp_0_vc_sel_0_0 = &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[9], decoded_invInputs[10]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_0_vc_sel_0_2 = &{decoded_invInputs[0], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_37 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid \|\| io.clear \|\| io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1) node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2) node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3) node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2) node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2) node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2) node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2) node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2) node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) node _T_7 = or(_T_6, prs1_wakeups_2) node _T_8 = or(_T_7, prs1_wakeups_3) when _T_8 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_4 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T_4, _next_uop_iw_p1_speculative_child_T_2) node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_3) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<2> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_6 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_4 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T_4, _next_uop_iw_p1_bypass_hint_T_2) node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_3) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_6 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_9 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_10 = or(_T_9, prs1_rebusys_2) node _T_11 = or(_T_10, prs1_rebusys_3) node _T_12 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_13 = neq(_T_12, UInt<1>(0h0)) node _T_14 = or(_T_11, _T_13) node _T_15 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_16 = and(_T_14, _T_15) when _T_16 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_17 = or(prs2_wakeups_0, prs2_wakeups_1) node _T_18 = or(_T_17, prs2_wakeups_2) node _T_19 = or(_T_18, prs2_wakeups_3) when _T_19 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_4 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T_4, _next_uop_iw_p2_speculative_child_T_2) node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_3) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<2> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_6 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_4 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T_4, _next_uop_iw_p2_bypass_hint_T_2) node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_3) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_6 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_20 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_21 = or(_T_20, prs2_rebusys_2) node _T_22 = or(_T_21, prs2_rebusys_3) node _T_23 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_24 = neq(_T_23, UInt<1>(0h0)) node _T_25 = or(_T_22, _T_24) node _T_26 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_27 = and(_T_25, _T_26) when _T_27 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_28 = or(prs3_wakeups_0, prs3_wakeups_1) node _T_29 = or(_T_28, prs3_wakeups_2) node _T_30 = or(_T_29, prs3_wakeups_3) when _T_30 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_4 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T_4, _next_uop_iw_p3_bypass_hint_T_2) node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_3) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_6 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_31 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_32 = and(io.pred_wakeup_port.valid, _T_31) when _T_32 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_33 = eq(io.squash_grant, UInt<1>(0h0)) node _T_34 = and(io.grant, _T_33) when _T_34 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_35 = and(slot_valid, slot_uop.iw_issued) when _T_35 : connect next_valid, rebusied	module IssueSlot_37( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [1:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7] wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to this FIRRTL code module PE_411 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_155 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_411( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_155 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_1 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<2>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<2>, clock reg probes_toN : UInt<2>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_T = eq(request.source, UInt<6>(0h24)) node _req_clientBit_T_1 = eq(request.source, UInt<6>(0h20)) node req_clientBit = cat(_req_clientBit_T_1, _req_clientBit_T) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node _probe_bit_T = eq(io.sinkc.bits.source, UInt<6>(0h24)) node _probe_bit_T_1 = eq(io.sinkc.bits.source, UInt<6>(0h20)) node probe_bit = cat(_probe_bit_T_1, _probe_bit_T) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_T = eq(new_request.source, UInt<6>(0h24)) node _new_clientBit_T_1 = eq(new_request.source, UInt<6>(0h20)) node new_clientBit = cat(_new_clientBit_T_1, _new_clientBit_T) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_1( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [1:0] meta_clients; // @[MSHR.scala:100:17] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [1:0] probes_done; // @[MSHR.scala:150:24] reg [1:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire _req_clientBit_T = request_source == 6'h24; // @[Parameters.scala:46:9] wire _req_clientBit_T_1 = request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] req_clientBit = {_req_clientBit_T_1, _req_clientBit_T}; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = \|meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = \|_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire [1:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _probe_bit_T = io_sinkc_bits_source_0 == 6'h24; // @[Parameters.scala:46:9] wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9] wire [1:0] probe_bit = {_probe_bit_T_1, _probe_bit_T}; // @[Parameters.scala:46:9] wire [1:0] _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:201:10] wire [1:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [1:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire [1:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire [1:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _new_clientBit_T = new_request_source == 6'h24; // @[Parameters.scala:46:9] wire _new_clientBit_T_1 = new_request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] new_clientBit = {_new_clientBit_T_1, _new_clientBit_T}; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_18 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_32 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_18( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_32 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_196 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_196( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_54 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_71 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_54( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_71 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s2k3z4c_3 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_44 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k3z4c_1 connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k3z4c_1 connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready inst nodeIn_b_q of Queue2_TLBundleB_a32d64s2k3z4c_1 connect nodeIn_b_q.clock, clock connect nodeIn_b_q.reset, reset connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready inst nodeOut_c_q of Queue2_TLBundleC_a32d64s2k3z4c_1 connect nodeOut_c_q.clock, clock connect nodeOut_c_q.reset, reset connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready inst nodeOut_e_q of Queue2_TLBundleE_a32d64s2k3z4c_1 connect nodeOut_e_q.clock, clock connect nodeOut_e_q.reset, reset connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready	module TLBuffer_a32d64s2k3z4c_3( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9] wire [63:0] auto_out_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_44 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s2k3z4c_1 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s2k3z4c_1 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d64s2k3z4c_1 nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d64s2k3z4c_1 nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d64s2k3z4c_1 nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_7 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_7( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_68 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _source_ok_T_2 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 connect _source_ok_WIRE[2], _source_ok_T_2 node _source_ok_T_3 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_3, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_23 = cvt(_T_22) node _T_24 = and(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = asSInt(_T_24) node _T_26 = eq(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = or(_T_21, _T_26) node _T_28 = and(_T_11, _T_19) node _T_29 = and(_T_28, _T_27) node _T_30 = asUInt(reset) node _T_31 = eq(_T_30, UInt<1>(0h0)) when _T_31 : node _T_32 = eq(_T_29, UInt<1>(0h0)) when _T_32 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_29, UInt<1>(0h1), "") : assert_1 node _T_33 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_33 : node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_38 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_40 = or(_T_37, _T_38) node _T_41 = or(_T_40, _T_39) node _T_42 = and(_T_36, _T_41) node _T_43 = or(UInt<1>(0h0), _T_42) node _T_44 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<14>(0h2000))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<13>(0h1000))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<17>(0h10000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<18>(0h2f000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<13>(0h1000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<27>(0h4000000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = or(_T_49, _T_54) node _T_86 = or(_T_85, _T_59) node _T_87 = or(_T_86, _T_64) node _T_88 = or(_T_87, _T_69) node _T_89 = or(_T_88, _T_74) node _T_90 = or(_T_89, _T_79) node _T_91 = or(_T_90, _T_84) node _T_92 = and(_T_44, _T_91) node _T_93 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<29>(0h10000000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = and(_T_94, _T_105) node _T_107 = or(UInt<1>(0h0), _T_92) node _T_108 = or(_T_107, _T_106) node _T_109 = and(_T_43, _T_108) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_109, UInt<1>(0h1), "") : assert_2 node _T_113 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_115 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_113 connect _WIRE[1], _T_114 connect _WIRE[2], _T_115 node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0)) node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_119 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_120 = or(_T_117, _T_118) node _T_121 = or(_T_120, _T_119) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_121 node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_124 = and(_T_122, _T_123) node _T_125 = or(UInt<1>(0h0), _T_124) node _T_126 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<14>(0h2000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<18>(0h2f000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<17>(0h10000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<29>(0h10000000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = or(_T_130, _T_135) node _T_177 = or(_T_176, _T_140) node _T_178 = or(_T_177, _T_145) node _T_179 = or(_T_178, _T_150) node _T_180 = or(_T_179, _T_155) node _T_181 = or(_T_180, _T_160) node _T_182 = or(_T_181, _T_165) node _T_183 = or(_T_182, _T_170) node _T_184 = or(_T_183, _T_175) node _T_185 = and(_T_125, _T_184) node _T_186 = or(UInt<1>(0h0), _T_185) node _T_187 = and(_WIRE_1, _T_186) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_187, UInt<1>(0h1), "") : assert_3 node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(source_ok, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_194 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_194, UInt<1>(0h1), "") : assert_5 node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(is_aligned, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_201 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_201, UInt<1>(0h1), "") : assert_7 node _T_205 = not(io.in.a.bits.mask) node _T_206 = eq(_T_205, UInt<1>(0h0)) node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_T_206, UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_206, UInt<1>(0h1), "") : assert_8 node _T_210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_211 = asUInt(reset) node _T_212 = eq(_T_211, UInt<1>(0h0)) when _T_212 : node _T_213 = eq(_T_210, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_210, UInt<1>(0h1), "") : assert_9 node _T_214 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_214 : node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_219 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_220 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_221 = or(_T_218, _T_219) node _T_222 = or(_T_221, _T_220) node _T_223 = and(_T_217, _T_222) node _T_224 = or(UInt<1>(0h0), _T_223) node _T_225 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<14>(0h2000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<17>(0h10000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<18>(0h2f000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<27>(0h4000000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<13>(0h1000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_230, _T_235) node _T_267 = or(_T_266, _T_240) node _T_268 = or(_T_267, _T_245) node _T_269 = or(_T_268, _T_250) node _T_270 = or(_T_269, _T_255) node _T_271 = or(_T_270, _T_260) node _T_272 = or(_T_271, _T_265) node _T_273 = and(_T_225, _T_272) node _T_274 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<17>(0h10000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<29>(0h10000000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_280, _T_285) node _T_287 = and(_T_275, _T_286) node _T_288 = or(UInt<1>(0h0), _T_273) node _T_289 = or(_T_288, _T_287) node _T_290 = and(_T_224, _T_289) node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(_T_290, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_290, UInt<1>(0h1), "") : assert_10 node _T_294 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_295 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_296 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_294 connect _WIRE_2[1], _T_295 connect _WIRE_2[2], _T_296 node _T_297 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_298 = mux(_WIRE_2[0], _T_297, UInt<1>(0h0)) node _T_299 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_300 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_301 = or(_T_298, _T_299) node _T_302 = or(_T_301, _T_300) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_302 node _T_303 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_304 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_305 = and(_T_303, _T_304) node _T_306 = or(UInt<1>(0h0), _T_305) node _T_307 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_308 = cvt(_T_307) node _T_309 = and(_T_308, asSInt(UInt<14>(0h2000))) node _T_310 = asSInt(_T_309) node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0))) node _T_312 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_313 = cvt(_T_312) node _T_314 = and(_T_313, asSInt(UInt<13>(0h1000))) node _T_315 = asSInt(_T_314) node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_318 = cvt(_T_317) node _T_319 = and(_T_318, asSInt(UInt<17>(0h10000))) node _T_320 = asSInt(_T_319) node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0))) node _T_322 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<18>(0h2f000))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_328 = cvt(_T_327) node _T_329 = and(_T_328, asSInt(UInt<17>(0h10000))) node _T_330 = asSInt(_T_329) node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0))) node _T_332 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<17>(0h10000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<27>(0h4000000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<13>(0h1000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<29>(0h10000000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = or(_T_311, _T_316) node _T_358 = or(_T_357, _T_321) node _T_359 = or(_T_358, _T_326) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_336) node _T_362 = or(_T_361, _T_341) node _T_363 = or(_T_362, _T_346) node _T_364 = or(_T_363, _T_351) node _T_365 = or(_T_364, _T_356) node _T_366 = and(_T_306, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_WIRE_3, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_368, UInt<1>(0h1), "") : assert_11 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(source_ok, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_375 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_375, UInt<1>(0h1), "") : assert_13 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(is_aligned, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_382 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_382, UInt<1>(0h1), "") : assert_15 node _T_386 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_386, UInt<1>(0h1), "") : assert_16 node _T_390 = not(io.in.a.bits.mask) node _T_391 = eq(_T_390, UInt<1>(0h0)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_391, UInt<1>(0h1), "") : assert_17 node _T_395 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_395, UInt<1>(0h1), "") : assert_18 node _T_399 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_399 : node _T_400 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_401 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_404 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_405 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_406 = or(_T_403, _T_404) node _T_407 = or(_T_406, _T_405) node _T_408 = and(_T_402, _T_407) node _T_409 = or(UInt<1>(0h0), _T_408) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_409, UInt<1>(0h1), "") : assert_19 node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_415 = and(_T_413, _T_414) node _T_416 = or(UInt<1>(0h0), _T_415) node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = and(_T_416, _T_421) node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_425 = and(_T_423, _T_424) node _T_426 = or(UInt<1>(0h0), _T_425) node _T_427 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<14>(0h2000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_433 = cvt(_T_432) node _T_434 = and(_T_433, asSInt(UInt<17>(0h10000))) node _T_435 = asSInt(_T_434) node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0))) node _T_437 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_438 = cvt(_T_437) node _T_439 = and(_T_438, asSInt(UInt<18>(0h2f000))) node _T_440 = asSInt(_T_439) node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0))) node _T_442 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_443 = cvt(_T_442) node _T_444 = and(_T_443, asSInt(UInt<17>(0h10000))) node _T_445 = asSInt(_T_444) node _T_446 = eq(_T_445, asSInt(UInt<1>(0h0))) node _T_447 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_453 = cvt(_T_452) node _T_454 = and(_T_453, asSInt(UInt<17>(0h10000))) node _T_455 = asSInt(_T_454) node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0))) node _T_457 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<27>(0h4000000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<29>(0h10000000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = or(_T_431, _T_436) node _T_473 = or(_T_472, _T_441) node _T_474 = or(_T_473, _T_446) node _T_475 = or(_T_474, _T_451) node _T_476 = or(_T_475, _T_456) node _T_477 = or(_T_476, _T_461) node _T_478 = or(_T_477, _T_466) node _T_479 = or(_T_478, _T_471) node _T_480 = and(_T_426, _T_479) node _T_481 = or(UInt<1>(0h0), _T_422) node _T_482 = or(_T_481, _T_480) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_482, UInt<1>(0h1), "") : assert_20 node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(source_ok, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(is_aligned, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_492 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_492, UInt<1>(0h1), "") : assert_23 node _T_496 = eq(io.in.a.bits.mask, mask) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_496, UInt<1>(0h1), "") : assert_24 node _T_500 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_500, UInt<1>(0h1), "") : assert_25 node _T_504 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_504 : node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_509 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_510 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_511 = or(_T_508, _T_509) node _T_512 = or(_T_511, _T_510) node _T_513 = and(_T_507, _T_512) node _T_514 = or(UInt<1>(0h0), _T_513) node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_516 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_517 = and(_T_515, _T_516) node _T_518 = or(UInt<1>(0h0), _T_517) node _T_519 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = and(_T_518, _T_523) node _T_525 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_526 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_527 = and(_T_525, _T_526) node _T_528 = or(UInt<1>(0h0), _T_527) node _T_529 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<14>(0h2000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<18>(0h2f000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<17>(0h10000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<17>(0h10000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<27>(0h4000000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<29>(0h10000000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = or(_T_533, _T_538) node _T_570 = or(_T_569, _T_543) node _T_571 = or(_T_570, _T_548) node _T_572 = or(_T_571, _T_553) node _T_573 = or(_T_572, _T_558) node _T_574 = or(_T_573, _T_563) node _T_575 = or(_T_574, _T_568) node _T_576 = and(_T_528, _T_575) node _T_577 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_578 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<17>(0h10000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = and(_T_577, _T_582) node _T_584 = or(UInt<1>(0h0), _T_524) node _T_585 = or(_T_584, _T_576) node _T_586 = or(_T_585, _T_583) node _T_587 = and(_T_514, _T_586) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_587, UInt<1>(0h1), "") : assert_26 node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(source_ok, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(is_aligned, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_597 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_597, UInt<1>(0h1), "") : assert_29 node _T_601 = eq(io.in.a.bits.mask, mask) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_601, UInt<1>(0h1), "") : assert_30 node _T_605 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_605 : node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_607 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_608 = and(_T_606, _T_607) node _T_609 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_610 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_611 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_612 = or(_T_609, _T_610) node _T_613 = or(_T_612, _T_611) node _T_614 = and(_T_608, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<27>(0h4000000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<29>(0h10000000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = or(_T_634, _T_639) node _T_671 = or(_T_670, _T_644) node _T_672 = or(_T_671, _T_649) node _T_673 = or(_T_672, _T_654) node _T_674 = or(_T_673, _T_659) node _T_675 = or(_T_674, _T_664) node _T_676 = or(_T_675, _T_669) node _T_677 = and(_T_629, _T_676) node _T_678 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_679 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_680 = cvt(_T_679) node _T_681 = and(_T_680, asSInt(UInt<17>(0h10000))) node _T_682 = asSInt(_T_681) node _T_683 = eq(_T_682, asSInt(UInt<1>(0h0))) node _T_684 = and(_T_678, _T_683) node _T_685 = or(UInt<1>(0h0), _T_625) node _T_686 = or(_T_685, _T_677) node _T_687 = or(_T_686, _T_684) node _T_688 = and(_T_615, _T_687) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_688, UInt<1>(0h1), "") : assert_31 node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(source_ok, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(is_aligned, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_698, UInt<1>(0h1), "") : assert_34 node _T_702 = not(mask) node _T_703 = and(io.in.a.bits.mask, _T_702) node _T_704 = eq(_T_703, UInt<1>(0h0)) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_704, UInt<1>(0h1), "") : assert_35 node _T_708 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_708 : node _T_709 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_710 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_711 = and(_T_709, _T_710) node _T_712 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_713 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_714 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_715 = or(_T_712, _T_713) node _T_716 = or(_T_715, _T_714) node _T_717 = and(_T_711, _T_716) node _T_718 = or(UInt<1>(0h0), _T_717) node _T_719 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_720 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_721 = and(_T_719, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<14>(0h2000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<18>(0h2f000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_749 = cvt(_T_748) node _T_750 = and(_T_749, asSInt(UInt<17>(0h10000))) node _T_751 = asSInt(_T_750) node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0))) node _T_753 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<27>(0h4000000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_759 = cvt(_T_758) node _T_760 = and(_T_759, asSInt(UInt<13>(0h1000))) node _T_761 = asSInt(_T_760) node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0))) node _T_763 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_764 = cvt(_T_763) node _T_765 = and(_T_764, asSInt(UInt<29>(0h10000000))) node _T_766 = asSInt(_T_765) node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0))) node _T_768 = or(_T_727, _T_732) node _T_769 = or(_T_768, _T_737) node _T_770 = or(_T_769, _T_742) node _T_771 = or(_T_770, _T_747) node _T_772 = or(_T_771, _T_752) node _T_773 = or(_T_772, _T_757) node _T_774 = or(_T_773, _T_762) node _T_775 = or(_T_774, _T_767) node _T_776 = and(_T_722, _T_775) node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_778 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<17>(0h10000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = and(_T_777, _T_782) node _T_784 = or(UInt<1>(0h0), _T_776) node _T_785 = or(_T_784, _T_783) node _T_786 = and(_T_718, _T_785) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_786, UInt<1>(0h1), "") : assert_36 node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(source_ok, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(is_aligned, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_796 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_796, UInt<1>(0h1), "") : assert_39 node _T_800 = eq(io.in.a.bits.mask, mask) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_800, UInt<1>(0h1), "") : assert_40 node _T_804 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_809 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_810 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_811 = or(_T_808, _T_809) node _T_812 = or(_T_811, _T_810) node _T_813 = and(_T_807, _T_812) node _T_814 = or(UInt<1>(0h0), _T_813) node _T_815 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_816 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_817 = and(_T_815, _T_816) node _T_818 = or(UInt<1>(0h0), _T_817) node _T_819 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_820 = cvt(_T_819) node _T_821 = and(_T_820, asSInt(UInt<14>(0h2000))) node _T_822 = asSInt(_T_821) node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0))) node _T_824 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<13>(0h1000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<18>(0h2f000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<17>(0h10000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<13>(0h1000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<27>(0h4000000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<29>(0h10000000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = or(_T_823, _T_828) node _T_865 = or(_T_864, _T_833) node _T_866 = or(_T_865, _T_838) node _T_867 = or(_T_866, _T_843) node _T_868 = or(_T_867, _T_848) node _T_869 = or(_T_868, _T_853) node _T_870 = or(_T_869, _T_858) node _T_871 = or(_T_870, _T_863) node _T_872 = and(_T_818, _T_871) node _T_873 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_874 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<17>(0h10000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = and(_T_873, _T_878) node _T_880 = or(UInt<1>(0h0), _T_872) node _T_881 = or(_T_880, _T_879) node _T_882 = and(_T_814, _T_881) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_882, UInt<1>(0h1), "") : assert_41 node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(source_ok, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(is_aligned, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_892 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_892, UInt<1>(0h1), "") : assert_44 node _T_896 = eq(io.in.a.bits.mask, mask) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_896, UInt<1>(0h1), "") : assert_45 node _T_900 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_900 : node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_903 = and(_T_901, _T_902) node _T_904 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_905 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_906 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_907 = or(_T_904, _T_905) node _T_908 = or(_T_907, _T_906) node _T_909 = and(_T_903, _T_908) node _T_910 = or(UInt<1>(0h0), _T_909) node _T_911 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_912 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_913 = and(_T_911, _T_912) node _T_914 = or(UInt<1>(0h0), _T_913) node _T_915 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<13>(0h1000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = and(_T_914, _T_919) node _T_921 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_923 = cvt(_T_922) node _T_924 = and(_T_923, asSInt(UInt<14>(0h2000))) node _T_925 = asSInt(_T_924) node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0))) node _T_927 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<17>(0h10000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_933 = cvt(_T_932) node _T_934 = and(_T_933, asSInt(UInt<18>(0h2f000))) node _T_935 = asSInt(_T_934) node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0))) node _T_937 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_938 = cvt(_T_937) node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000))) node _T_940 = asSInt(_T_939) node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0))) node _T_942 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<13>(0h1000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_948 = cvt(_T_947) node _T_949 = and(_T_948, asSInt(UInt<27>(0h4000000))) node _T_950 = asSInt(_T_949) node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0))) node _T_952 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_953 = cvt(_T_952) node _T_954 = and(_T_953, asSInt(UInt<13>(0h1000))) node _T_955 = asSInt(_T_954) node _T_956 = eq(_T_955, asSInt(UInt<1>(0h0))) node _T_957 = or(_T_926, _T_931) node _T_958 = or(_T_957, _T_936) node _T_959 = or(_T_958, _T_941) node _T_960 = or(_T_959, _T_946) node _T_961 = or(_T_960, _T_951) node _T_962 = or(_T_961, _T_956) node _T_963 = and(_T_921, _T_962) node _T_964 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_965 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_966 = and(_T_964, _T_965) node _T_967 = or(UInt<1>(0h0), _T_966) node _T_968 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_969 = cvt(_T_968) node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000))) node _T_971 = asSInt(_T_970) node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0))) node _T_973 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_974 = cvt(_T_973) node _T_975 = and(_T_974, asSInt(UInt<29>(0h10000000))) node _T_976 = asSInt(_T_975) node _T_977 = eq(_T_976, asSInt(UInt<1>(0h0))) node _T_978 = or(_T_972, _T_977) node _T_979 = and(_T_967, _T_978) node _T_980 = or(UInt<1>(0h0), _T_920) node _T_981 = or(_T_980, _T_963) node _T_982 = or(_T_981, _T_979) node _T_983 = and(_T_910, _T_982) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_983, UInt<1>(0h1), "") : assert_46 node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(source_ok, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(is_aligned, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_993 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_993, UInt<1>(0h1), "") : assert_49 node _T_997 = eq(io.in.a.bits.mask, mask) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_997, UInt<1>(0h1), "") : assert_50 node _T_1001 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1005 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_52 node _source_ok_T_4 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.d.bits.source, UInt<1>(0h1)) node _source_ok_T_6 = eq(io.in.d.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_4 connect _source_ok_WIRE_1[1], _source_ok_T_5 connect _source_ok_WIRE_1[2], _source_ok_T_6 node _source_ok_T_7 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_7, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1009 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1009 : node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(source_ok_1, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_54 node _T_1017 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_55 node _T_1021 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_56 node _T_1025 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_57 node _T_1029 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1029 : node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(source_ok_1, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(sink_ok, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1036 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_60 node _T_1040 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_61 node _T_1044 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_62 node _T_1048 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_63 node _T_1052 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1053 = or(UInt<1>(0h1), _T_1052) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_64 node _T_1057 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1057 : node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(source_ok_1, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(sink_ok, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1064 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_67 node _T_1068 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_68 node _T_1072 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_69 node _T_1076 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1077 = or(_T_1076, io.in.d.bits.corrupt) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_70 node _T_1081 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1082 = or(UInt<1>(0h1), _T_1081) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_71 node _T_1086 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1086 : node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(source_ok_1, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1090 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_73 node _T_1094 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_74 node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1099 = or(UInt<1>(0h1), _T_1098) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_75 node _T_1103 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1103 : node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(source_ok_1, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1107 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_T_1107, UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1107, UInt<1>(0h1), "") : assert_77 node _T_1111 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1112 = or(_T_1111, io.in.d.bits.corrupt) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_78 node _T_1116 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1117 = or(UInt<1>(0h1), _T_1116) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_79 node _T_1121 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1121 : node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(source_ok_1, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1125 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_81 node _T_1129 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_82 node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1134 = or(UInt<1>(0h1), _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1138 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_84 node _T_1142 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) node _T_1144 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = or(_T_1143, _T_1148) node _T_1150 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<1>(0h0))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = or(_T_1151, _T_1156) node _T_1158 = eq(io.in.b.bits.source, UInt<2>(0h2)) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) node _T_1160 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1161 = cvt(_T_1160) node _T_1162 = and(_T_1161, asSInt(UInt<1>(0h0))) node _T_1163 = asSInt(_T_1162) node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0))) node _T_1165 = or(_T_1159, _T_1164) node _T_1166 = and(_T_1149, _T_1157) node _T_1167 = and(_T_1166, _T_1165) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _legal_source_T_2 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 connect _legal_source_WIRE[2], _legal_source_T_2 node _legal_source_T_3 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_4 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_5 = mux(_legal_source_WIRE[2], UInt<2>(0h2), UInt<1>(0h0)) node _legal_source_T_6 = or(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_7 = or(_legal_source_T_6, _legal_source_T_5) wire _legal_source_WIRE_1 : UInt<2> connect _legal_source_WIRE_1, _legal_source_T_7 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1171 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1171 : node _T_1172 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1173 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1174 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1172 connect _WIRE_4[1], _T_1173 connect _WIRE_4[2], _T_1174 node _T_1175 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1176 = mux(_WIRE_4[0], _T_1175, UInt<1>(0h0)) node _T_1177 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1178 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1179 = or(_T_1176, _T_1177) node _T_1180 = or(_T_1179, _T_1178) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1180 node _T_1181 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1182 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1183 = and(_T_1181, _T_1182) node _T_1184 = or(UInt<1>(0h0), _T_1183) node _T_1185 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1186 = cvt(_T_1185) node _T_1187 = and(_T_1186, asSInt(UInt<14>(0h2000))) node _T_1188 = asSInt(_T_1187) node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0))) node _T_1190 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1191 = cvt(_T_1190) node _T_1192 = and(_T_1191, asSInt(UInt<13>(0h1000))) node _T_1193 = asSInt(_T_1192) node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1196 = cvt(_T_1195) node _T_1197 = and(_T_1196, asSInt(UInt<17>(0h10000))) node _T_1198 = asSInt(_T_1197) node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0))) node _T_1200 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1201 = cvt(_T_1200) node _T_1202 = and(_T_1201, asSInt(UInt<18>(0h2f000))) node _T_1203 = asSInt(_T_1202) node _T_1204 = eq(_T_1203, asSInt(UInt<1>(0h0))) node _T_1205 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1206 = cvt(_T_1205) node _T_1207 = and(_T_1206, asSInt(UInt<17>(0h10000))) node _T_1208 = asSInt(_T_1207) node _T_1209 = eq(_T_1208, asSInt(UInt<1>(0h0))) node _T_1210 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1211 = cvt(_T_1210) node _T_1212 = and(_T_1211, asSInt(UInt<13>(0h1000))) node _T_1213 = asSInt(_T_1212) node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1216 = cvt(_T_1215) node _T_1217 = and(_T_1216, asSInt(UInt<17>(0h10000))) node _T_1218 = asSInt(_T_1217) node _T_1219 = eq(_T_1218, asSInt(UInt<1>(0h0))) node _T_1220 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<27>(0h4000000))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1226 = cvt(_T_1225) node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000))) node _T_1228 = asSInt(_T_1227) node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0))) node _T_1230 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<29>(0h10000000))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = or(_T_1189, _T_1194) node _T_1236 = or(_T_1235, _T_1199) node _T_1237 = or(_T_1236, _T_1204) node _T_1238 = or(_T_1237, _T_1209) node _T_1239 = or(_T_1238, _T_1214) node _T_1240 = or(_T_1239, _T_1219) node _T_1241 = or(_T_1240, _T_1224) node _T_1242 = or(_T_1241, _T_1229) node _T_1243 = or(_T_1242, _T_1234) node _T_1244 = and(_T_1184, _T_1243) node _T_1245 = or(UInt<1>(0h0), _T_1244) node _T_1246 = and(_WIRE_5, _T_1245) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_86 node _T_1250 = asUInt(reset) node _T_1251 = eq(_T_1250, UInt<1>(0h0)) when _T_1251 : node _T_1252 = eq(address_ok, UInt<1>(0h0)) when _T_1252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(legal_source, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1259 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_90 node _T_1263 = eq(io.in.b.bits.mask, mask_1) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_91 node _T_1267 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1268 = asUInt(reset) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) when _T_1269 : node _T_1270 = eq(_T_1267, UInt<1>(0h0)) when _T_1270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1267, UInt<1>(0h1), "") : assert_92 node _T_1271 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1271 : node _T_1272 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1273 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1274 = and(_T_1272, _T_1273) node _T_1275 = or(UInt<1>(0h0), _T_1274) node _T_1276 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1277 = cvt(_T_1276) node _T_1278 = and(_T_1277, asSInt(UInt<14>(0h2000))) node _T_1279 = asSInt(_T_1278) node _T_1280 = eq(_T_1279, asSInt(UInt<1>(0h0))) node _T_1281 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1282 = cvt(_T_1281) node _T_1283 = and(_T_1282, asSInt(UInt<13>(0h1000))) node _T_1284 = asSInt(_T_1283) node _T_1285 = eq(_T_1284, asSInt(UInt<1>(0h0))) node _T_1286 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1287 = cvt(_T_1286) node _T_1288 = and(_T_1287, asSInt(UInt<17>(0h10000))) node _T_1289 = asSInt(_T_1288) node _T_1290 = eq(_T_1289, asSInt(UInt<1>(0h0))) node _T_1291 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1292 = cvt(_T_1291) node _T_1293 = and(_T_1292, asSInt(UInt<18>(0h2f000))) node _T_1294 = asSInt(_T_1293) node _T_1295 = eq(_T_1294, asSInt(UInt<1>(0h0))) node _T_1296 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1297 = cvt(_T_1296) node _T_1298 = and(_T_1297, asSInt(UInt<17>(0h10000))) node _T_1299 = asSInt(_T_1298) node _T_1300 = eq(_T_1299, asSInt(UInt<1>(0h0))) node _T_1301 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1302 = cvt(_T_1301) node _T_1303 = and(_T_1302, asSInt(UInt<13>(0h1000))) node _T_1304 = asSInt(_T_1303) node _T_1305 = eq(_T_1304, asSInt(UInt<1>(0h0))) node _T_1306 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1307 = cvt(_T_1306) node _T_1308 = and(_T_1307, asSInt(UInt<17>(0h10000))) node _T_1309 = asSInt(_T_1308) node _T_1310 = eq(_T_1309, asSInt(UInt<1>(0h0))) node _T_1311 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1312 = cvt(_T_1311) node _T_1313 = and(_T_1312, asSInt(UInt<27>(0h4000000))) node _T_1314 = asSInt(_T_1313) node _T_1315 = eq(_T_1314, asSInt(UInt<1>(0h0))) node _T_1316 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1317 = cvt(_T_1316) node _T_1318 = and(_T_1317, asSInt(UInt<13>(0h1000))) node _T_1319 = asSInt(_T_1318) node _T_1320 = eq(_T_1319, asSInt(UInt<1>(0h0))) node _T_1321 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1322 = cvt(_T_1321) node _T_1323 = and(_T_1322, asSInt(UInt<29>(0h10000000))) node _T_1324 = asSInt(_T_1323) node _T_1325 = eq(_T_1324, asSInt(UInt<1>(0h0))) node _T_1326 = or(_T_1280, _T_1285) node _T_1327 = or(_T_1326, _T_1290) node _T_1328 = or(_T_1327, _T_1295) node _T_1329 = or(_T_1328, _T_1300) node _T_1330 = or(_T_1329, _T_1305) node _T_1331 = or(_T_1330, _T_1310) node _T_1332 = or(_T_1331, _T_1315) node _T_1333 = or(_T_1332, _T_1320) node _T_1334 = or(_T_1333, _T_1325) node _T_1335 = and(_T_1275, _T_1334) node _T_1336 = or(UInt<1>(0h0), _T_1335) node _T_1337 = and(UInt<1>(0h0), _T_1336) node _T_1338 = asUInt(reset) node _T_1339 = eq(_T_1338, UInt<1>(0h0)) when _T_1339 : node _T_1340 = eq(_T_1337, UInt<1>(0h0)) when _T_1340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1337, UInt<1>(0h1), "") : assert_93 node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(address_ok, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(legal_source, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1350 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_97 node _T_1354 = eq(io.in.b.bits.mask, mask_1) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_98 node _T_1358 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_99 node _T_1362 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1362 : node _T_1363 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1364 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1365 = and(_T_1363, _T_1364) node _T_1366 = or(UInt<1>(0h0), _T_1365) node _T_1367 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1368 = cvt(_T_1367) node _T_1369 = and(_T_1368, asSInt(UInt<14>(0h2000))) node _T_1370 = asSInt(_T_1369) node _T_1371 = eq(_T_1370, asSInt(UInt<1>(0h0))) node _T_1372 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1373 = cvt(_T_1372) node _T_1374 = and(_T_1373, asSInt(UInt<13>(0h1000))) node _T_1375 = asSInt(_T_1374) node _T_1376 = eq(_T_1375, asSInt(UInt<1>(0h0))) node _T_1377 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1378 = cvt(_T_1377) node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h10000))) node _T_1380 = asSInt(_T_1379) node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0))) node _T_1382 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1383 = cvt(_T_1382) node _T_1384 = and(_T_1383, asSInt(UInt<18>(0h2f000))) node _T_1385 = asSInt(_T_1384) node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0))) node _T_1387 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1388 = cvt(_T_1387) node _T_1389 = and(_T_1388, asSInt(UInt<17>(0h10000))) node _T_1390 = asSInt(_T_1389) node _T_1391 = eq(_T_1390, asSInt(UInt<1>(0h0))) node _T_1392 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1393 = cvt(_T_1392) node _T_1394 = and(_T_1393, asSInt(UInt<13>(0h1000))) node _T_1395 = asSInt(_T_1394) node _T_1396 = eq(_T_1395, asSInt(UInt<1>(0h0))) node _T_1397 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1398 = cvt(_T_1397) node _T_1399 = and(_T_1398, asSInt(UInt<17>(0h10000))) node _T_1400 = asSInt(_T_1399) node _T_1401 = eq(_T_1400, asSInt(UInt<1>(0h0))) node _T_1402 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1403 = cvt(_T_1402) node _T_1404 = and(_T_1403, asSInt(UInt<27>(0h4000000))) node _T_1405 = asSInt(_T_1404) node _T_1406 = eq(_T_1405, asSInt(UInt<1>(0h0))) node _T_1407 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1408 = cvt(_T_1407) node _T_1409 = and(_T_1408, asSInt(UInt<13>(0h1000))) node _T_1410 = asSInt(_T_1409) node _T_1411 = eq(_T_1410, asSInt(UInt<1>(0h0))) node _T_1412 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1413 = cvt(_T_1412) node _T_1414 = and(_T_1413, asSInt(UInt<29>(0h10000000))) node _T_1415 = asSInt(_T_1414) node _T_1416 = eq(_T_1415, asSInt(UInt<1>(0h0))) node _T_1417 = or(_T_1371, _T_1376) node _T_1418 = or(_T_1417, _T_1381) node _T_1419 = or(_T_1418, _T_1386) node _T_1420 = or(_T_1419, _T_1391) node _T_1421 = or(_T_1420, _T_1396) node _T_1422 = or(_T_1421, _T_1401) node _T_1423 = or(_T_1422, _T_1406) node _T_1424 = or(_T_1423, _T_1411) node _T_1425 = or(_T_1424, _T_1416) node _T_1426 = and(_T_1366, _T_1425) node _T_1427 = or(UInt<1>(0h0), _T_1426) node _T_1428 = and(UInt<1>(0h0), _T_1427) node _T_1429 = asUInt(reset) node _T_1430 = eq(_T_1429, UInt<1>(0h0)) when _T_1430 : node _T_1431 = eq(_T_1428, UInt<1>(0h0)) when _T_1431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1428, UInt<1>(0h1), "") : assert_100 node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(address_ok, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1435 = asUInt(reset) node _T_1436 = eq(_T_1435, UInt<1>(0h0)) when _T_1436 : node _T_1437 = eq(legal_source, UInt<1>(0h0)) when _T_1437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1438 = asUInt(reset) node _T_1439 = eq(_T_1438, UInt<1>(0h0)) when _T_1439 : node _T_1440 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1441 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_104 node _T_1445 = eq(io.in.b.bits.mask, mask_1) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_105 node _T_1449 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1449 : node _T_1450 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1451 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1452 = and(_T_1450, _T_1451) node _T_1453 = or(UInt<1>(0h0), _T_1452) node _T_1454 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1455 = cvt(_T_1454) node _T_1456 = and(_T_1455, asSInt(UInt<14>(0h2000))) node _T_1457 = asSInt(_T_1456) node _T_1458 = eq(_T_1457, asSInt(UInt<1>(0h0))) node _T_1459 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1460 = cvt(_T_1459) node _T_1461 = and(_T_1460, asSInt(UInt<13>(0h1000))) node _T_1462 = asSInt(_T_1461) node _T_1463 = eq(_T_1462, asSInt(UInt<1>(0h0))) node _T_1464 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1465 = cvt(_T_1464) node _T_1466 = and(_T_1465, asSInt(UInt<17>(0h10000))) node _T_1467 = asSInt(_T_1466) node _T_1468 = eq(_T_1467, asSInt(UInt<1>(0h0))) node _T_1469 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1470 = cvt(_T_1469) node _T_1471 = and(_T_1470, asSInt(UInt<18>(0h2f000))) node _T_1472 = asSInt(_T_1471) node _T_1473 = eq(_T_1472, asSInt(UInt<1>(0h0))) node _T_1474 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1475 = cvt(_T_1474) node _T_1476 = and(_T_1475, asSInt(UInt<17>(0h10000))) node _T_1477 = asSInt(_T_1476) node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0))) node _T_1479 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1480 = cvt(_T_1479) node _T_1481 = and(_T_1480, asSInt(UInt<13>(0h1000))) node _T_1482 = asSInt(_T_1481) node _T_1483 = eq(_T_1482, asSInt(UInt<1>(0h0))) node _T_1484 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1485 = cvt(_T_1484) node _T_1486 = and(_T_1485, asSInt(UInt<17>(0h10000))) node _T_1487 = asSInt(_T_1486) node _T_1488 = eq(_T_1487, asSInt(UInt<1>(0h0))) node _T_1489 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1490 = cvt(_T_1489) node _T_1491 = and(_T_1490, asSInt(UInt<27>(0h4000000))) node _T_1492 = asSInt(_T_1491) node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0))) node _T_1494 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1495 = cvt(_T_1494) node _T_1496 = and(_T_1495, asSInt(UInt<13>(0h1000))) node _T_1497 = asSInt(_T_1496) node _T_1498 = eq(_T_1497, asSInt(UInt<1>(0h0))) node _T_1499 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1500 = cvt(_T_1499) node _T_1501 = and(_T_1500, asSInt(UInt<29>(0h10000000))) node _T_1502 = asSInt(_T_1501) node _T_1503 = eq(_T_1502, asSInt(UInt<1>(0h0))) node _T_1504 = or(_T_1458, _T_1463) node _T_1505 = or(_T_1504, _T_1468) node _T_1506 = or(_T_1505, _T_1473) node _T_1507 = or(_T_1506, _T_1478) node _T_1508 = or(_T_1507, _T_1483) node _T_1509 = or(_T_1508, _T_1488) node _T_1510 = or(_T_1509, _T_1493) node _T_1511 = or(_T_1510, _T_1498) node _T_1512 = or(_T_1511, _T_1503) node _T_1513 = and(_T_1453, _T_1512) node _T_1514 = or(UInt<1>(0h0), _T_1513) node _T_1515 = and(UInt<1>(0h0), _T_1514) node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(_T_1515, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1515, UInt<1>(0h1), "") : assert_106 node _T_1519 = asUInt(reset) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) when _T_1520 : node _T_1521 = eq(address_ok, UInt<1>(0h0)) when _T_1521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(legal_source, UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1528 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_110 node _T_1532 = not(mask_1) node _T_1533 = and(io.in.b.bits.mask, _T_1532) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_111 node _T_1538 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1538 : node _T_1539 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1540 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1541 = and(_T_1539, _T_1540) node _T_1542 = or(UInt<1>(0h0), _T_1541) node _T_1543 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1544 = cvt(_T_1543) node _T_1545 = and(_T_1544, asSInt(UInt<14>(0h2000))) node _T_1546 = asSInt(_T_1545) node _T_1547 = eq(_T_1546, asSInt(UInt<1>(0h0))) node _T_1548 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1549 = cvt(_T_1548) node _T_1550 = and(_T_1549, asSInt(UInt<13>(0h1000))) node _T_1551 = asSInt(_T_1550) node _T_1552 = eq(_T_1551, asSInt(UInt<1>(0h0))) node _T_1553 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1554 = cvt(_T_1553) node _T_1555 = and(_T_1554, asSInt(UInt<17>(0h10000))) node _T_1556 = asSInt(_T_1555) node _T_1557 = eq(_T_1556, asSInt(UInt<1>(0h0))) node _T_1558 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1559 = cvt(_T_1558) node _T_1560 = and(_T_1559, asSInt(UInt<18>(0h2f000))) node _T_1561 = asSInt(_T_1560) node _T_1562 = eq(_T_1561, asSInt(UInt<1>(0h0))) node _T_1563 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1564 = cvt(_T_1563) node _T_1565 = and(_T_1564, asSInt(UInt<17>(0h10000))) node _T_1566 = asSInt(_T_1565) node _T_1567 = eq(_T_1566, asSInt(UInt<1>(0h0))) node _T_1568 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1569 = cvt(_T_1568) node _T_1570 = and(_T_1569, asSInt(UInt<13>(0h1000))) node _T_1571 = asSInt(_T_1570) node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1574 = cvt(_T_1573) node _T_1575 = and(_T_1574, asSInt(UInt<17>(0h10000))) node _T_1576 = asSInt(_T_1575) node _T_1577 = eq(_T_1576, asSInt(UInt<1>(0h0))) node _T_1578 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1579 = cvt(_T_1578) node _T_1580 = and(_T_1579, asSInt(UInt<27>(0h4000000))) node _T_1581 = asSInt(_T_1580) node _T_1582 = eq(_T_1581, asSInt(UInt<1>(0h0))) node _T_1583 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1584 = cvt(_T_1583) node _T_1585 = and(_T_1584, asSInt(UInt<13>(0h1000))) node _T_1586 = asSInt(_T_1585) node _T_1587 = eq(_T_1586, asSInt(UInt<1>(0h0))) node _T_1588 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1589 = cvt(_T_1588) node _T_1590 = and(_T_1589, asSInt(UInt<29>(0h10000000))) node _T_1591 = asSInt(_T_1590) node _T_1592 = eq(_T_1591, asSInt(UInt<1>(0h0))) node _T_1593 = or(_T_1547, _T_1552) node _T_1594 = or(_T_1593, _T_1557) node _T_1595 = or(_T_1594, _T_1562) node _T_1596 = or(_T_1595, _T_1567) node _T_1597 = or(_T_1596, _T_1572) node _T_1598 = or(_T_1597, _T_1577) node _T_1599 = or(_T_1598, _T_1582) node _T_1600 = or(_T_1599, _T_1587) node _T_1601 = or(_T_1600, _T_1592) node _T_1602 = and(_T_1542, _T_1601) node _T_1603 = or(UInt<1>(0h0), _T_1602) node _T_1604 = and(UInt<1>(0h0), _T_1603) node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(_T_1604, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1604, UInt<1>(0h1), "") : assert_112 node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(address_ok, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(legal_source, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1617 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(_T_1617, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1617, UInt<1>(0h1), "") : assert_116 node _T_1621 = eq(io.in.b.bits.mask, mask_1) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_117 node _T_1625 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1625 : node _T_1626 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1627 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1628 = and(_T_1626, _T_1627) node _T_1629 = or(UInt<1>(0h0), _T_1628) node _T_1630 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1631 = cvt(_T_1630) node _T_1632 = and(_T_1631, asSInt(UInt<14>(0h2000))) node _T_1633 = asSInt(_T_1632) node _T_1634 = eq(_T_1633, asSInt(UInt<1>(0h0))) node _T_1635 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1636 = cvt(_T_1635) node _T_1637 = and(_T_1636, asSInt(UInt<13>(0h1000))) node _T_1638 = asSInt(_T_1637) node _T_1639 = eq(_T_1638, asSInt(UInt<1>(0h0))) node _T_1640 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1641 = cvt(_T_1640) node _T_1642 = and(_T_1641, asSInt(UInt<17>(0h10000))) node _T_1643 = asSInt(_T_1642) node _T_1644 = eq(_T_1643, asSInt(UInt<1>(0h0))) node _T_1645 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1646 = cvt(_T_1645) node _T_1647 = and(_T_1646, asSInt(UInt<18>(0h2f000))) node _T_1648 = asSInt(_T_1647) node _T_1649 = eq(_T_1648, asSInt(UInt<1>(0h0))) node _T_1650 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1651 = cvt(_T_1650) node _T_1652 = and(_T_1651, asSInt(UInt<17>(0h10000))) node _T_1653 = asSInt(_T_1652) node _T_1654 = eq(_T_1653, asSInt(UInt<1>(0h0))) node _T_1655 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1656 = cvt(_T_1655) node _T_1657 = and(_T_1656, asSInt(UInt<13>(0h1000))) node _T_1658 = asSInt(_T_1657) node _T_1659 = eq(_T_1658, asSInt(UInt<1>(0h0))) node _T_1660 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1661 = cvt(_T_1660) node _T_1662 = and(_T_1661, asSInt(UInt<17>(0h10000))) node _T_1663 = asSInt(_T_1662) node _T_1664 = eq(_T_1663, asSInt(UInt<1>(0h0))) node _T_1665 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1666 = cvt(_T_1665) node _T_1667 = and(_T_1666, asSInt(UInt<27>(0h4000000))) node _T_1668 = asSInt(_T_1667) node _T_1669 = eq(_T_1668, asSInt(UInt<1>(0h0))) node _T_1670 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1671 = cvt(_T_1670) node _T_1672 = and(_T_1671, asSInt(UInt<13>(0h1000))) node _T_1673 = asSInt(_T_1672) node _T_1674 = eq(_T_1673, asSInt(UInt<1>(0h0))) node _T_1675 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1676 = cvt(_T_1675) node _T_1677 = and(_T_1676, asSInt(UInt<29>(0h10000000))) node _T_1678 = asSInt(_T_1677) node _T_1679 = eq(_T_1678, asSInt(UInt<1>(0h0))) node _T_1680 = or(_T_1634, _T_1639) node _T_1681 = or(_T_1680, _T_1644) node _T_1682 = or(_T_1681, _T_1649) node _T_1683 = or(_T_1682, _T_1654) node _T_1684 = or(_T_1683, _T_1659) node _T_1685 = or(_T_1684, _T_1664) node _T_1686 = or(_T_1685, _T_1669) node _T_1687 = or(_T_1686, _T_1674) node _T_1688 = or(_T_1687, _T_1679) node _T_1689 = and(_T_1629, _T_1688) node _T_1690 = or(UInt<1>(0h0), _T_1689) node _T_1691 = and(UInt<1>(0h0), _T_1690) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_118 node _T_1695 = asUInt(reset) node _T_1696 = eq(_T_1695, UInt<1>(0h0)) when _T_1696 : node _T_1697 = eq(address_ok, UInt<1>(0h0)) when _T_1697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1698 = asUInt(reset) node _T_1699 = eq(_T_1698, UInt<1>(0h0)) when _T_1699 : node _T_1700 = eq(legal_source, UInt<1>(0h0)) when _T_1700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1701 = asUInt(reset) node _T_1702 = eq(_T_1701, UInt<1>(0h0)) when _T_1702 : node _T_1703 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1704 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1705 = asUInt(reset) node _T_1706 = eq(_T_1705, UInt<1>(0h0)) when _T_1706 : node _T_1707 = eq(_T_1704, UInt<1>(0h0)) when _T_1707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1704, UInt<1>(0h1), "") : assert_122 node _T_1708 = eq(io.in.b.bits.mask, mask_1) node _T_1709 = asUInt(reset) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) when _T_1710 : node _T_1711 = eq(_T_1708, UInt<1>(0h0)) when _T_1711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1708, UInt<1>(0h1), "") : assert_123 node _T_1712 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1712 : node _T_1713 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1714 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1715 = and(_T_1713, _T_1714) node _T_1716 = or(UInt<1>(0h0), _T_1715) node _T_1717 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1718 = cvt(_T_1717) node _T_1719 = and(_T_1718, asSInt(UInt<14>(0h2000))) node _T_1720 = asSInt(_T_1719) node _T_1721 = eq(_T_1720, asSInt(UInt<1>(0h0))) node _T_1722 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1723 = cvt(_T_1722) node _T_1724 = and(_T_1723, asSInt(UInt<13>(0h1000))) node _T_1725 = asSInt(_T_1724) node _T_1726 = eq(_T_1725, asSInt(UInt<1>(0h0))) node _T_1727 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1728 = cvt(_T_1727) node _T_1729 = and(_T_1728, asSInt(UInt<17>(0h10000))) node _T_1730 = asSInt(_T_1729) node _T_1731 = eq(_T_1730, asSInt(UInt<1>(0h0))) node _T_1732 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1733 = cvt(_T_1732) node _T_1734 = and(_T_1733, asSInt(UInt<18>(0h2f000))) node _T_1735 = asSInt(_T_1734) node _T_1736 = eq(_T_1735, asSInt(UInt<1>(0h0))) node _T_1737 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1738 = cvt(_T_1737) node _T_1739 = and(_T_1738, asSInt(UInt<17>(0h10000))) node _T_1740 = asSInt(_T_1739) node _T_1741 = eq(_T_1740, asSInt(UInt<1>(0h0))) node _T_1742 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1743 = cvt(_T_1742) node _T_1744 = and(_T_1743, asSInt(UInt<13>(0h1000))) node _T_1745 = asSInt(_T_1744) node _T_1746 = eq(_T_1745, asSInt(UInt<1>(0h0))) node _T_1747 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1748 = cvt(_T_1747) node _T_1749 = and(_T_1748, asSInt(UInt<17>(0h10000))) node _T_1750 = asSInt(_T_1749) node _T_1751 = eq(_T_1750, asSInt(UInt<1>(0h0))) node _T_1752 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1753 = cvt(_T_1752) node _T_1754 = and(_T_1753, asSInt(UInt<27>(0h4000000))) node _T_1755 = asSInt(_T_1754) node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1758 = cvt(_T_1757) node _T_1759 = and(_T_1758, asSInt(UInt<13>(0h1000))) node _T_1760 = asSInt(_T_1759) node _T_1761 = eq(_T_1760, asSInt(UInt<1>(0h0))) node _T_1762 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<29>(0h10000000))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = or(_T_1721, _T_1726) node _T_1768 = or(_T_1767, _T_1731) node _T_1769 = or(_T_1768, _T_1736) node _T_1770 = or(_T_1769, _T_1741) node _T_1771 = or(_T_1770, _T_1746) node _T_1772 = or(_T_1771, _T_1751) node _T_1773 = or(_T_1772, _T_1756) node _T_1774 = or(_T_1773, _T_1761) node _T_1775 = or(_T_1774, _T_1766) node _T_1776 = and(_T_1716, _T_1775) node _T_1777 = or(UInt<1>(0h0), _T_1776) node _T_1778 = and(UInt<1>(0h0), _T_1777) node _T_1779 = asUInt(reset) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : node _T_1781 = eq(_T_1778, UInt<1>(0h0)) when _T_1781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1778, UInt<1>(0h1), "") : assert_124 node _T_1782 = asUInt(reset) node _T_1783 = eq(_T_1782, UInt<1>(0h0)) when _T_1783 : node _T_1784 = eq(address_ok, UInt<1>(0h0)) when _T_1784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1785 = asUInt(reset) node _T_1786 = eq(_T_1785, UInt<1>(0h0)) when _T_1786 : node _T_1787 = eq(legal_source, UInt<1>(0h0)) when _T_1787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1791 = eq(io.in.b.bits.mask, mask_1) node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(_T_1791, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1791, UInt<1>(0h1), "") : assert_128 node _T_1795 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1796 = asUInt(reset) node _T_1797 = eq(_T_1796, UInt<1>(0h0)) when _T_1797 : node _T_1798 = eq(_T_1795, UInt<1>(0h0)) when _T_1798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1795, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1799 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1800 = asUInt(reset) node _T_1801 = eq(_T_1800, UInt<1>(0h0)) when _T_1801 : node _T_1802 = eq(_T_1799, UInt<1>(0h0)) when _T_1802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1799, UInt<1>(0h1), "") : assert_130 node _source_ok_T_8 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_9 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _source_ok_T_10 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_8 connect _source_ok_WIRE_2[1], _source_ok_T_9 connect _source_ok_WIRE_2[2], _source_ok_T_10 node _source_ok_T_11 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_11, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _T_1803 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) node _T_1805 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1806 = cvt(_T_1805) node _T_1807 = and(_T_1806, asSInt(UInt<1>(0h0))) node _T_1808 = asSInt(_T_1807) node _T_1809 = eq(_T_1808, asSInt(UInt<1>(0h0))) node _T_1810 = or(_T_1804, _T_1809) node _T_1811 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1812 = eq(_T_1811, UInt<1>(0h0)) node _T_1813 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1814 = cvt(_T_1813) node _T_1815 = and(_T_1814, asSInt(UInt<1>(0h0))) node _T_1816 = asSInt(_T_1815) node _T_1817 = eq(_T_1816, asSInt(UInt<1>(0h0))) node _T_1818 = or(_T_1812, _T_1817) node _T_1819 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1820 = eq(_T_1819, UInt<1>(0h0)) node _T_1821 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1822 = cvt(_T_1821) node _T_1823 = and(_T_1822, asSInt(UInt<1>(0h0))) node _T_1824 = asSInt(_T_1823) node _T_1825 = eq(_T_1824, asSInt(UInt<1>(0h0))) node _T_1826 = or(_T_1820, _T_1825) node _T_1827 = and(_T_1810, _T_1818) node _T_1828 = and(_T_1827, _T_1826) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_131 node _T_1832 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1832 : node _T_1833 = asUInt(reset) node _T_1834 = eq(_T_1833, UInt<1>(0h0)) when _T_1834 : node _T_1835 = eq(address_ok_1, UInt<1>(0h0)) when _T_1835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1836 = asUInt(reset) node _T_1837 = eq(_T_1836, UInt<1>(0h0)) when _T_1837 : node _T_1838 = eq(source_ok_2, UInt<1>(0h0)) when _T_1838 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1839 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1840 = asUInt(reset) node _T_1841 = eq(_T_1840, UInt<1>(0h0)) when _T_1841 : node _T_1842 = eq(_T_1839, UInt<1>(0h0)) when _T_1842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1839, UInt<1>(0h1), "") : assert_134 node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1846 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_136 node _T_1850 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1851 = asUInt(reset) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) when _T_1852 : node _T_1853 = eq(_T_1850, UInt<1>(0h0)) when _T_1853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1850, UInt<1>(0h1), "") : assert_137 node _T_1854 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1854 : node _T_1855 = asUInt(reset) node _T_1856 = eq(_T_1855, UInt<1>(0h0)) when _T_1856 : node _T_1857 = eq(address_ok_1, UInt<1>(0h0)) when _T_1857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1858 = asUInt(reset) node _T_1859 = eq(_T_1858, UInt<1>(0h0)) when _T_1859 : node _T_1860 = eq(source_ok_2, UInt<1>(0h0)) when _T_1860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1861 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1862 = asUInt(reset) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) when _T_1863 : node _T_1864 = eq(_T_1861, UInt<1>(0h0)) when _T_1864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1861, UInt<1>(0h1), "") : assert_140 node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1868 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_142 node _T_1872 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1872 : node _T_1873 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1874 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1875 = and(_T_1873, _T_1874) node _T_1876 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1877 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1878 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1879 = or(_T_1876, _T_1877) node _T_1880 = or(_T_1879, _T_1878) node _T_1881 = and(_T_1875, _T_1880) node _T_1882 = or(UInt<1>(0h0), _T_1881) node _T_1883 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1884 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1885 = cvt(_T_1884) node _T_1886 = and(_T_1885, asSInt(UInt<14>(0h2000))) node _T_1887 = asSInt(_T_1886) node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0))) node _T_1889 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1890 = cvt(_T_1889) node _T_1891 = and(_T_1890, asSInt(UInt<13>(0h1000))) node _T_1892 = asSInt(_T_1891) node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0))) node _T_1894 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1895 = cvt(_T_1894) node _T_1896 = and(_T_1895, asSInt(UInt<17>(0h10000))) node _T_1897 = asSInt(_T_1896) node _T_1898 = eq(_T_1897, asSInt(UInt<1>(0h0))) node _T_1899 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1900 = cvt(_T_1899) node _T_1901 = and(_T_1900, asSInt(UInt<18>(0h2f000))) node _T_1902 = asSInt(_T_1901) node _T_1903 = eq(_T_1902, asSInt(UInt<1>(0h0))) node _T_1904 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1905 = cvt(_T_1904) node _T_1906 = and(_T_1905, asSInt(UInt<17>(0h10000))) node _T_1907 = asSInt(_T_1906) node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0))) node _T_1909 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1910 = cvt(_T_1909) node _T_1911 = and(_T_1910, asSInt(UInt<13>(0h1000))) node _T_1912 = asSInt(_T_1911) node _T_1913 = eq(_T_1912, asSInt(UInt<1>(0h0))) node _T_1914 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1915 = cvt(_T_1914) node _T_1916 = and(_T_1915, asSInt(UInt<27>(0h4000000))) node _T_1917 = asSInt(_T_1916) node _T_1918 = eq(_T_1917, asSInt(UInt<1>(0h0))) node _T_1919 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1920 = cvt(_T_1919) node _T_1921 = and(_T_1920, asSInt(UInt<13>(0h1000))) node _T_1922 = asSInt(_T_1921) node _T_1923 = eq(_T_1922, asSInt(UInt<1>(0h0))) node _T_1924 = or(_T_1888, _T_1893) node _T_1925 = or(_T_1924, _T_1898) node _T_1926 = or(_T_1925, _T_1903) node _T_1927 = or(_T_1926, _T_1908) node _T_1928 = or(_T_1927, _T_1913) node _T_1929 = or(_T_1928, _T_1918) node _T_1930 = or(_T_1929, _T_1923) node _T_1931 = and(_T_1883, _T_1930) node _T_1932 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1933 = or(UInt<1>(0h0), _T_1932) node _T_1934 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1935 = cvt(_T_1934) node _T_1936 = and(_T_1935, asSInt(UInt<17>(0h10000))) node _T_1937 = asSInt(_T_1936) node _T_1938 = eq(_T_1937, asSInt(UInt<1>(0h0))) node _T_1939 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1940 = cvt(_T_1939) node _T_1941 = and(_T_1940, asSInt(UInt<29>(0h10000000))) node _T_1942 = asSInt(_T_1941) node _T_1943 = eq(_T_1942, asSInt(UInt<1>(0h0))) node _T_1944 = or(_T_1938, _T_1943) node _T_1945 = and(_T_1933, _T_1944) node _T_1946 = or(UInt<1>(0h0), _T_1931) node _T_1947 = or(_T_1946, _T_1945) node _T_1948 = and(_T_1882, _T_1947) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_143 node _T_1952 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1953 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1954 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_1952 connect _WIRE_6[1], _T_1953 connect _WIRE_6[2], _T_1954 node _T_1955 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1956 = mux(_WIRE_6[0], _T_1955, UInt<1>(0h0)) node _T_1957 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1958 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1959 = or(_T_1956, _T_1957) node _T_1960 = or(_T_1959, _T_1958) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1960 node _T_1961 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1962 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1963 = and(_T_1961, _T_1962) node _T_1964 = or(UInt<1>(0h0), _T_1963) node _T_1965 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1966 = cvt(_T_1965) node _T_1967 = and(_T_1966, asSInt(UInt<14>(0h2000))) node _T_1968 = asSInt(_T_1967) node _T_1969 = eq(_T_1968, asSInt(UInt<1>(0h0))) node _T_1970 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1971 = cvt(_T_1970) node _T_1972 = and(_T_1971, asSInt(UInt<13>(0h1000))) node _T_1973 = asSInt(_T_1972) node _T_1974 = eq(_T_1973, asSInt(UInt<1>(0h0))) node _T_1975 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1976 = cvt(_T_1975) node _T_1977 = and(_T_1976, asSInt(UInt<17>(0h10000))) node _T_1978 = asSInt(_T_1977) node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0))) node _T_1980 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1981 = cvt(_T_1980) node _T_1982 = and(_T_1981, asSInt(UInt<18>(0h2f000))) node _T_1983 = asSInt(_T_1982) node _T_1984 = eq(_T_1983, asSInt(UInt<1>(0h0))) node _T_1985 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1986 = cvt(_T_1985) node _T_1987 = and(_T_1986, asSInt(UInt<17>(0h10000))) node _T_1988 = asSInt(_T_1987) node _T_1989 = eq(_T_1988, asSInt(UInt<1>(0h0))) node _T_1990 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1991 = cvt(_T_1990) node _T_1992 = and(_T_1991, asSInt(UInt<13>(0h1000))) node _T_1993 = asSInt(_T_1992) node _T_1994 = eq(_T_1993, asSInt(UInt<1>(0h0))) node _T_1995 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1996 = cvt(_T_1995) node _T_1997 = and(_T_1996, asSInt(UInt<17>(0h10000))) node _T_1998 = asSInt(_T_1997) node _T_1999 = eq(_T_1998, asSInt(UInt<1>(0h0))) node _T_2000 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2001 = cvt(_T_2000) node _T_2002 = and(_T_2001, asSInt(UInt<27>(0h4000000))) node _T_2003 = asSInt(_T_2002) node _T_2004 = eq(_T_2003, asSInt(UInt<1>(0h0))) node _T_2005 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2006 = cvt(_T_2005) node _T_2007 = and(_T_2006, asSInt(UInt<13>(0h1000))) node _T_2008 = asSInt(_T_2007) node _T_2009 = eq(_T_2008, asSInt(UInt<1>(0h0))) node _T_2010 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2011 = cvt(_T_2010) node _T_2012 = and(_T_2011, asSInt(UInt<29>(0h10000000))) node _T_2013 = asSInt(_T_2012) node _T_2014 = eq(_T_2013, asSInt(UInt<1>(0h0))) node _T_2015 = or(_T_1969, _T_1974) node _T_2016 = or(_T_2015, _T_1979) node _T_2017 = or(_T_2016, _T_1984) node _T_2018 = or(_T_2017, _T_1989) node _T_2019 = or(_T_2018, _T_1994) node _T_2020 = or(_T_2019, _T_1999) node _T_2021 = or(_T_2020, _T_2004) node _T_2022 = or(_T_2021, _T_2009) node _T_2023 = or(_T_2022, _T_2014) node _T_2024 = and(_T_1964, _T_2023) node _T_2025 = or(UInt<1>(0h0), _T_2024) node _T_2026 = and(_WIRE_7, _T_2025) node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(_T_2026, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2026, UInt<1>(0h1), "") : assert_144 node _T_2030 = asUInt(reset) node _T_2031 = eq(_T_2030, UInt<1>(0h0)) when _T_2031 : node _T_2032 = eq(source_ok_2, UInt<1>(0h0)) when _T_2032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2033 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_146 node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2040 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2041 = asUInt(reset) node _T_2042 = eq(_T_2041, UInt<1>(0h0)) when _T_2042 : node _T_2043 = eq(_T_2040, UInt<1>(0h0)) when _T_2043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2040, UInt<1>(0h1), "") : assert_148 node _T_2044 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2045 = asUInt(reset) node _T_2046 = eq(_T_2045, UInt<1>(0h0)) when _T_2046 : node _T_2047 = eq(_T_2044, UInt<1>(0h0)) when _T_2047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2044, UInt<1>(0h1), "") : assert_149 node _T_2048 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2048 : node _T_2049 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2050 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2051 = and(_T_2049, _T_2050) node _T_2052 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2053 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2054 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_2055 = or(_T_2052, _T_2053) node _T_2056 = or(_T_2055, _T_2054) node _T_2057 = and(_T_2051, _T_2056) node _T_2058 = or(UInt<1>(0h0), _T_2057) node _T_2059 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2060 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<14>(0h2000))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2066 = cvt(_T_2065) node _T_2067 = and(_T_2066, asSInt(UInt<13>(0h1000))) node _T_2068 = asSInt(_T_2067) node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) node _T_2070 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<17>(0h10000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<18>(0h2f000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<17>(0h10000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<27>(0h4000000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2096 = cvt(_T_2095) node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000))) node _T_2098 = asSInt(_T_2097) node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0))) node _T_2100 = or(_T_2064, _T_2069) node _T_2101 = or(_T_2100, _T_2074) node _T_2102 = or(_T_2101, _T_2079) node _T_2103 = or(_T_2102, _T_2084) node _T_2104 = or(_T_2103, _T_2089) node _T_2105 = or(_T_2104, _T_2094) node _T_2106 = or(_T_2105, _T_2099) node _T_2107 = and(_T_2059, _T_2106) node _T_2108 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2109 = or(UInt<1>(0h0), _T_2108) node _T_2110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2111 = cvt(_T_2110) node _T_2112 = and(_T_2111, asSInt(UInt<17>(0h10000))) node _T_2113 = asSInt(_T_2112) node _T_2114 = eq(_T_2113, asSInt(UInt<1>(0h0))) node _T_2115 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2116 = cvt(_T_2115) node _T_2117 = and(_T_2116, asSInt(UInt<29>(0h10000000))) node _T_2118 = asSInt(_T_2117) node _T_2119 = eq(_T_2118, asSInt(UInt<1>(0h0))) node _T_2120 = or(_T_2114, _T_2119) node _T_2121 = and(_T_2109, _T_2120) node _T_2122 = or(UInt<1>(0h0), _T_2107) node _T_2123 = or(_T_2122, _T_2121) node _T_2124 = and(_T_2058, _T_2123) node _T_2125 = asUInt(reset) node _T_2126 = eq(_T_2125, UInt<1>(0h0)) when _T_2126 : node _T_2127 = eq(_T_2124, UInt<1>(0h0)) when _T_2127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2124, UInt<1>(0h1), "") : assert_150 node _T_2128 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2130 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2128 connect _WIRE_8[1], _T_2129 connect _WIRE_8[2], _T_2130 node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2132 = mux(_WIRE_8[0], _T_2131, UInt<1>(0h0)) node _T_2133 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2134 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2135 = or(_T_2132, _T_2133) node _T_2136 = or(_T_2135, _T_2134) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2136 node _T_2137 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2138 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2139 = and(_T_2137, _T_2138) node _T_2140 = or(UInt<1>(0h0), _T_2139) node _T_2141 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2142 = cvt(_T_2141) node _T_2143 = and(_T_2142, asSInt(UInt<14>(0h2000))) node _T_2144 = asSInt(_T_2143) node _T_2145 = eq(_T_2144, asSInt(UInt<1>(0h0))) node _T_2146 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2147 = cvt(_T_2146) node _T_2148 = and(_T_2147, asSInt(UInt<13>(0h1000))) node _T_2149 = asSInt(_T_2148) node _T_2150 = eq(_T_2149, asSInt(UInt<1>(0h0))) node _T_2151 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2152 = cvt(_T_2151) node _T_2153 = and(_T_2152, asSInt(UInt<17>(0h10000))) node _T_2154 = asSInt(_T_2153) node _T_2155 = eq(_T_2154, asSInt(UInt<1>(0h0))) node _T_2156 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2157 = cvt(_T_2156) node _T_2158 = and(_T_2157, asSInt(UInt<18>(0h2f000))) node _T_2159 = asSInt(_T_2158) node _T_2160 = eq(_T_2159, asSInt(UInt<1>(0h0))) node _T_2161 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2162 = cvt(_T_2161) node _T_2163 = and(_T_2162, asSInt(UInt<17>(0h10000))) node _T_2164 = asSInt(_T_2163) node _T_2165 = eq(_T_2164, asSInt(UInt<1>(0h0))) node _T_2166 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2167 = cvt(_T_2166) node _T_2168 = and(_T_2167, asSInt(UInt<13>(0h1000))) node _T_2169 = asSInt(_T_2168) node _T_2170 = eq(_T_2169, asSInt(UInt<1>(0h0))) node _T_2171 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2172 = cvt(_T_2171) node _T_2173 = and(_T_2172, asSInt(UInt<17>(0h10000))) node _T_2174 = asSInt(_T_2173) node _T_2175 = eq(_T_2174, asSInt(UInt<1>(0h0))) node _T_2176 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2177 = cvt(_T_2176) node _T_2178 = and(_T_2177, asSInt(UInt<27>(0h4000000))) node _T_2179 = asSInt(_T_2178) node _T_2180 = eq(_T_2179, asSInt(UInt<1>(0h0))) node _T_2181 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2182 = cvt(_T_2181) node _T_2183 = and(_T_2182, asSInt(UInt<13>(0h1000))) node _T_2184 = asSInt(_T_2183) node _T_2185 = eq(_T_2184, asSInt(UInt<1>(0h0))) node _T_2186 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2187 = cvt(_T_2186) node _T_2188 = and(_T_2187, asSInt(UInt<29>(0h10000000))) node _T_2189 = asSInt(_T_2188) node _T_2190 = eq(_T_2189, asSInt(UInt<1>(0h0))) node _T_2191 = or(_T_2145, _T_2150) node _T_2192 = or(_T_2191, _T_2155) node _T_2193 = or(_T_2192, _T_2160) node _T_2194 = or(_T_2193, _T_2165) node _T_2195 = or(_T_2194, _T_2170) node _T_2196 = or(_T_2195, _T_2175) node _T_2197 = or(_T_2196, _T_2180) node _T_2198 = or(_T_2197, _T_2185) node _T_2199 = or(_T_2198, _T_2190) node _T_2200 = and(_T_2140, _T_2199) node _T_2201 = or(UInt<1>(0h0), _T_2200) node _T_2202 = and(_WIRE_9, _T_2201) node _T_2203 = asUInt(reset) node _T_2204 = eq(_T_2203, UInt<1>(0h0)) when _T_2204 : node _T_2205 = eq(_T_2202, UInt<1>(0h0)) when _T_2205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2202, UInt<1>(0h1), "") : assert_151 node _T_2206 = asUInt(reset) node _T_2207 = eq(_T_2206, UInt<1>(0h0)) when _T_2207 : node _T_2208 = eq(source_ok_2, UInt<1>(0h0)) when _T_2208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2209 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : node _T_2212 = eq(_T_2209, UInt<1>(0h0)) when _T_2212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2209, UInt<1>(0h1), "") : assert_153 node _T_2213 = asUInt(reset) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) when _T_2214 : node _T_2215 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2216 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2217 = asUInt(reset) node _T_2218 = eq(_T_2217, UInt<1>(0h0)) when _T_2218 : node _T_2219 = eq(_T_2216, UInt<1>(0h0)) when _T_2219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2216, UInt<1>(0h1), "") : assert_155 node _T_2220 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2220 : node _T_2221 = asUInt(reset) node _T_2222 = eq(_T_2221, UInt<1>(0h0)) when _T_2222 : node _T_2223 = eq(address_ok_1, UInt<1>(0h0)) when _T_2223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2224 = asUInt(reset) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) when _T_2225 : node _T_2226 = eq(source_ok_2, UInt<1>(0h0)) when _T_2226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2230 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_159 node _T_2234 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2235 = asUInt(reset) node _T_2236 = eq(_T_2235, UInt<1>(0h0)) when _T_2236 : node _T_2237 = eq(_T_2234, UInt<1>(0h0)) when _T_2237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2234, UInt<1>(0h1), "") : assert_160 node _T_2238 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2238 : node _T_2239 = asUInt(reset) node _T_2240 = eq(_T_2239, UInt<1>(0h0)) when _T_2240 : node _T_2241 = eq(address_ok_1, UInt<1>(0h0)) when _T_2241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : node _T_2244 = eq(source_ok_2, UInt<1>(0h0)) when _T_2244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2248 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_164 node _T_2252 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2252 : node _T_2253 = asUInt(reset) node _T_2254 = eq(_T_2253, UInt<1>(0h0)) when _T_2254 : node _T_2255 = eq(address_ok_1, UInt<1>(0h0)) when _T_2255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2256 = asUInt(reset) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) when _T_2257 : node _T_2258 = eq(source_ok_2, UInt<1>(0h0)) when _T_2258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2259 = asUInt(reset) node _T_2260 = eq(_T_2259, UInt<1>(0h0)) when _T_2260 : node _T_2261 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2262 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2263 = asUInt(reset) node _T_2264 = eq(_T_2263, UInt<1>(0h0)) when _T_2264 : node _T_2265 = eq(_T_2262, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2262, UInt<1>(0h1), "") : assert_168 node _T_2266 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(_T_2266, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2266, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2273 = eq(a_first, UInt<1>(0h0)) node _T_2274 = and(io.in.a.valid, _T_2273) when _T_2274 : node _T_2275 = eq(io.in.a.bits.opcode, opcode) node _T_2276 = asUInt(reset) node _T_2277 = eq(_T_2276, UInt<1>(0h0)) when _T_2277 : node _T_2278 = eq(_T_2275, UInt<1>(0h0)) when _T_2278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2275, UInt<1>(0h1), "") : assert_171 node _T_2279 = eq(io.in.a.bits.param, param) node _T_2280 = asUInt(reset) node _T_2281 = eq(_T_2280, UInt<1>(0h0)) when _T_2281 : node _T_2282 = eq(_T_2279, UInt<1>(0h0)) when _T_2282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2279, UInt<1>(0h1), "") : assert_172 node _T_2283 = eq(io.in.a.bits.size, size) node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : node _T_2286 = eq(_T_2283, UInt<1>(0h0)) when _T_2286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2283, UInt<1>(0h1), "") : assert_173 node _T_2287 = eq(io.in.a.bits.source, source) node _T_2288 = asUInt(reset) node _T_2289 = eq(_T_2288, UInt<1>(0h0)) when _T_2289 : node _T_2290 = eq(_T_2287, UInt<1>(0h0)) when _T_2290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2287, UInt<1>(0h1), "") : assert_174 node _T_2291 = eq(io.in.a.bits.address, address) node _T_2292 = asUInt(reset) node _T_2293 = eq(_T_2292, UInt<1>(0h0)) when _T_2293 : node _T_2294 = eq(_T_2291, UInt<1>(0h0)) when _T_2294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2291, UInt<1>(0h1), "") : assert_175 node _T_2295 = and(io.in.a.ready, io.in.a.valid) node _T_2296 = and(_T_2295, a_first) when _T_2296 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2297 = eq(d_first, UInt<1>(0h0)) node _T_2298 = and(io.in.d.valid, _T_2297) when _T_2298 : node _T_2299 = eq(io.in.d.bits.opcode, opcode_1) node _T_2300 = asUInt(reset) node _T_2301 = eq(_T_2300, UInt<1>(0h0)) when _T_2301 : node _T_2302 = eq(_T_2299, UInt<1>(0h0)) when _T_2302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2299, UInt<1>(0h1), "") : assert_176 node _T_2303 = eq(io.in.d.bits.param, param_1) node _T_2304 = asUInt(reset) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) when _T_2305 : node _T_2306 = eq(_T_2303, UInt<1>(0h0)) when _T_2306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2303, UInt<1>(0h1), "") : assert_177 node _T_2307 = eq(io.in.d.bits.size, size_1) node _T_2308 = asUInt(reset) node _T_2309 = eq(_T_2308, UInt<1>(0h0)) when _T_2309 : node _T_2310 = eq(_T_2307, UInt<1>(0h0)) when _T_2310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2307, UInt<1>(0h1), "") : assert_178 node _T_2311 = eq(io.in.d.bits.source, source_1) node _T_2312 = asUInt(reset) node _T_2313 = eq(_T_2312, UInt<1>(0h0)) when _T_2313 : node _T_2314 = eq(_T_2311, UInt<1>(0h0)) when _T_2314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2311, UInt<1>(0h1), "") : assert_179 node _T_2315 = eq(io.in.d.bits.sink, sink) node _T_2316 = asUInt(reset) node _T_2317 = eq(_T_2316, UInt<1>(0h0)) when _T_2317 : node _T_2318 = eq(_T_2315, UInt<1>(0h0)) when _T_2318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2315, UInt<1>(0h1), "") : assert_180 node _T_2319 = eq(io.in.d.bits.denied, denied) node _T_2320 = asUInt(reset) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) when _T_2321 : node _T_2322 = eq(_T_2319, UInt<1>(0h0)) when _T_2322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2319, UInt<1>(0h1), "") : assert_181 node _T_2323 = and(io.in.d.ready, io.in.d.valid) node _T_2324 = and(_T_2323, d_first) when _T_2324 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2325 = eq(b_first, UInt<1>(0h0)) node _T_2326 = and(io.in.b.valid, _T_2325) when _T_2326 : node _T_2327 = eq(io.in.b.bits.opcode, opcode_2) node _T_2328 = asUInt(reset) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) when _T_2329 : node _T_2330 = eq(_T_2327, UInt<1>(0h0)) when _T_2330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2327, UInt<1>(0h1), "") : assert_182 node _T_2331 = eq(io.in.b.bits.param, param_2) node _T_2332 = asUInt(reset) node _T_2333 = eq(_T_2332, UInt<1>(0h0)) when _T_2333 : node _T_2334 = eq(_T_2331, UInt<1>(0h0)) when _T_2334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2331, UInt<1>(0h1), "") : assert_183 node _T_2335 = eq(io.in.b.bits.size, size_2) node _T_2336 = asUInt(reset) node _T_2337 = eq(_T_2336, UInt<1>(0h0)) when _T_2337 : node _T_2338 = eq(_T_2335, UInt<1>(0h0)) when _T_2338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2335, UInt<1>(0h1), "") : assert_184 node _T_2339 = eq(io.in.b.bits.source, source_2) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_185 node _T_2343 = eq(io.in.b.bits.address, address_1) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_186 node _T_2347 = and(io.in.b.ready, io.in.b.valid) node _T_2348 = and(_T_2347, b_first) when _T_2348 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2349 = eq(c_first, UInt<1>(0h0)) node _T_2350 = and(io.in.c.valid, _T_2349) when _T_2350 : node _T_2351 = eq(io.in.c.bits.opcode, opcode_3) node _T_2352 = asUInt(reset) node _T_2353 = eq(_T_2352, UInt<1>(0h0)) when _T_2353 : node _T_2354 = eq(_T_2351, UInt<1>(0h0)) when _T_2354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2351, UInt<1>(0h1), "") : assert_187 node _T_2355 = eq(io.in.c.bits.param, param_3) node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(_T_2355, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2355, UInt<1>(0h1), "") : assert_188 node _T_2359 = eq(io.in.c.bits.size, size_3) node _T_2360 = asUInt(reset) node _T_2361 = eq(_T_2360, UInt<1>(0h0)) when _T_2361 : node _T_2362 = eq(_T_2359, UInt<1>(0h0)) when _T_2362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2359, UInt<1>(0h1), "") : assert_189 node _T_2363 = eq(io.in.c.bits.source, source_3) node _T_2364 = asUInt(reset) node _T_2365 = eq(_T_2364, UInt<1>(0h0)) when _T_2365 : node _T_2366 = eq(_T_2363, UInt<1>(0h0)) when _T_2366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2363, UInt<1>(0h1), "") : assert_190 node _T_2367 = eq(io.in.c.bits.address, address_2) node _T_2368 = asUInt(reset) node _T_2369 = eq(_T_2368, UInt<1>(0h0)) when _T_2369 : node _T_2370 = eq(_T_2367, UInt<1>(0h0)) when _T_2370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2367, UInt<1>(0h1), "") : assert_191 node _T_2371 = and(io.in.c.ready, io.in.c.valid) node _T_2372 = and(_T_2371, c_first) when _T_2372 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes : UInt<24>, clock, reset, UInt<24>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<3> connect a_set, UInt<3>(0h0) wire a_set_wo_ready : UInt<3> connect a_set_wo_ready, UInt<3>(0h0) wire a_opcodes_set : UInt<12> connect a_opcodes_set, UInt<12>(0h0) wire a_sizes_set : UInt<24> connect a_sizes_set, UInt<24>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2373 = and(io.in.a.valid, a_first_1) node _T_2374 = and(_T_2373, UInt<1>(0h1)) when _T_2374 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2375 = and(io.in.a.ready, io.in.a.valid) node _T_2376 = and(_T_2375, a_first_1) node _T_2377 = and(_T_2376, UInt<1>(0h1)) when _T_2377 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2378 = dshr(inflight, io.in.a.bits.source) node _T_2379 = bits(_T_2378, 0, 0) node _T_2380 = eq(_T_2379, UInt<1>(0h0)) node _T_2381 = asUInt(reset) node _T_2382 = eq(_T_2381, UInt<1>(0h0)) when _T_2382 : node _T_2383 = eq(_T_2380, UInt<1>(0h0)) when _T_2383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2380, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<3> connect d_clr, UInt<3>(0h0) wire d_clr_wo_ready : UInt<3> connect d_clr_wo_ready, UInt<3>(0h0) wire d_opcodes_clr : UInt<12> connect d_opcodes_clr, UInt<12>(0h0) wire d_sizes_clr : UInt<24> connect d_sizes_clr, UInt<24>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2384 = and(io.in.d.valid, d_first_1) node _T_2385 = and(_T_2384, UInt<1>(0h1)) node _T_2386 = eq(d_release_ack, UInt<1>(0h0)) node _T_2387 = and(_T_2385, _T_2386) when _T_2387 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2388 = and(io.in.d.ready, io.in.d.valid) node _T_2389 = and(_T_2388, d_first_1) node _T_2390 = and(_T_2389, UInt<1>(0h1)) node _T_2391 = eq(d_release_ack, UInt<1>(0h0)) node _T_2392 = and(_T_2390, _T_2391) when _T_2392 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2393 = and(io.in.d.valid, d_first_1) node _T_2394 = and(_T_2393, UInt<1>(0h1)) node _T_2395 = eq(d_release_ack, UInt<1>(0h0)) node _T_2396 = and(_T_2394, _T_2395) when _T_2396 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2397 = dshr(inflight, io.in.d.bits.source) node _T_2398 = bits(_T_2397, 0, 0) node _T_2399 = or(_T_2398, same_cycle_resp) node _T_2400 = asUInt(reset) node _T_2401 = eq(_T_2400, UInt<1>(0h0)) when _T_2401 : node _T_2402 = eq(_T_2399, UInt<1>(0h0)) when _T_2402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2399, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2403 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2404 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2405 = or(_T_2403, _T_2404) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_194 node _T_2409 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2410 = asUInt(reset) node _T_2411 = eq(_T_2410, UInt<1>(0h0)) when _T_2411 : node _T_2412 = eq(_T_2409, UInt<1>(0h0)) when _T_2412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2409, UInt<1>(0h1), "") : assert_195 else : node _T_2413 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2414 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2415 = or(_T_2413, _T_2414) node _T_2416 = asUInt(reset) node _T_2417 = eq(_T_2416, UInt<1>(0h0)) when _T_2417 : node _T_2418 = eq(_T_2415, UInt<1>(0h0)) when _T_2418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2415, UInt<1>(0h1), "") : assert_196 node _T_2419 = eq(io.in.d.bits.size, a_size_lookup) node _T_2420 = asUInt(reset) node _T_2421 = eq(_T_2420, UInt<1>(0h0)) when _T_2421 : node _T_2422 = eq(_T_2419, UInt<1>(0h0)) when _T_2422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2419, UInt<1>(0h1), "") : assert_197 node _T_2423 = and(io.in.d.valid, d_first_1) node _T_2424 = and(_T_2423, a_first_1) node _T_2425 = and(_T_2424, io.in.a.valid) node _T_2426 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2427 = and(_T_2425, _T_2426) node _T_2428 = eq(d_release_ack, UInt<1>(0h0)) node _T_2429 = and(_T_2427, _T_2428) when _T_2429 : node _T_2430 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2431 = or(_T_2430, io.in.a.ready) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_198 node _T_2435 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2436 = orr(a_set_wo_ready) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) node _T_2438 = or(_T_2435, _T_2437) node _T_2439 = asUInt(reset) node _T_2440 = eq(_T_2439, UInt<1>(0h0)) when _T_2440 : node _T_2441 = eq(_T_2438, UInt<1>(0h0)) when _T_2441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2438, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_143 node _T_2442 = orr(inflight) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) node _T_2444 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2445 = or(_T_2443, _T_2444) node _T_2446 = lt(watchdog, plusarg_reader.out) node _T_2447 = or(_T_2445, _T_2446) node _T_2448 = asUInt(reset) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) when _T_2449 : node _T_2450 = eq(_T_2447, UInt<1>(0h0)) when _T_2450 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2447, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2451 = and(io.in.a.ready, io.in.a.valid) node _T_2452 = and(io.in.d.ready, io.in.d.valid) node _T_2453 = or(_T_2451, _T_2452) when _T_2453 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes_1 : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes_1 : UInt<24>, clock, reset, UInt<24>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<3> connect c_set, UInt<3>(0h0) wire c_set_wo_ready : UInt<3> connect c_set_wo_ready, UInt<3>(0h0) wire c_opcodes_set : UInt<12> connect c_opcodes_set, UInt<12>(0h0) wire c_sizes_set : UInt<24> connect c_sizes_set, UInt<24>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2454 = and(io.in.c.valid, c_first_1) node _T_2455 = bits(io.in.c.bits.opcode, 2, 2) node _T_2456 = bits(io.in.c.bits.opcode, 1, 1) node _T_2457 = and(_T_2455, _T_2456) node _T_2458 = and(_T_2454, _T_2457) when _T_2458 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2459 = and(io.in.c.ready, io.in.c.valid) node _T_2460 = and(_T_2459, c_first_1) node _T_2461 = bits(io.in.c.bits.opcode, 2, 2) node _T_2462 = bits(io.in.c.bits.opcode, 1, 1) node _T_2463 = and(_T_2461, _T_2462) node _T_2464 = and(_T_2460, _T_2463) when _T_2464 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2465 = dshr(inflight_1, io.in.c.bits.source) node _T_2466 = bits(_T_2465, 0, 0) node _T_2467 = eq(_T_2466, UInt<1>(0h0)) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<3> connect d_clr_1, UInt<3>(0h0) wire d_clr_wo_ready_1 : UInt<3> connect d_clr_wo_ready_1, UInt<3>(0h0) wire d_opcodes_clr_1 : UInt<12> connect d_opcodes_clr_1, UInt<12>(0h0) wire d_sizes_clr_1 : UInt<24> connect d_sizes_clr_1, UInt<24>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2471 = and(io.in.d.valid, d_first_2) node _T_2472 = and(_T_2471, UInt<1>(0h1)) node _T_2473 = and(_T_2472, d_release_ack_1) when _T_2473 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2474 = and(io.in.d.ready, io.in.d.valid) node _T_2475 = and(_T_2474, d_first_2) node _T_2476 = and(_T_2475, UInt<1>(0h1)) node _T_2477 = and(_T_2476, d_release_ack_1) when _T_2477 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2478 = and(io.in.d.valid, d_first_2) node _T_2479 = and(_T_2478, UInt<1>(0h1)) node _T_2480 = and(_T_2479, d_release_ack_1) when _T_2480 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2481 = dshr(inflight_1, io.in.d.bits.source) node _T_2482 = bits(_T_2481, 0, 0) node _T_2483 = or(_T_2482, same_cycle_resp_1) node _T_2484 = asUInt(reset) node _T_2485 = eq(_T_2484, UInt<1>(0h0)) when _T_2485 : node _T_2486 = eq(_T_2483, UInt<1>(0h0)) when _T_2486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2483, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2487 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2488 = asUInt(reset) node _T_2489 = eq(_T_2488, UInt<1>(0h0)) when _T_2489 : node _T_2490 = eq(_T_2487, UInt<1>(0h0)) when _T_2490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2487, UInt<1>(0h1), "") : assert_203 else : node _T_2491 = eq(io.in.d.bits.size, c_size_lookup) node _T_2492 = asUInt(reset) node _T_2493 = eq(_T_2492, UInt<1>(0h0)) when _T_2493 : node _T_2494 = eq(_T_2491, UInt<1>(0h0)) when _T_2494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2491, UInt<1>(0h1), "") : assert_204 node _T_2495 = and(io.in.d.valid, d_first_2) node _T_2496 = and(_T_2495, c_first_1) node _T_2497 = and(_T_2496, io.in.c.valid) node _T_2498 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2499 = and(_T_2497, _T_2498) node _T_2500 = and(_T_2499, d_release_ack_1) node _T_2501 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2502 = and(_T_2500, _T_2501) when _T_2502 : node _T_2503 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2504 = or(_T_2503, io.in.c.ready) node _T_2505 = asUInt(reset) node _T_2506 = eq(_T_2505, UInt<1>(0h0)) when _T_2506 : node _T_2507 = eq(_T_2504, UInt<1>(0h0)) when _T_2507 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2504, UInt<1>(0h1), "") : assert_205 node _T_2508 = orr(c_set_wo_ready) when _T_2508 : node _T_2509 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_144 node _T_2513 = orr(inflight_1) node _T_2514 = eq(_T_2513, UInt<1>(0h0)) node _T_2515 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2516 = or(_T_2514, _T_2515) node _T_2517 = lt(watchdog_1, plusarg_reader_1.out) node _T_2518 = or(_T_2516, _T_2517) node _T_2519 = asUInt(reset) node _T_2520 = eq(_T_2519, UInt<1>(0h0)) when _T_2520 : node _T_2521 = eq(_T_2518, UInt<1>(0h0)) when _T_2521 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2518, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2522 = and(io.in.c.ready, io.in.c.valid) node _T_2523 = and(io.in.d.ready, io.in.d.valid) node _T_2524 = or(_T_2522, _T_2523) when _T_2524 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2525 = and(io.in.d.ready, io.in.d.valid) node _T_2526 = and(_T_2525, d_first_3) node _T_2527 = bits(io.in.d.bits.opcode, 2, 2) node _T_2528 = bits(io.in.d.bits.opcode, 1, 1) node _T_2529 = eq(_T_2528, UInt<1>(0h0)) node _T_2530 = and(_T_2527, _T_2529) node _T_2531 = and(_T_2526, _T_2530) when _T_2531 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2532 = dshr(inflight_2, io.in.d.bits.sink) node _T_2533 = bits(_T_2532, 0, 0) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) node _T_2535 = asUInt(reset) node _T_2536 = eq(_T_2535, UInt<1>(0h0)) when _T_2536 : node _T_2537 = eq(_T_2534, UInt<1>(0h0)) when _T_2537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2534, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2538 = and(io.in.e.ready, io.in.e.valid) node _T_2539 = and(_T_2538, UInt<1>(0h1)) node _T_2540 = and(_T_2539, UInt<1>(0h1)) when _T_2540 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2541 = or(d_set, inflight_2) node _T_2542 = dshr(_T_2541, io.in.e.bits.sink) node _T_2543 = bits(_T_2542, 0, 0) node _T_2544 = asUInt(reset) node _T_2545 = eq(_T_2544, UInt<1>(0h0)) when _T_2545 : node _T_2546 = eq(_T_2543, UInt<1>(0h0)) when _T_2546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2543, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8	module TLMonitor_68( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_3 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_3 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_7 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _legal_source_T = io_in_b_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _legal_source_T_1 = io_in_b_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _legal_source_T_2 = io_in_b_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_2; // @[Parameters.scala:1138:31] wire _legal_source_T_4 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_6 = _legal_source_T_4; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_5 = {_legal_source_WIRE_2, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_7 = {1'h0, _legal_source_T_6} \| _legal_source_T_5; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_7; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31] wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31] wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31] wire _source_ok_T_11 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_11 \| _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2451 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2451; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2451; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2525; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2522 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2522; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2522; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] a_set; // @[Monitor.scala:626:34] wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [23:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_21 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2377 = _T_2451 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2377 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2377 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2377 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2377 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2377 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2:0] d_clr; // @[Monitor.scala:664:34] wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2423 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_23 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2423 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2392 = _T_2525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2392 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2392 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2392 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [11:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [23:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] c_set; // @[Monitor.scala:738:34] wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [23:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_24 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2464 = _T_2522 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2464 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2464 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2464 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2464 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2464 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [2:0] d_clr_1; // @[Monitor.scala:774:34] wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2495 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2495 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2477 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2477 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2477 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [2:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2531 = _T_2525 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_25 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2531 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2540 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_26 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2540 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module IssueUnitCollapsing_3 : input clock : Clock input reset : Reset output io : { flip dis_uops : { flip ready : UInt<1>, valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}[1], iss_valids : UInt<1>[1], iss_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<6>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<4>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<6>}[1], flip fu_types : UInt<10>[1], flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip flush_pipeline : UInt<1>, flip ld_miss : UInt<1>, event_empty : UInt<1>, flip tsc_reg : UInt<64>} wire _WIRE : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect _WIRE, io.dis_uops[0].bits connect _WIRE.iw_p1_poisoned, UInt<1>(0h0) connect _WIRE.iw_p2_poisoned, UInt<1>(0h0) connect _WIRE.iw_state, UInt<2>(0h1) node _T = eq(io.dis_uops[0].bits.uopc, UInt<7>(0h2)) when _T : connect _WIRE.lrs1_rtype, UInt<2>(0h2) connect _WIRE.prs1_busy, UInt<1>(0h0) node _T_1 = and(io.dis_uops[0].bits.ppred_busy, io.dis_uops[0].valid) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit.scala:145 assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert connect _WIRE.ppred_busy, UInt<1>(0h0) inst slots_0 of IssueSlot_24 connect slots_0.clock, clock connect slots_0.reset, reset inst slots_1 of IssueSlot_25 connect slots_1.clock, clock connect slots_1.reset, reset inst slots_2 of IssueSlot_26 connect slots_2.clock, clock connect slots_2.reset, reset inst slots_3 of IssueSlot_27 connect slots_3.clock, clock connect slots_3.reset, reset inst slots_4 of IssueSlot_28 connect slots_4.clock, clock connect slots_4.reset, reset inst slots_5 of IssueSlot_29 connect slots_5.clock, clock connect slots_5.reset, reset inst slots_6 of IssueSlot_30 connect slots_6.clock, clock connect slots_6.reset, reset inst slots_7 of IssueSlot_31 connect slots_7.clock, clock connect slots_7.reset, reset wire issue_slots : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<6>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<4>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<6>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}[8] connect issue_slots[0].debug.state, slots_0.io.debug.state connect issue_slots[0].debug.ppred, slots_0.io.debug.ppred connect issue_slots[0].debug.p3, slots_0.io.debug.p3 connect issue_slots[0].debug.p2, slots_0.io.debug.p2 connect issue_slots[0].debug.p1, slots_0.io.debug.p1 connect issue_slots[0].uop.debug_tsrc, slots_0.io.uop.debug_tsrc connect issue_slots[0].uop.debug_fsrc, slots_0.io.uop.debug_fsrc connect issue_slots[0].uop.bp_xcpt_if, slots_0.io.uop.bp_xcpt_if connect issue_slots[0].uop.bp_debug_if, slots_0.io.uop.bp_debug_if connect issue_slots[0].uop.xcpt_ma_if, slots_0.io.uop.xcpt_ma_if connect issue_slots[0].uop.xcpt_ae_if, slots_0.io.uop.xcpt_ae_if connect issue_slots[0].uop.xcpt_pf_if, slots_0.io.uop.xcpt_pf_if connect issue_slots[0].uop.fp_single, slots_0.io.uop.fp_single connect issue_slots[0].uop.fp_val, slots_0.io.uop.fp_val connect issue_slots[0].uop.frs3_en, slots_0.io.uop.frs3_en connect issue_slots[0].uop.lrs2_rtype, slots_0.io.uop.lrs2_rtype connect issue_slots[0].uop.lrs1_rtype, slots_0.io.uop.lrs1_rtype connect issue_slots[0].uop.dst_rtype, slots_0.io.uop.dst_rtype connect issue_slots[0].uop.ldst_val, slots_0.io.uop.ldst_val connect issue_slots[0].uop.lrs3, slots_0.io.uop.lrs3 connect issue_slots[0].uop.lrs2, slots_0.io.uop.lrs2 connect issue_slots[0].uop.lrs1, slots_0.io.uop.lrs1 connect issue_slots[0].uop.ldst, slots_0.io.uop.ldst connect issue_slots[0].uop.ldst_is_rs1, slots_0.io.uop.ldst_is_rs1 connect issue_slots[0].uop.flush_on_commit, slots_0.io.uop.flush_on_commit connect issue_slots[0].uop.is_unique, slots_0.io.uop.is_unique connect issue_slots[0].uop.is_sys_pc2epc, slots_0.io.uop.is_sys_pc2epc connect issue_slots[0].uop.uses_stq, slots_0.io.uop.uses_stq connect issue_slots[0].uop.uses_ldq, slots_0.io.uop.uses_ldq connect issue_slots[0].uop.is_amo, slots_0.io.uop.is_amo connect issue_slots[0].uop.is_fencei, slots_0.io.uop.is_fencei connect issue_slots[0].uop.is_fence, slots_0.io.uop.is_fence connect issue_slots[0].uop.mem_signed, slots_0.io.uop.mem_signed connect issue_slots[0].uop.mem_size, slots_0.io.uop.mem_size connect issue_slots[0].uop.mem_cmd, slots_0.io.uop.mem_cmd connect issue_slots[0].uop.bypassable, slots_0.io.uop.bypassable connect issue_slots[0].uop.exc_cause, slots_0.io.uop.exc_cause connect issue_slots[0].uop.exception, slots_0.io.uop.exception connect issue_slots[0].uop.stale_pdst, slots_0.io.uop.stale_pdst connect issue_slots[0].uop.ppred_busy, slots_0.io.uop.ppred_busy connect issue_slots[0].uop.prs3_busy, slots_0.io.uop.prs3_busy connect issue_slots[0].uop.prs2_busy, slots_0.io.uop.prs2_busy connect issue_slots[0].uop.prs1_busy, slots_0.io.uop.prs1_busy connect issue_slots[0].uop.ppred, slots_0.io.uop.ppred connect issue_slots[0].uop.prs3, slots_0.io.uop.prs3 connect issue_slots[0].uop.prs2, slots_0.io.uop.prs2 connect issue_slots[0].uop.prs1, slots_0.io.uop.prs1 connect issue_slots[0].uop.pdst, slots_0.io.uop.pdst connect issue_slots[0].uop.rxq_idx, slots_0.io.uop.rxq_idx connect issue_slots[0].uop.stq_idx, slots_0.io.uop.stq_idx connect issue_slots[0].uop.ldq_idx, slots_0.io.uop.ldq_idx connect issue_slots[0].uop.rob_idx, slots_0.io.uop.rob_idx connect issue_slots[0].uop.csr_addr, slots_0.io.uop.csr_addr connect issue_slots[0].uop.imm_packed, slots_0.io.uop.imm_packed connect issue_slots[0].uop.taken, slots_0.io.uop.taken connect issue_slots[0].uop.pc_lob, slots_0.io.uop.pc_lob connect issue_slots[0].uop.edge_inst, slots_0.io.uop.edge_inst connect issue_slots[0].uop.ftq_idx, slots_0.io.uop.ftq_idx connect issue_slots[0].uop.br_tag, slots_0.io.uop.br_tag connect issue_slots[0].uop.br_mask, slots_0.io.uop.br_mask connect issue_slots[0].uop.is_sfb, slots_0.io.uop.is_sfb connect issue_slots[0].uop.is_jal, slots_0.io.uop.is_jal connect issue_slots[0].uop.is_jalr, slots_0.io.uop.is_jalr connect issue_slots[0].uop.is_br, slots_0.io.uop.is_br connect issue_slots[0].uop.iw_p2_poisoned, slots_0.io.uop.iw_p2_poisoned connect issue_slots[0].uop.iw_p1_poisoned, slots_0.io.uop.iw_p1_poisoned connect issue_slots[0].uop.iw_state, slots_0.io.uop.iw_state connect issue_slots[0].uop.ctrl.is_std, slots_0.io.uop.ctrl.is_std connect issue_slots[0].uop.ctrl.is_sta, slots_0.io.uop.ctrl.is_sta connect issue_slots[0].uop.ctrl.is_load, slots_0.io.uop.ctrl.is_load connect issue_slots[0].uop.ctrl.csr_cmd, slots_0.io.uop.ctrl.csr_cmd connect issue_slots[0].uop.ctrl.fcn_dw, slots_0.io.uop.ctrl.fcn_dw connect issue_slots[0].uop.ctrl.op_fcn, slots_0.io.uop.ctrl.op_fcn connect issue_slots[0].uop.ctrl.imm_sel, slots_0.io.uop.ctrl.imm_sel connect issue_slots[0].uop.ctrl.op2_sel, slots_0.io.uop.ctrl.op2_sel connect issue_slots[0].uop.ctrl.op1_sel, slots_0.io.uop.ctrl.op1_sel connect issue_slots[0].uop.ctrl.br_type, slots_0.io.uop.ctrl.br_type connect issue_slots[0].uop.fu_code, slots_0.io.uop.fu_code connect issue_slots[0].uop.iq_type, slots_0.io.uop.iq_type connect issue_slots[0].uop.debug_pc, slots_0.io.uop.debug_pc connect issue_slots[0].uop.is_rvc, slots_0.io.uop.is_rvc connect issue_slots[0].uop.debug_inst, slots_0.io.uop.debug_inst connect issue_slots[0].uop.inst, slots_0.io.uop.inst connect issue_slots[0].uop.uopc, slots_0.io.uop.uopc connect issue_slots[0].out_uop.debug_tsrc, slots_0.io.out_uop.debug_tsrc connect issue_slots[0].out_uop.debug_fsrc, slots_0.io.out_uop.debug_fsrc connect issue_slots[0].out_uop.bp_xcpt_if, slots_0.io.out_uop.bp_xcpt_if connect issue_slots[0].out_uop.bp_debug_if, slots_0.io.out_uop.bp_debug_if connect issue_slots[0].out_uop.xcpt_ma_if, slots_0.io.out_uop.xcpt_ma_if connect issue_slots[0].out_uop.xcpt_ae_if, slots_0.io.out_uop.xcpt_ae_if connect issue_slots[0].out_uop.xcpt_pf_if, slots_0.io.out_uop.xcpt_pf_if connect issue_slots[0].out_uop.fp_single, slots_0.io.out_uop.fp_single connect issue_slots[0].out_uop.fp_val, slots_0.io.out_uop.fp_val connect issue_slots[0].out_uop.frs3_en, slots_0.io.out_uop.frs3_en connect issue_slots[0].out_uop.lrs2_rtype, slots_0.io.out_uop.lrs2_rtype connect issue_slots[0].out_uop.lrs1_rtype, slots_0.io.out_uop.lrs1_rtype connect issue_slots[0].out_uop.dst_rtype, slots_0.io.out_uop.dst_rtype connect issue_slots[0].out_uop.ldst_val, slots_0.io.out_uop.ldst_val connect issue_slots[0].out_uop.lrs3, slots_0.io.out_uop.lrs3 connect issue_slots[0].out_uop.lrs2, slots_0.io.out_uop.lrs2 connect issue_slots[0].out_uop.lrs1, slots_0.io.out_uop.lrs1 connect issue_slots[0].out_uop.ldst, slots_0.io.out_uop.ldst connect issue_slots[0].out_uop.ldst_is_rs1, slots_0.io.out_uop.ldst_is_rs1 connect issue_slots[0].out_uop.flush_on_commit, slots_0.io.out_uop.flush_on_commit connect issue_slots[0].out_uop.is_unique, slots_0.io.out_uop.is_unique connect issue_slots[0].out_uop.is_sys_pc2epc, slots_0.io.out_uop.is_sys_pc2epc connect issue_slots[0].out_uop.uses_stq, slots_0.io.out_uop.uses_stq connect issue_slots[0].out_uop.uses_ldq, slots_0.io.out_uop.uses_ldq connect issue_slots[0].out_uop.is_amo, slots_0.io.out_uop.is_amo connect issue_slots[0].out_uop.is_fencei, slots_0.io.out_uop.is_fencei connect issue_slots[0].out_uop.is_fence, slots_0.io.out_uop.is_fence connect issue_slots[0].out_uop.mem_signed, slots_0.io.out_uop.mem_signed connect issue_slots[0].out_uop.mem_size, slots_0.io.out_uop.mem_size connect issue_slots[0].out_uop.mem_cmd, slots_0.io.out_uop.mem_cmd connect issue_slots[0].out_uop.bypassable, slots_0.io.out_uop.bypassable connect issue_slots[0].out_uop.exc_cause, slots_0.io.out_uop.exc_cause connect issue_slots[0].out_uop.exception, slots_0.io.out_uop.exception connect issue_slots[0].out_uop.stale_pdst, slots_0.io.out_uop.stale_pdst connect issue_slots[0].out_uop.ppred_busy, slots_0.io.out_uop.ppred_busy connect issue_slots[0].out_uop.prs3_busy, slots_0.io.out_uop.prs3_busy connect issue_slots[0].out_uop.prs2_busy, slots_0.io.out_uop.prs2_busy connect issue_slots[0].out_uop.prs1_busy, slots_0.io.out_uop.prs1_busy connect issue_slots[0].out_uop.ppred, slots_0.io.out_uop.ppred connect issue_slots[0].out_uop.prs3, slots_0.io.out_uop.prs3 connect issue_slots[0].out_uop.prs2, slots_0.io.out_uop.prs2 connect issue_slots[0].out_uop.prs1, slots_0.io.out_uop.prs1 connect issue_slots[0].out_uop.pdst, slots_0.io.out_uop.pdst connect issue_slots[0].out_uop.rxq_idx, slots_0.io.out_uop.rxq_idx connect issue_slots[0].out_uop.stq_idx, slots_0.io.out_uop.stq_idx connect issue_slots[0].out_uop.ldq_idx, slots_0.io.out_uop.ldq_idx connect issue_slots[0].out_uop.rob_idx, slots_0.io.out_uop.rob_idx connect issue_slots[0].out_uop.csr_addr, slots_0.io.out_uop.csr_addr connect issue_slots[0].out_uop.imm_packed, slots_0.io.out_uop.imm_packed connect issue_slots[0].out_uop.taken, slots_0.io.out_uop.taken connect issue_slots[0].out_uop.pc_lob, slots_0.io.out_uop.pc_lob connect issue_slots[0].out_uop.edge_inst, slots_0.io.out_uop.edge_inst connect issue_slots[0].out_uop.ftq_idx, slots_0.io.out_uop.ftq_idx connect issue_slots[0].out_uop.br_tag, slots_0.io.out_uop.br_tag connect issue_slots[0].out_uop.br_mask, slots_0.io.out_uop.br_mask connect issue_slots[0].out_uop.is_sfb, slots_0.io.out_uop.is_sfb connect issue_slots[0].out_uop.is_jal, slots_0.io.out_uop.is_jal connect issue_slots[0].out_uop.is_jalr, slots_0.io.out_uop.is_jalr connect issue_slots[0].out_uop.is_br, slots_0.io.out_uop.is_br connect issue_slots[0].out_uop.iw_p2_poisoned, slots_0.io.out_uop.iw_p2_poisoned connect issue_slots[0].out_uop.iw_p1_poisoned, slots_0.io.out_uop.iw_p1_poisoned connect issue_slots[0].out_uop.iw_state, slots_0.io.out_uop.iw_state connect issue_slots[0].out_uop.ctrl.is_std, slots_0.io.out_uop.ctrl.is_std connect issue_slots[0].out_uop.ctrl.is_sta, slots_0.io.out_uop.ctrl.is_sta connect issue_slots[0].out_uop.ctrl.is_load, slots_0.io.out_uop.ctrl.is_load connect issue_slots[0].out_uop.ctrl.csr_cmd, slots_0.io.out_uop.ctrl.csr_cmd connect issue_slots[0].out_uop.ctrl.fcn_dw, slots_0.io.out_uop.ctrl.fcn_dw connect issue_slots[0].out_uop.ctrl.op_fcn, slots_0.io.out_uop.ctrl.op_fcn connect issue_slots[0].out_uop.ctrl.imm_sel, slots_0.io.out_uop.ctrl.imm_sel connect issue_slots[0].out_uop.ctrl.op2_sel, slots_0.io.out_uop.ctrl.op2_sel connect issue_slots[0].out_uop.ctrl.op1_sel, slots_0.io.out_uop.ctrl.op1_sel connect issue_slots[0].out_uop.ctrl.br_type, slots_0.io.out_uop.ctrl.br_type connect issue_slots[0].out_uop.fu_code, slots_0.io.out_uop.fu_code connect issue_slots[0].out_uop.iq_type, slots_0.io.out_uop.iq_type connect issue_slots[0].out_uop.debug_pc, slots_0.io.out_uop.debug_pc connect issue_slots[0].out_uop.is_rvc, slots_0.io.out_uop.is_rvc connect issue_slots[0].out_uop.debug_inst, slots_0.io.out_uop.debug_inst connect issue_slots[0].out_uop.inst, slots_0.io.out_uop.inst connect issue_slots[0].out_uop.uopc, slots_0.io.out_uop.uopc connect slots_0.io.in_uop.bits.debug_tsrc, issue_slots[0].in_uop.bits.debug_tsrc connect slots_0.io.in_uop.bits.debug_fsrc, issue_slots[0].in_uop.bits.debug_fsrc connect slots_0.io.in_uop.bits.bp_xcpt_if, issue_slots[0].in_uop.bits.bp_xcpt_if connect slots_0.io.in_uop.bits.bp_debug_if, issue_slots[0].in_uop.bits.bp_debug_if connect slots_0.io.in_uop.bits.xcpt_ma_if, issue_slots[0].in_uop.bits.xcpt_ma_if connect slots_0.io.in_uop.bits.xcpt_ae_if, issue_slots[0].in_uop.bits.xcpt_ae_if connect slots_0.io.in_uop.bits.xcpt_pf_if, issue_slots[0].in_uop.bits.xcpt_pf_if connect slots_0.io.in_uop.bits.fp_single, issue_slots[0].in_uop.bits.fp_single connect slots_0.io.in_uop.bits.fp_val, issue_slots[0].in_uop.bits.fp_val connect slots_0.io.in_uop.bits.frs3_en, issue_slots[0].in_uop.bits.frs3_en connect slots_0.io.in_uop.bits.lrs2_rtype, issue_slots[0].in_uop.bits.lrs2_rtype connect slots_0.io.in_uop.bits.lrs1_rtype, issue_slots[0].in_uop.bits.lrs1_rtype connect slots_0.io.in_uop.bits.dst_rtype, issue_slots[0].in_uop.bits.dst_rtype connect slots_0.io.in_uop.bits.ldst_val, issue_slots[0].in_uop.bits.ldst_val connect slots_0.io.in_uop.bits.lrs3, issue_slots[0].in_uop.bits.lrs3 connect slots_0.io.in_uop.bits.lrs2, issue_slots[0].in_uop.bits.lrs2 connect slots_0.io.in_uop.bits.lrs1, issue_slots[0].in_uop.bits.lrs1 connect slots_0.io.in_uop.bits.ldst, issue_slots[0].in_uop.bits.ldst connect slots_0.io.in_uop.bits.ldst_is_rs1, issue_slots[0].in_uop.bits.ldst_is_rs1 connect slots_0.io.in_uop.bits.flush_on_commit, issue_slots[0].in_uop.bits.flush_on_commit connect slots_0.io.in_uop.bits.is_unique, issue_slots[0].in_uop.bits.is_unique connect slots_0.io.in_uop.bits.is_sys_pc2epc, issue_slots[0].in_uop.bits.is_sys_pc2epc connect slots_0.io.in_uop.bits.uses_stq, issue_slots[0].in_uop.bits.uses_stq connect slots_0.io.in_uop.bits.uses_ldq, issue_slots[0].in_uop.bits.uses_ldq connect slots_0.io.in_uop.bits.is_amo, issue_slots[0].in_uop.bits.is_amo connect slots_0.io.in_uop.bits.is_fencei, issue_slots[0].in_uop.bits.is_fencei connect slots_0.io.in_uop.bits.is_fence, issue_slots[0].in_uop.bits.is_fence connect slots_0.io.in_uop.bits.mem_signed, issue_slots[0].in_uop.bits.mem_signed connect slots_0.io.in_uop.bits.mem_size, issue_slots[0].in_uop.bits.mem_size connect slots_0.io.in_uop.bits.mem_cmd, issue_slots[0].in_uop.bits.mem_cmd connect slots_0.io.in_uop.bits.bypassable, issue_slots[0].in_uop.bits.bypassable connect slots_0.io.in_uop.bits.exc_cause, issue_slots[0].in_uop.bits.exc_cause connect slots_0.io.in_uop.bits.exception, issue_slots[0].in_uop.bits.exception connect slots_0.io.in_uop.bits.stale_pdst, issue_slots[0].in_uop.bits.stale_pdst connect slots_0.io.in_uop.bits.ppred_busy, issue_slots[0].in_uop.bits.ppred_busy connect slots_0.io.in_uop.bits.prs3_busy, issue_slots[0].in_uop.bits.prs3_busy connect slots_0.io.in_uop.bits.prs2_busy, issue_slots[0].in_uop.bits.prs2_busy connect slots_0.io.in_uop.bits.prs1_busy, issue_slots[0].in_uop.bits.prs1_busy connect slots_0.io.in_uop.bits.ppred, issue_slots[0].in_uop.bits.ppred connect slots_0.io.in_uop.bits.prs3, issue_slots[0].in_uop.bits.prs3 connect slots_0.io.in_uop.bits.prs2, issue_slots[0].in_uop.bits.prs2 connect slots_0.io.in_uop.bits.prs1, issue_slots[0].in_uop.bits.prs1 connect slots_0.io.in_uop.bits.pdst, issue_slots[0].in_uop.bits.pdst connect slots_0.io.in_uop.bits.rxq_idx, issue_slots[0].in_uop.bits.rxq_idx connect slots_0.io.in_uop.bits.stq_idx, issue_slots[0].in_uop.bits.stq_idx connect slots_0.io.in_uop.bits.ldq_idx, issue_slots[0].in_uop.bits.ldq_idx connect slots_0.io.in_uop.bits.rob_idx, issue_slots[0].in_uop.bits.rob_idx connect slots_0.io.in_uop.bits.csr_addr, issue_slots[0].in_uop.bits.csr_addr connect slots_0.io.in_uop.bits.imm_packed, issue_slots[0].in_uop.bits.imm_packed connect slots_0.io.in_uop.bits.taken, issue_slots[0].in_uop.bits.taken connect slots_0.io.in_uop.bits.pc_lob, issue_slots[0].in_uop.bits.pc_lob connect slots_0.io.in_uop.bits.edge_inst, issue_slots[0].in_uop.bits.edge_inst connect slots_0.io.in_uop.bits.ftq_idx, issue_slots[0].in_uop.bits.ftq_idx connect slots_0.io.in_uop.bits.br_tag, issue_slots[0].in_uop.bits.br_tag connect slots_0.io.in_uop.bits.br_mask, issue_slots[0].in_uop.bits.br_mask connect slots_0.io.in_uop.bits.is_sfb, issue_slots[0].in_uop.bits.is_sfb connect slots_0.io.in_uop.bits.is_jal, issue_slots[0].in_uop.bits.is_jal connect slots_0.io.in_uop.bits.is_jalr, issue_slots[0].in_uop.bits.is_jalr connect slots_0.io.in_uop.bits.is_br, issue_slots[0].in_uop.bits.is_br connect slots_0.io.in_uop.bits.iw_p2_poisoned, issue_slots[0].in_uop.bits.iw_p2_poisoned connect slots_0.io.in_uop.bits.iw_p1_poisoned, issue_slots[0].in_uop.bits.iw_p1_poisoned connect slots_0.io.in_uop.bits.iw_state, issue_slots[0].in_uop.bits.iw_state connect slots_0.io.in_uop.bits.ctrl.is_std, issue_slots[0].in_uop.bits.ctrl.is_std connect slots_0.io.in_uop.bits.ctrl.is_sta, issue_slots[0].in_uop.bits.ctrl.is_sta connect slots_0.io.in_uop.bits.ctrl.is_load, issue_slots[0].in_uop.bits.ctrl.is_load connect slots_0.io.in_uop.bits.ctrl.csr_cmd, issue_slots[0].in_uop.bits.ctrl.csr_cmd connect slots_0.io.in_uop.bits.ctrl.fcn_dw, issue_slots[0].in_uop.bits.ctrl.fcn_dw connect slots_0.io.in_uop.bits.ctrl.op_fcn, issue_slots[0].in_uop.bits.ctrl.op_fcn connect slots_0.io.in_uop.bits.ctrl.imm_sel, issue_slots[0].in_uop.bits.ctrl.imm_sel connect slots_0.io.in_uop.bits.ctrl.op2_sel, issue_slots[0].in_uop.bits.ctrl.op2_sel connect slots_0.io.in_uop.bits.ctrl.op1_sel, issue_slots[0].in_uop.bits.ctrl.op1_sel connect slots_0.io.in_uop.bits.ctrl.br_type, issue_slots[0].in_uop.bits.ctrl.br_type connect slots_0.io.in_uop.bits.fu_code, issue_slots[0].in_uop.bits.fu_code connect slots_0.io.in_uop.bits.iq_type, issue_slots[0].in_uop.bits.iq_type connect slots_0.io.in_uop.bits.debug_pc, issue_slots[0].in_uop.bits.debug_pc connect slots_0.io.in_uop.bits.is_rvc, issue_slots[0].in_uop.bits.is_rvc connect slots_0.io.in_uop.bits.debug_inst, issue_slots[0].in_uop.bits.debug_inst connect slots_0.io.in_uop.bits.inst, issue_slots[0].in_uop.bits.inst connect slots_0.io.in_uop.bits.uopc, issue_slots[0].in_uop.bits.uopc connect slots_0.io.in_uop.valid, issue_slots[0].in_uop.valid connect slots_0.io.spec_ld_wakeup[0].bits, issue_slots[0].spec_ld_wakeup[0].bits connect slots_0.io.spec_ld_wakeup[0].valid, issue_slots[0].spec_ld_wakeup[0].valid connect slots_0.io.pred_wakeup_port.bits, issue_slots[0].pred_wakeup_port.bits connect slots_0.io.pred_wakeup_port.valid, issue_slots[0].pred_wakeup_port.valid connect slots_0.io.wakeup_ports[0].bits.poisoned, issue_slots[0].wakeup_ports[0].bits.poisoned connect slots_0.io.wakeup_ports[0].bits.pdst, issue_slots[0].wakeup_ports[0].bits.pdst connect slots_0.io.wakeup_ports[0].valid, issue_slots[0].wakeup_ports[0].valid connect slots_0.io.wakeup_ports[1].bits.poisoned, issue_slots[0].wakeup_ports[1].bits.poisoned connect slots_0.io.wakeup_ports[1].bits.pdst, issue_slots[0].wakeup_ports[1].bits.pdst connect slots_0.io.wakeup_ports[1].valid, issue_slots[0].wakeup_ports[1].valid connect slots_0.io.ldspec_miss, issue_slots[0].ldspec_miss connect slots_0.io.clear, issue_slots[0].clear connect slots_0.io.kill, issue_slots[0].kill connect slots_0.io.brupdate.b2.target_offset, issue_slots[0].brupdate.b2.target_offset connect slots_0.io.brupdate.b2.jalr_target, issue_slots[0].brupdate.b2.jalr_target connect slots_0.io.brupdate.b2.pc_sel, issue_slots[0].brupdate.b2.pc_sel connect slots_0.io.brupdate.b2.cfi_type, issue_slots[0].brupdate.b2.cfi_type connect slots_0.io.brupdate.b2.taken, issue_slots[0].brupdate.b2.taken connect slots_0.io.brupdate.b2.mispredict, issue_slots[0].brupdate.b2.mispredict connect slots_0.io.brupdate.b2.valid, issue_slots[0].brupdate.b2.valid connect slots_0.io.brupdate.b2.uop.debug_tsrc, issue_slots[0].brupdate.b2.uop.debug_tsrc connect slots_0.io.brupdate.b2.uop.debug_fsrc, issue_slots[0].brupdate.b2.uop.debug_fsrc connect slots_0.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[0].brupdate.b2.uop.bp_xcpt_if connect slots_0.io.brupdate.b2.uop.bp_debug_if, issue_slots[0].brupdate.b2.uop.bp_debug_if connect slots_0.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[0].brupdate.b2.uop.xcpt_ma_if connect slots_0.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[0].brupdate.b2.uop.xcpt_ae_if connect slots_0.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[0].brupdate.b2.uop.xcpt_pf_if connect slots_0.io.brupdate.b2.uop.fp_single, issue_slots[0].brupdate.b2.uop.fp_single connect slots_0.io.brupdate.b2.uop.fp_val, issue_slots[0].brupdate.b2.uop.fp_val connect slots_0.io.brupdate.b2.uop.frs3_en, issue_slots[0].brupdate.b2.uop.frs3_en connect slots_0.io.brupdate.b2.uop.lrs2_rtype, issue_slots[0].brupdate.b2.uop.lrs2_rtype connect slots_0.io.brupdate.b2.uop.lrs1_rtype, issue_slots[0].brupdate.b2.uop.lrs1_rtype connect slots_0.io.brupdate.b2.uop.dst_rtype, issue_slots[0].brupdate.b2.uop.dst_rtype connect slots_0.io.brupdate.b2.uop.ldst_val, issue_slots[0].brupdate.b2.uop.ldst_val connect slots_0.io.brupdate.b2.uop.lrs3, issue_slots[0].brupdate.b2.uop.lrs3 connect slots_0.io.brupdate.b2.uop.lrs2, issue_slots[0].brupdate.b2.uop.lrs2 connect slots_0.io.brupdate.b2.uop.lrs1, issue_slots[0].brupdate.b2.uop.lrs1 connect slots_0.io.brupdate.b2.uop.ldst, issue_slots[0].brupdate.b2.uop.ldst connect slots_0.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[0].brupdate.b2.uop.ldst_is_rs1 connect slots_0.io.brupdate.b2.uop.flush_on_commit, issue_slots[0].brupdate.b2.uop.flush_on_commit connect slots_0.io.brupdate.b2.uop.is_unique, issue_slots[0].brupdate.b2.uop.is_unique connect slots_0.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[0].brupdate.b2.uop.is_sys_pc2epc connect slots_0.io.brupdate.b2.uop.uses_stq, issue_slots[0].brupdate.b2.uop.uses_stq connect slots_0.io.brupdate.b2.uop.uses_ldq, issue_slots[0].brupdate.b2.uop.uses_ldq connect slots_0.io.brupdate.b2.uop.is_amo, issue_slots[0].brupdate.b2.uop.is_amo connect slots_0.io.brupdate.b2.uop.is_fencei, issue_slots[0].brupdate.b2.uop.is_fencei connect slots_0.io.brupdate.b2.uop.is_fence, issue_slots[0].brupdate.b2.uop.is_fence connect slots_0.io.brupdate.b2.uop.mem_signed, issue_slots[0].brupdate.b2.uop.mem_signed connect slots_0.io.brupdate.b2.uop.mem_size, issue_slots[0].brupdate.b2.uop.mem_size connect slots_0.io.brupdate.b2.uop.mem_cmd, issue_slots[0].brupdate.b2.uop.mem_cmd connect slots_0.io.brupdate.b2.uop.bypassable, issue_slots[0].brupdate.b2.uop.bypassable connect slots_0.io.brupdate.b2.uop.exc_cause, issue_slots[0].brupdate.b2.uop.exc_cause connect slots_0.io.brupdate.b2.uop.exception, issue_slots[0].brupdate.b2.uop.exception connect slots_0.io.brupdate.b2.uop.stale_pdst, issue_slots[0].brupdate.b2.uop.stale_pdst connect slots_0.io.brupdate.b2.uop.ppred_busy, issue_slots[0].brupdate.b2.uop.ppred_busy connect slots_0.io.brupdate.b2.uop.prs3_busy, issue_slots[0].brupdate.b2.uop.prs3_busy connect slots_0.io.brupdate.b2.uop.prs2_busy, issue_slots[0].brupdate.b2.uop.prs2_busy connect slots_0.io.brupdate.b2.uop.prs1_busy, issue_slots[0].brupdate.b2.uop.prs1_busy connect slots_0.io.brupdate.b2.uop.ppred, issue_slots[0].brupdate.b2.uop.ppred connect slots_0.io.brupdate.b2.uop.prs3, issue_slots[0].brupdate.b2.uop.prs3 connect slots_0.io.brupdate.b2.uop.prs2, issue_slots[0].brupdate.b2.uop.prs2 connect slots_0.io.brupdate.b2.uop.prs1, issue_slots[0].brupdate.b2.uop.prs1 connect slots_0.io.brupdate.b2.uop.pdst, issue_slots[0].brupdate.b2.uop.pdst connect slots_0.io.brupdate.b2.uop.rxq_idx, issue_slots[0].brupdate.b2.uop.rxq_idx connect slots_0.io.brupdate.b2.uop.stq_idx, issue_slots[0].brupdate.b2.uop.stq_idx connect slots_0.io.brupdate.b2.uop.ldq_idx, issue_slots[0].brupdate.b2.uop.ldq_idx connect slots_0.io.brupdate.b2.uop.rob_idx, issue_slots[0].brupdate.b2.uop.rob_idx connect slots_0.io.brupdate.b2.uop.csr_addr, issue_slots[0].brupdate.b2.uop.csr_addr connect slots_0.io.brupdate.b2.uop.imm_packed, issue_slots[0].brupdate.b2.uop.imm_packed connect slots_0.io.brupdate.b2.uop.taken, issue_slots[0].brupdate.b2.uop.taken connect slots_0.io.brupdate.b2.uop.pc_lob, issue_slots[0].brupdate.b2.uop.pc_lob connect slots_0.io.brupdate.b2.uop.edge_inst, issue_slots[0].brupdate.b2.uop.edge_inst connect slots_0.io.brupdate.b2.uop.ftq_idx, issue_slots[0].brupdate.b2.uop.ftq_idx connect slots_0.io.brupdate.b2.uop.br_tag, issue_slots[0].brupdate.b2.uop.br_tag connect slots_0.io.brupdate.b2.uop.br_mask, issue_slots[0].brupdate.b2.uop.br_mask connect slots_0.io.brupdate.b2.uop.is_sfb, issue_slots[0].brupdate.b2.uop.is_sfb connect slots_0.io.brupdate.b2.uop.is_jal, issue_slots[0].brupdate.b2.uop.is_jal connect slots_0.io.brupdate.b2.uop.is_jalr, issue_slots[0].brupdate.b2.uop.is_jalr connect slots_0.io.brupdate.b2.uop.is_br, issue_slots[0].brupdate.b2.uop.is_br connect slots_0.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[0].brupdate.b2.uop.iw_p2_poisoned connect slots_0.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[0].brupdate.b2.uop.iw_p1_poisoned connect slots_0.io.brupdate.b2.uop.iw_state, issue_slots[0].brupdate.b2.uop.iw_state connect slots_0.io.brupdate.b2.uop.ctrl.is_std, issue_slots[0].brupdate.b2.uop.ctrl.is_std connect slots_0.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[0].brupdate.b2.uop.ctrl.is_sta connect slots_0.io.brupdate.b2.uop.ctrl.is_load, issue_slots[0].brupdate.b2.uop.ctrl.is_load connect slots_0.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[0].brupdate.b2.uop.ctrl.csr_cmd connect slots_0.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[0].brupdate.b2.uop.ctrl.fcn_dw connect slots_0.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[0].brupdate.b2.uop.ctrl.op_fcn connect slots_0.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[0].brupdate.b2.uop.ctrl.imm_sel connect slots_0.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[0].brupdate.b2.uop.ctrl.op2_sel connect slots_0.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[0].brupdate.b2.uop.ctrl.op1_sel connect slots_0.io.brupdate.b2.uop.ctrl.br_type, issue_slots[0].brupdate.b2.uop.ctrl.br_type connect slots_0.io.brupdate.b2.uop.fu_code, issue_slots[0].brupdate.b2.uop.fu_code connect slots_0.io.brupdate.b2.uop.iq_type, issue_slots[0].brupdate.b2.uop.iq_type connect slots_0.io.brupdate.b2.uop.debug_pc, issue_slots[0].brupdate.b2.uop.debug_pc connect slots_0.io.brupdate.b2.uop.is_rvc, issue_slots[0].brupdate.b2.uop.is_rvc connect slots_0.io.brupdate.b2.uop.debug_inst, issue_slots[0].brupdate.b2.uop.debug_inst connect slots_0.io.brupdate.b2.uop.inst, issue_slots[0].brupdate.b2.uop.inst connect slots_0.io.brupdate.b2.uop.uopc, issue_slots[0].brupdate.b2.uop.uopc connect slots_0.io.brupdate.b1.mispredict_mask, issue_slots[0].brupdate.b1.mispredict_mask connect slots_0.io.brupdate.b1.resolve_mask, issue_slots[0].brupdate.b1.resolve_mask connect slots_0.io.grant, issue_slots[0].grant connect issue_slots[0].request_hp, slots_0.io.request_hp connect issue_slots[0].request, slots_0.io.request connect issue_slots[0].will_be_valid, slots_0.io.will_be_valid connect issue_slots[0].valid, slots_0.io.valid connect issue_slots[1].debug.state, slots_1.io.debug.state connect issue_slots[1].debug.ppred, slots_1.io.debug.ppred connect issue_slots[1].debug.p3, slots_1.io.debug.p3 connect issue_slots[1].debug.p2, slots_1.io.debug.p2 connect issue_slots[1].debug.p1, slots_1.io.debug.p1 connect issue_slots[1].uop.debug_tsrc, slots_1.io.uop.debug_tsrc connect issue_slots[1].uop.debug_fsrc, slots_1.io.uop.debug_fsrc connect issue_slots[1].uop.bp_xcpt_if, slots_1.io.uop.bp_xcpt_if connect issue_slots[1].uop.bp_debug_if, slots_1.io.uop.bp_debug_if connect issue_slots[1].uop.xcpt_ma_if, slots_1.io.uop.xcpt_ma_if connect issue_slots[1].uop.xcpt_ae_if, slots_1.io.uop.xcpt_ae_if connect issue_slots[1].uop.xcpt_pf_if, slots_1.io.uop.xcpt_pf_if connect issue_slots[1].uop.fp_single, slots_1.io.uop.fp_single connect issue_slots[1].uop.fp_val, slots_1.io.uop.fp_val connect issue_slots[1].uop.frs3_en, slots_1.io.uop.frs3_en connect issue_slots[1].uop.lrs2_rtype, slots_1.io.uop.lrs2_rtype connect issue_slots[1].uop.lrs1_rtype, slots_1.io.uop.lrs1_rtype connect issue_slots[1].uop.dst_rtype, slots_1.io.uop.dst_rtype connect issue_slots[1].uop.ldst_val, slots_1.io.uop.ldst_val connect issue_slots[1].uop.lrs3, slots_1.io.uop.lrs3 connect issue_slots[1].uop.lrs2, slots_1.io.uop.lrs2 connect issue_slots[1].uop.lrs1, slots_1.io.uop.lrs1 connect issue_slots[1].uop.ldst, slots_1.io.uop.ldst connect issue_slots[1].uop.ldst_is_rs1, slots_1.io.uop.ldst_is_rs1 connect issue_slots[1].uop.flush_on_commit, slots_1.io.uop.flush_on_commit connect issue_slots[1].uop.is_unique, slots_1.io.uop.is_unique connect issue_slots[1].uop.is_sys_pc2epc, slots_1.io.uop.is_sys_pc2epc connect issue_slots[1].uop.uses_stq, slots_1.io.uop.uses_stq connect issue_slots[1].uop.uses_ldq, slots_1.io.uop.uses_ldq connect issue_slots[1].uop.is_amo, slots_1.io.uop.is_amo connect issue_slots[1].uop.is_fencei, slots_1.io.uop.is_fencei connect issue_slots[1].uop.is_fence, slots_1.io.uop.is_fence connect issue_slots[1].uop.mem_signed, slots_1.io.uop.mem_signed connect issue_slots[1].uop.mem_size, slots_1.io.uop.mem_size connect issue_slots[1].uop.mem_cmd, slots_1.io.uop.mem_cmd connect issue_slots[1].uop.bypassable, slots_1.io.uop.bypassable connect issue_slots[1].uop.exc_cause, slots_1.io.uop.exc_cause connect issue_slots[1].uop.exception, slots_1.io.uop.exception connect issue_slots[1].uop.stale_pdst, slots_1.io.uop.stale_pdst connect issue_slots[1].uop.ppred_busy, slots_1.io.uop.ppred_busy connect issue_slots[1].uop.prs3_busy, slots_1.io.uop.prs3_busy connect issue_slots[1].uop.prs2_busy, slots_1.io.uop.prs2_busy connect issue_slots[1].uop.prs1_busy, slots_1.io.uop.prs1_busy connect issue_slots[1].uop.ppred, slots_1.io.uop.ppred connect issue_slots[1].uop.prs3, slots_1.io.uop.prs3 connect issue_slots[1].uop.prs2, slots_1.io.uop.prs2 connect issue_slots[1].uop.prs1, slots_1.io.uop.prs1 connect issue_slots[1].uop.pdst, slots_1.io.uop.pdst connect issue_slots[1].uop.rxq_idx, slots_1.io.uop.rxq_idx connect issue_slots[1].uop.stq_idx, slots_1.io.uop.stq_idx connect issue_slots[1].uop.ldq_idx, slots_1.io.uop.ldq_idx connect issue_slots[1].uop.rob_idx, slots_1.io.uop.rob_idx connect issue_slots[1].uop.csr_addr, slots_1.io.uop.csr_addr connect issue_slots[1].uop.imm_packed, slots_1.io.uop.imm_packed connect issue_slots[1].uop.taken, slots_1.io.uop.taken connect issue_slots[1].uop.pc_lob, slots_1.io.uop.pc_lob connect issue_slots[1].uop.edge_inst, slots_1.io.uop.edge_inst connect issue_slots[1].uop.ftq_idx, slots_1.io.uop.ftq_idx connect issue_slots[1].uop.br_tag, slots_1.io.uop.br_tag connect issue_slots[1].uop.br_mask, slots_1.io.uop.br_mask connect issue_slots[1].uop.is_sfb, slots_1.io.uop.is_sfb connect issue_slots[1].uop.is_jal, slots_1.io.uop.is_jal connect issue_slots[1].uop.is_jalr, slots_1.io.uop.is_jalr connect issue_slots[1].uop.is_br, slots_1.io.uop.is_br connect issue_slots[1].uop.iw_p2_poisoned, slots_1.io.uop.iw_p2_poisoned connect issue_slots[1].uop.iw_p1_poisoned, slots_1.io.uop.iw_p1_poisoned connect issue_slots[1].uop.iw_state, slots_1.io.uop.iw_state connect issue_slots[1].uop.ctrl.is_std, slots_1.io.uop.ctrl.is_std connect issue_slots[1].uop.ctrl.is_sta, slots_1.io.uop.ctrl.is_sta connect issue_slots[1].uop.ctrl.is_load, slots_1.io.uop.ctrl.is_load connect issue_slots[1].uop.ctrl.csr_cmd, slots_1.io.uop.ctrl.csr_cmd connect issue_slots[1].uop.ctrl.fcn_dw, slots_1.io.uop.ctrl.fcn_dw connect issue_slots[1].uop.ctrl.op_fcn, slots_1.io.uop.ctrl.op_fcn connect issue_slots[1].uop.ctrl.imm_sel, slots_1.io.uop.ctrl.imm_sel connect issue_slots[1].uop.ctrl.op2_sel, slots_1.io.uop.ctrl.op2_sel connect issue_slots[1].uop.ctrl.op1_sel, slots_1.io.uop.ctrl.op1_sel connect issue_slots[1].uop.ctrl.br_type, slots_1.io.uop.ctrl.br_type connect issue_slots[1].uop.fu_code, slots_1.io.uop.fu_code connect issue_slots[1].uop.iq_type, slots_1.io.uop.iq_type connect issue_slots[1].uop.debug_pc, slots_1.io.uop.debug_pc connect issue_slots[1].uop.is_rvc, slots_1.io.uop.is_rvc connect issue_slots[1].uop.debug_inst, slots_1.io.uop.debug_inst connect issue_slots[1].uop.inst, slots_1.io.uop.inst connect issue_slots[1].uop.uopc, slots_1.io.uop.uopc connect issue_slots[1].out_uop.debug_tsrc, slots_1.io.out_uop.debug_tsrc connect issue_slots[1].out_uop.debug_fsrc, slots_1.io.out_uop.debug_fsrc connect issue_slots[1].out_uop.bp_xcpt_if, slots_1.io.out_uop.bp_xcpt_if connect issue_slots[1].out_uop.bp_debug_if, slots_1.io.out_uop.bp_debug_if connect issue_slots[1].out_uop.xcpt_ma_if, slots_1.io.out_uop.xcpt_ma_if connect issue_slots[1].out_uop.xcpt_ae_if, slots_1.io.out_uop.xcpt_ae_if connect issue_slots[1].out_uop.xcpt_pf_if, slots_1.io.out_uop.xcpt_pf_if connect issue_slots[1].out_uop.fp_single, slots_1.io.out_uop.fp_single connect issue_slots[1].out_uop.fp_val, slots_1.io.out_uop.fp_val connect issue_slots[1].out_uop.frs3_en, slots_1.io.out_uop.frs3_en connect issue_slots[1].out_uop.lrs2_rtype, slots_1.io.out_uop.lrs2_rtype connect issue_slots[1].out_uop.lrs1_rtype, slots_1.io.out_uop.lrs1_rtype connect issue_slots[1].out_uop.dst_rtype, slots_1.io.out_uop.dst_rtype connect issue_slots[1].out_uop.ldst_val, slots_1.io.out_uop.ldst_val connect issue_slots[1].out_uop.lrs3, slots_1.io.out_uop.lrs3 connect issue_slots[1].out_uop.lrs2, slots_1.io.out_uop.lrs2 connect issue_slots[1].out_uop.lrs1, slots_1.io.out_uop.lrs1 connect issue_slots[1].out_uop.ldst, slots_1.io.out_uop.ldst connect issue_slots[1].out_uop.ldst_is_rs1, slots_1.io.out_uop.ldst_is_rs1 connect issue_slots[1].out_uop.flush_on_commit, slots_1.io.out_uop.flush_on_commit connect issue_slots[1].out_uop.is_unique, slots_1.io.out_uop.is_unique connect issue_slots[1].out_uop.is_sys_pc2epc, slots_1.io.out_uop.is_sys_pc2epc connect issue_slots[1].out_uop.uses_stq, slots_1.io.out_uop.uses_stq connect issue_slots[1].out_uop.uses_ldq, slots_1.io.out_uop.uses_ldq connect issue_slots[1].out_uop.is_amo, slots_1.io.out_uop.is_amo connect issue_slots[1].out_uop.is_fencei, slots_1.io.out_uop.is_fencei connect issue_slots[1].out_uop.is_fence, slots_1.io.out_uop.is_fence connect issue_slots[1].out_uop.mem_signed, slots_1.io.out_uop.mem_signed connect issue_slots[1].out_uop.mem_size, slots_1.io.out_uop.mem_size connect issue_slots[1].out_uop.mem_cmd, slots_1.io.out_uop.mem_cmd connect issue_slots[1].out_uop.bypassable, slots_1.io.out_uop.bypassable connect issue_slots[1].out_uop.exc_cause, slots_1.io.out_uop.exc_cause connect issue_slots[1].out_uop.exception, slots_1.io.out_uop.exception connect issue_slots[1].out_uop.stale_pdst, slots_1.io.out_uop.stale_pdst connect issue_slots[1].out_uop.ppred_busy, slots_1.io.out_uop.ppred_busy connect issue_slots[1].out_uop.prs3_busy, slots_1.io.out_uop.prs3_busy connect issue_slots[1].out_uop.prs2_busy, slots_1.io.out_uop.prs2_busy connect issue_slots[1].out_uop.prs1_busy, slots_1.io.out_uop.prs1_busy connect issue_slots[1].out_uop.ppred, slots_1.io.out_uop.ppred connect issue_slots[1].out_uop.prs3, slots_1.io.out_uop.prs3 connect issue_slots[1].out_uop.prs2, slots_1.io.out_uop.prs2 connect issue_slots[1].out_uop.prs1, slots_1.io.out_uop.prs1 connect issue_slots[1].out_uop.pdst, slots_1.io.out_uop.pdst connect issue_slots[1].out_uop.rxq_idx, slots_1.io.out_uop.rxq_idx connect issue_slots[1].out_uop.stq_idx, slots_1.io.out_uop.stq_idx connect issue_slots[1].out_uop.ldq_idx, slots_1.io.out_uop.ldq_idx connect issue_slots[1].out_uop.rob_idx, slots_1.io.out_uop.rob_idx connect issue_slots[1].out_uop.csr_addr, slots_1.io.out_uop.csr_addr connect issue_slots[1].out_uop.imm_packed, slots_1.io.out_uop.imm_packed connect issue_slots[1].out_uop.taken, slots_1.io.out_uop.taken connect issue_slots[1].out_uop.pc_lob, slots_1.io.out_uop.pc_lob connect issue_slots[1].out_uop.edge_inst, slots_1.io.out_uop.edge_inst connect issue_slots[1].out_uop.ftq_idx, slots_1.io.out_uop.ftq_idx connect issue_slots[1].out_uop.br_tag, slots_1.io.out_uop.br_tag connect issue_slots[1].out_uop.br_mask, slots_1.io.out_uop.br_mask connect issue_slots[1].out_uop.is_sfb, slots_1.io.out_uop.is_sfb connect issue_slots[1].out_uop.is_jal, slots_1.io.out_uop.is_jal connect issue_slots[1].out_uop.is_jalr, slots_1.io.out_uop.is_jalr connect issue_slots[1].out_uop.is_br, slots_1.io.out_uop.is_br connect issue_slots[1].out_uop.iw_p2_poisoned, slots_1.io.out_uop.iw_p2_poisoned connect issue_slots[1].out_uop.iw_p1_poisoned, slots_1.io.out_uop.iw_p1_poisoned connect issue_slots[1].out_uop.iw_state, slots_1.io.out_uop.iw_state connect issue_slots[1].out_uop.ctrl.is_std, slots_1.io.out_uop.ctrl.is_std connect issue_slots[1].out_uop.ctrl.is_sta, slots_1.io.out_uop.ctrl.is_sta connect issue_slots[1].out_uop.ctrl.is_load, slots_1.io.out_uop.ctrl.is_load connect issue_slots[1].out_uop.ctrl.csr_cmd, slots_1.io.out_uop.ctrl.csr_cmd connect issue_slots[1].out_uop.ctrl.fcn_dw, slots_1.io.out_uop.ctrl.fcn_dw connect issue_slots[1].out_uop.ctrl.op_fcn, slots_1.io.out_uop.ctrl.op_fcn connect issue_slots[1].out_uop.ctrl.imm_sel, slots_1.io.out_uop.ctrl.imm_sel connect issue_slots[1].out_uop.ctrl.op2_sel, slots_1.io.out_uop.ctrl.op2_sel connect issue_slots[1].out_uop.ctrl.op1_sel, slots_1.io.out_uop.ctrl.op1_sel connect issue_slots[1].out_uop.ctrl.br_type, slots_1.io.out_uop.ctrl.br_type connect issue_slots[1].out_uop.fu_code, slots_1.io.out_uop.fu_code connect issue_slots[1].out_uop.iq_type, slots_1.io.out_uop.iq_type connect issue_slots[1].out_uop.debug_pc, slots_1.io.out_uop.debug_pc connect issue_slots[1].out_uop.is_rvc, slots_1.io.out_uop.is_rvc connect issue_slots[1].out_uop.debug_inst, slots_1.io.out_uop.debug_inst connect issue_slots[1].out_uop.inst, slots_1.io.out_uop.inst connect issue_slots[1].out_uop.uopc, slots_1.io.out_uop.uopc connect slots_1.io.in_uop.bits.debug_tsrc, issue_slots[1].in_uop.bits.debug_tsrc connect slots_1.io.in_uop.bits.debug_fsrc, issue_slots[1].in_uop.bits.debug_fsrc connect slots_1.io.in_uop.bits.bp_xcpt_if, issue_slots[1].in_uop.bits.bp_xcpt_if connect slots_1.io.in_uop.bits.bp_debug_if, issue_slots[1].in_uop.bits.bp_debug_if connect slots_1.io.in_uop.bits.xcpt_ma_if, issue_slots[1].in_uop.bits.xcpt_ma_if connect slots_1.io.in_uop.bits.xcpt_ae_if, issue_slots[1].in_uop.bits.xcpt_ae_if connect slots_1.io.in_uop.bits.xcpt_pf_if, issue_slots[1].in_uop.bits.xcpt_pf_if connect slots_1.io.in_uop.bits.fp_single, issue_slots[1].in_uop.bits.fp_single connect slots_1.io.in_uop.bits.fp_val, issue_slots[1].in_uop.bits.fp_val connect slots_1.io.in_uop.bits.frs3_en, issue_slots[1].in_uop.bits.frs3_en connect slots_1.io.in_uop.bits.lrs2_rtype, issue_slots[1].in_uop.bits.lrs2_rtype connect slots_1.io.in_uop.bits.lrs1_rtype, issue_slots[1].in_uop.bits.lrs1_rtype connect slots_1.io.in_uop.bits.dst_rtype, issue_slots[1].in_uop.bits.dst_rtype connect slots_1.io.in_uop.bits.ldst_val, issue_slots[1].in_uop.bits.ldst_val connect slots_1.io.in_uop.bits.lrs3, issue_slots[1].in_uop.bits.lrs3 connect slots_1.io.in_uop.bits.lrs2, issue_slots[1].in_uop.bits.lrs2 connect slots_1.io.in_uop.bits.lrs1, issue_slots[1].in_uop.bits.lrs1 connect slots_1.io.in_uop.bits.ldst, issue_slots[1].in_uop.bits.ldst connect slots_1.io.in_uop.bits.ldst_is_rs1, issue_slots[1].in_uop.bits.ldst_is_rs1 connect slots_1.io.in_uop.bits.flush_on_commit, issue_slots[1].in_uop.bits.flush_on_commit connect slots_1.io.in_uop.bits.is_unique, issue_slots[1].in_uop.bits.is_unique connect slots_1.io.in_uop.bits.is_sys_pc2epc, issue_slots[1].in_uop.bits.is_sys_pc2epc connect slots_1.io.in_uop.bits.uses_stq, issue_slots[1].in_uop.bits.uses_stq connect slots_1.io.in_uop.bits.uses_ldq, issue_slots[1].in_uop.bits.uses_ldq connect slots_1.io.in_uop.bits.is_amo, issue_slots[1].in_uop.bits.is_amo connect slots_1.io.in_uop.bits.is_fencei, issue_slots[1].in_uop.bits.is_fencei connect slots_1.io.in_uop.bits.is_fence, issue_slots[1].in_uop.bits.is_fence connect slots_1.io.in_uop.bits.mem_signed, issue_slots[1].in_uop.bits.mem_signed connect slots_1.io.in_uop.bits.mem_size, issue_slots[1].in_uop.bits.mem_size connect slots_1.io.in_uop.bits.mem_cmd, issue_slots[1].in_uop.bits.mem_cmd connect slots_1.io.in_uop.bits.bypassable, issue_slots[1].in_uop.bits.bypassable connect slots_1.io.in_uop.bits.exc_cause, issue_slots[1].in_uop.bits.exc_cause connect slots_1.io.in_uop.bits.exception, issue_slots[1].in_uop.bits.exception connect slots_1.io.in_uop.bits.stale_pdst, issue_slots[1].in_uop.bits.stale_pdst connect slots_1.io.in_uop.bits.ppred_busy, issue_slots[1].in_uop.bits.ppred_busy connect slots_1.io.in_uop.bits.prs3_busy, issue_slots[1].in_uop.bits.prs3_busy connect slots_1.io.in_uop.bits.prs2_busy, issue_slots[1].in_uop.bits.prs2_busy connect slots_1.io.in_uop.bits.prs1_busy, issue_slots[1].in_uop.bits.prs1_busy connect slots_1.io.in_uop.bits.ppred, issue_slots[1].in_uop.bits.ppred connect slots_1.io.in_uop.bits.prs3, issue_slots[1].in_uop.bits.prs3 connect slots_1.io.in_uop.bits.prs2, issue_slots[1].in_uop.bits.prs2 connect slots_1.io.in_uop.bits.prs1, issue_slots[1].in_uop.bits.prs1 connect slots_1.io.in_uop.bits.pdst, issue_slots[1].in_uop.bits.pdst connect slots_1.io.in_uop.bits.rxq_idx, issue_slots[1].in_uop.bits.rxq_idx connect slots_1.io.in_uop.bits.stq_idx, issue_slots[1].in_uop.bits.stq_idx connect slots_1.io.in_uop.bits.ldq_idx, issue_slots[1].in_uop.bits.ldq_idx connect slots_1.io.in_uop.bits.rob_idx, issue_slots[1].in_uop.bits.rob_idx connect slots_1.io.in_uop.bits.csr_addr, issue_slots[1].in_uop.bits.csr_addr connect slots_1.io.in_uop.bits.imm_packed, issue_slots[1].in_uop.bits.imm_packed connect slots_1.io.in_uop.bits.taken, issue_slots[1].in_uop.bits.taken connect slots_1.io.in_uop.bits.pc_lob, issue_slots[1].in_uop.bits.pc_lob connect slots_1.io.in_uop.bits.edge_inst, issue_slots[1].in_uop.bits.edge_inst connect slots_1.io.in_uop.bits.ftq_idx, issue_slots[1].in_uop.bits.ftq_idx connect slots_1.io.in_uop.bits.br_tag, issue_slots[1].in_uop.bits.br_tag connect slots_1.io.in_uop.bits.br_mask, issue_slots[1].in_uop.bits.br_mask connect slots_1.io.in_uop.bits.is_sfb, issue_slots[1].in_uop.bits.is_sfb connect slots_1.io.in_uop.bits.is_jal, issue_slots[1].in_uop.bits.is_jal connect slots_1.io.in_uop.bits.is_jalr, issue_slots[1].in_uop.bits.is_jalr connect slots_1.io.in_uop.bits.is_br, issue_slots[1].in_uop.bits.is_br connect slots_1.io.in_uop.bits.iw_p2_poisoned, issue_slots[1].in_uop.bits.iw_p2_poisoned connect slots_1.io.in_uop.bits.iw_p1_poisoned, issue_slots[1].in_uop.bits.iw_p1_poisoned connect slots_1.io.in_uop.bits.iw_state, issue_slots[1].in_uop.bits.iw_state connect slots_1.io.in_uop.bits.ctrl.is_std, issue_slots[1].in_uop.bits.ctrl.is_std connect slots_1.io.in_uop.bits.ctrl.is_sta, issue_slots[1].in_uop.bits.ctrl.is_sta connect slots_1.io.in_uop.bits.ctrl.is_load, issue_slots[1].in_uop.bits.ctrl.is_load connect slots_1.io.in_uop.bits.ctrl.csr_cmd, issue_slots[1].in_uop.bits.ctrl.csr_cmd connect slots_1.io.in_uop.bits.ctrl.fcn_dw, issue_slots[1].in_uop.bits.ctrl.fcn_dw connect slots_1.io.in_uop.bits.ctrl.op_fcn, issue_slots[1].in_uop.bits.ctrl.op_fcn connect slots_1.io.in_uop.bits.ctrl.imm_sel, issue_slots[1].in_uop.bits.ctrl.imm_sel connect slots_1.io.in_uop.bits.ctrl.op2_sel, issue_slots[1].in_uop.bits.ctrl.op2_sel connect slots_1.io.in_uop.bits.ctrl.op1_sel, issue_slots[1].in_uop.bits.ctrl.op1_sel connect slots_1.io.in_uop.bits.ctrl.br_type, issue_slots[1].in_uop.bits.ctrl.br_type connect slots_1.io.in_uop.bits.fu_code, issue_slots[1].in_uop.bits.fu_code connect slots_1.io.in_uop.bits.iq_type, issue_slots[1].in_uop.bits.iq_type connect slots_1.io.in_uop.bits.debug_pc, issue_slots[1].in_uop.bits.debug_pc connect slots_1.io.in_uop.bits.is_rvc, issue_slots[1].in_uop.bits.is_rvc connect slots_1.io.in_uop.bits.debug_inst, issue_slots[1].in_uop.bits.debug_inst connect slots_1.io.in_uop.bits.inst, issue_slots[1].in_uop.bits.inst connect slots_1.io.in_uop.bits.uopc, issue_slots[1].in_uop.bits.uopc connect slots_1.io.in_uop.valid, issue_slots[1].in_uop.valid connect slots_1.io.spec_ld_wakeup[0].bits, issue_slots[1].spec_ld_wakeup[0].bits connect slots_1.io.spec_ld_wakeup[0].valid, issue_slots[1].spec_ld_wakeup[0].valid connect slots_1.io.pred_wakeup_port.bits, issue_slots[1].pred_wakeup_port.bits connect slots_1.io.pred_wakeup_port.valid, issue_slots[1].pred_wakeup_port.valid connect slots_1.io.wakeup_ports[0].bits.poisoned, issue_slots[1].wakeup_ports[0].bits.poisoned connect slots_1.io.wakeup_ports[0].bits.pdst, issue_slots[1].wakeup_ports[0].bits.pdst connect slots_1.io.wakeup_ports[0].valid, issue_slots[1].wakeup_ports[0].valid connect slots_1.io.wakeup_ports[1].bits.poisoned, issue_slots[1].wakeup_ports[1].bits.poisoned connect slots_1.io.wakeup_ports[1].bits.pdst, issue_slots[1].wakeup_ports[1].bits.pdst connect slots_1.io.wakeup_ports[1].valid, issue_slots[1].wakeup_ports[1].valid connect slots_1.io.ldspec_miss, issue_slots[1].ldspec_miss connect slots_1.io.clear, issue_slots[1].clear connect slots_1.io.kill, issue_slots[1].kill connect slots_1.io.brupdate.b2.target_offset, issue_slots[1].brupdate.b2.target_offset connect slots_1.io.brupdate.b2.jalr_target, issue_slots[1].brupdate.b2.jalr_target connect slots_1.io.brupdate.b2.pc_sel, issue_slots[1].brupdate.b2.pc_sel connect slots_1.io.brupdate.b2.cfi_type, issue_slots[1].brupdate.b2.cfi_type connect slots_1.io.brupdate.b2.taken, issue_slots[1].brupdate.b2.taken connect slots_1.io.brupdate.b2.mispredict, issue_slots[1].brupdate.b2.mispredict connect slots_1.io.brupdate.b2.valid, issue_slots[1].brupdate.b2.valid connect slots_1.io.brupdate.b2.uop.debug_tsrc, issue_slots[1].brupdate.b2.uop.debug_tsrc connect slots_1.io.brupdate.b2.uop.debug_fsrc, issue_slots[1].brupdate.b2.uop.debug_fsrc connect slots_1.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[1].brupdate.b2.uop.bp_xcpt_if connect slots_1.io.brupdate.b2.uop.bp_debug_if, issue_slots[1].brupdate.b2.uop.bp_debug_if connect slots_1.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[1].brupdate.b2.uop.xcpt_ma_if connect slots_1.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[1].brupdate.b2.uop.xcpt_ae_if connect slots_1.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[1].brupdate.b2.uop.xcpt_pf_if connect slots_1.io.brupdate.b2.uop.fp_single, issue_slots[1].brupdate.b2.uop.fp_single connect slots_1.io.brupdate.b2.uop.fp_val, issue_slots[1].brupdate.b2.uop.fp_val connect slots_1.io.brupdate.b2.uop.frs3_en, issue_slots[1].brupdate.b2.uop.frs3_en connect slots_1.io.brupdate.b2.uop.lrs2_rtype, issue_slots[1].brupdate.b2.uop.lrs2_rtype connect slots_1.io.brupdate.b2.uop.lrs1_rtype, issue_slots[1].brupdate.b2.uop.lrs1_rtype connect slots_1.io.brupdate.b2.uop.dst_rtype, issue_slots[1].brupdate.b2.uop.dst_rtype connect slots_1.io.brupdate.b2.uop.ldst_val, issue_slots[1].brupdate.b2.uop.ldst_val connect slots_1.io.brupdate.b2.uop.lrs3, issue_slots[1].brupdate.b2.uop.lrs3 connect slots_1.io.brupdate.b2.uop.lrs2, issue_slots[1].brupdate.b2.uop.lrs2 connect slots_1.io.brupdate.b2.uop.lrs1, issue_slots[1].brupdate.b2.uop.lrs1 connect slots_1.io.brupdate.b2.uop.ldst, issue_slots[1].brupdate.b2.uop.ldst connect slots_1.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[1].brupdate.b2.uop.ldst_is_rs1 connect slots_1.io.brupdate.b2.uop.flush_on_commit, issue_slots[1].brupdate.b2.uop.flush_on_commit connect slots_1.io.brupdate.b2.uop.is_unique, issue_slots[1].brupdate.b2.uop.is_unique connect slots_1.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[1].brupdate.b2.uop.is_sys_pc2epc connect slots_1.io.brupdate.b2.uop.uses_stq, issue_slots[1].brupdate.b2.uop.uses_stq connect slots_1.io.brupdate.b2.uop.uses_ldq, issue_slots[1].brupdate.b2.uop.uses_ldq connect slots_1.io.brupdate.b2.uop.is_amo, issue_slots[1].brupdate.b2.uop.is_amo connect slots_1.io.brupdate.b2.uop.is_fencei, issue_slots[1].brupdate.b2.uop.is_fencei connect slots_1.io.brupdate.b2.uop.is_fence, issue_slots[1].brupdate.b2.uop.is_fence connect slots_1.io.brupdate.b2.uop.mem_signed, issue_slots[1].brupdate.b2.uop.mem_signed connect slots_1.io.brupdate.b2.uop.mem_size, issue_slots[1].brupdate.b2.uop.mem_size connect slots_1.io.brupdate.b2.uop.mem_cmd, issue_slots[1].brupdate.b2.uop.mem_cmd connect slots_1.io.brupdate.b2.uop.bypassable, issue_slots[1].brupdate.b2.uop.bypassable connect slots_1.io.brupdate.b2.uop.exc_cause, issue_slots[1].brupdate.b2.uop.exc_cause connect slots_1.io.brupdate.b2.uop.exception, issue_slots[1].brupdate.b2.uop.exception connect slots_1.io.brupdate.b2.uop.stale_pdst, issue_slots[1].brupdate.b2.uop.stale_pdst connect slots_1.io.brupdate.b2.uop.ppred_busy, issue_slots[1].brupdate.b2.uop.ppred_busy connect slots_1.io.brupdate.b2.uop.prs3_busy, issue_slots[1].brupdate.b2.uop.prs3_busy connect slots_1.io.brupdate.b2.uop.prs2_busy, issue_slots[1].brupdate.b2.uop.prs2_busy connect slots_1.io.brupdate.b2.uop.prs1_busy, issue_slots[1].brupdate.b2.uop.prs1_busy connect slots_1.io.brupdate.b2.uop.ppred, issue_slots[1].brupdate.b2.uop.ppred connect slots_1.io.brupdate.b2.uop.prs3, issue_slots[1].brupdate.b2.uop.prs3 connect slots_1.io.brupdate.b2.uop.prs2, issue_slots[1].brupdate.b2.uop.prs2 connect slots_1.io.brupdate.b2.uop.prs1, issue_slots[1].brupdate.b2.uop.prs1 connect slots_1.io.brupdate.b2.uop.pdst, issue_slots[1].brupdate.b2.uop.pdst connect slots_1.io.brupdate.b2.uop.rxq_idx, issue_slots[1].brupdate.b2.uop.rxq_idx connect slots_1.io.brupdate.b2.uop.stq_idx, issue_slots[1].brupdate.b2.uop.stq_idx connect slots_1.io.brupdate.b2.uop.ldq_idx, issue_slots[1].brupdate.b2.uop.ldq_idx connect slots_1.io.brupdate.b2.uop.rob_idx, issue_slots[1].brupdate.b2.uop.rob_idx connect slots_1.io.brupdate.b2.uop.csr_addr, issue_slots[1].brupdate.b2.uop.csr_addr connect slots_1.io.brupdate.b2.uop.imm_packed, issue_slots[1].brupdate.b2.uop.imm_packed connect slots_1.io.brupdate.b2.uop.taken, issue_slots[1].brupdate.b2.uop.taken connect slots_1.io.brupdate.b2.uop.pc_lob, issue_slots[1].brupdate.b2.uop.pc_lob connect slots_1.io.brupdate.b2.uop.edge_inst, issue_slots[1].brupdate.b2.uop.edge_inst connect slots_1.io.brupdate.b2.uop.ftq_idx, issue_slots[1].brupdate.b2.uop.ftq_idx connect slots_1.io.brupdate.b2.uop.br_tag, issue_slots[1].brupdate.b2.uop.br_tag connect slots_1.io.brupdate.b2.uop.br_mask, issue_slots[1].brupdate.b2.uop.br_mask connect slots_1.io.brupdate.b2.uop.is_sfb, issue_slots[1].brupdate.b2.uop.is_sfb connect slots_1.io.brupdate.b2.uop.is_jal, issue_slots[1].brupdate.b2.uop.is_jal connect slots_1.io.brupdate.b2.uop.is_jalr, issue_slots[1].brupdate.b2.uop.is_jalr connect slots_1.io.brupdate.b2.uop.is_br, issue_slots[1].brupdate.b2.uop.is_br connect slots_1.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[1].brupdate.b2.uop.iw_p2_poisoned connect slots_1.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[1].brupdate.b2.uop.iw_p1_poisoned connect slots_1.io.brupdate.b2.uop.iw_state, issue_slots[1].brupdate.b2.uop.iw_state connect slots_1.io.brupdate.b2.uop.ctrl.is_std, issue_slots[1].brupdate.b2.uop.ctrl.is_std connect slots_1.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[1].brupdate.b2.uop.ctrl.is_sta connect slots_1.io.brupdate.b2.uop.ctrl.is_load, issue_slots[1].brupdate.b2.uop.ctrl.is_load connect slots_1.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[1].brupdate.b2.uop.ctrl.csr_cmd connect slots_1.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[1].brupdate.b2.uop.ctrl.fcn_dw connect slots_1.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[1].brupdate.b2.uop.ctrl.op_fcn connect slots_1.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[1].brupdate.b2.uop.ctrl.imm_sel connect slots_1.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[1].brupdate.b2.uop.ctrl.op2_sel connect slots_1.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[1].brupdate.b2.uop.ctrl.op1_sel connect slots_1.io.brupdate.b2.uop.ctrl.br_type, issue_slots[1].brupdate.b2.uop.ctrl.br_type connect slots_1.io.brupdate.b2.uop.fu_code, issue_slots[1].brupdate.b2.uop.fu_code connect slots_1.io.brupdate.b2.uop.iq_type, issue_slots[1].brupdate.b2.uop.iq_type connect slots_1.io.brupdate.b2.uop.debug_pc, issue_slots[1].brupdate.b2.uop.debug_pc connect slots_1.io.brupdate.b2.uop.is_rvc, issue_slots[1].brupdate.b2.uop.is_rvc connect slots_1.io.brupdate.b2.uop.debug_inst, issue_slots[1].brupdate.b2.uop.debug_inst connect slots_1.io.brupdate.b2.uop.inst, issue_slots[1].brupdate.b2.uop.inst connect slots_1.io.brupdate.b2.uop.uopc, issue_slots[1].brupdate.b2.uop.uopc connect slots_1.io.brupdate.b1.mispredict_mask, issue_slots[1].brupdate.b1.mispredict_mask connect slots_1.io.brupdate.b1.resolve_mask, issue_slots[1].brupdate.b1.resolve_mask connect slots_1.io.grant, issue_slots[1].grant connect issue_slots[1].request_hp, slots_1.io.request_hp connect issue_slots[1].request, slots_1.io.request connect issue_slots[1].will_be_valid, slots_1.io.will_be_valid connect issue_slots[1].valid, slots_1.io.valid connect issue_slots[2].debug.state, slots_2.io.debug.state connect issue_slots[2].debug.ppred, slots_2.io.debug.ppred connect issue_slots[2].debug.p3, slots_2.io.debug.p3 connect issue_slots[2].debug.p2, slots_2.io.debug.p2 connect issue_slots[2].debug.p1, slots_2.io.debug.p1 connect issue_slots[2].uop.debug_tsrc, slots_2.io.uop.debug_tsrc connect issue_slots[2].uop.debug_fsrc, slots_2.io.uop.debug_fsrc connect issue_slots[2].uop.bp_xcpt_if, slots_2.io.uop.bp_xcpt_if connect issue_slots[2].uop.bp_debug_if, slots_2.io.uop.bp_debug_if connect issue_slots[2].uop.xcpt_ma_if, slots_2.io.uop.xcpt_ma_if connect issue_slots[2].uop.xcpt_ae_if, slots_2.io.uop.xcpt_ae_if connect issue_slots[2].uop.xcpt_pf_if, slots_2.io.uop.xcpt_pf_if connect issue_slots[2].uop.fp_single, slots_2.io.uop.fp_single connect issue_slots[2].uop.fp_val, slots_2.io.uop.fp_val connect issue_slots[2].uop.frs3_en, slots_2.io.uop.frs3_en connect issue_slots[2].uop.lrs2_rtype, slots_2.io.uop.lrs2_rtype connect issue_slots[2].uop.lrs1_rtype, slots_2.io.uop.lrs1_rtype connect issue_slots[2].uop.dst_rtype, slots_2.io.uop.dst_rtype connect issue_slots[2].uop.ldst_val, slots_2.io.uop.ldst_val connect issue_slots[2].uop.lrs3, slots_2.io.uop.lrs3 connect issue_slots[2].uop.lrs2, slots_2.io.uop.lrs2 connect issue_slots[2].uop.lrs1, slots_2.io.uop.lrs1 connect issue_slots[2].uop.ldst, slots_2.io.uop.ldst connect issue_slots[2].uop.ldst_is_rs1, slots_2.io.uop.ldst_is_rs1 connect issue_slots[2].uop.flush_on_commit, slots_2.io.uop.flush_on_commit connect issue_slots[2].uop.is_unique, slots_2.io.uop.is_unique connect issue_slots[2].uop.is_sys_pc2epc, slots_2.io.uop.is_sys_pc2epc connect issue_slots[2].uop.uses_stq, slots_2.io.uop.uses_stq connect issue_slots[2].uop.uses_ldq, slots_2.io.uop.uses_ldq connect issue_slots[2].uop.is_amo, slots_2.io.uop.is_amo connect issue_slots[2].uop.is_fencei, slots_2.io.uop.is_fencei connect issue_slots[2].uop.is_fence, slots_2.io.uop.is_fence connect issue_slots[2].uop.mem_signed, slots_2.io.uop.mem_signed connect issue_slots[2].uop.mem_size, slots_2.io.uop.mem_size connect issue_slots[2].uop.mem_cmd, slots_2.io.uop.mem_cmd connect issue_slots[2].uop.bypassable, slots_2.io.uop.bypassable connect issue_slots[2].uop.exc_cause, slots_2.io.uop.exc_cause connect issue_slots[2].uop.exception, slots_2.io.uop.exception connect issue_slots[2].uop.stale_pdst, slots_2.io.uop.stale_pdst connect issue_slots[2].uop.ppred_busy, slots_2.io.uop.ppred_busy connect issue_slots[2].uop.prs3_busy, slots_2.io.uop.prs3_busy connect issue_slots[2].uop.prs2_busy, slots_2.io.uop.prs2_busy connect issue_slots[2].uop.prs1_busy, slots_2.io.uop.prs1_busy connect issue_slots[2].uop.ppred, slots_2.io.uop.ppred connect issue_slots[2].uop.prs3, slots_2.io.uop.prs3 connect issue_slots[2].uop.prs2, slots_2.io.uop.prs2 connect issue_slots[2].uop.prs1, slots_2.io.uop.prs1 connect issue_slots[2].uop.pdst, slots_2.io.uop.pdst connect issue_slots[2].uop.rxq_idx, slots_2.io.uop.rxq_idx connect issue_slots[2].uop.stq_idx, slots_2.io.uop.stq_idx connect issue_slots[2].uop.ldq_idx, slots_2.io.uop.ldq_idx connect issue_slots[2].uop.rob_idx, slots_2.io.uop.rob_idx connect issue_slots[2].uop.csr_addr, slots_2.io.uop.csr_addr connect issue_slots[2].uop.imm_packed, slots_2.io.uop.imm_packed connect issue_slots[2].uop.taken, slots_2.io.uop.taken connect issue_slots[2].uop.pc_lob, slots_2.io.uop.pc_lob connect issue_slots[2].uop.edge_inst, slots_2.io.uop.edge_inst connect issue_slots[2].uop.ftq_idx, slots_2.io.uop.ftq_idx connect issue_slots[2].uop.br_tag, slots_2.io.uop.br_tag connect issue_slots[2].uop.br_mask, slots_2.io.uop.br_mask connect issue_slots[2].uop.is_sfb, slots_2.io.uop.is_sfb connect issue_slots[2].uop.is_jal, slots_2.io.uop.is_jal connect issue_slots[2].uop.is_jalr, slots_2.io.uop.is_jalr connect issue_slots[2].uop.is_br, slots_2.io.uop.is_br connect issue_slots[2].uop.iw_p2_poisoned, slots_2.io.uop.iw_p2_poisoned connect issue_slots[2].uop.iw_p1_poisoned, slots_2.io.uop.iw_p1_poisoned connect issue_slots[2].uop.iw_state, slots_2.io.uop.iw_state connect issue_slots[2].uop.ctrl.is_std, slots_2.io.uop.ctrl.is_std connect issue_slots[2].uop.ctrl.is_sta, slots_2.io.uop.ctrl.is_sta connect issue_slots[2].uop.ctrl.is_load, slots_2.io.uop.ctrl.is_load connect issue_slots[2].uop.ctrl.csr_cmd, slots_2.io.uop.ctrl.csr_cmd connect issue_slots[2].uop.ctrl.fcn_dw, slots_2.io.uop.ctrl.fcn_dw connect issue_slots[2].uop.ctrl.op_fcn, slots_2.io.uop.ctrl.op_fcn connect issue_slots[2].uop.ctrl.imm_sel, slots_2.io.uop.ctrl.imm_sel connect issue_slots[2].uop.ctrl.op2_sel, slots_2.io.uop.ctrl.op2_sel connect issue_slots[2].uop.ctrl.op1_sel, slots_2.io.uop.ctrl.op1_sel connect issue_slots[2].uop.ctrl.br_type, slots_2.io.uop.ctrl.br_type connect issue_slots[2].uop.fu_code, slots_2.io.uop.fu_code connect issue_slots[2].uop.iq_type, slots_2.io.uop.iq_type connect issue_slots[2].uop.debug_pc, slots_2.io.uop.debug_pc connect issue_slots[2].uop.is_rvc, slots_2.io.uop.is_rvc connect issue_slots[2].uop.debug_inst, slots_2.io.uop.debug_inst connect issue_slots[2].uop.inst, slots_2.io.uop.inst connect issue_slots[2].uop.uopc, slots_2.io.uop.uopc connect issue_slots[2].out_uop.debug_tsrc, slots_2.io.out_uop.debug_tsrc connect issue_slots[2].out_uop.debug_fsrc, slots_2.io.out_uop.debug_fsrc connect issue_slots[2].out_uop.bp_xcpt_if, slots_2.io.out_uop.bp_xcpt_if connect issue_slots[2].out_uop.bp_debug_if, slots_2.io.out_uop.bp_debug_if connect issue_slots[2].out_uop.xcpt_ma_if, slots_2.io.out_uop.xcpt_ma_if connect issue_slots[2].out_uop.xcpt_ae_if, slots_2.io.out_uop.xcpt_ae_if connect issue_slots[2].out_uop.xcpt_pf_if, slots_2.io.out_uop.xcpt_pf_if connect issue_slots[2].out_uop.fp_single, slots_2.io.out_uop.fp_single connect issue_slots[2].out_uop.fp_val, slots_2.io.out_uop.fp_val connect issue_slots[2].out_uop.frs3_en, slots_2.io.out_uop.frs3_en connect issue_slots[2].out_uop.lrs2_rtype, slots_2.io.out_uop.lrs2_rtype connect issue_slots[2].out_uop.lrs1_rtype, slots_2.io.out_uop.lrs1_rtype connect issue_slots[2].out_uop.dst_rtype, slots_2.io.out_uop.dst_rtype connect issue_slots[2].out_uop.ldst_val, slots_2.io.out_uop.ldst_val connect issue_slots[2].out_uop.lrs3, slots_2.io.out_uop.lrs3 connect issue_slots[2].out_uop.lrs2, slots_2.io.out_uop.lrs2 connect issue_slots[2].out_uop.lrs1, slots_2.io.out_uop.lrs1 connect issue_slots[2].out_uop.ldst, slots_2.io.out_uop.ldst connect issue_slots[2].out_uop.ldst_is_rs1, slots_2.io.out_uop.ldst_is_rs1 connect issue_slots[2].out_uop.flush_on_commit, slots_2.io.out_uop.flush_on_commit connect issue_slots[2].out_uop.is_unique, slots_2.io.out_uop.is_unique connect issue_slots[2].out_uop.is_sys_pc2epc, slots_2.io.out_uop.is_sys_pc2epc connect issue_slots[2].out_uop.uses_stq, slots_2.io.out_uop.uses_stq connect issue_slots[2].out_uop.uses_ldq, slots_2.io.out_uop.uses_ldq connect issue_slots[2].out_uop.is_amo, slots_2.io.out_uop.is_amo connect issue_slots[2].out_uop.is_fencei, slots_2.io.out_uop.is_fencei connect issue_slots[2].out_uop.is_fence, slots_2.io.out_uop.is_fence connect issue_slots[2].out_uop.mem_signed, slots_2.io.out_uop.mem_signed connect issue_slots[2].out_uop.mem_size, slots_2.io.out_uop.mem_size connect issue_slots[2].out_uop.mem_cmd, slots_2.io.out_uop.mem_cmd connect issue_slots[2].out_uop.bypassable, slots_2.io.out_uop.bypassable connect issue_slots[2].out_uop.exc_cause, slots_2.io.out_uop.exc_cause connect issue_slots[2].out_uop.exception, slots_2.io.out_uop.exception connect issue_slots[2].out_uop.stale_pdst, slots_2.io.out_uop.stale_pdst connect issue_slots[2].out_uop.ppred_busy, slots_2.io.out_uop.ppred_busy connect issue_slots[2].out_uop.prs3_busy, slots_2.io.out_uop.prs3_busy connect issue_slots[2].out_uop.prs2_busy, slots_2.io.out_uop.prs2_busy connect issue_slots[2].out_uop.prs1_busy, slots_2.io.out_uop.prs1_busy connect issue_slots[2].out_uop.ppred, slots_2.io.out_uop.ppred connect issue_slots[2].out_uop.prs3, slots_2.io.out_uop.prs3 connect issue_slots[2].out_uop.prs2, slots_2.io.out_uop.prs2 connect issue_slots[2].out_uop.prs1, slots_2.io.out_uop.prs1 connect issue_slots[2].out_uop.pdst, slots_2.io.out_uop.pdst connect issue_slots[2].out_uop.rxq_idx, slots_2.io.out_uop.rxq_idx connect issue_slots[2].out_uop.stq_idx, slots_2.io.out_uop.stq_idx connect issue_slots[2].out_uop.ldq_idx, slots_2.io.out_uop.ldq_idx connect issue_slots[2].out_uop.rob_idx, slots_2.io.out_uop.rob_idx connect issue_slots[2].out_uop.csr_addr, slots_2.io.out_uop.csr_addr connect issue_slots[2].out_uop.imm_packed, slots_2.io.out_uop.imm_packed connect issue_slots[2].out_uop.taken, slots_2.io.out_uop.taken connect issue_slots[2].out_uop.pc_lob, slots_2.io.out_uop.pc_lob connect issue_slots[2].out_uop.edge_inst, slots_2.io.out_uop.edge_inst connect issue_slots[2].out_uop.ftq_idx, slots_2.io.out_uop.ftq_idx connect issue_slots[2].out_uop.br_tag, slots_2.io.out_uop.br_tag connect issue_slots[2].out_uop.br_mask, slots_2.io.out_uop.br_mask connect issue_slots[2].out_uop.is_sfb, slots_2.io.out_uop.is_sfb connect issue_slots[2].out_uop.is_jal, slots_2.io.out_uop.is_jal connect issue_slots[2].out_uop.is_jalr, slots_2.io.out_uop.is_jalr connect issue_slots[2].out_uop.is_br, slots_2.io.out_uop.is_br connect issue_slots[2].out_uop.iw_p2_poisoned, slots_2.io.out_uop.iw_p2_poisoned connect issue_slots[2].out_uop.iw_p1_poisoned, slots_2.io.out_uop.iw_p1_poisoned connect issue_slots[2].out_uop.iw_state, slots_2.io.out_uop.iw_state connect issue_slots[2].out_uop.ctrl.is_std, slots_2.io.out_uop.ctrl.is_std connect issue_slots[2].out_uop.ctrl.is_sta, slots_2.io.out_uop.ctrl.is_sta connect issue_slots[2].out_uop.ctrl.is_load, slots_2.io.out_uop.ctrl.is_load connect issue_slots[2].out_uop.ctrl.csr_cmd, slots_2.io.out_uop.ctrl.csr_cmd connect issue_slots[2].out_uop.ctrl.fcn_dw, slots_2.io.out_uop.ctrl.fcn_dw connect issue_slots[2].out_uop.ctrl.op_fcn, slots_2.io.out_uop.ctrl.op_fcn connect issue_slots[2].out_uop.ctrl.imm_sel, slots_2.io.out_uop.ctrl.imm_sel connect issue_slots[2].out_uop.ctrl.op2_sel, slots_2.io.out_uop.ctrl.op2_sel connect issue_slots[2].out_uop.ctrl.op1_sel, slots_2.io.out_uop.ctrl.op1_sel connect issue_slots[2].out_uop.ctrl.br_type, slots_2.io.out_uop.ctrl.br_type connect issue_slots[2].out_uop.fu_code, slots_2.io.out_uop.fu_code connect issue_slots[2].out_uop.iq_type, slots_2.io.out_uop.iq_type connect issue_slots[2].out_uop.debug_pc, slots_2.io.out_uop.debug_pc connect issue_slots[2].out_uop.is_rvc, slots_2.io.out_uop.is_rvc connect issue_slots[2].out_uop.debug_inst, slots_2.io.out_uop.debug_inst connect issue_slots[2].out_uop.inst, slots_2.io.out_uop.inst connect issue_slots[2].out_uop.uopc, slots_2.io.out_uop.uopc connect slots_2.io.in_uop.bits.debug_tsrc, issue_slots[2].in_uop.bits.debug_tsrc connect slots_2.io.in_uop.bits.debug_fsrc, issue_slots[2].in_uop.bits.debug_fsrc connect slots_2.io.in_uop.bits.bp_xcpt_if, issue_slots[2].in_uop.bits.bp_xcpt_if connect slots_2.io.in_uop.bits.bp_debug_if, issue_slots[2].in_uop.bits.bp_debug_if connect slots_2.io.in_uop.bits.xcpt_ma_if, issue_slots[2].in_uop.bits.xcpt_ma_if connect slots_2.io.in_uop.bits.xcpt_ae_if, issue_slots[2].in_uop.bits.xcpt_ae_if connect slots_2.io.in_uop.bits.xcpt_pf_if, issue_slots[2].in_uop.bits.xcpt_pf_if connect slots_2.io.in_uop.bits.fp_single, issue_slots[2].in_uop.bits.fp_single connect slots_2.io.in_uop.bits.fp_val, issue_slots[2].in_uop.bits.fp_val connect slots_2.io.in_uop.bits.frs3_en, issue_slots[2].in_uop.bits.frs3_en connect slots_2.io.in_uop.bits.lrs2_rtype, issue_slots[2].in_uop.bits.lrs2_rtype connect slots_2.io.in_uop.bits.lrs1_rtype, issue_slots[2].in_uop.bits.lrs1_rtype connect slots_2.io.in_uop.bits.dst_rtype, issue_slots[2].in_uop.bits.dst_rtype connect slots_2.io.in_uop.bits.ldst_val, issue_slots[2].in_uop.bits.ldst_val connect slots_2.io.in_uop.bits.lrs3, issue_slots[2].in_uop.bits.lrs3 connect slots_2.io.in_uop.bits.lrs2, issue_slots[2].in_uop.bits.lrs2 connect slots_2.io.in_uop.bits.lrs1, issue_slots[2].in_uop.bits.lrs1 connect slots_2.io.in_uop.bits.ldst, issue_slots[2].in_uop.bits.ldst connect slots_2.io.in_uop.bits.ldst_is_rs1, issue_slots[2].in_uop.bits.ldst_is_rs1 connect slots_2.io.in_uop.bits.flush_on_commit, issue_slots[2].in_uop.bits.flush_on_commit connect slots_2.io.in_uop.bits.is_unique, issue_slots[2].in_uop.bits.is_unique connect slots_2.io.in_uop.bits.is_sys_pc2epc, issue_slots[2].in_uop.bits.is_sys_pc2epc connect slots_2.io.in_uop.bits.uses_stq, issue_slots[2].in_uop.bits.uses_stq connect slots_2.io.in_uop.bits.uses_ldq, issue_slots[2].in_uop.bits.uses_ldq connect slots_2.io.in_uop.bits.is_amo, issue_slots[2].in_uop.bits.is_amo connect slots_2.io.in_uop.bits.is_fencei, issue_slots[2].in_uop.bits.is_fencei connect slots_2.io.in_uop.bits.is_fence, issue_slots[2].in_uop.bits.is_fence connect slots_2.io.in_uop.bits.mem_signed, issue_slots[2].in_uop.bits.mem_signed connect slots_2.io.in_uop.bits.mem_size, issue_slots[2].in_uop.bits.mem_size connect slots_2.io.in_uop.bits.mem_cmd, issue_slots[2].in_uop.bits.mem_cmd connect slots_2.io.in_uop.bits.bypassable, issue_slots[2].in_uop.bits.bypassable connect slots_2.io.in_uop.bits.exc_cause, issue_slots[2].in_uop.bits.exc_cause connect slots_2.io.in_uop.bits.exception, issue_slots[2].in_uop.bits.exception connect slots_2.io.in_uop.bits.stale_pdst, issue_slots[2].in_uop.bits.stale_pdst connect slots_2.io.in_uop.bits.ppred_busy, issue_slots[2].in_uop.bits.ppred_busy connect slots_2.io.in_uop.bits.prs3_busy, issue_slots[2].in_uop.bits.prs3_busy connect slots_2.io.in_uop.bits.prs2_busy, issue_slots[2].in_uop.bits.prs2_busy connect slots_2.io.in_uop.bits.prs1_busy, issue_slots[2].in_uop.bits.prs1_busy connect slots_2.io.in_uop.bits.ppred, issue_slots[2].in_uop.bits.ppred connect slots_2.io.in_uop.bits.prs3, issue_slots[2].in_uop.bits.prs3 connect slots_2.io.in_uop.bits.prs2, issue_slots[2].in_uop.bits.prs2 connect slots_2.io.in_uop.bits.prs1, issue_slots[2].in_uop.bits.prs1 connect slots_2.io.in_uop.bits.pdst, issue_slots[2].in_uop.bits.pdst connect slots_2.io.in_uop.bits.rxq_idx, issue_slots[2].in_uop.bits.rxq_idx connect slots_2.io.in_uop.bits.stq_idx, issue_slots[2].in_uop.bits.stq_idx connect slots_2.io.in_uop.bits.ldq_idx, issue_slots[2].in_uop.bits.ldq_idx connect slots_2.io.in_uop.bits.rob_idx, issue_slots[2].in_uop.bits.rob_idx connect slots_2.io.in_uop.bits.csr_addr, issue_slots[2].in_uop.bits.csr_addr connect slots_2.io.in_uop.bits.imm_packed, issue_slots[2].in_uop.bits.imm_packed connect slots_2.io.in_uop.bits.taken, issue_slots[2].in_uop.bits.taken connect slots_2.io.in_uop.bits.pc_lob, issue_slots[2].in_uop.bits.pc_lob connect slots_2.io.in_uop.bits.edge_inst, issue_slots[2].in_uop.bits.edge_inst connect slots_2.io.in_uop.bits.ftq_idx, issue_slots[2].in_uop.bits.ftq_idx connect slots_2.io.in_uop.bits.br_tag, issue_slots[2].in_uop.bits.br_tag connect slots_2.io.in_uop.bits.br_mask, issue_slots[2].in_uop.bits.br_mask connect slots_2.io.in_uop.bits.is_sfb, issue_slots[2].in_uop.bits.is_sfb connect slots_2.io.in_uop.bits.is_jal, issue_slots[2].in_uop.bits.is_jal connect slots_2.io.in_uop.bits.is_jalr, issue_slots[2].in_uop.bits.is_jalr connect slots_2.io.in_uop.bits.is_br, issue_slots[2].in_uop.bits.is_br connect slots_2.io.in_uop.bits.iw_p2_poisoned, issue_slots[2].in_uop.bits.iw_p2_poisoned connect slots_2.io.in_uop.bits.iw_p1_poisoned, issue_slots[2].in_uop.bits.iw_p1_poisoned connect slots_2.io.in_uop.bits.iw_state, issue_slots[2].in_uop.bits.iw_state connect slots_2.io.in_uop.bits.ctrl.is_std, issue_slots[2].in_uop.bits.ctrl.is_std connect slots_2.io.in_uop.bits.ctrl.is_sta, issue_slots[2].in_uop.bits.ctrl.is_sta connect slots_2.io.in_uop.bits.ctrl.is_load, issue_slots[2].in_uop.bits.ctrl.is_load connect slots_2.io.in_uop.bits.ctrl.csr_cmd, issue_slots[2].in_uop.bits.ctrl.csr_cmd connect slots_2.io.in_uop.bits.ctrl.fcn_dw, issue_slots[2].in_uop.bits.ctrl.fcn_dw connect slots_2.io.in_uop.bits.ctrl.op_fcn, issue_slots[2].in_uop.bits.ctrl.op_fcn connect slots_2.io.in_uop.bits.ctrl.imm_sel, issue_slots[2].in_uop.bits.ctrl.imm_sel connect slots_2.io.in_uop.bits.ctrl.op2_sel, issue_slots[2].in_uop.bits.ctrl.op2_sel connect slots_2.io.in_uop.bits.ctrl.op1_sel, issue_slots[2].in_uop.bits.ctrl.op1_sel connect slots_2.io.in_uop.bits.ctrl.br_type, issue_slots[2].in_uop.bits.ctrl.br_type connect slots_2.io.in_uop.bits.fu_code, issue_slots[2].in_uop.bits.fu_code connect slots_2.io.in_uop.bits.iq_type, issue_slots[2].in_uop.bits.iq_type connect slots_2.io.in_uop.bits.debug_pc, issue_slots[2].in_uop.bits.debug_pc connect slots_2.io.in_uop.bits.is_rvc, issue_slots[2].in_uop.bits.is_rvc connect slots_2.io.in_uop.bits.debug_inst, issue_slots[2].in_uop.bits.debug_inst connect slots_2.io.in_uop.bits.inst, issue_slots[2].in_uop.bits.inst connect slots_2.io.in_uop.bits.uopc, issue_slots[2].in_uop.bits.uopc connect slots_2.io.in_uop.valid, issue_slots[2].in_uop.valid connect slots_2.io.spec_ld_wakeup[0].bits, issue_slots[2].spec_ld_wakeup[0].bits connect slots_2.io.spec_ld_wakeup[0].valid, issue_slots[2].spec_ld_wakeup[0].valid connect slots_2.io.pred_wakeup_port.bits, issue_slots[2].pred_wakeup_port.bits connect slots_2.io.pred_wakeup_port.valid, issue_slots[2].pred_wakeup_port.valid connect slots_2.io.wakeup_ports[0].bits.poisoned, issue_slots[2].wakeup_ports[0].bits.poisoned connect slots_2.io.wakeup_ports[0].bits.pdst, issue_slots[2].wakeup_ports[0].bits.pdst connect slots_2.io.wakeup_ports[0].valid, issue_slots[2].wakeup_ports[0].valid connect slots_2.io.wakeup_ports[1].bits.poisoned, issue_slots[2].wakeup_ports[1].bits.poisoned connect slots_2.io.wakeup_ports[1].bits.pdst, issue_slots[2].wakeup_ports[1].bits.pdst connect slots_2.io.wakeup_ports[1].valid, issue_slots[2].wakeup_ports[1].valid connect slots_2.io.ldspec_miss, issue_slots[2].ldspec_miss connect slots_2.io.clear, issue_slots[2].clear connect slots_2.io.kill, issue_slots[2].kill connect slots_2.io.brupdate.b2.target_offset, issue_slots[2].brupdate.b2.target_offset connect slots_2.io.brupdate.b2.jalr_target, issue_slots[2].brupdate.b2.jalr_target connect slots_2.io.brupdate.b2.pc_sel, issue_slots[2].brupdate.b2.pc_sel connect slots_2.io.brupdate.b2.cfi_type, issue_slots[2].brupdate.b2.cfi_type connect slots_2.io.brupdate.b2.taken, issue_slots[2].brupdate.b2.taken connect slots_2.io.brupdate.b2.mispredict, issue_slots[2].brupdate.b2.mispredict connect slots_2.io.brupdate.b2.valid, issue_slots[2].brupdate.b2.valid connect slots_2.io.brupdate.b2.uop.debug_tsrc, issue_slots[2].brupdate.b2.uop.debug_tsrc connect slots_2.io.brupdate.b2.uop.debug_fsrc, issue_slots[2].brupdate.b2.uop.debug_fsrc connect slots_2.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[2].brupdate.b2.uop.bp_xcpt_if connect slots_2.io.brupdate.b2.uop.bp_debug_if, issue_slots[2].brupdate.b2.uop.bp_debug_if connect slots_2.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[2].brupdate.b2.uop.xcpt_ma_if connect slots_2.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[2].brupdate.b2.uop.xcpt_ae_if connect slots_2.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[2].brupdate.b2.uop.xcpt_pf_if connect slots_2.io.brupdate.b2.uop.fp_single, issue_slots[2].brupdate.b2.uop.fp_single connect slots_2.io.brupdate.b2.uop.fp_val, issue_slots[2].brupdate.b2.uop.fp_val connect slots_2.io.brupdate.b2.uop.frs3_en, issue_slots[2].brupdate.b2.uop.frs3_en connect slots_2.io.brupdate.b2.uop.lrs2_rtype, issue_slots[2].brupdate.b2.uop.lrs2_rtype connect slots_2.io.brupdate.b2.uop.lrs1_rtype, issue_slots[2].brupdate.b2.uop.lrs1_rtype connect slots_2.io.brupdate.b2.uop.dst_rtype, issue_slots[2].brupdate.b2.uop.dst_rtype connect slots_2.io.brupdate.b2.uop.ldst_val, issue_slots[2].brupdate.b2.uop.ldst_val connect slots_2.io.brupdate.b2.uop.lrs3, issue_slots[2].brupdate.b2.uop.lrs3 connect slots_2.io.brupdate.b2.uop.lrs2, issue_slots[2].brupdate.b2.uop.lrs2 connect slots_2.io.brupdate.b2.uop.lrs1, issue_slots[2].brupdate.b2.uop.lrs1 connect slots_2.io.brupdate.b2.uop.ldst, issue_slots[2].brupdate.b2.uop.ldst connect slots_2.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[2].brupdate.b2.uop.ldst_is_rs1 connect slots_2.io.brupdate.b2.uop.flush_on_commit, issue_slots[2].brupdate.b2.uop.flush_on_commit connect slots_2.io.brupdate.b2.uop.is_unique, issue_slots[2].brupdate.b2.uop.is_unique connect slots_2.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[2].brupdate.b2.uop.is_sys_pc2epc connect slots_2.io.brupdate.b2.uop.uses_stq, issue_slots[2].brupdate.b2.uop.uses_stq connect slots_2.io.brupdate.b2.uop.uses_ldq, issue_slots[2].brupdate.b2.uop.uses_ldq connect slots_2.io.brupdate.b2.uop.is_amo, issue_slots[2].brupdate.b2.uop.is_amo connect slots_2.io.brupdate.b2.uop.is_fencei, issue_slots[2].brupdate.b2.uop.is_fencei connect slots_2.io.brupdate.b2.uop.is_fence, issue_slots[2].brupdate.b2.uop.is_fence connect slots_2.io.brupdate.b2.uop.mem_signed, issue_slots[2].brupdate.b2.uop.mem_signed connect slots_2.io.brupdate.b2.uop.mem_size, issue_slots[2].brupdate.b2.uop.mem_size connect slots_2.io.brupdate.b2.uop.mem_cmd, issue_slots[2].brupdate.b2.uop.mem_cmd connect slots_2.io.brupdate.b2.uop.bypassable, issue_slots[2].brupdate.b2.uop.bypassable connect slots_2.io.brupdate.b2.uop.exc_cause, issue_slots[2].brupdate.b2.uop.exc_cause connect slots_2.io.brupdate.b2.uop.exception, issue_slots[2].brupdate.b2.uop.exception connect slots_2.io.brupdate.b2.uop.stale_pdst, issue_slots[2].brupdate.b2.uop.stale_pdst connect slots_2.io.brupdate.b2.uop.ppred_busy, issue_slots[2].brupdate.b2.uop.ppred_busy connect slots_2.io.brupdate.b2.uop.prs3_busy, issue_slots[2].brupdate.b2.uop.prs3_busy connect slots_2.io.brupdate.b2.uop.prs2_busy, issue_slots[2].brupdate.b2.uop.prs2_busy connect slots_2.io.brupdate.b2.uop.prs1_busy, issue_slots[2].brupdate.b2.uop.prs1_busy connect slots_2.io.brupdate.b2.uop.ppred, issue_slots[2].brupdate.b2.uop.ppred connect slots_2.io.brupdate.b2.uop.prs3, issue_slots[2].brupdate.b2.uop.prs3 connect slots_2.io.brupdate.b2.uop.prs2, issue_slots[2].brupdate.b2.uop.prs2 connect slots_2.io.brupdate.b2.uop.prs1, issue_slots[2].brupdate.b2.uop.prs1 connect slots_2.io.brupdate.b2.uop.pdst, issue_slots[2].brupdate.b2.uop.pdst connect slots_2.io.brupdate.b2.uop.rxq_idx, issue_slots[2].brupdate.b2.uop.rxq_idx connect slots_2.io.brupdate.b2.uop.stq_idx, issue_slots[2].brupdate.b2.uop.stq_idx connect slots_2.io.brupdate.b2.uop.ldq_idx, issue_slots[2].brupdate.b2.uop.ldq_idx connect slots_2.io.brupdate.b2.uop.rob_idx, issue_slots[2].brupdate.b2.uop.rob_idx connect slots_2.io.brupdate.b2.uop.csr_addr, issue_slots[2].brupdate.b2.uop.csr_addr connect slots_2.io.brupdate.b2.uop.imm_packed, issue_slots[2].brupdate.b2.uop.imm_packed connect slots_2.io.brupdate.b2.uop.taken, issue_slots[2].brupdate.b2.uop.taken connect slots_2.io.brupdate.b2.uop.pc_lob, issue_slots[2].brupdate.b2.uop.pc_lob connect slots_2.io.brupdate.b2.uop.edge_inst, issue_slots[2].brupdate.b2.uop.edge_inst connect slots_2.io.brupdate.b2.uop.ftq_idx, issue_slots[2].brupdate.b2.uop.ftq_idx connect slots_2.io.brupdate.b2.uop.br_tag, issue_slots[2].brupdate.b2.uop.br_tag connect slots_2.io.brupdate.b2.uop.br_mask, issue_slots[2].brupdate.b2.uop.br_mask connect slots_2.io.brupdate.b2.uop.is_sfb, issue_slots[2].brupdate.b2.uop.is_sfb connect slots_2.io.brupdate.b2.uop.is_jal, issue_slots[2].brupdate.b2.uop.is_jal connect slots_2.io.brupdate.b2.uop.is_jalr, issue_slots[2].brupdate.b2.uop.is_jalr connect slots_2.io.brupdate.b2.uop.is_br, issue_slots[2].brupdate.b2.uop.is_br connect slots_2.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[2].brupdate.b2.uop.iw_p2_poisoned connect slots_2.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[2].brupdate.b2.uop.iw_p1_poisoned connect slots_2.io.brupdate.b2.uop.iw_state, issue_slots[2].brupdate.b2.uop.iw_state connect slots_2.io.brupdate.b2.uop.ctrl.is_std, issue_slots[2].brupdate.b2.uop.ctrl.is_std connect slots_2.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[2].brupdate.b2.uop.ctrl.is_sta connect slots_2.io.brupdate.b2.uop.ctrl.is_load, issue_slots[2].brupdate.b2.uop.ctrl.is_load connect slots_2.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[2].brupdate.b2.uop.ctrl.csr_cmd connect slots_2.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[2].brupdate.b2.uop.ctrl.fcn_dw connect slots_2.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[2].brupdate.b2.uop.ctrl.op_fcn connect slots_2.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[2].brupdate.b2.uop.ctrl.imm_sel connect slots_2.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[2].brupdate.b2.uop.ctrl.op2_sel connect slots_2.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[2].brupdate.b2.uop.ctrl.op1_sel connect slots_2.io.brupdate.b2.uop.ctrl.br_type, issue_slots[2].brupdate.b2.uop.ctrl.br_type connect slots_2.io.brupdate.b2.uop.fu_code, issue_slots[2].brupdate.b2.uop.fu_code connect slots_2.io.brupdate.b2.uop.iq_type, issue_slots[2].brupdate.b2.uop.iq_type connect slots_2.io.brupdate.b2.uop.debug_pc, issue_slots[2].brupdate.b2.uop.debug_pc connect slots_2.io.brupdate.b2.uop.is_rvc, issue_slots[2].brupdate.b2.uop.is_rvc connect slots_2.io.brupdate.b2.uop.debug_inst, issue_slots[2].brupdate.b2.uop.debug_inst connect slots_2.io.brupdate.b2.uop.inst, issue_slots[2].brupdate.b2.uop.inst connect slots_2.io.brupdate.b2.uop.uopc, issue_slots[2].brupdate.b2.uop.uopc connect slots_2.io.brupdate.b1.mispredict_mask, issue_slots[2].brupdate.b1.mispredict_mask connect slots_2.io.brupdate.b1.resolve_mask, issue_slots[2].brupdate.b1.resolve_mask connect slots_2.io.grant, issue_slots[2].grant connect issue_slots[2].request_hp, slots_2.io.request_hp connect issue_slots[2].request, slots_2.io.request connect issue_slots[2].will_be_valid, slots_2.io.will_be_valid connect issue_slots[2].valid, slots_2.io.valid connect issue_slots[3].debug.state, slots_3.io.debug.state connect issue_slots[3].debug.ppred, slots_3.io.debug.ppred connect issue_slots[3].debug.p3, slots_3.io.debug.p3 connect issue_slots[3].debug.p2, slots_3.io.debug.p2 connect issue_slots[3].debug.p1, slots_3.io.debug.p1 connect issue_slots[3].uop.debug_tsrc, slots_3.io.uop.debug_tsrc connect issue_slots[3].uop.debug_fsrc, slots_3.io.uop.debug_fsrc connect issue_slots[3].uop.bp_xcpt_if, slots_3.io.uop.bp_xcpt_if connect issue_slots[3].uop.bp_debug_if, slots_3.io.uop.bp_debug_if connect issue_slots[3].uop.xcpt_ma_if, slots_3.io.uop.xcpt_ma_if connect issue_slots[3].uop.xcpt_ae_if, slots_3.io.uop.xcpt_ae_if connect issue_slots[3].uop.xcpt_pf_if, slots_3.io.uop.xcpt_pf_if connect issue_slots[3].uop.fp_single, slots_3.io.uop.fp_single connect issue_slots[3].uop.fp_val, slots_3.io.uop.fp_val connect issue_slots[3].uop.frs3_en, slots_3.io.uop.frs3_en connect issue_slots[3].uop.lrs2_rtype, slots_3.io.uop.lrs2_rtype connect issue_slots[3].uop.lrs1_rtype, slots_3.io.uop.lrs1_rtype connect issue_slots[3].uop.dst_rtype, slots_3.io.uop.dst_rtype connect issue_slots[3].uop.ldst_val, slots_3.io.uop.ldst_val connect issue_slots[3].uop.lrs3, slots_3.io.uop.lrs3 connect issue_slots[3].uop.lrs2, slots_3.io.uop.lrs2 connect issue_slots[3].uop.lrs1, slots_3.io.uop.lrs1 connect issue_slots[3].uop.ldst, slots_3.io.uop.ldst connect issue_slots[3].uop.ldst_is_rs1, slots_3.io.uop.ldst_is_rs1 connect issue_slots[3].uop.flush_on_commit, slots_3.io.uop.flush_on_commit connect issue_slots[3].uop.is_unique, slots_3.io.uop.is_unique connect issue_slots[3].uop.is_sys_pc2epc, slots_3.io.uop.is_sys_pc2epc connect issue_slots[3].uop.uses_stq, slots_3.io.uop.uses_stq connect issue_slots[3].uop.uses_ldq, slots_3.io.uop.uses_ldq connect issue_slots[3].uop.is_amo, slots_3.io.uop.is_amo connect issue_slots[3].uop.is_fencei, slots_3.io.uop.is_fencei connect issue_slots[3].uop.is_fence, slots_3.io.uop.is_fence connect issue_slots[3].uop.mem_signed, slots_3.io.uop.mem_signed connect issue_slots[3].uop.mem_size, slots_3.io.uop.mem_size connect issue_slots[3].uop.mem_cmd, slots_3.io.uop.mem_cmd connect issue_slots[3].uop.bypassable, slots_3.io.uop.bypassable connect issue_slots[3].uop.exc_cause, slots_3.io.uop.exc_cause connect issue_slots[3].uop.exception, slots_3.io.uop.exception connect issue_slots[3].uop.stale_pdst, slots_3.io.uop.stale_pdst connect issue_slots[3].uop.ppred_busy, slots_3.io.uop.ppred_busy connect issue_slots[3].uop.prs3_busy, slots_3.io.uop.prs3_busy connect issue_slots[3].uop.prs2_busy, slots_3.io.uop.prs2_busy connect issue_slots[3].uop.prs1_busy, slots_3.io.uop.prs1_busy connect issue_slots[3].uop.ppred, slots_3.io.uop.ppred connect issue_slots[3].uop.prs3, slots_3.io.uop.prs3 connect issue_slots[3].uop.prs2, slots_3.io.uop.prs2 connect issue_slots[3].uop.prs1, slots_3.io.uop.prs1 connect issue_slots[3].uop.pdst, slots_3.io.uop.pdst connect issue_slots[3].uop.rxq_idx, slots_3.io.uop.rxq_idx connect issue_slots[3].uop.stq_idx, slots_3.io.uop.stq_idx connect issue_slots[3].uop.ldq_idx, slots_3.io.uop.ldq_idx connect issue_slots[3].uop.rob_idx, slots_3.io.uop.rob_idx connect issue_slots[3].uop.csr_addr, slots_3.io.uop.csr_addr connect issue_slots[3].uop.imm_packed, slots_3.io.uop.imm_packed connect issue_slots[3].uop.taken, slots_3.io.uop.taken connect issue_slots[3].uop.pc_lob, slots_3.io.uop.pc_lob connect issue_slots[3].uop.edge_inst, slots_3.io.uop.edge_inst connect issue_slots[3].uop.ftq_idx, slots_3.io.uop.ftq_idx connect issue_slots[3].uop.br_tag, slots_3.io.uop.br_tag connect issue_slots[3].uop.br_mask, slots_3.io.uop.br_mask connect issue_slots[3].uop.is_sfb, slots_3.io.uop.is_sfb connect issue_slots[3].uop.is_jal, slots_3.io.uop.is_jal connect issue_slots[3].uop.is_jalr, slots_3.io.uop.is_jalr connect issue_slots[3].uop.is_br, slots_3.io.uop.is_br connect issue_slots[3].uop.iw_p2_poisoned, slots_3.io.uop.iw_p2_poisoned connect issue_slots[3].uop.iw_p1_poisoned, slots_3.io.uop.iw_p1_poisoned connect issue_slots[3].uop.iw_state, slots_3.io.uop.iw_state connect issue_slots[3].uop.ctrl.is_std, slots_3.io.uop.ctrl.is_std connect issue_slots[3].uop.ctrl.is_sta, slots_3.io.uop.ctrl.is_sta connect issue_slots[3].uop.ctrl.is_load, slots_3.io.uop.ctrl.is_load connect issue_slots[3].uop.ctrl.csr_cmd, slots_3.io.uop.ctrl.csr_cmd connect issue_slots[3].uop.ctrl.fcn_dw, slots_3.io.uop.ctrl.fcn_dw connect issue_slots[3].uop.ctrl.op_fcn, slots_3.io.uop.ctrl.op_fcn connect issue_slots[3].uop.ctrl.imm_sel, slots_3.io.uop.ctrl.imm_sel connect issue_slots[3].uop.ctrl.op2_sel, slots_3.io.uop.ctrl.op2_sel connect issue_slots[3].uop.ctrl.op1_sel, slots_3.io.uop.ctrl.op1_sel connect issue_slots[3].uop.ctrl.br_type, slots_3.io.uop.ctrl.br_type connect issue_slots[3].uop.fu_code, slots_3.io.uop.fu_code connect issue_slots[3].uop.iq_type, slots_3.io.uop.iq_type connect issue_slots[3].uop.debug_pc, slots_3.io.uop.debug_pc connect issue_slots[3].uop.is_rvc, slots_3.io.uop.is_rvc connect issue_slots[3].uop.debug_inst, slots_3.io.uop.debug_inst connect issue_slots[3].uop.inst, slots_3.io.uop.inst connect issue_slots[3].uop.uopc, slots_3.io.uop.uopc connect issue_slots[3].out_uop.debug_tsrc, slots_3.io.out_uop.debug_tsrc connect issue_slots[3].out_uop.debug_fsrc, slots_3.io.out_uop.debug_fsrc connect issue_slots[3].out_uop.bp_xcpt_if, slots_3.io.out_uop.bp_xcpt_if connect issue_slots[3].out_uop.bp_debug_if, slots_3.io.out_uop.bp_debug_if connect issue_slots[3].out_uop.xcpt_ma_if, slots_3.io.out_uop.xcpt_ma_if connect issue_slots[3].out_uop.xcpt_ae_if, slots_3.io.out_uop.xcpt_ae_if connect issue_slots[3].out_uop.xcpt_pf_if, slots_3.io.out_uop.xcpt_pf_if connect issue_slots[3].out_uop.fp_single, slots_3.io.out_uop.fp_single connect issue_slots[3].out_uop.fp_val, slots_3.io.out_uop.fp_val connect issue_slots[3].out_uop.frs3_en, slots_3.io.out_uop.frs3_en connect issue_slots[3].out_uop.lrs2_rtype, slots_3.io.out_uop.lrs2_rtype connect issue_slots[3].out_uop.lrs1_rtype, slots_3.io.out_uop.lrs1_rtype connect issue_slots[3].out_uop.dst_rtype, slots_3.io.out_uop.dst_rtype connect issue_slots[3].out_uop.ldst_val, slots_3.io.out_uop.ldst_val connect issue_slots[3].out_uop.lrs3, slots_3.io.out_uop.lrs3 connect issue_slots[3].out_uop.lrs2, slots_3.io.out_uop.lrs2 connect issue_slots[3].out_uop.lrs1, slots_3.io.out_uop.lrs1 connect issue_slots[3].out_uop.ldst, slots_3.io.out_uop.ldst connect issue_slots[3].out_uop.ldst_is_rs1, slots_3.io.out_uop.ldst_is_rs1 connect issue_slots[3].out_uop.flush_on_commit, slots_3.io.out_uop.flush_on_commit connect issue_slots[3].out_uop.is_unique, slots_3.io.out_uop.is_unique connect issue_slots[3].out_uop.is_sys_pc2epc, slots_3.io.out_uop.is_sys_pc2epc connect issue_slots[3].out_uop.uses_stq, slots_3.io.out_uop.uses_stq connect issue_slots[3].out_uop.uses_ldq, slots_3.io.out_uop.uses_ldq connect issue_slots[3].out_uop.is_amo, slots_3.io.out_uop.is_amo connect issue_slots[3].out_uop.is_fencei, slots_3.io.out_uop.is_fencei connect issue_slots[3].out_uop.is_fence, slots_3.io.out_uop.is_fence connect issue_slots[3].out_uop.mem_signed, slots_3.io.out_uop.mem_signed connect issue_slots[3].out_uop.mem_size, slots_3.io.out_uop.mem_size connect issue_slots[3].out_uop.mem_cmd, slots_3.io.out_uop.mem_cmd connect issue_slots[3].out_uop.bypassable, slots_3.io.out_uop.bypassable connect issue_slots[3].out_uop.exc_cause, slots_3.io.out_uop.exc_cause connect issue_slots[3].out_uop.exception, slots_3.io.out_uop.exception connect issue_slots[3].out_uop.stale_pdst, slots_3.io.out_uop.stale_pdst connect issue_slots[3].out_uop.ppred_busy, slots_3.io.out_uop.ppred_busy connect issue_slots[3].out_uop.prs3_busy, slots_3.io.out_uop.prs3_busy connect issue_slots[3].out_uop.prs2_busy, slots_3.io.out_uop.prs2_busy connect issue_slots[3].out_uop.prs1_busy, slots_3.io.out_uop.prs1_busy connect issue_slots[3].out_uop.ppred, slots_3.io.out_uop.ppred connect issue_slots[3].out_uop.prs3, slots_3.io.out_uop.prs3 connect issue_slots[3].out_uop.prs2, slots_3.io.out_uop.prs2 connect issue_slots[3].out_uop.prs1, slots_3.io.out_uop.prs1 connect issue_slots[3].out_uop.pdst, slots_3.io.out_uop.pdst connect issue_slots[3].out_uop.rxq_idx, slots_3.io.out_uop.rxq_idx connect issue_slots[3].out_uop.stq_idx, slots_3.io.out_uop.stq_idx connect issue_slots[3].out_uop.ldq_idx, slots_3.io.out_uop.ldq_idx connect issue_slots[3].out_uop.rob_idx, slots_3.io.out_uop.rob_idx connect issue_slots[3].out_uop.csr_addr, slots_3.io.out_uop.csr_addr connect issue_slots[3].out_uop.imm_packed, slots_3.io.out_uop.imm_packed connect issue_slots[3].out_uop.taken, slots_3.io.out_uop.taken connect issue_slots[3].out_uop.pc_lob, slots_3.io.out_uop.pc_lob connect issue_slots[3].out_uop.edge_inst, slots_3.io.out_uop.edge_inst connect issue_slots[3].out_uop.ftq_idx, slots_3.io.out_uop.ftq_idx connect issue_slots[3].out_uop.br_tag, slots_3.io.out_uop.br_tag connect issue_slots[3].out_uop.br_mask, slots_3.io.out_uop.br_mask connect issue_slots[3].out_uop.is_sfb, slots_3.io.out_uop.is_sfb connect issue_slots[3].out_uop.is_jal, slots_3.io.out_uop.is_jal connect issue_slots[3].out_uop.is_jalr, slots_3.io.out_uop.is_jalr connect issue_slots[3].out_uop.is_br, slots_3.io.out_uop.is_br connect issue_slots[3].out_uop.iw_p2_poisoned, slots_3.io.out_uop.iw_p2_poisoned connect issue_slots[3].out_uop.iw_p1_poisoned, slots_3.io.out_uop.iw_p1_poisoned connect issue_slots[3].out_uop.iw_state, slots_3.io.out_uop.iw_state connect issue_slots[3].out_uop.ctrl.is_std, slots_3.io.out_uop.ctrl.is_std connect issue_slots[3].out_uop.ctrl.is_sta, slots_3.io.out_uop.ctrl.is_sta connect issue_slots[3].out_uop.ctrl.is_load, slots_3.io.out_uop.ctrl.is_load connect issue_slots[3].out_uop.ctrl.csr_cmd, slots_3.io.out_uop.ctrl.csr_cmd connect issue_slots[3].out_uop.ctrl.fcn_dw, slots_3.io.out_uop.ctrl.fcn_dw connect issue_slots[3].out_uop.ctrl.op_fcn, slots_3.io.out_uop.ctrl.op_fcn connect issue_slots[3].out_uop.ctrl.imm_sel, slots_3.io.out_uop.ctrl.imm_sel connect issue_slots[3].out_uop.ctrl.op2_sel, slots_3.io.out_uop.ctrl.op2_sel connect issue_slots[3].out_uop.ctrl.op1_sel, slots_3.io.out_uop.ctrl.op1_sel connect issue_slots[3].out_uop.ctrl.br_type, slots_3.io.out_uop.ctrl.br_type connect issue_slots[3].out_uop.fu_code, slots_3.io.out_uop.fu_code connect issue_slots[3].out_uop.iq_type, slots_3.io.out_uop.iq_type connect issue_slots[3].out_uop.debug_pc, slots_3.io.out_uop.debug_pc connect issue_slots[3].out_uop.is_rvc, slots_3.io.out_uop.is_rvc connect issue_slots[3].out_uop.debug_inst, slots_3.io.out_uop.debug_inst connect issue_slots[3].out_uop.inst, slots_3.io.out_uop.inst connect issue_slots[3].out_uop.uopc, slots_3.io.out_uop.uopc connect slots_3.io.in_uop.bits.debug_tsrc, issue_slots[3].in_uop.bits.debug_tsrc connect slots_3.io.in_uop.bits.debug_fsrc, issue_slots[3].in_uop.bits.debug_fsrc connect slots_3.io.in_uop.bits.bp_xcpt_if, issue_slots[3].in_uop.bits.bp_xcpt_if connect slots_3.io.in_uop.bits.bp_debug_if, issue_slots[3].in_uop.bits.bp_debug_if connect slots_3.io.in_uop.bits.xcpt_ma_if, issue_slots[3].in_uop.bits.xcpt_ma_if connect slots_3.io.in_uop.bits.xcpt_ae_if, issue_slots[3].in_uop.bits.xcpt_ae_if connect slots_3.io.in_uop.bits.xcpt_pf_if, issue_slots[3].in_uop.bits.xcpt_pf_if connect slots_3.io.in_uop.bits.fp_single, issue_slots[3].in_uop.bits.fp_single connect slots_3.io.in_uop.bits.fp_val, issue_slots[3].in_uop.bits.fp_val connect slots_3.io.in_uop.bits.frs3_en, issue_slots[3].in_uop.bits.frs3_en connect slots_3.io.in_uop.bits.lrs2_rtype, issue_slots[3].in_uop.bits.lrs2_rtype connect slots_3.io.in_uop.bits.lrs1_rtype, issue_slots[3].in_uop.bits.lrs1_rtype connect slots_3.io.in_uop.bits.dst_rtype, issue_slots[3].in_uop.bits.dst_rtype connect slots_3.io.in_uop.bits.ldst_val, issue_slots[3].in_uop.bits.ldst_val connect slots_3.io.in_uop.bits.lrs3, issue_slots[3].in_uop.bits.lrs3 connect slots_3.io.in_uop.bits.lrs2, issue_slots[3].in_uop.bits.lrs2 connect slots_3.io.in_uop.bits.lrs1, issue_slots[3].in_uop.bits.lrs1 connect slots_3.io.in_uop.bits.ldst, issue_slots[3].in_uop.bits.ldst connect slots_3.io.in_uop.bits.ldst_is_rs1, issue_slots[3].in_uop.bits.ldst_is_rs1 connect slots_3.io.in_uop.bits.flush_on_commit, issue_slots[3].in_uop.bits.flush_on_commit connect slots_3.io.in_uop.bits.is_unique, issue_slots[3].in_uop.bits.is_unique connect slots_3.io.in_uop.bits.is_sys_pc2epc, issue_slots[3].in_uop.bits.is_sys_pc2epc connect slots_3.io.in_uop.bits.uses_stq, issue_slots[3].in_uop.bits.uses_stq connect slots_3.io.in_uop.bits.uses_ldq, issue_slots[3].in_uop.bits.uses_ldq connect slots_3.io.in_uop.bits.is_amo, issue_slots[3].in_uop.bits.is_amo connect slots_3.io.in_uop.bits.is_fencei, issue_slots[3].in_uop.bits.is_fencei connect slots_3.io.in_uop.bits.is_fence, issue_slots[3].in_uop.bits.is_fence connect slots_3.io.in_uop.bits.mem_signed, issue_slots[3].in_uop.bits.mem_signed connect slots_3.io.in_uop.bits.mem_size, issue_slots[3].in_uop.bits.mem_size connect slots_3.io.in_uop.bits.mem_cmd, issue_slots[3].in_uop.bits.mem_cmd connect slots_3.io.in_uop.bits.bypassable, issue_slots[3].in_uop.bits.bypassable connect slots_3.io.in_uop.bits.exc_cause, issue_slots[3].in_uop.bits.exc_cause connect slots_3.io.in_uop.bits.exception, issue_slots[3].in_uop.bits.exception connect slots_3.io.in_uop.bits.stale_pdst, issue_slots[3].in_uop.bits.stale_pdst connect slots_3.io.in_uop.bits.ppred_busy, issue_slots[3].in_uop.bits.ppred_busy connect slots_3.io.in_uop.bits.prs3_busy, issue_slots[3].in_uop.bits.prs3_busy connect slots_3.io.in_uop.bits.prs2_busy, issue_slots[3].in_uop.bits.prs2_busy connect slots_3.io.in_uop.bits.prs1_busy, issue_slots[3].in_uop.bits.prs1_busy connect slots_3.io.in_uop.bits.ppred, issue_slots[3].in_uop.bits.ppred connect slots_3.io.in_uop.bits.prs3, issue_slots[3].in_uop.bits.prs3 connect slots_3.io.in_uop.bits.prs2, issue_slots[3].in_uop.bits.prs2 connect slots_3.io.in_uop.bits.prs1, issue_slots[3].in_uop.bits.prs1 connect slots_3.io.in_uop.bits.pdst, issue_slots[3].in_uop.bits.pdst connect slots_3.io.in_uop.bits.rxq_idx, issue_slots[3].in_uop.bits.rxq_idx connect slots_3.io.in_uop.bits.stq_idx, issue_slots[3].in_uop.bits.stq_idx connect slots_3.io.in_uop.bits.ldq_idx, issue_slots[3].in_uop.bits.ldq_idx connect slots_3.io.in_uop.bits.rob_idx, issue_slots[3].in_uop.bits.rob_idx connect slots_3.io.in_uop.bits.csr_addr, issue_slots[3].in_uop.bits.csr_addr connect slots_3.io.in_uop.bits.imm_packed, issue_slots[3].in_uop.bits.imm_packed connect slots_3.io.in_uop.bits.taken, issue_slots[3].in_uop.bits.taken connect slots_3.io.in_uop.bits.pc_lob, issue_slots[3].in_uop.bits.pc_lob connect slots_3.io.in_uop.bits.edge_inst, issue_slots[3].in_uop.bits.edge_inst connect slots_3.io.in_uop.bits.ftq_idx, issue_slots[3].in_uop.bits.ftq_idx connect slots_3.io.in_uop.bits.br_tag, issue_slots[3].in_uop.bits.br_tag connect slots_3.io.in_uop.bits.br_mask, issue_slots[3].in_uop.bits.br_mask connect slots_3.io.in_uop.bits.is_sfb, issue_slots[3].in_uop.bits.is_sfb connect slots_3.io.in_uop.bits.is_jal, issue_slots[3].in_uop.bits.is_jal connect slots_3.io.in_uop.bits.is_jalr, issue_slots[3].in_uop.bits.is_jalr connect slots_3.io.in_uop.bits.is_br, issue_slots[3].in_uop.bits.is_br connect slots_3.io.in_uop.bits.iw_p2_poisoned, issue_slots[3].in_uop.bits.iw_p2_poisoned connect slots_3.io.in_uop.bits.iw_p1_poisoned, issue_slots[3].in_uop.bits.iw_p1_poisoned connect slots_3.io.in_uop.bits.iw_state, issue_slots[3].in_uop.bits.iw_state connect slots_3.io.in_uop.bits.ctrl.is_std, issue_slots[3].in_uop.bits.ctrl.is_std connect slots_3.io.in_uop.bits.ctrl.is_sta, issue_slots[3].in_uop.bits.ctrl.is_sta connect slots_3.io.in_uop.bits.ctrl.is_load, issue_slots[3].in_uop.bits.ctrl.is_load connect slots_3.io.in_uop.bits.ctrl.csr_cmd, issue_slots[3].in_uop.bits.ctrl.csr_cmd connect slots_3.io.in_uop.bits.ctrl.fcn_dw, issue_slots[3].in_uop.bits.ctrl.fcn_dw connect slots_3.io.in_uop.bits.ctrl.op_fcn, issue_slots[3].in_uop.bits.ctrl.op_fcn connect slots_3.io.in_uop.bits.ctrl.imm_sel, issue_slots[3].in_uop.bits.ctrl.imm_sel connect slots_3.io.in_uop.bits.ctrl.op2_sel, issue_slots[3].in_uop.bits.ctrl.op2_sel connect slots_3.io.in_uop.bits.ctrl.op1_sel, issue_slots[3].in_uop.bits.ctrl.op1_sel connect slots_3.io.in_uop.bits.ctrl.br_type, issue_slots[3].in_uop.bits.ctrl.br_type connect slots_3.io.in_uop.bits.fu_code, issue_slots[3].in_uop.bits.fu_code connect slots_3.io.in_uop.bits.iq_type, issue_slots[3].in_uop.bits.iq_type connect slots_3.io.in_uop.bits.debug_pc, issue_slots[3].in_uop.bits.debug_pc connect slots_3.io.in_uop.bits.is_rvc, issue_slots[3].in_uop.bits.is_rvc connect slots_3.io.in_uop.bits.debug_inst, issue_slots[3].in_uop.bits.debug_inst connect slots_3.io.in_uop.bits.inst, issue_slots[3].in_uop.bits.inst connect slots_3.io.in_uop.bits.uopc, issue_slots[3].in_uop.bits.uopc connect slots_3.io.in_uop.valid, issue_slots[3].in_uop.valid connect slots_3.io.spec_ld_wakeup[0].bits, issue_slots[3].spec_ld_wakeup[0].bits connect slots_3.io.spec_ld_wakeup[0].valid, issue_slots[3].spec_ld_wakeup[0].valid connect slots_3.io.pred_wakeup_port.bits, issue_slots[3].pred_wakeup_port.bits connect slots_3.io.pred_wakeup_port.valid, issue_slots[3].pred_wakeup_port.valid connect slots_3.io.wakeup_ports[0].bits.poisoned, issue_slots[3].wakeup_ports[0].bits.poisoned connect slots_3.io.wakeup_ports[0].bits.pdst, issue_slots[3].wakeup_ports[0].bits.pdst connect slots_3.io.wakeup_ports[0].valid, issue_slots[3].wakeup_ports[0].valid connect slots_3.io.wakeup_ports[1].bits.poisoned, issue_slots[3].wakeup_ports[1].bits.poisoned connect slots_3.io.wakeup_ports[1].bits.pdst, issue_slots[3].wakeup_ports[1].bits.pdst connect slots_3.io.wakeup_ports[1].valid, issue_slots[3].wakeup_ports[1].valid connect slots_3.io.ldspec_miss, issue_slots[3].ldspec_miss connect slots_3.io.clear, issue_slots[3].clear connect slots_3.io.kill, issue_slots[3].kill connect slots_3.io.brupdate.b2.target_offset, issue_slots[3].brupdate.b2.target_offset connect slots_3.io.brupdate.b2.jalr_target, issue_slots[3].brupdate.b2.jalr_target connect slots_3.io.brupdate.b2.pc_sel, issue_slots[3].brupdate.b2.pc_sel connect slots_3.io.brupdate.b2.cfi_type, issue_slots[3].brupdate.b2.cfi_type connect slots_3.io.brupdate.b2.taken, issue_slots[3].brupdate.b2.taken connect slots_3.io.brupdate.b2.mispredict, issue_slots[3].brupdate.b2.mispredict connect slots_3.io.brupdate.b2.valid, issue_slots[3].brupdate.b2.valid connect slots_3.io.brupdate.b2.uop.debug_tsrc, issue_slots[3].brupdate.b2.uop.debug_tsrc connect slots_3.io.brupdate.b2.uop.debug_fsrc, issue_slots[3].brupdate.b2.uop.debug_fsrc connect slots_3.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[3].brupdate.b2.uop.bp_xcpt_if connect slots_3.io.brupdate.b2.uop.bp_debug_if, issue_slots[3].brupdate.b2.uop.bp_debug_if connect slots_3.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[3].brupdate.b2.uop.xcpt_ma_if connect slots_3.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[3].brupdate.b2.uop.xcpt_ae_if connect slots_3.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[3].brupdate.b2.uop.xcpt_pf_if connect slots_3.io.brupdate.b2.uop.fp_single, issue_slots[3].brupdate.b2.uop.fp_single connect slots_3.io.brupdate.b2.uop.fp_val, issue_slots[3].brupdate.b2.uop.fp_val connect slots_3.io.brupdate.b2.uop.frs3_en, issue_slots[3].brupdate.b2.uop.frs3_en connect slots_3.io.brupdate.b2.uop.lrs2_rtype, issue_slots[3].brupdate.b2.uop.lrs2_rtype connect slots_3.io.brupdate.b2.uop.lrs1_rtype, issue_slots[3].brupdate.b2.uop.lrs1_rtype connect slots_3.io.brupdate.b2.uop.dst_rtype, issue_slots[3].brupdate.b2.uop.dst_rtype connect slots_3.io.brupdate.b2.uop.ldst_val, issue_slots[3].brupdate.b2.uop.ldst_val connect slots_3.io.brupdate.b2.uop.lrs3, issue_slots[3].brupdate.b2.uop.lrs3 connect slots_3.io.brupdate.b2.uop.lrs2, issue_slots[3].brupdate.b2.uop.lrs2 connect slots_3.io.brupdate.b2.uop.lrs1, issue_slots[3].brupdate.b2.uop.lrs1 connect slots_3.io.brupdate.b2.uop.ldst, issue_slots[3].brupdate.b2.uop.ldst connect slots_3.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[3].brupdate.b2.uop.ldst_is_rs1 connect slots_3.io.brupdate.b2.uop.flush_on_commit, issue_slots[3].brupdate.b2.uop.flush_on_commit connect slots_3.io.brupdate.b2.uop.is_unique, issue_slots[3].brupdate.b2.uop.is_unique connect slots_3.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[3].brupdate.b2.uop.is_sys_pc2epc connect slots_3.io.brupdate.b2.uop.uses_stq, issue_slots[3].brupdate.b2.uop.uses_stq connect slots_3.io.brupdate.b2.uop.uses_ldq, issue_slots[3].brupdate.b2.uop.uses_ldq connect slots_3.io.brupdate.b2.uop.is_amo, issue_slots[3].brupdate.b2.uop.is_amo connect slots_3.io.brupdate.b2.uop.is_fencei, issue_slots[3].brupdate.b2.uop.is_fencei connect slots_3.io.brupdate.b2.uop.is_fence, issue_slots[3].brupdate.b2.uop.is_fence connect slots_3.io.brupdate.b2.uop.mem_signed, issue_slots[3].brupdate.b2.uop.mem_signed connect slots_3.io.brupdate.b2.uop.mem_size, issue_slots[3].brupdate.b2.uop.mem_size connect slots_3.io.brupdate.b2.uop.mem_cmd, issue_slots[3].brupdate.b2.uop.mem_cmd connect slots_3.io.brupdate.b2.uop.bypassable, issue_slots[3].brupdate.b2.uop.bypassable connect slots_3.io.brupdate.b2.uop.exc_cause, issue_slots[3].brupdate.b2.uop.exc_cause connect slots_3.io.brupdate.b2.uop.exception, issue_slots[3].brupdate.b2.uop.exception connect slots_3.io.brupdate.b2.uop.stale_pdst, issue_slots[3].brupdate.b2.uop.stale_pdst connect slots_3.io.brupdate.b2.uop.ppred_busy, issue_slots[3].brupdate.b2.uop.ppred_busy connect slots_3.io.brupdate.b2.uop.prs3_busy, issue_slots[3].brupdate.b2.uop.prs3_busy connect slots_3.io.brupdate.b2.uop.prs2_busy, issue_slots[3].brupdate.b2.uop.prs2_busy connect slots_3.io.brupdate.b2.uop.prs1_busy, issue_slots[3].brupdate.b2.uop.prs1_busy connect slots_3.io.brupdate.b2.uop.ppred, issue_slots[3].brupdate.b2.uop.ppred connect slots_3.io.brupdate.b2.uop.prs3, issue_slots[3].brupdate.b2.uop.prs3 connect slots_3.io.brupdate.b2.uop.prs2, issue_slots[3].brupdate.b2.uop.prs2 connect slots_3.io.brupdate.b2.uop.prs1, issue_slots[3].brupdate.b2.uop.prs1 connect slots_3.io.brupdate.b2.uop.pdst, issue_slots[3].brupdate.b2.uop.pdst connect slots_3.io.brupdate.b2.uop.rxq_idx, issue_slots[3].brupdate.b2.uop.rxq_idx connect slots_3.io.brupdate.b2.uop.stq_idx, issue_slots[3].brupdate.b2.uop.stq_idx connect slots_3.io.brupdate.b2.uop.ldq_idx, issue_slots[3].brupdate.b2.uop.ldq_idx connect slots_3.io.brupdate.b2.uop.rob_idx, issue_slots[3].brupdate.b2.uop.rob_idx connect slots_3.io.brupdate.b2.uop.csr_addr, issue_slots[3].brupdate.b2.uop.csr_addr connect slots_3.io.brupdate.b2.uop.imm_packed, issue_slots[3].brupdate.b2.uop.imm_packed connect slots_3.io.brupdate.b2.uop.taken, issue_slots[3].brupdate.b2.uop.taken connect slots_3.io.brupdate.b2.uop.pc_lob, issue_slots[3].brupdate.b2.uop.pc_lob connect slots_3.io.brupdate.b2.uop.edge_inst, issue_slots[3].brupdate.b2.uop.edge_inst connect slots_3.io.brupdate.b2.uop.ftq_idx, issue_slots[3].brupdate.b2.uop.ftq_idx connect slots_3.io.brupdate.b2.uop.br_tag, issue_slots[3].brupdate.b2.uop.br_tag connect slots_3.io.brupdate.b2.uop.br_mask, issue_slots[3].brupdate.b2.uop.br_mask connect slots_3.io.brupdate.b2.uop.is_sfb, issue_slots[3].brupdate.b2.uop.is_sfb connect slots_3.io.brupdate.b2.uop.is_jal, issue_slots[3].brupdate.b2.uop.is_jal connect slots_3.io.brupdate.b2.uop.is_jalr, issue_slots[3].brupdate.b2.uop.is_jalr connect slots_3.io.brupdate.b2.uop.is_br, issue_slots[3].brupdate.b2.uop.is_br connect slots_3.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[3].brupdate.b2.uop.iw_p2_poisoned connect slots_3.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[3].brupdate.b2.uop.iw_p1_poisoned connect slots_3.io.brupdate.b2.uop.iw_state, issue_slots[3].brupdate.b2.uop.iw_state connect slots_3.io.brupdate.b2.uop.ctrl.is_std, issue_slots[3].brupdate.b2.uop.ctrl.is_std connect slots_3.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[3].brupdate.b2.uop.ctrl.is_sta connect slots_3.io.brupdate.b2.uop.ctrl.is_load, issue_slots[3].brupdate.b2.uop.ctrl.is_load connect slots_3.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[3].brupdate.b2.uop.ctrl.csr_cmd connect slots_3.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[3].brupdate.b2.uop.ctrl.fcn_dw connect slots_3.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[3].brupdate.b2.uop.ctrl.op_fcn connect slots_3.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[3].brupdate.b2.uop.ctrl.imm_sel connect slots_3.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[3].brupdate.b2.uop.ctrl.op2_sel connect slots_3.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[3].brupdate.b2.uop.ctrl.op1_sel connect slots_3.io.brupdate.b2.uop.ctrl.br_type, issue_slots[3].brupdate.b2.uop.ctrl.br_type connect slots_3.io.brupdate.b2.uop.fu_code, issue_slots[3].brupdate.b2.uop.fu_code connect slots_3.io.brupdate.b2.uop.iq_type, issue_slots[3].brupdate.b2.uop.iq_type connect slots_3.io.brupdate.b2.uop.debug_pc, issue_slots[3].brupdate.b2.uop.debug_pc connect slots_3.io.brupdate.b2.uop.is_rvc, issue_slots[3].brupdate.b2.uop.is_rvc connect slots_3.io.brupdate.b2.uop.debug_inst, issue_slots[3].brupdate.b2.uop.debug_inst connect slots_3.io.brupdate.b2.uop.inst, issue_slots[3].brupdate.b2.uop.inst connect slots_3.io.brupdate.b2.uop.uopc, issue_slots[3].brupdate.b2.uop.uopc connect slots_3.io.brupdate.b1.mispredict_mask, issue_slots[3].brupdate.b1.mispredict_mask connect slots_3.io.brupdate.b1.resolve_mask, issue_slots[3].brupdate.b1.resolve_mask connect slots_3.io.grant, issue_slots[3].grant connect issue_slots[3].request_hp, slots_3.io.request_hp connect issue_slots[3].request, slots_3.io.request connect issue_slots[3].will_be_valid, slots_3.io.will_be_valid connect issue_slots[3].valid, slots_3.io.valid connect issue_slots[4].debug.state, slots_4.io.debug.state connect issue_slots[4].debug.ppred, slots_4.io.debug.ppred connect issue_slots[4].debug.p3, slots_4.io.debug.p3 connect issue_slots[4].debug.p2, slots_4.io.debug.p2 connect issue_slots[4].debug.p1, slots_4.io.debug.p1 connect issue_slots[4].uop.debug_tsrc, slots_4.io.uop.debug_tsrc connect issue_slots[4].uop.debug_fsrc, slots_4.io.uop.debug_fsrc connect issue_slots[4].uop.bp_xcpt_if, slots_4.io.uop.bp_xcpt_if connect issue_slots[4].uop.bp_debug_if, slots_4.io.uop.bp_debug_if connect issue_slots[4].uop.xcpt_ma_if, slots_4.io.uop.xcpt_ma_if connect issue_slots[4].uop.xcpt_ae_if, slots_4.io.uop.xcpt_ae_if connect issue_slots[4].uop.xcpt_pf_if, slots_4.io.uop.xcpt_pf_if connect issue_slots[4].uop.fp_single, slots_4.io.uop.fp_single connect issue_slots[4].uop.fp_val, slots_4.io.uop.fp_val connect issue_slots[4].uop.frs3_en, slots_4.io.uop.frs3_en connect issue_slots[4].uop.lrs2_rtype, slots_4.io.uop.lrs2_rtype connect issue_slots[4].uop.lrs1_rtype, slots_4.io.uop.lrs1_rtype connect issue_slots[4].uop.dst_rtype, slots_4.io.uop.dst_rtype connect issue_slots[4].uop.ldst_val, slots_4.io.uop.ldst_val connect issue_slots[4].uop.lrs3, slots_4.io.uop.lrs3 connect issue_slots[4].uop.lrs2, slots_4.io.uop.lrs2 connect issue_slots[4].uop.lrs1, slots_4.io.uop.lrs1 connect issue_slots[4].uop.ldst, slots_4.io.uop.ldst connect issue_slots[4].uop.ldst_is_rs1, slots_4.io.uop.ldst_is_rs1 connect issue_slots[4].uop.flush_on_commit, slots_4.io.uop.flush_on_commit connect issue_slots[4].uop.is_unique, slots_4.io.uop.is_unique connect issue_slots[4].uop.is_sys_pc2epc, slots_4.io.uop.is_sys_pc2epc connect issue_slots[4].uop.uses_stq, slots_4.io.uop.uses_stq connect issue_slots[4].uop.uses_ldq, slots_4.io.uop.uses_ldq connect issue_slots[4].uop.is_amo, slots_4.io.uop.is_amo connect issue_slots[4].uop.is_fencei, slots_4.io.uop.is_fencei connect issue_slots[4].uop.is_fence, slots_4.io.uop.is_fence connect issue_slots[4].uop.mem_signed, slots_4.io.uop.mem_signed connect issue_slots[4].uop.mem_size, slots_4.io.uop.mem_size connect issue_slots[4].uop.mem_cmd, slots_4.io.uop.mem_cmd connect issue_slots[4].uop.bypassable, slots_4.io.uop.bypassable connect issue_slots[4].uop.exc_cause, slots_4.io.uop.exc_cause connect issue_slots[4].uop.exception, slots_4.io.uop.exception connect issue_slots[4].uop.stale_pdst, slots_4.io.uop.stale_pdst connect issue_slots[4].uop.ppred_busy, slots_4.io.uop.ppred_busy connect issue_slots[4].uop.prs3_busy, slots_4.io.uop.prs3_busy connect issue_slots[4].uop.prs2_busy, slots_4.io.uop.prs2_busy connect issue_slots[4].uop.prs1_busy, slots_4.io.uop.prs1_busy connect issue_slots[4].uop.ppred, slots_4.io.uop.ppred connect issue_slots[4].uop.prs3, slots_4.io.uop.prs3 connect issue_slots[4].uop.prs2, slots_4.io.uop.prs2 connect issue_slots[4].uop.prs1, slots_4.io.uop.prs1 connect issue_slots[4].uop.pdst, slots_4.io.uop.pdst connect issue_slots[4].uop.rxq_idx, slots_4.io.uop.rxq_idx connect issue_slots[4].uop.stq_idx, slots_4.io.uop.stq_idx connect issue_slots[4].uop.ldq_idx, slots_4.io.uop.ldq_idx connect issue_slots[4].uop.rob_idx, slots_4.io.uop.rob_idx connect issue_slots[4].uop.csr_addr, slots_4.io.uop.csr_addr connect issue_slots[4].uop.imm_packed, slots_4.io.uop.imm_packed connect issue_slots[4].uop.taken, slots_4.io.uop.taken connect issue_slots[4].uop.pc_lob, slots_4.io.uop.pc_lob connect issue_slots[4].uop.edge_inst, slots_4.io.uop.edge_inst connect issue_slots[4].uop.ftq_idx, slots_4.io.uop.ftq_idx connect issue_slots[4].uop.br_tag, slots_4.io.uop.br_tag connect issue_slots[4].uop.br_mask, slots_4.io.uop.br_mask connect issue_slots[4].uop.is_sfb, slots_4.io.uop.is_sfb connect issue_slots[4].uop.is_jal, slots_4.io.uop.is_jal connect issue_slots[4].uop.is_jalr, slots_4.io.uop.is_jalr connect issue_slots[4].uop.is_br, slots_4.io.uop.is_br connect issue_slots[4].uop.iw_p2_poisoned, slots_4.io.uop.iw_p2_poisoned connect issue_slots[4].uop.iw_p1_poisoned, slots_4.io.uop.iw_p1_poisoned connect issue_slots[4].uop.iw_state, slots_4.io.uop.iw_state connect issue_slots[4].uop.ctrl.is_std, slots_4.io.uop.ctrl.is_std connect issue_slots[4].uop.ctrl.is_sta, slots_4.io.uop.ctrl.is_sta connect issue_slots[4].uop.ctrl.is_load, slots_4.io.uop.ctrl.is_load connect issue_slots[4].uop.ctrl.csr_cmd, slots_4.io.uop.ctrl.csr_cmd connect issue_slots[4].uop.ctrl.fcn_dw, slots_4.io.uop.ctrl.fcn_dw connect issue_slots[4].uop.ctrl.op_fcn, slots_4.io.uop.ctrl.op_fcn connect issue_slots[4].uop.ctrl.imm_sel, slots_4.io.uop.ctrl.imm_sel connect issue_slots[4].uop.ctrl.op2_sel, slots_4.io.uop.ctrl.op2_sel connect issue_slots[4].uop.ctrl.op1_sel, slots_4.io.uop.ctrl.op1_sel connect issue_slots[4].uop.ctrl.br_type, slots_4.io.uop.ctrl.br_type connect issue_slots[4].uop.fu_code, slots_4.io.uop.fu_code connect issue_slots[4].uop.iq_type, slots_4.io.uop.iq_type connect issue_slots[4].uop.debug_pc, slots_4.io.uop.debug_pc connect issue_slots[4].uop.is_rvc, slots_4.io.uop.is_rvc connect issue_slots[4].uop.debug_inst, slots_4.io.uop.debug_inst connect issue_slots[4].uop.inst, slots_4.io.uop.inst connect issue_slots[4].uop.uopc, slots_4.io.uop.uopc connect issue_slots[4].out_uop.debug_tsrc, slots_4.io.out_uop.debug_tsrc connect issue_slots[4].out_uop.debug_fsrc, slots_4.io.out_uop.debug_fsrc connect issue_slots[4].out_uop.bp_xcpt_if, slots_4.io.out_uop.bp_xcpt_if connect issue_slots[4].out_uop.bp_debug_if, slots_4.io.out_uop.bp_debug_if connect issue_slots[4].out_uop.xcpt_ma_if, slots_4.io.out_uop.xcpt_ma_if connect issue_slots[4].out_uop.xcpt_ae_if, slots_4.io.out_uop.xcpt_ae_if connect issue_slots[4].out_uop.xcpt_pf_if, slots_4.io.out_uop.xcpt_pf_if connect issue_slots[4].out_uop.fp_single, slots_4.io.out_uop.fp_single connect issue_slots[4].out_uop.fp_val, slots_4.io.out_uop.fp_val connect issue_slots[4].out_uop.frs3_en, slots_4.io.out_uop.frs3_en connect issue_slots[4].out_uop.lrs2_rtype, slots_4.io.out_uop.lrs2_rtype connect issue_slots[4].out_uop.lrs1_rtype, slots_4.io.out_uop.lrs1_rtype connect issue_slots[4].out_uop.dst_rtype, slots_4.io.out_uop.dst_rtype connect issue_slots[4].out_uop.ldst_val, slots_4.io.out_uop.ldst_val connect issue_slots[4].out_uop.lrs3, slots_4.io.out_uop.lrs3 connect issue_slots[4].out_uop.lrs2, slots_4.io.out_uop.lrs2 connect issue_slots[4].out_uop.lrs1, slots_4.io.out_uop.lrs1 connect issue_slots[4].out_uop.ldst, slots_4.io.out_uop.ldst connect issue_slots[4].out_uop.ldst_is_rs1, slots_4.io.out_uop.ldst_is_rs1 connect issue_slots[4].out_uop.flush_on_commit, slots_4.io.out_uop.flush_on_commit connect issue_slots[4].out_uop.is_unique, slots_4.io.out_uop.is_unique connect issue_slots[4].out_uop.is_sys_pc2epc, slots_4.io.out_uop.is_sys_pc2epc connect issue_slots[4].out_uop.uses_stq, slots_4.io.out_uop.uses_stq connect issue_slots[4].out_uop.uses_ldq, slots_4.io.out_uop.uses_ldq connect issue_slots[4].out_uop.is_amo, slots_4.io.out_uop.is_amo connect issue_slots[4].out_uop.is_fencei, slots_4.io.out_uop.is_fencei connect issue_slots[4].out_uop.is_fence, slots_4.io.out_uop.is_fence connect issue_slots[4].out_uop.mem_signed, slots_4.io.out_uop.mem_signed connect issue_slots[4].out_uop.mem_size, slots_4.io.out_uop.mem_size connect issue_slots[4].out_uop.mem_cmd, slots_4.io.out_uop.mem_cmd connect issue_slots[4].out_uop.bypassable, slots_4.io.out_uop.bypassable connect issue_slots[4].out_uop.exc_cause, slots_4.io.out_uop.exc_cause connect issue_slots[4].out_uop.exception, slots_4.io.out_uop.exception connect issue_slots[4].out_uop.stale_pdst, slots_4.io.out_uop.stale_pdst connect issue_slots[4].out_uop.ppred_busy, slots_4.io.out_uop.ppred_busy connect issue_slots[4].out_uop.prs3_busy, slots_4.io.out_uop.prs3_busy connect issue_slots[4].out_uop.prs2_busy, slots_4.io.out_uop.prs2_busy connect issue_slots[4].out_uop.prs1_busy, slots_4.io.out_uop.prs1_busy connect issue_slots[4].out_uop.ppred, slots_4.io.out_uop.ppred connect issue_slots[4].out_uop.prs3, slots_4.io.out_uop.prs3 connect issue_slots[4].out_uop.prs2, slots_4.io.out_uop.prs2 connect issue_slots[4].out_uop.prs1, slots_4.io.out_uop.prs1 connect issue_slots[4].out_uop.pdst, slots_4.io.out_uop.pdst connect issue_slots[4].out_uop.rxq_idx, slots_4.io.out_uop.rxq_idx connect issue_slots[4].out_uop.stq_idx, slots_4.io.out_uop.stq_idx connect issue_slots[4].out_uop.ldq_idx, slots_4.io.out_uop.ldq_idx connect issue_slots[4].out_uop.rob_idx, slots_4.io.out_uop.rob_idx connect issue_slots[4].out_uop.csr_addr, slots_4.io.out_uop.csr_addr connect issue_slots[4].out_uop.imm_packed, slots_4.io.out_uop.imm_packed connect issue_slots[4].out_uop.taken, slots_4.io.out_uop.taken connect issue_slots[4].out_uop.pc_lob, slots_4.io.out_uop.pc_lob connect issue_slots[4].out_uop.edge_inst, slots_4.io.out_uop.edge_inst connect issue_slots[4].out_uop.ftq_idx, slots_4.io.out_uop.ftq_idx connect issue_slots[4].out_uop.br_tag, slots_4.io.out_uop.br_tag connect issue_slots[4].out_uop.br_mask, slots_4.io.out_uop.br_mask connect issue_slots[4].out_uop.is_sfb, slots_4.io.out_uop.is_sfb connect issue_slots[4].out_uop.is_jal, slots_4.io.out_uop.is_jal connect issue_slots[4].out_uop.is_jalr, slots_4.io.out_uop.is_jalr connect issue_slots[4].out_uop.is_br, slots_4.io.out_uop.is_br connect issue_slots[4].out_uop.iw_p2_poisoned, slots_4.io.out_uop.iw_p2_poisoned connect issue_slots[4].out_uop.iw_p1_poisoned, slots_4.io.out_uop.iw_p1_poisoned connect issue_slots[4].out_uop.iw_state, slots_4.io.out_uop.iw_state connect issue_slots[4].out_uop.ctrl.is_std, slots_4.io.out_uop.ctrl.is_std connect issue_slots[4].out_uop.ctrl.is_sta, slots_4.io.out_uop.ctrl.is_sta connect issue_slots[4].out_uop.ctrl.is_load, slots_4.io.out_uop.ctrl.is_load connect issue_slots[4].out_uop.ctrl.csr_cmd, slots_4.io.out_uop.ctrl.csr_cmd connect issue_slots[4].out_uop.ctrl.fcn_dw, slots_4.io.out_uop.ctrl.fcn_dw connect issue_slots[4].out_uop.ctrl.op_fcn, slots_4.io.out_uop.ctrl.op_fcn connect issue_slots[4].out_uop.ctrl.imm_sel, slots_4.io.out_uop.ctrl.imm_sel connect issue_slots[4].out_uop.ctrl.op2_sel, slots_4.io.out_uop.ctrl.op2_sel connect issue_slots[4].out_uop.ctrl.op1_sel, slots_4.io.out_uop.ctrl.op1_sel connect issue_slots[4].out_uop.ctrl.br_type, slots_4.io.out_uop.ctrl.br_type connect issue_slots[4].out_uop.fu_code, slots_4.io.out_uop.fu_code connect issue_slots[4].out_uop.iq_type, slots_4.io.out_uop.iq_type connect issue_slots[4].out_uop.debug_pc, slots_4.io.out_uop.debug_pc connect issue_slots[4].out_uop.is_rvc, slots_4.io.out_uop.is_rvc connect issue_slots[4].out_uop.debug_inst, slots_4.io.out_uop.debug_inst connect issue_slots[4].out_uop.inst, slots_4.io.out_uop.inst connect issue_slots[4].out_uop.uopc, slots_4.io.out_uop.uopc connect slots_4.io.in_uop.bits.debug_tsrc, issue_slots[4].in_uop.bits.debug_tsrc connect slots_4.io.in_uop.bits.debug_fsrc, issue_slots[4].in_uop.bits.debug_fsrc connect slots_4.io.in_uop.bits.bp_xcpt_if, issue_slots[4].in_uop.bits.bp_xcpt_if connect slots_4.io.in_uop.bits.bp_debug_if, issue_slots[4].in_uop.bits.bp_debug_if connect slots_4.io.in_uop.bits.xcpt_ma_if, issue_slots[4].in_uop.bits.xcpt_ma_if connect slots_4.io.in_uop.bits.xcpt_ae_if, issue_slots[4].in_uop.bits.xcpt_ae_if connect slots_4.io.in_uop.bits.xcpt_pf_if, issue_slots[4].in_uop.bits.xcpt_pf_if connect slots_4.io.in_uop.bits.fp_single, issue_slots[4].in_uop.bits.fp_single connect slots_4.io.in_uop.bits.fp_val, issue_slots[4].in_uop.bits.fp_val connect slots_4.io.in_uop.bits.frs3_en, issue_slots[4].in_uop.bits.frs3_en connect slots_4.io.in_uop.bits.lrs2_rtype, issue_slots[4].in_uop.bits.lrs2_rtype connect slots_4.io.in_uop.bits.lrs1_rtype, issue_slots[4].in_uop.bits.lrs1_rtype connect slots_4.io.in_uop.bits.dst_rtype, issue_slots[4].in_uop.bits.dst_rtype connect slots_4.io.in_uop.bits.ldst_val, issue_slots[4].in_uop.bits.ldst_val connect slots_4.io.in_uop.bits.lrs3, issue_slots[4].in_uop.bits.lrs3 connect slots_4.io.in_uop.bits.lrs2, issue_slots[4].in_uop.bits.lrs2 connect slots_4.io.in_uop.bits.lrs1, issue_slots[4].in_uop.bits.lrs1 connect slots_4.io.in_uop.bits.ldst, issue_slots[4].in_uop.bits.ldst connect slots_4.io.in_uop.bits.ldst_is_rs1, issue_slots[4].in_uop.bits.ldst_is_rs1 connect slots_4.io.in_uop.bits.flush_on_commit, issue_slots[4].in_uop.bits.flush_on_commit connect slots_4.io.in_uop.bits.is_unique, issue_slots[4].in_uop.bits.is_unique connect slots_4.io.in_uop.bits.is_sys_pc2epc, issue_slots[4].in_uop.bits.is_sys_pc2epc connect slots_4.io.in_uop.bits.uses_stq, issue_slots[4].in_uop.bits.uses_stq connect slots_4.io.in_uop.bits.uses_ldq, issue_slots[4].in_uop.bits.uses_ldq connect slots_4.io.in_uop.bits.is_amo, issue_slots[4].in_uop.bits.is_amo connect slots_4.io.in_uop.bits.is_fencei, issue_slots[4].in_uop.bits.is_fencei connect slots_4.io.in_uop.bits.is_fence, issue_slots[4].in_uop.bits.is_fence connect slots_4.io.in_uop.bits.mem_signed, issue_slots[4].in_uop.bits.mem_signed connect slots_4.io.in_uop.bits.mem_size, issue_slots[4].in_uop.bits.mem_size connect slots_4.io.in_uop.bits.mem_cmd, issue_slots[4].in_uop.bits.mem_cmd connect slots_4.io.in_uop.bits.bypassable, issue_slots[4].in_uop.bits.bypassable connect slots_4.io.in_uop.bits.exc_cause, issue_slots[4].in_uop.bits.exc_cause connect slots_4.io.in_uop.bits.exception, issue_slots[4].in_uop.bits.exception connect slots_4.io.in_uop.bits.stale_pdst, issue_slots[4].in_uop.bits.stale_pdst connect slots_4.io.in_uop.bits.ppred_busy, issue_slots[4].in_uop.bits.ppred_busy connect slots_4.io.in_uop.bits.prs3_busy, issue_slots[4].in_uop.bits.prs3_busy connect slots_4.io.in_uop.bits.prs2_busy, issue_slots[4].in_uop.bits.prs2_busy connect slots_4.io.in_uop.bits.prs1_busy, issue_slots[4].in_uop.bits.prs1_busy connect slots_4.io.in_uop.bits.ppred, issue_slots[4].in_uop.bits.ppred connect slots_4.io.in_uop.bits.prs3, issue_slots[4].in_uop.bits.prs3 connect slots_4.io.in_uop.bits.prs2, issue_slots[4].in_uop.bits.prs2 connect slots_4.io.in_uop.bits.prs1, issue_slots[4].in_uop.bits.prs1 connect slots_4.io.in_uop.bits.pdst, issue_slots[4].in_uop.bits.pdst connect slots_4.io.in_uop.bits.rxq_idx, issue_slots[4].in_uop.bits.rxq_idx connect slots_4.io.in_uop.bits.stq_idx, issue_slots[4].in_uop.bits.stq_idx connect slots_4.io.in_uop.bits.ldq_idx, issue_slots[4].in_uop.bits.ldq_idx connect slots_4.io.in_uop.bits.rob_idx, issue_slots[4].in_uop.bits.rob_idx connect slots_4.io.in_uop.bits.csr_addr, issue_slots[4].in_uop.bits.csr_addr connect slots_4.io.in_uop.bits.imm_packed, issue_slots[4].in_uop.bits.imm_packed connect slots_4.io.in_uop.bits.taken, issue_slots[4].in_uop.bits.taken connect slots_4.io.in_uop.bits.pc_lob, issue_slots[4].in_uop.bits.pc_lob connect slots_4.io.in_uop.bits.edge_inst, issue_slots[4].in_uop.bits.edge_inst connect slots_4.io.in_uop.bits.ftq_idx, issue_slots[4].in_uop.bits.ftq_idx connect slots_4.io.in_uop.bits.br_tag, issue_slots[4].in_uop.bits.br_tag connect slots_4.io.in_uop.bits.br_mask, issue_slots[4].in_uop.bits.br_mask connect slots_4.io.in_uop.bits.is_sfb, issue_slots[4].in_uop.bits.is_sfb connect slots_4.io.in_uop.bits.is_jal, issue_slots[4].in_uop.bits.is_jal connect slots_4.io.in_uop.bits.is_jalr, issue_slots[4].in_uop.bits.is_jalr connect slots_4.io.in_uop.bits.is_br, issue_slots[4].in_uop.bits.is_br connect slots_4.io.in_uop.bits.iw_p2_poisoned, issue_slots[4].in_uop.bits.iw_p2_poisoned connect slots_4.io.in_uop.bits.iw_p1_poisoned, issue_slots[4].in_uop.bits.iw_p1_poisoned connect slots_4.io.in_uop.bits.iw_state, issue_slots[4].in_uop.bits.iw_state connect slots_4.io.in_uop.bits.ctrl.is_std, issue_slots[4].in_uop.bits.ctrl.is_std connect slots_4.io.in_uop.bits.ctrl.is_sta, issue_slots[4].in_uop.bits.ctrl.is_sta connect slots_4.io.in_uop.bits.ctrl.is_load, issue_slots[4].in_uop.bits.ctrl.is_load connect slots_4.io.in_uop.bits.ctrl.csr_cmd, issue_slots[4].in_uop.bits.ctrl.csr_cmd connect slots_4.io.in_uop.bits.ctrl.fcn_dw, issue_slots[4].in_uop.bits.ctrl.fcn_dw connect slots_4.io.in_uop.bits.ctrl.op_fcn, issue_slots[4].in_uop.bits.ctrl.op_fcn connect slots_4.io.in_uop.bits.ctrl.imm_sel, issue_slots[4].in_uop.bits.ctrl.imm_sel connect slots_4.io.in_uop.bits.ctrl.op2_sel, issue_slots[4].in_uop.bits.ctrl.op2_sel connect slots_4.io.in_uop.bits.ctrl.op1_sel, issue_slots[4].in_uop.bits.ctrl.op1_sel connect slots_4.io.in_uop.bits.ctrl.br_type, issue_slots[4].in_uop.bits.ctrl.br_type connect slots_4.io.in_uop.bits.fu_code, issue_slots[4].in_uop.bits.fu_code connect slots_4.io.in_uop.bits.iq_type, issue_slots[4].in_uop.bits.iq_type connect slots_4.io.in_uop.bits.debug_pc, issue_slots[4].in_uop.bits.debug_pc connect slots_4.io.in_uop.bits.is_rvc, issue_slots[4].in_uop.bits.is_rvc connect slots_4.io.in_uop.bits.debug_inst, issue_slots[4].in_uop.bits.debug_inst connect slots_4.io.in_uop.bits.inst, issue_slots[4].in_uop.bits.inst connect slots_4.io.in_uop.bits.uopc, issue_slots[4].in_uop.bits.uopc connect slots_4.io.in_uop.valid, issue_slots[4].in_uop.valid connect slots_4.io.spec_ld_wakeup[0].bits, issue_slots[4].spec_ld_wakeup[0].bits connect slots_4.io.spec_ld_wakeup[0].valid, issue_slots[4].spec_ld_wakeup[0].valid connect slots_4.io.pred_wakeup_port.bits, issue_slots[4].pred_wakeup_port.bits connect slots_4.io.pred_wakeup_port.valid, issue_slots[4].pred_wakeup_port.valid connect slots_4.io.wakeup_ports[0].bits.poisoned, issue_slots[4].wakeup_ports[0].bits.poisoned connect slots_4.io.wakeup_ports[0].bits.pdst, issue_slots[4].wakeup_ports[0].bits.pdst connect slots_4.io.wakeup_ports[0].valid, issue_slots[4].wakeup_ports[0].valid connect slots_4.io.wakeup_ports[1].bits.poisoned, issue_slots[4].wakeup_ports[1].bits.poisoned connect slots_4.io.wakeup_ports[1].bits.pdst, issue_slots[4].wakeup_ports[1].bits.pdst connect slots_4.io.wakeup_ports[1].valid, issue_slots[4].wakeup_ports[1].valid connect slots_4.io.ldspec_miss, issue_slots[4].ldspec_miss connect slots_4.io.clear, issue_slots[4].clear connect slots_4.io.kill, issue_slots[4].kill connect slots_4.io.brupdate.b2.target_offset, issue_slots[4].brupdate.b2.target_offset connect slots_4.io.brupdate.b2.jalr_target, issue_slots[4].brupdate.b2.jalr_target connect slots_4.io.brupdate.b2.pc_sel, issue_slots[4].brupdate.b2.pc_sel connect slots_4.io.brupdate.b2.cfi_type, issue_slots[4].brupdate.b2.cfi_type connect slots_4.io.brupdate.b2.taken, issue_slots[4].brupdate.b2.taken connect slots_4.io.brupdate.b2.mispredict, issue_slots[4].brupdate.b2.mispredict connect slots_4.io.brupdate.b2.valid, issue_slots[4].brupdate.b2.valid connect slots_4.io.brupdate.b2.uop.debug_tsrc, issue_slots[4].brupdate.b2.uop.debug_tsrc connect slots_4.io.brupdate.b2.uop.debug_fsrc, issue_slots[4].brupdate.b2.uop.debug_fsrc connect slots_4.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[4].brupdate.b2.uop.bp_xcpt_if connect slots_4.io.brupdate.b2.uop.bp_debug_if, issue_slots[4].brupdate.b2.uop.bp_debug_if connect slots_4.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[4].brupdate.b2.uop.xcpt_ma_if connect slots_4.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[4].brupdate.b2.uop.xcpt_ae_if connect slots_4.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[4].brupdate.b2.uop.xcpt_pf_if connect slots_4.io.brupdate.b2.uop.fp_single, issue_slots[4].brupdate.b2.uop.fp_single connect slots_4.io.brupdate.b2.uop.fp_val, issue_slots[4].brupdate.b2.uop.fp_val connect slots_4.io.brupdate.b2.uop.frs3_en, issue_slots[4].brupdate.b2.uop.frs3_en connect slots_4.io.brupdate.b2.uop.lrs2_rtype, issue_slots[4].brupdate.b2.uop.lrs2_rtype connect slots_4.io.brupdate.b2.uop.lrs1_rtype, issue_slots[4].brupdate.b2.uop.lrs1_rtype connect slots_4.io.brupdate.b2.uop.dst_rtype, issue_slots[4].brupdate.b2.uop.dst_rtype connect slots_4.io.brupdate.b2.uop.ldst_val, issue_slots[4].brupdate.b2.uop.ldst_val connect slots_4.io.brupdate.b2.uop.lrs3, issue_slots[4].brupdate.b2.uop.lrs3 connect slots_4.io.brupdate.b2.uop.lrs2, issue_slots[4].brupdate.b2.uop.lrs2 connect slots_4.io.brupdate.b2.uop.lrs1, issue_slots[4].brupdate.b2.uop.lrs1 connect slots_4.io.brupdate.b2.uop.ldst, issue_slots[4].brupdate.b2.uop.ldst connect slots_4.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[4].brupdate.b2.uop.ldst_is_rs1 connect slots_4.io.brupdate.b2.uop.flush_on_commit, issue_slots[4].brupdate.b2.uop.flush_on_commit connect slots_4.io.brupdate.b2.uop.is_unique, issue_slots[4].brupdate.b2.uop.is_unique connect slots_4.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[4].brupdate.b2.uop.is_sys_pc2epc connect slots_4.io.brupdate.b2.uop.uses_stq, issue_slots[4].brupdate.b2.uop.uses_stq connect slots_4.io.brupdate.b2.uop.uses_ldq, issue_slots[4].brupdate.b2.uop.uses_ldq connect slots_4.io.brupdate.b2.uop.is_amo, issue_slots[4].brupdate.b2.uop.is_amo connect slots_4.io.brupdate.b2.uop.is_fencei, issue_slots[4].brupdate.b2.uop.is_fencei connect slots_4.io.brupdate.b2.uop.is_fence, issue_slots[4].brupdate.b2.uop.is_fence connect slots_4.io.brupdate.b2.uop.mem_signed, issue_slots[4].brupdate.b2.uop.mem_signed connect slots_4.io.brupdate.b2.uop.mem_size, issue_slots[4].brupdate.b2.uop.mem_size connect slots_4.io.brupdate.b2.uop.mem_cmd, issue_slots[4].brupdate.b2.uop.mem_cmd connect slots_4.io.brupdate.b2.uop.bypassable, issue_slots[4].brupdate.b2.uop.bypassable connect slots_4.io.brupdate.b2.uop.exc_cause, issue_slots[4].brupdate.b2.uop.exc_cause connect slots_4.io.brupdate.b2.uop.exception, issue_slots[4].brupdate.b2.uop.exception connect slots_4.io.brupdate.b2.uop.stale_pdst, issue_slots[4].brupdate.b2.uop.stale_pdst connect slots_4.io.brupdate.b2.uop.ppred_busy, issue_slots[4].brupdate.b2.uop.ppred_busy connect slots_4.io.brupdate.b2.uop.prs3_busy, issue_slots[4].brupdate.b2.uop.prs3_busy connect slots_4.io.brupdate.b2.uop.prs2_busy, issue_slots[4].brupdate.b2.uop.prs2_busy connect slots_4.io.brupdate.b2.uop.prs1_busy, issue_slots[4].brupdate.b2.uop.prs1_busy connect slots_4.io.brupdate.b2.uop.ppred, issue_slots[4].brupdate.b2.uop.ppred connect slots_4.io.brupdate.b2.uop.prs3, issue_slots[4].brupdate.b2.uop.prs3 connect slots_4.io.brupdate.b2.uop.prs2, issue_slots[4].brupdate.b2.uop.prs2 connect slots_4.io.brupdate.b2.uop.prs1, issue_slots[4].brupdate.b2.uop.prs1 connect slots_4.io.brupdate.b2.uop.pdst, issue_slots[4].brupdate.b2.uop.pdst connect slots_4.io.brupdate.b2.uop.rxq_idx, issue_slots[4].brupdate.b2.uop.rxq_idx connect slots_4.io.brupdate.b2.uop.stq_idx, issue_slots[4].brupdate.b2.uop.stq_idx connect slots_4.io.brupdate.b2.uop.ldq_idx, issue_slots[4].brupdate.b2.uop.ldq_idx connect slots_4.io.brupdate.b2.uop.rob_idx, issue_slots[4].brupdate.b2.uop.rob_idx connect slots_4.io.brupdate.b2.uop.csr_addr, issue_slots[4].brupdate.b2.uop.csr_addr connect slots_4.io.brupdate.b2.uop.imm_packed, issue_slots[4].brupdate.b2.uop.imm_packed connect slots_4.io.brupdate.b2.uop.taken, issue_slots[4].brupdate.b2.uop.taken connect slots_4.io.brupdate.b2.uop.pc_lob, issue_slots[4].brupdate.b2.uop.pc_lob connect slots_4.io.brupdate.b2.uop.edge_inst, issue_slots[4].brupdate.b2.uop.edge_inst connect slots_4.io.brupdate.b2.uop.ftq_idx, issue_slots[4].brupdate.b2.uop.ftq_idx connect slots_4.io.brupdate.b2.uop.br_tag, issue_slots[4].brupdate.b2.uop.br_tag connect slots_4.io.brupdate.b2.uop.br_mask, issue_slots[4].brupdate.b2.uop.br_mask connect slots_4.io.brupdate.b2.uop.is_sfb, issue_slots[4].brupdate.b2.uop.is_sfb connect slots_4.io.brupdate.b2.uop.is_jal, issue_slots[4].brupdate.b2.uop.is_jal connect slots_4.io.brupdate.b2.uop.is_jalr, issue_slots[4].brupdate.b2.uop.is_jalr connect slots_4.io.brupdate.b2.uop.is_br, issue_slots[4].brupdate.b2.uop.is_br connect slots_4.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[4].brupdate.b2.uop.iw_p2_poisoned connect slots_4.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[4].brupdate.b2.uop.iw_p1_poisoned connect slots_4.io.brupdate.b2.uop.iw_state, issue_slots[4].brupdate.b2.uop.iw_state connect slots_4.io.brupdate.b2.uop.ctrl.is_std, issue_slots[4].brupdate.b2.uop.ctrl.is_std connect slots_4.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[4].brupdate.b2.uop.ctrl.is_sta connect slots_4.io.brupdate.b2.uop.ctrl.is_load, issue_slots[4].brupdate.b2.uop.ctrl.is_load connect slots_4.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[4].brupdate.b2.uop.ctrl.csr_cmd connect slots_4.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[4].brupdate.b2.uop.ctrl.fcn_dw connect slots_4.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[4].brupdate.b2.uop.ctrl.op_fcn connect slots_4.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[4].brupdate.b2.uop.ctrl.imm_sel connect slots_4.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[4].brupdate.b2.uop.ctrl.op2_sel connect slots_4.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[4].brupdate.b2.uop.ctrl.op1_sel connect slots_4.io.brupdate.b2.uop.ctrl.br_type, issue_slots[4].brupdate.b2.uop.ctrl.br_type connect slots_4.io.brupdate.b2.uop.fu_code, issue_slots[4].brupdate.b2.uop.fu_code connect slots_4.io.brupdate.b2.uop.iq_type, issue_slots[4].brupdate.b2.uop.iq_type connect slots_4.io.brupdate.b2.uop.debug_pc, issue_slots[4].brupdate.b2.uop.debug_pc connect slots_4.io.brupdate.b2.uop.is_rvc, issue_slots[4].brupdate.b2.uop.is_rvc connect slots_4.io.brupdate.b2.uop.debug_inst, issue_slots[4].brupdate.b2.uop.debug_inst connect slots_4.io.brupdate.b2.uop.inst, issue_slots[4].brupdate.b2.uop.inst connect slots_4.io.brupdate.b2.uop.uopc, issue_slots[4].brupdate.b2.uop.uopc connect slots_4.io.brupdate.b1.mispredict_mask, issue_slots[4].brupdate.b1.mispredict_mask connect slots_4.io.brupdate.b1.resolve_mask, issue_slots[4].brupdate.b1.resolve_mask connect slots_4.io.grant, issue_slots[4].grant connect issue_slots[4].request_hp, slots_4.io.request_hp connect issue_slots[4].request, slots_4.io.request connect issue_slots[4].will_be_valid, slots_4.io.will_be_valid connect issue_slots[4].valid, slots_4.io.valid connect issue_slots[5].debug.state, slots_5.io.debug.state connect issue_slots[5].debug.ppred, slots_5.io.debug.ppred connect issue_slots[5].debug.p3, slots_5.io.debug.p3 connect issue_slots[5].debug.p2, slots_5.io.debug.p2 connect issue_slots[5].debug.p1, slots_5.io.debug.p1 connect issue_slots[5].uop.debug_tsrc, slots_5.io.uop.debug_tsrc connect issue_slots[5].uop.debug_fsrc, slots_5.io.uop.debug_fsrc connect issue_slots[5].uop.bp_xcpt_if, slots_5.io.uop.bp_xcpt_if connect issue_slots[5].uop.bp_debug_if, slots_5.io.uop.bp_debug_if connect issue_slots[5].uop.xcpt_ma_if, slots_5.io.uop.xcpt_ma_if connect issue_slots[5].uop.xcpt_ae_if, slots_5.io.uop.xcpt_ae_if connect issue_slots[5].uop.xcpt_pf_if, slots_5.io.uop.xcpt_pf_if connect issue_slots[5].uop.fp_single, slots_5.io.uop.fp_single connect issue_slots[5].uop.fp_val, slots_5.io.uop.fp_val connect issue_slots[5].uop.frs3_en, slots_5.io.uop.frs3_en connect issue_slots[5].uop.lrs2_rtype, slots_5.io.uop.lrs2_rtype connect issue_slots[5].uop.lrs1_rtype, slots_5.io.uop.lrs1_rtype connect issue_slots[5].uop.dst_rtype, slots_5.io.uop.dst_rtype connect issue_slots[5].uop.ldst_val, slots_5.io.uop.ldst_val connect issue_slots[5].uop.lrs3, slots_5.io.uop.lrs3 connect issue_slots[5].uop.lrs2, slots_5.io.uop.lrs2 connect issue_slots[5].uop.lrs1, slots_5.io.uop.lrs1 connect issue_slots[5].uop.ldst, slots_5.io.uop.ldst connect issue_slots[5].uop.ldst_is_rs1, slots_5.io.uop.ldst_is_rs1 connect issue_slots[5].uop.flush_on_commit, slots_5.io.uop.flush_on_commit connect issue_slots[5].uop.is_unique, slots_5.io.uop.is_unique connect issue_slots[5].uop.is_sys_pc2epc, slots_5.io.uop.is_sys_pc2epc connect issue_slots[5].uop.uses_stq, slots_5.io.uop.uses_stq connect issue_slots[5].uop.uses_ldq, slots_5.io.uop.uses_ldq connect issue_slots[5].uop.is_amo, slots_5.io.uop.is_amo connect issue_slots[5].uop.is_fencei, slots_5.io.uop.is_fencei connect issue_slots[5].uop.is_fence, slots_5.io.uop.is_fence connect issue_slots[5].uop.mem_signed, slots_5.io.uop.mem_signed connect issue_slots[5].uop.mem_size, slots_5.io.uop.mem_size connect issue_slots[5].uop.mem_cmd, slots_5.io.uop.mem_cmd connect issue_slots[5].uop.bypassable, slots_5.io.uop.bypassable connect issue_slots[5].uop.exc_cause, slots_5.io.uop.exc_cause connect issue_slots[5].uop.exception, slots_5.io.uop.exception connect issue_slots[5].uop.stale_pdst, slots_5.io.uop.stale_pdst connect issue_slots[5].uop.ppred_busy, slots_5.io.uop.ppred_busy connect issue_slots[5].uop.prs3_busy, slots_5.io.uop.prs3_busy connect issue_slots[5].uop.prs2_busy, slots_5.io.uop.prs2_busy connect issue_slots[5].uop.prs1_busy, slots_5.io.uop.prs1_busy connect issue_slots[5].uop.ppred, slots_5.io.uop.ppred connect issue_slots[5].uop.prs3, slots_5.io.uop.prs3 connect issue_slots[5].uop.prs2, slots_5.io.uop.prs2 connect issue_slots[5].uop.prs1, slots_5.io.uop.prs1 connect issue_slots[5].uop.pdst, slots_5.io.uop.pdst connect issue_slots[5].uop.rxq_idx, slots_5.io.uop.rxq_idx connect issue_slots[5].uop.stq_idx, slots_5.io.uop.stq_idx connect issue_slots[5].uop.ldq_idx, slots_5.io.uop.ldq_idx connect issue_slots[5].uop.rob_idx, slots_5.io.uop.rob_idx connect issue_slots[5].uop.csr_addr, slots_5.io.uop.csr_addr connect issue_slots[5].uop.imm_packed, slots_5.io.uop.imm_packed connect issue_slots[5].uop.taken, slots_5.io.uop.taken connect issue_slots[5].uop.pc_lob, slots_5.io.uop.pc_lob connect issue_slots[5].uop.edge_inst, slots_5.io.uop.edge_inst connect issue_slots[5].uop.ftq_idx, slots_5.io.uop.ftq_idx connect issue_slots[5].uop.br_tag, slots_5.io.uop.br_tag connect issue_slots[5].uop.br_mask, slots_5.io.uop.br_mask connect issue_slots[5].uop.is_sfb, slots_5.io.uop.is_sfb connect issue_slots[5].uop.is_jal, slots_5.io.uop.is_jal connect issue_slots[5].uop.is_jalr, slots_5.io.uop.is_jalr connect issue_slots[5].uop.is_br, slots_5.io.uop.is_br connect issue_slots[5].uop.iw_p2_poisoned, slots_5.io.uop.iw_p2_poisoned connect issue_slots[5].uop.iw_p1_poisoned, slots_5.io.uop.iw_p1_poisoned connect issue_slots[5].uop.iw_state, slots_5.io.uop.iw_state connect issue_slots[5].uop.ctrl.is_std, slots_5.io.uop.ctrl.is_std connect issue_slots[5].uop.ctrl.is_sta, slots_5.io.uop.ctrl.is_sta connect issue_slots[5].uop.ctrl.is_load, slots_5.io.uop.ctrl.is_load connect issue_slots[5].uop.ctrl.csr_cmd, slots_5.io.uop.ctrl.csr_cmd connect issue_slots[5].uop.ctrl.fcn_dw, slots_5.io.uop.ctrl.fcn_dw connect issue_slots[5].uop.ctrl.op_fcn, slots_5.io.uop.ctrl.op_fcn connect issue_slots[5].uop.ctrl.imm_sel, slots_5.io.uop.ctrl.imm_sel connect issue_slots[5].uop.ctrl.op2_sel, slots_5.io.uop.ctrl.op2_sel connect issue_slots[5].uop.ctrl.op1_sel, slots_5.io.uop.ctrl.op1_sel connect issue_slots[5].uop.ctrl.br_type, slots_5.io.uop.ctrl.br_type connect issue_slots[5].uop.fu_code, slots_5.io.uop.fu_code connect issue_slots[5].uop.iq_type, slots_5.io.uop.iq_type connect issue_slots[5].uop.debug_pc, slots_5.io.uop.debug_pc connect issue_slots[5].uop.is_rvc, slots_5.io.uop.is_rvc connect issue_slots[5].uop.debug_inst, slots_5.io.uop.debug_inst connect issue_slots[5].uop.inst, slots_5.io.uop.inst connect issue_slots[5].uop.uopc, slots_5.io.uop.uopc connect issue_slots[5].out_uop.debug_tsrc, slots_5.io.out_uop.debug_tsrc connect issue_slots[5].out_uop.debug_fsrc, slots_5.io.out_uop.debug_fsrc connect issue_slots[5].out_uop.bp_xcpt_if, slots_5.io.out_uop.bp_xcpt_if connect issue_slots[5].out_uop.bp_debug_if, slots_5.io.out_uop.bp_debug_if connect issue_slots[5].out_uop.xcpt_ma_if, slots_5.io.out_uop.xcpt_ma_if connect issue_slots[5].out_uop.xcpt_ae_if, slots_5.io.out_uop.xcpt_ae_if connect issue_slots[5].out_uop.xcpt_pf_if, slots_5.io.out_uop.xcpt_pf_if connect issue_slots[5].out_uop.fp_single, slots_5.io.out_uop.fp_single connect issue_slots[5].out_uop.fp_val, slots_5.io.out_uop.fp_val connect issue_slots[5].out_uop.frs3_en, slots_5.io.out_uop.frs3_en connect issue_slots[5].out_uop.lrs2_rtype, slots_5.io.out_uop.lrs2_rtype connect issue_slots[5].out_uop.lrs1_rtype, slots_5.io.out_uop.lrs1_rtype connect issue_slots[5].out_uop.dst_rtype, slots_5.io.out_uop.dst_rtype connect issue_slots[5].out_uop.ldst_val, slots_5.io.out_uop.ldst_val connect issue_slots[5].out_uop.lrs3, slots_5.io.out_uop.lrs3 connect issue_slots[5].out_uop.lrs2, slots_5.io.out_uop.lrs2 connect issue_slots[5].out_uop.lrs1, slots_5.io.out_uop.lrs1 connect issue_slots[5].out_uop.ldst, slots_5.io.out_uop.ldst connect issue_slots[5].out_uop.ldst_is_rs1, slots_5.io.out_uop.ldst_is_rs1 connect issue_slots[5].out_uop.flush_on_commit, slots_5.io.out_uop.flush_on_commit connect issue_slots[5].out_uop.is_unique, slots_5.io.out_uop.is_unique connect issue_slots[5].out_uop.is_sys_pc2epc, slots_5.io.out_uop.is_sys_pc2epc connect issue_slots[5].out_uop.uses_stq, slots_5.io.out_uop.uses_stq connect issue_slots[5].out_uop.uses_ldq, slots_5.io.out_uop.uses_ldq connect issue_slots[5].out_uop.is_amo, slots_5.io.out_uop.is_amo connect issue_slots[5].out_uop.is_fencei, slots_5.io.out_uop.is_fencei connect issue_slots[5].out_uop.is_fence, slots_5.io.out_uop.is_fence connect issue_slots[5].out_uop.mem_signed, slots_5.io.out_uop.mem_signed connect issue_slots[5].out_uop.mem_size, slots_5.io.out_uop.mem_size connect issue_slots[5].out_uop.mem_cmd, slots_5.io.out_uop.mem_cmd connect issue_slots[5].out_uop.bypassable, slots_5.io.out_uop.bypassable connect issue_slots[5].out_uop.exc_cause, slots_5.io.out_uop.exc_cause connect issue_slots[5].out_uop.exception, slots_5.io.out_uop.exception connect issue_slots[5].out_uop.stale_pdst, slots_5.io.out_uop.stale_pdst connect issue_slots[5].out_uop.ppred_busy, slots_5.io.out_uop.ppred_busy connect issue_slots[5].out_uop.prs3_busy, slots_5.io.out_uop.prs3_busy connect issue_slots[5].out_uop.prs2_busy, slots_5.io.out_uop.prs2_busy connect issue_slots[5].out_uop.prs1_busy, slots_5.io.out_uop.prs1_busy connect issue_slots[5].out_uop.ppred, slots_5.io.out_uop.ppred connect issue_slots[5].out_uop.prs3, slots_5.io.out_uop.prs3 connect issue_slots[5].out_uop.prs2, slots_5.io.out_uop.prs2 connect issue_slots[5].out_uop.prs1, slots_5.io.out_uop.prs1 connect issue_slots[5].out_uop.pdst, slots_5.io.out_uop.pdst connect issue_slots[5].out_uop.rxq_idx, slots_5.io.out_uop.rxq_idx connect issue_slots[5].out_uop.stq_idx, slots_5.io.out_uop.stq_idx connect issue_slots[5].out_uop.ldq_idx, slots_5.io.out_uop.ldq_idx connect issue_slots[5].out_uop.rob_idx, slots_5.io.out_uop.rob_idx connect issue_slots[5].out_uop.csr_addr, slots_5.io.out_uop.csr_addr connect issue_slots[5].out_uop.imm_packed, slots_5.io.out_uop.imm_packed connect issue_slots[5].out_uop.taken, slots_5.io.out_uop.taken connect issue_slots[5].out_uop.pc_lob, slots_5.io.out_uop.pc_lob connect issue_slots[5].out_uop.edge_inst, slots_5.io.out_uop.edge_inst connect issue_slots[5].out_uop.ftq_idx, slots_5.io.out_uop.ftq_idx connect issue_slots[5].out_uop.br_tag, slots_5.io.out_uop.br_tag connect issue_slots[5].out_uop.br_mask, slots_5.io.out_uop.br_mask connect issue_slots[5].out_uop.is_sfb, slots_5.io.out_uop.is_sfb connect issue_slots[5].out_uop.is_jal, slots_5.io.out_uop.is_jal connect issue_slots[5].out_uop.is_jalr, slots_5.io.out_uop.is_jalr connect issue_slots[5].out_uop.is_br, slots_5.io.out_uop.is_br connect issue_slots[5].out_uop.iw_p2_poisoned, slots_5.io.out_uop.iw_p2_poisoned connect issue_slots[5].out_uop.iw_p1_poisoned, slots_5.io.out_uop.iw_p1_poisoned connect issue_slots[5].out_uop.iw_state, slots_5.io.out_uop.iw_state connect issue_slots[5].out_uop.ctrl.is_std, slots_5.io.out_uop.ctrl.is_std connect issue_slots[5].out_uop.ctrl.is_sta, slots_5.io.out_uop.ctrl.is_sta connect issue_slots[5].out_uop.ctrl.is_load, slots_5.io.out_uop.ctrl.is_load connect issue_slots[5].out_uop.ctrl.csr_cmd, slots_5.io.out_uop.ctrl.csr_cmd connect issue_slots[5].out_uop.ctrl.fcn_dw, slots_5.io.out_uop.ctrl.fcn_dw connect issue_slots[5].out_uop.ctrl.op_fcn, slots_5.io.out_uop.ctrl.op_fcn connect issue_slots[5].out_uop.ctrl.imm_sel, slots_5.io.out_uop.ctrl.imm_sel connect issue_slots[5].out_uop.ctrl.op2_sel, slots_5.io.out_uop.ctrl.op2_sel connect issue_slots[5].out_uop.ctrl.op1_sel, slots_5.io.out_uop.ctrl.op1_sel connect issue_slots[5].out_uop.ctrl.br_type, slots_5.io.out_uop.ctrl.br_type connect issue_slots[5].out_uop.fu_code, slots_5.io.out_uop.fu_code connect issue_slots[5].out_uop.iq_type, slots_5.io.out_uop.iq_type connect issue_slots[5].out_uop.debug_pc, slots_5.io.out_uop.debug_pc connect issue_slots[5].out_uop.is_rvc, slots_5.io.out_uop.is_rvc connect issue_slots[5].out_uop.debug_inst, slots_5.io.out_uop.debug_inst connect issue_slots[5].out_uop.inst, slots_5.io.out_uop.inst connect issue_slots[5].out_uop.uopc, slots_5.io.out_uop.uopc connect slots_5.io.in_uop.bits.debug_tsrc, issue_slots[5].in_uop.bits.debug_tsrc connect slots_5.io.in_uop.bits.debug_fsrc, issue_slots[5].in_uop.bits.debug_fsrc connect slots_5.io.in_uop.bits.bp_xcpt_if, issue_slots[5].in_uop.bits.bp_xcpt_if connect slots_5.io.in_uop.bits.bp_debug_if, issue_slots[5].in_uop.bits.bp_debug_if connect slots_5.io.in_uop.bits.xcpt_ma_if, issue_slots[5].in_uop.bits.xcpt_ma_if connect slots_5.io.in_uop.bits.xcpt_ae_if, issue_slots[5].in_uop.bits.xcpt_ae_if connect slots_5.io.in_uop.bits.xcpt_pf_if, issue_slots[5].in_uop.bits.xcpt_pf_if connect slots_5.io.in_uop.bits.fp_single, issue_slots[5].in_uop.bits.fp_single connect slots_5.io.in_uop.bits.fp_val, issue_slots[5].in_uop.bits.fp_val connect slots_5.io.in_uop.bits.frs3_en, issue_slots[5].in_uop.bits.frs3_en connect slots_5.io.in_uop.bits.lrs2_rtype, issue_slots[5].in_uop.bits.lrs2_rtype connect slots_5.io.in_uop.bits.lrs1_rtype, issue_slots[5].in_uop.bits.lrs1_rtype connect slots_5.io.in_uop.bits.dst_rtype, issue_slots[5].in_uop.bits.dst_rtype connect slots_5.io.in_uop.bits.ldst_val, issue_slots[5].in_uop.bits.ldst_val connect slots_5.io.in_uop.bits.lrs3, issue_slots[5].in_uop.bits.lrs3 connect slots_5.io.in_uop.bits.lrs2, issue_slots[5].in_uop.bits.lrs2 connect slots_5.io.in_uop.bits.lrs1, issue_slots[5].in_uop.bits.lrs1 connect slots_5.io.in_uop.bits.ldst, issue_slots[5].in_uop.bits.ldst connect slots_5.io.in_uop.bits.ldst_is_rs1, issue_slots[5].in_uop.bits.ldst_is_rs1 connect slots_5.io.in_uop.bits.flush_on_commit, issue_slots[5].in_uop.bits.flush_on_commit connect slots_5.io.in_uop.bits.is_unique, issue_slots[5].in_uop.bits.is_unique connect slots_5.io.in_uop.bits.is_sys_pc2epc, issue_slots[5].in_uop.bits.is_sys_pc2epc connect slots_5.io.in_uop.bits.uses_stq, issue_slots[5].in_uop.bits.uses_stq connect slots_5.io.in_uop.bits.uses_ldq, issue_slots[5].in_uop.bits.uses_ldq connect slots_5.io.in_uop.bits.is_amo, issue_slots[5].in_uop.bits.is_amo connect slots_5.io.in_uop.bits.is_fencei, issue_slots[5].in_uop.bits.is_fencei connect slots_5.io.in_uop.bits.is_fence, issue_slots[5].in_uop.bits.is_fence connect slots_5.io.in_uop.bits.mem_signed, issue_slots[5].in_uop.bits.mem_signed connect slots_5.io.in_uop.bits.mem_size, issue_slots[5].in_uop.bits.mem_size connect slots_5.io.in_uop.bits.mem_cmd, issue_slots[5].in_uop.bits.mem_cmd connect slots_5.io.in_uop.bits.bypassable, issue_slots[5].in_uop.bits.bypassable connect slots_5.io.in_uop.bits.exc_cause, issue_slots[5].in_uop.bits.exc_cause connect slots_5.io.in_uop.bits.exception, issue_slots[5].in_uop.bits.exception connect slots_5.io.in_uop.bits.stale_pdst, issue_slots[5].in_uop.bits.stale_pdst connect slots_5.io.in_uop.bits.ppred_busy, issue_slots[5].in_uop.bits.ppred_busy connect slots_5.io.in_uop.bits.prs3_busy, issue_slots[5].in_uop.bits.prs3_busy connect slots_5.io.in_uop.bits.prs2_busy, issue_slots[5].in_uop.bits.prs2_busy connect slots_5.io.in_uop.bits.prs1_busy, issue_slots[5].in_uop.bits.prs1_busy connect slots_5.io.in_uop.bits.ppred, issue_slots[5].in_uop.bits.ppred connect slots_5.io.in_uop.bits.prs3, issue_slots[5].in_uop.bits.prs3 connect slots_5.io.in_uop.bits.prs2, issue_slots[5].in_uop.bits.prs2 connect slots_5.io.in_uop.bits.prs1, issue_slots[5].in_uop.bits.prs1 connect slots_5.io.in_uop.bits.pdst, issue_slots[5].in_uop.bits.pdst connect slots_5.io.in_uop.bits.rxq_idx, issue_slots[5].in_uop.bits.rxq_idx connect slots_5.io.in_uop.bits.stq_idx, issue_slots[5].in_uop.bits.stq_idx connect slots_5.io.in_uop.bits.ldq_idx, issue_slots[5].in_uop.bits.ldq_idx connect slots_5.io.in_uop.bits.rob_idx, issue_slots[5].in_uop.bits.rob_idx connect slots_5.io.in_uop.bits.csr_addr, issue_slots[5].in_uop.bits.csr_addr connect slots_5.io.in_uop.bits.imm_packed, issue_slots[5].in_uop.bits.imm_packed connect slots_5.io.in_uop.bits.taken, issue_slots[5].in_uop.bits.taken connect slots_5.io.in_uop.bits.pc_lob, issue_slots[5].in_uop.bits.pc_lob connect slots_5.io.in_uop.bits.edge_inst, issue_slots[5].in_uop.bits.edge_inst connect slots_5.io.in_uop.bits.ftq_idx, issue_slots[5].in_uop.bits.ftq_idx connect slots_5.io.in_uop.bits.br_tag, issue_slots[5].in_uop.bits.br_tag connect slots_5.io.in_uop.bits.br_mask, issue_slots[5].in_uop.bits.br_mask connect slots_5.io.in_uop.bits.is_sfb, issue_slots[5].in_uop.bits.is_sfb connect slots_5.io.in_uop.bits.is_jal, issue_slots[5].in_uop.bits.is_jal connect slots_5.io.in_uop.bits.is_jalr, issue_slots[5].in_uop.bits.is_jalr connect slots_5.io.in_uop.bits.is_br, issue_slots[5].in_uop.bits.is_br connect slots_5.io.in_uop.bits.iw_p2_poisoned, issue_slots[5].in_uop.bits.iw_p2_poisoned connect slots_5.io.in_uop.bits.iw_p1_poisoned, issue_slots[5].in_uop.bits.iw_p1_poisoned connect slots_5.io.in_uop.bits.iw_state, issue_slots[5].in_uop.bits.iw_state connect slots_5.io.in_uop.bits.ctrl.is_std, issue_slots[5].in_uop.bits.ctrl.is_std connect slots_5.io.in_uop.bits.ctrl.is_sta, issue_slots[5].in_uop.bits.ctrl.is_sta connect slots_5.io.in_uop.bits.ctrl.is_load, issue_slots[5].in_uop.bits.ctrl.is_load connect slots_5.io.in_uop.bits.ctrl.csr_cmd, issue_slots[5].in_uop.bits.ctrl.csr_cmd connect slots_5.io.in_uop.bits.ctrl.fcn_dw, issue_slots[5].in_uop.bits.ctrl.fcn_dw connect slots_5.io.in_uop.bits.ctrl.op_fcn, issue_slots[5].in_uop.bits.ctrl.op_fcn connect slots_5.io.in_uop.bits.ctrl.imm_sel, issue_slots[5].in_uop.bits.ctrl.imm_sel connect slots_5.io.in_uop.bits.ctrl.op2_sel, issue_slots[5].in_uop.bits.ctrl.op2_sel connect slots_5.io.in_uop.bits.ctrl.op1_sel, issue_slots[5].in_uop.bits.ctrl.op1_sel connect slots_5.io.in_uop.bits.ctrl.br_type, issue_slots[5].in_uop.bits.ctrl.br_type connect slots_5.io.in_uop.bits.fu_code, issue_slots[5].in_uop.bits.fu_code connect slots_5.io.in_uop.bits.iq_type, issue_slots[5].in_uop.bits.iq_type connect slots_5.io.in_uop.bits.debug_pc, issue_slots[5].in_uop.bits.debug_pc connect slots_5.io.in_uop.bits.is_rvc, issue_slots[5].in_uop.bits.is_rvc connect slots_5.io.in_uop.bits.debug_inst, issue_slots[5].in_uop.bits.debug_inst connect slots_5.io.in_uop.bits.inst, issue_slots[5].in_uop.bits.inst connect slots_5.io.in_uop.bits.uopc, issue_slots[5].in_uop.bits.uopc connect slots_5.io.in_uop.valid, issue_slots[5].in_uop.valid connect slots_5.io.spec_ld_wakeup[0].bits, issue_slots[5].spec_ld_wakeup[0].bits connect slots_5.io.spec_ld_wakeup[0].valid, issue_slots[5].spec_ld_wakeup[0].valid connect slots_5.io.pred_wakeup_port.bits, issue_slots[5].pred_wakeup_port.bits connect slots_5.io.pred_wakeup_port.valid, issue_slots[5].pred_wakeup_port.valid connect slots_5.io.wakeup_ports[0].bits.poisoned, issue_slots[5].wakeup_ports[0].bits.poisoned connect slots_5.io.wakeup_ports[0].bits.pdst, issue_slots[5].wakeup_ports[0].bits.pdst connect slots_5.io.wakeup_ports[0].valid, issue_slots[5].wakeup_ports[0].valid connect slots_5.io.wakeup_ports[1].bits.poisoned, issue_slots[5].wakeup_ports[1].bits.poisoned connect slots_5.io.wakeup_ports[1].bits.pdst, issue_slots[5].wakeup_ports[1].bits.pdst connect slots_5.io.wakeup_ports[1].valid, issue_slots[5].wakeup_ports[1].valid connect slots_5.io.ldspec_miss, issue_slots[5].ldspec_miss connect slots_5.io.clear, issue_slots[5].clear connect slots_5.io.kill, issue_slots[5].kill connect slots_5.io.brupdate.b2.target_offset, issue_slots[5].brupdate.b2.target_offset connect slots_5.io.brupdate.b2.jalr_target, issue_slots[5].brupdate.b2.jalr_target connect slots_5.io.brupdate.b2.pc_sel, issue_slots[5].brupdate.b2.pc_sel connect slots_5.io.brupdate.b2.cfi_type, issue_slots[5].brupdate.b2.cfi_type connect slots_5.io.brupdate.b2.taken, issue_slots[5].brupdate.b2.taken connect slots_5.io.brupdate.b2.mispredict, issue_slots[5].brupdate.b2.mispredict connect slots_5.io.brupdate.b2.valid, issue_slots[5].brupdate.b2.valid connect slots_5.io.brupdate.b2.uop.debug_tsrc, issue_slots[5].brupdate.b2.uop.debug_tsrc connect slots_5.io.brupdate.b2.uop.debug_fsrc, issue_slots[5].brupdate.b2.uop.debug_fsrc connect slots_5.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[5].brupdate.b2.uop.bp_xcpt_if connect slots_5.io.brupdate.b2.uop.bp_debug_if, issue_slots[5].brupdate.b2.uop.bp_debug_if connect slots_5.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[5].brupdate.b2.uop.xcpt_ma_if connect slots_5.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[5].brupdate.b2.uop.xcpt_ae_if connect slots_5.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[5].brupdate.b2.uop.xcpt_pf_if connect slots_5.io.brupdate.b2.uop.fp_single, issue_slots[5].brupdate.b2.uop.fp_single connect slots_5.io.brupdate.b2.uop.fp_val, issue_slots[5].brupdate.b2.uop.fp_val connect slots_5.io.brupdate.b2.uop.frs3_en, issue_slots[5].brupdate.b2.uop.frs3_en connect slots_5.io.brupdate.b2.uop.lrs2_rtype, issue_slots[5].brupdate.b2.uop.lrs2_rtype connect slots_5.io.brupdate.b2.uop.lrs1_rtype, issue_slots[5].brupdate.b2.uop.lrs1_rtype connect slots_5.io.brupdate.b2.uop.dst_rtype, issue_slots[5].brupdate.b2.uop.dst_rtype connect slots_5.io.brupdate.b2.uop.ldst_val, issue_slots[5].brupdate.b2.uop.ldst_val connect slots_5.io.brupdate.b2.uop.lrs3, issue_slots[5].brupdate.b2.uop.lrs3 connect slots_5.io.brupdate.b2.uop.lrs2, issue_slots[5].brupdate.b2.uop.lrs2 connect slots_5.io.brupdate.b2.uop.lrs1, issue_slots[5].brupdate.b2.uop.lrs1 connect slots_5.io.brupdate.b2.uop.ldst, issue_slots[5].brupdate.b2.uop.ldst connect slots_5.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[5].brupdate.b2.uop.ldst_is_rs1 connect slots_5.io.brupdate.b2.uop.flush_on_commit, issue_slots[5].brupdate.b2.uop.flush_on_commit connect slots_5.io.brupdate.b2.uop.is_unique, issue_slots[5].brupdate.b2.uop.is_unique connect slots_5.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[5].brupdate.b2.uop.is_sys_pc2epc connect slots_5.io.brupdate.b2.uop.uses_stq, issue_slots[5].brupdate.b2.uop.uses_stq connect slots_5.io.brupdate.b2.uop.uses_ldq, issue_slots[5].brupdate.b2.uop.uses_ldq connect slots_5.io.brupdate.b2.uop.is_amo, issue_slots[5].brupdate.b2.uop.is_amo connect slots_5.io.brupdate.b2.uop.is_fencei, issue_slots[5].brupdate.b2.uop.is_fencei connect slots_5.io.brupdate.b2.uop.is_fence, issue_slots[5].brupdate.b2.uop.is_fence connect slots_5.io.brupdate.b2.uop.mem_signed, issue_slots[5].brupdate.b2.uop.mem_signed connect slots_5.io.brupdate.b2.uop.mem_size, issue_slots[5].brupdate.b2.uop.mem_size connect slots_5.io.brupdate.b2.uop.mem_cmd, issue_slots[5].brupdate.b2.uop.mem_cmd connect slots_5.io.brupdate.b2.uop.bypassable, issue_slots[5].brupdate.b2.uop.bypassable connect slots_5.io.brupdate.b2.uop.exc_cause, issue_slots[5].brupdate.b2.uop.exc_cause connect slots_5.io.brupdate.b2.uop.exception, issue_slots[5].brupdate.b2.uop.exception connect slots_5.io.brupdate.b2.uop.stale_pdst, issue_slots[5].brupdate.b2.uop.stale_pdst connect slots_5.io.brupdate.b2.uop.ppred_busy, issue_slots[5].brupdate.b2.uop.ppred_busy connect slots_5.io.brupdate.b2.uop.prs3_busy, issue_slots[5].brupdate.b2.uop.prs3_busy connect slots_5.io.brupdate.b2.uop.prs2_busy, issue_slots[5].brupdate.b2.uop.prs2_busy connect slots_5.io.brupdate.b2.uop.prs1_busy, issue_slots[5].brupdate.b2.uop.prs1_busy connect slots_5.io.brupdate.b2.uop.ppred, issue_slots[5].brupdate.b2.uop.ppred connect slots_5.io.brupdate.b2.uop.prs3, issue_slots[5].brupdate.b2.uop.prs3 connect slots_5.io.brupdate.b2.uop.prs2, issue_slots[5].brupdate.b2.uop.prs2 connect slots_5.io.brupdate.b2.uop.prs1, issue_slots[5].brupdate.b2.uop.prs1 connect slots_5.io.brupdate.b2.uop.pdst, issue_slots[5].brupdate.b2.uop.pdst connect slots_5.io.brupdate.b2.uop.rxq_idx, issue_slots[5].brupdate.b2.uop.rxq_idx connect slots_5.io.brupdate.b2.uop.stq_idx, issue_slots[5].brupdate.b2.uop.stq_idx connect slots_5.io.brupdate.b2.uop.ldq_idx, issue_slots[5].brupdate.b2.uop.ldq_idx connect slots_5.io.brupdate.b2.uop.rob_idx, issue_slots[5].brupdate.b2.uop.rob_idx connect slots_5.io.brupdate.b2.uop.csr_addr, issue_slots[5].brupdate.b2.uop.csr_addr connect slots_5.io.brupdate.b2.uop.imm_packed, issue_slots[5].brupdate.b2.uop.imm_packed connect slots_5.io.brupdate.b2.uop.taken, issue_slots[5].brupdate.b2.uop.taken connect slots_5.io.brupdate.b2.uop.pc_lob, issue_slots[5].brupdate.b2.uop.pc_lob connect slots_5.io.brupdate.b2.uop.edge_inst, issue_slots[5].brupdate.b2.uop.edge_inst connect slots_5.io.brupdate.b2.uop.ftq_idx, issue_slots[5].brupdate.b2.uop.ftq_idx connect slots_5.io.brupdate.b2.uop.br_tag, issue_slots[5].brupdate.b2.uop.br_tag connect slots_5.io.brupdate.b2.uop.br_mask, issue_slots[5].brupdate.b2.uop.br_mask connect slots_5.io.brupdate.b2.uop.is_sfb, issue_slots[5].brupdate.b2.uop.is_sfb connect slots_5.io.brupdate.b2.uop.is_jal, issue_slots[5].brupdate.b2.uop.is_jal connect slots_5.io.brupdate.b2.uop.is_jalr, issue_slots[5].brupdate.b2.uop.is_jalr connect slots_5.io.brupdate.b2.uop.is_br, issue_slots[5].brupdate.b2.uop.is_br connect slots_5.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[5].brupdate.b2.uop.iw_p2_poisoned connect slots_5.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[5].brupdate.b2.uop.iw_p1_poisoned connect slots_5.io.brupdate.b2.uop.iw_state, issue_slots[5].brupdate.b2.uop.iw_state connect slots_5.io.brupdate.b2.uop.ctrl.is_std, issue_slots[5].brupdate.b2.uop.ctrl.is_std connect slots_5.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[5].brupdate.b2.uop.ctrl.is_sta connect slots_5.io.brupdate.b2.uop.ctrl.is_load, issue_slots[5].brupdate.b2.uop.ctrl.is_load connect slots_5.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[5].brupdate.b2.uop.ctrl.csr_cmd connect slots_5.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[5].brupdate.b2.uop.ctrl.fcn_dw connect slots_5.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[5].brupdate.b2.uop.ctrl.op_fcn connect slots_5.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[5].brupdate.b2.uop.ctrl.imm_sel connect slots_5.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[5].brupdate.b2.uop.ctrl.op2_sel connect slots_5.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[5].brupdate.b2.uop.ctrl.op1_sel connect slots_5.io.brupdate.b2.uop.ctrl.br_type, issue_slots[5].brupdate.b2.uop.ctrl.br_type connect slots_5.io.brupdate.b2.uop.fu_code, issue_slots[5].brupdate.b2.uop.fu_code connect slots_5.io.brupdate.b2.uop.iq_type, issue_slots[5].brupdate.b2.uop.iq_type connect slots_5.io.brupdate.b2.uop.debug_pc, issue_slots[5].brupdate.b2.uop.debug_pc connect slots_5.io.brupdate.b2.uop.is_rvc, issue_slots[5].brupdate.b2.uop.is_rvc connect slots_5.io.brupdate.b2.uop.debug_inst, issue_slots[5].brupdate.b2.uop.debug_inst connect slots_5.io.brupdate.b2.uop.inst, issue_slots[5].brupdate.b2.uop.inst connect slots_5.io.brupdate.b2.uop.uopc, issue_slots[5].brupdate.b2.uop.uopc connect slots_5.io.brupdate.b1.mispredict_mask, issue_slots[5].brupdate.b1.mispredict_mask connect slots_5.io.brupdate.b1.resolve_mask, issue_slots[5].brupdate.b1.resolve_mask connect slots_5.io.grant, issue_slots[5].grant connect issue_slots[5].request_hp, slots_5.io.request_hp connect issue_slots[5].request, slots_5.io.request connect issue_slots[5].will_be_valid, slots_5.io.will_be_valid connect issue_slots[5].valid, slots_5.io.valid connect issue_slots[6].debug.state, slots_6.io.debug.state connect issue_slots[6].debug.ppred, slots_6.io.debug.ppred connect issue_slots[6].debug.p3, slots_6.io.debug.p3 connect issue_slots[6].debug.p2, slots_6.io.debug.p2 connect issue_slots[6].debug.p1, slots_6.io.debug.p1 connect issue_slots[6].uop.debug_tsrc, slots_6.io.uop.debug_tsrc connect issue_slots[6].uop.debug_fsrc, slots_6.io.uop.debug_fsrc connect issue_slots[6].uop.bp_xcpt_if, slots_6.io.uop.bp_xcpt_if connect issue_slots[6].uop.bp_debug_if, slots_6.io.uop.bp_debug_if connect issue_slots[6].uop.xcpt_ma_if, slots_6.io.uop.xcpt_ma_if connect issue_slots[6].uop.xcpt_ae_if, slots_6.io.uop.xcpt_ae_if connect issue_slots[6].uop.xcpt_pf_if, slots_6.io.uop.xcpt_pf_if connect issue_slots[6].uop.fp_single, slots_6.io.uop.fp_single connect issue_slots[6].uop.fp_val, slots_6.io.uop.fp_val connect issue_slots[6].uop.frs3_en, slots_6.io.uop.frs3_en connect issue_slots[6].uop.lrs2_rtype, slots_6.io.uop.lrs2_rtype connect issue_slots[6].uop.lrs1_rtype, slots_6.io.uop.lrs1_rtype connect issue_slots[6].uop.dst_rtype, slots_6.io.uop.dst_rtype connect issue_slots[6].uop.ldst_val, slots_6.io.uop.ldst_val connect issue_slots[6].uop.lrs3, slots_6.io.uop.lrs3 connect issue_slots[6].uop.lrs2, slots_6.io.uop.lrs2 connect issue_slots[6].uop.lrs1, slots_6.io.uop.lrs1 connect issue_slots[6].uop.ldst, slots_6.io.uop.ldst connect issue_slots[6].uop.ldst_is_rs1, slots_6.io.uop.ldst_is_rs1 connect issue_slots[6].uop.flush_on_commit, slots_6.io.uop.flush_on_commit connect issue_slots[6].uop.is_unique, slots_6.io.uop.is_unique connect issue_slots[6].uop.is_sys_pc2epc, slots_6.io.uop.is_sys_pc2epc connect issue_slots[6].uop.uses_stq, slots_6.io.uop.uses_stq connect issue_slots[6].uop.uses_ldq, slots_6.io.uop.uses_ldq connect issue_slots[6].uop.is_amo, slots_6.io.uop.is_amo connect issue_slots[6].uop.is_fencei, slots_6.io.uop.is_fencei connect issue_slots[6].uop.is_fence, slots_6.io.uop.is_fence connect issue_slots[6].uop.mem_signed, slots_6.io.uop.mem_signed connect issue_slots[6].uop.mem_size, slots_6.io.uop.mem_size connect issue_slots[6].uop.mem_cmd, slots_6.io.uop.mem_cmd connect issue_slots[6].uop.bypassable, slots_6.io.uop.bypassable connect issue_slots[6].uop.exc_cause, slots_6.io.uop.exc_cause connect issue_slots[6].uop.exception, slots_6.io.uop.exception connect issue_slots[6].uop.stale_pdst, slots_6.io.uop.stale_pdst connect issue_slots[6].uop.ppred_busy, slots_6.io.uop.ppred_busy connect issue_slots[6].uop.prs3_busy, slots_6.io.uop.prs3_busy connect issue_slots[6].uop.prs2_busy, slots_6.io.uop.prs2_busy connect issue_slots[6].uop.prs1_busy, slots_6.io.uop.prs1_busy connect issue_slots[6].uop.ppred, slots_6.io.uop.ppred connect issue_slots[6].uop.prs3, slots_6.io.uop.prs3 connect issue_slots[6].uop.prs2, slots_6.io.uop.prs2 connect issue_slots[6].uop.prs1, slots_6.io.uop.prs1 connect issue_slots[6].uop.pdst, slots_6.io.uop.pdst connect issue_slots[6].uop.rxq_idx, slots_6.io.uop.rxq_idx connect issue_slots[6].uop.stq_idx, slots_6.io.uop.stq_idx connect issue_slots[6].uop.ldq_idx, slots_6.io.uop.ldq_idx connect issue_slots[6].uop.rob_idx, slots_6.io.uop.rob_idx connect issue_slots[6].uop.csr_addr, slots_6.io.uop.csr_addr connect issue_slots[6].uop.imm_packed, slots_6.io.uop.imm_packed connect issue_slots[6].uop.taken, slots_6.io.uop.taken connect issue_slots[6].uop.pc_lob, slots_6.io.uop.pc_lob connect issue_slots[6].uop.edge_inst, slots_6.io.uop.edge_inst connect issue_slots[6].uop.ftq_idx, slots_6.io.uop.ftq_idx connect issue_slots[6].uop.br_tag, slots_6.io.uop.br_tag connect issue_slots[6].uop.br_mask, slots_6.io.uop.br_mask connect issue_slots[6].uop.is_sfb, slots_6.io.uop.is_sfb connect issue_slots[6].uop.is_jal, slots_6.io.uop.is_jal connect issue_slots[6].uop.is_jalr, slots_6.io.uop.is_jalr connect issue_slots[6].uop.is_br, slots_6.io.uop.is_br connect issue_slots[6].uop.iw_p2_poisoned, slots_6.io.uop.iw_p2_poisoned connect issue_slots[6].uop.iw_p1_poisoned, slots_6.io.uop.iw_p1_poisoned connect issue_slots[6].uop.iw_state, slots_6.io.uop.iw_state connect issue_slots[6].uop.ctrl.is_std, slots_6.io.uop.ctrl.is_std connect issue_slots[6].uop.ctrl.is_sta, slots_6.io.uop.ctrl.is_sta connect issue_slots[6].uop.ctrl.is_load, slots_6.io.uop.ctrl.is_load connect issue_slots[6].uop.ctrl.csr_cmd, slots_6.io.uop.ctrl.csr_cmd connect issue_slots[6].uop.ctrl.fcn_dw, slots_6.io.uop.ctrl.fcn_dw connect issue_slots[6].uop.ctrl.op_fcn, slots_6.io.uop.ctrl.op_fcn connect issue_slots[6].uop.ctrl.imm_sel, slots_6.io.uop.ctrl.imm_sel connect issue_slots[6].uop.ctrl.op2_sel, slots_6.io.uop.ctrl.op2_sel connect issue_slots[6].uop.ctrl.op1_sel, slots_6.io.uop.ctrl.op1_sel connect issue_slots[6].uop.ctrl.br_type, slots_6.io.uop.ctrl.br_type connect issue_slots[6].uop.fu_code, slots_6.io.uop.fu_code connect issue_slots[6].uop.iq_type, slots_6.io.uop.iq_type connect issue_slots[6].uop.debug_pc, slots_6.io.uop.debug_pc connect issue_slots[6].uop.is_rvc, slots_6.io.uop.is_rvc connect issue_slots[6].uop.debug_inst, slots_6.io.uop.debug_inst connect issue_slots[6].uop.inst, slots_6.io.uop.inst connect issue_slots[6].uop.uopc, slots_6.io.uop.uopc connect issue_slots[6].out_uop.debug_tsrc, slots_6.io.out_uop.debug_tsrc connect issue_slots[6].out_uop.debug_fsrc, slots_6.io.out_uop.debug_fsrc connect issue_slots[6].out_uop.bp_xcpt_if, slots_6.io.out_uop.bp_xcpt_if connect issue_slots[6].out_uop.bp_debug_if, slots_6.io.out_uop.bp_debug_if connect issue_slots[6].out_uop.xcpt_ma_if, slots_6.io.out_uop.xcpt_ma_if connect issue_slots[6].out_uop.xcpt_ae_if, slots_6.io.out_uop.xcpt_ae_if connect issue_slots[6].out_uop.xcpt_pf_if, slots_6.io.out_uop.xcpt_pf_if connect issue_slots[6].out_uop.fp_single, slots_6.io.out_uop.fp_single connect issue_slots[6].out_uop.fp_val, slots_6.io.out_uop.fp_val connect issue_slots[6].out_uop.frs3_en, slots_6.io.out_uop.frs3_en connect issue_slots[6].out_uop.lrs2_rtype, slots_6.io.out_uop.lrs2_rtype connect issue_slots[6].out_uop.lrs1_rtype, slots_6.io.out_uop.lrs1_rtype connect issue_slots[6].out_uop.dst_rtype, slots_6.io.out_uop.dst_rtype connect issue_slots[6].out_uop.ldst_val, slots_6.io.out_uop.ldst_val connect issue_slots[6].out_uop.lrs3, slots_6.io.out_uop.lrs3 connect issue_slots[6].out_uop.lrs2, slots_6.io.out_uop.lrs2 connect issue_slots[6].out_uop.lrs1, slots_6.io.out_uop.lrs1 connect issue_slots[6].out_uop.ldst, slots_6.io.out_uop.ldst connect issue_slots[6].out_uop.ldst_is_rs1, slots_6.io.out_uop.ldst_is_rs1 connect issue_slots[6].out_uop.flush_on_commit, slots_6.io.out_uop.flush_on_commit connect issue_slots[6].out_uop.is_unique, slots_6.io.out_uop.is_unique connect issue_slots[6].out_uop.is_sys_pc2epc, slots_6.io.out_uop.is_sys_pc2epc connect issue_slots[6].out_uop.uses_stq, slots_6.io.out_uop.uses_stq connect issue_slots[6].out_uop.uses_ldq, slots_6.io.out_uop.uses_ldq connect issue_slots[6].out_uop.is_amo, slots_6.io.out_uop.is_amo connect issue_slots[6].out_uop.is_fencei, slots_6.io.out_uop.is_fencei connect issue_slots[6].out_uop.is_fence, slots_6.io.out_uop.is_fence connect issue_slots[6].out_uop.mem_signed, slots_6.io.out_uop.mem_signed connect issue_slots[6].out_uop.mem_size, slots_6.io.out_uop.mem_size connect issue_slots[6].out_uop.mem_cmd, slots_6.io.out_uop.mem_cmd connect issue_slots[6].out_uop.bypassable, slots_6.io.out_uop.bypassable connect issue_slots[6].out_uop.exc_cause, slots_6.io.out_uop.exc_cause connect issue_slots[6].out_uop.exception, slots_6.io.out_uop.exception connect issue_slots[6].out_uop.stale_pdst, slots_6.io.out_uop.stale_pdst connect issue_slots[6].out_uop.ppred_busy, slots_6.io.out_uop.ppred_busy connect issue_slots[6].out_uop.prs3_busy, slots_6.io.out_uop.prs3_busy connect issue_slots[6].out_uop.prs2_busy, slots_6.io.out_uop.prs2_busy connect issue_slots[6].out_uop.prs1_busy, slots_6.io.out_uop.prs1_busy connect issue_slots[6].out_uop.ppred, slots_6.io.out_uop.ppred connect issue_slots[6].out_uop.prs3, slots_6.io.out_uop.prs3 connect issue_slots[6].out_uop.prs2, slots_6.io.out_uop.prs2 connect issue_slots[6].out_uop.prs1, slots_6.io.out_uop.prs1 connect issue_slots[6].out_uop.pdst, slots_6.io.out_uop.pdst connect issue_slots[6].out_uop.rxq_idx, slots_6.io.out_uop.rxq_idx connect issue_slots[6].out_uop.stq_idx, slots_6.io.out_uop.stq_idx connect issue_slots[6].out_uop.ldq_idx, slots_6.io.out_uop.ldq_idx connect issue_slots[6].out_uop.rob_idx, slots_6.io.out_uop.rob_idx connect issue_slots[6].out_uop.csr_addr, slots_6.io.out_uop.csr_addr connect issue_slots[6].out_uop.imm_packed, slots_6.io.out_uop.imm_packed connect issue_slots[6].out_uop.taken, slots_6.io.out_uop.taken connect issue_slots[6].out_uop.pc_lob, slots_6.io.out_uop.pc_lob connect issue_slots[6].out_uop.edge_inst, slots_6.io.out_uop.edge_inst connect issue_slots[6].out_uop.ftq_idx, slots_6.io.out_uop.ftq_idx connect issue_slots[6].out_uop.br_tag, slots_6.io.out_uop.br_tag connect issue_slots[6].out_uop.br_mask, slots_6.io.out_uop.br_mask connect issue_slots[6].out_uop.is_sfb, slots_6.io.out_uop.is_sfb connect issue_slots[6].out_uop.is_jal, slots_6.io.out_uop.is_jal connect issue_slots[6].out_uop.is_jalr, slots_6.io.out_uop.is_jalr connect issue_slots[6].out_uop.is_br, slots_6.io.out_uop.is_br connect issue_slots[6].out_uop.iw_p2_poisoned, slots_6.io.out_uop.iw_p2_poisoned connect issue_slots[6].out_uop.iw_p1_poisoned, slots_6.io.out_uop.iw_p1_poisoned connect issue_slots[6].out_uop.iw_state, slots_6.io.out_uop.iw_state connect issue_slots[6].out_uop.ctrl.is_std, slots_6.io.out_uop.ctrl.is_std connect issue_slots[6].out_uop.ctrl.is_sta, slots_6.io.out_uop.ctrl.is_sta connect issue_slots[6].out_uop.ctrl.is_load, slots_6.io.out_uop.ctrl.is_load connect issue_slots[6].out_uop.ctrl.csr_cmd, slots_6.io.out_uop.ctrl.csr_cmd connect issue_slots[6].out_uop.ctrl.fcn_dw, slots_6.io.out_uop.ctrl.fcn_dw connect issue_slots[6].out_uop.ctrl.op_fcn, slots_6.io.out_uop.ctrl.op_fcn connect issue_slots[6].out_uop.ctrl.imm_sel, slots_6.io.out_uop.ctrl.imm_sel connect issue_slots[6].out_uop.ctrl.op2_sel, slots_6.io.out_uop.ctrl.op2_sel connect issue_slots[6].out_uop.ctrl.op1_sel, slots_6.io.out_uop.ctrl.op1_sel connect issue_slots[6].out_uop.ctrl.br_type, slots_6.io.out_uop.ctrl.br_type connect issue_slots[6].out_uop.fu_code, slots_6.io.out_uop.fu_code connect issue_slots[6].out_uop.iq_type, slots_6.io.out_uop.iq_type connect issue_slots[6].out_uop.debug_pc, slots_6.io.out_uop.debug_pc connect issue_slots[6].out_uop.is_rvc, slots_6.io.out_uop.is_rvc connect issue_slots[6].out_uop.debug_inst, slots_6.io.out_uop.debug_inst connect issue_slots[6].out_uop.inst, slots_6.io.out_uop.inst connect issue_slots[6].out_uop.uopc, slots_6.io.out_uop.uopc connect slots_6.io.in_uop.bits.debug_tsrc, issue_slots[6].in_uop.bits.debug_tsrc connect slots_6.io.in_uop.bits.debug_fsrc, issue_slots[6].in_uop.bits.debug_fsrc connect slots_6.io.in_uop.bits.bp_xcpt_if, issue_slots[6].in_uop.bits.bp_xcpt_if connect slots_6.io.in_uop.bits.bp_debug_if, issue_slots[6].in_uop.bits.bp_debug_if connect slots_6.io.in_uop.bits.xcpt_ma_if, issue_slots[6].in_uop.bits.xcpt_ma_if connect slots_6.io.in_uop.bits.xcpt_ae_if, issue_slots[6].in_uop.bits.xcpt_ae_if connect slots_6.io.in_uop.bits.xcpt_pf_if, issue_slots[6].in_uop.bits.xcpt_pf_if connect slots_6.io.in_uop.bits.fp_single, issue_slots[6].in_uop.bits.fp_single connect slots_6.io.in_uop.bits.fp_val, issue_slots[6].in_uop.bits.fp_val connect slots_6.io.in_uop.bits.frs3_en, issue_slots[6].in_uop.bits.frs3_en connect slots_6.io.in_uop.bits.lrs2_rtype, issue_slots[6].in_uop.bits.lrs2_rtype connect slots_6.io.in_uop.bits.lrs1_rtype, issue_slots[6].in_uop.bits.lrs1_rtype connect slots_6.io.in_uop.bits.dst_rtype, issue_slots[6].in_uop.bits.dst_rtype connect slots_6.io.in_uop.bits.ldst_val, issue_slots[6].in_uop.bits.ldst_val connect slots_6.io.in_uop.bits.lrs3, issue_slots[6].in_uop.bits.lrs3 connect slots_6.io.in_uop.bits.lrs2, issue_slots[6].in_uop.bits.lrs2 connect slots_6.io.in_uop.bits.lrs1, issue_slots[6].in_uop.bits.lrs1 connect slots_6.io.in_uop.bits.ldst, issue_slots[6].in_uop.bits.ldst connect slots_6.io.in_uop.bits.ldst_is_rs1, issue_slots[6].in_uop.bits.ldst_is_rs1 connect slots_6.io.in_uop.bits.flush_on_commit, issue_slots[6].in_uop.bits.flush_on_commit connect slots_6.io.in_uop.bits.is_unique, issue_slots[6].in_uop.bits.is_unique connect slots_6.io.in_uop.bits.is_sys_pc2epc, issue_slots[6].in_uop.bits.is_sys_pc2epc connect slots_6.io.in_uop.bits.uses_stq, issue_slots[6].in_uop.bits.uses_stq connect slots_6.io.in_uop.bits.uses_ldq, issue_slots[6].in_uop.bits.uses_ldq connect slots_6.io.in_uop.bits.is_amo, issue_slots[6].in_uop.bits.is_amo connect slots_6.io.in_uop.bits.is_fencei, issue_slots[6].in_uop.bits.is_fencei connect slots_6.io.in_uop.bits.is_fence, issue_slots[6].in_uop.bits.is_fence connect slots_6.io.in_uop.bits.mem_signed, issue_slots[6].in_uop.bits.mem_signed connect slots_6.io.in_uop.bits.mem_size, issue_slots[6].in_uop.bits.mem_size connect slots_6.io.in_uop.bits.mem_cmd, issue_slots[6].in_uop.bits.mem_cmd connect slots_6.io.in_uop.bits.bypassable, issue_slots[6].in_uop.bits.bypassable connect slots_6.io.in_uop.bits.exc_cause, issue_slots[6].in_uop.bits.exc_cause connect slots_6.io.in_uop.bits.exception, issue_slots[6].in_uop.bits.exception connect slots_6.io.in_uop.bits.stale_pdst, issue_slots[6].in_uop.bits.stale_pdst connect slots_6.io.in_uop.bits.ppred_busy, issue_slots[6].in_uop.bits.ppred_busy connect slots_6.io.in_uop.bits.prs3_busy, issue_slots[6].in_uop.bits.prs3_busy connect slots_6.io.in_uop.bits.prs2_busy, issue_slots[6].in_uop.bits.prs2_busy connect slots_6.io.in_uop.bits.prs1_busy, issue_slots[6].in_uop.bits.prs1_busy connect slots_6.io.in_uop.bits.ppred, issue_slots[6].in_uop.bits.ppred connect slots_6.io.in_uop.bits.prs3, issue_slots[6].in_uop.bits.prs3 connect slots_6.io.in_uop.bits.prs2, issue_slots[6].in_uop.bits.prs2 connect slots_6.io.in_uop.bits.prs1, issue_slots[6].in_uop.bits.prs1 connect slots_6.io.in_uop.bits.pdst, issue_slots[6].in_uop.bits.pdst connect slots_6.io.in_uop.bits.rxq_idx, issue_slots[6].in_uop.bits.rxq_idx connect slots_6.io.in_uop.bits.stq_idx, issue_slots[6].in_uop.bits.stq_idx connect slots_6.io.in_uop.bits.ldq_idx, issue_slots[6].in_uop.bits.ldq_idx connect slots_6.io.in_uop.bits.rob_idx, issue_slots[6].in_uop.bits.rob_idx connect slots_6.io.in_uop.bits.csr_addr, issue_slots[6].in_uop.bits.csr_addr connect slots_6.io.in_uop.bits.imm_packed, issue_slots[6].in_uop.bits.imm_packed connect slots_6.io.in_uop.bits.taken, issue_slots[6].in_uop.bits.taken connect slots_6.io.in_uop.bits.pc_lob, issue_slots[6].in_uop.bits.pc_lob connect slots_6.io.in_uop.bits.edge_inst, issue_slots[6].in_uop.bits.edge_inst connect slots_6.io.in_uop.bits.ftq_idx, issue_slots[6].in_uop.bits.ftq_idx connect slots_6.io.in_uop.bits.br_tag, issue_slots[6].in_uop.bits.br_tag connect slots_6.io.in_uop.bits.br_mask, issue_slots[6].in_uop.bits.br_mask connect slots_6.io.in_uop.bits.is_sfb, issue_slots[6].in_uop.bits.is_sfb connect slots_6.io.in_uop.bits.is_jal, issue_slots[6].in_uop.bits.is_jal connect slots_6.io.in_uop.bits.is_jalr, issue_slots[6].in_uop.bits.is_jalr connect slots_6.io.in_uop.bits.is_br, issue_slots[6].in_uop.bits.is_br connect slots_6.io.in_uop.bits.iw_p2_poisoned, issue_slots[6].in_uop.bits.iw_p2_poisoned connect slots_6.io.in_uop.bits.iw_p1_poisoned, issue_slots[6].in_uop.bits.iw_p1_poisoned connect slots_6.io.in_uop.bits.iw_state, issue_slots[6].in_uop.bits.iw_state connect slots_6.io.in_uop.bits.ctrl.is_std, issue_slots[6].in_uop.bits.ctrl.is_std connect slots_6.io.in_uop.bits.ctrl.is_sta, issue_slots[6].in_uop.bits.ctrl.is_sta connect slots_6.io.in_uop.bits.ctrl.is_load, issue_slots[6].in_uop.bits.ctrl.is_load connect slots_6.io.in_uop.bits.ctrl.csr_cmd, issue_slots[6].in_uop.bits.ctrl.csr_cmd connect slots_6.io.in_uop.bits.ctrl.fcn_dw, issue_slots[6].in_uop.bits.ctrl.fcn_dw connect slots_6.io.in_uop.bits.ctrl.op_fcn, issue_slots[6].in_uop.bits.ctrl.op_fcn connect slots_6.io.in_uop.bits.ctrl.imm_sel, issue_slots[6].in_uop.bits.ctrl.imm_sel connect slots_6.io.in_uop.bits.ctrl.op2_sel, issue_slots[6].in_uop.bits.ctrl.op2_sel connect slots_6.io.in_uop.bits.ctrl.op1_sel, issue_slots[6].in_uop.bits.ctrl.op1_sel connect slots_6.io.in_uop.bits.ctrl.br_type, issue_slots[6].in_uop.bits.ctrl.br_type connect slots_6.io.in_uop.bits.fu_code, issue_slots[6].in_uop.bits.fu_code connect slots_6.io.in_uop.bits.iq_type, issue_slots[6].in_uop.bits.iq_type connect slots_6.io.in_uop.bits.debug_pc, issue_slots[6].in_uop.bits.debug_pc connect slots_6.io.in_uop.bits.is_rvc, issue_slots[6].in_uop.bits.is_rvc connect slots_6.io.in_uop.bits.debug_inst, issue_slots[6].in_uop.bits.debug_inst connect slots_6.io.in_uop.bits.inst, issue_slots[6].in_uop.bits.inst connect slots_6.io.in_uop.bits.uopc, issue_slots[6].in_uop.bits.uopc connect slots_6.io.in_uop.valid, issue_slots[6].in_uop.valid connect slots_6.io.spec_ld_wakeup[0].bits, issue_slots[6].spec_ld_wakeup[0].bits connect slots_6.io.spec_ld_wakeup[0].valid, issue_slots[6].spec_ld_wakeup[0].valid connect slots_6.io.pred_wakeup_port.bits, issue_slots[6].pred_wakeup_port.bits connect slots_6.io.pred_wakeup_port.valid, issue_slots[6].pred_wakeup_port.valid connect slots_6.io.wakeup_ports[0].bits.poisoned, issue_slots[6].wakeup_ports[0].bits.poisoned connect slots_6.io.wakeup_ports[0].bits.pdst, issue_slots[6].wakeup_ports[0].bits.pdst connect slots_6.io.wakeup_ports[0].valid, issue_slots[6].wakeup_ports[0].valid connect slots_6.io.wakeup_ports[1].bits.poisoned, issue_slots[6].wakeup_ports[1].bits.poisoned connect slots_6.io.wakeup_ports[1].bits.pdst, issue_slots[6].wakeup_ports[1].bits.pdst connect slots_6.io.wakeup_ports[1].valid, issue_slots[6].wakeup_ports[1].valid connect slots_6.io.ldspec_miss, issue_slots[6].ldspec_miss connect slots_6.io.clear, issue_slots[6].clear connect slots_6.io.kill, issue_slots[6].kill connect slots_6.io.brupdate.b2.target_offset, issue_slots[6].brupdate.b2.target_offset connect slots_6.io.brupdate.b2.jalr_target, issue_slots[6].brupdate.b2.jalr_target connect slots_6.io.brupdate.b2.pc_sel, issue_slots[6].brupdate.b2.pc_sel connect slots_6.io.brupdate.b2.cfi_type, issue_slots[6].brupdate.b2.cfi_type connect slots_6.io.brupdate.b2.taken, issue_slots[6].brupdate.b2.taken connect slots_6.io.brupdate.b2.mispredict, issue_slots[6].brupdate.b2.mispredict connect slots_6.io.brupdate.b2.valid, issue_slots[6].brupdate.b2.valid connect slots_6.io.brupdate.b2.uop.debug_tsrc, issue_slots[6].brupdate.b2.uop.debug_tsrc connect slots_6.io.brupdate.b2.uop.debug_fsrc, issue_slots[6].brupdate.b2.uop.debug_fsrc connect slots_6.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[6].brupdate.b2.uop.bp_xcpt_if connect slots_6.io.brupdate.b2.uop.bp_debug_if, issue_slots[6].brupdate.b2.uop.bp_debug_if connect slots_6.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[6].brupdate.b2.uop.xcpt_ma_if connect slots_6.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[6].brupdate.b2.uop.xcpt_ae_if connect slots_6.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[6].brupdate.b2.uop.xcpt_pf_if connect slots_6.io.brupdate.b2.uop.fp_single, issue_slots[6].brupdate.b2.uop.fp_single connect slots_6.io.brupdate.b2.uop.fp_val, issue_slots[6].brupdate.b2.uop.fp_val connect slots_6.io.brupdate.b2.uop.frs3_en, issue_slots[6].brupdate.b2.uop.frs3_en connect slots_6.io.brupdate.b2.uop.lrs2_rtype, issue_slots[6].brupdate.b2.uop.lrs2_rtype connect slots_6.io.brupdate.b2.uop.lrs1_rtype, issue_slots[6].brupdate.b2.uop.lrs1_rtype connect slots_6.io.brupdate.b2.uop.dst_rtype, issue_slots[6].brupdate.b2.uop.dst_rtype connect slots_6.io.brupdate.b2.uop.ldst_val, issue_slots[6].brupdate.b2.uop.ldst_val connect slots_6.io.brupdate.b2.uop.lrs3, issue_slots[6].brupdate.b2.uop.lrs3 connect slots_6.io.brupdate.b2.uop.lrs2, issue_slots[6].brupdate.b2.uop.lrs2 connect slots_6.io.brupdate.b2.uop.lrs1, issue_slots[6].brupdate.b2.uop.lrs1 connect slots_6.io.brupdate.b2.uop.ldst, issue_slots[6].brupdate.b2.uop.ldst connect slots_6.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[6].brupdate.b2.uop.ldst_is_rs1 connect slots_6.io.brupdate.b2.uop.flush_on_commit, issue_slots[6].brupdate.b2.uop.flush_on_commit connect slots_6.io.brupdate.b2.uop.is_unique, issue_slots[6].brupdate.b2.uop.is_unique connect slots_6.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[6].brupdate.b2.uop.is_sys_pc2epc connect slots_6.io.brupdate.b2.uop.uses_stq, issue_slots[6].brupdate.b2.uop.uses_stq connect slots_6.io.brupdate.b2.uop.uses_ldq, issue_slots[6].brupdate.b2.uop.uses_ldq connect slots_6.io.brupdate.b2.uop.is_amo, issue_slots[6].brupdate.b2.uop.is_amo connect slots_6.io.brupdate.b2.uop.is_fencei, issue_slots[6].brupdate.b2.uop.is_fencei connect slots_6.io.brupdate.b2.uop.is_fence, issue_slots[6].brupdate.b2.uop.is_fence connect slots_6.io.brupdate.b2.uop.mem_signed, issue_slots[6].brupdate.b2.uop.mem_signed connect slots_6.io.brupdate.b2.uop.mem_size, issue_slots[6].brupdate.b2.uop.mem_size connect slots_6.io.brupdate.b2.uop.mem_cmd, issue_slots[6].brupdate.b2.uop.mem_cmd connect slots_6.io.brupdate.b2.uop.bypassable, issue_slots[6].brupdate.b2.uop.bypassable connect slots_6.io.brupdate.b2.uop.exc_cause, issue_slots[6].brupdate.b2.uop.exc_cause connect slots_6.io.brupdate.b2.uop.exception, issue_slots[6].brupdate.b2.uop.exception connect slots_6.io.brupdate.b2.uop.stale_pdst, issue_slots[6].brupdate.b2.uop.stale_pdst connect slots_6.io.brupdate.b2.uop.ppred_busy, issue_slots[6].brupdate.b2.uop.ppred_busy connect slots_6.io.brupdate.b2.uop.prs3_busy, issue_slots[6].brupdate.b2.uop.prs3_busy connect slots_6.io.brupdate.b2.uop.prs2_busy, issue_slots[6].brupdate.b2.uop.prs2_busy connect slots_6.io.brupdate.b2.uop.prs1_busy, issue_slots[6].brupdate.b2.uop.prs1_busy connect slots_6.io.brupdate.b2.uop.ppred, issue_slots[6].brupdate.b2.uop.ppred connect slots_6.io.brupdate.b2.uop.prs3, issue_slots[6].brupdate.b2.uop.prs3 connect slots_6.io.brupdate.b2.uop.prs2, issue_slots[6].brupdate.b2.uop.prs2 connect slots_6.io.brupdate.b2.uop.prs1, issue_slots[6].brupdate.b2.uop.prs1 connect slots_6.io.brupdate.b2.uop.pdst, issue_slots[6].brupdate.b2.uop.pdst connect slots_6.io.brupdate.b2.uop.rxq_idx, issue_slots[6].brupdate.b2.uop.rxq_idx connect slots_6.io.brupdate.b2.uop.stq_idx, issue_slots[6].brupdate.b2.uop.stq_idx connect slots_6.io.brupdate.b2.uop.ldq_idx, issue_slots[6].brupdate.b2.uop.ldq_idx connect slots_6.io.brupdate.b2.uop.rob_idx, issue_slots[6].brupdate.b2.uop.rob_idx connect slots_6.io.brupdate.b2.uop.csr_addr, issue_slots[6].brupdate.b2.uop.csr_addr connect slots_6.io.brupdate.b2.uop.imm_packed, issue_slots[6].brupdate.b2.uop.imm_packed connect slots_6.io.brupdate.b2.uop.taken, issue_slots[6].brupdate.b2.uop.taken connect slots_6.io.brupdate.b2.uop.pc_lob, issue_slots[6].brupdate.b2.uop.pc_lob connect slots_6.io.brupdate.b2.uop.edge_inst, issue_slots[6].brupdate.b2.uop.edge_inst connect slots_6.io.brupdate.b2.uop.ftq_idx, issue_slots[6].brupdate.b2.uop.ftq_idx connect slots_6.io.brupdate.b2.uop.br_tag, issue_slots[6].brupdate.b2.uop.br_tag connect slots_6.io.brupdate.b2.uop.br_mask, issue_slots[6].brupdate.b2.uop.br_mask connect slots_6.io.brupdate.b2.uop.is_sfb, issue_slots[6].brupdate.b2.uop.is_sfb connect slots_6.io.brupdate.b2.uop.is_jal, issue_slots[6].brupdate.b2.uop.is_jal connect slots_6.io.brupdate.b2.uop.is_jalr, issue_slots[6].brupdate.b2.uop.is_jalr connect slots_6.io.brupdate.b2.uop.is_br, issue_slots[6].brupdate.b2.uop.is_br connect slots_6.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[6].brupdate.b2.uop.iw_p2_poisoned connect slots_6.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[6].brupdate.b2.uop.iw_p1_poisoned connect slots_6.io.brupdate.b2.uop.iw_state, issue_slots[6].brupdate.b2.uop.iw_state connect slots_6.io.brupdate.b2.uop.ctrl.is_std, issue_slots[6].brupdate.b2.uop.ctrl.is_std connect slots_6.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[6].brupdate.b2.uop.ctrl.is_sta connect slots_6.io.brupdate.b2.uop.ctrl.is_load, issue_slots[6].brupdate.b2.uop.ctrl.is_load connect slots_6.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[6].brupdate.b2.uop.ctrl.csr_cmd connect slots_6.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[6].brupdate.b2.uop.ctrl.fcn_dw connect slots_6.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[6].brupdate.b2.uop.ctrl.op_fcn connect slots_6.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[6].brupdate.b2.uop.ctrl.imm_sel connect slots_6.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[6].brupdate.b2.uop.ctrl.op2_sel connect slots_6.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[6].brupdate.b2.uop.ctrl.op1_sel connect slots_6.io.brupdate.b2.uop.ctrl.br_type, issue_slots[6].brupdate.b2.uop.ctrl.br_type connect slots_6.io.brupdate.b2.uop.fu_code, issue_slots[6].brupdate.b2.uop.fu_code connect slots_6.io.brupdate.b2.uop.iq_type, issue_slots[6].brupdate.b2.uop.iq_type connect slots_6.io.brupdate.b2.uop.debug_pc, issue_slots[6].brupdate.b2.uop.debug_pc connect slots_6.io.brupdate.b2.uop.is_rvc, issue_slots[6].brupdate.b2.uop.is_rvc connect slots_6.io.brupdate.b2.uop.debug_inst, issue_slots[6].brupdate.b2.uop.debug_inst connect slots_6.io.brupdate.b2.uop.inst, issue_slots[6].brupdate.b2.uop.inst connect slots_6.io.brupdate.b2.uop.uopc, issue_slots[6].brupdate.b2.uop.uopc connect slots_6.io.brupdate.b1.mispredict_mask, issue_slots[6].brupdate.b1.mispredict_mask connect slots_6.io.brupdate.b1.resolve_mask, issue_slots[6].brupdate.b1.resolve_mask connect slots_6.io.grant, issue_slots[6].grant connect issue_slots[6].request_hp, slots_6.io.request_hp connect issue_slots[6].request, slots_6.io.request connect issue_slots[6].will_be_valid, slots_6.io.will_be_valid connect issue_slots[6].valid, slots_6.io.valid connect issue_slots[7].debug.state, slots_7.io.debug.state connect issue_slots[7].debug.ppred, slots_7.io.debug.ppred connect issue_slots[7].debug.p3, slots_7.io.debug.p3 connect issue_slots[7].debug.p2, slots_7.io.debug.p2 connect issue_slots[7].debug.p1, slots_7.io.debug.p1 connect issue_slots[7].uop.debug_tsrc, slots_7.io.uop.debug_tsrc connect issue_slots[7].uop.debug_fsrc, slots_7.io.uop.debug_fsrc connect issue_slots[7].uop.bp_xcpt_if, slots_7.io.uop.bp_xcpt_if connect issue_slots[7].uop.bp_debug_if, slots_7.io.uop.bp_debug_if connect issue_slots[7].uop.xcpt_ma_if, slots_7.io.uop.xcpt_ma_if connect issue_slots[7].uop.xcpt_ae_if, slots_7.io.uop.xcpt_ae_if connect issue_slots[7].uop.xcpt_pf_if, slots_7.io.uop.xcpt_pf_if connect issue_slots[7].uop.fp_single, slots_7.io.uop.fp_single connect issue_slots[7].uop.fp_val, slots_7.io.uop.fp_val connect issue_slots[7].uop.frs3_en, slots_7.io.uop.frs3_en connect issue_slots[7].uop.lrs2_rtype, slots_7.io.uop.lrs2_rtype connect issue_slots[7].uop.lrs1_rtype, slots_7.io.uop.lrs1_rtype connect issue_slots[7].uop.dst_rtype, slots_7.io.uop.dst_rtype connect issue_slots[7].uop.ldst_val, slots_7.io.uop.ldst_val connect issue_slots[7].uop.lrs3, slots_7.io.uop.lrs3 connect issue_slots[7].uop.lrs2, slots_7.io.uop.lrs2 connect issue_slots[7].uop.lrs1, slots_7.io.uop.lrs1 connect issue_slots[7].uop.ldst, slots_7.io.uop.ldst connect issue_slots[7].uop.ldst_is_rs1, slots_7.io.uop.ldst_is_rs1 connect issue_slots[7].uop.flush_on_commit, slots_7.io.uop.flush_on_commit connect issue_slots[7].uop.is_unique, slots_7.io.uop.is_unique connect issue_slots[7].uop.is_sys_pc2epc, slots_7.io.uop.is_sys_pc2epc connect issue_slots[7].uop.uses_stq, slots_7.io.uop.uses_stq connect issue_slots[7].uop.uses_ldq, slots_7.io.uop.uses_ldq connect issue_slots[7].uop.is_amo, slots_7.io.uop.is_amo connect issue_slots[7].uop.is_fencei, slots_7.io.uop.is_fencei connect issue_slots[7].uop.is_fence, slots_7.io.uop.is_fence connect issue_slots[7].uop.mem_signed, slots_7.io.uop.mem_signed connect issue_slots[7].uop.mem_size, slots_7.io.uop.mem_size connect issue_slots[7].uop.mem_cmd, slots_7.io.uop.mem_cmd connect issue_slots[7].uop.bypassable, slots_7.io.uop.bypassable connect issue_slots[7].uop.exc_cause, slots_7.io.uop.exc_cause connect issue_slots[7].uop.exception, slots_7.io.uop.exception connect issue_slots[7].uop.stale_pdst, slots_7.io.uop.stale_pdst connect issue_slots[7].uop.ppred_busy, slots_7.io.uop.ppred_busy connect issue_slots[7].uop.prs3_busy, slots_7.io.uop.prs3_busy connect issue_slots[7].uop.prs2_busy, slots_7.io.uop.prs2_busy connect issue_slots[7].uop.prs1_busy, slots_7.io.uop.prs1_busy connect issue_slots[7].uop.ppred, slots_7.io.uop.ppred connect issue_slots[7].uop.prs3, slots_7.io.uop.prs3 connect issue_slots[7].uop.prs2, slots_7.io.uop.prs2 connect issue_slots[7].uop.prs1, slots_7.io.uop.prs1 connect issue_slots[7].uop.pdst, slots_7.io.uop.pdst connect issue_slots[7].uop.rxq_idx, slots_7.io.uop.rxq_idx connect issue_slots[7].uop.stq_idx, slots_7.io.uop.stq_idx connect issue_slots[7].uop.ldq_idx, slots_7.io.uop.ldq_idx connect issue_slots[7].uop.rob_idx, slots_7.io.uop.rob_idx connect issue_slots[7].uop.csr_addr, slots_7.io.uop.csr_addr connect issue_slots[7].uop.imm_packed, slots_7.io.uop.imm_packed connect issue_slots[7].uop.taken, slots_7.io.uop.taken connect issue_slots[7].uop.pc_lob, slots_7.io.uop.pc_lob connect issue_slots[7].uop.edge_inst, slots_7.io.uop.edge_inst connect issue_slots[7].uop.ftq_idx, slots_7.io.uop.ftq_idx connect issue_slots[7].uop.br_tag, slots_7.io.uop.br_tag connect issue_slots[7].uop.br_mask, slots_7.io.uop.br_mask connect issue_slots[7].uop.is_sfb, slots_7.io.uop.is_sfb connect issue_slots[7].uop.is_jal, slots_7.io.uop.is_jal connect issue_slots[7].uop.is_jalr, slots_7.io.uop.is_jalr connect issue_slots[7].uop.is_br, slots_7.io.uop.is_br connect issue_slots[7].uop.iw_p2_poisoned, slots_7.io.uop.iw_p2_poisoned connect issue_slots[7].uop.iw_p1_poisoned, slots_7.io.uop.iw_p1_poisoned connect issue_slots[7].uop.iw_state, slots_7.io.uop.iw_state connect issue_slots[7].uop.ctrl.is_std, slots_7.io.uop.ctrl.is_std connect issue_slots[7].uop.ctrl.is_sta, slots_7.io.uop.ctrl.is_sta connect issue_slots[7].uop.ctrl.is_load, slots_7.io.uop.ctrl.is_load connect issue_slots[7].uop.ctrl.csr_cmd, slots_7.io.uop.ctrl.csr_cmd connect issue_slots[7].uop.ctrl.fcn_dw, slots_7.io.uop.ctrl.fcn_dw connect issue_slots[7].uop.ctrl.op_fcn, slots_7.io.uop.ctrl.op_fcn connect issue_slots[7].uop.ctrl.imm_sel, slots_7.io.uop.ctrl.imm_sel connect issue_slots[7].uop.ctrl.op2_sel, slots_7.io.uop.ctrl.op2_sel connect issue_slots[7].uop.ctrl.op1_sel, slots_7.io.uop.ctrl.op1_sel connect issue_slots[7].uop.ctrl.br_type, slots_7.io.uop.ctrl.br_type connect issue_slots[7].uop.fu_code, slots_7.io.uop.fu_code connect issue_slots[7].uop.iq_type, slots_7.io.uop.iq_type connect issue_slots[7].uop.debug_pc, slots_7.io.uop.debug_pc connect issue_slots[7].uop.is_rvc, slots_7.io.uop.is_rvc connect issue_slots[7].uop.debug_inst, slots_7.io.uop.debug_inst connect issue_slots[7].uop.inst, slots_7.io.uop.inst connect issue_slots[7].uop.uopc, slots_7.io.uop.uopc connect issue_slots[7].out_uop.debug_tsrc, slots_7.io.out_uop.debug_tsrc connect issue_slots[7].out_uop.debug_fsrc, slots_7.io.out_uop.debug_fsrc connect issue_slots[7].out_uop.bp_xcpt_if, slots_7.io.out_uop.bp_xcpt_if connect issue_slots[7].out_uop.bp_debug_if, slots_7.io.out_uop.bp_debug_if connect issue_slots[7].out_uop.xcpt_ma_if, slots_7.io.out_uop.xcpt_ma_if connect issue_slots[7].out_uop.xcpt_ae_if, slots_7.io.out_uop.xcpt_ae_if connect issue_slots[7].out_uop.xcpt_pf_if, slots_7.io.out_uop.xcpt_pf_if connect issue_slots[7].out_uop.fp_single, slots_7.io.out_uop.fp_single connect issue_slots[7].out_uop.fp_val, slots_7.io.out_uop.fp_val connect issue_slots[7].out_uop.frs3_en, slots_7.io.out_uop.frs3_en connect issue_slots[7].out_uop.lrs2_rtype, slots_7.io.out_uop.lrs2_rtype connect issue_slots[7].out_uop.lrs1_rtype, slots_7.io.out_uop.lrs1_rtype connect issue_slots[7].out_uop.dst_rtype, slots_7.io.out_uop.dst_rtype connect issue_slots[7].out_uop.ldst_val, slots_7.io.out_uop.ldst_val connect issue_slots[7].out_uop.lrs3, slots_7.io.out_uop.lrs3 connect issue_slots[7].out_uop.lrs2, slots_7.io.out_uop.lrs2 connect issue_slots[7].out_uop.lrs1, slots_7.io.out_uop.lrs1 connect issue_slots[7].out_uop.ldst, slots_7.io.out_uop.ldst connect issue_slots[7].out_uop.ldst_is_rs1, slots_7.io.out_uop.ldst_is_rs1 connect issue_slots[7].out_uop.flush_on_commit, slots_7.io.out_uop.flush_on_commit connect issue_slots[7].out_uop.is_unique, slots_7.io.out_uop.is_unique connect issue_slots[7].out_uop.is_sys_pc2epc, slots_7.io.out_uop.is_sys_pc2epc connect issue_slots[7].out_uop.uses_stq, slots_7.io.out_uop.uses_stq connect issue_slots[7].out_uop.uses_ldq, slots_7.io.out_uop.uses_ldq connect issue_slots[7].out_uop.is_amo, slots_7.io.out_uop.is_amo connect issue_slots[7].out_uop.is_fencei, slots_7.io.out_uop.is_fencei connect issue_slots[7].out_uop.is_fence, slots_7.io.out_uop.is_fence connect issue_slots[7].out_uop.mem_signed, slots_7.io.out_uop.mem_signed connect issue_slots[7].out_uop.mem_size, slots_7.io.out_uop.mem_size connect issue_slots[7].out_uop.mem_cmd, slots_7.io.out_uop.mem_cmd connect issue_slots[7].out_uop.bypassable, slots_7.io.out_uop.bypassable connect issue_slots[7].out_uop.exc_cause, slots_7.io.out_uop.exc_cause connect issue_slots[7].out_uop.exception, slots_7.io.out_uop.exception connect issue_slots[7].out_uop.stale_pdst, slots_7.io.out_uop.stale_pdst connect issue_slots[7].out_uop.ppred_busy, slots_7.io.out_uop.ppred_busy connect issue_slots[7].out_uop.prs3_busy, slots_7.io.out_uop.prs3_busy connect issue_slots[7].out_uop.prs2_busy, slots_7.io.out_uop.prs2_busy connect issue_slots[7].out_uop.prs1_busy, slots_7.io.out_uop.prs1_busy connect issue_slots[7].out_uop.ppred, slots_7.io.out_uop.ppred connect issue_slots[7].out_uop.prs3, slots_7.io.out_uop.prs3 connect issue_slots[7].out_uop.prs2, slots_7.io.out_uop.prs2 connect issue_slots[7].out_uop.prs1, slots_7.io.out_uop.prs1 connect issue_slots[7].out_uop.pdst, slots_7.io.out_uop.pdst connect issue_slots[7].out_uop.rxq_idx, slots_7.io.out_uop.rxq_idx connect issue_slots[7].out_uop.stq_idx, slots_7.io.out_uop.stq_idx connect issue_slots[7].out_uop.ldq_idx, slots_7.io.out_uop.ldq_idx connect issue_slots[7].out_uop.rob_idx, slots_7.io.out_uop.rob_idx connect issue_slots[7].out_uop.csr_addr, slots_7.io.out_uop.csr_addr connect issue_slots[7].out_uop.imm_packed, slots_7.io.out_uop.imm_packed connect issue_slots[7].out_uop.taken, slots_7.io.out_uop.taken connect issue_slots[7].out_uop.pc_lob, slots_7.io.out_uop.pc_lob connect issue_slots[7].out_uop.edge_inst, slots_7.io.out_uop.edge_inst connect issue_slots[7].out_uop.ftq_idx, slots_7.io.out_uop.ftq_idx connect issue_slots[7].out_uop.br_tag, slots_7.io.out_uop.br_tag connect issue_slots[7].out_uop.br_mask, slots_7.io.out_uop.br_mask connect issue_slots[7].out_uop.is_sfb, slots_7.io.out_uop.is_sfb connect issue_slots[7].out_uop.is_jal, slots_7.io.out_uop.is_jal connect issue_slots[7].out_uop.is_jalr, slots_7.io.out_uop.is_jalr connect issue_slots[7].out_uop.is_br, slots_7.io.out_uop.is_br connect issue_slots[7].out_uop.iw_p2_poisoned, slots_7.io.out_uop.iw_p2_poisoned connect issue_slots[7].out_uop.iw_p1_poisoned, slots_7.io.out_uop.iw_p1_poisoned connect issue_slots[7].out_uop.iw_state, slots_7.io.out_uop.iw_state connect issue_slots[7].out_uop.ctrl.is_std, slots_7.io.out_uop.ctrl.is_std connect issue_slots[7].out_uop.ctrl.is_sta, slots_7.io.out_uop.ctrl.is_sta connect issue_slots[7].out_uop.ctrl.is_load, slots_7.io.out_uop.ctrl.is_load connect issue_slots[7].out_uop.ctrl.csr_cmd, slots_7.io.out_uop.ctrl.csr_cmd connect issue_slots[7].out_uop.ctrl.fcn_dw, slots_7.io.out_uop.ctrl.fcn_dw connect issue_slots[7].out_uop.ctrl.op_fcn, slots_7.io.out_uop.ctrl.op_fcn connect issue_slots[7].out_uop.ctrl.imm_sel, slots_7.io.out_uop.ctrl.imm_sel connect issue_slots[7].out_uop.ctrl.op2_sel, slots_7.io.out_uop.ctrl.op2_sel connect issue_slots[7].out_uop.ctrl.op1_sel, slots_7.io.out_uop.ctrl.op1_sel connect issue_slots[7].out_uop.ctrl.br_type, slots_7.io.out_uop.ctrl.br_type connect issue_slots[7].out_uop.fu_code, slots_7.io.out_uop.fu_code connect issue_slots[7].out_uop.iq_type, slots_7.io.out_uop.iq_type connect issue_slots[7].out_uop.debug_pc, slots_7.io.out_uop.debug_pc connect issue_slots[7].out_uop.is_rvc, slots_7.io.out_uop.is_rvc connect issue_slots[7].out_uop.debug_inst, slots_7.io.out_uop.debug_inst connect issue_slots[7].out_uop.inst, slots_7.io.out_uop.inst connect issue_slots[7].out_uop.uopc, slots_7.io.out_uop.uopc connect slots_7.io.in_uop.bits.debug_tsrc, issue_slots[7].in_uop.bits.debug_tsrc connect slots_7.io.in_uop.bits.debug_fsrc, issue_slots[7].in_uop.bits.debug_fsrc connect slots_7.io.in_uop.bits.bp_xcpt_if, issue_slots[7].in_uop.bits.bp_xcpt_if connect slots_7.io.in_uop.bits.bp_debug_if, issue_slots[7].in_uop.bits.bp_debug_if connect slots_7.io.in_uop.bits.xcpt_ma_if, issue_slots[7].in_uop.bits.xcpt_ma_if connect slots_7.io.in_uop.bits.xcpt_ae_if, issue_slots[7].in_uop.bits.xcpt_ae_if connect slots_7.io.in_uop.bits.xcpt_pf_if, issue_slots[7].in_uop.bits.xcpt_pf_if connect slots_7.io.in_uop.bits.fp_single, issue_slots[7].in_uop.bits.fp_single connect slots_7.io.in_uop.bits.fp_val, issue_slots[7].in_uop.bits.fp_val connect slots_7.io.in_uop.bits.frs3_en, issue_slots[7].in_uop.bits.frs3_en connect slots_7.io.in_uop.bits.lrs2_rtype, issue_slots[7].in_uop.bits.lrs2_rtype connect slots_7.io.in_uop.bits.lrs1_rtype, issue_slots[7].in_uop.bits.lrs1_rtype connect slots_7.io.in_uop.bits.dst_rtype, issue_slots[7].in_uop.bits.dst_rtype connect slots_7.io.in_uop.bits.ldst_val, issue_slots[7].in_uop.bits.ldst_val connect slots_7.io.in_uop.bits.lrs3, issue_slots[7].in_uop.bits.lrs3 connect slots_7.io.in_uop.bits.lrs2, issue_slots[7].in_uop.bits.lrs2 connect slots_7.io.in_uop.bits.lrs1, issue_slots[7].in_uop.bits.lrs1 connect slots_7.io.in_uop.bits.ldst, issue_slots[7].in_uop.bits.ldst connect slots_7.io.in_uop.bits.ldst_is_rs1, issue_slots[7].in_uop.bits.ldst_is_rs1 connect slots_7.io.in_uop.bits.flush_on_commit, issue_slots[7].in_uop.bits.flush_on_commit connect slots_7.io.in_uop.bits.is_unique, issue_slots[7].in_uop.bits.is_unique connect slots_7.io.in_uop.bits.is_sys_pc2epc, issue_slots[7].in_uop.bits.is_sys_pc2epc connect slots_7.io.in_uop.bits.uses_stq, issue_slots[7].in_uop.bits.uses_stq connect slots_7.io.in_uop.bits.uses_ldq, issue_slots[7].in_uop.bits.uses_ldq connect slots_7.io.in_uop.bits.is_amo, issue_slots[7].in_uop.bits.is_amo connect slots_7.io.in_uop.bits.is_fencei, issue_slots[7].in_uop.bits.is_fencei connect slots_7.io.in_uop.bits.is_fence, issue_slots[7].in_uop.bits.is_fence connect slots_7.io.in_uop.bits.mem_signed, issue_slots[7].in_uop.bits.mem_signed connect slots_7.io.in_uop.bits.mem_size, issue_slots[7].in_uop.bits.mem_size connect slots_7.io.in_uop.bits.mem_cmd, issue_slots[7].in_uop.bits.mem_cmd connect slots_7.io.in_uop.bits.bypassable, issue_slots[7].in_uop.bits.bypassable connect slots_7.io.in_uop.bits.exc_cause, issue_slots[7].in_uop.bits.exc_cause connect slots_7.io.in_uop.bits.exception, issue_slots[7].in_uop.bits.exception connect slots_7.io.in_uop.bits.stale_pdst, issue_slots[7].in_uop.bits.stale_pdst connect slots_7.io.in_uop.bits.ppred_busy, issue_slots[7].in_uop.bits.ppred_busy connect slots_7.io.in_uop.bits.prs3_busy, issue_slots[7].in_uop.bits.prs3_busy connect slots_7.io.in_uop.bits.prs2_busy, issue_slots[7].in_uop.bits.prs2_busy connect slots_7.io.in_uop.bits.prs1_busy, issue_slots[7].in_uop.bits.prs1_busy connect slots_7.io.in_uop.bits.ppred, issue_slots[7].in_uop.bits.ppred connect slots_7.io.in_uop.bits.prs3, issue_slots[7].in_uop.bits.prs3 connect slots_7.io.in_uop.bits.prs2, issue_slots[7].in_uop.bits.prs2 connect slots_7.io.in_uop.bits.prs1, issue_slots[7].in_uop.bits.prs1 connect slots_7.io.in_uop.bits.pdst, issue_slots[7].in_uop.bits.pdst connect slots_7.io.in_uop.bits.rxq_idx, issue_slots[7].in_uop.bits.rxq_idx connect slots_7.io.in_uop.bits.stq_idx, issue_slots[7].in_uop.bits.stq_idx connect slots_7.io.in_uop.bits.ldq_idx, issue_slots[7].in_uop.bits.ldq_idx connect slots_7.io.in_uop.bits.rob_idx, issue_slots[7].in_uop.bits.rob_idx connect slots_7.io.in_uop.bits.csr_addr, issue_slots[7].in_uop.bits.csr_addr connect slots_7.io.in_uop.bits.imm_packed, issue_slots[7].in_uop.bits.imm_packed connect slots_7.io.in_uop.bits.taken, issue_slots[7].in_uop.bits.taken connect slots_7.io.in_uop.bits.pc_lob, issue_slots[7].in_uop.bits.pc_lob connect slots_7.io.in_uop.bits.edge_inst, issue_slots[7].in_uop.bits.edge_inst connect slots_7.io.in_uop.bits.ftq_idx, issue_slots[7].in_uop.bits.ftq_idx connect slots_7.io.in_uop.bits.br_tag, issue_slots[7].in_uop.bits.br_tag connect slots_7.io.in_uop.bits.br_mask, issue_slots[7].in_uop.bits.br_mask connect slots_7.io.in_uop.bits.is_sfb, issue_slots[7].in_uop.bits.is_sfb connect slots_7.io.in_uop.bits.is_jal, issue_slots[7].in_uop.bits.is_jal connect slots_7.io.in_uop.bits.is_jalr, issue_slots[7].in_uop.bits.is_jalr connect slots_7.io.in_uop.bits.is_br, issue_slots[7].in_uop.bits.is_br connect slots_7.io.in_uop.bits.iw_p2_poisoned, issue_slots[7].in_uop.bits.iw_p2_poisoned connect slots_7.io.in_uop.bits.iw_p1_poisoned, issue_slots[7].in_uop.bits.iw_p1_poisoned connect slots_7.io.in_uop.bits.iw_state, issue_slots[7].in_uop.bits.iw_state connect slots_7.io.in_uop.bits.ctrl.is_std, issue_slots[7].in_uop.bits.ctrl.is_std connect slots_7.io.in_uop.bits.ctrl.is_sta, issue_slots[7].in_uop.bits.ctrl.is_sta connect slots_7.io.in_uop.bits.ctrl.is_load, issue_slots[7].in_uop.bits.ctrl.is_load connect slots_7.io.in_uop.bits.ctrl.csr_cmd, issue_slots[7].in_uop.bits.ctrl.csr_cmd connect slots_7.io.in_uop.bits.ctrl.fcn_dw, issue_slots[7].in_uop.bits.ctrl.fcn_dw connect slots_7.io.in_uop.bits.ctrl.op_fcn, issue_slots[7].in_uop.bits.ctrl.op_fcn connect slots_7.io.in_uop.bits.ctrl.imm_sel, issue_slots[7].in_uop.bits.ctrl.imm_sel connect slots_7.io.in_uop.bits.ctrl.op2_sel, issue_slots[7].in_uop.bits.ctrl.op2_sel connect slots_7.io.in_uop.bits.ctrl.op1_sel, issue_slots[7].in_uop.bits.ctrl.op1_sel connect slots_7.io.in_uop.bits.ctrl.br_type, issue_slots[7].in_uop.bits.ctrl.br_type connect slots_7.io.in_uop.bits.fu_code, issue_slots[7].in_uop.bits.fu_code connect slots_7.io.in_uop.bits.iq_type, issue_slots[7].in_uop.bits.iq_type connect slots_7.io.in_uop.bits.debug_pc, issue_slots[7].in_uop.bits.debug_pc connect slots_7.io.in_uop.bits.is_rvc, issue_slots[7].in_uop.bits.is_rvc connect slots_7.io.in_uop.bits.debug_inst, issue_slots[7].in_uop.bits.debug_inst connect slots_7.io.in_uop.bits.inst, issue_slots[7].in_uop.bits.inst connect slots_7.io.in_uop.bits.uopc, issue_slots[7].in_uop.bits.uopc connect slots_7.io.in_uop.valid, issue_slots[7].in_uop.valid connect slots_7.io.spec_ld_wakeup[0].bits, issue_slots[7].spec_ld_wakeup[0].bits connect slots_7.io.spec_ld_wakeup[0].valid, issue_slots[7].spec_ld_wakeup[0].valid connect slots_7.io.pred_wakeup_port.bits, issue_slots[7].pred_wakeup_port.bits connect slots_7.io.pred_wakeup_port.valid, issue_slots[7].pred_wakeup_port.valid connect slots_7.io.wakeup_ports[0].bits.poisoned, issue_slots[7].wakeup_ports[0].bits.poisoned connect slots_7.io.wakeup_ports[0].bits.pdst, issue_slots[7].wakeup_ports[0].bits.pdst connect slots_7.io.wakeup_ports[0].valid, issue_slots[7].wakeup_ports[0].valid connect slots_7.io.wakeup_ports[1].bits.poisoned, issue_slots[7].wakeup_ports[1].bits.poisoned connect slots_7.io.wakeup_ports[1].bits.pdst, issue_slots[7].wakeup_ports[1].bits.pdst connect slots_7.io.wakeup_ports[1].valid, issue_slots[7].wakeup_ports[1].valid connect slots_7.io.ldspec_miss, issue_slots[7].ldspec_miss connect slots_7.io.clear, issue_slots[7].clear connect slots_7.io.kill, issue_slots[7].kill connect slots_7.io.brupdate.b2.target_offset, issue_slots[7].brupdate.b2.target_offset connect slots_7.io.brupdate.b2.jalr_target, issue_slots[7].brupdate.b2.jalr_target connect slots_7.io.brupdate.b2.pc_sel, issue_slots[7].brupdate.b2.pc_sel connect slots_7.io.brupdate.b2.cfi_type, issue_slots[7].brupdate.b2.cfi_type connect slots_7.io.brupdate.b2.taken, issue_slots[7].brupdate.b2.taken connect slots_7.io.brupdate.b2.mispredict, issue_slots[7].brupdate.b2.mispredict connect slots_7.io.brupdate.b2.valid, issue_slots[7].brupdate.b2.valid connect slots_7.io.brupdate.b2.uop.debug_tsrc, issue_slots[7].brupdate.b2.uop.debug_tsrc connect slots_7.io.brupdate.b2.uop.debug_fsrc, issue_slots[7].brupdate.b2.uop.debug_fsrc connect slots_7.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[7].brupdate.b2.uop.bp_xcpt_if connect slots_7.io.brupdate.b2.uop.bp_debug_if, issue_slots[7].brupdate.b2.uop.bp_debug_if connect slots_7.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[7].brupdate.b2.uop.xcpt_ma_if connect slots_7.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[7].brupdate.b2.uop.xcpt_ae_if connect slots_7.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[7].brupdate.b2.uop.xcpt_pf_if connect slots_7.io.brupdate.b2.uop.fp_single, issue_slots[7].brupdate.b2.uop.fp_single connect slots_7.io.brupdate.b2.uop.fp_val, issue_slots[7].brupdate.b2.uop.fp_val connect slots_7.io.brupdate.b2.uop.frs3_en, issue_slots[7].brupdate.b2.uop.frs3_en connect slots_7.io.brupdate.b2.uop.lrs2_rtype, issue_slots[7].brupdate.b2.uop.lrs2_rtype connect slots_7.io.brupdate.b2.uop.lrs1_rtype, issue_slots[7].brupdate.b2.uop.lrs1_rtype connect slots_7.io.brupdate.b2.uop.dst_rtype, issue_slots[7].brupdate.b2.uop.dst_rtype connect slots_7.io.brupdate.b2.uop.ldst_val, issue_slots[7].brupdate.b2.uop.ldst_val connect slots_7.io.brupdate.b2.uop.lrs3, issue_slots[7].brupdate.b2.uop.lrs3 connect slots_7.io.brupdate.b2.uop.lrs2, issue_slots[7].brupdate.b2.uop.lrs2 connect slots_7.io.brupdate.b2.uop.lrs1, issue_slots[7].brupdate.b2.uop.lrs1 connect slots_7.io.brupdate.b2.uop.ldst, issue_slots[7].brupdate.b2.uop.ldst connect slots_7.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[7].brupdate.b2.uop.ldst_is_rs1 connect slots_7.io.brupdate.b2.uop.flush_on_commit, issue_slots[7].brupdate.b2.uop.flush_on_commit connect slots_7.io.brupdate.b2.uop.is_unique, issue_slots[7].brupdate.b2.uop.is_unique connect slots_7.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[7].brupdate.b2.uop.is_sys_pc2epc connect slots_7.io.brupdate.b2.uop.uses_stq, issue_slots[7].brupdate.b2.uop.uses_stq connect slots_7.io.brupdate.b2.uop.uses_ldq, issue_slots[7].brupdate.b2.uop.uses_ldq connect slots_7.io.brupdate.b2.uop.is_amo, issue_slots[7].brupdate.b2.uop.is_amo connect slots_7.io.brupdate.b2.uop.is_fencei, issue_slots[7].brupdate.b2.uop.is_fencei connect slots_7.io.brupdate.b2.uop.is_fence, issue_slots[7].brupdate.b2.uop.is_fence connect slots_7.io.brupdate.b2.uop.mem_signed, issue_slots[7].brupdate.b2.uop.mem_signed connect slots_7.io.brupdate.b2.uop.mem_size, issue_slots[7].brupdate.b2.uop.mem_size connect slots_7.io.brupdate.b2.uop.mem_cmd, issue_slots[7].brupdate.b2.uop.mem_cmd connect slots_7.io.brupdate.b2.uop.bypassable, issue_slots[7].brupdate.b2.uop.bypassable connect slots_7.io.brupdate.b2.uop.exc_cause, issue_slots[7].brupdate.b2.uop.exc_cause connect slots_7.io.brupdate.b2.uop.exception, issue_slots[7].brupdate.b2.uop.exception connect slots_7.io.brupdate.b2.uop.stale_pdst, issue_slots[7].brupdate.b2.uop.stale_pdst connect slots_7.io.brupdate.b2.uop.ppred_busy, issue_slots[7].brupdate.b2.uop.ppred_busy connect slots_7.io.brupdate.b2.uop.prs3_busy, issue_slots[7].brupdate.b2.uop.prs3_busy connect slots_7.io.brupdate.b2.uop.prs2_busy, issue_slots[7].brupdate.b2.uop.prs2_busy connect slots_7.io.brupdate.b2.uop.prs1_busy, issue_slots[7].brupdate.b2.uop.prs1_busy connect slots_7.io.brupdate.b2.uop.ppred, issue_slots[7].brupdate.b2.uop.ppred connect slots_7.io.brupdate.b2.uop.prs3, issue_slots[7].brupdate.b2.uop.prs3 connect slots_7.io.brupdate.b2.uop.prs2, issue_slots[7].brupdate.b2.uop.prs2 connect slots_7.io.brupdate.b2.uop.prs1, issue_slots[7].brupdate.b2.uop.prs1 connect slots_7.io.brupdate.b2.uop.pdst, issue_slots[7].brupdate.b2.uop.pdst connect slots_7.io.brupdate.b2.uop.rxq_idx, issue_slots[7].brupdate.b2.uop.rxq_idx connect slots_7.io.brupdate.b2.uop.stq_idx, issue_slots[7].brupdate.b2.uop.stq_idx connect slots_7.io.brupdate.b2.uop.ldq_idx, issue_slots[7].brupdate.b2.uop.ldq_idx connect slots_7.io.brupdate.b2.uop.rob_idx, issue_slots[7].brupdate.b2.uop.rob_idx connect slots_7.io.brupdate.b2.uop.csr_addr, issue_slots[7].brupdate.b2.uop.csr_addr connect slots_7.io.brupdate.b2.uop.imm_packed, issue_slots[7].brupdate.b2.uop.imm_packed connect slots_7.io.brupdate.b2.uop.taken, issue_slots[7].brupdate.b2.uop.taken connect slots_7.io.brupdate.b2.uop.pc_lob, issue_slots[7].brupdate.b2.uop.pc_lob connect slots_7.io.brupdate.b2.uop.edge_inst, issue_slots[7].brupdate.b2.uop.edge_inst connect slots_7.io.brupdate.b2.uop.ftq_idx, issue_slots[7].brupdate.b2.uop.ftq_idx connect slots_7.io.brupdate.b2.uop.br_tag, issue_slots[7].brupdate.b2.uop.br_tag connect slots_7.io.brupdate.b2.uop.br_mask, issue_slots[7].brupdate.b2.uop.br_mask connect slots_7.io.brupdate.b2.uop.is_sfb, issue_slots[7].brupdate.b2.uop.is_sfb connect slots_7.io.brupdate.b2.uop.is_jal, issue_slots[7].brupdate.b2.uop.is_jal connect slots_7.io.brupdate.b2.uop.is_jalr, issue_slots[7].brupdate.b2.uop.is_jalr connect slots_7.io.brupdate.b2.uop.is_br, issue_slots[7].brupdate.b2.uop.is_br connect slots_7.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[7].brupdate.b2.uop.iw_p2_poisoned connect slots_7.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[7].brupdate.b2.uop.iw_p1_poisoned connect slots_7.io.brupdate.b2.uop.iw_state, issue_slots[7].brupdate.b2.uop.iw_state connect slots_7.io.brupdate.b2.uop.ctrl.is_std, issue_slots[7].brupdate.b2.uop.ctrl.is_std connect slots_7.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[7].brupdate.b2.uop.ctrl.is_sta connect slots_7.io.brupdate.b2.uop.ctrl.is_load, issue_slots[7].brupdate.b2.uop.ctrl.is_load connect slots_7.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[7].brupdate.b2.uop.ctrl.csr_cmd connect slots_7.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[7].brupdate.b2.uop.ctrl.fcn_dw connect slots_7.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[7].brupdate.b2.uop.ctrl.op_fcn connect slots_7.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[7].brupdate.b2.uop.ctrl.imm_sel connect slots_7.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[7].brupdate.b2.uop.ctrl.op2_sel connect slots_7.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[7].brupdate.b2.uop.ctrl.op1_sel connect slots_7.io.brupdate.b2.uop.ctrl.br_type, issue_slots[7].brupdate.b2.uop.ctrl.br_type connect slots_7.io.brupdate.b2.uop.fu_code, issue_slots[7].brupdate.b2.uop.fu_code connect slots_7.io.brupdate.b2.uop.iq_type, issue_slots[7].brupdate.b2.uop.iq_type connect slots_7.io.brupdate.b2.uop.debug_pc, issue_slots[7].brupdate.b2.uop.debug_pc connect slots_7.io.brupdate.b2.uop.is_rvc, issue_slots[7].brupdate.b2.uop.is_rvc connect slots_7.io.brupdate.b2.uop.debug_inst, issue_slots[7].brupdate.b2.uop.debug_inst connect slots_7.io.brupdate.b2.uop.inst, issue_slots[7].brupdate.b2.uop.inst connect slots_7.io.brupdate.b2.uop.uopc, issue_slots[7].brupdate.b2.uop.uopc connect slots_7.io.brupdate.b1.mispredict_mask, issue_slots[7].brupdate.b1.mispredict_mask connect slots_7.io.brupdate.b1.resolve_mask, issue_slots[7].brupdate.b1.resolve_mask connect slots_7.io.grant, issue_slots[7].grant connect issue_slots[7].request_hp, slots_7.io.request_hp connect issue_slots[7].request, slots_7.io.request connect issue_slots[7].will_be_valid, slots_7.io.will_be_valid connect issue_slots[7].valid, slots_7.io.valid connect issue_slots[0].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[0].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[0].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[0].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[0].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[0].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[0].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[0].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[0].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[0].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[0].ldspec_miss, io.ld_miss connect issue_slots[0].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[0].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[0].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[0].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[0].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[0].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[0].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[0].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[0].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[0].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[0].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[0].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[0].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[0].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[0].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[0].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[0].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[0].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[0].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[0].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[0].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[0].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[0].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[0].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[0].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[0].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[0].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[0].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[0].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[0].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[0].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[0].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[0].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[0].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[0].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[0].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[0].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[0].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[0].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[0].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[0].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[0].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[0].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[0].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[0].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[0].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[0].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[0].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[0].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[0].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[0].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[0].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[0].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[0].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[0].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[0].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[0].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[0].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[0].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[0].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[0].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[0].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[0].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[0].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[0].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[0].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[0].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[0].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[0].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[0].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[0].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[0].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[0].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[0].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[0].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[0].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[0].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[0].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[0].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[0].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[0].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[0].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[0].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[0].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[0].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[0].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[0].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[0].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[0].kill, io.flush_pipeline connect issue_slots[1].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[1].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[1].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[1].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[1].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[1].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[1].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[1].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[1].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[1].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[1].ldspec_miss, io.ld_miss connect issue_slots[1].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[1].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[1].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[1].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[1].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[1].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[1].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[1].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[1].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[1].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[1].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[1].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[1].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[1].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[1].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[1].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[1].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[1].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[1].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[1].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[1].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[1].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[1].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[1].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[1].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[1].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[1].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[1].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[1].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[1].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[1].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[1].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[1].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[1].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[1].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[1].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[1].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[1].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[1].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[1].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[1].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[1].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[1].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[1].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[1].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[1].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[1].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[1].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[1].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[1].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[1].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[1].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[1].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[1].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[1].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[1].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[1].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[1].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[1].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[1].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[1].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[1].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[1].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[1].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[1].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[1].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[1].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[1].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[1].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[1].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[1].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[1].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[1].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[1].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[1].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[1].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[1].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[1].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[1].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[1].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[1].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[1].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[1].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[1].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[1].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[1].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[1].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[1].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[1].kill, io.flush_pipeline connect issue_slots[2].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[2].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[2].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[2].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[2].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[2].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[2].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[2].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[2].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[2].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[2].ldspec_miss, io.ld_miss connect issue_slots[2].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[2].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[2].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[2].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[2].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[2].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[2].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[2].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[2].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[2].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[2].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[2].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[2].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[2].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[2].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[2].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[2].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[2].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[2].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[2].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[2].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[2].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[2].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[2].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[2].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[2].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[2].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[2].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[2].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[2].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[2].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[2].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[2].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[2].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[2].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[2].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[2].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[2].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[2].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[2].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[2].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[2].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[2].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[2].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[2].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[2].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[2].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[2].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[2].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[2].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[2].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[2].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[2].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[2].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[2].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[2].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[2].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[2].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[2].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[2].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[2].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[2].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[2].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[2].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[2].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[2].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[2].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[2].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[2].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[2].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[2].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[2].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[2].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[2].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[2].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[2].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[2].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[2].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[2].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[2].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[2].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[2].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[2].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[2].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[2].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[2].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[2].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[2].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[2].kill, io.flush_pipeline connect issue_slots[3].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[3].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[3].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[3].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[3].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[3].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[3].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[3].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[3].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[3].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[3].ldspec_miss, io.ld_miss connect issue_slots[3].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[3].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[3].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[3].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[3].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[3].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[3].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[3].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[3].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[3].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[3].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[3].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[3].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[3].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[3].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[3].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[3].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[3].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[3].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[3].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[3].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[3].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[3].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[3].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[3].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[3].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[3].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[3].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[3].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[3].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[3].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[3].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[3].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[3].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[3].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[3].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[3].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[3].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[3].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[3].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[3].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[3].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[3].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[3].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[3].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[3].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[3].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[3].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[3].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[3].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[3].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[3].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[3].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[3].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[3].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[3].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[3].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[3].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[3].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[3].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[3].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[3].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[3].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[3].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[3].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[3].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[3].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[3].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[3].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[3].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[3].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[3].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[3].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[3].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[3].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[3].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[3].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[3].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[3].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[3].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[3].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[3].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[3].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[3].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[3].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[3].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[3].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[3].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[3].kill, io.flush_pipeline connect issue_slots[4].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[4].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[4].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[4].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[4].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[4].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[4].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[4].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[4].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[4].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[4].ldspec_miss, io.ld_miss connect issue_slots[4].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[4].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[4].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[4].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[4].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[4].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[4].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[4].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[4].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[4].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[4].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[4].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[4].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[4].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[4].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[4].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[4].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[4].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[4].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[4].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[4].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[4].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[4].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[4].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[4].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[4].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[4].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[4].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[4].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[4].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[4].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[4].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[4].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[4].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[4].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[4].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[4].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[4].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[4].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[4].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[4].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[4].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[4].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[4].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[4].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[4].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[4].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[4].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[4].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[4].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[4].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[4].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[4].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[4].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[4].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[4].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[4].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[4].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[4].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[4].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[4].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[4].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[4].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[4].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[4].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[4].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[4].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[4].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[4].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[4].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[4].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[4].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[4].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[4].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[4].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[4].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[4].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[4].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[4].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[4].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[4].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[4].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[4].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[4].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[4].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[4].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[4].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[4].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[4].kill, io.flush_pipeline connect issue_slots[5].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[5].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[5].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[5].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[5].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[5].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[5].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[5].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[5].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[5].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[5].ldspec_miss, io.ld_miss connect issue_slots[5].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[5].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[5].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[5].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[5].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[5].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[5].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[5].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[5].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[5].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[5].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[5].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[5].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[5].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[5].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[5].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[5].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[5].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[5].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[5].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[5].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[5].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[5].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[5].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[5].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[5].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[5].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[5].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[5].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[5].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[5].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[5].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[5].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[5].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[5].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[5].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[5].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[5].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[5].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[5].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[5].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[5].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[5].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[5].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[5].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[5].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[5].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[5].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[5].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[5].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[5].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[5].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[5].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[5].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[5].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[5].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[5].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[5].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[5].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[5].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[5].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[5].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[5].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[5].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[5].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[5].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[5].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[5].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[5].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[5].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[5].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[5].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[5].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[5].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[5].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[5].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[5].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[5].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[5].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[5].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[5].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[5].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[5].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[5].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[5].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[5].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[5].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[5].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[5].kill, io.flush_pipeline connect issue_slots[6].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[6].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[6].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[6].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[6].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[6].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[6].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[6].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[6].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[6].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[6].ldspec_miss, io.ld_miss connect issue_slots[6].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[6].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[6].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[6].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[6].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[6].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[6].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[6].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[6].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[6].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[6].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[6].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[6].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[6].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[6].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[6].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[6].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[6].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[6].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[6].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[6].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[6].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[6].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[6].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[6].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[6].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[6].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[6].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[6].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[6].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[6].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[6].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[6].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[6].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[6].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[6].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[6].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[6].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[6].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[6].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[6].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[6].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[6].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[6].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[6].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[6].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[6].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[6].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[6].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[6].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[6].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[6].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[6].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[6].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[6].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[6].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[6].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[6].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[6].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[6].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[6].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[6].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[6].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[6].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[6].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[6].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[6].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[6].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[6].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[6].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[6].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[6].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[6].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[6].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[6].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[6].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[6].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[6].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[6].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[6].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[6].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[6].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[6].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[6].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[6].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[6].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[6].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[6].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[6].kill, io.flush_pipeline connect issue_slots[7].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[7].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[7].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[7].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[7].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[7].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[7].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[7].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[7].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[7].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[7].ldspec_miss, io.ld_miss connect issue_slots[7].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[7].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[7].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[7].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[7].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[7].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[7].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[7].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[7].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[7].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[7].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[7].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[7].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[7].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[7].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[7].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[7].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[7].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[7].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[7].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[7].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[7].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[7].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[7].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[7].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[7].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[7].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[7].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[7].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[7].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[7].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[7].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[7].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[7].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[7].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[7].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[7].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[7].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[7].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[7].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[7].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[7].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[7].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[7].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[7].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[7].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[7].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[7].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[7].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[7].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[7].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[7].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[7].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[7].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[7].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[7].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[7].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[7].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[7].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[7].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[7].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[7].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[7].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[7].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[7].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[7].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[7].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[7].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[7].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[7].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[7].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[7].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[7].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[7].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[7].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[7].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[7].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[7].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[7].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[7].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[7].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[7].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[7].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[7].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[7].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[7].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[7].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[7].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[7].kill, io.flush_pipeline node _io_event_empty_T = or(issue_slots[0].valid, issue_slots[1].valid) node _io_event_empty_T_1 = or(_io_event_empty_T, issue_slots[2].valid) node _io_event_empty_T_2 = or(_io_event_empty_T_1, issue_slots[3].valid) node _io_event_empty_T_3 = or(_io_event_empty_T_2, issue_slots[4].valid) node _io_event_empty_T_4 = or(_io_event_empty_T_3, issue_slots[5].valid) node _io_event_empty_T_5 = or(_io_event_empty_T_4, issue_slots[6].valid) node _io_event_empty_T_6 = or(_io_event_empty_T_5, issue_slots[7].valid) node _io_event_empty_T_7 = eq(_io_event_empty_T_6, UInt<1>(0h0)) connect io.event_empty, _io_event_empty_T_7 node _count_T = add(slots_0.io.valid, slots_1.io.valid) node _count_T_1 = bits(_count_T, 1, 0) node _count_T_2 = add(slots_2.io.valid, slots_3.io.valid) node _count_T_3 = bits(_count_T_2, 1, 0) node _count_T_4 = add(_count_T_1, _count_T_3) node _count_T_5 = bits(_count_T_4, 2, 0) node _count_T_6 = add(slots_4.io.valid, slots_5.io.valid) node _count_T_7 = bits(_count_T_6, 1, 0) node _count_T_8 = add(slots_6.io.valid, slots_7.io.valid) node _count_T_9 = bits(_count_T_8, 1, 0) node _count_T_10 = add(_count_T_7, _count_T_9) node _count_T_11 = bits(_count_T_10, 2, 0) node _count_T_12 = add(_count_T_5, _count_T_11) node count = bits(_count_T_12, 3, 0) node _T_6 = add(issue_slots[0].grant, issue_slots[1].grant) node _T_7 = bits(_T_6, 1, 0) node _T_8 = add(issue_slots[2].grant, issue_slots[3].grant) node _T_9 = bits(_T_8, 1, 0) node _T_10 = add(_T_7, _T_9) node _T_11 = bits(_T_10, 2, 0) node _T_12 = add(issue_slots[4].grant, issue_slots[5].grant) node _T_13 = bits(_T_12, 1, 0) node _T_14 = add(issue_slots[6].grant, issue_slots[7].grant) node _T_15 = bits(_T_14, 1, 0) node _T_16 = add(_T_13, _T_15) node _T_17 = bits(_T_16, 2, 0) node _T_18 = add(_T_11, _T_17) node _T_19 = bits(_T_18, 3, 0) node _T_20 = leq(_T_19, UInt<1>(0h1)) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed: [issue] window giving out too many grants.\n at issue-unit.scala:172 assert (PopCount(issue_slots.map(s => s.grant)) <= issueWidth.U, \"[issue] window giving out too many grants.\")\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 node vacants_0 = eq(issue_slots[0].valid, UInt<1>(0h0)) node vacants_1 = eq(issue_slots[1].valid, UInt<1>(0h0)) node vacants_2 = eq(issue_slots[2].valid, UInt<1>(0h0)) node vacants_3 = eq(issue_slots[3].valid, UInt<1>(0h0)) node vacants_4 = eq(issue_slots[4].valid, UInt<1>(0h0)) node vacants_5 = eq(issue_slots[5].valid, UInt<1>(0h0)) node vacants_6 = eq(issue_slots[6].valid, UInt<1>(0h0)) node vacants_7 = eq(issue_slots[7].valid, UInt<1>(0h0)) node vacants_8 = eq(io.dis_uops[0].valid, UInt<1>(0h0)) wire _WIRE_1 : UInt<1> wire _WIRE_2 : UInt<1> wire _WIRE_3 : UInt<1> wire _WIRE_4 : UInt<1> wire _WIRE_5 : UInt<1> wire _WIRE_6 : UInt<1> wire _WIRE_7 : UInt<1> wire _WIRE_8 : UInt<1> wire _WIRE_9 : UInt<1> connect _WIRE_1, UInt<1>(0h0) wire next : UInt<1> connect next, _WIRE_1 node _T_24 = eq(_WIRE_1, UInt<1>(0h0)) node _T_25 = and(_T_24, vacants_0) when _T_25 : connect next, UInt<1>(0h1) else : node _T_26 = bits(_WIRE_1, 0, 0) node _T_27 = eq(_T_26, UInt<1>(0h0)) node _T_28 = and(_T_27, vacants_0) when _T_28 : node _next_T = dshl(_WIRE_1, UInt<1>(0h1)) connect next, _next_T connect _WIRE_2, next wire next_1 : UInt<1> connect next_1, _WIRE_2 node _T_29 = eq(_WIRE_2, UInt<1>(0h0)) node _T_30 = and(_T_29, vacants_1) when _T_30 : connect next_1, UInt<1>(0h1) else : node _T_31 = bits(_WIRE_2, 0, 0) node _T_32 = eq(_T_31, UInt<1>(0h0)) node _T_33 = and(_T_32, vacants_1) when _T_33 : node _next_T_1 = dshl(_WIRE_2, UInt<1>(0h1)) connect next_1, _next_T_1 connect _WIRE_3, next_1 wire next_2 : UInt<1> connect next_2, _WIRE_3 node _T_34 = eq(_WIRE_3, UInt<1>(0h0)) node _T_35 = and(_T_34, vacants_2) when _T_35 : connect next_2, UInt<1>(0h1) else : node _T_36 = bits(_WIRE_3, 0, 0) node _T_37 = eq(_T_36, UInt<1>(0h0)) node _T_38 = and(_T_37, vacants_2) when _T_38 : node _next_T_2 = dshl(_WIRE_3, UInt<1>(0h1)) connect next_2, _next_T_2 connect _WIRE_4, next_2 wire next_3 : UInt<1> connect next_3, _WIRE_4 node _T_39 = eq(_WIRE_4, UInt<1>(0h0)) node _T_40 = and(_T_39, vacants_3) when _T_40 : connect next_3, UInt<1>(0h1) else : node _T_41 = bits(_WIRE_4, 0, 0) node _T_42 = eq(_T_41, UInt<1>(0h0)) node _T_43 = and(_T_42, vacants_3) when _T_43 : node _next_T_3 = dshl(_WIRE_4, UInt<1>(0h1)) connect next_3, _next_T_3 connect _WIRE_5, next_3 wire next_4 : UInt<1> connect next_4, _WIRE_5 node _T_44 = eq(_WIRE_5, UInt<1>(0h0)) node _T_45 = and(_T_44, vacants_4) when _T_45 : connect next_4, UInt<1>(0h1) else : node _T_46 = bits(_WIRE_5, 0, 0) node _T_47 = eq(_T_46, UInt<1>(0h0)) node _T_48 = and(_T_47, vacants_4) when _T_48 : node _next_T_4 = dshl(_WIRE_5, UInt<1>(0h1)) connect next_4, _next_T_4 connect _WIRE_6, next_4 wire next_5 : UInt<1> connect next_5, _WIRE_6 node _T_49 = eq(_WIRE_6, UInt<1>(0h0)) node _T_50 = and(_T_49, vacants_5) when _T_50 : connect next_5, UInt<1>(0h1) else : node _T_51 = bits(_WIRE_6, 0, 0) node _T_52 = eq(_T_51, UInt<1>(0h0)) node _T_53 = and(_T_52, vacants_5) when _T_53 : node _next_T_5 = dshl(_WIRE_6, UInt<1>(0h1)) connect next_5, _next_T_5 connect _WIRE_7, next_5 wire next_6 : UInt<1> connect next_6, _WIRE_7 node _T_54 = eq(_WIRE_7, UInt<1>(0h0)) node _T_55 = and(_T_54, vacants_6) when _T_55 : connect next_6, UInt<1>(0h1) else : node _T_56 = bits(_WIRE_7, 0, 0) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = and(_T_57, vacants_6) when _T_58 : node _next_T_6 = dshl(_WIRE_7, UInt<1>(0h1)) connect next_6, _next_T_6 connect _WIRE_8, next_6 wire next_7 : UInt<1> connect next_7, _WIRE_8 node _T_59 = eq(_WIRE_8, UInt<1>(0h0)) node _T_60 = and(_T_59, vacants_7) when _T_60 : connect next_7, UInt<1>(0h1) else : node _T_61 = bits(_WIRE_8, 0, 0) node _T_62 = eq(_T_61, UInt<1>(0h0)) node _T_63 = and(_T_62, vacants_7) when _T_63 : node _next_T_7 = dshl(_WIRE_8, UInt<1>(0h1)) connect next_7, _next_T_7 connect _WIRE_9, next_7 node _will_be_valid_T = eq(_WIRE.exception, UInt<1>(0h0)) node _will_be_valid_T_1 = and(io.dis_uops[0].valid, _will_be_valid_T) node _will_be_valid_T_2 = eq(_WIRE.is_fence, UInt<1>(0h0)) node _will_be_valid_T_3 = and(_will_be_valid_T_1, _will_be_valid_T_2) node _will_be_valid_T_4 = eq(_WIRE.is_fencei, UInt<1>(0h0)) node will_be_valid_8 = and(_will_be_valid_T_3, _will_be_valid_T_4) connect issue_slots[0].in_uop.valid, UInt<1>(0h0) connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_single, issue_slots[1].out_uop.fp_single connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.ldst_val, issue_slots[1].out_uop.ldst_val connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.bypassable, issue_slots[1].out_uop.bypassable connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx connect issue_slots[0].in_uop.bits.csr_addr, issue_slots[1].out_uop.csr_addr connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb connect issue_slots[0].in_uop.bits.is_jal, issue_slots[1].out_uop.is_jal connect issue_slots[0].in_uop.bits.is_jalr, issue_slots[1].out_uop.is_jalr connect issue_slots[0].in_uop.bits.is_br, issue_slots[1].out_uop.is_br connect issue_slots[0].in_uop.bits.iw_p2_poisoned, issue_slots[1].out_uop.iw_p2_poisoned connect issue_slots[0].in_uop.bits.iw_p1_poisoned, issue_slots[1].out_uop.iw_p1_poisoned connect issue_slots[0].in_uop.bits.iw_state, issue_slots[1].out_uop.iw_state connect issue_slots[0].in_uop.bits.ctrl.is_std, issue_slots[1].out_uop.ctrl.is_std connect issue_slots[0].in_uop.bits.ctrl.is_sta, issue_slots[1].out_uop.ctrl.is_sta connect issue_slots[0].in_uop.bits.ctrl.is_load, issue_slots[1].out_uop.ctrl.is_load connect issue_slots[0].in_uop.bits.ctrl.csr_cmd, issue_slots[1].out_uop.ctrl.csr_cmd connect issue_slots[0].in_uop.bits.ctrl.fcn_dw, issue_slots[1].out_uop.ctrl.fcn_dw connect issue_slots[0].in_uop.bits.ctrl.op_fcn, issue_slots[1].out_uop.ctrl.op_fcn connect issue_slots[0].in_uop.bits.ctrl.imm_sel, issue_slots[1].out_uop.ctrl.imm_sel connect issue_slots[0].in_uop.bits.ctrl.op2_sel, issue_slots[1].out_uop.ctrl.op2_sel connect issue_slots[0].in_uop.bits.ctrl.op1_sel, issue_slots[1].out_uop.ctrl.op1_sel connect issue_slots[0].in_uop.bits.ctrl.br_type, issue_slots[1].out_uop.ctrl.br_type connect issue_slots[0].in_uop.bits.fu_code, issue_slots[1].out_uop.fu_code connect issue_slots[0].in_uop.bits.iq_type, issue_slots[1].out_uop.iq_type connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst connect issue_slots[0].in_uop.bits.uopc, issue_slots[1].out_uop.uopc node _T_64 = eq(_WIRE_2, UInt<1>(0h1)) when _T_64 : connect issue_slots[0].in_uop.valid, issue_slots[1].will_be_valid connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_single, issue_slots[1].out_uop.fp_single connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.ldst_val, issue_slots[1].out_uop.ldst_val connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.bypassable, issue_slots[1].out_uop.bypassable connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx connect issue_slots[0].in_uop.bits.csr_addr, issue_slots[1].out_uop.csr_addr connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb connect issue_slots[0].in_uop.bits.is_jal, issue_slots[1].out_uop.is_jal connect issue_slots[0].in_uop.bits.is_jalr, issue_slots[1].out_uop.is_jalr connect issue_slots[0].in_uop.bits.is_br, issue_slots[1].out_uop.is_br connect issue_slots[0].in_uop.bits.iw_p2_poisoned, issue_slots[1].out_uop.iw_p2_poisoned connect issue_slots[0].in_uop.bits.iw_p1_poisoned, issue_slots[1].out_uop.iw_p1_poisoned connect issue_slots[0].in_uop.bits.iw_state, issue_slots[1].out_uop.iw_state connect issue_slots[0].in_uop.bits.ctrl.is_std, issue_slots[1].out_uop.ctrl.is_std connect issue_slots[0].in_uop.bits.ctrl.is_sta, issue_slots[1].out_uop.ctrl.is_sta connect issue_slots[0].in_uop.bits.ctrl.is_load, issue_slots[1].out_uop.ctrl.is_load connect issue_slots[0].in_uop.bits.ctrl.csr_cmd, issue_slots[1].out_uop.ctrl.csr_cmd connect issue_slots[0].in_uop.bits.ctrl.fcn_dw, issue_slots[1].out_uop.ctrl.fcn_dw connect issue_slots[0].in_uop.bits.ctrl.op_fcn, issue_slots[1].out_uop.ctrl.op_fcn connect issue_slots[0].in_uop.bits.ctrl.imm_sel, issue_slots[1].out_uop.ctrl.imm_sel connect issue_slots[0].in_uop.bits.ctrl.op2_sel, issue_slots[1].out_uop.ctrl.op2_sel connect issue_slots[0].in_uop.bits.ctrl.op1_sel, issue_slots[1].out_uop.ctrl.op1_sel connect issue_slots[0].in_uop.bits.ctrl.br_type, issue_slots[1].out_uop.ctrl.br_type connect issue_slots[0].in_uop.bits.fu_code, issue_slots[1].out_uop.fu_code connect issue_slots[0].in_uop.bits.iq_type, issue_slots[1].out_uop.iq_type connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst connect issue_slots[0].in_uop.bits.uopc, issue_slots[1].out_uop.uopc node _issue_slots_0_clear_T = neq(_WIRE_1, UInt<1>(0h0)) connect issue_slots[0].clear, _issue_slots_0_clear_T connect issue_slots[1].in_uop.valid, UInt<1>(0h0) connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_single, issue_slots[2].out_uop.fp_single connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.ldst_val, issue_slots[2].out_uop.ldst_val connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.bypassable, issue_slots[2].out_uop.bypassable connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx connect issue_slots[1].in_uop.bits.csr_addr, issue_slots[2].out_uop.csr_addr connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb connect issue_slots[1].in_uop.bits.is_jal, issue_slots[2].out_uop.is_jal connect issue_slots[1].in_uop.bits.is_jalr, issue_slots[2].out_uop.is_jalr connect issue_slots[1].in_uop.bits.is_br, issue_slots[2].out_uop.is_br connect issue_slots[1].in_uop.bits.iw_p2_poisoned, issue_slots[2].out_uop.iw_p2_poisoned connect issue_slots[1].in_uop.bits.iw_p1_poisoned, issue_slots[2].out_uop.iw_p1_poisoned connect issue_slots[1].in_uop.bits.iw_state, issue_slots[2].out_uop.iw_state connect issue_slots[1].in_uop.bits.ctrl.is_std, issue_slots[2].out_uop.ctrl.is_std connect issue_slots[1].in_uop.bits.ctrl.is_sta, issue_slots[2].out_uop.ctrl.is_sta connect issue_slots[1].in_uop.bits.ctrl.is_load, issue_slots[2].out_uop.ctrl.is_load connect issue_slots[1].in_uop.bits.ctrl.csr_cmd, issue_slots[2].out_uop.ctrl.csr_cmd connect issue_slots[1].in_uop.bits.ctrl.fcn_dw, issue_slots[2].out_uop.ctrl.fcn_dw connect issue_slots[1].in_uop.bits.ctrl.op_fcn, issue_slots[2].out_uop.ctrl.op_fcn connect issue_slots[1].in_uop.bits.ctrl.imm_sel, issue_slots[2].out_uop.ctrl.imm_sel connect issue_slots[1].in_uop.bits.ctrl.op2_sel, issue_slots[2].out_uop.ctrl.op2_sel connect issue_slots[1].in_uop.bits.ctrl.op1_sel, issue_slots[2].out_uop.ctrl.op1_sel connect issue_slots[1].in_uop.bits.ctrl.br_type, issue_slots[2].out_uop.ctrl.br_type connect issue_slots[1].in_uop.bits.fu_code, issue_slots[2].out_uop.fu_code connect issue_slots[1].in_uop.bits.iq_type, issue_slots[2].out_uop.iq_type connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst connect issue_slots[1].in_uop.bits.uopc, issue_slots[2].out_uop.uopc node _T_65 = eq(_WIRE_3, UInt<1>(0h1)) when _T_65 : connect issue_slots[1].in_uop.valid, issue_slots[2].will_be_valid connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_single, issue_slots[2].out_uop.fp_single connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.ldst_val, issue_slots[2].out_uop.ldst_val connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.bypassable, issue_slots[2].out_uop.bypassable connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx connect issue_slots[1].in_uop.bits.csr_addr, issue_slots[2].out_uop.csr_addr connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb connect issue_slots[1].in_uop.bits.is_jal, issue_slots[2].out_uop.is_jal connect issue_slots[1].in_uop.bits.is_jalr, issue_slots[2].out_uop.is_jalr connect issue_slots[1].in_uop.bits.is_br, issue_slots[2].out_uop.is_br connect issue_slots[1].in_uop.bits.iw_p2_poisoned, issue_slots[2].out_uop.iw_p2_poisoned connect issue_slots[1].in_uop.bits.iw_p1_poisoned, issue_slots[2].out_uop.iw_p1_poisoned connect issue_slots[1].in_uop.bits.iw_state, issue_slots[2].out_uop.iw_state connect issue_slots[1].in_uop.bits.ctrl.is_std, issue_slots[2].out_uop.ctrl.is_std connect issue_slots[1].in_uop.bits.ctrl.is_sta, issue_slots[2].out_uop.ctrl.is_sta connect issue_slots[1].in_uop.bits.ctrl.is_load, issue_slots[2].out_uop.ctrl.is_load connect issue_slots[1].in_uop.bits.ctrl.csr_cmd, issue_slots[2].out_uop.ctrl.csr_cmd connect issue_slots[1].in_uop.bits.ctrl.fcn_dw, issue_slots[2].out_uop.ctrl.fcn_dw connect issue_slots[1].in_uop.bits.ctrl.op_fcn, issue_slots[2].out_uop.ctrl.op_fcn connect issue_slots[1].in_uop.bits.ctrl.imm_sel, issue_slots[2].out_uop.ctrl.imm_sel connect issue_slots[1].in_uop.bits.ctrl.op2_sel, issue_slots[2].out_uop.ctrl.op2_sel connect issue_slots[1].in_uop.bits.ctrl.op1_sel, issue_slots[2].out_uop.ctrl.op1_sel connect issue_slots[1].in_uop.bits.ctrl.br_type, issue_slots[2].out_uop.ctrl.br_type connect issue_slots[1].in_uop.bits.fu_code, issue_slots[2].out_uop.fu_code connect issue_slots[1].in_uop.bits.iq_type, issue_slots[2].out_uop.iq_type connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst connect issue_slots[1].in_uop.bits.uopc, issue_slots[2].out_uop.uopc node _issue_slots_1_clear_T = neq(_WIRE_2, UInt<1>(0h0)) connect issue_slots[1].clear, _issue_slots_1_clear_T connect issue_slots[2].in_uop.valid, UInt<1>(0h0) connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_single, issue_slots[3].out_uop.fp_single connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.ldst_val, issue_slots[3].out_uop.ldst_val connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.bypassable, issue_slots[3].out_uop.bypassable connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[2].in_uop.bits.csr_addr, issue_slots[3].out_uop.csr_addr connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[2].in_uop.bits.is_jal, issue_slots[3].out_uop.is_jal connect issue_slots[2].in_uop.bits.is_jalr, issue_slots[3].out_uop.is_jalr connect issue_slots[2].in_uop.bits.is_br, issue_slots[3].out_uop.is_br connect issue_slots[2].in_uop.bits.iw_p2_poisoned, issue_slots[3].out_uop.iw_p2_poisoned connect issue_slots[2].in_uop.bits.iw_p1_poisoned, issue_slots[3].out_uop.iw_p1_poisoned connect issue_slots[2].in_uop.bits.iw_state, issue_slots[3].out_uop.iw_state connect issue_slots[2].in_uop.bits.ctrl.is_std, issue_slots[3].out_uop.ctrl.is_std connect issue_slots[2].in_uop.bits.ctrl.is_sta, issue_slots[3].out_uop.ctrl.is_sta connect issue_slots[2].in_uop.bits.ctrl.is_load, issue_slots[3].out_uop.ctrl.is_load connect issue_slots[2].in_uop.bits.ctrl.csr_cmd, issue_slots[3].out_uop.ctrl.csr_cmd connect issue_slots[2].in_uop.bits.ctrl.fcn_dw, issue_slots[3].out_uop.ctrl.fcn_dw connect issue_slots[2].in_uop.bits.ctrl.op_fcn, issue_slots[3].out_uop.ctrl.op_fcn connect issue_slots[2].in_uop.bits.ctrl.imm_sel, issue_slots[3].out_uop.ctrl.imm_sel connect issue_slots[2].in_uop.bits.ctrl.op2_sel, issue_slots[3].out_uop.ctrl.op2_sel connect issue_slots[2].in_uop.bits.ctrl.op1_sel, issue_slots[3].out_uop.ctrl.op1_sel connect issue_slots[2].in_uop.bits.ctrl.br_type, issue_slots[3].out_uop.ctrl.br_type connect issue_slots[2].in_uop.bits.fu_code, issue_slots[3].out_uop.fu_code connect issue_slots[2].in_uop.bits.iq_type, issue_slots[3].out_uop.iq_type connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst connect issue_slots[2].in_uop.bits.uopc, issue_slots[3].out_uop.uopc node _T_66 = eq(_WIRE_4, UInt<1>(0h1)) when _T_66 : connect issue_slots[2].in_uop.valid, issue_slots[3].will_be_valid connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_single, issue_slots[3].out_uop.fp_single connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.ldst_val, issue_slots[3].out_uop.ldst_val connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.bypassable, issue_slots[3].out_uop.bypassable connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[2].in_uop.bits.csr_addr, issue_slots[3].out_uop.csr_addr connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[2].in_uop.bits.is_jal, issue_slots[3].out_uop.is_jal connect issue_slots[2].in_uop.bits.is_jalr, issue_slots[3].out_uop.is_jalr connect issue_slots[2].in_uop.bits.is_br, issue_slots[3].out_uop.is_br connect issue_slots[2].in_uop.bits.iw_p2_poisoned, issue_slots[3].out_uop.iw_p2_poisoned connect issue_slots[2].in_uop.bits.iw_p1_poisoned, issue_slots[3].out_uop.iw_p1_poisoned connect issue_slots[2].in_uop.bits.iw_state, issue_slots[3].out_uop.iw_state connect issue_slots[2].in_uop.bits.ctrl.is_std, issue_slots[3].out_uop.ctrl.is_std connect issue_slots[2].in_uop.bits.ctrl.is_sta, issue_slots[3].out_uop.ctrl.is_sta connect issue_slots[2].in_uop.bits.ctrl.is_load, issue_slots[3].out_uop.ctrl.is_load connect issue_slots[2].in_uop.bits.ctrl.csr_cmd, issue_slots[3].out_uop.ctrl.csr_cmd connect issue_slots[2].in_uop.bits.ctrl.fcn_dw, issue_slots[3].out_uop.ctrl.fcn_dw connect issue_slots[2].in_uop.bits.ctrl.op_fcn, issue_slots[3].out_uop.ctrl.op_fcn connect issue_slots[2].in_uop.bits.ctrl.imm_sel, issue_slots[3].out_uop.ctrl.imm_sel connect issue_slots[2].in_uop.bits.ctrl.op2_sel, issue_slots[3].out_uop.ctrl.op2_sel connect issue_slots[2].in_uop.bits.ctrl.op1_sel, issue_slots[3].out_uop.ctrl.op1_sel connect issue_slots[2].in_uop.bits.ctrl.br_type, issue_slots[3].out_uop.ctrl.br_type connect issue_slots[2].in_uop.bits.fu_code, issue_slots[3].out_uop.fu_code connect issue_slots[2].in_uop.bits.iq_type, issue_slots[3].out_uop.iq_type connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst connect issue_slots[2].in_uop.bits.uopc, issue_slots[3].out_uop.uopc node _issue_slots_2_clear_T = neq(_WIRE_3, UInt<1>(0h0)) connect issue_slots[2].clear, _issue_slots_2_clear_T connect issue_slots[3].in_uop.valid, UInt<1>(0h0) connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_single, issue_slots[4].out_uop.fp_single connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.ldst_val, issue_slots[4].out_uop.ldst_val connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.bypassable, issue_slots[4].out_uop.bypassable connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[3].in_uop.bits.csr_addr, issue_slots[4].out_uop.csr_addr connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[3].in_uop.bits.is_jal, issue_slots[4].out_uop.is_jal connect issue_slots[3].in_uop.bits.is_jalr, issue_slots[4].out_uop.is_jalr connect issue_slots[3].in_uop.bits.is_br, issue_slots[4].out_uop.is_br connect issue_slots[3].in_uop.bits.iw_p2_poisoned, issue_slots[4].out_uop.iw_p2_poisoned connect issue_slots[3].in_uop.bits.iw_p1_poisoned, issue_slots[4].out_uop.iw_p1_poisoned connect issue_slots[3].in_uop.bits.iw_state, issue_slots[4].out_uop.iw_state connect issue_slots[3].in_uop.bits.ctrl.is_std, issue_slots[4].out_uop.ctrl.is_std connect issue_slots[3].in_uop.bits.ctrl.is_sta, issue_slots[4].out_uop.ctrl.is_sta connect issue_slots[3].in_uop.bits.ctrl.is_load, issue_slots[4].out_uop.ctrl.is_load connect issue_slots[3].in_uop.bits.ctrl.csr_cmd, issue_slots[4].out_uop.ctrl.csr_cmd connect issue_slots[3].in_uop.bits.ctrl.fcn_dw, issue_slots[4].out_uop.ctrl.fcn_dw connect issue_slots[3].in_uop.bits.ctrl.op_fcn, issue_slots[4].out_uop.ctrl.op_fcn connect issue_slots[3].in_uop.bits.ctrl.imm_sel, issue_slots[4].out_uop.ctrl.imm_sel connect issue_slots[3].in_uop.bits.ctrl.op2_sel, issue_slots[4].out_uop.ctrl.op2_sel connect issue_slots[3].in_uop.bits.ctrl.op1_sel, issue_slots[4].out_uop.ctrl.op1_sel connect issue_slots[3].in_uop.bits.ctrl.br_type, issue_slots[4].out_uop.ctrl.br_type connect issue_slots[3].in_uop.bits.fu_code, issue_slots[4].out_uop.fu_code connect issue_slots[3].in_uop.bits.iq_type, issue_slots[4].out_uop.iq_type connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst connect issue_slots[3].in_uop.bits.uopc, issue_slots[4].out_uop.uopc node _T_67 = eq(_WIRE_5, UInt<1>(0h1)) when _T_67 : connect issue_slots[3].in_uop.valid, issue_slots[4].will_be_valid connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_single, issue_slots[4].out_uop.fp_single connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.ldst_val, issue_slots[4].out_uop.ldst_val connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.bypassable, issue_slots[4].out_uop.bypassable connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[3].in_uop.bits.csr_addr, issue_slots[4].out_uop.csr_addr connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[3].in_uop.bits.is_jal, issue_slots[4].out_uop.is_jal connect issue_slots[3].in_uop.bits.is_jalr, issue_slots[4].out_uop.is_jalr connect issue_slots[3].in_uop.bits.is_br, issue_slots[4].out_uop.is_br connect issue_slots[3].in_uop.bits.iw_p2_poisoned, issue_slots[4].out_uop.iw_p2_poisoned connect issue_slots[3].in_uop.bits.iw_p1_poisoned, issue_slots[4].out_uop.iw_p1_poisoned connect issue_slots[3].in_uop.bits.iw_state, issue_slots[4].out_uop.iw_state connect issue_slots[3].in_uop.bits.ctrl.is_std, issue_slots[4].out_uop.ctrl.is_std connect issue_slots[3].in_uop.bits.ctrl.is_sta, issue_slots[4].out_uop.ctrl.is_sta connect issue_slots[3].in_uop.bits.ctrl.is_load, issue_slots[4].out_uop.ctrl.is_load connect issue_slots[3].in_uop.bits.ctrl.csr_cmd, issue_slots[4].out_uop.ctrl.csr_cmd connect issue_slots[3].in_uop.bits.ctrl.fcn_dw, issue_slots[4].out_uop.ctrl.fcn_dw connect issue_slots[3].in_uop.bits.ctrl.op_fcn, issue_slots[4].out_uop.ctrl.op_fcn connect issue_slots[3].in_uop.bits.ctrl.imm_sel, issue_slots[4].out_uop.ctrl.imm_sel connect issue_slots[3].in_uop.bits.ctrl.op2_sel, issue_slots[4].out_uop.ctrl.op2_sel connect issue_slots[3].in_uop.bits.ctrl.op1_sel, issue_slots[4].out_uop.ctrl.op1_sel connect issue_slots[3].in_uop.bits.ctrl.br_type, issue_slots[4].out_uop.ctrl.br_type connect issue_slots[3].in_uop.bits.fu_code, issue_slots[4].out_uop.fu_code connect issue_slots[3].in_uop.bits.iq_type, issue_slots[4].out_uop.iq_type connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst connect issue_slots[3].in_uop.bits.uopc, issue_slots[4].out_uop.uopc node _issue_slots_3_clear_T = neq(_WIRE_4, UInt<1>(0h0)) connect issue_slots[3].clear, _issue_slots_3_clear_T connect issue_slots[4].in_uop.valid, UInt<1>(0h0) connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_single, issue_slots[5].out_uop.fp_single connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.ldst_val, issue_slots[5].out_uop.ldst_val connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.bypassable, issue_slots[5].out_uop.bypassable connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[4].in_uop.bits.csr_addr, issue_slots[5].out_uop.csr_addr connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[4].in_uop.bits.is_jal, issue_slots[5].out_uop.is_jal connect issue_slots[4].in_uop.bits.is_jalr, issue_slots[5].out_uop.is_jalr connect issue_slots[4].in_uop.bits.is_br, issue_slots[5].out_uop.is_br connect issue_slots[4].in_uop.bits.iw_p2_poisoned, issue_slots[5].out_uop.iw_p2_poisoned connect issue_slots[4].in_uop.bits.iw_p1_poisoned, issue_slots[5].out_uop.iw_p1_poisoned connect issue_slots[4].in_uop.bits.iw_state, issue_slots[5].out_uop.iw_state connect issue_slots[4].in_uop.bits.ctrl.is_std, issue_slots[5].out_uop.ctrl.is_std connect issue_slots[4].in_uop.bits.ctrl.is_sta, issue_slots[5].out_uop.ctrl.is_sta connect issue_slots[4].in_uop.bits.ctrl.is_load, issue_slots[5].out_uop.ctrl.is_load connect issue_slots[4].in_uop.bits.ctrl.csr_cmd, issue_slots[5].out_uop.ctrl.csr_cmd connect issue_slots[4].in_uop.bits.ctrl.fcn_dw, issue_slots[5].out_uop.ctrl.fcn_dw connect issue_slots[4].in_uop.bits.ctrl.op_fcn, issue_slots[5].out_uop.ctrl.op_fcn connect issue_slots[4].in_uop.bits.ctrl.imm_sel, issue_slots[5].out_uop.ctrl.imm_sel connect issue_slots[4].in_uop.bits.ctrl.op2_sel, issue_slots[5].out_uop.ctrl.op2_sel connect issue_slots[4].in_uop.bits.ctrl.op1_sel, issue_slots[5].out_uop.ctrl.op1_sel connect issue_slots[4].in_uop.bits.ctrl.br_type, issue_slots[5].out_uop.ctrl.br_type connect issue_slots[4].in_uop.bits.fu_code, issue_slots[5].out_uop.fu_code connect issue_slots[4].in_uop.bits.iq_type, issue_slots[5].out_uop.iq_type connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst connect issue_slots[4].in_uop.bits.uopc, issue_slots[5].out_uop.uopc node _T_68 = eq(_WIRE_6, UInt<1>(0h1)) when _T_68 : connect issue_slots[4].in_uop.valid, issue_slots[5].will_be_valid connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_single, issue_slots[5].out_uop.fp_single connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.ldst_val, issue_slots[5].out_uop.ldst_val connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.bypassable, issue_slots[5].out_uop.bypassable connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[4].in_uop.bits.csr_addr, issue_slots[5].out_uop.csr_addr connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[4].in_uop.bits.is_jal, issue_slots[5].out_uop.is_jal connect issue_slots[4].in_uop.bits.is_jalr, issue_slots[5].out_uop.is_jalr connect issue_slots[4].in_uop.bits.is_br, issue_slots[5].out_uop.is_br connect issue_slots[4].in_uop.bits.iw_p2_poisoned, issue_slots[5].out_uop.iw_p2_poisoned connect issue_slots[4].in_uop.bits.iw_p1_poisoned, issue_slots[5].out_uop.iw_p1_poisoned connect issue_slots[4].in_uop.bits.iw_state, issue_slots[5].out_uop.iw_state connect issue_slots[4].in_uop.bits.ctrl.is_std, issue_slots[5].out_uop.ctrl.is_std connect issue_slots[4].in_uop.bits.ctrl.is_sta, issue_slots[5].out_uop.ctrl.is_sta connect issue_slots[4].in_uop.bits.ctrl.is_load, issue_slots[5].out_uop.ctrl.is_load connect issue_slots[4].in_uop.bits.ctrl.csr_cmd, issue_slots[5].out_uop.ctrl.csr_cmd connect issue_slots[4].in_uop.bits.ctrl.fcn_dw, issue_slots[5].out_uop.ctrl.fcn_dw connect issue_slots[4].in_uop.bits.ctrl.op_fcn, issue_slots[5].out_uop.ctrl.op_fcn connect issue_slots[4].in_uop.bits.ctrl.imm_sel, issue_slots[5].out_uop.ctrl.imm_sel connect issue_slots[4].in_uop.bits.ctrl.op2_sel, issue_slots[5].out_uop.ctrl.op2_sel connect issue_slots[4].in_uop.bits.ctrl.op1_sel, issue_slots[5].out_uop.ctrl.op1_sel connect issue_slots[4].in_uop.bits.ctrl.br_type, issue_slots[5].out_uop.ctrl.br_type connect issue_slots[4].in_uop.bits.fu_code, issue_slots[5].out_uop.fu_code connect issue_slots[4].in_uop.bits.iq_type, issue_slots[5].out_uop.iq_type connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst connect issue_slots[4].in_uop.bits.uopc, issue_slots[5].out_uop.uopc node _issue_slots_4_clear_T = neq(_WIRE_5, UInt<1>(0h0)) connect issue_slots[4].clear, _issue_slots_4_clear_T connect issue_slots[5].in_uop.valid, UInt<1>(0h0) connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_single, issue_slots[6].out_uop.fp_single connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.ldst_val, issue_slots[6].out_uop.ldst_val connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.bypassable, issue_slots[6].out_uop.bypassable connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[5].in_uop.bits.csr_addr, issue_slots[6].out_uop.csr_addr connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[5].in_uop.bits.is_jal, issue_slots[6].out_uop.is_jal connect issue_slots[5].in_uop.bits.is_jalr, issue_slots[6].out_uop.is_jalr connect issue_slots[5].in_uop.bits.is_br, issue_slots[6].out_uop.is_br connect issue_slots[5].in_uop.bits.iw_p2_poisoned, issue_slots[6].out_uop.iw_p2_poisoned connect issue_slots[5].in_uop.bits.iw_p1_poisoned, issue_slots[6].out_uop.iw_p1_poisoned connect issue_slots[5].in_uop.bits.iw_state, issue_slots[6].out_uop.iw_state connect issue_slots[5].in_uop.bits.ctrl.is_std, issue_slots[6].out_uop.ctrl.is_std connect issue_slots[5].in_uop.bits.ctrl.is_sta, issue_slots[6].out_uop.ctrl.is_sta connect issue_slots[5].in_uop.bits.ctrl.is_load, issue_slots[6].out_uop.ctrl.is_load connect issue_slots[5].in_uop.bits.ctrl.csr_cmd, issue_slots[6].out_uop.ctrl.csr_cmd connect issue_slots[5].in_uop.bits.ctrl.fcn_dw, issue_slots[6].out_uop.ctrl.fcn_dw connect issue_slots[5].in_uop.bits.ctrl.op_fcn, issue_slots[6].out_uop.ctrl.op_fcn connect issue_slots[5].in_uop.bits.ctrl.imm_sel, issue_slots[6].out_uop.ctrl.imm_sel connect issue_slots[5].in_uop.bits.ctrl.op2_sel, issue_slots[6].out_uop.ctrl.op2_sel connect issue_slots[5].in_uop.bits.ctrl.op1_sel, issue_slots[6].out_uop.ctrl.op1_sel connect issue_slots[5].in_uop.bits.ctrl.br_type, issue_slots[6].out_uop.ctrl.br_type connect issue_slots[5].in_uop.bits.fu_code, issue_slots[6].out_uop.fu_code connect issue_slots[5].in_uop.bits.iq_type, issue_slots[6].out_uop.iq_type connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst connect issue_slots[5].in_uop.bits.uopc, issue_slots[6].out_uop.uopc node _T_69 = eq(_WIRE_7, UInt<1>(0h1)) when _T_69 : connect issue_slots[5].in_uop.valid, issue_slots[6].will_be_valid connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_single, issue_slots[6].out_uop.fp_single connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.ldst_val, issue_slots[6].out_uop.ldst_val connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.bypassable, issue_slots[6].out_uop.bypassable connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[5].in_uop.bits.csr_addr, issue_slots[6].out_uop.csr_addr connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[5].in_uop.bits.is_jal, issue_slots[6].out_uop.is_jal connect issue_slots[5].in_uop.bits.is_jalr, issue_slots[6].out_uop.is_jalr connect issue_slots[5].in_uop.bits.is_br, issue_slots[6].out_uop.is_br connect issue_slots[5].in_uop.bits.iw_p2_poisoned, issue_slots[6].out_uop.iw_p2_poisoned connect issue_slots[5].in_uop.bits.iw_p1_poisoned, issue_slots[6].out_uop.iw_p1_poisoned connect issue_slots[5].in_uop.bits.iw_state, issue_slots[6].out_uop.iw_state connect issue_slots[5].in_uop.bits.ctrl.is_std, issue_slots[6].out_uop.ctrl.is_std connect issue_slots[5].in_uop.bits.ctrl.is_sta, issue_slots[6].out_uop.ctrl.is_sta connect issue_slots[5].in_uop.bits.ctrl.is_load, issue_slots[6].out_uop.ctrl.is_load connect issue_slots[5].in_uop.bits.ctrl.csr_cmd, issue_slots[6].out_uop.ctrl.csr_cmd connect issue_slots[5].in_uop.bits.ctrl.fcn_dw, issue_slots[6].out_uop.ctrl.fcn_dw connect issue_slots[5].in_uop.bits.ctrl.op_fcn, issue_slots[6].out_uop.ctrl.op_fcn connect issue_slots[5].in_uop.bits.ctrl.imm_sel, issue_slots[6].out_uop.ctrl.imm_sel connect issue_slots[5].in_uop.bits.ctrl.op2_sel, issue_slots[6].out_uop.ctrl.op2_sel connect issue_slots[5].in_uop.bits.ctrl.op1_sel, issue_slots[6].out_uop.ctrl.op1_sel connect issue_slots[5].in_uop.bits.ctrl.br_type, issue_slots[6].out_uop.ctrl.br_type connect issue_slots[5].in_uop.bits.fu_code, issue_slots[6].out_uop.fu_code connect issue_slots[5].in_uop.bits.iq_type, issue_slots[6].out_uop.iq_type connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst connect issue_slots[5].in_uop.bits.uopc, issue_slots[6].out_uop.uopc node _issue_slots_5_clear_T = neq(_WIRE_6, UInt<1>(0h0)) connect issue_slots[5].clear, _issue_slots_5_clear_T connect issue_slots[6].in_uop.valid, UInt<1>(0h0) connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_single, issue_slots[7].out_uop.fp_single connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.ldst_val, issue_slots[7].out_uop.ldst_val connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.bypassable, issue_slots[7].out_uop.bypassable connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[6].in_uop.bits.csr_addr, issue_slots[7].out_uop.csr_addr connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[6].in_uop.bits.is_jal, issue_slots[7].out_uop.is_jal connect issue_slots[6].in_uop.bits.is_jalr, issue_slots[7].out_uop.is_jalr connect issue_slots[6].in_uop.bits.is_br, issue_slots[7].out_uop.is_br connect issue_slots[6].in_uop.bits.iw_p2_poisoned, issue_slots[7].out_uop.iw_p2_poisoned connect issue_slots[6].in_uop.bits.iw_p1_poisoned, issue_slots[7].out_uop.iw_p1_poisoned connect issue_slots[6].in_uop.bits.iw_state, issue_slots[7].out_uop.iw_state connect issue_slots[6].in_uop.bits.ctrl.is_std, issue_slots[7].out_uop.ctrl.is_std connect issue_slots[6].in_uop.bits.ctrl.is_sta, issue_slots[7].out_uop.ctrl.is_sta connect issue_slots[6].in_uop.bits.ctrl.is_load, issue_slots[7].out_uop.ctrl.is_load connect issue_slots[6].in_uop.bits.ctrl.csr_cmd, issue_slots[7].out_uop.ctrl.csr_cmd connect issue_slots[6].in_uop.bits.ctrl.fcn_dw, issue_slots[7].out_uop.ctrl.fcn_dw connect issue_slots[6].in_uop.bits.ctrl.op_fcn, issue_slots[7].out_uop.ctrl.op_fcn connect issue_slots[6].in_uop.bits.ctrl.imm_sel, issue_slots[7].out_uop.ctrl.imm_sel connect issue_slots[6].in_uop.bits.ctrl.op2_sel, issue_slots[7].out_uop.ctrl.op2_sel connect issue_slots[6].in_uop.bits.ctrl.op1_sel, issue_slots[7].out_uop.ctrl.op1_sel connect issue_slots[6].in_uop.bits.ctrl.br_type, issue_slots[7].out_uop.ctrl.br_type connect issue_slots[6].in_uop.bits.fu_code, issue_slots[7].out_uop.fu_code connect issue_slots[6].in_uop.bits.iq_type, issue_slots[7].out_uop.iq_type connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst connect issue_slots[6].in_uop.bits.uopc, issue_slots[7].out_uop.uopc node _T_70 = eq(_WIRE_8, UInt<1>(0h1)) when _T_70 : connect issue_slots[6].in_uop.valid, issue_slots[7].will_be_valid connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_single, issue_slots[7].out_uop.fp_single connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.ldst_val, issue_slots[7].out_uop.ldst_val connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.bypassable, issue_slots[7].out_uop.bypassable connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[6].in_uop.bits.csr_addr, issue_slots[7].out_uop.csr_addr connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[6].in_uop.bits.is_jal, issue_slots[7].out_uop.is_jal connect issue_slots[6].in_uop.bits.is_jalr, issue_slots[7].out_uop.is_jalr connect issue_slots[6].in_uop.bits.is_br, issue_slots[7].out_uop.is_br connect issue_slots[6].in_uop.bits.iw_p2_poisoned, issue_slots[7].out_uop.iw_p2_poisoned connect issue_slots[6].in_uop.bits.iw_p1_poisoned, issue_slots[7].out_uop.iw_p1_poisoned connect issue_slots[6].in_uop.bits.iw_state, issue_slots[7].out_uop.iw_state connect issue_slots[6].in_uop.bits.ctrl.is_std, issue_slots[7].out_uop.ctrl.is_std connect issue_slots[6].in_uop.bits.ctrl.is_sta, issue_slots[7].out_uop.ctrl.is_sta connect issue_slots[6].in_uop.bits.ctrl.is_load, issue_slots[7].out_uop.ctrl.is_load connect issue_slots[6].in_uop.bits.ctrl.csr_cmd, issue_slots[7].out_uop.ctrl.csr_cmd connect issue_slots[6].in_uop.bits.ctrl.fcn_dw, issue_slots[7].out_uop.ctrl.fcn_dw connect issue_slots[6].in_uop.bits.ctrl.op_fcn, issue_slots[7].out_uop.ctrl.op_fcn connect issue_slots[6].in_uop.bits.ctrl.imm_sel, issue_slots[7].out_uop.ctrl.imm_sel connect issue_slots[6].in_uop.bits.ctrl.op2_sel, issue_slots[7].out_uop.ctrl.op2_sel connect issue_slots[6].in_uop.bits.ctrl.op1_sel, issue_slots[7].out_uop.ctrl.op1_sel connect issue_slots[6].in_uop.bits.ctrl.br_type, issue_slots[7].out_uop.ctrl.br_type connect issue_slots[6].in_uop.bits.fu_code, issue_slots[7].out_uop.fu_code connect issue_slots[6].in_uop.bits.iq_type, issue_slots[7].out_uop.iq_type connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst connect issue_slots[6].in_uop.bits.uopc, issue_slots[7].out_uop.uopc node _issue_slots_6_clear_T = neq(_WIRE_7, UInt<1>(0h0)) connect issue_slots[6].clear, _issue_slots_6_clear_T connect issue_slots[7].in_uop.valid, UInt<1>(0h0) connect issue_slots[7].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_single, _WIRE.fp_single connect issue_slots[7].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[7].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[7].in_uop.bits.ldst_val, _WIRE.ldst_val connect issue_slots[7].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[7].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[7].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[7].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[7].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[7].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[7].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[7].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[7].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[7].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[7].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[7].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[7].in_uop.bits.bypassable, _WIRE.bypassable connect issue_slots[7].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[7].in_uop.bits.exception, _WIRE.exception connect issue_slots[7].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[7].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[7].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[7].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[7].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[7].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[7].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[7].in_uop.bits.csr_addr, _WIRE.csr_addr connect issue_slots[7].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[7].in_uop.bits.taken, _WIRE.taken connect issue_slots[7].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[7].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[7].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[7].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[7].in_uop.bits.is_jal, _WIRE.is_jal connect issue_slots[7].in_uop.bits.is_jalr, _WIRE.is_jalr connect issue_slots[7].in_uop.bits.is_br, _WIRE.is_br connect issue_slots[7].in_uop.bits.iw_p2_poisoned, _WIRE.iw_p2_poisoned connect issue_slots[7].in_uop.bits.iw_p1_poisoned, _WIRE.iw_p1_poisoned connect issue_slots[7].in_uop.bits.iw_state, _WIRE.iw_state connect issue_slots[7].in_uop.bits.ctrl.is_std, _WIRE.ctrl.is_std connect issue_slots[7].in_uop.bits.ctrl.is_sta, _WIRE.ctrl.is_sta connect issue_slots[7].in_uop.bits.ctrl.is_load, _WIRE.ctrl.is_load connect issue_slots[7].in_uop.bits.ctrl.csr_cmd, _WIRE.ctrl.csr_cmd connect issue_slots[7].in_uop.bits.ctrl.fcn_dw, _WIRE.ctrl.fcn_dw connect issue_slots[7].in_uop.bits.ctrl.op_fcn, _WIRE.ctrl.op_fcn connect issue_slots[7].in_uop.bits.ctrl.imm_sel, _WIRE.ctrl.imm_sel connect issue_slots[7].in_uop.bits.ctrl.op2_sel, _WIRE.ctrl.op2_sel connect issue_slots[7].in_uop.bits.ctrl.op1_sel, _WIRE.ctrl.op1_sel connect issue_slots[7].in_uop.bits.ctrl.br_type, _WIRE.ctrl.br_type connect issue_slots[7].in_uop.bits.fu_code, _WIRE.fu_code connect issue_slots[7].in_uop.bits.iq_type, _WIRE.iq_type connect issue_slots[7].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[7].in_uop.bits.inst, _WIRE.inst connect issue_slots[7].in_uop.bits.uopc, _WIRE.uopc node _T_71 = eq(_WIRE_9, UInt<1>(0h1)) when _T_71 : connect issue_slots[7].in_uop.valid, will_be_valid_8 connect issue_slots[7].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_single, _WIRE.fp_single connect issue_slots[7].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[7].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[7].in_uop.bits.ldst_val, _WIRE.ldst_val connect issue_slots[7].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[7].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[7].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[7].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[7].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[7].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[7].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[7].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[7].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[7].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[7].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[7].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[7].in_uop.bits.bypassable, _WIRE.bypassable connect issue_slots[7].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[7].in_uop.bits.exception, _WIRE.exception connect issue_slots[7].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[7].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[7].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[7].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[7].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[7].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[7].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[7].in_uop.bits.csr_addr, _WIRE.csr_addr connect issue_slots[7].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[7].in_uop.bits.taken, _WIRE.taken connect issue_slots[7].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[7].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[7].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[7].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[7].in_uop.bits.is_jal, _WIRE.is_jal connect issue_slots[7].in_uop.bits.is_jalr, _WIRE.is_jalr connect issue_slots[7].in_uop.bits.is_br, _WIRE.is_br connect issue_slots[7].in_uop.bits.iw_p2_poisoned, _WIRE.iw_p2_poisoned connect issue_slots[7].in_uop.bits.iw_p1_poisoned, _WIRE.iw_p1_poisoned connect issue_slots[7].in_uop.bits.iw_state, _WIRE.iw_state connect issue_slots[7].in_uop.bits.ctrl.is_std, _WIRE.ctrl.is_std connect issue_slots[7].in_uop.bits.ctrl.is_sta, _WIRE.ctrl.is_sta connect issue_slots[7].in_uop.bits.ctrl.is_load, _WIRE.ctrl.is_load connect issue_slots[7].in_uop.bits.ctrl.csr_cmd, _WIRE.ctrl.csr_cmd connect issue_slots[7].in_uop.bits.ctrl.fcn_dw, _WIRE.ctrl.fcn_dw connect issue_slots[7].in_uop.bits.ctrl.op_fcn, _WIRE.ctrl.op_fcn connect issue_slots[7].in_uop.bits.ctrl.imm_sel, _WIRE.ctrl.imm_sel connect issue_slots[7].in_uop.bits.ctrl.op2_sel, _WIRE.ctrl.op2_sel connect issue_slots[7].in_uop.bits.ctrl.op1_sel, _WIRE.ctrl.op1_sel connect issue_slots[7].in_uop.bits.ctrl.br_type, _WIRE.ctrl.br_type connect issue_slots[7].in_uop.bits.fu_code, _WIRE.fu_code connect issue_slots[7].in_uop.bits.iq_type, _WIRE.iq_type connect issue_slots[7].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[7].in_uop.bits.inst, _WIRE.inst connect issue_slots[7].in_uop.bits.uopc, _WIRE.uopc node _issue_slots_7_clear_T = neq(_WIRE_8, UInt<1>(0h0)) connect issue_slots[7].clear, _issue_slots_7_clear_T node _will_be_available_T = eq(issue_slots[0].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_1 = or(_will_be_available_T, issue_slots[0].clear) node _will_be_available_T_2 = eq(issue_slots[0].in_uop.valid, UInt<1>(0h0)) node will_be_available_0 = and(_will_be_available_T_1, _will_be_available_T_2) node _will_be_available_T_3 = eq(issue_slots[1].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_4 = or(_will_be_available_T_3, issue_slots[1].clear) node _will_be_available_T_5 = eq(issue_slots[1].in_uop.valid, UInt<1>(0h0)) node will_be_available_1 = and(_will_be_available_T_4, _will_be_available_T_5) node _will_be_available_T_6 = eq(issue_slots[2].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_7 = or(_will_be_available_T_6, issue_slots[2].clear) node _will_be_available_T_8 = eq(issue_slots[2].in_uop.valid, UInt<1>(0h0)) node will_be_available_2 = and(_will_be_available_T_7, _will_be_available_T_8) node _will_be_available_T_9 = eq(issue_slots[3].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_10 = or(_will_be_available_T_9, issue_slots[3].clear) node _will_be_available_T_11 = eq(issue_slots[3].in_uop.valid, UInt<1>(0h0)) node will_be_available_3 = and(_will_be_available_T_10, _will_be_available_T_11) node _will_be_available_T_12 = eq(issue_slots[4].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_13 = or(_will_be_available_T_12, issue_slots[4].clear) node _will_be_available_T_14 = eq(issue_slots[4].in_uop.valid, UInt<1>(0h0)) node will_be_available_4 = and(_will_be_available_T_13, _will_be_available_T_14) node _will_be_available_T_15 = eq(issue_slots[5].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_16 = or(_will_be_available_T_15, issue_slots[5].clear) node _will_be_available_T_17 = eq(issue_slots[5].in_uop.valid, UInt<1>(0h0)) node will_be_available_5 = and(_will_be_available_T_16, _will_be_available_T_17) node _will_be_available_T_18 = eq(issue_slots[6].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_19 = or(_will_be_available_T_18, issue_slots[6].clear) node _will_be_available_T_20 = eq(issue_slots[6].in_uop.valid, UInt<1>(0h0)) node will_be_available_6 = and(_will_be_available_T_19, _will_be_available_T_20) node _will_be_available_T_21 = eq(issue_slots[7].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_22 = or(_will_be_available_T_21, issue_slots[7].clear) node _will_be_available_T_23 = eq(issue_slots[7].in_uop.valid, UInt<1>(0h0)) node will_be_available_7 = and(_will_be_available_T_22, _will_be_available_T_23) node _num_available_T = add(will_be_available_0, will_be_available_1) node _num_available_T_1 = bits(_num_available_T, 1, 0) node _num_available_T_2 = add(will_be_available_2, will_be_available_3) node _num_available_T_3 = bits(_num_available_T_2, 1, 0) node _num_available_T_4 = add(_num_available_T_1, _num_available_T_3) node _num_available_T_5 = bits(_num_available_T_4, 2, 0) node _num_available_T_6 = add(will_be_available_4, will_be_available_5) node _num_available_T_7 = bits(_num_available_T_6, 1, 0) node _num_available_T_8 = add(will_be_available_6, will_be_available_7) node _num_available_T_9 = bits(_num_available_T_8, 1, 0) node _num_available_T_10 = add(_num_available_T_7, _num_available_T_9) node _num_available_T_11 = bits(_num_available_T_10, 2, 0) node _num_available_T_12 = add(_num_available_T_5, _num_available_T_11) node num_available = bits(_num_available_T_12, 3, 0) node _io_dis_uops_0_ready_T = gt(num_available, UInt<1>(0h0)) reg io_dis_uops_0_ready_REG : UInt<1>, clock connect io_dis_uops_0_ready_REG, _io_dis_uops_0_ready_T connect io.dis_uops[0].ready, io_dis_uops_0_ready_REG connect io.iss_valids[0], UInt<1>(0h0) wire io_iss_uops_0_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate io_iss_uops_0_uop.debug_tsrc invalidate io_iss_uops_0_uop.debug_fsrc invalidate io_iss_uops_0_uop.bp_xcpt_if invalidate io_iss_uops_0_uop.bp_debug_if invalidate io_iss_uops_0_uop.xcpt_ma_if invalidate io_iss_uops_0_uop.xcpt_ae_if invalidate io_iss_uops_0_uop.xcpt_pf_if invalidate io_iss_uops_0_uop.fp_single invalidate io_iss_uops_0_uop.fp_val invalidate io_iss_uops_0_uop.frs3_en invalidate io_iss_uops_0_uop.lrs2_rtype invalidate io_iss_uops_0_uop.lrs1_rtype invalidate io_iss_uops_0_uop.dst_rtype invalidate io_iss_uops_0_uop.ldst_val invalidate io_iss_uops_0_uop.lrs3 invalidate io_iss_uops_0_uop.lrs2 invalidate io_iss_uops_0_uop.lrs1 invalidate io_iss_uops_0_uop.ldst invalidate io_iss_uops_0_uop.ldst_is_rs1 invalidate io_iss_uops_0_uop.flush_on_commit invalidate io_iss_uops_0_uop.is_unique invalidate io_iss_uops_0_uop.is_sys_pc2epc invalidate io_iss_uops_0_uop.uses_stq invalidate io_iss_uops_0_uop.uses_ldq invalidate io_iss_uops_0_uop.is_amo invalidate io_iss_uops_0_uop.is_fencei invalidate io_iss_uops_0_uop.is_fence invalidate io_iss_uops_0_uop.mem_signed invalidate io_iss_uops_0_uop.mem_size invalidate io_iss_uops_0_uop.mem_cmd invalidate io_iss_uops_0_uop.bypassable invalidate io_iss_uops_0_uop.exc_cause invalidate io_iss_uops_0_uop.exception invalidate io_iss_uops_0_uop.stale_pdst invalidate io_iss_uops_0_uop.ppred_busy invalidate io_iss_uops_0_uop.prs3_busy invalidate io_iss_uops_0_uop.prs2_busy invalidate io_iss_uops_0_uop.prs1_busy invalidate io_iss_uops_0_uop.ppred invalidate io_iss_uops_0_uop.prs3 invalidate io_iss_uops_0_uop.prs2 invalidate io_iss_uops_0_uop.prs1 invalidate io_iss_uops_0_uop.pdst invalidate io_iss_uops_0_uop.rxq_idx invalidate io_iss_uops_0_uop.stq_idx invalidate io_iss_uops_0_uop.ldq_idx invalidate io_iss_uops_0_uop.rob_idx invalidate io_iss_uops_0_uop.csr_addr invalidate io_iss_uops_0_uop.imm_packed invalidate io_iss_uops_0_uop.taken invalidate io_iss_uops_0_uop.pc_lob invalidate io_iss_uops_0_uop.edge_inst invalidate io_iss_uops_0_uop.ftq_idx invalidate io_iss_uops_0_uop.br_tag invalidate io_iss_uops_0_uop.br_mask invalidate io_iss_uops_0_uop.is_sfb invalidate io_iss_uops_0_uop.is_jal invalidate io_iss_uops_0_uop.is_jalr invalidate io_iss_uops_0_uop.is_br invalidate io_iss_uops_0_uop.iw_p2_poisoned invalidate io_iss_uops_0_uop.iw_p1_poisoned invalidate io_iss_uops_0_uop.iw_state invalidate io_iss_uops_0_uop.ctrl.is_std invalidate io_iss_uops_0_uop.ctrl.is_sta invalidate io_iss_uops_0_uop.ctrl.is_load invalidate io_iss_uops_0_uop.ctrl.csr_cmd invalidate io_iss_uops_0_uop.ctrl.fcn_dw invalidate io_iss_uops_0_uop.ctrl.op_fcn invalidate io_iss_uops_0_uop.ctrl.imm_sel invalidate io_iss_uops_0_uop.ctrl.op2_sel invalidate io_iss_uops_0_uop.ctrl.op1_sel invalidate io_iss_uops_0_uop.ctrl.br_type invalidate io_iss_uops_0_uop.fu_code invalidate io_iss_uops_0_uop.iq_type invalidate io_iss_uops_0_uop.debug_pc invalidate io_iss_uops_0_uop.is_rvc invalidate io_iss_uops_0_uop.debug_inst invalidate io_iss_uops_0_uop.inst invalidate io_iss_uops_0_uop.uopc connect io_iss_uops_0_uop.uopc, UInt<7>(0h0) connect io_iss_uops_0_uop.bypassable, UInt<1>(0h0) connect io_iss_uops_0_uop.fp_val, UInt<1>(0h0) connect io_iss_uops_0_uop.uses_stq, UInt<1>(0h0) connect io_iss_uops_0_uop.uses_ldq, UInt<1>(0h0) connect io_iss_uops_0_uop.pdst, UInt<1>(0h0) connect io_iss_uops_0_uop.dst_rtype, UInt<2>(0h2) wire io_iss_uops_0_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate io_iss_uops_0_cs.is_std invalidate io_iss_uops_0_cs.is_sta invalidate io_iss_uops_0_cs.is_load invalidate io_iss_uops_0_cs.csr_cmd invalidate io_iss_uops_0_cs.fcn_dw invalidate io_iss_uops_0_cs.op_fcn invalidate io_iss_uops_0_cs.imm_sel invalidate io_iss_uops_0_cs.op2_sel invalidate io_iss_uops_0_cs.op1_sel invalidate io_iss_uops_0_cs.br_type connect io_iss_uops_0_cs.br_type, UInt<4>(0h0) connect io_iss_uops_0_cs.csr_cmd, UInt<3>(0h0) connect io_iss_uops_0_cs.is_load, UInt<1>(0h0) connect io_iss_uops_0_cs.is_sta, UInt<1>(0h0) connect io_iss_uops_0_cs.is_std, UInt<1>(0h0) connect io_iss_uops_0_uop.ctrl, io_iss_uops_0_cs connect io.iss_uops[0], io_iss_uops_0_uop connect io.iss_uops[0].prs1, UInt<1>(0h0) connect io.iss_uops[0].prs2, UInt<1>(0h0) connect io.iss_uops[0].prs3, UInt<1>(0h0) connect io.iss_uops[0].lrs1_rtype, UInt<2>(0h2) connect io.iss_uops[0].lrs2_rtype, UInt<2>(0h2) connect issue_slots[0].grant, UInt<1>(0h0) node _can_allocate_T = and(issue_slots[0].uop.fu_code, io.fu_types[0]) node can_allocate = neq(_can_allocate_T, UInt<1>(0h0)) node _T_72 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_73 = and(issue_slots[0].request, _T_72) node _T_74 = and(_T_73, can_allocate) node _T_75 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_76 = and(_T_74, _T_75) when _T_76 : connect issue_slots[0].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[0].uop node _T_77 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_78 = and(issue_slots[0].request, _T_77) node _T_79 = and(_T_78, can_allocate) node _T_80 = or(_T_79, UInt<1>(0h0)) node _T_81 = and(issue_slots[0].request, can_allocate) node _T_82 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_83 = and(_T_81, _T_82) node _T_84 = or(_T_83, UInt<1>(0h0)) connect issue_slots[1].grant, UInt<1>(0h0) node _can_allocate_T_1 = and(issue_slots[1].uop.fu_code, io.fu_types[0]) node can_allocate_1 = neq(_can_allocate_T_1, UInt<1>(0h0)) node _T_85 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_86 = and(issue_slots[1].request, _T_85) node _T_87 = and(_T_86, can_allocate_1) node _T_88 = eq(_T_80, UInt<1>(0h0)) node _T_89 = and(_T_87, _T_88) when _T_89 : connect issue_slots[1].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[1].uop node _T_90 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_91 = and(issue_slots[1].request, _T_90) node _T_92 = and(_T_91, can_allocate_1) node _T_93 = or(_T_92, _T_80) node _T_94 = and(issue_slots[1].request, can_allocate_1) node _T_95 = eq(_T_80, UInt<1>(0h0)) node _T_96 = and(_T_94, _T_95) node _T_97 = or(_T_96, UInt<1>(0h0)) connect issue_slots[2].grant, UInt<1>(0h0) node _can_allocate_T_2 = and(issue_slots[2].uop.fu_code, io.fu_types[0]) node can_allocate_2 = neq(_can_allocate_T_2, UInt<1>(0h0)) node _T_98 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_99 = and(issue_slots[2].request, _T_98) node _T_100 = and(_T_99, can_allocate_2) node _T_101 = eq(_T_93, UInt<1>(0h0)) node _T_102 = and(_T_100, _T_101) when _T_102 : connect issue_slots[2].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[2].uop node _T_103 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_104 = and(issue_slots[2].request, _T_103) node _T_105 = and(_T_104, can_allocate_2) node _T_106 = or(_T_105, _T_93) node _T_107 = and(issue_slots[2].request, can_allocate_2) node _T_108 = eq(_T_93, UInt<1>(0h0)) node _T_109 = and(_T_107, _T_108) node _T_110 = or(_T_109, UInt<1>(0h0)) connect issue_slots[3].grant, UInt<1>(0h0) node _can_allocate_T_3 = and(issue_slots[3].uop.fu_code, io.fu_types[0]) node can_allocate_3 = neq(_can_allocate_T_3, UInt<1>(0h0)) node _T_111 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_112 = and(issue_slots[3].request, _T_111) node _T_113 = and(_T_112, can_allocate_3) node _T_114 = eq(_T_106, UInt<1>(0h0)) node _T_115 = and(_T_113, _T_114) when _T_115 : connect issue_slots[3].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[3].uop node _T_116 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_117 = and(issue_slots[3].request, _T_116) node _T_118 = and(_T_117, can_allocate_3) node _T_119 = or(_T_118, _T_106) node _T_120 = and(issue_slots[3].request, can_allocate_3) node _T_121 = eq(_T_106, UInt<1>(0h0)) node _T_122 = and(_T_120, _T_121) node _T_123 = or(_T_122, UInt<1>(0h0)) connect issue_slots[4].grant, UInt<1>(0h0) node _can_allocate_T_4 = and(issue_slots[4].uop.fu_code, io.fu_types[0]) node can_allocate_4 = neq(_can_allocate_T_4, UInt<1>(0h0)) node _T_124 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_125 = and(issue_slots[4].request, _T_124) node _T_126 = and(_T_125, can_allocate_4) node _T_127 = eq(_T_119, UInt<1>(0h0)) node _T_128 = and(_T_126, _T_127) when _T_128 : connect issue_slots[4].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[4].uop node _T_129 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_130 = and(issue_slots[4].request, _T_129) node _T_131 = and(_T_130, can_allocate_4) node _T_132 = or(_T_131, _T_119) node _T_133 = and(issue_slots[4].request, can_allocate_4) node _T_134 = eq(_T_119, UInt<1>(0h0)) node _T_135 = and(_T_133, _T_134) node _T_136 = or(_T_135, UInt<1>(0h0)) connect issue_slots[5].grant, UInt<1>(0h0) node _can_allocate_T_5 = and(issue_slots[5].uop.fu_code, io.fu_types[0]) node can_allocate_5 = neq(_can_allocate_T_5, UInt<1>(0h0)) node _T_137 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_138 = and(issue_slots[5].request, _T_137) node _T_139 = and(_T_138, can_allocate_5) node _T_140 = eq(_T_132, UInt<1>(0h0)) node _T_141 = and(_T_139, _T_140) when _T_141 : connect issue_slots[5].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[5].uop node _T_142 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_143 = and(issue_slots[5].request, _T_142) node _T_144 = and(_T_143, can_allocate_5) node _T_145 = or(_T_144, _T_132) node _T_146 = and(issue_slots[5].request, can_allocate_5) node _T_147 = eq(_T_132, UInt<1>(0h0)) node _T_148 = and(_T_146, _T_147) node _T_149 = or(_T_148, UInt<1>(0h0)) connect issue_slots[6].grant, UInt<1>(0h0) node _can_allocate_T_6 = and(issue_slots[6].uop.fu_code, io.fu_types[0]) node can_allocate_6 = neq(_can_allocate_T_6, UInt<1>(0h0)) node _T_150 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = and(issue_slots[6].request, _T_150) node _T_152 = and(_T_151, can_allocate_6) node _T_153 = eq(_T_145, UInt<1>(0h0)) node _T_154 = and(_T_152, _T_153) when _T_154 : connect issue_slots[6].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[6].uop node _T_155 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_156 = and(issue_slots[6].request, _T_155) node _T_157 = and(_T_156, can_allocate_6) node _T_158 = or(_T_157, _T_145) node _T_159 = and(issue_slots[6].request, can_allocate_6) node _T_160 = eq(_T_145, UInt<1>(0h0)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(_T_161, UInt<1>(0h0)) connect issue_slots[7].grant, UInt<1>(0h0) node _can_allocate_T_7 = and(issue_slots[7].uop.fu_code, io.fu_types[0]) node can_allocate_7 = neq(_can_allocate_T_7, UInt<1>(0h0)) node _T_163 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_164 = and(issue_slots[7].request, _T_163) node _T_165 = and(_T_164, can_allocate_7) node _T_166 = eq(_T_158, UInt<1>(0h0)) node _T_167 = and(_T_165, _T_166) when _T_167 : connect issue_slots[7].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[7].uop node _T_168 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_169 = and(issue_slots[7].request, _T_168) node _T_170 = and(_T_169, can_allocate_7) node _T_171 = or(_T_170, _T_158) node _T_172 = and(issue_slots[7].request, can_allocate_7) node _T_173 = eq(_T_158, UInt<1>(0h0)) node _T_174 = and(_T_172, _T_173) node _T_175 = or(_T_174, UInt<1>(0h0))	module IssueUnitCollapsing_3( // @[issue-unit-age-ordered.scala:29:7] input clock, // @[issue-unit-age-ordered.scala:29:7] input reset, // @[issue-unit-age-ordered.scala:29:7] output io_dis_uops_0_ready, // @[issue-unit.scala:112:14] input io_dis_uops_0_valid, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_0_bits_uopc, // @[issue-unit.scala:112:14] input [31:0] io_dis_uops_0_bits_inst, // @[issue-unit.scala:112:14] input [31:0] io_dis_uops_0_bits_debug_inst, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_rvc, // @[issue-unit.scala:112:14] input [39:0] io_dis_uops_0_bits_debug_pc, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_iq_type, // @[issue-unit.scala:112:14] input [9:0] io_dis_uops_0_bits_fu_code, // @[issue-unit.scala:112:14] input [3:0] io_dis_uops_0_bits_ctrl_br_type, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_ctrl_op1_sel, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_ctrl_op2_sel, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_ctrl_imm_sel, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_0_bits_ctrl_op_fcn, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ctrl_fcn_dw, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_ctrl_csr_cmd, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ctrl_is_load, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ctrl_is_sta, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ctrl_is_std, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_iw_state, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_iw_p1_poisoned, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_iw_p2_poisoned, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_br, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_jalr, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_jal, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_sfb, // @[issue-unit.scala:112:14] input [7:0] io_dis_uops_0_bits_br_mask, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_br_tag, // @[issue-unit.scala:112:14] input [3:0] io_dis_uops_0_bits_ftq_idx, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_edge_inst, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_pc_lob, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_taken, // @[issue-unit.scala:112:14] input [19:0] io_dis_uops_0_bits_imm_packed, // @[issue-unit.scala:112:14] input [11:0] io_dis_uops_0_bits_csr_addr, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_0_bits_rob_idx, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_ldq_idx, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_stq_idx, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_rxq_idx, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_pdst, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_prs1, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_prs2, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_prs3, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_prs1_busy, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_prs2_busy, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_prs3_busy, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_stale_pdst, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_exception, // @[issue-unit.scala:112:14] input [63:0] io_dis_uops_0_bits_exc_cause, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_bypassable, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_0_bits_mem_cmd, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_mem_size, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_mem_signed, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_fence, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_fencei, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_amo, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_uses_ldq, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_uses_stq, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_unique, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_flush_on_commit, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_ldst, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_lrs1, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_lrs2, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_lrs3, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ldst_val, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_dst_rtype, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_frs3_en, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_fp_val, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_fp_single, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_bp_debug_if, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_debug_fsrc, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_debug_tsrc, // @[issue-unit.scala:112:14] output io_iss_valids_0, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_0_uopc, // @[issue-unit.scala:112:14] output [31:0] io_iss_uops_0_inst, // @[issue-unit.scala:112:14] output [31:0] io_iss_uops_0_debug_inst, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_rvc, // @[issue-unit.scala:112:14] output [39:0] io_iss_uops_0_debug_pc, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_iq_type, // @[issue-unit.scala:112:14] output [9:0] io_iss_uops_0_fu_code, // @[issue-unit.scala:112:14] output [3:0] io_iss_uops_0_ctrl_br_type, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_ctrl_op1_sel, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_ctrl_op2_sel, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_ctrl_imm_sel, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_0_ctrl_op_fcn, // @[issue-unit.scala:112:14] output io_iss_uops_0_ctrl_fcn_dw, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_ctrl_csr_cmd, // @[issue-unit.scala:112:14] output io_iss_uops_0_ctrl_is_load, // @[issue-unit.scala:112:14] output io_iss_uops_0_ctrl_is_sta, // @[issue-unit.scala:112:14] output io_iss_uops_0_ctrl_is_std, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_iw_state, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_br, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_jalr, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_jal, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_sfb, // @[issue-unit.scala:112:14] output [7:0] io_iss_uops_0_br_mask, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_br_tag, // @[issue-unit.scala:112:14] output [3:0] io_iss_uops_0_ftq_idx, // @[issue-unit.scala:112:14] output io_iss_uops_0_edge_inst, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_pc_lob, // @[issue-unit.scala:112:14] output io_iss_uops_0_taken, // @[issue-unit.scala:112:14] output [19:0] io_iss_uops_0_imm_packed, // @[issue-unit.scala:112:14] output [11:0] io_iss_uops_0_csr_addr, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_0_rob_idx, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_ldq_idx, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_stq_idx, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_rxq_idx, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_pdst, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_prs1, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_prs2, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_prs3, // @[issue-unit.scala:112:14] output [3:0] io_iss_uops_0_ppred, // @[issue-unit.scala:112:14] output io_iss_uops_0_prs1_busy, // @[issue-unit.scala:112:14] output io_iss_uops_0_prs2_busy, // @[issue-unit.scala:112:14] output io_iss_uops_0_prs3_busy, // @[issue-unit.scala:112:14] output io_iss_uops_0_ppred_busy, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_stale_pdst, // @[issue-unit.scala:112:14] output io_iss_uops_0_exception, // @[issue-unit.scala:112:14] output [63:0] io_iss_uops_0_exc_cause, // @[issue-unit.scala:112:14] output io_iss_uops_0_bypassable, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_0_mem_cmd, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_mem_size, // @[issue-unit.scala:112:14] output io_iss_uops_0_mem_signed, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_fence, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_fencei, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_amo, // @[issue-unit.scala:112:14] output io_iss_uops_0_uses_ldq, // @[issue-unit.scala:112:14] output io_iss_uops_0_uses_stq, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_sys_pc2epc, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_unique, // @[issue-unit.scala:112:14] output io_iss_uops_0_flush_on_commit, // @[issue-unit.scala:112:14] output io_iss_uops_0_ldst_is_rs1, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_ldst, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_lrs1, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_lrs2, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_lrs3, // @[issue-unit.scala:112:14] output io_iss_uops_0_ldst_val, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_dst_rtype, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_lrs1_rtype, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_lrs2_rtype, // @[issue-unit.scala:112:14] output io_iss_uops_0_frs3_en, // @[issue-unit.scala:112:14] output io_iss_uops_0_fp_val, // @[issue-unit.scala:112:14] output io_iss_uops_0_fp_single, // @[issue-unit.scala:112:14] output io_iss_uops_0_xcpt_pf_if, // @[issue-unit.scala:112:14] output io_iss_uops_0_xcpt_ae_if, // @[issue-unit.scala:112:14] output io_iss_uops_0_xcpt_ma_if, // @[issue-unit.scala:112:14] output io_iss_uops_0_bp_debug_if, // @[issue-unit.scala:112:14] output io_iss_uops_0_bp_xcpt_if, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_debug_fsrc, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_debug_tsrc, // @[issue-unit.scala:112:14] input io_wakeup_ports_0_valid, // @[issue-unit.scala:112:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-unit.scala:112:14] input io_wakeup_ports_1_valid, // @[issue-unit.scala:112:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-unit.scala:112:14] input [9:0] io_fu_types_0, // @[issue-unit.scala:112:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-unit.scala:112:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-unit.scala:112:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-unit.scala:112:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-unit.scala:112:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_rvc, // @[issue-unit.scala:112:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-unit.scala:112:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-unit.scala:112:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-unit.scala:112:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_br, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_jalr, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_jal, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_sfb, // @[issue-unit.scala:112:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-unit.scala:112:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_edge_inst, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_taken, // @[issue-unit.scala:112:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-unit.scala:112:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-unit.scala:112:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-unit.scala:112:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_exception, // @[issue-unit.scala:112:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_bypassable, // @[issue-unit.scala:112:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_mem_signed, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_fence, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_fencei, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_amo, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_uses_stq, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_unique, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ldst_val, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_frs3_en, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_fp_val, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_fp_single, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-unit.scala:112:14] input io_brupdate_b2_valid, // @[issue-unit.scala:112:14] input io_brupdate_b2_mispredict, // @[issue-unit.scala:112:14] input io_brupdate_b2_taken, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-unit.scala:112:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-unit.scala:112:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-unit.scala:112:14] input io_flush_pipeline, // @[issue-unit.scala:112:14] input [63:0] io_tsc_reg // @[issue-unit.scala:112:14] ); wire _slots_7_io_valid; // @[issue-unit.scala:153:73] wire _slots_6_io_valid; // @[issue-unit.scala:153:73] wire _slots_5_io_valid; // @[issue-unit.scala:153:73] wire _slots_4_io_valid; // @[issue-unit.scala:153:73] wire _slots_3_io_valid; // @[issue-unit.scala:153:73] wire _slots_2_io_valid; // @[issue-unit.scala:153:73] wire _slots_1_io_valid; // @[issue-unit.scala:153:73] wire _slots_0_io_valid; // @[issue-unit.scala:153:73] wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_0_bits_uopc_0 = io_dis_uops_0_bits_uopc; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_iq_type_0 = io_dis_uops_0_bits_iq_type; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_dis_uops_0_bits_fu_code_0 = io_dis_uops_0_bits_fu_code; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_dis_uops_0_bits_ctrl_br_type_0 = io_dis_uops_0_bits_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_ctrl_op1_sel_0 = io_dis_uops_0_bits_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_ctrl_op2_sel_0 = io_dis_uops_0_bits_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_ctrl_imm_sel_0 = io_dis_uops_0_bits_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_0_bits_ctrl_op_fcn_0 = io_dis_uops_0_bits_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ctrl_fcn_dw_0 = io_dis_uops_0_bits_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_ctrl_csr_cmd_0 = io_dis_uops_0_bits_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ctrl_is_load_0 = io_dis_uops_0_bits_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ctrl_is_sta_0 = io_dis_uops_0_bits_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ctrl_is_std_0 = io_dis_uops_0_bits_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_iw_state_0 = io_dis_uops_0_bits_iw_state; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_iw_p1_poisoned_0 = io_dis_uops_0_bits_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_iw_p2_poisoned_0 = io_dis_uops_0_bits_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_br_0 = io_dis_uops_0_bits_is_br; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_jalr_0 = io_dis_uops_0_bits_is_jalr; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_jal_0 = io_dis_uops_0_bits_is_jal; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:29:7] wire [7:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:29:7] wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:29:7] wire [11:0] io_dis_uops_0_bits_csr_addr_0 = io_dis_uops_0_bits_csr_addr; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_bypassable_0 = io_dis_uops_0_bits_bypassable; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ldst_val_0 = io_dis_uops_0_bits_ldst_val; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_fp_single_0 = io_dis_uops_0_bits_fp_single; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_fu_types_0_0 = io_fu_types_0; // @[issue-unit-age-ordered.scala:29:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-unit-age-ordered.scala:29:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-unit-age-ordered.scala:29:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-unit-age-ordered.scala:29:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-unit-age-ordered.scala:29:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-unit-age-ordered.scala:29:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-unit-age-ordered.scala:29:7] wire io_flush_pipeline_0 = io_flush_pipeline; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_tsc_reg_0 = io_tsc_reg; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_iw_p1_poisoned = 1'h0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_iw_p2_poisoned = 1'h0; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit-age-ordered.scala:29:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:29:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit-age-ordered.scala:29:7] wire io_ld_miss = 1'h0; // @[issue-unit-age-ordered.scala:29:7] wire issue_slots_0_clear = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_0_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_0_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_0_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_1_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_1_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_1_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_2_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_2_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_2_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_3_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_3_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_3_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_4_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_4_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_4_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_5_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_5_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_5_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_6_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_6_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_6_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_ldspec_miss = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_spec_ld_wakeup_0_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ppred_busy = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ppred_busy = 1'h0; // @[issue-unit.scala:154:28] wire _issue_slots_0_clear_T = 1'h0; // @[issue-unit-age-ordered.scala:76:49] wire io_iss_uops_0_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_br = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_taken = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_exception = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_0_cs_is_load = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_0_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_0_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [3:0] io_dis_uops_0_bits_ppred = 4'h0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] issue_slots_0_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_in_uop_bits_ppred = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_in_uop_bits_ppred = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_out_uop_ppred = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_uop_ppred = 4'h0; // @[issue-unit.scala:154:28] wire [3:0] io_iss_uops_0_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] io_iss_uops_0_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] io_iss_uops_0_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] io_iss_uops_0_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] issue_slots_7_in_uop_bits_iw_state = 2'h1; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_iw_state = 2'h1; // @[issue-unit.scala:154:28] wire [5:0] io_spec_ld_wakeup_0_bits = 6'h0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] issue_slots_0_spec_ld_wakeup_0_bits = 6'h0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_spec_ld_wakeup_0_bits = 6'h0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_spec_ld_wakeup_0_bits = 6'h0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_spec_ld_wakeup_0_bits = 6'h0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_spec_ld_wakeup_0_bits = 6'h0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_spec_ld_wakeup_0_bits = 6'h0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_spec_ld_wakeup_0_bits = 6'h0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_spec_ld_wakeup_0_bits = 6'h0; // @[issue-unit.scala:154:28] wire [5:0] io_iss_uops_0_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] io_iss_uops_0_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] io_iss_uops_0_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] io_iss_uops_0_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_0_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_0_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_0_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] _next_T = 2'h0; // @[issue-unit-age-ordered.scala:48:26] wire [1:0] io_iss_uops_0_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] io_iss_uops_0_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [63:0] io_iss_uops_0_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] io_iss_uops_0_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] io_iss_uops_0_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] io_iss_uops_0_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] io_iss_uops_0_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] io_iss_uops_0_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] io_iss_uops_0_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] io_iss_uops_0_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_0_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] issue_slots_7_in_uop_bits_uopc = io_dis_uops_0_bits_uopc_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_in_uop_bits_inst = io_dis_uops_0_bits_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_in_uop_bits_debug_inst = io_dis_uops_0_bits_debug_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_rvc = io_dis_uops_0_bits_is_rvc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_7_in_uop_bits_debug_pc = io_dis_uops_0_bits_debug_pc_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_iq_type = io_dis_uops_0_bits_iq_type_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_7_in_uop_bits_fu_code = io_dis_uops_0_bits_fu_code_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_in_uop_bits_ctrl_br_type = io_dis_uops_0_bits_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_ctrl_op1_sel = io_dis_uops_0_bits_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_ctrl_op2_sel = io_dis_uops_0_bits_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_ctrl_imm_sel = io_dis_uops_0_bits_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_in_uop_bits_ctrl_op_fcn = io_dis_uops_0_bits_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ctrl_fcn_dw = io_dis_uops_0_bits_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_ctrl_csr_cmd = io_dis_uops_0_bits_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ctrl_is_load = io_dis_uops_0_bits_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ctrl_is_sta = io_dis_uops_0_bits_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ctrl_is_std = io_dis_uops_0_bits_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_br = io_dis_uops_0_bits_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_jalr = io_dis_uops_0_bits_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_jal = io_dis_uops_0_bits_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_sfb = io_dis_uops_0_bits_is_sfb_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_7_in_uop_bits_br_mask = io_dis_uops_0_bits_br_mask_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_br_tag = io_dis_uops_0_bits_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_in_uop_bits_ftq_idx = io_dis_uops_0_bits_ftq_idx_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_edge_inst = io_dis_uops_0_bits_edge_inst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_pc_lob = io_dis_uops_0_bits_pc_lob_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_taken = io_dis_uops_0_bits_taken_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_7_in_uop_bits_imm_packed = io_dis_uops_0_bits_imm_packed_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_7_in_uop_bits_csr_addr = io_dis_uops_0_bits_csr_addr_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_in_uop_bits_rob_idx = io_dis_uops_0_bits_rob_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_ldq_idx = io_dis_uops_0_bits_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_stq_idx = io_dis_uops_0_bits_stq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_rxq_idx = io_dis_uops_0_bits_rxq_idx_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_pdst = io_dis_uops_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_prs1 = io_dis_uops_0_bits_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_prs2 = io_dis_uops_0_bits_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_prs3 = io_dis_uops_0_bits_prs3_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_prs2_busy = io_dis_uops_0_bits_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_prs3_busy = io_dis_uops_0_bits_prs3_busy_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_stale_pdst = io_dis_uops_0_bits_stale_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_exception = io_dis_uops_0_bits_exception_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_7_in_uop_bits_exc_cause = io_dis_uops_0_bits_exc_cause_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_bypassable = io_dis_uops_0_bits_bypassable_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_in_uop_bits_mem_cmd = io_dis_uops_0_bits_mem_cmd_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_mem_size = io_dis_uops_0_bits_mem_size_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_mem_signed = io_dis_uops_0_bits_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_fence = io_dis_uops_0_bits_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_fencei = io_dis_uops_0_bits_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_amo = io_dis_uops_0_bits_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_uses_ldq = io_dis_uops_0_bits_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_uses_stq = io_dis_uops_0_bits_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_sys_pc2epc = io_dis_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_unique = io_dis_uops_0_bits_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_flush_on_commit = io_dis_uops_0_bits_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ldst_is_rs1 = io_dis_uops_0_bits_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_ldst = io_dis_uops_0_bits_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_lrs1 = io_dis_uops_0_bits_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_lrs2 = io_dis_uops_0_bits_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_lrs3 = io_dis_uops_0_bits_lrs3_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ldst_val = io_dis_uops_0_bits_ldst_val_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_dst_rtype = io_dis_uops_0_bits_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_lrs2_rtype = io_dis_uops_0_bits_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_frs3_en = io_dis_uops_0_bits_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_fp_val = io_dis_uops_0_bits_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_fp_single = io_dis_uops_0_bits_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_xcpt_pf_if = io_dis_uops_0_bits_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_xcpt_ae_if = io_dis_uops_0_bits_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_xcpt_ma_if = io_dis_uops_0_bits_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_bp_debug_if = io_dis_uops_0_bits_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_bp_xcpt_if = io_dis_uops_0_bits_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_debug_fsrc = io_dis_uops_0_bits_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_debug_tsrc = io_dis_uops_0_bits_debug_tsrc_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_0_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_1_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_2_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_3_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_4_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_5_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_6_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_7_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_0_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_1_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_2_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_3_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_4_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_5_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_6_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_7_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_0_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_1_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_2_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_3_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_4_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_5_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_6_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_7_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_0_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_1_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_2_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_3_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_4_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_5_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_6_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_7_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_0_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_1_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_2_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_3_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_4_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_5_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_6_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_7_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_0_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_1_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_2_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_3_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_4_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_5_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_6_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_7_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_0_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_1_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_2_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_3_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_4_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_5_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_6_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_7_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_0_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_1_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_2_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_3_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_4_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_5_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_6_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_7_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_0_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_1_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_2_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_3_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_4_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_5_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_6_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_7_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_0_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_1_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_2_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_3_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_4_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_5_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_6_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_7_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire issue_slots_0_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_1_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_2_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_3_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_4_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_5_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_6_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_7_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire _io_event_empty_T_7; // @[issue-unit.scala:165:21] wire io_dis_uops_0_ready_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_valids_0_0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_iss_uops_0_ctrl_br_type_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_ctrl_op1_sel_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_ctrl_op2_sel_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_ctrl_imm_sel_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_0_ctrl_op_fcn_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ctrl_fcn_dw_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_ctrl_csr_cmd_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ctrl_is_load_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ctrl_is_sta_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ctrl_is_std_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_0_uopc_0; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_iss_uops_0_inst_0; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_iss_uops_0_debug_inst_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_rvc_0; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_iss_uops_0_debug_pc_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_iq_type_0; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_iss_uops_0_fu_code_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_iw_state_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_br_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_jalr_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_jal_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_sfb_0; // @[issue-unit-age-ordered.scala:29:7] wire [7:0] io_iss_uops_0_br_mask_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_br_tag_0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_iss_uops_0_ftq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_edge_inst_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_pc_lob_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_taken_0; // @[issue-unit-age-ordered.scala:29:7] wire [19:0] io_iss_uops_0_imm_packed_0; // @[issue-unit-age-ordered.scala:29:7] wire [11:0] io_iss_uops_0_csr_addr_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_0_rob_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_ldq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_stq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_rxq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_pdst_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_prs1_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_prs2_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_prs3_0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_iss_uops_0_ppred_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_prs1_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_prs2_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_prs3_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ppred_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_stale_pdst_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_exception_0; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_iss_uops_0_exc_cause_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_bypassable_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_0_mem_cmd_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_mem_size_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_mem_signed_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_fence_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_fencei_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_amo_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_uses_ldq_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_uses_stq_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_unique_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_flush_on_commit_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_ldst_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_lrs1_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_lrs2_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_lrs3_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ldst_val_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_dst_rtype_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_frs3_en_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_fp_val_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_fp_single_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_bp_debug_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_debug_fsrc_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_debug_tsrc_0; // @[issue-unit-age-ordered.scala:29:7] wire io_event_empty; // @[issue-unit-age-ordered.scala:29:7] wire _T = io_dis_uops_0_bits_uopc_0 == 7'h2; // @[issue-unit.scala:138:38] wire [1:0] issue_slots_7_in_uop_bits_lrs1_rtype = _T ? 2'h2 : io_dis_uops_0_bits_lrs1_rtype_0; // @[issue-unit.scala:120:17, :138:{38,50}, :139:32, :154:28] wire issue_slots_7_in_uop_bits_prs1_busy = ~_T & io_dis_uops_0_bits_prs1_busy_0; // @[issue-unit.scala:120:17, :138:{38,50}, :140:32, :154:28] wire [6:0] issue_slots_1_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_1_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_1_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_1_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_1_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_1_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_1_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire [6:0] issue_slots_2_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_2_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_2_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_2_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_2_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_2_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_2_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_in_uop_bits_uopc = issue_slots_1_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_in_uop_bits_inst = issue_slots_1_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_in_uop_bits_debug_inst = issue_slots_1_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_rvc = issue_slots_1_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_0_in_uop_bits_debug_pc = issue_slots_1_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_iq_type = issue_slots_1_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_0_in_uop_bits_fu_code = issue_slots_1_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_in_uop_bits_ctrl_br_type = issue_slots_1_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_ctrl_op1_sel = issue_slots_1_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_ctrl_op2_sel = issue_slots_1_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_ctrl_imm_sel = issue_slots_1_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_in_uop_bits_ctrl_op_fcn = issue_slots_1_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ctrl_fcn_dw = issue_slots_1_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_ctrl_csr_cmd = issue_slots_1_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ctrl_is_load = issue_slots_1_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ctrl_is_sta = issue_slots_1_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ctrl_is_std = issue_slots_1_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_iw_state = issue_slots_1_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_br = issue_slots_1_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_jalr = issue_slots_1_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_jal = issue_slots_1_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_sfb = issue_slots_1_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_0_in_uop_bits_br_mask = issue_slots_1_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_br_tag = issue_slots_1_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_in_uop_bits_ftq_idx = issue_slots_1_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_edge_inst = issue_slots_1_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_pc_lob = issue_slots_1_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_taken = issue_slots_1_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_0_in_uop_bits_imm_packed = issue_slots_1_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_0_in_uop_bits_csr_addr = issue_slots_1_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_in_uop_bits_rob_idx = issue_slots_1_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_ldq_idx = issue_slots_1_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_stq_idx = issue_slots_1_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_rxq_idx = issue_slots_1_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_pdst = issue_slots_1_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_prs1 = issue_slots_1_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_prs2 = issue_slots_1_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_prs3 = issue_slots_1_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_in_uop_bits_ppred = issue_slots_1_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_prs1_busy = issue_slots_1_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_prs2_busy = issue_slots_1_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_prs3_busy = issue_slots_1_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ppred_busy = issue_slots_1_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_stale_pdst = issue_slots_1_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_exception = issue_slots_1_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_0_in_uop_bits_exc_cause = issue_slots_1_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_bypassable = issue_slots_1_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_in_uop_bits_mem_cmd = issue_slots_1_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_mem_size = issue_slots_1_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_mem_signed = issue_slots_1_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_fence = issue_slots_1_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_fencei = issue_slots_1_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_amo = issue_slots_1_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_uses_ldq = issue_slots_1_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_uses_stq = issue_slots_1_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_sys_pc2epc = issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_unique = issue_slots_1_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_flush_on_commit = issue_slots_1_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ldst_is_rs1 = issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_ldst = issue_slots_1_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_lrs1 = issue_slots_1_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_lrs2 = issue_slots_1_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_lrs3 = issue_slots_1_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ldst_val = issue_slots_1_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_dst_rtype = issue_slots_1_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_lrs1_rtype = issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_lrs2_rtype = issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_frs3_en = issue_slots_1_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_fp_val = issue_slots_1_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_fp_single = issue_slots_1_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_xcpt_pf_if = issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_xcpt_ae_if = issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_xcpt_ma_if = issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_bp_debug_if = issue_slots_1_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_bp_xcpt_if = issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_debug_fsrc = issue_slots_1_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_debug_tsrc = issue_slots_1_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire [6:0] issue_slots_3_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_3_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_3_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_3_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_3_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_3_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_3_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_in_uop_bits_uopc = issue_slots_2_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_in_uop_bits_inst = issue_slots_2_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_in_uop_bits_debug_inst = issue_slots_2_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_rvc = issue_slots_2_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_1_in_uop_bits_debug_pc = issue_slots_2_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_iq_type = issue_slots_2_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_1_in_uop_bits_fu_code = issue_slots_2_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_in_uop_bits_ctrl_br_type = issue_slots_2_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_ctrl_op1_sel = issue_slots_2_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_ctrl_op2_sel = issue_slots_2_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_ctrl_imm_sel = issue_slots_2_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_in_uop_bits_ctrl_op_fcn = issue_slots_2_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ctrl_fcn_dw = issue_slots_2_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_ctrl_csr_cmd = issue_slots_2_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ctrl_is_load = issue_slots_2_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ctrl_is_sta = issue_slots_2_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ctrl_is_std = issue_slots_2_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_iw_state = issue_slots_2_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_br = issue_slots_2_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_jalr = issue_slots_2_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_jal = issue_slots_2_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_sfb = issue_slots_2_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_1_in_uop_bits_br_mask = issue_slots_2_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_br_tag = issue_slots_2_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_in_uop_bits_ftq_idx = issue_slots_2_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_edge_inst = issue_slots_2_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_pc_lob = issue_slots_2_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_taken = issue_slots_2_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_1_in_uop_bits_imm_packed = issue_slots_2_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_1_in_uop_bits_csr_addr = issue_slots_2_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_in_uop_bits_rob_idx = issue_slots_2_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_ldq_idx = issue_slots_2_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_stq_idx = issue_slots_2_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_rxq_idx = issue_slots_2_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_pdst = issue_slots_2_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_prs1 = issue_slots_2_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_prs2 = issue_slots_2_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_prs3 = issue_slots_2_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_in_uop_bits_ppred = issue_slots_2_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_prs1_busy = issue_slots_2_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_prs2_busy = issue_slots_2_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_prs3_busy = issue_slots_2_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ppred_busy = issue_slots_2_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_stale_pdst = issue_slots_2_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_exception = issue_slots_2_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_1_in_uop_bits_exc_cause = issue_slots_2_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_bypassable = issue_slots_2_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_in_uop_bits_mem_cmd = issue_slots_2_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_mem_size = issue_slots_2_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_mem_signed = issue_slots_2_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_fence = issue_slots_2_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_fencei = issue_slots_2_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_amo = issue_slots_2_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_uses_ldq = issue_slots_2_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_uses_stq = issue_slots_2_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_sys_pc2epc = issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_unique = issue_slots_2_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_flush_on_commit = issue_slots_2_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ldst_is_rs1 = issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_ldst = issue_slots_2_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_lrs1 = issue_slots_2_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_lrs2 = issue_slots_2_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_lrs3 = issue_slots_2_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ldst_val = issue_slots_2_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_dst_rtype = issue_slots_2_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_lrs1_rtype = issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_lrs2_rtype = issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_frs3_en = issue_slots_2_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_fp_val = issue_slots_2_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_fp_single = issue_slots_2_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_xcpt_pf_if = issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_xcpt_ae_if = issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_xcpt_ma_if = issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_bp_debug_if = issue_slots_2_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_bp_xcpt_if = issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_debug_fsrc = issue_slots_2_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_debug_tsrc = issue_slots_2_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire [6:0] issue_slots_4_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_4_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_4_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_4_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_4_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_4_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_4_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_in_uop_bits_uopc = issue_slots_3_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_in_uop_bits_inst = issue_slots_3_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_in_uop_bits_debug_inst = issue_slots_3_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_rvc = issue_slots_3_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_2_in_uop_bits_debug_pc = issue_slots_3_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_iq_type = issue_slots_3_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_2_in_uop_bits_fu_code = issue_slots_3_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_in_uop_bits_ctrl_br_type = issue_slots_3_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_ctrl_op1_sel = issue_slots_3_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_ctrl_op2_sel = issue_slots_3_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_ctrl_imm_sel = issue_slots_3_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_in_uop_bits_ctrl_op_fcn = issue_slots_3_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ctrl_fcn_dw = issue_slots_3_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_ctrl_csr_cmd = issue_slots_3_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ctrl_is_load = issue_slots_3_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ctrl_is_sta = issue_slots_3_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ctrl_is_std = issue_slots_3_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_iw_state = issue_slots_3_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_br = issue_slots_3_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_jalr = issue_slots_3_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_jal = issue_slots_3_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_sfb = issue_slots_3_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_2_in_uop_bits_br_mask = issue_slots_3_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_br_tag = issue_slots_3_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_in_uop_bits_ftq_idx = issue_slots_3_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_edge_inst = issue_slots_3_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_pc_lob = issue_slots_3_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_taken = issue_slots_3_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_2_in_uop_bits_imm_packed = issue_slots_3_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_2_in_uop_bits_csr_addr = issue_slots_3_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_in_uop_bits_rob_idx = issue_slots_3_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_ldq_idx = issue_slots_3_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_stq_idx = issue_slots_3_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_rxq_idx = issue_slots_3_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_pdst = issue_slots_3_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_prs1 = issue_slots_3_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_prs2 = issue_slots_3_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_prs3 = issue_slots_3_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_in_uop_bits_ppred = issue_slots_3_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_prs1_busy = issue_slots_3_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_prs2_busy = issue_slots_3_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_prs3_busy = issue_slots_3_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ppred_busy = issue_slots_3_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_stale_pdst = issue_slots_3_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_exception = issue_slots_3_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_2_in_uop_bits_exc_cause = issue_slots_3_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_bypassable = issue_slots_3_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_in_uop_bits_mem_cmd = issue_slots_3_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_mem_size = issue_slots_3_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_mem_signed = issue_slots_3_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_fence = issue_slots_3_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_fencei = issue_slots_3_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_amo = issue_slots_3_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_uses_ldq = issue_slots_3_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_uses_stq = issue_slots_3_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_sys_pc2epc = issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_unique = issue_slots_3_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_flush_on_commit = issue_slots_3_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ldst_is_rs1 = issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_ldst = issue_slots_3_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_lrs1 = issue_slots_3_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_lrs2 = issue_slots_3_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_lrs3 = issue_slots_3_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ldst_val = issue_slots_3_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_dst_rtype = issue_slots_3_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_lrs1_rtype = issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_lrs2_rtype = issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_frs3_en = issue_slots_3_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_fp_val = issue_slots_3_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_fp_single = issue_slots_3_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_xcpt_pf_if = issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_xcpt_ae_if = issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_xcpt_ma_if = issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_bp_debug_if = issue_slots_3_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_bp_xcpt_if = issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_debug_fsrc = issue_slots_3_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_debug_tsrc = issue_slots_3_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire [6:0] issue_slots_5_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_5_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_5_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_5_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_5_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_5_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_5_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_in_uop_bits_uopc = issue_slots_4_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_in_uop_bits_inst = issue_slots_4_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_in_uop_bits_debug_inst = issue_slots_4_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_rvc = issue_slots_4_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_3_in_uop_bits_debug_pc = issue_slots_4_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_iq_type = issue_slots_4_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_3_in_uop_bits_fu_code = issue_slots_4_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_in_uop_bits_ctrl_br_type = issue_slots_4_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_ctrl_op1_sel = issue_slots_4_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_ctrl_op2_sel = issue_slots_4_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_ctrl_imm_sel = issue_slots_4_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_in_uop_bits_ctrl_op_fcn = issue_slots_4_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ctrl_fcn_dw = issue_slots_4_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_ctrl_csr_cmd = issue_slots_4_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ctrl_is_load = issue_slots_4_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ctrl_is_sta = issue_slots_4_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ctrl_is_std = issue_slots_4_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_iw_state = issue_slots_4_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_br = issue_slots_4_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_jalr = issue_slots_4_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_jal = issue_slots_4_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_sfb = issue_slots_4_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_3_in_uop_bits_br_mask = issue_slots_4_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_br_tag = issue_slots_4_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_in_uop_bits_ftq_idx = issue_slots_4_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_edge_inst = issue_slots_4_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_pc_lob = issue_slots_4_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_taken = issue_slots_4_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_3_in_uop_bits_imm_packed = issue_slots_4_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_3_in_uop_bits_csr_addr = issue_slots_4_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_in_uop_bits_rob_idx = issue_slots_4_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_ldq_idx = issue_slots_4_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_stq_idx = issue_slots_4_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_rxq_idx = issue_slots_4_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_pdst = issue_slots_4_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_prs1 = issue_slots_4_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_prs2 = issue_slots_4_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_prs3 = issue_slots_4_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_in_uop_bits_ppred = issue_slots_4_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_prs1_busy = issue_slots_4_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_prs2_busy = issue_slots_4_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_prs3_busy = issue_slots_4_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ppred_busy = issue_slots_4_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_stale_pdst = issue_slots_4_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_exception = issue_slots_4_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_3_in_uop_bits_exc_cause = issue_slots_4_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_bypassable = issue_slots_4_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_in_uop_bits_mem_cmd = issue_slots_4_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_mem_size = issue_slots_4_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_mem_signed = issue_slots_4_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_fence = issue_slots_4_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_fencei = issue_slots_4_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_amo = issue_slots_4_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_uses_ldq = issue_slots_4_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_uses_stq = issue_slots_4_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_sys_pc2epc = issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_unique = issue_slots_4_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_flush_on_commit = issue_slots_4_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ldst_is_rs1 = issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_ldst = issue_slots_4_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_lrs1 = issue_slots_4_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_lrs2 = issue_slots_4_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_lrs3 = issue_slots_4_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ldst_val = issue_slots_4_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_dst_rtype = issue_slots_4_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_lrs1_rtype = issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_lrs2_rtype = issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_frs3_en = issue_slots_4_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_fp_val = issue_slots_4_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_fp_single = issue_slots_4_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_xcpt_pf_if = issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_xcpt_ae_if = issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_xcpt_ma_if = issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_bp_debug_if = issue_slots_4_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_bp_xcpt_if = issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_debug_fsrc = issue_slots_4_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_debug_tsrc = issue_slots_4_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire [6:0] issue_slots_6_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_6_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_6_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_6_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_6_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_6_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_6_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_in_uop_bits_uopc = issue_slots_5_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_in_uop_bits_inst = issue_slots_5_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_in_uop_bits_debug_inst = issue_slots_5_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_rvc = issue_slots_5_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_4_in_uop_bits_debug_pc = issue_slots_5_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_iq_type = issue_slots_5_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_4_in_uop_bits_fu_code = issue_slots_5_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_in_uop_bits_ctrl_br_type = issue_slots_5_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_ctrl_op1_sel = issue_slots_5_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_ctrl_op2_sel = issue_slots_5_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_ctrl_imm_sel = issue_slots_5_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_in_uop_bits_ctrl_op_fcn = issue_slots_5_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ctrl_fcn_dw = issue_slots_5_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_ctrl_csr_cmd = issue_slots_5_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ctrl_is_load = issue_slots_5_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ctrl_is_sta = issue_slots_5_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ctrl_is_std = issue_slots_5_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_iw_state = issue_slots_5_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_br = issue_slots_5_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_jalr = issue_slots_5_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_jal = issue_slots_5_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_sfb = issue_slots_5_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_4_in_uop_bits_br_mask = issue_slots_5_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_br_tag = issue_slots_5_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_in_uop_bits_ftq_idx = issue_slots_5_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_edge_inst = issue_slots_5_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_pc_lob = issue_slots_5_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_taken = issue_slots_5_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_4_in_uop_bits_imm_packed = issue_slots_5_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_4_in_uop_bits_csr_addr = issue_slots_5_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_in_uop_bits_rob_idx = issue_slots_5_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_ldq_idx = issue_slots_5_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_stq_idx = issue_slots_5_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_rxq_idx = issue_slots_5_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_pdst = issue_slots_5_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_prs1 = issue_slots_5_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_prs2 = issue_slots_5_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_prs3 = issue_slots_5_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_in_uop_bits_ppred = issue_slots_5_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_prs1_busy = issue_slots_5_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_prs2_busy = issue_slots_5_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_prs3_busy = issue_slots_5_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ppred_busy = issue_slots_5_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_stale_pdst = issue_slots_5_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_exception = issue_slots_5_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_4_in_uop_bits_exc_cause = issue_slots_5_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_bypassable = issue_slots_5_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_in_uop_bits_mem_cmd = issue_slots_5_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_mem_size = issue_slots_5_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_mem_signed = issue_slots_5_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_fence = issue_slots_5_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_fencei = issue_slots_5_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_amo = issue_slots_5_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_uses_ldq = issue_slots_5_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_uses_stq = issue_slots_5_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_sys_pc2epc = issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_unique = issue_slots_5_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_flush_on_commit = issue_slots_5_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ldst_is_rs1 = issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_ldst = issue_slots_5_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_lrs1 = issue_slots_5_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_lrs2 = issue_slots_5_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_lrs3 = issue_slots_5_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ldst_val = issue_slots_5_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_dst_rtype = issue_slots_5_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_lrs1_rtype = issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_lrs2_rtype = issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_frs3_en = issue_slots_5_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_fp_val = issue_slots_5_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_fp_single = issue_slots_5_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_xcpt_pf_if = issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_xcpt_ae_if = issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_xcpt_ma_if = issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_bp_debug_if = issue_slots_5_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_bp_xcpt_if = issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_debug_fsrc = issue_slots_5_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_debug_tsrc = issue_slots_5_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire [6:0] issue_slots_7_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_7_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_7_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_7_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_7_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_7_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_prs3; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_7_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_in_uop_bits_uopc = issue_slots_6_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_in_uop_bits_inst = issue_slots_6_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_in_uop_bits_debug_inst = issue_slots_6_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_rvc = issue_slots_6_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_5_in_uop_bits_debug_pc = issue_slots_6_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_iq_type = issue_slots_6_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_5_in_uop_bits_fu_code = issue_slots_6_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_in_uop_bits_ctrl_br_type = issue_slots_6_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_ctrl_op1_sel = issue_slots_6_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_ctrl_op2_sel = issue_slots_6_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_ctrl_imm_sel = issue_slots_6_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_in_uop_bits_ctrl_op_fcn = issue_slots_6_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ctrl_fcn_dw = issue_slots_6_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_ctrl_csr_cmd = issue_slots_6_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ctrl_is_load = issue_slots_6_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ctrl_is_sta = issue_slots_6_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ctrl_is_std = issue_slots_6_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_iw_state = issue_slots_6_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_br = issue_slots_6_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_jalr = issue_slots_6_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_jal = issue_slots_6_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_sfb = issue_slots_6_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_5_in_uop_bits_br_mask = issue_slots_6_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_br_tag = issue_slots_6_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_in_uop_bits_ftq_idx = issue_slots_6_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_edge_inst = issue_slots_6_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_pc_lob = issue_slots_6_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_taken = issue_slots_6_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_5_in_uop_bits_imm_packed = issue_slots_6_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_5_in_uop_bits_csr_addr = issue_slots_6_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_in_uop_bits_rob_idx = issue_slots_6_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_ldq_idx = issue_slots_6_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_stq_idx = issue_slots_6_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_rxq_idx = issue_slots_6_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_pdst = issue_slots_6_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_prs1 = issue_slots_6_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_prs2 = issue_slots_6_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_prs3 = issue_slots_6_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_in_uop_bits_ppred = issue_slots_6_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_prs1_busy = issue_slots_6_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_prs2_busy = issue_slots_6_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_prs3_busy = issue_slots_6_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ppred_busy = issue_slots_6_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_stale_pdst = issue_slots_6_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_exception = issue_slots_6_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_5_in_uop_bits_exc_cause = issue_slots_6_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_bypassable = issue_slots_6_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_in_uop_bits_mem_cmd = issue_slots_6_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_mem_size = issue_slots_6_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_mem_signed = issue_slots_6_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_fence = issue_slots_6_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_fencei = issue_slots_6_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_amo = issue_slots_6_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_uses_ldq = issue_slots_6_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_uses_stq = issue_slots_6_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_sys_pc2epc = issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_unique = issue_slots_6_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_flush_on_commit = issue_slots_6_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ldst_is_rs1 = issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_ldst = issue_slots_6_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_lrs1 = issue_slots_6_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_lrs2 = issue_slots_6_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_lrs3 = issue_slots_6_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ldst_val = issue_slots_6_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_dst_rtype = issue_slots_6_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_lrs1_rtype = issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_lrs2_rtype = issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_frs3_en = issue_slots_6_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_fp_val = issue_slots_6_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_fp_single = issue_slots_6_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_xcpt_pf_if = issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_xcpt_ae_if = issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_xcpt_ma_if = issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_bp_debug_if = issue_slots_6_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_bp_xcpt_if = issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_debug_fsrc = issue_slots_6_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_debug_tsrc = issue_slots_6_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire [6:0] issue_slots_6_in_uop_bits_uopc = issue_slots_7_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_in_uop_bits_inst = issue_slots_7_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_in_uop_bits_debug_inst = issue_slots_7_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_rvc = issue_slots_7_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_6_in_uop_bits_debug_pc = issue_slots_7_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_iq_type = issue_slots_7_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_6_in_uop_bits_fu_code = issue_slots_7_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_in_uop_bits_ctrl_br_type = issue_slots_7_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_ctrl_op1_sel = issue_slots_7_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_ctrl_op2_sel = issue_slots_7_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_ctrl_imm_sel = issue_slots_7_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_in_uop_bits_ctrl_op_fcn = issue_slots_7_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ctrl_fcn_dw = issue_slots_7_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_ctrl_csr_cmd = issue_slots_7_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ctrl_is_load = issue_slots_7_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ctrl_is_sta = issue_slots_7_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ctrl_is_std = issue_slots_7_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_iw_state = issue_slots_7_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_br = issue_slots_7_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_jalr = issue_slots_7_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_jal = issue_slots_7_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_sfb = issue_slots_7_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_6_in_uop_bits_br_mask = issue_slots_7_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_br_tag = issue_slots_7_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_in_uop_bits_ftq_idx = issue_slots_7_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_edge_inst = issue_slots_7_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_pc_lob = issue_slots_7_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_taken = issue_slots_7_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_6_in_uop_bits_imm_packed = issue_slots_7_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_6_in_uop_bits_csr_addr = issue_slots_7_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_in_uop_bits_rob_idx = issue_slots_7_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_ldq_idx = issue_slots_7_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_stq_idx = issue_slots_7_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_rxq_idx = issue_slots_7_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_pdst = issue_slots_7_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_prs1 = issue_slots_7_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_prs2 = issue_slots_7_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_prs3 = issue_slots_7_out_uop_prs3; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_prs1_busy = issue_slots_7_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_prs2_busy = issue_slots_7_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_prs3_busy = issue_slots_7_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ppred_busy = issue_slots_7_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_stale_pdst = issue_slots_7_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_exception = issue_slots_7_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_6_in_uop_bits_exc_cause = issue_slots_7_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_bypassable = issue_slots_7_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_in_uop_bits_mem_cmd = issue_slots_7_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_mem_size = issue_slots_7_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_mem_signed = issue_slots_7_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_fence = issue_slots_7_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_fencei = issue_slots_7_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_amo = issue_slots_7_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_uses_ldq = issue_slots_7_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_uses_stq = issue_slots_7_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_sys_pc2epc = issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_unique = issue_slots_7_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_flush_on_commit = issue_slots_7_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ldst_is_rs1 = issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_ldst = issue_slots_7_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_lrs1 = issue_slots_7_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_lrs2 = issue_slots_7_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_lrs3 = issue_slots_7_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ldst_val = issue_slots_7_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_dst_rtype = issue_slots_7_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_lrs1_rtype = issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_lrs2_rtype = issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_frs3_en = issue_slots_7_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_fp_val = issue_slots_7_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_fp_single = issue_slots_7_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_xcpt_pf_if = issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_xcpt_ae_if = issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_xcpt_ma_if = issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_bp_debug_if = issue_slots_7_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_bp_xcpt_if = issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_debug_fsrc = issue_slots_7_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_debug_tsrc = issue_slots_7_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_0_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_0_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_0_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_0_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_0_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_0_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_0_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_0_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_0_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_0_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_0_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_0_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_0_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_0_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_0_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_0_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_0_valid; // @[issue-unit.scala:154:28] wire issue_slots_0_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_0_request; // @[issue-unit.scala:154:28] wire issue_slots_0_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_0_grant; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_1_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_1_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_1_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_1_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_1_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_1_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_1_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_1_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_1_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_1_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_1_valid; // @[issue-unit.scala:154:28] wire issue_slots_1_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_1_request; // @[issue-unit.scala:154:28] wire issue_slots_1_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_1_grant; // @[issue-unit.scala:154:28] wire issue_slots_1_clear; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_2_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_2_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_2_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_2_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_2_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_2_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_2_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_2_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_2_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_2_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_2_valid; // @[issue-unit.scala:154:28] wire issue_slots_2_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_2_request; // @[issue-unit.scala:154:28] wire issue_slots_2_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_2_grant; // @[issue-unit.scala:154:28] wire issue_slots_2_clear; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_3_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_3_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_3_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_3_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_3_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_3_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_3_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_3_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_3_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_3_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_3_valid; // @[issue-unit.scala:154:28] wire issue_slots_3_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_3_request; // @[issue-unit.scala:154:28] wire issue_slots_3_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_3_grant; // @[issue-unit.scala:154:28] wire issue_slots_3_clear; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_4_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_4_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_4_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_4_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_4_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_4_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_4_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_4_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_4_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_4_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_4_valid; // @[issue-unit.scala:154:28] wire issue_slots_4_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_4_request; // @[issue-unit.scala:154:28] wire issue_slots_4_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_4_grant; // @[issue-unit.scala:154:28] wire issue_slots_4_clear; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_5_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_5_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_5_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_5_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_5_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_5_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_5_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_5_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_5_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_5_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_5_valid; // @[issue-unit.scala:154:28] wire issue_slots_5_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_5_request; // @[issue-unit.scala:154:28] wire issue_slots_5_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_5_grant; // @[issue-unit.scala:154:28] wire issue_slots_5_clear; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_6_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_6_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_6_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_6_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_6_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_prs3; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_6_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_6_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_6_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_6_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_6_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_6_valid; // @[issue-unit.scala:154:28] wire issue_slots_6_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_6_request; // @[issue-unit.scala:154:28] wire issue_slots_6_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_6_grant; // @[issue-unit.scala:154:28] wire issue_slots_6_clear; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_7_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_7_uop_fu_code; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_sfb; // @[issue-unit.scala:154:28] wire [7:0] issue_slots_7_uop_br_mask; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_br_tag; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_7_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_7_uop_csr_addr; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_uop_rob_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_pdst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_prs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_prs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_prs3; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_prs3_busy; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_7_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_7_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_7_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_7_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_7_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_7_valid; // @[issue-unit.scala:154:28] wire issue_slots_7_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_7_request; // @[issue-unit.scala:154:28] wire issue_slots_7_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_7_grant; // @[issue-unit.scala:154:28] wire issue_slots_7_clear; // @[issue-unit.scala:154:28] wire _io_event_empty_T = issue_slots_0_valid \| issue_slots_1_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_1 = _io_event_empty_T \| issue_slots_2_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_2 = _io_event_empty_T_1 \| issue_slots_3_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_3 = _io_event_empty_T_2 \| issue_slots_4_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_4 = _io_event_empty_T_3 \| issue_slots_5_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_5 = _io_event_empty_T_4 \| issue_slots_6_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_6 = _io_event_empty_T_5 \| issue_slots_7_valid; // @[issue-unit.scala:154:28, :165:61] assign _io_event_empty_T_7 = ~_io_event_empty_T_6; // @[issue-unit.scala:165:{21,61}] assign io_event_empty = _io_event_empty_T_7; // @[issue-unit.scala:165:21] wire [1:0] _count_T = {1'h0, _slots_0_io_valid} + {1'h0, _slots_1_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_1 = _count_T; // @[issue-unit.scala:167:23] wire [1:0] _count_T_2 = {1'h0, _slots_2_io_valid} + {1'h0, _slots_3_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_3 = _count_T_2; // @[issue-unit.scala:167:23] wire [2:0] _count_T_4 = {1'h0, _count_T_1} + {1'h0, _count_T_3}; // @[issue-unit.scala:167:23] wire [2:0] _count_T_5 = _count_T_4; // @[issue-unit.scala:167:23] wire [1:0] _count_T_6 = {1'h0, _slots_4_io_valid} + {1'h0, _slots_5_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_7 = _count_T_6; // @[issue-unit.scala:167:23] wire [1:0] _count_T_8 = {1'h0, _slots_6_io_valid} + {1'h0, _slots_7_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_9 = _count_T_8; // @[issue-unit.scala:167:23] wire [2:0] _count_T_10 = {1'h0, _count_T_7} + {1'h0, _count_T_9}; // @[issue-unit.scala:167:23] wire [2:0] _count_T_11 = _count_T_10; // @[issue-unit.scala:167:23] wire [3:0] _count_T_12 = {1'h0, _count_T_5} + {1'h0, _count_T_11}; // @[issue-unit.scala:167:23] wire [3:0] count = _count_T_12; // @[issue-unit.scala:167:23]
Generate the Verilog code corresponding to this FIRRTL code module Tile_80 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_336 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_80( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_336 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BoomFrontend_1 : input clock : Clock input reset : Reset output auto : { icache_master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip reset_vector_sink_in : UInt<32>} output io : { flip cpu : { flip fetchpacket : { flip ready : UInt<1>, valid : UInt<1>, bits : { uops : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}[1]}}, flip get_pc : { flip ftq_idx : UInt<4>, entry : { cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_type : UInt<3>, br_mask : UInt<4>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ras_idx : UInt<5>, start_bank : UInt<1>}, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, pc : UInt<40>, com_pc : UInt<40>, next_val : UInt<1>, next_pc : UInt<40>}[2], debug_ftq_idx : UInt<4>[1], flip debug_fetch_pc : UInt<40>[1], status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], mcontext : UInt<0>, scontext : UInt<0>, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, redirect_flush : UInt<1>, redirect_val : UInt<1>, redirect_pc : UInt, redirect_ftq_idx : UInt, redirect_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, commit : { valid : UInt<1>, bits : UInt<16>}, flush_icache : UInt<1>, flip perf : { acquire : UInt<1>, tlbMiss : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[2]}}} inst icache of ICache_1 connect icache.clock, clock connect icache.reset, reset wire resetVectorSinkNodeIn : UInt<32> invalidate resetVectorSinkNodeIn connect resetVectorSinkNodeIn, auto.reset_vector_sink_in connect icache.auto.master_out.d, auto.icache_master_out.d connect auto.icache_master_out.a.bits, icache.auto.master_out.a.bits connect auto.icache_master_out.a.valid, icache.auto.master_out.a.valid connect icache.auto.master_out.a.ready, auto.icache_master_out.a.ready inst bpd of BranchPredictor_1 connect bpd.clock, clock connect bpd.reset, reset connect bpd.io.f3_fire, UInt<1>(0h0) inst ras of BoomRAS_1 connect ras.clock, clock connect ras.reset, reset connect icache.io.invalidate, io.cpu.flush_icache inst tlb of ITLB_1 connect tlb.clock, clock connect tlb.reset, reset connect tlb.io.ptw.customCSRs, io.ptw.customCSRs connect tlb.io.ptw.pmp[0], io.ptw.pmp[0] connect tlb.io.ptw.pmp[1], io.ptw.pmp[1] connect tlb.io.ptw.pmp[2], io.ptw.pmp[2] connect tlb.io.ptw.pmp[3], io.ptw.pmp[3] connect tlb.io.ptw.pmp[4], io.ptw.pmp[4] connect tlb.io.ptw.pmp[5], io.ptw.pmp[5] connect tlb.io.ptw.pmp[6], io.ptw.pmp[6] connect tlb.io.ptw.pmp[7], io.ptw.pmp[7] connect tlb.io.ptw.gstatus, io.ptw.gstatus connect tlb.io.ptw.hstatus, io.ptw.hstatus connect tlb.io.ptw.status, io.ptw.status connect tlb.io.ptw.vsatp, io.ptw.vsatp connect tlb.io.ptw.hgatp, io.ptw.hgatp connect tlb.io.ptw.ptbr, io.ptw.ptbr connect tlb.io.ptw.resp, io.ptw.resp connect io.ptw.req.bits, tlb.io.ptw.req.bits connect io.ptw.req.valid, tlb.io.ptw.req.valid connect tlb.io.ptw.req.ready, io.ptw.req.ready node _io_cpu_perf_tlbMiss_T = and(io.ptw.req.ready, io.ptw.req.valid) connect io.cpu.perf.tlbMiss, _io_cpu_perf_tlbMiss_T connect io.cpu.perf.acquire, icache.io.perf.acquire wire s0_vpc : UInt<40> connect s0_vpc, UInt<40>(0h0) wire _s0_ghist_WIRE : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} connect _s0_ghist_WIRE.ras_idx, UInt<5>(0h0) connect _s0_ghist_WIRE.new_saw_branch_taken, UInt<1>(0h0) connect _s0_ghist_WIRE.new_saw_branch_not_taken, UInt<1>(0h0) connect _s0_ghist_WIRE.current_saw_branch_not_taken, UInt<1>(0h0) connect _s0_ghist_WIRE.old_history, UInt<64>(0h0) wire s0_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} connect s0_ghist, _s0_ghist_WIRE wire s0_tsrc : UInt<2> connect s0_tsrc, UInt<2>(0h0) wire s0_valid : UInt<1> connect s0_valid, UInt<1>(0h0) wire s0_is_replay : UInt<1> connect s0_is_replay, UInt<1>(0h0) wire s0_is_sfence : UInt<1> connect s0_is_sfence, UInt<1>(0h0) wire s0_replay_resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>} wire s0_replay_bpd_resp : { pc : UInt<40>, preds : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], meta : UInt<120>[1], lhist : UInt<1>[1]} wire s0_replay_ppc : UInt wire s0_s1_use_f3_bpd_resp : UInt<1> connect s0_s1_use_f3_bpd_resp, UInt<1>(0h0) node _T = asUInt(reset) reg REG : UInt<1>, clock connect REG, _T node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = and(REG, _T_2) when _T_3 : connect s0_valid, UInt<1>(0h1) connect s0_vpc, resetVectorSinkNodeIn wire _s0_ghist_WIRE_1 : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} connect _s0_ghist_WIRE_1.ras_idx, UInt<5>(0h0) connect _s0_ghist_WIRE_1.new_saw_branch_taken, UInt<1>(0h0) connect _s0_ghist_WIRE_1.new_saw_branch_not_taken, UInt<1>(0h0) connect _s0_ghist_WIRE_1.current_saw_branch_not_taken, UInt<1>(0h0) connect _s0_ghist_WIRE_1.old_history, UInt<64>(0h0) connect s0_ghist, _s0_ghist_WIRE_1 connect s0_tsrc, UInt<2>(0h3) connect icache.io.req.valid, s0_valid connect icache.io.req.bits.addr, s0_vpc connect bpd.io.f0_req.valid, s0_valid connect bpd.io.f0_req.bits.pc, s0_vpc connect bpd.io.f0_req.bits.ghist.ras_idx, s0_ghist.ras_idx connect bpd.io.f0_req.bits.ghist.new_saw_branch_taken, s0_ghist.new_saw_branch_taken connect bpd.io.f0_req.bits.ghist.new_saw_branch_not_taken, s0_ghist.new_saw_branch_not_taken connect bpd.io.f0_req.bits.ghist.current_saw_branch_not_taken, s0_ghist.current_saw_branch_not_taken connect bpd.io.f0_req.bits.ghist.old_history, s0_ghist.old_history reg s1_vpc : UInt, clock connect s1_vpc, s0_vpc regreset s1_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect s1_valid, s0_valid reg s1_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, clock connect s1_ghist, s0_ghist reg s1_is_replay : UInt<1>, clock connect s1_is_replay, s0_is_replay reg s1_is_sfence : UInt<1>, clock connect s1_is_sfence, s0_is_sfence wire f1_clear : UInt<1> connect f1_clear, UInt<1>(0h0) reg s1_tsrc : UInt, clock connect s1_tsrc, s0_tsrc node _tlb_io_req_valid_T = eq(s1_is_replay, UInt<1>(0h0)) node _tlb_io_req_valid_T_1 = and(s1_valid, _tlb_io_req_valid_T) node _tlb_io_req_valid_T_2 = eq(f1_clear, UInt<1>(0h0)) node _tlb_io_req_valid_T_3 = and(_tlb_io_req_valid_T_1, _tlb_io_req_valid_T_2) node _tlb_io_req_valid_T_4 = or(_tlb_io_req_valid_T_3, s1_is_sfence) connect tlb.io.req.valid, _tlb_io_req_valid_T_4 invalidate tlb.io.req.bits.cmd connect tlb.io.req.bits.vaddr, s1_vpc connect tlb.io.req.bits.passthrough, UInt<1>(0h0) connect tlb.io.req.bits.size, UInt<2>(0h3) connect tlb.io.req.bits.v, io.ptw.status.v connect tlb.io.req.bits.prv, io.ptw.status.prv reg tlb_io_sfence_REG : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, clock connect tlb_io_sfence_REG, io.cpu.sfence connect tlb.io.sfence.bits.hg, tlb_io_sfence_REG.bits.hg connect tlb.io.sfence.bits.hv, tlb_io_sfence_REG.bits.hv connect tlb.io.sfence.bits.asid, tlb_io_sfence_REG.bits.asid connect tlb.io.sfence.bits.addr, tlb_io_sfence_REG.bits.addr connect tlb.io.sfence.bits.rs2, tlb_io_sfence_REG.bits.rs2 connect tlb.io.sfence.bits.rs1, tlb_io_sfence_REG.bits.rs1 connect tlb.io.sfence.valid, tlb_io_sfence_REG.valid connect tlb.io.kill, UInt<1>(0h0) node _s1_tlb_miss_T = eq(s1_is_replay, UInt<1>(0h0)) node s1_tlb_miss = and(_s1_tlb_miss_T, tlb.io.resp.miss) reg s1_tlb_resp_REG : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, clock connect s1_tlb_resp_REG, s0_replay_resp node s1_tlb_resp = mux(s1_is_replay, s1_tlb_resp_REG, tlb.io.resp) reg s1_ppc_REG : UInt, clock connect s1_ppc_REG, s0_replay_ppc node s1_ppc = mux(s1_is_replay, s1_ppc_REG, tlb.io.resp.paddr) connect icache.io.s1_paddr, s1_ppc node _icache_io_s1_kill_T = or(tlb.io.resp.miss, f1_clear) connect icache.io.s1_kill, _icache_io_s1_kill_T node f1_mask_idx = bits(s1_vpc, 2, 1) node f1_mask = dshl(UInt<4>(0hf), f1_mask_idx) node _f1_redirects_T = bits(f1_mask, 0, 0) node _f1_redirects_T_1 = and(s1_valid, _f1_redirects_T) node _f1_redirects_T_2 = and(_f1_redirects_T_1, bpd.io.resp.f1.preds[0].predicted_pc.valid) node _f1_redirects_T_3 = and(bpd.io.resp.f1.preds[0].is_br, bpd.io.resp.f1.preds[0].taken) node _f1_redirects_T_4 = or(bpd.io.resp.f1.preds[0].is_jal, _f1_redirects_T_3) node f1_redirects_0 = and(_f1_redirects_T_2, _f1_redirects_T_4) node _f1_redirects_T_5 = bits(f1_mask, 1, 1) node _f1_redirects_T_6 = and(s1_valid, _f1_redirects_T_5) node _f1_redirects_T_7 = and(_f1_redirects_T_6, bpd.io.resp.f1.preds[1].predicted_pc.valid) node _f1_redirects_T_8 = and(bpd.io.resp.f1.preds[1].is_br, bpd.io.resp.f1.preds[1].taken) node _f1_redirects_T_9 = or(bpd.io.resp.f1.preds[1].is_jal, _f1_redirects_T_8) node f1_redirects_1 = and(_f1_redirects_T_7, _f1_redirects_T_9) node _f1_redirects_T_10 = bits(f1_mask, 2, 2) node _f1_redirects_T_11 = and(s1_valid, _f1_redirects_T_10) node _f1_redirects_T_12 = and(_f1_redirects_T_11, bpd.io.resp.f1.preds[2].predicted_pc.valid) node _f1_redirects_T_13 = and(bpd.io.resp.f1.preds[2].is_br, bpd.io.resp.f1.preds[2].taken) node _f1_redirects_T_14 = or(bpd.io.resp.f1.preds[2].is_jal, _f1_redirects_T_13) node f1_redirects_2 = and(_f1_redirects_T_12, _f1_redirects_T_14) node _f1_redirects_T_15 = bits(f1_mask, 3, 3) node _f1_redirects_T_16 = and(s1_valid, _f1_redirects_T_15) node _f1_redirects_T_17 = and(_f1_redirects_T_16, bpd.io.resp.f1.preds[3].predicted_pc.valid) node _f1_redirects_T_18 = and(bpd.io.resp.f1.preds[3].is_br, bpd.io.resp.f1.preds[3].taken) node _f1_redirects_T_19 = or(bpd.io.resp.f1.preds[3].is_jal, _f1_redirects_T_18) node f1_redirects_3 = and(_f1_redirects_T_17, _f1_redirects_T_19) node _f1_redirect_idx_T = mux(f1_redirects_2, UInt<2>(0h2), UInt<2>(0h3)) node _f1_redirect_idx_T_1 = mux(f1_redirects_1, UInt<1>(0h1), _f1_redirect_idx_T) node f1_redirect_idx = mux(f1_redirects_0, UInt<1>(0h0), _f1_redirect_idx_T_1) node _f1_do_redirect_T = or(f1_redirects_0, f1_redirects_1) node _f1_do_redirect_T_1 = or(_f1_do_redirect_T, f1_redirects_2) node _f1_do_redirect_T_2 = or(_f1_do_redirect_T_1, f1_redirects_3) node f1_do_redirect = and(_f1_do_redirect_T_2, UInt<1>(0h1)) node _f1_predicted_target_T = eq(f1_redirect_idx, UInt<1>(0h1)) node _f1_predicted_target_T_1 = mux(_f1_predicted_target_T, bpd.io.resp.f1.preds[1].predicted_pc.bits, bpd.io.resp.f1.preds[0].predicted_pc.bits) node _f1_predicted_target_T_2 = eq(f1_redirect_idx, UInt<2>(0h2)) node _f1_predicted_target_T_3 = mux(_f1_predicted_target_T_2, bpd.io.resp.f1.preds[2].predicted_pc.bits, _f1_predicted_target_T_1) node _f1_predicted_target_T_4 = eq(f1_redirect_idx, UInt<2>(0h3)) node _f1_predicted_target_T_5 = mux(_f1_predicted_target_T_4, bpd.io.resp.f1.preds[3].predicted_pc.bits, _f1_predicted_target_T_3) node _f1_predicted_target_T_6 = not(s1_vpc) node _f1_predicted_target_T_7 = or(_f1_predicted_target_T_6, UInt<3>(0h7)) node _f1_predicted_target_T_8 = not(_f1_predicted_target_T_7) node _f1_predicted_target_T_9 = add(_f1_predicted_target_T_8, UInt<4>(0h8)) node _f1_predicted_target_T_10 = tail(_f1_predicted_target_T_9, 1) node f1_predicted_target = mux(f1_do_redirect, _f1_predicted_target_T_5, _f1_predicted_target_T_10) node _f1_predicted_ghist_T = and(bpd.io.resp.f1.preds[0].is_br, bpd.io.resp.f1.preds[0].predicted_pc.valid) node _f1_predicted_ghist_T_1 = and(bpd.io.resp.f1.preds[1].is_br, bpd.io.resp.f1.preds[1].predicted_pc.valid) node _f1_predicted_ghist_T_2 = and(bpd.io.resp.f1.preds[2].is_br, bpd.io.resp.f1.preds[2].predicted_pc.valid) node _f1_predicted_ghist_T_3 = and(bpd.io.resp.f1.preds[3].is_br, bpd.io.resp.f1.preds[3].predicted_pc.valid) node f1_predicted_ghist_lo = cat(_f1_predicted_ghist_T_1, _f1_predicted_ghist_T) node f1_predicted_ghist_hi = cat(_f1_predicted_ghist_T_3, _f1_predicted_ghist_T_2) node _f1_predicted_ghist_T_4 = cat(f1_predicted_ghist_hi, f1_predicted_ghist_lo) node _f1_predicted_ghist_T_5 = and(_f1_predicted_ghist_T_4, f1_mask) node _f1_predicted_ghist_T_6 = and(bpd.io.resp.f1.preds[f1_redirect_idx].taken, f1_do_redirect) node f1_predicted_ghist_cfi_idx_fixed = bits(f1_redirect_idx, 1, 0) node f1_predicted_ghist_cfi_idx_oh = dshl(UInt<1>(0h1), f1_predicted_ghist_cfi_idx_fixed) wire f1_predicted_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} node _f1_predicted_ghist_not_taken_branches_T = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<1>(0h0)) node _f1_predicted_ghist_not_taken_branches_T_1 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<1>(0h1)) node _f1_predicted_ghist_not_taken_branches_T_2 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<2>(0h2)) node _f1_predicted_ghist_not_taken_branches_T_3 = dshr(f1_predicted_ghist_cfi_idx_oh, UInt<2>(0h3)) node _f1_predicted_ghist_not_taken_branches_T_4 = or(_f1_predicted_ghist_not_taken_branches_T, _f1_predicted_ghist_not_taken_branches_T_1) node _f1_predicted_ghist_not_taken_branches_T_5 = or(_f1_predicted_ghist_not_taken_branches_T_4, _f1_predicted_ghist_not_taken_branches_T_2) node _f1_predicted_ghist_not_taken_branches_T_6 = or(_f1_predicted_ghist_not_taken_branches_T_5, _f1_predicted_ghist_not_taken_branches_T_3) node _f1_predicted_ghist_not_taken_branches_T_7 = and(bpd.io.resp.f1.preds[f1_redirect_idx].is_br, _f1_predicted_ghist_T_6) node _f1_predicted_ghist_not_taken_branches_T_8 = mux(_f1_predicted_ghist_not_taken_branches_T_7, f1_predicted_ghist_cfi_idx_oh, UInt<4>(0h0)) node _f1_predicted_ghist_not_taken_branches_T_9 = not(_f1_predicted_ghist_not_taken_branches_T_8) node _f1_predicted_ghist_not_taken_branches_T_10 = and(_f1_predicted_ghist_not_taken_branches_T_6, _f1_predicted_ghist_not_taken_branches_T_9) node _f1_predicted_ghist_not_taken_branches_T_11 = not(UInt<4>(0h0)) node _f1_predicted_ghist_not_taken_branches_T_12 = mux(f1_do_redirect, _f1_predicted_ghist_not_taken_branches_T_10, _f1_predicted_ghist_not_taken_branches_T_11) node f1_predicted_ghist_not_taken_branches = and(_f1_predicted_ghist_T_5, _f1_predicted_ghist_not_taken_branches_T_12) invalidate f1_predicted_ghist.ras_idx invalidate f1_predicted_ghist.new_saw_branch_taken invalidate f1_predicted_ghist.new_saw_branch_not_taken invalidate f1_predicted_ghist.current_saw_branch_not_taken invalidate f1_predicted_ghist.old_history connect f1_predicted_ghist.current_saw_branch_not_taken, UInt<1>(0h0) node _f1_predicted_ghist_saw_not_taken_branch_T = neq(f1_predicted_ghist_not_taken_branches, UInt<1>(0h0)) node f1_predicted_ghist_saw_not_taken_branch = or(_f1_predicted_ghist_saw_not_taken_branch_T, s1_ghist.current_saw_branch_not_taken) node _f1_predicted_ghist_new_history_old_history_T = and(bpd.io.resp.f1.preds[f1_redirect_idx].is_br, _f1_predicted_ghist_T_6) node _f1_predicted_ghist_new_history_old_history_T_1 = and(_f1_predicted_ghist_new_history_old_history_T, f1_do_redirect) node _f1_predicted_ghist_new_history_old_history_T_2 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_3 = or(_f1_predicted_ghist_new_history_old_history_T_2, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_old_history_T_4 = shl(s1_ghist.old_history, 1) node _f1_predicted_ghist_new_history_old_history_T_5 = mux(f1_predicted_ghist_saw_not_taken_branch, _f1_predicted_ghist_new_history_old_history_T_4, s1_ghist.old_history) node _f1_predicted_ghist_new_history_old_history_T_6 = mux(_f1_predicted_ghist_new_history_old_history_T_1, _f1_predicted_ghist_new_history_old_history_T_3, _f1_predicted_ghist_new_history_old_history_T_5) connect f1_predicted_ghist.old_history, _f1_predicted_ghist_new_history_old_history_T_6 node _f1_predicted_ghist_new_history_ras_idx_T = and(f1_do_redirect, UInt<1>(0h0)) node _f1_predicted_ghist_new_history_ras_idx_T_1 = add(s1_ghist.ras_idx, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_ras_idx_T_2 = tail(_f1_predicted_ghist_new_history_ras_idx_T_1, 1) node _f1_predicted_ghist_new_history_ras_idx_T_3 = bits(_f1_predicted_ghist_new_history_ras_idx_T_2, 4, 0) node _f1_predicted_ghist_new_history_ras_idx_T_4 = and(f1_do_redirect, UInt<1>(0h0)) node _f1_predicted_ghist_new_history_ras_idx_T_5 = sub(s1_ghist.ras_idx, UInt<1>(0h1)) node _f1_predicted_ghist_new_history_ras_idx_T_6 = tail(_f1_predicted_ghist_new_history_ras_idx_T_5, 1) node _f1_predicted_ghist_new_history_ras_idx_T_7 = bits(_f1_predicted_ghist_new_history_ras_idx_T_6, 4, 0) node _f1_predicted_ghist_new_history_ras_idx_T_8 = mux(_f1_predicted_ghist_new_history_ras_idx_T_4, _f1_predicted_ghist_new_history_ras_idx_T_7, s1_ghist.ras_idx) node _f1_predicted_ghist_new_history_ras_idx_T_9 = mux(_f1_predicted_ghist_new_history_ras_idx_T, _f1_predicted_ghist_new_history_ras_idx_T_3, _f1_predicted_ghist_new_history_ras_idx_T_8) connect f1_predicted_ghist.ras_idx, _f1_predicted_ghist_new_history_ras_idx_T_9 node _T_4 = eq(s1_tlb_miss, UInt<1>(0h0)) node _T_5 = and(s1_valid, _T_4) when _T_5 : node _s0_valid_T = or(s1_tlb_resp.ae.inst, s1_tlb_resp.pf.inst) node _s0_valid_T_1 = eq(_s0_valid_T, UInt<1>(0h0)) connect s0_valid, _s0_valid_T_1 connect s0_tsrc, UInt<2>(0h0) connect s0_vpc, f1_predicted_target connect s0_ghist, f1_predicted_ghist connect s0_is_replay, UInt<1>(0h0) node _s2_valid_T = eq(f1_clear, UInt<1>(0h0)) node _s2_valid_T_1 = and(s1_valid, _s2_valid_T) regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect s2_valid, _s2_valid_T_1 reg s2_vpc : UInt, clock connect s2_vpc, s1_vpc reg s2_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, clock connect s2_ghist, s1_ghist reg s2_ppc : UInt, clock connect s2_ppc, s1_ppc reg s2_tsrc : UInt, clock connect s2_tsrc, s1_tsrc wire s2_fsrc : UInt<2> connect s2_fsrc, UInt<2>(0h0) wire f2_clear : UInt<1> connect f2_clear, UInt<1>(0h0) reg s2_tlb_resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, clock connect s2_tlb_resp, s1_tlb_resp reg s2_tlb_miss : UInt<1>, clock connect s2_tlb_miss, s1_tlb_miss reg s2_is_replay_REG : UInt<1>, clock connect s2_is_replay_REG, s1_is_replay node s2_is_replay = and(s2_is_replay_REG, s2_valid) node _s2_xcpt_T = or(s2_tlb_resp.ae.inst, s2_tlb_resp.pf.inst) node _s2_xcpt_T_1 = and(s2_valid, _s2_xcpt_T) node _s2_xcpt_T_2 = eq(s2_is_replay, UInt<1>(0h0)) node s2_xcpt = and(_s2_xcpt_T_1, _s2_xcpt_T_2) wire f3_ready : UInt<1> connect icache.io.s2_kill, s2_xcpt node f2_mask_idx = bits(s2_vpc, 2, 1) node f2_mask = dshl(UInt<4>(0hf), f2_mask_idx) node _f2_redirects_T = bits(f2_mask, 0, 0) node _f2_redirects_T_1 = and(s2_valid, _f2_redirects_T) node _f2_redirects_T_2 = and(_f2_redirects_T_1, bpd.io.resp.f2.preds[0].predicted_pc.valid) node _f2_redirects_T_3 = and(bpd.io.resp.f2.preds[0].is_br, bpd.io.resp.f2.preds[0].taken) node _f2_redirects_T_4 = or(bpd.io.resp.f2.preds[0].is_jal, _f2_redirects_T_3) node f2_redirects_0 = and(_f2_redirects_T_2, _f2_redirects_T_4) node _f2_redirects_T_5 = bits(f2_mask, 1, 1) node _f2_redirects_T_6 = and(s2_valid, _f2_redirects_T_5) node _f2_redirects_T_7 = and(_f2_redirects_T_6, bpd.io.resp.f2.preds[1].predicted_pc.valid) node _f2_redirects_T_8 = and(bpd.io.resp.f2.preds[1].is_br, bpd.io.resp.f2.preds[1].taken) node _f2_redirects_T_9 = or(bpd.io.resp.f2.preds[1].is_jal, _f2_redirects_T_8) node f2_redirects_1 = and(_f2_redirects_T_7, _f2_redirects_T_9) node _f2_redirects_T_10 = bits(f2_mask, 2, 2) node _f2_redirects_T_11 = and(s2_valid, _f2_redirects_T_10) node _f2_redirects_T_12 = and(_f2_redirects_T_11, bpd.io.resp.f2.preds[2].predicted_pc.valid) node _f2_redirects_T_13 = and(bpd.io.resp.f2.preds[2].is_br, bpd.io.resp.f2.preds[2].taken) node _f2_redirects_T_14 = or(bpd.io.resp.f2.preds[2].is_jal, _f2_redirects_T_13) node f2_redirects_2 = and(_f2_redirects_T_12, _f2_redirects_T_14) node _f2_redirects_T_15 = bits(f2_mask, 3, 3) node _f2_redirects_T_16 = and(s2_valid, _f2_redirects_T_15) node _f2_redirects_T_17 = and(_f2_redirects_T_16, bpd.io.resp.f2.preds[3].predicted_pc.valid) node _f2_redirects_T_18 = and(bpd.io.resp.f2.preds[3].is_br, bpd.io.resp.f2.preds[3].taken) node _f2_redirects_T_19 = or(bpd.io.resp.f2.preds[3].is_jal, _f2_redirects_T_18) node f2_redirects_3 = and(_f2_redirects_T_17, _f2_redirects_T_19) node _f2_redirect_idx_T = mux(f2_redirects_2, UInt<2>(0h2), UInt<2>(0h3)) node _f2_redirect_idx_T_1 = mux(f2_redirects_1, UInt<1>(0h1), _f2_redirect_idx_T) node f2_redirect_idx = mux(f2_redirects_0, UInt<1>(0h0), _f2_redirect_idx_T_1) node _f2_do_redirect_T = or(f2_redirects_0, f2_redirects_1) node _f2_do_redirect_T_1 = or(_f2_do_redirect_T, f2_redirects_2) node _f2_do_redirect_T_2 = or(_f2_do_redirect_T_1, f2_redirects_3) node f2_do_redirect = and(_f2_do_redirect_T_2, UInt<1>(0h1)) node _f2_predicted_target_T = eq(f2_redirect_idx, UInt<1>(0h1)) node _f2_predicted_target_T_1 = mux(_f2_predicted_target_T, bpd.io.resp.f2.preds[1].predicted_pc.bits, bpd.io.resp.f2.preds[0].predicted_pc.bits) node _f2_predicted_target_T_2 = eq(f2_redirect_idx, UInt<2>(0h2)) node _f2_predicted_target_T_3 = mux(_f2_predicted_target_T_2, bpd.io.resp.f2.preds[2].predicted_pc.bits, _f2_predicted_target_T_1) node _f2_predicted_target_T_4 = eq(f2_redirect_idx, UInt<2>(0h3)) node _f2_predicted_target_T_5 = mux(_f2_predicted_target_T_4, bpd.io.resp.f2.preds[3].predicted_pc.bits, _f2_predicted_target_T_3) node _f2_predicted_target_T_6 = not(s2_vpc) node _f2_predicted_target_T_7 = or(_f2_predicted_target_T_6, UInt<3>(0h7)) node _f2_predicted_target_T_8 = not(_f2_predicted_target_T_7) node _f2_predicted_target_T_9 = add(_f2_predicted_target_T_8, UInt<4>(0h8)) node _f2_predicted_target_T_10 = tail(_f2_predicted_target_T_9, 1) node f2_predicted_target = mux(f2_do_redirect, _f2_predicted_target_T_5, _f2_predicted_target_T_10) node _f2_predicted_ghist_T = and(bpd.io.resp.f2.preds[0].is_br, bpd.io.resp.f2.preds[0].predicted_pc.valid) node _f2_predicted_ghist_T_1 = and(bpd.io.resp.f2.preds[1].is_br, bpd.io.resp.f2.preds[1].predicted_pc.valid) node _f2_predicted_ghist_T_2 = and(bpd.io.resp.f2.preds[2].is_br, bpd.io.resp.f2.preds[2].predicted_pc.valid) node _f2_predicted_ghist_T_3 = and(bpd.io.resp.f2.preds[3].is_br, bpd.io.resp.f2.preds[3].predicted_pc.valid) node f2_predicted_ghist_lo = cat(_f2_predicted_ghist_T_1, _f2_predicted_ghist_T) node f2_predicted_ghist_hi = cat(_f2_predicted_ghist_T_3, _f2_predicted_ghist_T_2) node _f2_predicted_ghist_T_4 = cat(f2_predicted_ghist_hi, f2_predicted_ghist_lo) node _f2_predicted_ghist_T_5 = and(_f2_predicted_ghist_T_4, f2_mask) node _f2_predicted_ghist_T_6 = and(bpd.io.resp.f2.preds[f2_redirect_idx].taken, f2_do_redirect) node f2_predicted_ghist_cfi_idx_fixed = bits(f2_redirect_idx, 1, 0) node f2_predicted_ghist_cfi_idx_oh = dshl(UInt<1>(0h1), f2_predicted_ghist_cfi_idx_fixed) wire f2_predicted_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} node _f2_predicted_ghist_not_taken_branches_T = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<1>(0h0)) node _f2_predicted_ghist_not_taken_branches_T_1 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<1>(0h1)) node _f2_predicted_ghist_not_taken_branches_T_2 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<2>(0h2)) node _f2_predicted_ghist_not_taken_branches_T_3 = dshr(f2_predicted_ghist_cfi_idx_oh, UInt<2>(0h3)) node _f2_predicted_ghist_not_taken_branches_T_4 = or(_f2_predicted_ghist_not_taken_branches_T, _f2_predicted_ghist_not_taken_branches_T_1) node _f2_predicted_ghist_not_taken_branches_T_5 = or(_f2_predicted_ghist_not_taken_branches_T_4, _f2_predicted_ghist_not_taken_branches_T_2) node _f2_predicted_ghist_not_taken_branches_T_6 = or(_f2_predicted_ghist_not_taken_branches_T_5, _f2_predicted_ghist_not_taken_branches_T_3) node _f2_predicted_ghist_not_taken_branches_T_7 = and(bpd.io.resp.f2.preds[f2_redirect_idx].is_br, _f2_predicted_ghist_T_6) node _f2_predicted_ghist_not_taken_branches_T_8 = mux(_f2_predicted_ghist_not_taken_branches_T_7, f2_predicted_ghist_cfi_idx_oh, UInt<4>(0h0)) node _f2_predicted_ghist_not_taken_branches_T_9 = not(_f2_predicted_ghist_not_taken_branches_T_8) node _f2_predicted_ghist_not_taken_branches_T_10 = and(_f2_predicted_ghist_not_taken_branches_T_6, _f2_predicted_ghist_not_taken_branches_T_9) node _f2_predicted_ghist_not_taken_branches_T_11 = not(UInt<4>(0h0)) node _f2_predicted_ghist_not_taken_branches_T_12 = mux(f2_do_redirect, _f2_predicted_ghist_not_taken_branches_T_10, _f2_predicted_ghist_not_taken_branches_T_11) node f2_predicted_ghist_not_taken_branches = and(_f2_predicted_ghist_T_5, _f2_predicted_ghist_not_taken_branches_T_12) invalidate f2_predicted_ghist.ras_idx invalidate f2_predicted_ghist.new_saw_branch_taken invalidate f2_predicted_ghist.new_saw_branch_not_taken invalidate f2_predicted_ghist.current_saw_branch_not_taken invalidate f2_predicted_ghist.old_history connect f2_predicted_ghist.current_saw_branch_not_taken, UInt<1>(0h0) node _f2_predicted_ghist_saw_not_taken_branch_T = neq(f2_predicted_ghist_not_taken_branches, UInt<1>(0h0)) node f2_predicted_ghist_saw_not_taken_branch = or(_f2_predicted_ghist_saw_not_taken_branch_T, s2_ghist.current_saw_branch_not_taken) node _f2_predicted_ghist_new_history_old_history_T = and(bpd.io.resp.f2.preds[f2_redirect_idx].is_br, _f2_predicted_ghist_T_6) node _f2_predicted_ghist_new_history_old_history_T_1 = and(_f2_predicted_ghist_new_history_old_history_T, f2_do_redirect) node _f2_predicted_ghist_new_history_old_history_T_2 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_3 = or(_f2_predicted_ghist_new_history_old_history_T_2, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_old_history_T_4 = shl(s2_ghist.old_history, 1) node _f2_predicted_ghist_new_history_old_history_T_5 = mux(f2_predicted_ghist_saw_not_taken_branch, _f2_predicted_ghist_new_history_old_history_T_4, s2_ghist.old_history) node _f2_predicted_ghist_new_history_old_history_T_6 = mux(_f2_predicted_ghist_new_history_old_history_T_1, _f2_predicted_ghist_new_history_old_history_T_3, _f2_predicted_ghist_new_history_old_history_T_5) connect f2_predicted_ghist.old_history, _f2_predicted_ghist_new_history_old_history_T_6 node _f2_predicted_ghist_new_history_ras_idx_T = and(f2_do_redirect, UInt<1>(0h0)) node _f2_predicted_ghist_new_history_ras_idx_T_1 = add(s2_ghist.ras_idx, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_ras_idx_T_2 = tail(_f2_predicted_ghist_new_history_ras_idx_T_1, 1) node _f2_predicted_ghist_new_history_ras_idx_T_3 = bits(_f2_predicted_ghist_new_history_ras_idx_T_2, 4, 0) node _f2_predicted_ghist_new_history_ras_idx_T_4 = and(f2_do_redirect, UInt<1>(0h0)) node _f2_predicted_ghist_new_history_ras_idx_T_5 = sub(s2_ghist.ras_idx, UInt<1>(0h1)) node _f2_predicted_ghist_new_history_ras_idx_T_6 = tail(_f2_predicted_ghist_new_history_ras_idx_T_5, 1) node _f2_predicted_ghist_new_history_ras_idx_T_7 = bits(_f2_predicted_ghist_new_history_ras_idx_T_6, 4, 0) node _f2_predicted_ghist_new_history_ras_idx_T_8 = mux(_f2_predicted_ghist_new_history_ras_idx_T_4, _f2_predicted_ghist_new_history_ras_idx_T_7, s2_ghist.ras_idx) node _f2_predicted_ghist_new_history_ras_idx_T_9 = mux(_f2_predicted_ghist_new_history_ras_idx_T, _f2_predicted_ghist_new_history_ras_idx_T_3, _f2_predicted_ghist_new_history_ras_idx_T_8) connect f2_predicted_ghist.ras_idx, _f2_predicted_ghist_new_history_ras_idx_T_9 node _f2_correct_f1_ghist_T = eq(s1_ghist.old_history, f2_predicted_ghist.old_history) node _f2_correct_f1_ghist_T_1 = eq(s1_ghist.new_saw_branch_not_taken, f2_predicted_ghist.new_saw_branch_not_taken) node _f2_correct_f1_ghist_T_2 = and(_f2_correct_f1_ghist_T, _f2_correct_f1_ghist_T_1) node _f2_correct_f1_ghist_T_3 = eq(s1_ghist.new_saw_branch_taken, f2_predicted_ghist.new_saw_branch_taken) node _f2_correct_f1_ghist_T_4 = and(_f2_correct_f1_ghist_T_2, _f2_correct_f1_ghist_T_3) node _f2_correct_f1_ghist_T_5 = eq(_f2_correct_f1_ghist_T_4, UInt<1>(0h0)) node f2_correct_f1_ghist = and(_f2_correct_f1_ghist_T_5, UInt<1>(0h1)) node _T_6 = eq(icache.io.resp.valid, UInt<1>(0h0)) node _T_7 = and(s2_valid, _T_6) node _T_8 = and(s2_valid, icache.io.resp.valid) node _T_9 = eq(f3_ready, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = or(_T_7, _T_10) when _T_11 : node _s0_valid_T_2 = eq(s2_tlb_resp.ae.inst, UInt<1>(0h0)) node _s0_valid_T_3 = eq(s2_tlb_resp.pf.inst, UInt<1>(0h0)) node _s0_valid_T_4 = and(_s0_valid_T_2, _s0_valid_T_3) node _s0_valid_T_5 = or(_s0_valid_T_4, s2_is_replay) node _s0_valid_T_6 = or(_s0_valid_T_5, s2_tlb_miss) connect s0_valid, _s0_valid_T_6 connect s0_vpc, s2_vpc node _s0_is_replay_T = and(s2_valid, icache.io.resp.valid) connect s0_is_replay, _s0_is_replay_T node _s0_s1_use_f3_bpd_resp_T = eq(s2_is_replay, UInt<1>(0h0)) connect s0_s1_use_f3_bpd_resp, _s0_s1_use_f3_bpd_resp_T connect s0_ghist, s2_ghist connect s0_tsrc, s2_tsrc connect f1_clear, UInt<1>(0h1) else : node _T_12 = and(s2_valid, f3_ready) when _T_12 : node _T_13 = eq(s1_vpc, f2_predicted_target) node _T_14 = and(s1_valid, _T_13) node _T_15 = eq(f2_correct_f1_ghist, UInt<1>(0h0)) node _T_16 = and(_T_14, _T_15) when _T_16 : connect s2_ghist, f2_predicted_ghist node _T_17 = neq(s1_vpc, f2_predicted_target) node _T_18 = or(_T_17, f2_correct_f1_ghist) node _T_19 = and(s1_valid, _T_18) node _T_20 = eq(s1_valid, UInt<1>(0h0)) node _T_21 = or(_T_19, _T_20) when _T_21 : connect f1_clear, UInt<1>(0h1) node _s0_valid_T_7 = or(s2_tlb_resp.ae.inst, s2_tlb_resp.pf.inst) node _s0_valid_T_8 = eq(s2_is_replay, UInt<1>(0h0)) node _s0_valid_T_9 = and(_s0_valid_T_7, _s0_valid_T_8) node _s0_valid_T_10 = eq(_s0_valid_T_9, UInt<1>(0h0)) connect s0_valid, _s0_valid_T_10 connect s0_vpc, f2_predicted_target connect s0_is_replay, UInt<1>(0h0) connect s0_ghist, f2_predicted_ghist connect s2_fsrc, UInt<2>(0h1) connect s0_tsrc, UInt<2>(0h1) connect s0_replay_bpd_resp.lhist, bpd.io.resp.f2.lhist connect s0_replay_bpd_resp.meta, bpd.io.resp.f2.meta connect s0_replay_bpd_resp.preds[0].predicted_pc, bpd.io.resp.f2.preds[0].predicted_pc connect s0_replay_bpd_resp.preds[0].is_jal, bpd.io.resp.f2.preds[0].is_jal connect s0_replay_bpd_resp.preds[0].is_br, bpd.io.resp.f2.preds[0].is_br connect s0_replay_bpd_resp.preds[0].taken, bpd.io.resp.f2.preds[0].taken connect s0_replay_bpd_resp.preds[1].predicted_pc, bpd.io.resp.f2.preds[1].predicted_pc connect s0_replay_bpd_resp.preds[1].is_jal, bpd.io.resp.f2.preds[1].is_jal connect s0_replay_bpd_resp.preds[1].is_br, bpd.io.resp.f2.preds[1].is_br connect s0_replay_bpd_resp.preds[1].taken, bpd.io.resp.f2.preds[1].taken connect s0_replay_bpd_resp.preds[2].predicted_pc, bpd.io.resp.f2.preds[2].predicted_pc connect s0_replay_bpd_resp.preds[2].is_jal, bpd.io.resp.f2.preds[2].is_jal connect s0_replay_bpd_resp.preds[2].is_br, bpd.io.resp.f2.preds[2].is_br connect s0_replay_bpd_resp.preds[2].taken, bpd.io.resp.f2.preds[2].taken connect s0_replay_bpd_resp.preds[3].predicted_pc, bpd.io.resp.f2.preds[3].predicted_pc connect s0_replay_bpd_resp.preds[3].is_jal, bpd.io.resp.f2.preds[3].is_jal connect s0_replay_bpd_resp.preds[3].is_br, bpd.io.resp.f2.preds[3].is_br connect s0_replay_bpd_resp.preds[3].taken, bpd.io.resp.f2.preds[3].taken connect s0_replay_bpd_resp.pc, bpd.io.resp.f2.pc connect s0_replay_resp, s2_tlb_resp connect s0_replay_ppc, s2_ppc wire f3_clear : UInt<1> connect f3_clear, UInt<1>(0h0) node _T_22 = asUInt(reset) node _T_23 = or(_T_22, f3_clear) inst f3 of Queue1_FrontendResp_1 connect f3.clock, clock connect f3.reset, _T_23 node _T_24 = asUInt(reset) node _T_25 = or(_T_24, f3_clear) inst f3_bpd_resp of Queue1_BranchPredictionBundle_1 connect f3_bpd_resp.clock, clock connect f3_bpd_resp.reset, _T_25 wire f4_ready : UInt<1> connect f3_ready, f3.io.enq.ready node _f3_io_enq_valid_T = eq(f2_clear, UInt<1>(0h0)) node _f3_io_enq_valid_T_1 = and(s2_valid, _f3_io_enq_valid_T) node _f3_io_enq_valid_T_2 = or(s2_tlb_resp.ae.inst, s2_tlb_resp.pf.inst) node _f3_io_enq_valid_T_3 = eq(s2_tlb_miss, UInt<1>(0h0)) node _f3_io_enq_valid_T_4 = and(_f3_io_enq_valid_T_2, _f3_io_enq_valid_T_3) node _f3_io_enq_valid_T_5 = or(icache.io.resp.valid, _f3_io_enq_valid_T_4) node _f3_io_enq_valid_T_6 = and(_f3_io_enq_valid_T_1, _f3_io_enq_valid_T_5) connect f3.io.enq.valid, _f3_io_enq_valid_T_6 connect f3.io.enq.bits.pc, s2_vpc node _f3_io_enq_bits_data_T = mux(s2_xcpt, UInt<1>(0h0), icache.io.resp.bits.data) connect f3.io.enq.bits.data, _f3_io_enq_bits_data_T connect f3.io.enq.bits.ghist.ras_idx, s2_ghist.ras_idx connect f3.io.enq.bits.ghist.new_saw_branch_taken, s2_ghist.new_saw_branch_taken connect f3.io.enq.bits.ghist.new_saw_branch_not_taken, s2_ghist.new_saw_branch_not_taken connect f3.io.enq.bits.ghist.current_saw_branch_not_taken, s2_ghist.current_saw_branch_not_taken connect f3.io.enq.bits.ghist.old_history, s2_ghist.old_history node f3_io_enq_bits_mask_idx = bits(s2_vpc, 2, 1) node _f3_io_enq_bits_mask_T = dshl(UInt<4>(0hf), f3_io_enq_bits_mask_idx) connect f3.io.enq.bits.mask, _f3_io_enq_bits_mask_T connect f3.io.enq.bits.xcpt.ae.inst, s2_tlb_resp.ae.inst connect f3.io.enq.bits.xcpt.gf.inst, s2_tlb_resp.gf.inst connect f3.io.enq.bits.xcpt.pf.inst, s2_tlb_resp.pf.inst connect f3.io.enq.bits.fsrc, s2_fsrc connect f3.io.enq.bits.tsrc, s2_tsrc regreset ras_read_idx : UInt<5>, clock, reset, UInt<5>(0h0) connect ras.io.read_idx, ras_read_idx node _T_26 = and(f3.io.enq.ready, f3.io.enq.valid) when _T_26 : connect ras_read_idx, f3.io.enq.bits.ghist.ras_idx connect ras.io.read_idx, f3.io.enq.bits.ghist.ras_idx reg f3_bpd_resp_io_enq_valid_REG : UInt<1>, clock connect f3_bpd_resp_io_enq_valid_REG, f3.io.enq.ready node _f3_bpd_resp_io_enq_valid_T = and(f3.io.deq.valid, f3_bpd_resp_io_enq_valid_REG) connect f3_bpd_resp.io.enq.valid, _f3_bpd_resp_io_enq_valid_T connect f3_bpd_resp.io.enq.bits.lhist[0], bpd.io.resp.f3.lhist[0] connect f3_bpd_resp.io.enq.bits.meta[0], bpd.io.resp.f3.meta[0] connect f3_bpd_resp.io.enq.bits.preds[0].predicted_pc.bits, bpd.io.resp.f3.preds[0].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[0].predicted_pc.valid, bpd.io.resp.f3.preds[0].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[0].is_jal, bpd.io.resp.f3.preds[0].is_jal connect f3_bpd_resp.io.enq.bits.preds[0].is_br, bpd.io.resp.f3.preds[0].is_br connect f3_bpd_resp.io.enq.bits.preds[0].taken, bpd.io.resp.f3.preds[0].taken connect f3_bpd_resp.io.enq.bits.preds[1].predicted_pc.bits, bpd.io.resp.f3.preds[1].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[1].predicted_pc.valid, bpd.io.resp.f3.preds[1].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[1].is_jal, bpd.io.resp.f3.preds[1].is_jal connect f3_bpd_resp.io.enq.bits.preds[1].is_br, bpd.io.resp.f3.preds[1].is_br connect f3_bpd_resp.io.enq.bits.preds[1].taken, bpd.io.resp.f3.preds[1].taken connect f3_bpd_resp.io.enq.bits.preds[2].predicted_pc.bits, bpd.io.resp.f3.preds[2].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[2].predicted_pc.valid, bpd.io.resp.f3.preds[2].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[2].is_jal, bpd.io.resp.f3.preds[2].is_jal connect f3_bpd_resp.io.enq.bits.preds[2].is_br, bpd.io.resp.f3.preds[2].is_br connect f3_bpd_resp.io.enq.bits.preds[2].taken, bpd.io.resp.f3.preds[2].taken connect f3_bpd_resp.io.enq.bits.preds[3].predicted_pc.bits, bpd.io.resp.f3.preds[3].predicted_pc.bits connect f3_bpd_resp.io.enq.bits.preds[3].predicted_pc.valid, bpd.io.resp.f3.preds[3].predicted_pc.valid connect f3_bpd_resp.io.enq.bits.preds[3].is_jal, bpd.io.resp.f3.preds[3].is_jal connect f3_bpd_resp.io.enq.bits.preds[3].is_br, bpd.io.resp.f3.preds[3].is_br connect f3_bpd_resp.io.enq.bits.preds[3].taken, bpd.io.resp.f3.preds[3].taken connect f3_bpd_resp.io.enq.bits.pc, bpd.io.resp.f3.pc node _T_27 = and(f3_bpd_resp.io.enq.ready, f3_bpd_resp.io.enq.valid) when _T_27 : connect bpd.io.f3_fire, UInt<1>(0h1) connect f3.io.deq.ready, f4_ready connect f3_bpd_resp.io.deq.ready, f4_ready node f3_bank_mask_idx = bits(f3.io.deq.bits.pc, 2, 1) node _f3_aligned_pc_T = not(f3.io.deq.bits.pc) node _f3_aligned_pc_T_1 = or(_f3_aligned_pc_T, UInt<3>(0h7)) node f3_aligned_pc = not(_f3_aligned_pc_T_1) node _f3_is_last_bank_in_block_T = bits(f3_aligned_pc, 5, 3) node _f3_is_last_bank_in_block_T_1 = eq(_f3_is_last_bank_in_block_T, UInt<3>(0h7)) node f3_is_last_bank_in_block = and(UInt<1>(0h0), _f3_is_last_bank_in_block_T_1) wire f3_is_rvc : UInt<1>[4] wire f3_redirects : UInt<1>[4] wire f3_targs : UInt<40>[4] wire f3_cfi_types : UInt<3>[4] wire f3_shadowed_mask : UInt<1>[4] wire f3_fetch_bundle : { pc : UInt<40>, next_pc : UInt<40>, edge_inst : UInt<1>[1], insts : UInt<32>[4], exp_insts : UInt<32>[4], sfbs : UInt<1>[4], sfb_masks : UInt<8>[4], sfb_dests : UInt<4>[4], shadowable_mask : UInt<1>[4], shadowed_mask : UInt<1>[4], cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_type : UInt<3>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ftq_idx : UInt<4>, mask : UInt<4>, br_mask : UInt<4>, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, lhist : UInt<1>[1], xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, bp_debug_if_oh : UInt<1>[4], bp_xcpt_if_oh : UInt<1>[4], end_half : { valid : UInt<1>, bits : UInt<16>}, bpd_meta : UInt[1], fsrc : UInt<2>, tsrc : UInt<2>} wire f3_mask : UInt<1>[4] wire f3_br_mask : UInt<1>[4] wire f3_call_mask : UInt<1>[4] wire f3_ret_mask : UInt<1>[4] wire f3_npc_plus4_mask : UInt<1>[4] wire f3_btb_mispredicts : UInt<1>[4] node f3_fetch_bundle_mask_lo = cat(f3_mask[1], f3_mask[0]) node f3_fetch_bundle_mask_hi = cat(f3_mask[3], f3_mask[2]) node _f3_fetch_bundle_mask_T = cat(f3_fetch_bundle_mask_hi, f3_fetch_bundle_mask_lo) connect f3_fetch_bundle.mask, _f3_fetch_bundle_mask_T node f3_fetch_bundle_br_mask_lo = cat(f3_br_mask[1], f3_br_mask[0]) node f3_fetch_bundle_br_mask_hi = cat(f3_br_mask[3], f3_br_mask[2]) node _f3_fetch_bundle_br_mask_T = cat(f3_fetch_bundle_br_mask_hi, f3_fetch_bundle_br_mask_lo) connect f3_fetch_bundle.br_mask, _f3_fetch_bundle_br_mask_T connect f3_fetch_bundle.pc, f3.io.deq.bits.pc connect f3_fetch_bundle.ftq_idx, UInt<1>(0h0) connect f3_fetch_bundle.xcpt_pf_if, f3.io.deq.bits.xcpt.pf.inst connect f3_fetch_bundle.xcpt_ae_if, f3.io.deq.bits.xcpt.ae.inst connect f3_fetch_bundle.fsrc, f3.io.deq.bits.fsrc connect f3_fetch_bundle.tsrc, f3.io.deq.bits.tsrc connect f3_fetch_bundle.shadowed_mask, f3_shadowed_mask reg f3_prev_half : UInt<16>, clock regreset f3_prev_is_half : UInt<1>, clock, reset, UInt<1>(0h0) node bank_data = bits(f3.io.deq.bits.data, 63, 0) wire bank_mask : UInt<1>[4] wire bank_insts : UInt<32>[4] wire valid : UInt<1> inst bpu of BreakpointUnit_5 connect bpu.clock, clock connect bpu.reset, reset connect bpu.io.status.uie, io.cpu.status.uie connect bpu.io.status.sie, io.cpu.status.sie connect bpu.io.status.hie, io.cpu.status.hie connect bpu.io.status.mie, io.cpu.status.mie connect bpu.io.status.upie, io.cpu.status.upie connect bpu.io.status.spie, io.cpu.status.spie connect bpu.io.status.ube, io.cpu.status.ube connect bpu.io.status.mpie, io.cpu.status.mpie connect bpu.io.status.spp, io.cpu.status.spp connect bpu.io.status.vs, io.cpu.status.vs connect bpu.io.status.mpp, io.cpu.status.mpp connect bpu.io.status.fs, io.cpu.status.fs connect bpu.io.status.xs, io.cpu.status.xs connect bpu.io.status.mprv, io.cpu.status.mprv connect bpu.io.status.sum, io.cpu.status.sum connect bpu.io.status.mxr, io.cpu.status.mxr connect bpu.io.status.tvm, io.cpu.status.tvm connect bpu.io.status.tw, io.cpu.status.tw connect bpu.io.status.tsr, io.cpu.status.tsr connect bpu.io.status.zero1, io.cpu.status.zero1 connect bpu.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu.io.status.uxl, io.cpu.status.uxl connect bpu.io.status.sxl, io.cpu.status.sxl connect bpu.io.status.sbe, io.cpu.status.sbe connect bpu.io.status.mbe, io.cpu.status.mbe connect bpu.io.status.gva, io.cpu.status.gva connect bpu.io.status.mpv, io.cpu.status.mpv connect bpu.io.status.zero2, io.cpu.status.zero2 connect bpu.io.status.sd, io.cpu.status.sd connect bpu.io.status.v, io.cpu.status.v connect bpu.io.status.prv, io.cpu.status.prv connect bpu.io.status.dv, io.cpu.status.dv connect bpu.io.status.dprv, io.cpu.status.dprv connect bpu.io.status.isa, io.cpu.status.isa connect bpu.io.status.wfi, io.cpu.status.wfi connect bpu.io.status.cease, io.cpu.status.cease connect bpu.io.status.debug, io.cpu.status.debug invalidate bpu.io.ea connect bpu.io.mcontext, io.cpu.mcontext connect bpu.io.scontext, io.cpu.scontext wire brsigs : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} node _inst0_T = bits(bank_data, 15, 0) node inst0 = cat(_inst0_T, f3_prev_half) node inst1 = bits(bank_data, 31, 0) inst exp_inst0_rvc_exp of RVCExpander_5 connect exp_inst0_rvc_exp.clock, clock connect exp_inst0_rvc_exp.reset, reset connect exp_inst0_rvc_exp.io.in, inst0 node exp_inst0 = mux(exp_inst0_rvc_exp.io.rvc, exp_inst0_rvc_exp.io.out.bits, inst0) inst exp_inst1_rvc_exp of RVCExpander_6 connect exp_inst1_rvc_exp.clock, clock connect exp_inst1_rvc_exp.reset, reset connect exp_inst1_rvc_exp.io.in, inst1 node exp_inst1 = mux(exp_inst1_rvc_exp.io.rvc, exp_inst1_rvc_exp.io.out.bits, inst1) node _pc0_T = add(f3_aligned_pc, UInt<1>(0h0)) node _pc0_T_1 = tail(_pc0_T, 1) node _pc0_T_2 = sub(_pc0_T_1, UInt<2>(0h2)) node pc0 = tail(_pc0_T_2, 1) node _pc1_T = add(f3_aligned_pc, UInt<1>(0h0)) node pc1 = tail(_pc1_T, 1) inst bpd_decoder0 of BranchDecode_5 connect bpd_decoder0.clock, clock connect bpd_decoder0.reset, reset connect bpd_decoder0.io.inst, exp_inst0 connect bpd_decoder0.io.pc, pc0 inst bpd_decoder1 of BranchDecode_6 connect bpd_decoder1.clock, clock connect bpd_decoder1.reset, reset connect bpd_decoder1.io.inst, exp_inst1 connect bpd_decoder1.io.pc, pc1 when f3_prev_is_half : connect bank_insts[0], inst0 connect f3_fetch_bundle.insts[0], inst0 connect f3_fetch_bundle.exp_insts[0], exp_inst0 connect bpu.io.pc, pc0 connect brsigs.shadowable, bpd_decoder0.io.out.shadowable connect brsigs.sfb_offset, bpd_decoder0.io.out.sfb_offset connect brsigs.cfi_type, bpd_decoder0.io.out.cfi_type connect brsigs.target, bpd_decoder0.io.out.target connect brsigs.is_call, bpd_decoder0.io.out.is_call connect brsigs.is_ret, bpd_decoder0.io.out.is_ret connect f3_fetch_bundle.edge_inst[0], UInt<1>(0h1) else : connect bank_insts[0], inst1 connect f3_fetch_bundle.insts[0], inst1 connect f3_fetch_bundle.exp_insts[0], exp_inst1 connect bpu.io.pc, pc1 connect brsigs.shadowable, bpd_decoder1.io.out.shadowable connect brsigs.sfb_offset, bpd_decoder1.io.out.sfb_offset connect brsigs.cfi_type, bpd_decoder1.io.out.cfi_type connect brsigs.target, bpd_decoder1.io.out.target connect brsigs.is_call, bpd_decoder1.io.out.is_call connect brsigs.is_ret, bpd_decoder1.io.out.is_ret connect f3_fetch_bundle.edge_inst[0], UInt<1>(0h0) connect valid, UInt<1>(0h1) node _f3_is_rvc_0_T = bits(bank_insts[0], 1, 0) node _f3_is_rvc_0_T_1 = neq(_f3_is_rvc_0_T, UInt<2>(0h3)) connect f3_is_rvc[0], _f3_is_rvc_0_T_1 node _bank_mask_0_T = bits(f3.io.deq.bits.mask, 0, 0) node _bank_mask_0_T_1 = and(f3.io.deq.valid, _bank_mask_0_T) node _bank_mask_0_T_2 = and(_bank_mask_0_T_1, valid) node _bank_mask_0_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bank_mask_0_T_4 = and(_bank_mask_0_T_2, _bank_mask_0_T_3) connect bank_mask[0], _bank_mask_0_T_4 node _f3_mask_0_T = bits(f3.io.deq.bits.mask, 0, 0) node _f3_mask_0_T_1 = and(f3.io.deq.valid, _f3_mask_0_T) node _f3_mask_0_T_2 = and(_f3_mask_0_T_1, valid) node _f3_mask_0_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _f3_mask_0_T_4 = and(_f3_mask_0_T_2, _f3_mask_0_T_3) connect f3_mask[0], _f3_mask_0_T_4 node _f3_targs_0_T = eq(brsigs.cfi_type, UInt<3>(0h3)) node _f3_targs_0_T_1 = mux(_f3_targs_0_T, f3_bpd_resp.io.deq.bits.preds[0].predicted_pc.bits, brsigs.target) connect f3_targs[0], _f3_targs_0_T_1 node _f3_btb_mispredicts_0_T = eq(brsigs.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_0_T_1 = and(_f3_btb_mispredicts_0_T, valid) node _f3_btb_mispredicts_0_T_2 = and(_f3_btb_mispredicts_0_T_1, f3_bpd_resp.io.deq.bits.preds[0].predicted_pc.valid) node _f3_btb_mispredicts_0_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[0].predicted_pc.bits, brsigs.target) node _f3_btb_mispredicts_0_T_4 = and(_f3_btb_mispredicts_0_T_2, _f3_btb_mispredicts_0_T_3) connect f3_btb_mispredicts[0], _f3_btb_mispredicts_0_T_4 node _f3_npc_plus4_mask_0_T = eq(f3_is_rvc[0], UInt<1>(0h0)) node _f3_npc_plus4_mask_0_T_1 = eq(f3_prev_is_half, UInt<1>(0h0)) node _f3_npc_plus4_mask_0_T_2 = and(_f3_npc_plus4_mask_0_T, _f3_npc_plus4_mask_0_T_1) connect f3_npc_plus4_mask[0], _f3_npc_plus4_mask_0_T_2 node _offset_from_aligned_pc_T = add(UInt<7>(0h0), brsigs.sfb_offset.bits) node _offset_from_aligned_pc_T_1 = tail(_offset_from_aligned_pc_T, 1) node _offset_from_aligned_pc_T_2 = and(f3_prev_is_half, UInt<1>(0h1)) node _offset_from_aligned_pc_T_3 = mux(_offset_from_aligned_pc_T_2, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_4 = sub(_offset_from_aligned_pc_T_1, _offset_from_aligned_pc_T_3) node offset_from_aligned_pc = tail(_offset_from_aligned_pc_T_4, 1) wire lower_mask : UInt<8> wire upper_mask : UInt<8> node _lower_mask_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) connect lower_mask, _lower_mask_T node _upper_mask_T = bits(offset_from_aligned_pc, 4, 1) node _upper_mask_T_1 = dshl(UInt<1>(0h1), _upper_mask_T) node _upper_mask_T_2 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_3 = dshl(_upper_mask_T_1, _upper_mask_T_2) connect upper_mask, _upper_mask_T_3 node _f3_fetch_bundle_sfbs_0_T = and(f3_mask[0], brsigs.sfb_offset.valid) node _f3_fetch_bundle_sfbs_0_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h10), UInt<5>(0h10)) node _f3_fetch_bundle_sfbs_0_T_2 = leq(offset_from_aligned_pc, _f3_fetch_bundle_sfbs_0_T_1) node _f3_fetch_bundle_sfbs_0_T_3 = and(_f3_fetch_bundle_sfbs_0_T, _f3_fetch_bundle_sfbs_0_T_2) connect f3_fetch_bundle.sfbs[0], _f3_fetch_bundle_sfbs_0_T_3 node _f3_fetch_bundle_sfb_masks_0_T = dshr(lower_mask, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_0_T_1 = dshr(lower_mask, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_0_T_2 = dshr(lower_mask, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_0_T_3 = dshr(lower_mask, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_0_T_4 = dshr(lower_mask, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_0_T_5 = dshr(lower_mask, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_0_T_6 = dshr(lower_mask, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_0_T_7 = dshr(lower_mask, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_0_T_8 = or(_f3_fetch_bundle_sfb_masks_0_T, _f3_fetch_bundle_sfb_masks_0_T_1) node _f3_fetch_bundle_sfb_masks_0_T_9 = or(_f3_fetch_bundle_sfb_masks_0_T_8, _f3_fetch_bundle_sfb_masks_0_T_2) node _f3_fetch_bundle_sfb_masks_0_T_10 = or(_f3_fetch_bundle_sfb_masks_0_T_9, _f3_fetch_bundle_sfb_masks_0_T_3) node _f3_fetch_bundle_sfb_masks_0_T_11 = or(_f3_fetch_bundle_sfb_masks_0_T_10, _f3_fetch_bundle_sfb_masks_0_T_4) node _f3_fetch_bundle_sfb_masks_0_T_12 = or(_f3_fetch_bundle_sfb_masks_0_T_11, _f3_fetch_bundle_sfb_masks_0_T_5) node _f3_fetch_bundle_sfb_masks_0_T_13 = or(_f3_fetch_bundle_sfb_masks_0_T_12, _f3_fetch_bundle_sfb_masks_0_T_6) node _f3_fetch_bundle_sfb_masks_0_T_14 = or(_f3_fetch_bundle_sfb_masks_0_T_13, _f3_fetch_bundle_sfb_masks_0_T_7) node _f3_fetch_bundle_sfb_masks_0_T_15 = not(_f3_fetch_bundle_sfb_masks_0_T_14) node _f3_fetch_bundle_sfb_masks_0_T_16 = dshl(upper_mask, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_0_T_17 = bits(_f3_fetch_bundle_sfb_masks_0_T_16, 7, 0) node _f3_fetch_bundle_sfb_masks_0_T_18 = dshl(upper_mask, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_0_T_19 = bits(_f3_fetch_bundle_sfb_masks_0_T_18, 7, 0) node _f3_fetch_bundle_sfb_masks_0_T_20 = dshl(upper_mask, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_0_T_21 = bits(_f3_fetch_bundle_sfb_masks_0_T_20, 7, 0) node _f3_fetch_bundle_sfb_masks_0_T_22 = dshl(upper_mask, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_0_T_23 = bits(_f3_fetch_bundle_sfb_masks_0_T_22, 7, 0) node _f3_fetch_bundle_sfb_masks_0_T_24 = dshl(upper_mask, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_0_T_25 = bits(_f3_fetch_bundle_sfb_masks_0_T_24, 7, 0) node _f3_fetch_bundle_sfb_masks_0_T_26 = dshl(upper_mask, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_0_T_27 = bits(_f3_fetch_bundle_sfb_masks_0_T_26, 7, 0) node _f3_fetch_bundle_sfb_masks_0_T_28 = dshl(upper_mask, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_0_T_29 = bits(_f3_fetch_bundle_sfb_masks_0_T_28, 7, 0) node _f3_fetch_bundle_sfb_masks_0_T_30 = dshl(upper_mask, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_0_T_31 = bits(_f3_fetch_bundle_sfb_masks_0_T_30, 7, 0) node _f3_fetch_bundle_sfb_masks_0_T_32 = or(_f3_fetch_bundle_sfb_masks_0_T_17, _f3_fetch_bundle_sfb_masks_0_T_19) node _f3_fetch_bundle_sfb_masks_0_T_33 = or(_f3_fetch_bundle_sfb_masks_0_T_32, _f3_fetch_bundle_sfb_masks_0_T_21) node _f3_fetch_bundle_sfb_masks_0_T_34 = or(_f3_fetch_bundle_sfb_masks_0_T_33, _f3_fetch_bundle_sfb_masks_0_T_23) node _f3_fetch_bundle_sfb_masks_0_T_35 = or(_f3_fetch_bundle_sfb_masks_0_T_34, _f3_fetch_bundle_sfb_masks_0_T_25) node _f3_fetch_bundle_sfb_masks_0_T_36 = or(_f3_fetch_bundle_sfb_masks_0_T_35, _f3_fetch_bundle_sfb_masks_0_T_27) node _f3_fetch_bundle_sfb_masks_0_T_37 = or(_f3_fetch_bundle_sfb_masks_0_T_36, _f3_fetch_bundle_sfb_masks_0_T_29) node _f3_fetch_bundle_sfb_masks_0_T_38 = or(_f3_fetch_bundle_sfb_masks_0_T_37, _f3_fetch_bundle_sfb_masks_0_T_31) node _f3_fetch_bundle_sfb_masks_0_T_39 = not(_f3_fetch_bundle_sfb_masks_0_T_38) node _f3_fetch_bundle_sfb_masks_0_T_40 = and(_f3_fetch_bundle_sfb_masks_0_T_15, _f3_fetch_bundle_sfb_masks_0_T_39) connect f3_fetch_bundle.sfb_masks[0], _f3_fetch_bundle_sfb_masks_0_T_40 node _f3_fetch_bundle_shadowable_mask_0_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_0_T_1 = or(_f3_fetch_bundle_shadowable_mask_0_T, bpu.io.debug_if) node _f3_fetch_bundle_shadowable_mask_0_T_2 = or(_f3_fetch_bundle_shadowable_mask_0_T_1, bpu.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_0_T_3 = eq(_f3_fetch_bundle_shadowable_mask_0_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_0_T_4 = and(_f3_fetch_bundle_shadowable_mask_0_T_3, UInt<1>(0h1)) node _f3_fetch_bundle_shadowable_mask_0_T_5 = eq(f3_mask[0], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_0_T_6 = or(brsigs.shadowable, _f3_fetch_bundle_shadowable_mask_0_T_5) node _f3_fetch_bundle_shadowable_mask_0_T_7 = and(_f3_fetch_bundle_shadowable_mask_0_T_4, _f3_fetch_bundle_shadowable_mask_0_T_6) connect f3_fetch_bundle.shadowable_mask[0], _f3_fetch_bundle_shadowable_mask_0_T_7 connect f3_fetch_bundle.sfb_dests[0], offset_from_aligned_pc node _f3_redirects_0_T = eq(brsigs.cfi_type, UInt<3>(0h2)) node _f3_redirects_0_T_1 = eq(brsigs.cfi_type, UInt<3>(0h3)) node _f3_redirects_0_T_2 = or(_f3_redirects_0_T, _f3_redirects_0_T_1) node _f3_redirects_0_T_3 = eq(brsigs.cfi_type, UInt<3>(0h1)) node _f3_redirects_0_T_4 = and(_f3_redirects_0_T_3, f3_bpd_resp.io.deq.bits.preds[0].taken) node _f3_redirects_0_T_5 = and(_f3_redirects_0_T_4, UInt<1>(0h1)) node _f3_redirects_0_T_6 = or(_f3_redirects_0_T_2, _f3_redirects_0_T_5) node _f3_redirects_0_T_7 = and(f3_mask[0], _f3_redirects_0_T_6) connect f3_redirects[0], _f3_redirects_0_T_7 node _f3_br_mask_0_T = eq(brsigs.cfi_type, UInt<3>(0h1)) node _f3_br_mask_0_T_1 = and(f3_mask[0], _f3_br_mask_0_T) connect f3_br_mask[0], _f3_br_mask_0_T_1 connect f3_cfi_types[0], brsigs.cfi_type connect f3_call_mask[0], brsigs.is_call connect f3_ret_mask[0], brsigs.is_ret connect f3_fetch_bundle.bp_debug_if_oh[0], bpu.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[0], bpu.io.xcpt_if node _T_28 = or(UInt<1>(0h0), f3_redirects[0]) wire valid_1 : UInt<1> inst bpu_1 of BreakpointUnit_6 connect bpu_1.clock, clock connect bpu_1.reset, reset connect bpu_1.io.status.uie, io.cpu.status.uie connect bpu_1.io.status.sie, io.cpu.status.sie connect bpu_1.io.status.hie, io.cpu.status.hie connect bpu_1.io.status.mie, io.cpu.status.mie connect bpu_1.io.status.upie, io.cpu.status.upie connect bpu_1.io.status.spie, io.cpu.status.spie connect bpu_1.io.status.ube, io.cpu.status.ube connect bpu_1.io.status.mpie, io.cpu.status.mpie connect bpu_1.io.status.spp, io.cpu.status.spp connect bpu_1.io.status.vs, io.cpu.status.vs connect bpu_1.io.status.mpp, io.cpu.status.mpp connect bpu_1.io.status.fs, io.cpu.status.fs connect bpu_1.io.status.xs, io.cpu.status.xs connect bpu_1.io.status.mprv, io.cpu.status.mprv connect bpu_1.io.status.sum, io.cpu.status.sum connect bpu_1.io.status.mxr, io.cpu.status.mxr connect bpu_1.io.status.tvm, io.cpu.status.tvm connect bpu_1.io.status.tw, io.cpu.status.tw connect bpu_1.io.status.tsr, io.cpu.status.tsr connect bpu_1.io.status.zero1, io.cpu.status.zero1 connect bpu_1.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_1.io.status.uxl, io.cpu.status.uxl connect bpu_1.io.status.sxl, io.cpu.status.sxl connect bpu_1.io.status.sbe, io.cpu.status.sbe connect bpu_1.io.status.mbe, io.cpu.status.mbe connect bpu_1.io.status.gva, io.cpu.status.gva connect bpu_1.io.status.mpv, io.cpu.status.mpv connect bpu_1.io.status.zero2, io.cpu.status.zero2 connect bpu_1.io.status.sd, io.cpu.status.sd connect bpu_1.io.status.v, io.cpu.status.v connect bpu_1.io.status.prv, io.cpu.status.prv connect bpu_1.io.status.dv, io.cpu.status.dv connect bpu_1.io.status.dprv, io.cpu.status.dprv connect bpu_1.io.status.isa, io.cpu.status.isa connect bpu_1.io.status.wfi, io.cpu.status.wfi connect bpu_1.io.status.cease, io.cpu.status.cease connect bpu_1.io.status.debug, io.cpu.status.debug invalidate bpu_1.io.ea connect bpu_1.io.mcontext, io.cpu.mcontext connect bpu_1.io.scontext, io.cpu.scontext wire brsigs_1 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} wire inst : UInt<32> inst exp_inst_rvc_exp of RVCExpander_7 connect exp_inst_rvc_exp.clock, clock connect exp_inst_rvc_exp.reset, reset connect exp_inst_rvc_exp.io.in, inst node exp_inst = mux(exp_inst_rvc_exp.io.rvc, exp_inst_rvc_exp.io.out.bits, inst) node _pc_T = add(f3_aligned_pc, UInt<2>(0h2)) node pc = tail(_pc_T, 1) inst bpd_decoder of BranchDecode_7 connect bpd_decoder.clock, clock connect bpd_decoder.reset, reset connect bpd_decoder.io.inst, exp_inst connect bpd_decoder.io.pc, pc connect bank_insts[1], inst connect f3_fetch_bundle.insts[1], inst connect f3_fetch_bundle.exp_insts[1], exp_inst connect bpu_1.io.pc, pc connect brsigs_1.shadowable, bpd_decoder.io.out.shadowable connect brsigs_1.sfb_offset, bpd_decoder.io.out.sfb_offset connect brsigs_1.cfi_type, bpd_decoder.io.out.cfi_type connect brsigs_1.target, bpd_decoder.io.out.target connect brsigs_1.is_call, bpd_decoder.io.out.is_call connect brsigs_1.is_ret, bpd_decoder.io.out.is_ret node _inst_T = bits(bank_data, 47, 16) connect inst, _inst_T node _valid_T = bits(bank_insts[0], 1, 0) node _valid_T_1 = neq(_valid_T, UInt<2>(0h3)) node _valid_T_2 = eq(_valid_T_1, UInt<1>(0h0)) node _valid_T_3 = and(bank_mask[0], _valid_T_2) node _valid_T_4 = eq(_valid_T_3, UInt<1>(0h0)) node _valid_T_5 = or(f3_prev_is_half, _valid_T_4) connect valid_1, _valid_T_5 node _f3_is_rvc_1_T = bits(bank_insts[1], 1, 0) node _f3_is_rvc_1_T_1 = neq(_f3_is_rvc_1_T, UInt<2>(0h3)) connect f3_is_rvc[1], _f3_is_rvc_1_T_1 node _bank_mask_1_T = bits(f3.io.deq.bits.mask, 1, 1) node _bank_mask_1_T_1 = and(f3.io.deq.valid, _bank_mask_1_T) node _bank_mask_1_T_2 = and(_bank_mask_1_T_1, valid_1) node _bank_mask_1_T_3 = eq(_T_28, UInt<1>(0h0)) node _bank_mask_1_T_4 = and(_bank_mask_1_T_2, _bank_mask_1_T_3) connect bank_mask[1], _bank_mask_1_T_4 node _f3_mask_1_T = bits(f3.io.deq.bits.mask, 1, 1) node _f3_mask_1_T_1 = and(f3.io.deq.valid, _f3_mask_1_T) node _f3_mask_1_T_2 = and(_f3_mask_1_T_1, valid_1) node _f3_mask_1_T_3 = eq(_T_28, UInt<1>(0h0)) node _f3_mask_1_T_4 = and(_f3_mask_1_T_2, _f3_mask_1_T_3) connect f3_mask[1], _f3_mask_1_T_4 node _f3_targs_1_T = eq(brsigs_1.cfi_type, UInt<3>(0h3)) node _f3_targs_1_T_1 = mux(_f3_targs_1_T, f3_bpd_resp.io.deq.bits.preds[1].predicted_pc.bits, brsigs_1.target) connect f3_targs[1], _f3_targs_1_T_1 node _f3_btb_mispredicts_1_T = eq(brsigs_1.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_1_T_1 = and(_f3_btb_mispredicts_1_T, valid_1) node _f3_btb_mispredicts_1_T_2 = and(_f3_btb_mispredicts_1_T_1, f3_bpd_resp.io.deq.bits.preds[1].predicted_pc.valid) node _f3_btb_mispredicts_1_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[1].predicted_pc.bits, brsigs_1.target) node _f3_btb_mispredicts_1_T_4 = and(_f3_btb_mispredicts_1_T_2, _f3_btb_mispredicts_1_T_3) connect f3_btb_mispredicts[1], _f3_btb_mispredicts_1_T_4 node _f3_npc_plus4_mask_1_T = eq(f3_is_rvc[1], UInt<1>(0h0)) connect f3_npc_plus4_mask[1], _f3_npc_plus4_mask_1_T node _offset_from_aligned_pc_T_5 = add(UInt<7>(0h2), brsigs_1.sfb_offset.bits) node _offset_from_aligned_pc_T_6 = tail(_offset_from_aligned_pc_T_5, 1) node _offset_from_aligned_pc_T_7 = and(f3_prev_is_half, UInt<1>(0h0)) node _offset_from_aligned_pc_T_8 = mux(_offset_from_aligned_pc_T_7, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_9 = sub(_offset_from_aligned_pc_T_6, _offset_from_aligned_pc_T_8) node offset_from_aligned_pc_1 = tail(_offset_from_aligned_pc_T_9, 1) wire lower_mask_1 : UInt<8> wire upper_mask_1 : UInt<8> node _lower_mask_T_1 = dshl(UInt<1>(0h1), UInt<1>(0h1)) connect lower_mask_1, _lower_mask_T_1 node _upper_mask_T_4 = bits(offset_from_aligned_pc_1, 4, 1) node _upper_mask_T_5 = dshl(UInt<1>(0h1), _upper_mask_T_4) node _upper_mask_T_6 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_7 = dshl(_upper_mask_T_5, _upper_mask_T_6) connect upper_mask_1, _upper_mask_T_7 node _f3_fetch_bundle_sfbs_1_T = and(f3_mask[1], brsigs_1.sfb_offset.valid) node _f3_fetch_bundle_sfbs_1_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h10), UInt<5>(0h10)) node _f3_fetch_bundle_sfbs_1_T_2 = leq(offset_from_aligned_pc_1, _f3_fetch_bundle_sfbs_1_T_1) node _f3_fetch_bundle_sfbs_1_T_3 = and(_f3_fetch_bundle_sfbs_1_T, _f3_fetch_bundle_sfbs_1_T_2) connect f3_fetch_bundle.sfbs[1], _f3_fetch_bundle_sfbs_1_T_3 node _f3_fetch_bundle_sfb_masks_1_T = dshr(lower_mask_1, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_1_T_1 = dshr(lower_mask_1, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_1_T_2 = dshr(lower_mask_1, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_1_T_3 = dshr(lower_mask_1, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_1_T_4 = dshr(lower_mask_1, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_1_T_5 = dshr(lower_mask_1, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_1_T_6 = dshr(lower_mask_1, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_1_T_7 = dshr(lower_mask_1, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_1_T_8 = or(_f3_fetch_bundle_sfb_masks_1_T, _f3_fetch_bundle_sfb_masks_1_T_1) node _f3_fetch_bundle_sfb_masks_1_T_9 = or(_f3_fetch_bundle_sfb_masks_1_T_8, _f3_fetch_bundle_sfb_masks_1_T_2) node _f3_fetch_bundle_sfb_masks_1_T_10 = or(_f3_fetch_bundle_sfb_masks_1_T_9, _f3_fetch_bundle_sfb_masks_1_T_3) node _f3_fetch_bundle_sfb_masks_1_T_11 = or(_f3_fetch_bundle_sfb_masks_1_T_10, _f3_fetch_bundle_sfb_masks_1_T_4) node _f3_fetch_bundle_sfb_masks_1_T_12 = or(_f3_fetch_bundle_sfb_masks_1_T_11, _f3_fetch_bundle_sfb_masks_1_T_5) node _f3_fetch_bundle_sfb_masks_1_T_13 = or(_f3_fetch_bundle_sfb_masks_1_T_12, _f3_fetch_bundle_sfb_masks_1_T_6) node _f3_fetch_bundle_sfb_masks_1_T_14 = or(_f3_fetch_bundle_sfb_masks_1_T_13, _f3_fetch_bundle_sfb_masks_1_T_7) node _f3_fetch_bundle_sfb_masks_1_T_15 = not(_f3_fetch_bundle_sfb_masks_1_T_14) node _f3_fetch_bundle_sfb_masks_1_T_16 = dshl(upper_mask_1, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_1_T_17 = bits(_f3_fetch_bundle_sfb_masks_1_T_16, 7, 0) node _f3_fetch_bundle_sfb_masks_1_T_18 = dshl(upper_mask_1, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_1_T_19 = bits(_f3_fetch_bundle_sfb_masks_1_T_18, 7, 0) node _f3_fetch_bundle_sfb_masks_1_T_20 = dshl(upper_mask_1, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_1_T_21 = bits(_f3_fetch_bundle_sfb_masks_1_T_20, 7, 0) node _f3_fetch_bundle_sfb_masks_1_T_22 = dshl(upper_mask_1, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_1_T_23 = bits(_f3_fetch_bundle_sfb_masks_1_T_22, 7, 0) node _f3_fetch_bundle_sfb_masks_1_T_24 = dshl(upper_mask_1, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_1_T_25 = bits(_f3_fetch_bundle_sfb_masks_1_T_24, 7, 0) node _f3_fetch_bundle_sfb_masks_1_T_26 = dshl(upper_mask_1, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_1_T_27 = bits(_f3_fetch_bundle_sfb_masks_1_T_26, 7, 0) node _f3_fetch_bundle_sfb_masks_1_T_28 = dshl(upper_mask_1, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_1_T_29 = bits(_f3_fetch_bundle_sfb_masks_1_T_28, 7, 0) node _f3_fetch_bundle_sfb_masks_1_T_30 = dshl(upper_mask_1, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_1_T_31 = bits(_f3_fetch_bundle_sfb_masks_1_T_30, 7, 0) node _f3_fetch_bundle_sfb_masks_1_T_32 = or(_f3_fetch_bundle_sfb_masks_1_T_17, _f3_fetch_bundle_sfb_masks_1_T_19) node _f3_fetch_bundle_sfb_masks_1_T_33 = or(_f3_fetch_bundle_sfb_masks_1_T_32, _f3_fetch_bundle_sfb_masks_1_T_21) node _f3_fetch_bundle_sfb_masks_1_T_34 = or(_f3_fetch_bundle_sfb_masks_1_T_33, _f3_fetch_bundle_sfb_masks_1_T_23) node _f3_fetch_bundle_sfb_masks_1_T_35 = or(_f3_fetch_bundle_sfb_masks_1_T_34, _f3_fetch_bundle_sfb_masks_1_T_25) node _f3_fetch_bundle_sfb_masks_1_T_36 = or(_f3_fetch_bundle_sfb_masks_1_T_35, _f3_fetch_bundle_sfb_masks_1_T_27) node _f3_fetch_bundle_sfb_masks_1_T_37 = or(_f3_fetch_bundle_sfb_masks_1_T_36, _f3_fetch_bundle_sfb_masks_1_T_29) node _f3_fetch_bundle_sfb_masks_1_T_38 = or(_f3_fetch_bundle_sfb_masks_1_T_37, _f3_fetch_bundle_sfb_masks_1_T_31) node _f3_fetch_bundle_sfb_masks_1_T_39 = not(_f3_fetch_bundle_sfb_masks_1_T_38) node _f3_fetch_bundle_sfb_masks_1_T_40 = and(_f3_fetch_bundle_sfb_masks_1_T_15, _f3_fetch_bundle_sfb_masks_1_T_39) connect f3_fetch_bundle.sfb_masks[1], _f3_fetch_bundle_sfb_masks_1_T_40 node _f3_fetch_bundle_shadowable_mask_1_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_1_T_1 = or(_f3_fetch_bundle_shadowable_mask_1_T, bpu_1.io.debug_if) node _f3_fetch_bundle_shadowable_mask_1_T_2 = or(_f3_fetch_bundle_shadowable_mask_1_T_1, bpu_1.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_1_T_3 = eq(_f3_fetch_bundle_shadowable_mask_1_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_1_T_4 = and(_f3_fetch_bundle_shadowable_mask_1_T_3, UInt<1>(0h1)) node _f3_fetch_bundle_shadowable_mask_1_T_5 = eq(f3_mask[1], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_1_T_6 = or(brsigs_1.shadowable, _f3_fetch_bundle_shadowable_mask_1_T_5) node _f3_fetch_bundle_shadowable_mask_1_T_7 = and(_f3_fetch_bundle_shadowable_mask_1_T_4, _f3_fetch_bundle_shadowable_mask_1_T_6) connect f3_fetch_bundle.shadowable_mask[1], _f3_fetch_bundle_shadowable_mask_1_T_7 connect f3_fetch_bundle.sfb_dests[1], offset_from_aligned_pc_1 node _f3_redirects_1_T = eq(brsigs_1.cfi_type, UInt<3>(0h2)) node _f3_redirects_1_T_1 = eq(brsigs_1.cfi_type, UInt<3>(0h3)) node _f3_redirects_1_T_2 = or(_f3_redirects_1_T, _f3_redirects_1_T_1) node _f3_redirects_1_T_3 = eq(brsigs_1.cfi_type, UInt<3>(0h1)) node _f3_redirects_1_T_4 = and(_f3_redirects_1_T_3, f3_bpd_resp.io.deq.bits.preds[1].taken) node _f3_redirects_1_T_5 = and(_f3_redirects_1_T_4, UInt<1>(0h1)) node _f3_redirects_1_T_6 = or(_f3_redirects_1_T_2, _f3_redirects_1_T_5) node _f3_redirects_1_T_7 = and(f3_mask[1], _f3_redirects_1_T_6) connect f3_redirects[1], _f3_redirects_1_T_7 node _f3_br_mask_1_T = eq(brsigs_1.cfi_type, UInt<3>(0h1)) node _f3_br_mask_1_T_1 = and(f3_mask[1], _f3_br_mask_1_T) connect f3_br_mask[1], _f3_br_mask_1_T_1 connect f3_cfi_types[1], brsigs_1.cfi_type connect f3_call_mask[1], brsigs_1.is_call connect f3_ret_mask[1], brsigs_1.is_ret connect f3_fetch_bundle.bp_debug_if_oh[1], bpu_1.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[1], bpu_1.io.xcpt_if node _T_29 = or(_T_28, f3_redirects[1]) wire valid_2 : UInt<1> inst bpu_2 of BreakpointUnit_7 connect bpu_2.clock, clock connect bpu_2.reset, reset connect bpu_2.io.status.uie, io.cpu.status.uie connect bpu_2.io.status.sie, io.cpu.status.sie connect bpu_2.io.status.hie, io.cpu.status.hie connect bpu_2.io.status.mie, io.cpu.status.mie connect bpu_2.io.status.upie, io.cpu.status.upie connect bpu_2.io.status.spie, io.cpu.status.spie connect bpu_2.io.status.ube, io.cpu.status.ube connect bpu_2.io.status.mpie, io.cpu.status.mpie connect bpu_2.io.status.spp, io.cpu.status.spp connect bpu_2.io.status.vs, io.cpu.status.vs connect bpu_2.io.status.mpp, io.cpu.status.mpp connect bpu_2.io.status.fs, io.cpu.status.fs connect bpu_2.io.status.xs, io.cpu.status.xs connect bpu_2.io.status.mprv, io.cpu.status.mprv connect bpu_2.io.status.sum, io.cpu.status.sum connect bpu_2.io.status.mxr, io.cpu.status.mxr connect bpu_2.io.status.tvm, io.cpu.status.tvm connect bpu_2.io.status.tw, io.cpu.status.tw connect bpu_2.io.status.tsr, io.cpu.status.tsr connect bpu_2.io.status.zero1, io.cpu.status.zero1 connect bpu_2.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_2.io.status.uxl, io.cpu.status.uxl connect bpu_2.io.status.sxl, io.cpu.status.sxl connect bpu_2.io.status.sbe, io.cpu.status.sbe connect bpu_2.io.status.mbe, io.cpu.status.mbe connect bpu_2.io.status.gva, io.cpu.status.gva connect bpu_2.io.status.mpv, io.cpu.status.mpv connect bpu_2.io.status.zero2, io.cpu.status.zero2 connect bpu_2.io.status.sd, io.cpu.status.sd connect bpu_2.io.status.v, io.cpu.status.v connect bpu_2.io.status.prv, io.cpu.status.prv connect bpu_2.io.status.dv, io.cpu.status.dv connect bpu_2.io.status.dprv, io.cpu.status.dprv connect bpu_2.io.status.isa, io.cpu.status.isa connect bpu_2.io.status.wfi, io.cpu.status.wfi connect bpu_2.io.status.cease, io.cpu.status.cease connect bpu_2.io.status.debug, io.cpu.status.debug invalidate bpu_2.io.ea connect bpu_2.io.mcontext, io.cpu.mcontext connect bpu_2.io.scontext, io.cpu.scontext wire brsigs_2 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} wire inst_1 : UInt<32> inst exp_inst_rvc_exp_1 of RVCExpander_8 connect exp_inst_rvc_exp_1.clock, clock connect exp_inst_rvc_exp_1.reset, reset connect exp_inst_rvc_exp_1.io.in, inst_1 node exp_inst_1 = mux(exp_inst_rvc_exp_1.io.rvc, exp_inst_rvc_exp_1.io.out.bits, inst_1) node _pc_T_1 = add(f3_aligned_pc, UInt<3>(0h4)) node pc_1 = tail(_pc_T_1, 1) inst bpd_decoder_1 of BranchDecode_8 connect bpd_decoder_1.clock, clock connect bpd_decoder_1.reset, reset connect bpd_decoder_1.io.inst, exp_inst_1 connect bpd_decoder_1.io.pc, pc_1 connect bank_insts[2], inst_1 connect f3_fetch_bundle.insts[2], inst_1 connect f3_fetch_bundle.exp_insts[2], exp_inst_1 connect bpu_2.io.pc, pc_1 connect brsigs_2.shadowable, bpd_decoder_1.io.out.shadowable connect brsigs_2.sfb_offset, bpd_decoder_1.io.out.sfb_offset connect brsigs_2.cfi_type, bpd_decoder_1.io.out.cfi_type connect brsigs_2.target, bpd_decoder_1.io.out.target connect brsigs_2.is_call, bpd_decoder_1.io.out.is_call connect brsigs_2.is_ret, bpd_decoder_1.io.out.is_ret node _inst_T_1 = bits(bank_data, 63, 32) connect inst_1, _inst_T_1 node _valid_T_6 = bits(bank_insts[1], 1, 0) node _valid_T_7 = neq(_valid_T_6, UInt<2>(0h3)) node _valid_T_8 = eq(_valid_T_7, UInt<1>(0h0)) node _valid_T_9 = and(bank_mask[1], _valid_T_8) node _valid_T_10 = eq(_valid_T_9, UInt<1>(0h0)) connect valid_2, _valid_T_10 node _f3_is_rvc_2_T = bits(bank_insts[2], 1, 0) node _f3_is_rvc_2_T_1 = neq(_f3_is_rvc_2_T, UInt<2>(0h3)) connect f3_is_rvc[2], _f3_is_rvc_2_T_1 node _bank_mask_2_T = bits(f3.io.deq.bits.mask, 2, 2) node _bank_mask_2_T_1 = and(f3.io.deq.valid, _bank_mask_2_T) node _bank_mask_2_T_2 = and(_bank_mask_2_T_1, valid_2) node _bank_mask_2_T_3 = eq(_T_29, UInt<1>(0h0)) node _bank_mask_2_T_4 = and(_bank_mask_2_T_2, _bank_mask_2_T_3) connect bank_mask[2], _bank_mask_2_T_4 node _f3_mask_2_T = bits(f3.io.deq.bits.mask, 2, 2) node _f3_mask_2_T_1 = and(f3.io.deq.valid, _f3_mask_2_T) node _f3_mask_2_T_2 = and(_f3_mask_2_T_1, valid_2) node _f3_mask_2_T_3 = eq(_T_29, UInt<1>(0h0)) node _f3_mask_2_T_4 = and(_f3_mask_2_T_2, _f3_mask_2_T_3) connect f3_mask[2], _f3_mask_2_T_4 node _f3_targs_2_T = eq(brsigs_2.cfi_type, UInt<3>(0h3)) node _f3_targs_2_T_1 = mux(_f3_targs_2_T, f3_bpd_resp.io.deq.bits.preds[2].predicted_pc.bits, brsigs_2.target) connect f3_targs[2], _f3_targs_2_T_1 node _f3_btb_mispredicts_2_T = eq(brsigs_2.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_2_T_1 = and(_f3_btb_mispredicts_2_T, valid_2) node _f3_btb_mispredicts_2_T_2 = and(_f3_btb_mispredicts_2_T_1, f3_bpd_resp.io.deq.bits.preds[2].predicted_pc.valid) node _f3_btb_mispredicts_2_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[2].predicted_pc.bits, brsigs_2.target) node _f3_btb_mispredicts_2_T_4 = and(_f3_btb_mispredicts_2_T_2, _f3_btb_mispredicts_2_T_3) connect f3_btb_mispredicts[2], _f3_btb_mispredicts_2_T_4 node _f3_npc_plus4_mask_2_T = eq(f3_is_rvc[2], UInt<1>(0h0)) connect f3_npc_plus4_mask[2], _f3_npc_plus4_mask_2_T node _offset_from_aligned_pc_T_10 = add(UInt<7>(0h4), brsigs_2.sfb_offset.bits) node _offset_from_aligned_pc_T_11 = tail(_offset_from_aligned_pc_T_10, 1) node _offset_from_aligned_pc_T_12 = and(f3_prev_is_half, UInt<1>(0h0)) node _offset_from_aligned_pc_T_13 = mux(_offset_from_aligned_pc_T_12, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_14 = sub(_offset_from_aligned_pc_T_11, _offset_from_aligned_pc_T_13) node offset_from_aligned_pc_2 = tail(_offset_from_aligned_pc_T_14, 1) wire lower_mask_2 : UInt<8> wire upper_mask_2 : UInt<8> node _lower_mask_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) connect lower_mask_2, _lower_mask_T_2 node _upper_mask_T_8 = bits(offset_from_aligned_pc_2, 4, 1) node _upper_mask_T_9 = dshl(UInt<1>(0h1), _upper_mask_T_8) node _upper_mask_T_10 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_11 = dshl(_upper_mask_T_9, _upper_mask_T_10) connect upper_mask_2, _upper_mask_T_11 node _f3_fetch_bundle_sfbs_2_T = and(f3_mask[2], brsigs_2.sfb_offset.valid) node _f3_fetch_bundle_sfbs_2_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h10), UInt<5>(0h10)) node _f3_fetch_bundle_sfbs_2_T_2 = leq(offset_from_aligned_pc_2, _f3_fetch_bundle_sfbs_2_T_1) node _f3_fetch_bundle_sfbs_2_T_3 = and(_f3_fetch_bundle_sfbs_2_T, _f3_fetch_bundle_sfbs_2_T_2) connect f3_fetch_bundle.sfbs[2], _f3_fetch_bundle_sfbs_2_T_3 node _f3_fetch_bundle_sfb_masks_2_T = dshr(lower_mask_2, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_2_T_1 = dshr(lower_mask_2, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_2_T_2 = dshr(lower_mask_2, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_2_T_3 = dshr(lower_mask_2, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_2_T_4 = dshr(lower_mask_2, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_2_T_5 = dshr(lower_mask_2, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_2_T_6 = dshr(lower_mask_2, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_2_T_7 = dshr(lower_mask_2, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_2_T_8 = or(_f3_fetch_bundle_sfb_masks_2_T, _f3_fetch_bundle_sfb_masks_2_T_1) node _f3_fetch_bundle_sfb_masks_2_T_9 = or(_f3_fetch_bundle_sfb_masks_2_T_8, _f3_fetch_bundle_sfb_masks_2_T_2) node _f3_fetch_bundle_sfb_masks_2_T_10 = or(_f3_fetch_bundle_sfb_masks_2_T_9, _f3_fetch_bundle_sfb_masks_2_T_3) node _f3_fetch_bundle_sfb_masks_2_T_11 = or(_f3_fetch_bundle_sfb_masks_2_T_10, _f3_fetch_bundle_sfb_masks_2_T_4) node _f3_fetch_bundle_sfb_masks_2_T_12 = or(_f3_fetch_bundle_sfb_masks_2_T_11, _f3_fetch_bundle_sfb_masks_2_T_5) node _f3_fetch_bundle_sfb_masks_2_T_13 = or(_f3_fetch_bundle_sfb_masks_2_T_12, _f3_fetch_bundle_sfb_masks_2_T_6) node _f3_fetch_bundle_sfb_masks_2_T_14 = or(_f3_fetch_bundle_sfb_masks_2_T_13, _f3_fetch_bundle_sfb_masks_2_T_7) node _f3_fetch_bundle_sfb_masks_2_T_15 = not(_f3_fetch_bundle_sfb_masks_2_T_14) node _f3_fetch_bundle_sfb_masks_2_T_16 = dshl(upper_mask_2, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_2_T_17 = bits(_f3_fetch_bundle_sfb_masks_2_T_16, 7, 0) node _f3_fetch_bundle_sfb_masks_2_T_18 = dshl(upper_mask_2, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_2_T_19 = bits(_f3_fetch_bundle_sfb_masks_2_T_18, 7, 0) node _f3_fetch_bundle_sfb_masks_2_T_20 = dshl(upper_mask_2, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_2_T_21 = bits(_f3_fetch_bundle_sfb_masks_2_T_20, 7, 0) node _f3_fetch_bundle_sfb_masks_2_T_22 = dshl(upper_mask_2, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_2_T_23 = bits(_f3_fetch_bundle_sfb_masks_2_T_22, 7, 0) node _f3_fetch_bundle_sfb_masks_2_T_24 = dshl(upper_mask_2, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_2_T_25 = bits(_f3_fetch_bundle_sfb_masks_2_T_24, 7, 0) node _f3_fetch_bundle_sfb_masks_2_T_26 = dshl(upper_mask_2, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_2_T_27 = bits(_f3_fetch_bundle_sfb_masks_2_T_26, 7, 0) node _f3_fetch_bundle_sfb_masks_2_T_28 = dshl(upper_mask_2, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_2_T_29 = bits(_f3_fetch_bundle_sfb_masks_2_T_28, 7, 0) node _f3_fetch_bundle_sfb_masks_2_T_30 = dshl(upper_mask_2, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_2_T_31 = bits(_f3_fetch_bundle_sfb_masks_2_T_30, 7, 0) node _f3_fetch_bundle_sfb_masks_2_T_32 = or(_f3_fetch_bundle_sfb_masks_2_T_17, _f3_fetch_bundle_sfb_masks_2_T_19) node _f3_fetch_bundle_sfb_masks_2_T_33 = or(_f3_fetch_bundle_sfb_masks_2_T_32, _f3_fetch_bundle_sfb_masks_2_T_21) node _f3_fetch_bundle_sfb_masks_2_T_34 = or(_f3_fetch_bundle_sfb_masks_2_T_33, _f3_fetch_bundle_sfb_masks_2_T_23) node _f3_fetch_bundle_sfb_masks_2_T_35 = or(_f3_fetch_bundle_sfb_masks_2_T_34, _f3_fetch_bundle_sfb_masks_2_T_25) node _f3_fetch_bundle_sfb_masks_2_T_36 = or(_f3_fetch_bundle_sfb_masks_2_T_35, _f3_fetch_bundle_sfb_masks_2_T_27) node _f3_fetch_bundle_sfb_masks_2_T_37 = or(_f3_fetch_bundle_sfb_masks_2_T_36, _f3_fetch_bundle_sfb_masks_2_T_29) node _f3_fetch_bundle_sfb_masks_2_T_38 = or(_f3_fetch_bundle_sfb_masks_2_T_37, _f3_fetch_bundle_sfb_masks_2_T_31) node _f3_fetch_bundle_sfb_masks_2_T_39 = not(_f3_fetch_bundle_sfb_masks_2_T_38) node _f3_fetch_bundle_sfb_masks_2_T_40 = and(_f3_fetch_bundle_sfb_masks_2_T_15, _f3_fetch_bundle_sfb_masks_2_T_39) connect f3_fetch_bundle.sfb_masks[2], _f3_fetch_bundle_sfb_masks_2_T_40 node _f3_fetch_bundle_shadowable_mask_2_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_2_T_1 = or(_f3_fetch_bundle_shadowable_mask_2_T, bpu_2.io.debug_if) node _f3_fetch_bundle_shadowable_mask_2_T_2 = or(_f3_fetch_bundle_shadowable_mask_2_T_1, bpu_2.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_2_T_3 = eq(_f3_fetch_bundle_shadowable_mask_2_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_2_T_4 = and(_f3_fetch_bundle_shadowable_mask_2_T_3, UInt<1>(0h1)) node _f3_fetch_bundle_shadowable_mask_2_T_5 = eq(f3_mask[2], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_2_T_6 = or(brsigs_2.shadowable, _f3_fetch_bundle_shadowable_mask_2_T_5) node _f3_fetch_bundle_shadowable_mask_2_T_7 = and(_f3_fetch_bundle_shadowable_mask_2_T_4, _f3_fetch_bundle_shadowable_mask_2_T_6) connect f3_fetch_bundle.shadowable_mask[2], _f3_fetch_bundle_shadowable_mask_2_T_7 connect f3_fetch_bundle.sfb_dests[2], offset_from_aligned_pc_2 node _f3_redirects_2_T = eq(brsigs_2.cfi_type, UInt<3>(0h2)) node _f3_redirects_2_T_1 = eq(brsigs_2.cfi_type, UInt<3>(0h3)) node _f3_redirects_2_T_2 = or(_f3_redirects_2_T, _f3_redirects_2_T_1) node _f3_redirects_2_T_3 = eq(brsigs_2.cfi_type, UInt<3>(0h1)) node _f3_redirects_2_T_4 = and(_f3_redirects_2_T_3, f3_bpd_resp.io.deq.bits.preds[2].taken) node _f3_redirects_2_T_5 = and(_f3_redirects_2_T_4, UInt<1>(0h1)) node _f3_redirects_2_T_6 = or(_f3_redirects_2_T_2, _f3_redirects_2_T_5) node _f3_redirects_2_T_7 = and(f3_mask[2], _f3_redirects_2_T_6) connect f3_redirects[2], _f3_redirects_2_T_7 node _f3_br_mask_2_T = eq(brsigs_2.cfi_type, UInt<3>(0h1)) node _f3_br_mask_2_T_1 = and(f3_mask[2], _f3_br_mask_2_T) connect f3_br_mask[2], _f3_br_mask_2_T_1 connect f3_cfi_types[2], brsigs_2.cfi_type connect f3_call_mask[2], brsigs_2.is_call connect f3_ret_mask[2], brsigs_2.is_ret connect f3_fetch_bundle.bp_debug_if_oh[2], bpu_2.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[2], bpu_2.io.xcpt_if node _T_30 = or(_T_29, f3_redirects[2]) wire valid_3 : UInt<1> inst bpu_3 of BreakpointUnit_8 connect bpu_3.clock, clock connect bpu_3.reset, reset connect bpu_3.io.status.uie, io.cpu.status.uie connect bpu_3.io.status.sie, io.cpu.status.sie connect bpu_3.io.status.hie, io.cpu.status.hie connect bpu_3.io.status.mie, io.cpu.status.mie connect bpu_3.io.status.upie, io.cpu.status.upie connect bpu_3.io.status.spie, io.cpu.status.spie connect bpu_3.io.status.ube, io.cpu.status.ube connect bpu_3.io.status.mpie, io.cpu.status.mpie connect bpu_3.io.status.spp, io.cpu.status.spp connect bpu_3.io.status.vs, io.cpu.status.vs connect bpu_3.io.status.mpp, io.cpu.status.mpp connect bpu_3.io.status.fs, io.cpu.status.fs connect bpu_3.io.status.xs, io.cpu.status.xs connect bpu_3.io.status.mprv, io.cpu.status.mprv connect bpu_3.io.status.sum, io.cpu.status.sum connect bpu_3.io.status.mxr, io.cpu.status.mxr connect bpu_3.io.status.tvm, io.cpu.status.tvm connect bpu_3.io.status.tw, io.cpu.status.tw connect bpu_3.io.status.tsr, io.cpu.status.tsr connect bpu_3.io.status.zero1, io.cpu.status.zero1 connect bpu_3.io.status.sd_rv32, io.cpu.status.sd_rv32 connect bpu_3.io.status.uxl, io.cpu.status.uxl connect bpu_3.io.status.sxl, io.cpu.status.sxl connect bpu_3.io.status.sbe, io.cpu.status.sbe connect bpu_3.io.status.mbe, io.cpu.status.mbe connect bpu_3.io.status.gva, io.cpu.status.gva connect bpu_3.io.status.mpv, io.cpu.status.mpv connect bpu_3.io.status.zero2, io.cpu.status.zero2 connect bpu_3.io.status.sd, io.cpu.status.sd connect bpu_3.io.status.v, io.cpu.status.v connect bpu_3.io.status.prv, io.cpu.status.prv connect bpu_3.io.status.dv, io.cpu.status.dv connect bpu_3.io.status.dprv, io.cpu.status.dprv connect bpu_3.io.status.isa, io.cpu.status.isa connect bpu_3.io.status.wfi, io.cpu.status.wfi connect bpu_3.io.status.cease, io.cpu.status.cease connect bpu_3.io.status.debug, io.cpu.status.debug invalidate bpu_3.io.ea connect bpu_3.io.mcontext, io.cpu.mcontext connect bpu_3.io.scontext, io.cpu.scontext wire brsigs_3 : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>} wire inst_2 : UInt<32> inst exp_inst_rvc_exp_2 of RVCExpander_9 connect exp_inst_rvc_exp_2.clock, clock connect exp_inst_rvc_exp_2.reset, reset connect exp_inst_rvc_exp_2.io.in, inst_2 node exp_inst_2 = mux(exp_inst_rvc_exp_2.io.rvc, exp_inst_rvc_exp_2.io.out.bits, inst_2) node _pc_T_2 = add(f3_aligned_pc, UInt<3>(0h6)) node pc_2 = tail(_pc_T_2, 1) inst bpd_decoder_2 of BranchDecode_9 connect bpd_decoder_2.clock, clock connect bpd_decoder_2.reset, reset connect bpd_decoder_2.io.inst, exp_inst_2 connect bpd_decoder_2.io.pc, pc_2 connect bank_insts[3], inst_2 connect f3_fetch_bundle.insts[3], inst_2 connect f3_fetch_bundle.exp_insts[3], exp_inst_2 connect bpu_3.io.pc, pc_2 connect brsigs_3.shadowable, bpd_decoder_2.io.out.shadowable connect brsigs_3.sfb_offset, bpd_decoder_2.io.out.sfb_offset connect brsigs_3.cfi_type, bpd_decoder_2.io.out.cfi_type connect brsigs_3.target, bpd_decoder_2.io.out.target connect brsigs_3.is_call, bpd_decoder_2.io.out.is_call connect brsigs_3.is_ret, bpd_decoder_2.io.out.is_ret node _inst_T_2 = bits(bank_data, 63, 48) node _inst_T_3 = cat(UInt<16>(0h0), _inst_T_2) connect inst_2, _inst_T_3 node _valid_T_11 = bits(bank_insts[2], 1, 0) node _valid_T_12 = neq(_valid_T_11, UInt<2>(0h3)) node _valid_T_13 = eq(_valid_T_12, UInt<1>(0h0)) node _valid_T_14 = and(bank_mask[2], _valid_T_13) node _valid_T_15 = bits(inst_2, 1, 0) node _valid_T_16 = neq(_valid_T_15, UInt<2>(0h3)) node _valid_T_17 = eq(_valid_T_16, UInt<1>(0h0)) node _valid_T_18 = or(_valid_T_14, _valid_T_17) node _valid_T_19 = eq(_valid_T_18, UInt<1>(0h0)) connect valid_3, _valid_T_19 node _f3_is_rvc_3_T = bits(bank_insts[3], 1, 0) node _f3_is_rvc_3_T_1 = neq(_f3_is_rvc_3_T, UInt<2>(0h3)) connect f3_is_rvc[3], _f3_is_rvc_3_T_1 node _bank_mask_3_T = bits(f3.io.deq.bits.mask, 3, 3) node _bank_mask_3_T_1 = and(f3.io.deq.valid, _bank_mask_3_T) node _bank_mask_3_T_2 = and(_bank_mask_3_T_1, valid_3) node _bank_mask_3_T_3 = eq(_T_30, UInt<1>(0h0)) node _bank_mask_3_T_4 = and(_bank_mask_3_T_2, _bank_mask_3_T_3) connect bank_mask[3], _bank_mask_3_T_4 node _f3_mask_3_T = bits(f3.io.deq.bits.mask, 3, 3) node _f3_mask_3_T_1 = and(f3.io.deq.valid, _f3_mask_3_T) node _f3_mask_3_T_2 = and(_f3_mask_3_T_1, valid_3) node _f3_mask_3_T_3 = eq(_T_30, UInt<1>(0h0)) node _f3_mask_3_T_4 = and(_f3_mask_3_T_2, _f3_mask_3_T_3) connect f3_mask[3], _f3_mask_3_T_4 node _f3_targs_3_T = eq(brsigs_3.cfi_type, UInt<3>(0h3)) node _f3_targs_3_T_1 = mux(_f3_targs_3_T, f3_bpd_resp.io.deq.bits.preds[3].predicted_pc.bits, brsigs_3.target) connect f3_targs[3], _f3_targs_3_T_1 node _f3_btb_mispredicts_3_T = eq(brsigs_3.cfi_type, UInt<3>(0h2)) node _f3_btb_mispredicts_3_T_1 = and(_f3_btb_mispredicts_3_T, valid_3) node _f3_btb_mispredicts_3_T_2 = and(_f3_btb_mispredicts_3_T_1, f3_bpd_resp.io.deq.bits.preds[3].predicted_pc.valid) node _f3_btb_mispredicts_3_T_3 = neq(f3_bpd_resp.io.deq.bits.preds[3].predicted_pc.bits, brsigs_3.target) node _f3_btb_mispredicts_3_T_4 = and(_f3_btb_mispredicts_3_T_2, _f3_btb_mispredicts_3_T_3) connect f3_btb_mispredicts[3], _f3_btb_mispredicts_3_T_4 node _f3_npc_plus4_mask_3_T = eq(f3_is_rvc[3], UInt<1>(0h0)) connect f3_npc_plus4_mask[3], _f3_npc_plus4_mask_3_T node _offset_from_aligned_pc_T_15 = add(UInt<7>(0h6), brsigs_3.sfb_offset.bits) node _offset_from_aligned_pc_T_16 = tail(_offset_from_aligned_pc_T_15, 1) node _offset_from_aligned_pc_T_17 = and(f3_prev_is_half, UInt<1>(0h0)) node _offset_from_aligned_pc_T_18 = mux(_offset_from_aligned_pc_T_17, UInt<2>(0h2), UInt<1>(0h0)) node _offset_from_aligned_pc_T_19 = sub(_offset_from_aligned_pc_T_16, _offset_from_aligned_pc_T_18) node offset_from_aligned_pc_3 = tail(_offset_from_aligned_pc_T_19, 1) wire lower_mask_3 : UInt<8> wire upper_mask_3 : UInt<8> node _lower_mask_T_3 = dshl(UInt<1>(0h1), UInt<2>(0h3)) connect lower_mask_3, _lower_mask_T_3 node _upper_mask_T_12 = bits(offset_from_aligned_pc_3, 4, 1) node _upper_mask_T_13 = dshl(UInt<1>(0h1), _upper_mask_T_12) node _upper_mask_T_14 = mux(f3_is_last_bank_in_block, UInt<3>(0h4), UInt<1>(0h0)) node _upper_mask_T_15 = dshl(_upper_mask_T_13, _upper_mask_T_14) connect upper_mask_3, _upper_mask_T_15 node _f3_fetch_bundle_sfbs_3_T = and(f3_mask[3], brsigs_3.sfb_offset.valid) node _f3_fetch_bundle_sfbs_3_T_1 = mux(f3_is_last_bank_in_block, UInt<5>(0h10), UInt<5>(0h10)) node _f3_fetch_bundle_sfbs_3_T_2 = leq(offset_from_aligned_pc_3, _f3_fetch_bundle_sfbs_3_T_1) node _f3_fetch_bundle_sfbs_3_T_3 = and(_f3_fetch_bundle_sfbs_3_T, _f3_fetch_bundle_sfbs_3_T_2) connect f3_fetch_bundle.sfbs[3], _f3_fetch_bundle_sfbs_3_T_3 node _f3_fetch_bundle_sfb_masks_3_T = dshr(lower_mask_3, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_3_T_1 = dshr(lower_mask_3, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_3_T_2 = dshr(lower_mask_3, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_3_T_3 = dshr(lower_mask_3, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_3_T_4 = dshr(lower_mask_3, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_3_T_5 = dshr(lower_mask_3, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_3_T_6 = dshr(lower_mask_3, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_3_T_7 = dshr(lower_mask_3, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_3_T_8 = or(_f3_fetch_bundle_sfb_masks_3_T, _f3_fetch_bundle_sfb_masks_3_T_1) node _f3_fetch_bundle_sfb_masks_3_T_9 = or(_f3_fetch_bundle_sfb_masks_3_T_8, _f3_fetch_bundle_sfb_masks_3_T_2) node _f3_fetch_bundle_sfb_masks_3_T_10 = or(_f3_fetch_bundle_sfb_masks_3_T_9, _f3_fetch_bundle_sfb_masks_3_T_3) node _f3_fetch_bundle_sfb_masks_3_T_11 = or(_f3_fetch_bundle_sfb_masks_3_T_10, _f3_fetch_bundle_sfb_masks_3_T_4) node _f3_fetch_bundle_sfb_masks_3_T_12 = or(_f3_fetch_bundle_sfb_masks_3_T_11, _f3_fetch_bundle_sfb_masks_3_T_5) node _f3_fetch_bundle_sfb_masks_3_T_13 = or(_f3_fetch_bundle_sfb_masks_3_T_12, _f3_fetch_bundle_sfb_masks_3_T_6) node _f3_fetch_bundle_sfb_masks_3_T_14 = or(_f3_fetch_bundle_sfb_masks_3_T_13, _f3_fetch_bundle_sfb_masks_3_T_7) node _f3_fetch_bundle_sfb_masks_3_T_15 = not(_f3_fetch_bundle_sfb_masks_3_T_14) node _f3_fetch_bundle_sfb_masks_3_T_16 = dshl(upper_mask_3, UInt<1>(0h0)) node _f3_fetch_bundle_sfb_masks_3_T_17 = bits(_f3_fetch_bundle_sfb_masks_3_T_16, 7, 0) node _f3_fetch_bundle_sfb_masks_3_T_18 = dshl(upper_mask_3, UInt<1>(0h1)) node _f3_fetch_bundle_sfb_masks_3_T_19 = bits(_f3_fetch_bundle_sfb_masks_3_T_18, 7, 0) node _f3_fetch_bundle_sfb_masks_3_T_20 = dshl(upper_mask_3, UInt<2>(0h2)) node _f3_fetch_bundle_sfb_masks_3_T_21 = bits(_f3_fetch_bundle_sfb_masks_3_T_20, 7, 0) node _f3_fetch_bundle_sfb_masks_3_T_22 = dshl(upper_mask_3, UInt<2>(0h3)) node _f3_fetch_bundle_sfb_masks_3_T_23 = bits(_f3_fetch_bundle_sfb_masks_3_T_22, 7, 0) node _f3_fetch_bundle_sfb_masks_3_T_24 = dshl(upper_mask_3, UInt<3>(0h4)) node _f3_fetch_bundle_sfb_masks_3_T_25 = bits(_f3_fetch_bundle_sfb_masks_3_T_24, 7, 0) node _f3_fetch_bundle_sfb_masks_3_T_26 = dshl(upper_mask_3, UInt<3>(0h5)) node _f3_fetch_bundle_sfb_masks_3_T_27 = bits(_f3_fetch_bundle_sfb_masks_3_T_26, 7, 0) node _f3_fetch_bundle_sfb_masks_3_T_28 = dshl(upper_mask_3, UInt<3>(0h6)) node _f3_fetch_bundle_sfb_masks_3_T_29 = bits(_f3_fetch_bundle_sfb_masks_3_T_28, 7, 0) node _f3_fetch_bundle_sfb_masks_3_T_30 = dshl(upper_mask_3, UInt<3>(0h7)) node _f3_fetch_bundle_sfb_masks_3_T_31 = bits(_f3_fetch_bundle_sfb_masks_3_T_30, 7, 0) node _f3_fetch_bundle_sfb_masks_3_T_32 = or(_f3_fetch_bundle_sfb_masks_3_T_17, _f3_fetch_bundle_sfb_masks_3_T_19) node _f3_fetch_bundle_sfb_masks_3_T_33 = or(_f3_fetch_bundle_sfb_masks_3_T_32, _f3_fetch_bundle_sfb_masks_3_T_21) node _f3_fetch_bundle_sfb_masks_3_T_34 = or(_f3_fetch_bundle_sfb_masks_3_T_33, _f3_fetch_bundle_sfb_masks_3_T_23) node _f3_fetch_bundle_sfb_masks_3_T_35 = or(_f3_fetch_bundle_sfb_masks_3_T_34, _f3_fetch_bundle_sfb_masks_3_T_25) node _f3_fetch_bundle_sfb_masks_3_T_36 = or(_f3_fetch_bundle_sfb_masks_3_T_35, _f3_fetch_bundle_sfb_masks_3_T_27) node _f3_fetch_bundle_sfb_masks_3_T_37 = or(_f3_fetch_bundle_sfb_masks_3_T_36, _f3_fetch_bundle_sfb_masks_3_T_29) node _f3_fetch_bundle_sfb_masks_3_T_38 = or(_f3_fetch_bundle_sfb_masks_3_T_37, _f3_fetch_bundle_sfb_masks_3_T_31) node _f3_fetch_bundle_sfb_masks_3_T_39 = not(_f3_fetch_bundle_sfb_masks_3_T_38) node _f3_fetch_bundle_sfb_masks_3_T_40 = and(_f3_fetch_bundle_sfb_masks_3_T_15, _f3_fetch_bundle_sfb_masks_3_T_39) connect f3_fetch_bundle.sfb_masks[3], _f3_fetch_bundle_sfb_masks_3_T_40 node _f3_fetch_bundle_shadowable_mask_3_T = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _f3_fetch_bundle_shadowable_mask_3_T_1 = or(_f3_fetch_bundle_shadowable_mask_3_T, bpu_3.io.debug_if) node _f3_fetch_bundle_shadowable_mask_3_T_2 = or(_f3_fetch_bundle_shadowable_mask_3_T_1, bpu_3.io.xcpt_if) node _f3_fetch_bundle_shadowable_mask_3_T_3 = eq(_f3_fetch_bundle_shadowable_mask_3_T_2, UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_3_T_4 = and(_f3_fetch_bundle_shadowable_mask_3_T_3, UInt<1>(0h1)) node _f3_fetch_bundle_shadowable_mask_3_T_5 = eq(f3_mask[3], UInt<1>(0h0)) node _f3_fetch_bundle_shadowable_mask_3_T_6 = or(brsigs_3.shadowable, _f3_fetch_bundle_shadowable_mask_3_T_5) node _f3_fetch_bundle_shadowable_mask_3_T_7 = and(_f3_fetch_bundle_shadowable_mask_3_T_4, _f3_fetch_bundle_shadowable_mask_3_T_6) connect f3_fetch_bundle.shadowable_mask[3], _f3_fetch_bundle_shadowable_mask_3_T_7 connect f3_fetch_bundle.sfb_dests[3], offset_from_aligned_pc_3 node _f3_redirects_3_T = eq(brsigs_3.cfi_type, UInt<3>(0h2)) node _f3_redirects_3_T_1 = eq(brsigs_3.cfi_type, UInt<3>(0h3)) node _f3_redirects_3_T_2 = or(_f3_redirects_3_T, _f3_redirects_3_T_1) node _f3_redirects_3_T_3 = eq(brsigs_3.cfi_type, UInt<3>(0h1)) node _f3_redirects_3_T_4 = and(_f3_redirects_3_T_3, f3_bpd_resp.io.deq.bits.preds[3].taken) node _f3_redirects_3_T_5 = and(_f3_redirects_3_T_4, UInt<1>(0h1)) node _f3_redirects_3_T_6 = or(_f3_redirects_3_T_2, _f3_redirects_3_T_5) node _f3_redirects_3_T_7 = and(f3_mask[3], _f3_redirects_3_T_6) connect f3_redirects[3], _f3_redirects_3_T_7 node _f3_br_mask_3_T = eq(brsigs_3.cfi_type, UInt<3>(0h1)) node _f3_br_mask_3_T_1 = and(f3_mask[3], _f3_br_mask_3_T) connect f3_br_mask[3], _f3_br_mask_3_T_1 connect f3_cfi_types[3], brsigs_3.cfi_type connect f3_call_mask[3], brsigs_3.is_call connect f3_ret_mask[3], brsigs_3.is_ret connect f3_fetch_bundle.bp_debug_if_oh[3], bpu_3.io.debug_if connect f3_fetch_bundle.bp_xcpt_if_oh[3], bpu_3.io.xcpt_if node _T_31 = or(_T_30, f3_redirects[3]) node _T_32 = bits(bank_insts[3], 15, 0) node _T_33 = bits(bank_insts[2], 1, 0) node _T_34 = neq(_T_33, UInt<2>(0h3)) node _T_35 = eq(_T_34, UInt<1>(0h0)) node _T_36 = and(bank_mask[2], _T_35) node _T_37 = eq(_T_36, UInt<1>(0h0)) node _T_38 = bits(_T_32, 1, 0) node _T_39 = neq(_T_38, UInt<2>(0h3)) node _T_40 = eq(_T_39, UInt<1>(0h0)) node _T_41 = and(_T_37, _T_40) node _T_42 = mux(UInt<1>(0h1), _T_41, f3_prev_is_half) node _T_43 = bits(_T_32, 15, 0) node _T_44 = mux(UInt<1>(0h1), _T_43, f3_prev_half) connect f3_fetch_bundle.cfi_type, f3_cfi_types[f3_fetch_bundle.cfi_idx.bits] connect f3_fetch_bundle.cfi_is_call, f3_call_mask[f3_fetch_bundle.cfi_idx.bits] connect f3_fetch_bundle.cfi_is_ret, f3_ret_mask[f3_fetch_bundle.cfi_idx.bits] connect f3_fetch_bundle.cfi_npc_plus4, f3_npc_plus4_mask[f3_fetch_bundle.cfi_idx.bits] connect f3_fetch_bundle.ghist, f3.io.deq.bits.ghist connect f3_fetch_bundle.lhist, f3_bpd_resp.io.deq.bits.lhist connect f3_fetch_bundle.bpd_meta, f3_bpd_resp.io.deq.bits.meta connect f3_fetch_bundle.end_half.valid, _T_42 connect f3_fetch_bundle.end_half.bits, _T_44 node _T_45 = and(f3.io.deq.ready, f3.io.deq.valid) when _T_45 : connect f3_prev_is_half, _T_42 connect f3_prev_half, _T_44 node _T_46 = eq(f3_bpd_resp.io.deq.bits.pc, f3_fetch_bundle.pc) node _T_47 = asUInt(reset) node _T_48 = eq(_T_47, UInt<1>(0h0)) when _T_48 : node _T_49 = eq(_T_46, UInt<1>(0h0)) when _T_49 : printf(clock, UInt<1>(0h1), "Assertion failed\n at frontend.scala:770 assert(f3_bpd_resp.io.deq.bits.pc === f3_fetch_bundle.pc)\n") : printf assert(clock, _T_46, UInt<1>(0h1), "") : assert when f3_clear : connect f3_prev_is_half, UInt<1>(0h0) node _f3_fetch_bundle_cfi_idx_valid_T = or(f3_redirects[0], f3_redirects[1]) node _f3_fetch_bundle_cfi_idx_valid_T_1 = or(_f3_fetch_bundle_cfi_idx_valid_T, f3_redirects[2]) node _f3_fetch_bundle_cfi_idx_valid_T_2 = or(_f3_fetch_bundle_cfi_idx_valid_T_1, f3_redirects[3]) connect f3_fetch_bundle.cfi_idx.valid, _f3_fetch_bundle_cfi_idx_valid_T_2 node _f3_fetch_bundle_cfi_idx_bits_T = mux(f3_redirects[2], UInt<2>(0h2), UInt<2>(0h3)) node _f3_fetch_bundle_cfi_idx_bits_T_1 = mux(f3_redirects[1], UInt<1>(0h1), _f3_fetch_bundle_cfi_idx_bits_T) node _f3_fetch_bundle_cfi_idx_bits_T_2 = mux(f3_redirects[0], UInt<1>(0h0), _f3_fetch_bundle_cfi_idx_bits_T_1) connect f3_fetch_bundle.cfi_idx.bits, _f3_fetch_bundle_cfi_idx_bits_T_2 connect f3_fetch_bundle.ras_top, ras.io.read_addr node _f3_predicted_target_T = or(f3_redirects[0], f3_redirects[1]) node _f3_predicted_target_T_1 = or(_f3_predicted_target_T, f3_redirects[2]) node _f3_predicted_target_T_2 = or(_f3_predicted_target_T_1, f3_redirects[3]) node _f3_predicted_target_T_3 = and(f3_fetch_bundle.cfi_is_ret, UInt<1>(0h1)) node _f3_predicted_target_T_4 = and(_f3_predicted_target_T_3, UInt<1>(0h1)) node _f3_predicted_target_T_5 = mux(f3_redirects[2], UInt<2>(0h2), UInt<2>(0h3)) node _f3_predicted_target_T_6 = mux(f3_redirects[1], UInt<1>(0h1), _f3_predicted_target_T_5) node _f3_predicted_target_T_7 = mux(f3_redirects[0], UInt<1>(0h0), _f3_predicted_target_T_6) node _f3_predicted_target_T_8 = mux(_f3_predicted_target_T_4, ras.io.read_addr, f3_targs[_f3_predicted_target_T_7]) node _f3_predicted_target_T_9 = not(f3_fetch_bundle.pc) node _f3_predicted_target_T_10 = or(_f3_predicted_target_T_9, UInt<3>(0h7)) node _f3_predicted_target_T_11 = not(_f3_predicted_target_T_10) node _f3_predicted_target_T_12 = add(_f3_predicted_target_T_11, UInt<4>(0h8)) node _f3_predicted_target_T_13 = tail(_f3_predicted_target_T_12, 1) node f3_predicted_target = mux(_f3_predicted_target_T_2, _f3_predicted_target_T_8, _f3_predicted_target_T_13) connect f3_fetch_bundle.next_pc, f3_predicted_target node _f3_predicted_ghist_T = dshr(f3_fetch_bundle.br_mask, f3_fetch_bundle.cfi_idx.bits) node _f3_predicted_ghist_T_1 = bits(_f3_predicted_ghist_T, 0, 0) node f3_predicted_ghist_cfi_idx_fixed = bits(f3_fetch_bundle.cfi_idx.bits, 1, 0) node f3_predicted_ghist_cfi_idx_oh = dshl(UInt<1>(0h1), f3_predicted_ghist_cfi_idx_fixed) wire f3_predicted_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} node _f3_predicted_ghist_not_taken_branches_T = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<1>(0h0)) node _f3_predicted_ghist_not_taken_branches_T_1 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<1>(0h1)) node _f3_predicted_ghist_not_taken_branches_T_2 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<2>(0h2)) node _f3_predicted_ghist_not_taken_branches_T_3 = dshr(f3_predicted_ghist_cfi_idx_oh, UInt<2>(0h3)) node _f3_predicted_ghist_not_taken_branches_T_4 = or(_f3_predicted_ghist_not_taken_branches_T, _f3_predicted_ghist_not_taken_branches_T_1) node _f3_predicted_ghist_not_taken_branches_T_5 = or(_f3_predicted_ghist_not_taken_branches_T_4, _f3_predicted_ghist_not_taken_branches_T_2) node _f3_predicted_ghist_not_taken_branches_T_6 = or(_f3_predicted_ghist_not_taken_branches_T_5, _f3_predicted_ghist_not_taken_branches_T_3) node _f3_predicted_ghist_not_taken_branches_T_7 = and(_f3_predicted_ghist_T_1, f3_fetch_bundle.cfi_idx.valid) node _f3_predicted_ghist_not_taken_branches_T_8 = mux(_f3_predicted_ghist_not_taken_branches_T_7, f3_predicted_ghist_cfi_idx_oh, UInt<4>(0h0)) node _f3_predicted_ghist_not_taken_branches_T_9 = not(_f3_predicted_ghist_not_taken_branches_T_8) node _f3_predicted_ghist_not_taken_branches_T_10 = and(_f3_predicted_ghist_not_taken_branches_T_6, _f3_predicted_ghist_not_taken_branches_T_9) node _f3_predicted_ghist_not_taken_branches_T_11 = not(UInt<4>(0h0)) node _f3_predicted_ghist_not_taken_branches_T_12 = mux(f3_fetch_bundle.cfi_idx.valid, _f3_predicted_ghist_not_taken_branches_T_10, _f3_predicted_ghist_not_taken_branches_T_11) node f3_predicted_ghist_not_taken_branches = and(f3_fetch_bundle.br_mask, _f3_predicted_ghist_not_taken_branches_T_12) invalidate f3_predicted_ghist.ras_idx invalidate f3_predicted_ghist.new_saw_branch_taken invalidate f3_predicted_ghist.new_saw_branch_not_taken invalidate f3_predicted_ghist.current_saw_branch_not_taken invalidate f3_predicted_ghist.old_history connect f3_predicted_ghist.current_saw_branch_not_taken, UInt<1>(0h0) node _f3_predicted_ghist_saw_not_taken_branch_T = neq(f3_predicted_ghist_not_taken_branches, UInt<1>(0h0)) node f3_predicted_ghist_saw_not_taken_branch = or(_f3_predicted_ghist_saw_not_taken_branch_T, f3_fetch_bundle.ghist.current_saw_branch_not_taken) node _f3_predicted_ghist_new_history_old_history_T = and(_f3_predicted_ghist_T_1, f3_fetch_bundle.cfi_idx.valid) node _f3_predicted_ghist_new_history_old_history_T_1 = and(_f3_predicted_ghist_new_history_old_history_T, f3_fetch_bundle.cfi_idx.valid) node _f3_predicted_ghist_new_history_old_history_T_2 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_3 = or(_f3_predicted_ghist_new_history_old_history_T_2, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_old_history_T_4 = shl(f3_fetch_bundle.ghist.old_history, 1) node _f3_predicted_ghist_new_history_old_history_T_5 = mux(f3_predicted_ghist_saw_not_taken_branch, _f3_predicted_ghist_new_history_old_history_T_4, f3_fetch_bundle.ghist.old_history) node _f3_predicted_ghist_new_history_old_history_T_6 = mux(_f3_predicted_ghist_new_history_old_history_T_1, _f3_predicted_ghist_new_history_old_history_T_3, _f3_predicted_ghist_new_history_old_history_T_5) connect f3_predicted_ghist.old_history, _f3_predicted_ghist_new_history_old_history_T_6 node _f3_predicted_ghist_new_history_ras_idx_T = and(f3_fetch_bundle.cfi_idx.valid, f3_fetch_bundle.cfi_is_call) node _f3_predicted_ghist_new_history_ras_idx_T_1 = add(f3_fetch_bundle.ghist.ras_idx, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_ras_idx_T_2 = tail(_f3_predicted_ghist_new_history_ras_idx_T_1, 1) node _f3_predicted_ghist_new_history_ras_idx_T_3 = bits(_f3_predicted_ghist_new_history_ras_idx_T_2, 4, 0) node _f3_predicted_ghist_new_history_ras_idx_T_4 = and(f3_fetch_bundle.cfi_idx.valid, f3_fetch_bundle.cfi_is_ret) node _f3_predicted_ghist_new_history_ras_idx_T_5 = sub(f3_fetch_bundle.ghist.ras_idx, UInt<1>(0h1)) node _f3_predicted_ghist_new_history_ras_idx_T_6 = tail(_f3_predicted_ghist_new_history_ras_idx_T_5, 1) node _f3_predicted_ghist_new_history_ras_idx_T_7 = bits(_f3_predicted_ghist_new_history_ras_idx_T_6, 4, 0) node _f3_predicted_ghist_new_history_ras_idx_T_8 = mux(_f3_predicted_ghist_new_history_ras_idx_T_4, _f3_predicted_ghist_new_history_ras_idx_T_7, f3_fetch_bundle.ghist.ras_idx) node _f3_predicted_ghist_new_history_ras_idx_T_9 = mux(_f3_predicted_ghist_new_history_ras_idx_T, _f3_predicted_ghist_new_history_ras_idx_T_3, _f3_predicted_ghist_new_history_ras_idx_T_8) connect f3_predicted_ghist.ras_idx, _f3_predicted_ghist_new_history_ras_idx_T_9 connect ras.io.write_valid, UInt<1>(0h0) node _ras_io_write_addr_T = shl(f3_fetch_bundle.cfi_idx.bits, 1) node _ras_io_write_addr_T_1 = add(f3_aligned_pc, _ras_io_write_addr_T) node _ras_io_write_addr_T_2 = tail(_ras_io_write_addr_T_1, 1) node _ras_io_write_addr_T_3 = mux(f3_fetch_bundle.cfi_npc_plus4, UInt<3>(0h4), UInt<2>(0h2)) node _ras_io_write_addr_T_4 = add(_ras_io_write_addr_T_2, _ras_io_write_addr_T_3) node _ras_io_write_addr_T_5 = tail(_ras_io_write_addr_T_4, 1) connect ras.io.write_addr, _ras_io_write_addr_T_5 node _ras_io_write_idx_T = add(f3_fetch_bundle.ghist.ras_idx, UInt<1>(0h1)) node _ras_io_write_idx_T_1 = tail(_ras_io_write_idx_T, 1) node _ras_io_write_idx_T_2 = bits(_ras_io_write_idx_T_1, 4, 0) connect ras.io.write_idx, _ras_io_write_idx_T_2 node _f3_correct_f1_ghist_T = eq(s1_ghist.old_history, f3_predicted_ghist.old_history) node _f3_correct_f1_ghist_T_1 = eq(s1_ghist.new_saw_branch_not_taken, f3_predicted_ghist.new_saw_branch_not_taken) node _f3_correct_f1_ghist_T_2 = and(_f3_correct_f1_ghist_T, _f3_correct_f1_ghist_T_1) node _f3_correct_f1_ghist_T_3 = eq(s1_ghist.new_saw_branch_taken, f3_predicted_ghist.new_saw_branch_taken) node _f3_correct_f1_ghist_T_4 = and(_f3_correct_f1_ghist_T_2, _f3_correct_f1_ghist_T_3) node _f3_correct_f1_ghist_T_5 = eq(_f3_correct_f1_ghist_T_4, UInt<1>(0h0)) node f3_correct_f1_ghist = and(_f3_correct_f1_ghist_T_5, UInt<1>(0h1)) node _f3_correct_f2_ghist_T = eq(s2_ghist.old_history, f3_predicted_ghist.old_history) node _f3_correct_f2_ghist_T_1 = eq(s2_ghist.new_saw_branch_not_taken, f3_predicted_ghist.new_saw_branch_not_taken) node _f3_correct_f2_ghist_T_2 = and(_f3_correct_f2_ghist_T, _f3_correct_f2_ghist_T_1) node _f3_correct_f2_ghist_T_3 = eq(s2_ghist.new_saw_branch_taken, f3_predicted_ghist.new_saw_branch_taken) node _f3_correct_f2_ghist_T_4 = and(_f3_correct_f2_ghist_T_2, _f3_correct_f2_ghist_T_3) node _f3_correct_f2_ghist_T_5 = eq(_f3_correct_f2_ghist_T_4, UInt<1>(0h0)) node f3_correct_f2_ghist = and(_f3_correct_f2_ghist_T_5, UInt<1>(0h1)) node _T_50 = and(f3.io.deq.valid, f4_ready) when _T_50 : node _T_51 = and(f3_fetch_bundle.cfi_is_call, f3_fetch_bundle.cfi_idx.valid) when _T_51 : connect ras.io.write_valid, UInt<1>(0h1) node _T_52 = or(f3_redirects[0], f3_redirects[1]) node _T_53 = or(_T_52, f3_redirects[2]) node _T_54 = or(_T_53, f3_redirects[3]) when _T_54 : connect f3_prev_is_half, UInt<1>(0h0) node _T_55 = eq(s2_vpc, f3_predicted_target) node _T_56 = and(s2_valid, _T_55) node _T_57 = eq(f3_correct_f2_ghist, UInt<1>(0h0)) node _T_58 = and(_T_56, _T_57) when _T_58 : connect f3.io.enq.bits.ghist.ras_idx, f3_predicted_ghist.ras_idx connect f3.io.enq.bits.ghist.new_saw_branch_taken, f3_predicted_ghist.new_saw_branch_taken connect f3.io.enq.bits.ghist.new_saw_branch_not_taken, f3_predicted_ghist.new_saw_branch_not_taken connect f3.io.enq.bits.ghist.current_saw_branch_not_taken, f3_predicted_ghist.current_saw_branch_not_taken connect f3.io.enq.bits.ghist.old_history, f3_predicted_ghist.old_history else : node _T_59 = eq(s2_valid, UInt<1>(0h0)) node _T_60 = and(_T_59, s1_valid) node _T_61 = eq(s1_vpc, f3_predicted_target) node _T_62 = and(_T_60, _T_61) node _T_63 = eq(f3_correct_f1_ghist, UInt<1>(0h0)) node _T_64 = and(_T_62, _T_63) when _T_64 : connect s2_ghist, f3_predicted_ghist else : node _T_65 = neq(s2_vpc, f3_predicted_target) node _T_66 = or(_T_65, f3_correct_f2_ghist) node _T_67 = and(s2_valid, _T_66) node _T_68 = eq(s2_valid, UInt<1>(0h0)) node _T_69 = and(_T_68, s1_valid) node _T_70 = neq(s1_vpc, f3_predicted_target) node _T_71 = or(_T_70, f3_correct_f1_ghist) node _T_72 = and(_T_69, _T_71) node _T_73 = or(_T_67, _T_72) node _T_74 = eq(s2_valid, UInt<1>(0h0)) node _T_75 = eq(s1_valid, UInt<1>(0h0)) node _T_76 = and(_T_74, _T_75) node _T_77 = or(_T_73, _T_76) when _T_77 : connect f2_clear, UInt<1>(0h1) connect f1_clear, UInt<1>(0h1) node _s0_valid_T_11 = or(f3_fetch_bundle.xcpt_pf_if, f3_fetch_bundle.xcpt_ae_if) node _s0_valid_T_12 = eq(_s0_valid_T_11, UInt<1>(0h0)) connect s0_valid, _s0_valid_T_12 connect s0_vpc, f3_predicted_target connect s0_is_replay, UInt<1>(0h0) connect s0_ghist, f3_predicted_ghist connect s0_tsrc, UInt<2>(0h2) connect f3_fetch_bundle.fsrc, UInt<2>(0h2) inst f4_btb_corrections of Queue2_BranchPredictionUpdate_1 connect f4_btb_corrections.clock, clock connect f4_btb_corrections.reset, reset node _f4_btb_corrections_io_enq_valid_T = and(f3.io.deq.ready, f3.io.deq.valid) node _f4_btb_corrections_io_enq_valid_T_1 = or(f3_btb_mispredicts[0], f3_btb_mispredicts[1]) node _f4_btb_corrections_io_enq_valid_T_2 = or(_f4_btb_corrections_io_enq_valid_T_1, f3_btb_mispredicts[2]) node _f4_btb_corrections_io_enq_valid_T_3 = or(_f4_btb_corrections_io_enq_valid_T_2, f3_btb_mispredicts[3]) node _f4_btb_corrections_io_enq_valid_T_4 = and(_f4_btb_corrections_io_enq_valid_T, _f4_btb_corrections_io_enq_valid_T_3) node _f4_btb_corrections_io_enq_valid_T_5 = and(_f4_btb_corrections_io_enq_valid_T_4, UInt<1>(0h1)) connect f4_btb_corrections.io.enq.valid, _f4_btb_corrections_io_enq_valid_T_5 invalidate f4_btb_corrections.io.enq.bits.meta[0] invalidate f4_btb_corrections.io.enq.bits.target invalidate f4_btb_corrections.io.enq.bits.lhist[0] invalidate f4_btb_corrections.io.enq.bits.ghist.ras_idx invalidate f4_btb_corrections.io.enq.bits.ghist.new_saw_branch_taken invalidate f4_btb_corrections.io.enq.bits.ghist.new_saw_branch_not_taken invalidate f4_btb_corrections.io.enq.bits.ghist.current_saw_branch_not_taken invalidate f4_btb_corrections.io.enq.bits.ghist.old_history invalidate f4_btb_corrections.io.enq.bits.cfi_is_jalr invalidate f4_btb_corrections.io.enq.bits.cfi_is_jal invalidate f4_btb_corrections.io.enq.bits.cfi_is_br invalidate f4_btb_corrections.io.enq.bits.cfi_mispredicted invalidate f4_btb_corrections.io.enq.bits.cfi_taken invalidate f4_btb_corrections.io.enq.bits.cfi_idx.bits invalidate f4_btb_corrections.io.enq.bits.cfi_idx.valid invalidate f4_btb_corrections.io.enq.bits.br_mask invalidate f4_btb_corrections.io.enq.bits.pc invalidate f4_btb_corrections.io.enq.bits.btb_mispredicts invalidate f4_btb_corrections.io.enq.bits.is_repair_update invalidate f4_btb_corrections.io.enq.bits.is_mispredict_update connect f4_btb_corrections.io.enq.bits.is_mispredict_update, UInt<1>(0h0) connect f4_btb_corrections.io.enq.bits.is_repair_update, UInt<1>(0h0) node f4_btb_corrections_io_enq_bits_btb_mispredicts_lo = cat(f3_btb_mispredicts[1], f3_btb_mispredicts[0]) node f4_btb_corrections_io_enq_bits_btb_mispredicts_hi = cat(f3_btb_mispredicts[3], f3_btb_mispredicts[2]) node _f4_btb_corrections_io_enq_bits_btb_mispredicts_T = cat(f4_btb_corrections_io_enq_bits_btb_mispredicts_hi, f4_btb_corrections_io_enq_bits_btb_mispredicts_lo) connect f4_btb_corrections.io.enq.bits.btb_mispredicts, _f4_btb_corrections_io_enq_bits_btb_mispredicts_T connect f4_btb_corrections.io.enq.bits.pc, f3_fetch_bundle.pc connect f4_btb_corrections.io.enq.bits.ghist.ras_idx, f3_fetch_bundle.ghist.ras_idx connect f4_btb_corrections.io.enq.bits.ghist.new_saw_branch_taken, f3_fetch_bundle.ghist.new_saw_branch_taken connect f4_btb_corrections.io.enq.bits.ghist.new_saw_branch_not_taken, f3_fetch_bundle.ghist.new_saw_branch_not_taken connect f4_btb_corrections.io.enq.bits.ghist.current_saw_branch_not_taken, f3_fetch_bundle.ghist.current_saw_branch_not_taken connect f4_btb_corrections.io.enq.bits.ghist.old_history, f3_fetch_bundle.ghist.old_history connect f4_btb_corrections.io.enq.bits.lhist[0], f3_fetch_bundle.lhist[0] connect f4_btb_corrections.io.enq.bits.meta[0], f3_fetch_bundle.bpd_meta[0] wire f4_clear : UInt<1> connect f4_clear, UInt<1>(0h0) node _T_78 = asUInt(reset) node _T_79 = or(_T_78, f4_clear) inst f4 of Queue1_FetchBundle_1 connect f4.clock, clock connect f4.reset, _T_79 inst fb of FetchBuffer_1 connect fb.clock, clock connect fb.reset, reset inst ftq of FetchTargetQueue_1 connect ftq.clock, clock connect ftq.reset, reset node f4_shadowable_masks_lo = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_hi = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node _f4_shadowable_masks_T = cat(f4_shadowable_masks_hi, f4_shadowable_masks_lo) node _f4_shadowable_masks_T_1 = bits(f4.io.deq.bits.sfb_masks[0], 3, 0) node _f4_shadowable_masks_T_2 = not(_f4_shadowable_masks_T_1) node _f4_shadowable_masks_T_3 = or(_f4_shadowable_masks_T, _f4_shadowable_masks_T_2) node f4_shadowable_masks_lo_1 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_hi_1 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node _f4_shadowable_masks_T_4 = cat(f4_shadowable_masks_hi_1, f4_shadowable_masks_lo_1) node _f4_shadowable_masks_T_5 = bits(f4.io.deq.bits.sfb_masks[1], 3, 0) node _f4_shadowable_masks_T_6 = not(_f4_shadowable_masks_T_5) node _f4_shadowable_masks_T_7 = or(_f4_shadowable_masks_T_4, _f4_shadowable_masks_T_6) node f4_shadowable_masks_lo_2 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_hi_2 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node _f4_shadowable_masks_T_8 = cat(f4_shadowable_masks_hi_2, f4_shadowable_masks_lo_2) node _f4_shadowable_masks_T_9 = bits(f4.io.deq.bits.sfb_masks[2], 3, 0) node _f4_shadowable_masks_T_10 = not(_f4_shadowable_masks_T_9) node _f4_shadowable_masks_T_11 = or(_f4_shadowable_masks_T_8, _f4_shadowable_masks_T_10) node f4_shadowable_masks_lo_3 = cat(f4.io.deq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[0]) node f4_shadowable_masks_hi_3 = cat(f4.io.deq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[2]) node _f4_shadowable_masks_T_12 = cat(f4_shadowable_masks_hi_3, f4_shadowable_masks_lo_3) node _f4_shadowable_masks_T_13 = bits(f4.io.deq.bits.sfb_masks[3], 3, 0) node _f4_shadowable_masks_T_14 = not(_f4_shadowable_masks_T_13) node _f4_shadowable_masks_T_15 = or(_f4_shadowable_masks_T_12, _f4_shadowable_masks_T_14) wire f4_shadowable_masks : UInt<4>[4] connect f4_shadowable_masks[0], _f4_shadowable_masks_T_3 connect f4_shadowable_masks[1], _f4_shadowable_masks_T_7 connect f4_shadowable_masks[2], _f4_shadowable_masks_T_11 connect f4_shadowable_masks[3], _f4_shadowable_masks_T_15 node f3_shadowable_masks_lo = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_hi = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node _f3_shadowable_masks_T = cat(f3_shadowable_masks_hi, f3_shadowable_masks_lo) node _f3_shadowable_masks_T_1 = mux(f4.io.enq.valid, _f3_shadowable_masks_T, UInt<1>(0h0)) node _f3_shadowable_masks_T_2 = bits(f4.io.deq.bits.sfb_masks[0], 7, 4) node _f3_shadowable_masks_T_3 = not(_f3_shadowable_masks_T_2) node _f3_shadowable_masks_T_4 = or(_f3_shadowable_masks_T_1, _f3_shadowable_masks_T_3) node f3_shadowable_masks_lo_1 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_hi_1 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node _f3_shadowable_masks_T_5 = cat(f3_shadowable_masks_hi_1, f3_shadowable_masks_lo_1) node _f3_shadowable_masks_T_6 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_5, UInt<1>(0h0)) node _f3_shadowable_masks_T_7 = bits(f4.io.deq.bits.sfb_masks[1], 7, 4) node _f3_shadowable_masks_T_8 = not(_f3_shadowable_masks_T_7) node _f3_shadowable_masks_T_9 = or(_f3_shadowable_masks_T_6, _f3_shadowable_masks_T_8) node f3_shadowable_masks_lo_2 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_hi_2 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node _f3_shadowable_masks_T_10 = cat(f3_shadowable_masks_hi_2, f3_shadowable_masks_lo_2) node _f3_shadowable_masks_T_11 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_10, UInt<1>(0h0)) node _f3_shadowable_masks_T_12 = bits(f4.io.deq.bits.sfb_masks[2], 7, 4) node _f3_shadowable_masks_T_13 = not(_f3_shadowable_masks_T_12) node _f3_shadowable_masks_T_14 = or(_f3_shadowable_masks_T_11, _f3_shadowable_masks_T_13) node f3_shadowable_masks_lo_3 = cat(f4.io.enq.bits.shadowable_mask[1], f4.io.enq.bits.shadowable_mask[0]) node f3_shadowable_masks_hi_3 = cat(f4.io.enq.bits.shadowable_mask[3], f4.io.enq.bits.shadowable_mask[2]) node _f3_shadowable_masks_T_15 = cat(f3_shadowable_masks_hi_3, f3_shadowable_masks_lo_3) node _f3_shadowable_masks_T_16 = mux(f4.io.enq.valid, _f3_shadowable_masks_T_15, UInt<1>(0h0)) node _f3_shadowable_masks_T_17 = bits(f4.io.deq.bits.sfb_masks[3], 7, 4) node _f3_shadowable_masks_T_18 = not(_f3_shadowable_masks_T_17) node _f3_shadowable_masks_T_19 = or(_f3_shadowable_masks_T_16, _f3_shadowable_masks_T_18) wire f3_shadowable_masks : UInt<4>[4] connect f3_shadowable_masks[0], _f3_shadowable_masks_T_4 connect f3_shadowable_masks[1], _f3_shadowable_masks_T_9 connect f3_shadowable_masks[2], _f3_shadowable_masks_T_14 connect f3_shadowable_masks[3], _f3_shadowable_masks_T_19 node _f4_sfbs_T = not(f4_shadowable_masks[0]) node _f4_sfbs_T_1 = eq(_f4_sfbs_T, UInt<1>(0h0)) node _f4_sfbs_T_2 = not(f3_shadowable_masks[0]) node _f4_sfbs_T_3 = eq(_f4_sfbs_T_2, UInt<1>(0h0)) node _f4_sfbs_T_4 = and(_f4_sfbs_T_1, _f4_sfbs_T_3) node _f4_sfbs_T_5 = and(_f4_sfbs_T_4, f4.io.deq.bits.sfbs[0]) node _f4_sfbs_T_6 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<1>(0h0)) node _f4_sfbs_T_7 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_6) node _f4_sfbs_T_8 = eq(_f4_sfbs_T_7, UInt<1>(0h0)) node _f4_sfbs_T_9 = and(_f4_sfbs_T_5, _f4_sfbs_T_8) node _f4_sfbs_T_10 = eq(f4.io.deq.bits.sfb_dests[0], UInt<1>(0h0)) node _f4_sfbs_T_11 = eq(_T_42, UInt<1>(0h0)) node _f4_sfbs_T_12 = eq(f4.io.deq.bits.sfb_dests[0], UInt<4>(0h8)) node _f4_sfbs_T_13 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_14 = mux(_f4_sfbs_T_12, _f4_sfbs_T_13, UInt<1>(0h1)) node _f4_sfbs_T_15 = mux(_f4_sfbs_T_10, _f4_sfbs_T_11, _f4_sfbs_T_14) node _f4_sfbs_T_16 = and(_f4_sfbs_T_9, _f4_sfbs_T_15) node _f4_sfbs_T_17 = and(UInt<1>(0h0), _f4_sfbs_T_16) node _f4_sfbs_T_18 = not(f4_shadowable_masks[1]) node _f4_sfbs_T_19 = eq(_f4_sfbs_T_18, UInt<1>(0h0)) node _f4_sfbs_T_20 = not(f3_shadowable_masks[1]) node _f4_sfbs_T_21 = eq(_f4_sfbs_T_20, UInt<1>(0h0)) node _f4_sfbs_T_22 = and(_f4_sfbs_T_19, _f4_sfbs_T_21) node _f4_sfbs_T_23 = and(_f4_sfbs_T_22, f4.io.deq.bits.sfbs[1]) node _f4_sfbs_T_24 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<1>(0h1)) node _f4_sfbs_T_25 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_24) node _f4_sfbs_T_26 = eq(_f4_sfbs_T_25, UInt<1>(0h0)) node _f4_sfbs_T_27 = and(_f4_sfbs_T_23, _f4_sfbs_T_26) node _f4_sfbs_T_28 = eq(f4.io.deq.bits.sfb_dests[1], UInt<1>(0h0)) node _f4_sfbs_T_29 = eq(_T_42, UInt<1>(0h0)) node _f4_sfbs_T_30 = eq(f4.io.deq.bits.sfb_dests[1], UInt<4>(0h8)) node _f4_sfbs_T_31 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_32 = mux(_f4_sfbs_T_30, _f4_sfbs_T_31, UInt<1>(0h1)) node _f4_sfbs_T_33 = mux(_f4_sfbs_T_28, _f4_sfbs_T_29, _f4_sfbs_T_32) node _f4_sfbs_T_34 = and(_f4_sfbs_T_27, _f4_sfbs_T_33) node _f4_sfbs_T_35 = and(UInt<1>(0h0), _f4_sfbs_T_34) node _f4_sfbs_T_36 = not(f4_shadowable_masks[2]) node _f4_sfbs_T_37 = eq(_f4_sfbs_T_36, UInt<1>(0h0)) node _f4_sfbs_T_38 = not(f3_shadowable_masks[2]) node _f4_sfbs_T_39 = eq(_f4_sfbs_T_38, UInt<1>(0h0)) node _f4_sfbs_T_40 = and(_f4_sfbs_T_37, _f4_sfbs_T_39) node _f4_sfbs_T_41 = and(_f4_sfbs_T_40, f4.io.deq.bits.sfbs[2]) node _f4_sfbs_T_42 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<2>(0h2)) node _f4_sfbs_T_43 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_42) node _f4_sfbs_T_44 = eq(_f4_sfbs_T_43, UInt<1>(0h0)) node _f4_sfbs_T_45 = and(_f4_sfbs_T_41, _f4_sfbs_T_44) node _f4_sfbs_T_46 = eq(f4.io.deq.bits.sfb_dests[2], UInt<1>(0h0)) node _f4_sfbs_T_47 = eq(_T_42, UInt<1>(0h0)) node _f4_sfbs_T_48 = eq(f4.io.deq.bits.sfb_dests[2], UInt<4>(0h8)) node _f4_sfbs_T_49 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_50 = mux(_f4_sfbs_T_48, _f4_sfbs_T_49, UInt<1>(0h1)) node _f4_sfbs_T_51 = mux(_f4_sfbs_T_46, _f4_sfbs_T_47, _f4_sfbs_T_50) node _f4_sfbs_T_52 = and(_f4_sfbs_T_45, _f4_sfbs_T_51) node _f4_sfbs_T_53 = and(UInt<1>(0h0), _f4_sfbs_T_52) node _f4_sfbs_T_54 = not(f4_shadowable_masks[3]) node _f4_sfbs_T_55 = eq(_f4_sfbs_T_54, UInt<1>(0h0)) node _f4_sfbs_T_56 = not(f3_shadowable_masks[3]) node _f4_sfbs_T_57 = eq(_f4_sfbs_T_56, UInt<1>(0h0)) node _f4_sfbs_T_58 = and(_f4_sfbs_T_55, _f4_sfbs_T_57) node _f4_sfbs_T_59 = and(_f4_sfbs_T_58, f4.io.deq.bits.sfbs[3]) node _f4_sfbs_T_60 = eq(f4.io.deq.bits.cfi_idx.bits, UInt<2>(0h3)) node _f4_sfbs_T_61 = and(f4.io.deq.bits.cfi_idx.valid, _f4_sfbs_T_60) node _f4_sfbs_T_62 = eq(_f4_sfbs_T_61, UInt<1>(0h0)) node _f4_sfbs_T_63 = and(_f4_sfbs_T_59, _f4_sfbs_T_62) node _f4_sfbs_T_64 = eq(f4.io.deq.bits.sfb_dests[3], UInt<1>(0h0)) node _f4_sfbs_T_65 = eq(_T_42, UInt<1>(0h0)) node _f4_sfbs_T_66 = eq(f4.io.deq.bits.sfb_dests[3], UInt<4>(0h8)) node _f4_sfbs_T_67 = eq(f4.io.deq.bits.end_half.valid, UInt<1>(0h0)) node _f4_sfbs_T_68 = mux(_f4_sfbs_T_66, _f4_sfbs_T_67, UInt<1>(0h1)) node _f4_sfbs_T_69 = mux(_f4_sfbs_T_64, _f4_sfbs_T_65, _f4_sfbs_T_68) node _f4_sfbs_T_70 = and(_f4_sfbs_T_63, _f4_sfbs_T_69) node _f4_sfbs_T_71 = and(UInt<1>(0h0), _f4_sfbs_T_70) wire f4_sfbs : UInt<1>[4] connect f4_sfbs[0], _f4_sfbs_T_17 connect f4_sfbs[1], _f4_sfbs_T_35 connect f4_sfbs[2], _f4_sfbs_T_53 connect f4_sfbs[3], _f4_sfbs_T_71 node _f4_sfb_valid_T = or(f4_sfbs[0], f4_sfbs[1]) node _f4_sfb_valid_T_1 = or(_f4_sfb_valid_T, f4_sfbs[2]) node _f4_sfb_valid_T_2 = or(_f4_sfb_valid_T_1, f4_sfbs[3]) node f4_sfb_valid = and(_f4_sfb_valid_T_2, f4.io.deq.valid) node _f4_sfb_idx_T = mux(f4_sfbs[2], UInt<2>(0h2), UInt<2>(0h3)) node _f4_sfb_idx_T_1 = mux(f4_sfbs[1], UInt<1>(0h1), _f4_sfb_idx_T) node f4_sfb_idx = mux(f4_sfbs[0], UInt<1>(0h0), _f4_sfb_idx_T_1) node _f4_delay_T = or(f4.io.deq.bits.sfbs[0], f4.io.deq.bits.sfbs[1]) node _f4_delay_T_1 = or(_f4_delay_T, f4.io.deq.bits.sfbs[2]) node _f4_delay_T_2 = or(_f4_delay_T_1, f4.io.deq.bits.sfbs[3]) node _f4_delay_T_3 = eq(f4.io.deq.bits.cfi_idx.valid, UInt<1>(0h0)) node _f4_delay_T_4 = and(_f4_delay_T_2, _f4_delay_T_3) node _f4_delay_T_5 = eq(f4.io.enq.valid, UInt<1>(0h0)) node _f4_delay_T_6 = and(_f4_delay_T_4, _f4_delay_T_5) node _f4_delay_T_7 = eq(f4.io.deq.bits.xcpt_pf_if, UInt<1>(0h0)) node _f4_delay_T_8 = and(_f4_delay_T_6, _f4_delay_T_7) node _f4_delay_T_9 = eq(f4.io.deq.bits.xcpt_ae_if, UInt<1>(0h0)) node f4_delay = and(_f4_delay_T_8, _f4_delay_T_9) when f4_sfb_valid : node _T_80 = bits(f4.io.deq.bits.sfb_masks[f4_sfb_idx], 7, 4) node _T_81 = bits(_T_80, 0, 0) node _T_82 = bits(_T_80, 1, 1) node _T_83 = bits(_T_80, 2, 2) node _T_84 = bits(_T_80, 3, 3) connect f3_shadowed_mask[0], _T_81 connect f3_shadowed_mask[1], _T_82 connect f3_shadowed_mask[2], _T_83 connect f3_shadowed_mask[3], _T_84 else : wire _WIRE : UInt<1>[4] connect _WIRE[0], UInt<1>(0h0) connect _WIRE[1], UInt<1>(0h0) connect _WIRE[2], UInt<1>(0h0) connect _WIRE[3], UInt<1>(0h0) connect f3_shadowed_mask, _WIRE connect f4_ready, f4.io.enq.ready node _f4_io_enq_valid_T = eq(f3_clear, UInt<1>(0h0)) node _f4_io_enq_valid_T_1 = and(f3.io.deq.valid, _f4_io_enq_valid_T) connect f4.io.enq.valid, _f4_io_enq_valid_T_1 connect f4.io.enq.bits.tsrc, f3_fetch_bundle.tsrc connect f4.io.enq.bits.fsrc, f3_fetch_bundle.fsrc connect f4.io.enq.bits.bpd_meta[0], f3_fetch_bundle.bpd_meta[0] connect f4.io.enq.bits.end_half.bits, f3_fetch_bundle.end_half.bits connect f4.io.enq.bits.end_half.valid, f3_fetch_bundle.end_half.valid connect f4.io.enq.bits.bp_xcpt_if_oh[0], f3_fetch_bundle.bp_xcpt_if_oh[0] connect f4.io.enq.bits.bp_xcpt_if_oh[1], f3_fetch_bundle.bp_xcpt_if_oh[1] connect f4.io.enq.bits.bp_xcpt_if_oh[2], f3_fetch_bundle.bp_xcpt_if_oh[2] connect f4.io.enq.bits.bp_xcpt_if_oh[3], f3_fetch_bundle.bp_xcpt_if_oh[3] connect f4.io.enq.bits.bp_debug_if_oh[0], f3_fetch_bundle.bp_debug_if_oh[0] connect f4.io.enq.bits.bp_debug_if_oh[1], f3_fetch_bundle.bp_debug_if_oh[1] connect f4.io.enq.bits.bp_debug_if_oh[2], f3_fetch_bundle.bp_debug_if_oh[2] connect f4.io.enq.bits.bp_debug_if_oh[3], f3_fetch_bundle.bp_debug_if_oh[3] connect f4.io.enq.bits.xcpt_ae_if, f3_fetch_bundle.xcpt_ae_if connect f4.io.enq.bits.xcpt_pf_if, f3_fetch_bundle.xcpt_pf_if connect f4.io.enq.bits.lhist[0], f3_fetch_bundle.lhist[0] connect f4.io.enq.bits.ghist.ras_idx, f3_fetch_bundle.ghist.ras_idx connect f4.io.enq.bits.ghist.new_saw_branch_taken, f3_fetch_bundle.ghist.new_saw_branch_taken connect f4.io.enq.bits.ghist.new_saw_branch_not_taken, f3_fetch_bundle.ghist.new_saw_branch_not_taken connect f4.io.enq.bits.ghist.current_saw_branch_not_taken, f3_fetch_bundle.ghist.current_saw_branch_not_taken connect f4.io.enq.bits.ghist.old_history, f3_fetch_bundle.ghist.old_history connect f4.io.enq.bits.br_mask, f3_fetch_bundle.br_mask connect f4.io.enq.bits.mask, f3_fetch_bundle.mask connect f4.io.enq.bits.ftq_idx, f3_fetch_bundle.ftq_idx connect f4.io.enq.bits.ras_top, f3_fetch_bundle.ras_top connect f4.io.enq.bits.cfi_npc_plus4, f3_fetch_bundle.cfi_npc_plus4 connect f4.io.enq.bits.cfi_is_ret, f3_fetch_bundle.cfi_is_ret connect f4.io.enq.bits.cfi_is_call, f3_fetch_bundle.cfi_is_call connect f4.io.enq.bits.cfi_type, f3_fetch_bundle.cfi_type connect f4.io.enq.bits.cfi_idx.bits, f3_fetch_bundle.cfi_idx.bits connect f4.io.enq.bits.cfi_idx.valid, f3_fetch_bundle.cfi_idx.valid connect f4.io.enq.bits.shadowed_mask[0], f3_fetch_bundle.shadowed_mask[0] connect f4.io.enq.bits.shadowed_mask[1], f3_fetch_bundle.shadowed_mask[1] connect f4.io.enq.bits.shadowed_mask[2], f3_fetch_bundle.shadowed_mask[2] connect f4.io.enq.bits.shadowed_mask[3], f3_fetch_bundle.shadowed_mask[3] connect f4.io.enq.bits.shadowable_mask[0], f3_fetch_bundle.shadowable_mask[0] connect f4.io.enq.bits.shadowable_mask[1], f3_fetch_bundle.shadowable_mask[1] connect f4.io.enq.bits.shadowable_mask[2], f3_fetch_bundle.shadowable_mask[2] connect f4.io.enq.bits.shadowable_mask[3], f3_fetch_bundle.shadowable_mask[3] connect f4.io.enq.bits.sfb_dests[0], f3_fetch_bundle.sfb_dests[0] connect f4.io.enq.bits.sfb_dests[1], f3_fetch_bundle.sfb_dests[1] connect f4.io.enq.bits.sfb_dests[2], f3_fetch_bundle.sfb_dests[2] connect f4.io.enq.bits.sfb_dests[3], f3_fetch_bundle.sfb_dests[3] connect f4.io.enq.bits.sfb_masks[0], f3_fetch_bundle.sfb_masks[0] connect f4.io.enq.bits.sfb_masks[1], f3_fetch_bundle.sfb_masks[1] connect f4.io.enq.bits.sfb_masks[2], f3_fetch_bundle.sfb_masks[2] connect f4.io.enq.bits.sfb_masks[3], f3_fetch_bundle.sfb_masks[3] connect f4.io.enq.bits.sfbs[0], f3_fetch_bundle.sfbs[0] connect f4.io.enq.bits.sfbs[1], f3_fetch_bundle.sfbs[1] connect f4.io.enq.bits.sfbs[2], f3_fetch_bundle.sfbs[2] connect f4.io.enq.bits.sfbs[3], f3_fetch_bundle.sfbs[3] connect f4.io.enq.bits.exp_insts[0], f3_fetch_bundle.exp_insts[0] connect f4.io.enq.bits.exp_insts[1], f3_fetch_bundle.exp_insts[1] connect f4.io.enq.bits.exp_insts[2], f3_fetch_bundle.exp_insts[2] connect f4.io.enq.bits.exp_insts[3], f3_fetch_bundle.exp_insts[3] connect f4.io.enq.bits.insts[0], f3_fetch_bundle.insts[0] connect f4.io.enq.bits.insts[1], f3_fetch_bundle.insts[1] connect f4.io.enq.bits.insts[2], f3_fetch_bundle.insts[2] connect f4.io.enq.bits.insts[3], f3_fetch_bundle.insts[3] connect f4.io.enq.bits.edge_inst[0], f3_fetch_bundle.edge_inst[0] connect f4.io.enq.bits.next_pc, f3_fetch_bundle.next_pc connect f4.io.enq.bits.pc, f3_fetch_bundle.pc node _f4_io_deq_ready_T = and(fb.io.enq.ready, ftq.io.enq.ready) node _f4_io_deq_ready_T_1 = eq(f4_delay, UInt<1>(0h0)) node _f4_io_deq_ready_T_2 = and(_f4_io_deq_ready_T, _f4_io_deq_ready_T_1) connect f4.io.deq.ready, _f4_io_deq_ready_T_2 node _fb_io_enq_valid_T = and(f4.io.deq.valid, ftq.io.enq.ready) node _fb_io_enq_valid_T_1 = eq(f4_delay, UInt<1>(0h0)) node _fb_io_enq_valid_T_2 = and(_fb_io_enq_valid_T, _fb_io_enq_valid_T_1) connect fb.io.enq.valid, _fb_io_enq_valid_T_2 connect fb.io.enq.bits.tsrc, f4.io.deq.bits.tsrc connect fb.io.enq.bits.fsrc, f4.io.deq.bits.fsrc connect fb.io.enq.bits.bpd_meta[0], f4.io.deq.bits.bpd_meta[0] connect fb.io.enq.bits.end_half.bits, f4.io.deq.bits.end_half.bits connect fb.io.enq.bits.end_half.valid, f4.io.deq.bits.end_half.valid connect fb.io.enq.bits.bp_xcpt_if_oh[0], f4.io.deq.bits.bp_xcpt_if_oh[0] connect fb.io.enq.bits.bp_xcpt_if_oh[1], f4.io.deq.bits.bp_xcpt_if_oh[1] connect fb.io.enq.bits.bp_xcpt_if_oh[2], f4.io.deq.bits.bp_xcpt_if_oh[2] connect fb.io.enq.bits.bp_xcpt_if_oh[3], f4.io.deq.bits.bp_xcpt_if_oh[3] connect fb.io.enq.bits.bp_debug_if_oh[0], f4.io.deq.bits.bp_debug_if_oh[0] connect fb.io.enq.bits.bp_debug_if_oh[1], f4.io.deq.bits.bp_debug_if_oh[1] connect fb.io.enq.bits.bp_debug_if_oh[2], f4.io.deq.bits.bp_debug_if_oh[2] connect fb.io.enq.bits.bp_debug_if_oh[3], f4.io.deq.bits.bp_debug_if_oh[3] connect fb.io.enq.bits.xcpt_ae_if, f4.io.deq.bits.xcpt_ae_if connect fb.io.enq.bits.xcpt_pf_if, f4.io.deq.bits.xcpt_pf_if connect fb.io.enq.bits.lhist[0], f4.io.deq.bits.lhist[0] connect fb.io.enq.bits.ghist.ras_idx, f4.io.deq.bits.ghist.ras_idx connect fb.io.enq.bits.ghist.new_saw_branch_taken, f4.io.deq.bits.ghist.new_saw_branch_taken connect fb.io.enq.bits.ghist.new_saw_branch_not_taken, f4.io.deq.bits.ghist.new_saw_branch_not_taken connect fb.io.enq.bits.ghist.current_saw_branch_not_taken, f4.io.deq.bits.ghist.current_saw_branch_not_taken connect fb.io.enq.bits.ghist.old_history, f4.io.deq.bits.ghist.old_history connect fb.io.enq.bits.br_mask, f4.io.deq.bits.br_mask connect fb.io.enq.bits.mask, f4.io.deq.bits.mask connect fb.io.enq.bits.ftq_idx, f4.io.deq.bits.ftq_idx connect fb.io.enq.bits.ras_top, f4.io.deq.bits.ras_top connect fb.io.enq.bits.cfi_npc_plus4, f4.io.deq.bits.cfi_npc_plus4 connect fb.io.enq.bits.cfi_is_ret, f4.io.deq.bits.cfi_is_ret connect fb.io.enq.bits.cfi_is_call, f4.io.deq.bits.cfi_is_call connect fb.io.enq.bits.cfi_type, f4.io.deq.bits.cfi_type connect fb.io.enq.bits.cfi_idx.bits, f4.io.deq.bits.cfi_idx.bits connect fb.io.enq.bits.cfi_idx.valid, f4.io.deq.bits.cfi_idx.valid connect fb.io.enq.bits.shadowed_mask[0], f4.io.deq.bits.shadowed_mask[0] connect fb.io.enq.bits.shadowed_mask[1], f4.io.deq.bits.shadowed_mask[1] connect fb.io.enq.bits.shadowed_mask[2], f4.io.deq.bits.shadowed_mask[2] connect fb.io.enq.bits.shadowed_mask[3], f4.io.deq.bits.shadowed_mask[3] connect fb.io.enq.bits.shadowable_mask[0], f4.io.deq.bits.shadowable_mask[0] connect fb.io.enq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[1] connect fb.io.enq.bits.shadowable_mask[2], f4.io.deq.bits.shadowable_mask[2] connect fb.io.enq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[3] connect fb.io.enq.bits.sfb_dests[0], f4.io.deq.bits.sfb_dests[0] connect fb.io.enq.bits.sfb_dests[1], f4.io.deq.bits.sfb_dests[1] connect fb.io.enq.bits.sfb_dests[2], f4.io.deq.bits.sfb_dests[2] connect fb.io.enq.bits.sfb_dests[3], f4.io.deq.bits.sfb_dests[3] connect fb.io.enq.bits.sfb_masks[0], f4.io.deq.bits.sfb_masks[0] connect fb.io.enq.bits.sfb_masks[1], f4.io.deq.bits.sfb_masks[1] connect fb.io.enq.bits.sfb_masks[2], f4.io.deq.bits.sfb_masks[2] connect fb.io.enq.bits.sfb_masks[3], f4.io.deq.bits.sfb_masks[3] connect fb.io.enq.bits.sfbs[0], f4.io.deq.bits.sfbs[0] connect fb.io.enq.bits.sfbs[1], f4.io.deq.bits.sfbs[1] connect fb.io.enq.bits.sfbs[2], f4.io.deq.bits.sfbs[2] connect fb.io.enq.bits.sfbs[3], f4.io.deq.bits.sfbs[3] connect fb.io.enq.bits.exp_insts[0], f4.io.deq.bits.exp_insts[0] connect fb.io.enq.bits.exp_insts[1], f4.io.deq.bits.exp_insts[1] connect fb.io.enq.bits.exp_insts[2], f4.io.deq.bits.exp_insts[2] connect fb.io.enq.bits.exp_insts[3], f4.io.deq.bits.exp_insts[3] connect fb.io.enq.bits.insts[0], f4.io.deq.bits.insts[0] connect fb.io.enq.bits.insts[1], f4.io.deq.bits.insts[1] connect fb.io.enq.bits.insts[2], f4.io.deq.bits.insts[2] connect fb.io.enq.bits.insts[3], f4.io.deq.bits.insts[3] connect fb.io.enq.bits.edge_inst[0], f4.io.deq.bits.edge_inst[0] connect fb.io.enq.bits.next_pc, f4.io.deq.bits.next_pc connect fb.io.enq.bits.pc, f4.io.deq.bits.pc connect fb.io.enq.bits.ftq_idx, ftq.io.enq_idx node _T_85 = dshl(UInt<1>(0h1), f4_sfb_idx) node _T_86 = mux(f4_sfb_valid, _T_85, UInt<4>(0h0)) node _T_87 = bits(_T_86, 0, 0) node _T_88 = bits(_T_86, 1, 1) node _T_89 = bits(_T_86, 2, 2) node _T_90 = bits(_T_86, 3, 3) connect fb.io.enq.bits.sfbs[0], _T_87 connect fb.io.enq.bits.sfbs[1], _T_88 connect fb.io.enq.bits.sfbs[2], _T_89 connect fb.io.enq.bits.sfbs[3], _T_90 node _T_91 = bits(f4.io.deq.bits.sfb_masks[f4_sfb_idx], 3, 0) node _T_92 = mux(f4_sfb_valid, _T_91, UInt<4>(0h0)) node lo = cat(f4.io.deq.bits.shadowed_mask[1], f4.io.deq.bits.shadowed_mask[0]) node hi = cat(f4.io.deq.bits.shadowed_mask[3], f4.io.deq.bits.shadowed_mask[2]) node _T_93 = cat(hi, lo) node _T_94 = or(_T_92, _T_93) node _T_95 = bits(_T_94, 0, 0) node _T_96 = bits(_T_94, 1, 1) node _T_97 = bits(_T_94, 2, 2) node _T_98 = bits(_T_94, 3, 3) connect fb.io.enq.bits.shadowed_mask[0], _T_95 connect fb.io.enq.bits.shadowed_mask[1], _T_96 connect fb.io.enq.bits.shadowed_mask[2], _T_97 connect fb.io.enq.bits.shadowed_mask[3], _T_98 node _ftq_io_enq_valid_T = and(f4.io.deq.valid, fb.io.enq.ready) node _ftq_io_enq_valid_T_1 = eq(f4_delay, UInt<1>(0h0)) node _ftq_io_enq_valid_T_2 = and(_ftq_io_enq_valid_T, _ftq_io_enq_valid_T_1) connect ftq.io.enq.valid, _ftq_io_enq_valid_T_2 connect ftq.io.enq.bits.tsrc, f4.io.deq.bits.tsrc connect ftq.io.enq.bits.fsrc, f4.io.deq.bits.fsrc connect ftq.io.enq.bits.bpd_meta[0], f4.io.deq.bits.bpd_meta[0] connect ftq.io.enq.bits.end_half.bits, f4.io.deq.bits.end_half.bits connect ftq.io.enq.bits.end_half.valid, f4.io.deq.bits.end_half.valid connect ftq.io.enq.bits.bp_xcpt_if_oh[0], f4.io.deq.bits.bp_xcpt_if_oh[0] connect ftq.io.enq.bits.bp_xcpt_if_oh[1], f4.io.deq.bits.bp_xcpt_if_oh[1] connect ftq.io.enq.bits.bp_xcpt_if_oh[2], f4.io.deq.bits.bp_xcpt_if_oh[2] connect ftq.io.enq.bits.bp_xcpt_if_oh[3], f4.io.deq.bits.bp_xcpt_if_oh[3] connect ftq.io.enq.bits.bp_debug_if_oh[0], f4.io.deq.bits.bp_debug_if_oh[0] connect ftq.io.enq.bits.bp_debug_if_oh[1], f4.io.deq.bits.bp_debug_if_oh[1] connect ftq.io.enq.bits.bp_debug_if_oh[2], f4.io.deq.bits.bp_debug_if_oh[2] connect ftq.io.enq.bits.bp_debug_if_oh[3], f4.io.deq.bits.bp_debug_if_oh[3] connect ftq.io.enq.bits.xcpt_ae_if, f4.io.deq.bits.xcpt_ae_if connect ftq.io.enq.bits.xcpt_pf_if, f4.io.deq.bits.xcpt_pf_if connect ftq.io.enq.bits.lhist[0], f4.io.deq.bits.lhist[0] connect ftq.io.enq.bits.ghist.ras_idx, f4.io.deq.bits.ghist.ras_idx connect ftq.io.enq.bits.ghist.new_saw_branch_taken, f4.io.deq.bits.ghist.new_saw_branch_taken connect ftq.io.enq.bits.ghist.new_saw_branch_not_taken, f4.io.deq.bits.ghist.new_saw_branch_not_taken connect ftq.io.enq.bits.ghist.current_saw_branch_not_taken, f4.io.deq.bits.ghist.current_saw_branch_not_taken connect ftq.io.enq.bits.ghist.old_history, f4.io.deq.bits.ghist.old_history connect ftq.io.enq.bits.br_mask, f4.io.deq.bits.br_mask connect ftq.io.enq.bits.mask, f4.io.deq.bits.mask connect ftq.io.enq.bits.ftq_idx, f4.io.deq.bits.ftq_idx connect ftq.io.enq.bits.ras_top, f4.io.deq.bits.ras_top connect ftq.io.enq.bits.cfi_npc_plus4, f4.io.deq.bits.cfi_npc_plus4 connect ftq.io.enq.bits.cfi_is_ret, f4.io.deq.bits.cfi_is_ret connect ftq.io.enq.bits.cfi_is_call, f4.io.deq.bits.cfi_is_call connect ftq.io.enq.bits.cfi_type, f4.io.deq.bits.cfi_type connect ftq.io.enq.bits.cfi_idx.bits, f4.io.deq.bits.cfi_idx.bits connect ftq.io.enq.bits.cfi_idx.valid, f4.io.deq.bits.cfi_idx.valid connect ftq.io.enq.bits.shadowed_mask[0], f4.io.deq.bits.shadowed_mask[0] connect ftq.io.enq.bits.shadowed_mask[1], f4.io.deq.bits.shadowed_mask[1] connect ftq.io.enq.bits.shadowed_mask[2], f4.io.deq.bits.shadowed_mask[2] connect ftq.io.enq.bits.shadowed_mask[3], f4.io.deq.bits.shadowed_mask[3] connect ftq.io.enq.bits.shadowable_mask[0], f4.io.deq.bits.shadowable_mask[0] connect ftq.io.enq.bits.shadowable_mask[1], f4.io.deq.bits.shadowable_mask[1] connect ftq.io.enq.bits.shadowable_mask[2], f4.io.deq.bits.shadowable_mask[2] connect ftq.io.enq.bits.shadowable_mask[3], f4.io.deq.bits.shadowable_mask[3] connect ftq.io.enq.bits.sfb_dests[0], f4.io.deq.bits.sfb_dests[0] connect ftq.io.enq.bits.sfb_dests[1], f4.io.deq.bits.sfb_dests[1] connect ftq.io.enq.bits.sfb_dests[2], f4.io.deq.bits.sfb_dests[2] connect ftq.io.enq.bits.sfb_dests[3], f4.io.deq.bits.sfb_dests[3] connect ftq.io.enq.bits.sfb_masks[0], f4.io.deq.bits.sfb_masks[0] connect ftq.io.enq.bits.sfb_masks[1], f4.io.deq.bits.sfb_masks[1] connect ftq.io.enq.bits.sfb_masks[2], f4.io.deq.bits.sfb_masks[2] connect ftq.io.enq.bits.sfb_masks[3], f4.io.deq.bits.sfb_masks[3] connect ftq.io.enq.bits.sfbs[0], f4.io.deq.bits.sfbs[0] connect ftq.io.enq.bits.sfbs[1], f4.io.deq.bits.sfbs[1] connect ftq.io.enq.bits.sfbs[2], f4.io.deq.bits.sfbs[2] connect ftq.io.enq.bits.sfbs[3], f4.io.deq.bits.sfbs[3] connect ftq.io.enq.bits.exp_insts[0], f4.io.deq.bits.exp_insts[0] connect ftq.io.enq.bits.exp_insts[1], f4.io.deq.bits.exp_insts[1] connect ftq.io.enq.bits.exp_insts[2], f4.io.deq.bits.exp_insts[2] connect ftq.io.enq.bits.exp_insts[3], f4.io.deq.bits.exp_insts[3] connect ftq.io.enq.bits.insts[0], f4.io.deq.bits.insts[0] connect ftq.io.enq.bits.insts[1], f4.io.deq.bits.insts[1] connect ftq.io.enq.bits.insts[2], f4.io.deq.bits.insts[2] connect ftq.io.enq.bits.insts[3], f4.io.deq.bits.insts[3] connect ftq.io.enq.bits.edge_inst[0], f4.io.deq.bits.edge_inst[0] connect ftq.io.enq.bits.next_pc, f4.io.deq.bits.next_pc connect ftq.io.enq.bits.pc, f4.io.deq.bits.pc inst bpd_update_arbiter of Arbiter2_BranchPredictionUpdate_1 connect bpd_update_arbiter.clock, clock connect bpd_update_arbiter.reset, reset connect bpd_update_arbiter.io.in[0].valid, ftq.io.bpdupdate.valid connect bpd_update_arbiter.io.in[0].bits.meta[0], ftq.io.bpdupdate.bits.meta[0] connect bpd_update_arbiter.io.in[0].bits.target, ftq.io.bpdupdate.bits.target connect bpd_update_arbiter.io.in[0].bits.lhist[0], ftq.io.bpdupdate.bits.lhist[0] connect bpd_update_arbiter.io.in[0].bits.ghist.ras_idx, ftq.io.bpdupdate.bits.ghist.ras_idx connect bpd_update_arbiter.io.in[0].bits.ghist.new_saw_branch_taken, ftq.io.bpdupdate.bits.ghist.new_saw_branch_taken connect bpd_update_arbiter.io.in[0].bits.ghist.new_saw_branch_not_taken, ftq.io.bpdupdate.bits.ghist.new_saw_branch_not_taken connect bpd_update_arbiter.io.in[0].bits.ghist.current_saw_branch_not_taken, ftq.io.bpdupdate.bits.ghist.current_saw_branch_not_taken connect bpd_update_arbiter.io.in[0].bits.ghist.old_history, ftq.io.bpdupdate.bits.ghist.old_history connect bpd_update_arbiter.io.in[0].bits.cfi_is_jalr, ftq.io.bpdupdate.bits.cfi_is_jalr connect bpd_update_arbiter.io.in[0].bits.cfi_is_jal, ftq.io.bpdupdate.bits.cfi_is_jal connect bpd_update_arbiter.io.in[0].bits.cfi_is_br, ftq.io.bpdupdate.bits.cfi_is_br connect bpd_update_arbiter.io.in[0].bits.cfi_mispredicted, ftq.io.bpdupdate.bits.cfi_mispredicted connect bpd_update_arbiter.io.in[0].bits.cfi_taken, ftq.io.bpdupdate.bits.cfi_taken connect bpd_update_arbiter.io.in[0].bits.cfi_idx.bits, ftq.io.bpdupdate.bits.cfi_idx.bits connect bpd_update_arbiter.io.in[0].bits.cfi_idx.valid, ftq.io.bpdupdate.bits.cfi_idx.valid connect bpd_update_arbiter.io.in[0].bits.br_mask, ftq.io.bpdupdate.bits.br_mask connect bpd_update_arbiter.io.in[0].bits.pc, ftq.io.bpdupdate.bits.pc connect bpd_update_arbiter.io.in[0].bits.btb_mispredicts, ftq.io.bpdupdate.bits.btb_mispredicts connect bpd_update_arbiter.io.in[0].bits.is_repair_update, ftq.io.bpdupdate.bits.is_repair_update connect bpd_update_arbiter.io.in[0].bits.is_mispredict_update, ftq.io.bpdupdate.bits.is_mispredict_update node _T_99 = asUInt(reset) node _T_100 = eq(_T_99, UInt<1>(0h0)) when _T_100 : node _T_101 = eq(bpd_update_arbiter.io.in[0].ready, UInt<1>(0h0)) when _T_101 : printf(clock, UInt<1>(0h1), "Assertion failed\n at frontend.scala:928 assert(bpd_update_arbiter.io.in(0).ready)\n") : printf_1 assert(clock, bpd_update_arbiter.io.in[0].ready, UInt<1>(0h1), "") : assert_1 connect bpd_update_arbiter.io.in[1], f4_btb_corrections.io.deq connect bpd.io.update.bits.meta[0], bpd_update_arbiter.io.out.bits.meta[0] connect bpd.io.update.bits.target, bpd_update_arbiter.io.out.bits.target connect bpd.io.update.bits.lhist[0], bpd_update_arbiter.io.out.bits.lhist[0] connect bpd.io.update.bits.ghist.ras_idx, bpd_update_arbiter.io.out.bits.ghist.ras_idx connect bpd.io.update.bits.ghist.new_saw_branch_taken, bpd_update_arbiter.io.out.bits.ghist.new_saw_branch_taken connect bpd.io.update.bits.ghist.new_saw_branch_not_taken, bpd_update_arbiter.io.out.bits.ghist.new_saw_branch_not_taken connect bpd.io.update.bits.ghist.current_saw_branch_not_taken, bpd_update_arbiter.io.out.bits.ghist.current_saw_branch_not_taken connect bpd.io.update.bits.ghist.old_history, bpd_update_arbiter.io.out.bits.ghist.old_history connect bpd.io.update.bits.cfi_is_jalr, bpd_update_arbiter.io.out.bits.cfi_is_jalr connect bpd.io.update.bits.cfi_is_jal, bpd_update_arbiter.io.out.bits.cfi_is_jal connect bpd.io.update.bits.cfi_is_br, bpd_update_arbiter.io.out.bits.cfi_is_br connect bpd.io.update.bits.cfi_mispredicted, bpd_update_arbiter.io.out.bits.cfi_mispredicted connect bpd.io.update.bits.cfi_taken, bpd_update_arbiter.io.out.bits.cfi_taken connect bpd.io.update.bits.cfi_idx.bits, bpd_update_arbiter.io.out.bits.cfi_idx.bits connect bpd.io.update.bits.cfi_idx.valid, bpd_update_arbiter.io.out.bits.cfi_idx.valid connect bpd.io.update.bits.br_mask, bpd_update_arbiter.io.out.bits.br_mask connect bpd.io.update.bits.pc, bpd_update_arbiter.io.out.bits.pc connect bpd.io.update.bits.btb_mispredicts, bpd_update_arbiter.io.out.bits.btb_mispredicts connect bpd.io.update.bits.is_repair_update, bpd_update_arbiter.io.out.bits.is_repair_update connect bpd.io.update.bits.is_mispredict_update, bpd_update_arbiter.io.out.bits.is_mispredict_update connect bpd.io.update.valid, bpd_update_arbiter.io.out.valid connect bpd_update_arbiter.io.out.ready, UInt<1>(0h1) node _T_102 = and(ftq.io.ras_update, UInt<1>(0h1)) when _T_102 : connect ras.io.write_valid, UInt<1>(0h1) connect ras.io.write_idx, ftq.io.ras_update_idx connect ras.io.write_addr, ftq.io.ras_update_pc connect io.cpu.fetchpacket.bits, fb.io.deq.bits connect io.cpu.fetchpacket.valid, fb.io.deq.valid connect fb.io.deq.ready, io.cpu.fetchpacket.ready connect io.cpu.get_pc[0].next_pc, ftq.io.get_ftq_pc[0].next_pc connect io.cpu.get_pc[0].next_val, ftq.io.get_ftq_pc[0].next_val connect io.cpu.get_pc[0].com_pc, ftq.io.get_ftq_pc[0].com_pc connect io.cpu.get_pc[0].pc, ftq.io.get_ftq_pc[0].pc connect io.cpu.get_pc[0].ghist, ftq.io.get_ftq_pc[0].ghist connect io.cpu.get_pc[0].entry, ftq.io.get_ftq_pc[0].entry connect ftq.io.get_ftq_pc[0].ftq_idx, io.cpu.get_pc[0].ftq_idx connect io.cpu.get_pc[1].next_pc, ftq.io.get_ftq_pc[1].next_pc connect io.cpu.get_pc[1].next_val, ftq.io.get_ftq_pc[1].next_val connect io.cpu.get_pc[1].com_pc, ftq.io.get_ftq_pc[1].com_pc connect io.cpu.get_pc[1].pc, ftq.io.get_ftq_pc[1].pc connect io.cpu.get_pc[1].ghist, ftq.io.get_ftq_pc[1].ghist connect io.cpu.get_pc[1].entry, ftq.io.get_ftq_pc[1].entry connect ftq.io.get_ftq_pc[1].ftq_idx, io.cpu.get_pc[1].ftq_idx connect ftq.io.deq.bits, io.cpu.commit.bits connect ftq.io.deq.valid, io.cpu.commit.valid connect ftq.io.brupdate.b2.target_offset, io.cpu.brupdate.b2.target_offset connect ftq.io.brupdate.b2.jalr_target, io.cpu.brupdate.b2.jalr_target connect ftq.io.brupdate.b2.pc_sel, io.cpu.brupdate.b2.pc_sel connect ftq.io.brupdate.b2.cfi_type, io.cpu.brupdate.b2.cfi_type connect ftq.io.brupdate.b2.taken, io.cpu.brupdate.b2.taken connect ftq.io.brupdate.b2.mispredict, io.cpu.brupdate.b2.mispredict connect ftq.io.brupdate.b2.valid, io.cpu.brupdate.b2.valid connect ftq.io.brupdate.b2.uop.debug_tsrc, io.cpu.brupdate.b2.uop.debug_tsrc connect ftq.io.brupdate.b2.uop.debug_fsrc, io.cpu.brupdate.b2.uop.debug_fsrc connect ftq.io.brupdate.b2.uop.bp_xcpt_if, io.cpu.brupdate.b2.uop.bp_xcpt_if connect ftq.io.brupdate.b2.uop.bp_debug_if, io.cpu.brupdate.b2.uop.bp_debug_if connect ftq.io.brupdate.b2.uop.xcpt_ma_if, io.cpu.brupdate.b2.uop.xcpt_ma_if connect ftq.io.brupdate.b2.uop.xcpt_ae_if, io.cpu.brupdate.b2.uop.xcpt_ae_if connect ftq.io.brupdate.b2.uop.xcpt_pf_if, io.cpu.brupdate.b2.uop.xcpt_pf_if connect ftq.io.brupdate.b2.uop.fp_single, io.cpu.brupdate.b2.uop.fp_single connect ftq.io.brupdate.b2.uop.fp_val, io.cpu.brupdate.b2.uop.fp_val connect ftq.io.brupdate.b2.uop.frs3_en, io.cpu.brupdate.b2.uop.frs3_en connect ftq.io.brupdate.b2.uop.lrs2_rtype, io.cpu.brupdate.b2.uop.lrs2_rtype connect ftq.io.brupdate.b2.uop.lrs1_rtype, io.cpu.brupdate.b2.uop.lrs1_rtype connect ftq.io.brupdate.b2.uop.dst_rtype, io.cpu.brupdate.b2.uop.dst_rtype connect ftq.io.brupdate.b2.uop.ldst_val, io.cpu.brupdate.b2.uop.ldst_val connect ftq.io.brupdate.b2.uop.lrs3, io.cpu.brupdate.b2.uop.lrs3 connect ftq.io.brupdate.b2.uop.lrs2, io.cpu.brupdate.b2.uop.lrs2 connect ftq.io.brupdate.b2.uop.lrs1, io.cpu.brupdate.b2.uop.lrs1 connect ftq.io.brupdate.b2.uop.ldst, io.cpu.brupdate.b2.uop.ldst connect ftq.io.brupdate.b2.uop.ldst_is_rs1, io.cpu.brupdate.b2.uop.ldst_is_rs1 connect ftq.io.brupdate.b2.uop.flush_on_commit, io.cpu.brupdate.b2.uop.flush_on_commit connect ftq.io.brupdate.b2.uop.is_unique, io.cpu.brupdate.b2.uop.is_unique connect ftq.io.brupdate.b2.uop.is_sys_pc2epc, io.cpu.brupdate.b2.uop.is_sys_pc2epc connect ftq.io.brupdate.b2.uop.uses_stq, io.cpu.brupdate.b2.uop.uses_stq connect ftq.io.brupdate.b2.uop.uses_ldq, io.cpu.brupdate.b2.uop.uses_ldq connect ftq.io.brupdate.b2.uop.is_amo, io.cpu.brupdate.b2.uop.is_amo connect ftq.io.brupdate.b2.uop.is_fencei, io.cpu.brupdate.b2.uop.is_fencei connect ftq.io.brupdate.b2.uop.is_fence, io.cpu.brupdate.b2.uop.is_fence connect ftq.io.brupdate.b2.uop.mem_signed, io.cpu.brupdate.b2.uop.mem_signed connect ftq.io.brupdate.b2.uop.mem_size, io.cpu.brupdate.b2.uop.mem_size connect ftq.io.brupdate.b2.uop.mem_cmd, io.cpu.brupdate.b2.uop.mem_cmd connect ftq.io.brupdate.b2.uop.bypassable, io.cpu.brupdate.b2.uop.bypassable connect ftq.io.brupdate.b2.uop.exc_cause, io.cpu.brupdate.b2.uop.exc_cause connect ftq.io.brupdate.b2.uop.exception, io.cpu.brupdate.b2.uop.exception connect ftq.io.brupdate.b2.uop.stale_pdst, io.cpu.brupdate.b2.uop.stale_pdst connect ftq.io.brupdate.b2.uop.ppred_busy, io.cpu.brupdate.b2.uop.ppred_busy connect ftq.io.brupdate.b2.uop.prs3_busy, io.cpu.brupdate.b2.uop.prs3_busy connect ftq.io.brupdate.b2.uop.prs2_busy, io.cpu.brupdate.b2.uop.prs2_busy connect ftq.io.brupdate.b2.uop.prs1_busy, io.cpu.brupdate.b2.uop.prs1_busy connect ftq.io.brupdate.b2.uop.ppred, io.cpu.brupdate.b2.uop.ppred connect ftq.io.brupdate.b2.uop.prs3, io.cpu.brupdate.b2.uop.prs3 connect ftq.io.brupdate.b2.uop.prs2, io.cpu.brupdate.b2.uop.prs2 connect ftq.io.brupdate.b2.uop.prs1, io.cpu.brupdate.b2.uop.prs1 connect ftq.io.brupdate.b2.uop.pdst, io.cpu.brupdate.b2.uop.pdst connect ftq.io.brupdate.b2.uop.rxq_idx, io.cpu.brupdate.b2.uop.rxq_idx connect ftq.io.brupdate.b2.uop.stq_idx, io.cpu.brupdate.b2.uop.stq_idx connect ftq.io.brupdate.b2.uop.ldq_idx, io.cpu.brupdate.b2.uop.ldq_idx connect ftq.io.brupdate.b2.uop.rob_idx, io.cpu.brupdate.b2.uop.rob_idx connect ftq.io.brupdate.b2.uop.csr_addr, io.cpu.brupdate.b2.uop.csr_addr connect ftq.io.brupdate.b2.uop.imm_packed, io.cpu.brupdate.b2.uop.imm_packed connect ftq.io.brupdate.b2.uop.taken, io.cpu.brupdate.b2.uop.taken connect ftq.io.brupdate.b2.uop.pc_lob, io.cpu.brupdate.b2.uop.pc_lob connect ftq.io.brupdate.b2.uop.edge_inst, io.cpu.brupdate.b2.uop.edge_inst connect ftq.io.brupdate.b2.uop.ftq_idx, io.cpu.brupdate.b2.uop.ftq_idx connect ftq.io.brupdate.b2.uop.br_tag, io.cpu.brupdate.b2.uop.br_tag connect ftq.io.brupdate.b2.uop.br_mask, io.cpu.brupdate.b2.uop.br_mask connect ftq.io.brupdate.b2.uop.is_sfb, io.cpu.brupdate.b2.uop.is_sfb connect ftq.io.brupdate.b2.uop.is_jal, io.cpu.brupdate.b2.uop.is_jal connect ftq.io.brupdate.b2.uop.is_jalr, io.cpu.brupdate.b2.uop.is_jalr connect ftq.io.brupdate.b2.uop.is_br, io.cpu.brupdate.b2.uop.is_br connect ftq.io.brupdate.b2.uop.iw_p2_poisoned, io.cpu.brupdate.b2.uop.iw_p2_poisoned connect ftq.io.brupdate.b2.uop.iw_p1_poisoned, io.cpu.brupdate.b2.uop.iw_p1_poisoned connect ftq.io.brupdate.b2.uop.iw_state, io.cpu.brupdate.b2.uop.iw_state connect ftq.io.brupdate.b2.uop.ctrl.is_std, io.cpu.brupdate.b2.uop.ctrl.is_std connect ftq.io.brupdate.b2.uop.ctrl.is_sta, io.cpu.brupdate.b2.uop.ctrl.is_sta connect ftq.io.brupdate.b2.uop.ctrl.is_load, io.cpu.brupdate.b2.uop.ctrl.is_load connect ftq.io.brupdate.b2.uop.ctrl.csr_cmd, io.cpu.brupdate.b2.uop.ctrl.csr_cmd connect ftq.io.brupdate.b2.uop.ctrl.fcn_dw, io.cpu.brupdate.b2.uop.ctrl.fcn_dw connect ftq.io.brupdate.b2.uop.ctrl.op_fcn, io.cpu.brupdate.b2.uop.ctrl.op_fcn connect ftq.io.brupdate.b2.uop.ctrl.imm_sel, io.cpu.brupdate.b2.uop.ctrl.imm_sel connect ftq.io.brupdate.b2.uop.ctrl.op2_sel, io.cpu.brupdate.b2.uop.ctrl.op2_sel connect ftq.io.brupdate.b2.uop.ctrl.op1_sel, io.cpu.brupdate.b2.uop.ctrl.op1_sel connect ftq.io.brupdate.b2.uop.ctrl.br_type, io.cpu.brupdate.b2.uop.ctrl.br_type connect ftq.io.brupdate.b2.uop.fu_code, io.cpu.brupdate.b2.uop.fu_code connect ftq.io.brupdate.b2.uop.iq_type, io.cpu.brupdate.b2.uop.iq_type connect ftq.io.brupdate.b2.uop.debug_pc, io.cpu.brupdate.b2.uop.debug_pc connect ftq.io.brupdate.b2.uop.is_rvc, io.cpu.brupdate.b2.uop.is_rvc connect ftq.io.brupdate.b2.uop.debug_inst, io.cpu.brupdate.b2.uop.debug_inst connect ftq.io.brupdate.b2.uop.inst, io.cpu.brupdate.b2.uop.inst connect ftq.io.brupdate.b2.uop.uopc, io.cpu.brupdate.b2.uop.uopc connect ftq.io.brupdate.b1.mispredict_mask, io.cpu.brupdate.b1.mispredict_mask connect ftq.io.brupdate.b1.resolve_mask, io.cpu.brupdate.b1.resolve_mask connect ftq.io.redirect.valid, io.cpu.redirect_val connect ftq.io.redirect.bits, io.cpu.redirect_ftq_idx connect fb.io.clear, UInt<1>(0h0) when io.cpu.sfence.valid : connect fb.io.clear, UInt<1>(0h1) connect f4_clear, UInt<1>(0h1) connect f3_clear, UInt<1>(0h1) connect f2_clear, UInt<1>(0h1) connect f1_clear, UInt<1>(0h1) connect s0_valid, UInt<1>(0h0) connect s0_vpc, io.cpu.sfence.bits.addr connect s0_is_replay, UInt<1>(0h0) connect s0_is_sfence, UInt<1>(0h1) else : when io.cpu.redirect_flush : connect fb.io.clear, UInt<1>(0h1) connect f4_clear, UInt<1>(0h1) connect f3_clear, UInt<1>(0h1) connect f2_clear, UInt<1>(0h1) connect f1_clear, UInt<1>(0h1) connect f3_prev_is_half, UInt<1>(0h0) connect s0_valid, io.cpu.redirect_val connect s0_vpc, io.cpu.redirect_pc connect s0_ghist, io.cpu.redirect_ghist connect s0_tsrc, UInt<2>(0h3) connect s0_is_replay, UInt<1>(0h0) connect ftq.io.redirect.valid, io.cpu.redirect_val connect ftq.io.redirect.bits, io.cpu.redirect_ftq_idx connect ftq.io.debug_ftq_idx[0], io.cpu.debug_ftq_idx[0] connect io.cpu.debug_fetch_pc, ftq.io.debug_fetch_pc	module BoomFrontend_1( // @[frontend.scala:322:7] input clock, // @[frontend.scala:322:7] input reset, // @[frontend.scala:322:7] input auto_icache_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_icache_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [31:0] auto_icache_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icache_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_icache_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icache_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icache_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_icache_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_cpu_fetchpacket_ready, // @[frontend.scala:326:14] output io_cpu_fetchpacket_valid, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_valid, // @[frontend.scala:326:14] output [31:0] io_cpu_fetchpacket_bits_uops_0_bits_inst, // @[frontend.scala:326:14] output [31:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_inst, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_is_rvc, // @[frontend.scala:326:14] output [39:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_pc, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_is_sfb, // @[frontend.scala:326:14] output [3:0] io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_edge_inst, // @[frontend.scala:326:14] output [5:0] io_cpu_fetchpacket_bits_uops_0_bits_pc_lob, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_taken, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if, // @[frontend.scala:326:14] output io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if, // @[frontend.scala:326:14] output [1:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc, // @[frontend.scala:326:14] input [3:0] io_cpu_get_pc_0_ftq_idx, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_idx_valid, // @[frontend.scala:326:14] output [1:0] io_cpu_get_pc_0_entry_cfi_idx_bits, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_taken, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_mispredicted, // @[frontend.scala:326:14] output [2:0] io_cpu_get_pc_0_entry_cfi_type, // @[frontend.scala:326:14] output [3:0] io_cpu_get_pc_0_entry_br_mask, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_is_call, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_is_ret, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_cfi_npc_plus4, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_0_entry_ras_top, // @[frontend.scala:326:14] output [4:0] io_cpu_get_pc_0_entry_ras_idx, // @[frontend.scala:326:14] output io_cpu_get_pc_0_entry_start_bank, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_0_pc, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_0_com_pc, // @[frontend.scala:326:14] output io_cpu_get_pc_0_next_val, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_0_next_pc, // @[frontend.scala:326:14] input [3:0] io_cpu_get_pc_1_ftq_idx, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_idx_valid, // @[frontend.scala:326:14] output [1:0] io_cpu_get_pc_1_entry_cfi_idx_bits, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_taken, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_mispredicted, // @[frontend.scala:326:14] output [2:0] io_cpu_get_pc_1_entry_cfi_type, // @[frontend.scala:326:14] output [3:0] io_cpu_get_pc_1_entry_br_mask, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_is_call, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_is_ret, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_cfi_npc_plus4, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_1_entry_ras_top, // @[frontend.scala:326:14] output [4:0] io_cpu_get_pc_1_entry_ras_idx, // @[frontend.scala:326:14] output io_cpu_get_pc_1_entry_start_bank, // @[frontend.scala:326:14] output [63:0] io_cpu_get_pc_1_ghist_old_history, // @[frontend.scala:326:14] output io_cpu_get_pc_1_ghist_current_saw_branch_not_taken, // @[frontend.scala:326:14] output io_cpu_get_pc_1_ghist_new_saw_branch_not_taken, // @[frontend.scala:326:14] output io_cpu_get_pc_1_ghist_new_saw_branch_taken, // @[frontend.scala:326:14] output [4:0] io_cpu_get_pc_1_ghist_ras_idx, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_1_pc, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_1_com_pc, // @[frontend.scala:326:14] output io_cpu_get_pc_1_next_val, // @[frontend.scala:326:14] output [39:0] io_cpu_get_pc_1_next_pc, // @[frontend.scala:326:14] output [39:0] io_cpu_debug_fetch_pc_0, // @[frontend.scala:326:14] input io_cpu_status_debug, // @[frontend.scala:326:14] input io_cpu_status_cease, // @[frontend.scala:326:14] input io_cpu_status_wfi, // @[frontend.scala:326:14] input [1:0] io_cpu_status_dprv, // @[frontend.scala:326:14] input io_cpu_status_dv, // @[frontend.scala:326:14] input [1:0] io_cpu_status_prv, // @[frontend.scala:326:14] input io_cpu_status_v, // @[frontend.scala:326:14] input io_cpu_status_sd, // @[frontend.scala:326:14] input io_cpu_status_mpv, // @[frontend.scala:326:14] input io_cpu_status_gva, // @[frontend.scala:326:14] input io_cpu_status_tsr, // @[frontend.scala:326:14] input io_cpu_status_tw, // @[frontend.scala:326:14] input io_cpu_status_tvm, // @[frontend.scala:326:14] input io_cpu_status_mxr, // @[frontend.scala:326:14] input io_cpu_status_sum, // @[frontend.scala:326:14] input io_cpu_status_mprv, // @[frontend.scala:326:14] input [1:0] io_cpu_status_fs, // @[frontend.scala:326:14] input [1:0] io_cpu_status_mpp, // @[frontend.scala:326:14] input io_cpu_status_spp, // @[frontend.scala:326:14] input io_cpu_status_mpie, // @[frontend.scala:326:14] input io_cpu_status_spie, // @[frontend.scala:326:14] input io_cpu_status_mie, // @[frontend.scala:326:14] input io_cpu_status_sie, // @[frontend.scala:326:14] input io_cpu_sfence_valid, // @[frontend.scala:326:14] input io_cpu_sfence_bits_rs1, // @[frontend.scala:326:14] input io_cpu_sfence_bits_rs2, // @[frontend.scala:326:14] input [38:0] io_cpu_sfence_bits_addr, // @[frontend.scala:326:14] input io_cpu_sfence_bits_asid, // @[frontend.scala:326:14] input [7:0] io_cpu_brupdate_b1_resolve_mask, // @[frontend.scala:326:14] input [7:0] io_cpu_brupdate_b1_mispredict_mask, // @[frontend.scala:326:14] input [6:0] io_cpu_brupdate_b2_uop_uopc, // @[frontend.scala:326:14] input [31:0] io_cpu_brupdate_b2_uop_inst, // @[frontend.scala:326:14] input [31:0] io_cpu_brupdate_b2_uop_debug_inst, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_rvc, // @[frontend.scala:326:14] input [39:0] io_cpu_brupdate_b2_uop_debug_pc, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_uop_iq_type, // @[frontend.scala:326:14] input [9:0] io_cpu_brupdate_b2_uop_fu_code, // @[frontend.scala:326:14] input [3:0] io_cpu_brupdate_b2_uop_ctrl_br_type, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_ctrl_op1_sel, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_uop_ctrl_op2_sel, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_uop_ctrl_imm_sel, // @[frontend.scala:326:14] input [4:0] io_cpu_brupdate_b2_uop_ctrl_op_fcn, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ctrl_fcn_dw, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_uop_ctrl_csr_cmd, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ctrl_is_load, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ctrl_is_sta, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ctrl_is_std, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_iw_state, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_iw_p1_poisoned, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_iw_p2_poisoned, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_br, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_jalr, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_jal, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_sfb, // @[frontend.scala:326:14] input [7:0] io_cpu_brupdate_b2_uop_br_mask, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_uop_br_tag, // @[frontend.scala:326:14] input [3:0] io_cpu_brupdate_b2_uop_ftq_idx, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_edge_inst, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_pc_lob, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_taken, // @[frontend.scala:326:14] input [19:0] io_cpu_brupdate_b2_uop_imm_packed, // @[frontend.scala:326:14] input [11:0] io_cpu_brupdate_b2_uop_csr_addr, // @[frontend.scala:326:14] input [4:0] io_cpu_brupdate_b2_uop_rob_idx, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_uop_ldq_idx, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_uop_stq_idx, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_rxq_idx, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_pdst, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_prs1, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_prs2, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_prs3, // @[frontend.scala:326:14] input [3:0] io_cpu_brupdate_b2_uop_ppred, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_prs1_busy, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_prs2_busy, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_prs3_busy, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ppred_busy, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_stale_pdst, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_exception, // @[frontend.scala:326:14] input [63:0] io_cpu_brupdate_b2_uop_exc_cause, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_bypassable, // @[frontend.scala:326:14] input [4:0] io_cpu_brupdate_b2_uop_mem_cmd, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_mem_size, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_mem_signed, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_fence, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_fencei, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_amo, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_uses_ldq, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_uses_stq, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_sys_pc2epc, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_is_unique, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_flush_on_commit, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ldst_is_rs1, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_ldst, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_lrs1, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_lrs2, // @[frontend.scala:326:14] input [5:0] io_cpu_brupdate_b2_uop_lrs3, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_ldst_val, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_dst_rtype, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_lrs1_rtype, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_lrs2_rtype, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_frs3_en, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_fp_val, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_fp_single, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_xcpt_pf_if, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_xcpt_ae_if, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_xcpt_ma_if, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_bp_debug_if, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_uop_bp_xcpt_if, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_debug_fsrc, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_uop_debug_tsrc, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_valid, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_mispredict, // @[frontend.scala:326:14] input io_cpu_brupdate_b2_taken, // @[frontend.scala:326:14] input [2:0] io_cpu_brupdate_b2_cfi_type, // @[frontend.scala:326:14] input [1:0] io_cpu_brupdate_b2_pc_sel, // @[frontend.scala:326:14] input [39:0] io_cpu_brupdate_b2_jalr_target, // @[frontend.scala:326:14] input [20:0] io_cpu_brupdate_b2_target_offset, // @[frontend.scala:326:14] input io_cpu_redirect_flush, // @[frontend.scala:326:14] input io_cpu_redirect_val, // @[frontend.scala:326:14] input [39:0] io_cpu_redirect_pc, // @[frontend.scala:326:14] input [3:0] io_cpu_redirect_ftq_idx, // @[frontend.scala:326:14] input [63:0] io_cpu_redirect_ghist_old_history, // @[frontend.scala:326:14] input io_cpu_redirect_ghist_current_saw_branch_not_taken, // @[frontend.scala:326:14] input io_cpu_redirect_ghist_new_saw_branch_not_taken, // @[frontend.scala:326:14] input io_cpu_redirect_ghist_new_saw_branch_taken, // @[frontend.scala:326:14] input [4:0] io_cpu_redirect_ghist_ras_idx, // @[frontend.scala:326:14] input io_cpu_commit_valid, // @[frontend.scala:326:14] input [15:0] io_cpu_commit_bits, // @[frontend.scala:326:14] input io_cpu_flush_icache, // @[frontend.scala:326:14] output io_cpu_perf_acquire, // @[frontend.scala:326:14] output io_cpu_perf_tlbMiss, // @[frontend.scala:326:14] input io_ptw_req_ready, // @[frontend.scala:326:14] output io_ptw_req_valid, // @[frontend.scala:326:14] output [26:0] io_ptw_req_bits_bits_addr, // @[frontend.scala:326:14] output io_ptw_req_bits_bits_need_gpa, // @[frontend.scala:326:14] input io_ptw_resp_valid, // @[frontend.scala:326:14] input io_ptw_resp_bits_ae_ptw, // @[frontend.scala:326:14] input io_ptw_resp_bits_ae_final, // @[frontend.scala:326:14] input io_ptw_resp_bits_pf, // @[frontend.scala:326:14] input io_ptw_resp_bits_gf, // @[frontend.scala:326:14] input io_ptw_resp_bits_hr, // @[frontend.scala:326:14] input io_ptw_resp_bits_hw, // @[frontend.scala:326:14] input io_ptw_resp_bits_hx, // @[frontend.scala:326:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[frontend.scala:326:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[frontend.scala:326:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_d, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_a, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_g, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_u, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_x, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_w, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_r, // @[frontend.scala:326:14] input io_ptw_resp_bits_pte_v, // @[frontend.scala:326:14] input [1:0] io_ptw_resp_bits_level, // @[frontend.scala:326:14] input io_ptw_resp_bits_homogeneous, // @[frontend.scala:326:14] input io_ptw_resp_bits_gpa_valid, // @[frontend.scala:326:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[frontend.scala:326:14] input io_ptw_resp_bits_gpa_is_pte, // @[frontend.scala:326:14] input [3:0] io_ptw_ptbr_mode, // @[frontend.scala:326:14] input [43:0] io_ptw_ptbr_ppn, // @[frontend.scala:326:14] input io_ptw_status_debug, // @[frontend.scala:326:14] input io_ptw_status_cease, // @[frontend.scala:326:14] input io_ptw_status_wfi, // @[frontend.scala:326:14] input [1:0] io_ptw_status_dprv, // @[frontend.scala:326:14] input io_ptw_status_dv, // @[frontend.scala:326:14] input [1:0] io_ptw_status_prv, // @[frontend.scala:326:14] input io_ptw_status_v, // @[frontend.scala:326:14] input io_ptw_status_sd, // @[frontend.scala:326:14] input io_ptw_status_mpv, // @[frontend.scala:326:14] input io_ptw_status_gva, // @[frontend.scala:326:14] input io_ptw_status_tsr, // @[frontend.scala:326:14] input io_ptw_status_tw, // @[frontend.scala:326:14] input io_ptw_status_tvm, // @[frontend.scala:326:14] input io_ptw_status_mxr, // @[frontend.scala:326:14] input io_ptw_status_sum, // @[frontend.scala:326:14] input io_ptw_status_mprv, // @[frontend.scala:326:14] input [1:0] io_ptw_status_fs, // @[frontend.scala:326:14] input [1:0] io_ptw_status_mpp, // @[frontend.scala:326:14] input io_ptw_status_spp, // @[frontend.scala:326:14] input io_ptw_status_mpie, // @[frontend.scala:326:14] input io_ptw_status_spie, // @[frontend.scala:326:14] input io_ptw_status_mie, // @[frontend.scala:326:14] input io_ptw_status_sie, // @[frontend.scala:326:14] input io_ptw_pmp_0_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_0_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_0_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_0_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_0_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_0_mask, // @[frontend.scala:326:14] input io_ptw_pmp_1_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_1_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_1_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_1_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_1_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_1_mask, // @[frontend.scala:326:14] input io_ptw_pmp_2_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_2_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_2_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_2_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_2_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_2_mask, // @[frontend.scala:326:14] input io_ptw_pmp_3_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_3_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_3_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_3_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_3_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_3_mask, // @[frontend.scala:326:14] input io_ptw_pmp_4_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_4_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_4_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_4_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_4_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_4_mask, // @[frontend.scala:326:14] input io_ptw_pmp_5_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_5_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_5_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_5_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_5_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_5_mask, // @[frontend.scala:326:14] input io_ptw_pmp_6_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_6_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_6_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_6_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_6_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_6_mask, // @[frontend.scala:326:14] input io_ptw_pmp_7_cfg_l, // @[frontend.scala:326:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[frontend.scala:326:14] input io_ptw_pmp_7_cfg_x, // @[frontend.scala:326:14] input io_ptw_pmp_7_cfg_w, // @[frontend.scala:326:14] input io_ptw_pmp_7_cfg_r, // @[frontend.scala:326:14] input [29:0] io_ptw_pmp_7_addr, // @[frontend.scala:326:14] input [31:0] io_ptw_pmp_7_mask // @[frontend.scala:326:14] ); wire [4:0] f3_io_enq_bits_ghist_ras_idx; // @[frontend.scala:533:24, :814:38, :821:79, :822:28] wire f3_fetch_bundle_cfi_is_ret; // @[frontend.scala:569:29] wire [1:0] f3_fetch_bundle_cfi_idx_bits; // @[frontend.scala:569:29] wire _bpd_update_arbiter_io_in_1_ready; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_valid; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_is_mispredict_update; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_is_repair_update; // @[frontend.scala:925:34] wire [3:0] _bpd_update_arbiter_io_out_bits_btb_mispredicts; // @[frontend.scala:925:34] wire [39:0] _bpd_update_arbiter_io_out_bits_pc; // @[frontend.scala:925:34] wire [3:0] _bpd_update_arbiter_io_out_bits_br_mask; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_idx_valid; // @[frontend.scala:925:34] wire [1:0] _bpd_update_arbiter_io_out_bits_cfi_idx_bits; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_taken; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_mispredicted; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_is_br; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_is_jal; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_cfi_is_jalr; // @[frontend.scala:925:34] wire [63:0] _bpd_update_arbiter_io_out_bits_ghist_old_history; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_ghist_current_saw_branch_not_taken; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_ghist_new_saw_branch_not_taken; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_ghist_new_saw_branch_taken; // @[frontend.scala:925:34] wire [4:0] _bpd_update_arbiter_io_out_bits_ghist_ras_idx; // @[frontend.scala:925:34] wire _bpd_update_arbiter_io_out_bits_lhist_0; // @[frontend.scala:925:34] wire [39:0] _bpd_update_arbiter_io_out_bits_target; // @[frontend.scala:925:34] wire [119:0] _bpd_update_arbiter_io_out_bits_meta_0; // @[frontend.scala:925:34] wire _ftq_io_enq_ready; // @[frontend.scala:862:19] wire [3:0] _ftq_io_enq_idx; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_valid; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_is_mispredict_update; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_is_repair_update; // @[frontend.scala:862:19] wire [39:0] _ftq_io_bpdupdate_bits_pc; // @[frontend.scala:862:19] wire [3:0] _ftq_io_bpdupdate_bits_br_mask; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_cfi_idx_valid; // @[frontend.scala:862:19] wire [1:0] _ftq_io_bpdupdate_bits_cfi_idx_bits; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_cfi_taken; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_cfi_mispredicted; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_cfi_is_br; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_cfi_is_jal; // @[frontend.scala:862:19] wire [63:0] _ftq_io_bpdupdate_bits_ghist_old_history; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_ghist_current_saw_branch_not_taken; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_ghist_new_saw_branch_not_taken; // @[frontend.scala:862:19] wire _ftq_io_bpdupdate_bits_ghist_new_saw_branch_taken; // @[frontend.scala:862:19] wire [4:0] _ftq_io_bpdupdate_bits_ghist_ras_idx; // @[frontend.scala:862:19] wire [39:0] _ftq_io_bpdupdate_bits_target; // @[frontend.scala:862:19] wire [119:0] _ftq_io_bpdupdate_bits_meta_0; // @[frontend.scala:862:19] wire _ftq_io_ras_update; // @[frontend.scala:862:19] wire [4:0] _ftq_io_ras_update_idx; // @[frontend.scala:862:19] wire [39:0] _ftq_io_ras_update_pc; // @[frontend.scala:862:19] wire _fb_io_enq_ready; // @[frontend.scala:861:19] wire _f4_io_deq_valid; // @[frontend.scala:859:11] wire [39:0] _f4_io_deq_bits_pc; // @[frontend.scala:859:11] wire [39:0] _f4_io_deq_bits_next_pc; // @[frontend.scala:859:11] wire _f4_io_deq_bits_edge_inst_0; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_0; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_1; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_2; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_insts_3; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_0; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_1; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_2; // @[frontend.scala:859:11] wire [31:0] _f4_io_deq_bits_exp_insts_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_2; // @[frontend.scala:859:11] wire _f4_io_deq_bits_sfbs_3; // @[frontend.scala:859:11] wire [7:0] _f4_io_deq_bits_sfb_masks_0; // @[frontend.scala:859:11] wire [7:0] _f4_io_deq_bits_sfb_masks_1; // @[frontend.scala:859:11] wire [7:0] _f4_io_deq_bits_sfb_masks_2; // @[frontend.scala:859:11] wire [7:0] _f4_io_deq_bits_sfb_masks_3; // @[frontend.scala:859:11] wire [3:0] _f4_io_deq_bits_sfb_dests_0; // @[frontend.scala:859:11] wire [3:0] _f4_io_deq_bits_sfb_dests_1; // @[frontend.scala:859:11] wire [3:0] _f4_io_deq_bits_sfb_dests_2; // @[frontend.scala:859:11] wire [3:0] _f4_io_deq_bits_sfb_dests_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_2; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowable_mask_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_2; // @[frontend.scala:859:11] wire _f4_io_deq_bits_shadowed_mask_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_cfi_idx_valid; // @[frontend.scala:859:11] wire [1:0] _f4_io_deq_bits_cfi_idx_bits; // @[frontend.scala:859:11] wire [2:0] _f4_io_deq_bits_cfi_type; // @[frontend.scala:859:11] wire _f4_io_deq_bits_cfi_is_call; // @[frontend.scala:859:11] wire _f4_io_deq_bits_cfi_is_ret; // @[frontend.scala:859:11] wire _f4_io_deq_bits_cfi_npc_plus4; // @[frontend.scala:859:11] wire [39:0] _f4_io_deq_bits_ras_top; // @[frontend.scala:859:11] wire [3:0] _f4_io_deq_bits_ftq_idx; // @[frontend.scala:859:11] wire [3:0] _f4_io_deq_bits_mask; // @[frontend.scala:859:11] wire [3:0] _f4_io_deq_bits_br_mask; // @[frontend.scala:859:11] wire [63:0] _f4_io_deq_bits_ghist_old_history; // @[frontend.scala:859:11] wire _f4_io_deq_bits_ghist_current_saw_branch_not_taken; // @[frontend.scala:859:11] wire _f4_io_deq_bits_ghist_new_saw_branch_not_taken; // @[frontend.scala:859:11] wire _f4_io_deq_bits_ghist_new_saw_branch_taken; // @[frontend.scala:859:11] wire [4:0] _f4_io_deq_bits_ghist_ras_idx; // @[frontend.scala:859:11] wire _f4_io_deq_bits_lhist_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_xcpt_pf_if; // @[frontend.scala:859:11] wire _f4_io_deq_bits_xcpt_ae_if; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_2; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_debug_if_oh_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_0; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_1; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_2; // @[frontend.scala:859:11] wire _f4_io_deq_bits_bp_xcpt_if_oh_3; // @[frontend.scala:859:11] wire _f4_io_deq_bits_end_half_valid; // @[frontend.scala:859:11] wire [15:0] _f4_io_deq_bits_end_half_bits; // @[frontend.scala:859:11] wire [119:0] _f4_io_deq_bits_bpd_meta_0; // @[frontend.scala:859:11] wire [1:0] _f4_io_deq_bits_fsrc; // @[frontend.scala:859:11] wire [1:0] _f4_io_deq_bits_tsrc; // @[frontend.scala:859:11] wire _f4_btb_corrections_io_deq_valid; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_is_mispredict_update; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_is_repair_update; // @[frontend.scala:842:34] wire [3:0] _f4_btb_corrections_io_deq_bits_btb_mispredicts; // @[frontend.scala:842:34] wire [39:0] _f4_btb_corrections_io_deq_bits_pc; // @[frontend.scala:842:34] wire [3:0] _f4_btb_corrections_io_deq_bits_br_mask; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_idx_valid; // @[frontend.scala:842:34] wire [1:0] _f4_btb_corrections_io_deq_bits_cfi_idx_bits; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_taken; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_mispredicted; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_is_br; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_is_jal; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_cfi_is_jalr; // @[frontend.scala:842:34] wire [63:0] _f4_btb_corrections_io_deq_bits_ghist_old_history; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_ghist_current_saw_branch_not_taken; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_ghist_new_saw_branch_not_taken; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_ghist_new_saw_branch_taken; // @[frontend.scala:842:34] wire [4:0] _f4_btb_corrections_io_deq_bits_ghist_ras_idx; // @[frontend.scala:842:34] wire _f4_btb_corrections_io_deq_bits_lhist_0; // @[frontend.scala:842:34] wire [39:0] _f4_btb_corrections_io_deq_bits_target; // @[frontend.scala:842:34] wire [119:0] _f4_btb_corrections_io_deq_bits_meta_0; // @[frontend.scala:842:34] wire [31:0] _exp_inst_rvc_exp_2_io_out_bits; // @[consts.scala:330:25] wire _exp_inst_rvc_exp_2_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst_rvc_exp_1_io_out_bits; // @[consts.scala:330:25] wire _exp_inst_rvc_exp_1_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst_rvc_exp_io_out_bits; // @[consts.scala:330:25] wire _exp_inst_rvc_exp_io_rvc; // @[consts.scala:330:25] wire _bpd_decoder1_io_out_is_ret; // @[frontend.scala:625:34] wire _bpd_decoder1_io_out_is_call; // @[frontend.scala:625:34] wire [39:0] _bpd_decoder1_io_out_target; // @[frontend.scala:625:34] wire [2:0] _bpd_decoder1_io_out_cfi_type; // @[frontend.scala:625:34] wire _bpd_decoder1_io_out_sfb_offset_valid; // @[frontend.scala:625:34] wire [5:0] _bpd_decoder1_io_out_sfb_offset_bits; // @[frontend.scala:625:34] wire _bpd_decoder1_io_out_shadowable; // @[frontend.scala:625:34] wire _bpd_decoder0_io_out_is_ret; // @[frontend.scala:622:34] wire _bpd_decoder0_io_out_is_call; // @[frontend.scala:622:34] wire [39:0] _bpd_decoder0_io_out_target; // @[frontend.scala:622:34] wire [2:0] _bpd_decoder0_io_out_cfi_type; // @[frontend.scala:622:34] wire _bpd_decoder0_io_out_sfb_offset_valid; // @[frontend.scala:622:34] wire [5:0] _bpd_decoder0_io_out_sfb_offset_bits; // @[frontend.scala:622:34] wire _bpd_decoder0_io_out_shadowable; // @[frontend.scala:622:34] wire [31:0] _exp_inst1_rvc_exp_io_out_bits; // @[consts.scala:330:25] wire _exp_inst1_rvc_exp_io_rvc; // @[consts.scala:330:25] wire [31:0] _exp_inst0_rvc_exp_io_out_bits; // @[consts.scala:330:25] wire _exp_inst0_rvc_exp_io_rvc; // @[consts.scala:330:25] wire _f3_bpd_resp_io_enq_ready; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_pc; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_0_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_0_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_0_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_1_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_1_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_1_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_2_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_2_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_2_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_3_taken; // @[frontend.scala:521:11] wire _f3_bpd_resp_io_deq_bits_preds_3_predicted_pc_valid; // @[frontend.scala:521:11] wire [39:0] _f3_bpd_resp_io_deq_bits_preds_3_predicted_pc_bits; // @[frontend.scala:521:11] wire _f3_io_enq_ready; // @[frontend.scala:516:11] wire _f3_io_deq_valid; // @[frontend.scala:516:11] wire [39:0] _f3_io_deq_bits_pc; // @[frontend.scala:516:11] wire [3:0] _f3_io_deq_bits_mask; // @[frontend.scala:516:11] wire [1:0] _f3_io_deq_bits_fsrc; // @[frontend.scala:516:11] wire _tlb_io_resp_miss; // @[frontend.scala:337:19] wire [31:0] _tlb_io_resp_paddr; // @[frontend.scala:337:19] wire [39:0] _tlb_io_resp_gpa; // @[frontend.scala:337:19] wire _tlb_io_resp_pf_ld; // @[frontend.scala:337:19] wire _tlb_io_resp_pf_inst; // @[frontend.scala:337:19] wire _tlb_io_resp_ae_ld; // @[frontend.scala:337:19] wire _tlb_io_resp_ae_inst; // @[frontend.scala:337:19] wire _tlb_io_resp_ma_ld; // @[frontend.scala:337:19] wire _tlb_io_resp_cacheable; // @[frontend.scala:337:19] wire _tlb_io_resp_prefetchable; // @[frontend.scala:337:19] wire [39:0] _ras_io_read_addr; // @[frontend.scala:333:19] wire _bpd_io_resp_f1_preds_0_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_0_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_0_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_0_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_0_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_1_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_1_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_1_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_1_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_1_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_2_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_2_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_2_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_2_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_2_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_3_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_3_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_3_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f1_preds_3_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f1_preds_3_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_0_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_0_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_0_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_0_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_0_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_1_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_1_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_1_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_1_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_1_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_2_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_2_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_2_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_2_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_2_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_3_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_3_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_3_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f2_preds_3_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f2_preds_3_predicted_pc_bits; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_pc; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_0_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_0_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_0_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_0_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_0_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_1_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_1_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_1_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_1_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_1_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_2_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_2_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_2_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_2_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_2_predicted_pc_bits; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_3_taken; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_3_is_br; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_3_is_jal; // @[frontend.scala:331:19] wire _bpd_io_resp_f3_preds_3_predicted_pc_valid; // @[frontend.scala:331:19] wire [39:0] _bpd_io_resp_f3_preds_3_predicted_pc_bits; // @[frontend.scala:331:19] wire [119:0] _bpd_io_resp_f3_meta_0; // @[frontend.scala:331:19] wire _icache_io_resp_valid; // @[frontend.scala:299:26] wire [63:0] _icache_io_resp_bits_data; // @[frontend.scala:299:26] wire auto_icache_master_out_a_ready_0 = auto_icache_master_out_a_ready; // @[frontend.scala:322:7] wire auto_icache_master_out_d_valid_0 = auto_icache_master_out_d_valid; // @[frontend.scala:322:7] wire [2:0] auto_icache_master_out_d_bits_opcode_0 = auto_icache_master_out_d_bits_opcode; // @[frontend.scala:322:7] wire [1:0] auto_icache_master_out_d_bits_param_0 = auto_icache_master_out_d_bits_param; // @[frontend.scala:322:7] wire [3:0] auto_icache_master_out_d_bits_size_0 = auto_icache_master_out_d_bits_size; // @[frontend.scala:322:7] wire [2:0] auto_icache_master_out_d_bits_sink_0 = auto_icache_master_out_d_bits_sink; // @[frontend.scala:322:7] wire auto_icache_master_out_d_bits_denied_0 = auto_icache_master_out_d_bits_denied; // @[frontend.scala:322:7] wire [63:0] auto_icache_master_out_d_bits_data_0 = auto_icache_master_out_d_bits_data; // @[frontend.scala:322:7] wire auto_icache_master_out_d_bits_corrupt_0 = auto_icache_master_out_d_bits_corrupt; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_ready_0 = io_cpu_fetchpacket_ready; // @[frontend.scala:322:7] wire [3:0] io_cpu_get_pc_0_ftq_idx_0 = io_cpu_get_pc_0_ftq_idx; // @[frontend.scala:322:7] wire [3:0] io_cpu_get_pc_1_ftq_idx_0 = io_cpu_get_pc_1_ftq_idx; // @[frontend.scala:322:7] wire io_cpu_status_debug_0 = io_cpu_status_debug; // @[frontend.scala:322:7] wire io_cpu_status_cease_0 = io_cpu_status_cease; // @[frontend.scala:322:7] wire io_cpu_status_wfi_0 = io_cpu_status_wfi; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_dprv_0 = io_cpu_status_dprv; // @[frontend.scala:322:7] wire io_cpu_status_dv_0 = io_cpu_status_dv; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_prv_0 = io_cpu_status_prv; // @[frontend.scala:322:7] wire io_cpu_status_v_0 = io_cpu_status_v; // @[frontend.scala:322:7] wire io_cpu_status_sd_0 = io_cpu_status_sd; // @[frontend.scala:322:7] wire io_cpu_status_mpv_0 = io_cpu_status_mpv; // @[frontend.scala:322:7] wire io_cpu_status_gva_0 = io_cpu_status_gva; // @[frontend.scala:322:7] wire io_cpu_status_tsr_0 = io_cpu_status_tsr; // @[frontend.scala:322:7] wire io_cpu_status_tw_0 = io_cpu_status_tw; // @[frontend.scala:322:7] wire io_cpu_status_tvm_0 = io_cpu_status_tvm; // @[frontend.scala:322:7] wire io_cpu_status_mxr_0 = io_cpu_status_mxr; // @[frontend.scala:322:7] wire io_cpu_status_sum_0 = io_cpu_status_sum; // @[frontend.scala:322:7] wire io_cpu_status_mprv_0 = io_cpu_status_mprv; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_fs_0 = io_cpu_status_fs; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_mpp_0 = io_cpu_status_mpp; // @[frontend.scala:322:7] wire io_cpu_status_spp_0 = io_cpu_status_spp; // @[frontend.scala:322:7] wire io_cpu_status_mpie_0 = io_cpu_status_mpie; // @[frontend.scala:322:7] wire io_cpu_status_spie_0 = io_cpu_status_spie; // @[frontend.scala:322:7] wire io_cpu_status_mie_0 = io_cpu_status_mie; // @[frontend.scala:322:7] wire io_cpu_status_sie_0 = io_cpu_status_sie; // @[frontend.scala:322:7] wire io_cpu_sfence_valid_0 = io_cpu_sfence_valid; // @[frontend.scala:322:7] wire io_cpu_sfence_bits_rs1_0 = io_cpu_sfence_bits_rs1; // @[frontend.scala:322:7] wire io_cpu_sfence_bits_rs2_0 = io_cpu_sfence_bits_rs2; // @[frontend.scala:322:7] wire [38:0] io_cpu_sfence_bits_addr_0 = io_cpu_sfence_bits_addr; // @[frontend.scala:322:7] wire io_cpu_sfence_bits_asid_0 = io_cpu_sfence_bits_asid; // @[frontend.scala:322:7] wire [7:0] io_cpu_brupdate_b1_resolve_mask_0 = io_cpu_brupdate_b1_resolve_mask; // @[frontend.scala:322:7] wire [7:0] io_cpu_brupdate_b1_mispredict_mask_0 = io_cpu_brupdate_b1_mispredict_mask; // @[frontend.scala:322:7] wire [6:0] io_cpu_brupdate_b2_uop_uopc_0 = io_cpu_brupdate_b2_uop_uopc; // @[frontend.scala:322:7] wire [31:0] io_cpu_brupdate_b2_uop_inst_0 = io_cpu_brupdate_b2_uop_inst; // @[frontend.scala:322:7] wire [31:0] io_cpu_brupdate_b2_uop_debug_inst_0 = io_cpu_brupdate_b2_uop_debug_inst; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_rvc_0 = io_cpu_brupdate_b2_uop_is_rvc; // @[frontend.scala:322:7] wire [39:0] io_cpu_brupdate_b2_uop_debug_pc_0 = io_cpu_brupdate_b2_uop_debug_pc; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_uop_iq_type_0 = io_cpu_brupdate_b2_uop_iq_type; // @[frontend.scala:322:7] wire [9:0] io_cpu_brupdate_b2_uop_fu_code_0 = io_cpu_brupdate_b2_uop_fu_code; // @[frontend.scala:322:7] wire [3:0] io_cpu_brupdate_b2_uop_ctrl_br_type_0 = io_cpu_brupdate_b2_uop_ctrl_br_type; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_ctrl_op1_sel_0 = io_cpu_brupdate_b2_uop_ctrl_op1_sel; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_uop_ctrl_op2_sel_0 = io_cpu_brupdate_b2_uop_ctrl_op2_sel; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_uop_ctrl_imm_sel_0 = io_cpu_brupdate_b2_uop_ctrl_imm_sel; // @[frontend.scala:322:7] wire [4:0] io_cpu_brupdate_b2_uop_ctrl_op_fcn_0 = io_cpu_brupdate_b2_uop_ctrl_op_fcn; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ctrl_fcn_dw_0 = io_cpu_brupdate_b2_uop_ctrl_fcn_dw; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_uop_ctrl_csr_cmd_0 = io_cpu_brupdate_b2_uop_ctrl_csr_cmd; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ctrl_is_load_0 = io_cpu_brupdate_b2_uop_ctrl_is_load; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ctrl_is_sta_0 = io_cpu_brupdate_b2_uop_ctrl_is_sta; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ctrl_is_std_0 = io_cpu_brupdate_b2_uop_ctrl_is_std; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_iw_state_0 = io_cpu_brupdate_b2_uop_iw_state; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_iw_p1_poisoned_0 = io_cpu_brupdate_b2_uop_iw_p1_poisoned; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_iw_p2_poisoned_0 = io_cpu_brupdate_b2_uop_iw_p2_poisoned; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_br_0 = io_cpu_brupdate_b2_uop_is_br; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_jalr_0 = io_cpu_brupdate_b2_uop_is_jalr; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_jal_0 = io_cpu_brupdate_b2_uop_is_jal; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_sfb_0 = io_cpu_brupdate_b2_uop_is_sfb; // @[frontend.scala:322:7] wire [7:0] io_cpu_brupdate_b2_uop_br_mask_0 = io_cpu_brupdate_b2_uop_br_mask; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_uop_br_tag_0 = io_cpu_brupdate_b2_uop_br_tag; // @[frontend.scala:322:7] wire [3:0] io_cpu_brupdate_b2_uop_ftq_idx_0 = io_cpu_brupdate_b2_uop_ftq_idx; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_edge_inst_0 = io_cpu_brupdate_b2_uop_edge_inst; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_pc_lob_0 = io_cpu_brupdate_b2_uop_pc_lob; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_taken_0 = io_cpu_brupdate_b2_uop_taken; // @[frontend.scala:322:7] wire [19:0] io_cpu_brupdate_b2_uop_imm_packed_0 = io_cpu_brupdate_b2_uop_imm_packed; // @[frontend.scala:322:7] wire [11:0] io_cpu_brupdate_b2_uop_csr_addr_0 = io_cpu_brupdate_b2_uop_csr_addr; // @[frontend.scala:322:7] wire [4:0] io_cpu_brupdate_b2_uop_rob_idx_0 = io_cpu_brupdate_b2_uop_rob_idx; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_uop_ldq_idx_0 = io_cpu_brupdate_b2_uop_ldq_idx; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_uop_stq_idx_0 = io_cpu_brupdate_b2_uop_stq_idx; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_rxq_idx_0 = io_cpu_brupdate_b2_uop_rxq_idx; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_pdst_0 = io_cpu_brupdate_b2_uop_pdst; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_prs1_0 = io_cpu_brupdate_b2_uop_prs1; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_prs2_0 = io_cpu_brupdate_b2_uop_prs2; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_prs3_0 = io_cpu_brupdate_b2_uop_prs3; // @[frontend.scala:322:7] wire [3:0] io_cpu_brupdate_b2_uop_ppred_0 = io_cpu_brupdate_b2_uop_ppred; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_prs1_busy_0 = io_cpu_brupdate_b2_uop_prs1_busy; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_prs2_busy_0 = io_cpu_brupdate_b2_uop_prs2_busy; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_prs3_busy_0 = io_cpu_brupdate_b2_uop_prs3_busy; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ppred_busy_0 = io_cpu_brupdate_b2_uop_ppred_busy; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_stale_pdst_0 = io_cpu_brupdate_b2_uop_stale_pdst; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_exception_0 = io_cpu_brupdate_b2_uop_exception; // @[frontend.scala:322:7] wire [63:0] io_cpu_brupdate_b2_uop_exc_cause_0 = io_cpu_brupdate_b2_uop_exc_cause; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_bypassable_0 = io_cpu_brupdate_b2_uop_bypassable; // @[frontend.scala:322:7] wire [4:0] io_cpu_brupdate_b2_uop_mem_cmd_0 = io_cpu_brupdate_b2_uop_mem_cmd; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_mem_size_0 = io_cpu_brupdate_b2_uop_mem_size; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_mem_signed_0 = io_cpu_brupdate_b2_uop_mem_signed; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_fence_0 = io_cpu_brupdate_b2_uop_is_fence; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_fencei_0 = io_cpu_brupdate_b2_uop_is_fencei; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_amo_0 = io_cpu_brupdate_b2_uop_is_amo; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_uses_ldq_0 = io_cpu_brupdate_b2_uop_uses_ldq; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_uses_stq_0 = io_cpu_brupdate_b2_uop_uses_stq; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_sys_pc2epc_0 = io_cpu_brupdate_b2_uop_is_sys_pc2epc; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_is_unique_0 = io_cpu_brupdate_b2_uop_is_unique; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_flush_on_commit_0 = io_cpu_brupdate_b2_uop_flush_on_commit; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ldst_is_rs1_0 = io_cpu_brupdate_b2_uop_ldst_is_rs1; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_ldst_0 = io_cpu_brupdate_b2_uop_ldst; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_lrs1_0 = io_cpu_brupdate_b2_uop_lrs1; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_lrs2_0 = io_cpu_brupdate_b2_uop_lrs2; // @[frontend.scala:322:7] wire [5:0] io_cpu_brupdate_b2_uop_lrs3_0 = io_cpu_brupdate_b2_uop_lrs3; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_ldst_val_0 = io_cpu_brupdate_b2_uop_ldst_val; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_dst_rtype_0 = io_cpu_brupdate_b2_uop_dst_rtype; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_lrs1_rtype_0 = io_cpu_brupdate_b2_uop_lrs1_rtype; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_lrs2_rtype_0 = io_cpu_brupdate_b2_uop_lrs2_rtype; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_frs3_en_0 = io_cpu_brupdate_b2_uop_frs3_en; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_fp_val_0 = io_cpu_brupdate_b2_uop_fp_val; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_fp_single_0 = io_cpu_brupdate_b2_uop_fp_single; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_xcpt_pf_if_0 = io_cpu_brupdate_b2_uop_xcpt_pf_if; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_xcpt_ae_if_0 = io_cpu_brupdate_b2_uop_xcpt_ae_if; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_xcpt_ma_if_0 = io_cpu_brupdate_b2_uop_xcpt_ma_if; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_bp_debug_if_0 = io_cpu_brupdate_b2_uop_bp_debug_if; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_uop_bp_xcpt_if_0 = io_cpu_brupdate_b2_uop_bp_xcpt_if; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_debug_fsrc_0 = io_cpu_brupdate_b2_uop_debug_fsrc; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_uop_debug_tsrc_0 = io_cpu_brupdate_b2_uop_debug_tsrc; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_valid_0 = io_cpu_brupdate_b2_valid; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_mispredict_0 = io_cpu_brupdate_b2_mispredict; // @[frontend.scala:322:7] wire io_cpu_brupdate_b2_taken_0 = io_cpu_brupdate_b2_taken; // @[frontend.scala:322:7] wire [2:0] io_cpu_brupdate_b2_cfi_type_0 = io_cpu_brupdate_b2_cfi_type; // @[frontend.scala:322:7] wire [1:0] io_cpu_brupdate_b2_pc_sel_0 = io_cpu_brupdate_b2_pc_sel; // @[frontend.scala:322:7] wire [39:0] io_cpu_brupdate_b2_jalr_target_0 = io_cpu_brupdate_b2_jalr_target; // @[frontend.scala:322:7] wire [20:0] io_cpu_brupdate_b2_target_offset_0 = io_cpu_brupdate_b2_target_offset; // @[frontend.scala:322:7] wire io_cpu_redirect_flush_0 = io_cpu_redirect_flush; // @[frontend.scala:322:7] wire io_cpu_redirect_val_0 = io_cpu_redirect_val; // @[frontend.scala:322:7] wire [39:0] io_cpu_redirect_pc_0 = io_cpu_redirect_pc; // @[frontend.scala:322:7] wire [3:0] io_cpu_redirect_ftq_idx_0 = io_cpu_redirect_ftq_idx; // @[frontend.scala:322:7] wire [63:0] io_cpu_redirect_ghist_old_history_0 = io_cpu_redirect_ghist_old_history; // @[frontend.scala:322:7] wire io_cpu_redirect_ghist_current_saw_branch_not_taken_0 = io_cpu_redirect_ghist_current_saw_branch_not_taken; // @[frontend.scala:322:7] wire io_cpu_redirect_ghist_new_saw_branch_not_taken_0 = io_cpu_redirect_ghist_new_saw_branch_not_taken; // @[frontend.scala:322:7] wire io_cpu_redirect_ghist_new_saw_branch_taken_0 = io_cpu_redirect_ghist_new_saw_branch_taken; // @[frontend.scala:322:7] wire [4:0] io_cpu_redirect_ghist_ras_idx_0 = io_cpu_redirect_ghist_ras_idx; // @[frontend.scala:322:7] wire io_cpu_commit_valid_0 = io_cpu_commit_valid; // @[frontend.scala:322:7] wire [15:0] io_cpu_commit_bits_0 = io_cpu_commit_bits; // @[frontend.scala:322:7] wire io_cpu_flush_icache_0 = io_cpu_flush_icache; // @[frontend.scala:322:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[frontend.scala:322:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[frontend.scala:322:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[frontend.scala:322:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[frontend.scala:322:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[frontend.scala:322:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[frontend.scala:322:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[frontend.scala:322:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[frontend.scala:322:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[frontend.scala:322:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[frontend.scala:322:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[frontend.scala:322:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[frontend.scala:322:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[frontend.scala:322:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[frontend.scala:322:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[frontend.scala:322:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[frontend.scala:322:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[frontend.scala:322:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[frontend.scala:322:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[frontend.scala:322:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[frontend.scala:322:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[frontend.scala:322:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[frontend.scala:322:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[frontend.scala:322:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[frontend.scala:322:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[frontend.scala:322:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[frontend.scala:322:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[frontend.scala:322:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[frontend.scala:322:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[frontend.scala:322:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[frontend.scala:322:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[frontend.scala:322:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[frontend.scala:322:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[frontend.scala:322:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[frontend.scala:322:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[frontend.scala:322:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[frontend.scala:322:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[frontend.scala:322:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[frontend.scala:322:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[frontend.scala:322:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[frontend.scala:322:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[frontend.scala:322:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[frontend.scala:322:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[frontend.scala:322:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[frontend.scala:322:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[frontend.scala:322:7] wire [6:0] io_cpu_fetchpacket_bits_uops_0_bits_uopc = 7'h0; // @[frontend.scala:322:7] wire [2:0] auto_icache_master_out_a_bits_param = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_0_bits_iq_type = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_op2_sel = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_imm_sel = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_csr_cmd = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_0_bits_br_tag = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_0_bits_ldq_idx = 3'h0; // @[frontend.scala:322:7] wire [2:0] io_cpu_fetchpacket_bits_uops_0_bits_stq_idx = 3'h0; // @[frontend.scala:322:7] wire [2:0] _upper_mask_T_2 = 3'h0; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_6 = 3'h0; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_10 = 3'h0; // @[frontend.scala:715:86] wire [2:0] _upper_mask_T_14 = 3'h0; // @[frontend.scala:715:86] wire [9:0] io_cpu_fetchpacket_bits_uops_0_bits_fu_code = 10'h0; // @[frontend.scala:322:7] wire [3:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_br_type = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_cpu_fetchpacket_bits_uops_0_bits_ppred = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_cpu_debug_ftq_idx_0 = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[frontend.scala:322:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[frontend.scala:322:7] wire [3:0] f3_fetch_bundle_ftq_idx = 4'h0; // @[frontend.scala:569:29] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_op1_sel = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_iw_state = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_rxq_idx = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_mem_size = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_dst_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_lrs1_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_lrs2_rtype = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_tsrc = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_xs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_vs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[frontend.scala:322:7] wire [1:0] _offset_from_aligned_pc_T_8 = 2'h0; // @[frontend.scala:710:12] wire [1:0] _offset_from_aligned_pc_T_13 = 2'h0; // @[frontend.scala:710:12] wire [1:0] _offset_from_aligned_pc_T_18 = 2'h0; // @[frontend.scala:710:12] wire [4:0] io_cpu_fetchpacket_bits_uops_0_bits_ctrl_op_fcn = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_0_bits_rob_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_fetchpacket_bits_uops_0_bits_mem_cmd = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_0_ghist_ras_idx = 5'h0; // @[frontend.scala:322:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[frontend.scala:322:7] wire [4:0] _s0_ghist_WIRE_ras_idx = 5'h0; // @[frontend.scala:348:45] wire [4:0] _s0_ghist_WIRE_1_ras_idx = 5'h0; // @[frontend.scala:364:33] wire auto_icache_master_out_a_bits_source = 1'h0; // @[frontend.scala:322:7] wire auto_icache_master_out_a_bits_corrupt = 1'h0; // @[frontend.scala:322:7] wire auto_icache_master_out_d_bits_source = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ctrl_fcn_dw = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ctrl_is_load = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ctrl_is_sta = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ctrl_is_std = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_iw_p1_poisoned = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_iw_p2_poisoned = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_br = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_jalr = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_jal = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_prs1_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_prs2_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_prs3_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ppred_busy = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_exception = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_bypassable = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_mem_signed = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_fence = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_fencei = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_amo = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_uses_ldq = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_uses_stq = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_sys_pc2epc = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_unique = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_flush_on_commit = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ldst_is_rs1 = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_ldst_val = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_frs3_en = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_fp_val = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_fp_single = 1'h0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ma_if = 1'h0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_ghist_new_saw_branch_not_taken = 1'h0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_ghist_new_saw_branch_taken = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_mbe = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_sbe = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_sd_rv32 = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_ube = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_upie = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_hie = 1'h0; // @[frontend.scala:322:7] wire io_cpu_status_uie = 1'h0; // @[frontend.scala:322:7] wire io_cpu_sfence_bits_hv = 1'h0; // @[frontend.scala:322:7] wire io_cpu_sfence_bits_hg = 1'h0; // @[frontend.scala:322:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[frontend.scala:322:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[frontend.scala:322:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_mbe = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_sbe = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_ube = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_upie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_hie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_status_uie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_vtw = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_hu = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_spvp = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_spv = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_gva = 1'h0; // @[frontend.scala:322:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_debug = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_cease = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_wfi = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_dv = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_v = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_sd = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mpv = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_gva = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mbe = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_sbe = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_tsr = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_tw = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_tvm = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mxr = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_sum = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mprv = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_spp = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mpie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_ube = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_spie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_upie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_mie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_hie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_sie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_gstatus_uie = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[frontend.scala:322:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[frontend.scala:322:7] wire _s0_ghist_WIRE_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:348:45] wire _s0_ghist_WIRE_new_saw_branch_not_taken = 1'h0; // @[frontend.scala:348:45] wire _s0_ghist_WIRE_new_saw_branch_taken = 1'h0; // @[frontend.scala:348:45] wire s0_replay_bpd_resp_lhist_0 = 1'h0; // @[frontend.scala:354:32] wire _s0_ghist_WIRE_1_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:364:33] wire _s0_ghist_WIRE_1_new_saw_branch_not_taken = 1'h0; // @[frontend.scala:364:33] wire _s0_ghist_WIRE_1_new_saw_branch_taken = 1'h0; // @[frontend.scala:364:33] wire f1_predicted_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27] wire f1_predicted_ghist_new_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27] wire f1_predicted_ghist_new_saw_branch_taken = 1'h0; // @[frontend.scala:87:27] wire _f1_predicted_ghist_new_history_ras_idx_T = 1'h0; // @[frontend.scala:123:42] wire _f1_predicted_ghist_new_history_ras_idx_T_4 = 1'h0; // @[frontend.scala:124:42] wire f2_predicted_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27] wire f2_predicted_ghist_new_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27] wire f2_predicted_ghist_new_saw_branch_taken = 1'h0; // @[frontend.scala:87:27] wire _f2_predicted_ghist_new_history_ras_idx_T = 1'h0; // @[frontend.scala:123:42] wire _f2_predicted_ghist_new_history_ras_idx_T_4 = 1'h0; // @[frontend.scala:124:42] wire f3_is_last_bank_in_block = 1'h0; // @[frontend.scala:152:21] wire f3_shadowed_mask_0 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_1 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_2 = 1'h0; // @[frontend.scala:568:30] wire f3_shadowed_mask_3 = 1'h0; // @[frontend.scala:568:30] wire f3_fetch_bundle_shadowed_mask_0 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_1 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_2 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowed_mask_3 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_0 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_1 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_2 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_debug_if_oh_3 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_0 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_1 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_2 = 1'h0; // @[frontend.scala:569:29] wire f3_fetch_bundle_bp_xcpt_if_oh_3 = 1'h0; // @[frontend.scala:569:29] wire _offset_from_aligned_pc_T_7 = 1'h0; // @[frontend.scala:710:31] wire _offset_from_aligned_pc_T_12 = 1'h0; // @[frontend.scala:710:31] wire _offset_from_aligned_pc_T_17 = 1'h0; // @[frontend.scala:710:31] wire f3_predicted_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27] wire f3_predicted_ghist_new_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27] wire f3_predicted_ghist_new_saw_branch_taken = 1'h0; // @[frontend.scala:87:27] wire _f4_sfbs_T_17 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_35 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_53 = 1'h0; // @[frontend.scala:876:20] wire _f4_sfbs_T_71 = 1'h0; // @[frontend.scala:876:20] wire f4_sfbs_0 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_1 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_2 = 1'h0; // @[frontend.scala:875:24] wire f4_sfbs_3 = 1'h0; // @[frontend.scala:875:24] wire _f4_sfb_valid_T = 1'h0; // @[frontend.scala:890:38] wire _f4_sfb_valid_T_1 = 1'h0; // @[frontend.scala:890:38] wire _f4_sfb_valid_T_2 = 1'h0; // @[frontend.scala:890:38] wire f4_sfb_valid = 1'h0; // @[frontend.scala:890:43] wire [7:0] io_cpu_fetchpacket_bits_uops_0_bits_br_mask = 8'h0; // @[frontend.scala:322:7] wire [7:0] io_cpu_status_zero1 = 8'h0; // @[frontend.scala:322:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[frontend.scala:322:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[frontend.scala:322:7] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_1 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_2 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_3 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_4 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_5 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_6 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_7 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_2 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_3 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_4 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_5 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_6 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_7 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_3 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_4 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_5 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_6 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_7 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_4 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_5 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_6 = 8'h0; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_7 = 8'h0; // @[util.scala:373:29] wire [19:0] io_cpu_fetchpacket_bits_uops_0_bits_imm_packed = 20'h0; // @[frontend.scala:322:7] wire [11:0] io_cpu_fetchpacket_bits_uops_0_bits_csr_addr = 12'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_pdst = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_prs1 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_prs2 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_prs3 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_stale_pdst = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_ldst = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_lrs1 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_lrs2 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_lrs3 = 6'h0; // @[frontend.scala:322:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[frontend.scala:322:7] wire [63:0] auto_icache_master_out_a_bits_data = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_cpu_fetchpacket_bits_uops_0_bits_exc_cause = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_cpu_get_pc_0_ghist_old_history = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[frontend.scala:322:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[frontend.scala:322:7] wire [63:0] _s0_ghist_WIRE_old_history = 64'h0; // @[frontend.scala:348:45] wire [63:0] _s0_ghist_WIRE_1_old_history = 64'h0; // @[frontend.scala:364:33] wire [31:0] io_cpu_status_isa = 32'h14112D; // @[frontend.scala:322:7] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[frontend.scala:322:7] wire [22:0] io_cpu_status_zero2 = 23'h0; // @[frontend.scala:322:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[frontend.scala:322:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[frontend.scala:322:7] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[frontend.scala:322:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[frontend.scala:322:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[frontend.scala:322:7] wire [2:0] auto_icache_master_out_a_bits_opcode = 3'h4; // @[frontend.scala:322:7] wire [3:0] auto_icache_master_out_a_bits_size = 4'h6; // @[frontend.scala:322:7] wire [7:0] auto_icache_master_out_a_bits_mask = 8'hFF; // @[frontend.scala:322:7] wire auto_icache_master_out_d_ready = 1'h1; // @[frontend.scala:322:7] wire io_ptw_req_bits_valid = 1'h1; // @[frontend.scala:322:7] wire valid = 1'h1; // @[frontend.scala:605:23] wire _bank_mask_0_T_3 = 1'h1; // @[frontend.scala:689:74] wire _f3_mask_0_T_3 = 1'h1; // @[frontend.scala:690:74] wire [31:0] auto_reset_vector_sink_in = 32'h10000; // @[frontend.scala:322:7] wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[MixedNode.scala:551:17] wire [1:0] io_cpu_status_sxl = 2'h2; // @[frontend.scala:322:7] wire [1:0] io_cpu_status_uxl = 2'h2; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[frontend.scala:322:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[frontend.scala:322:7] wire [1:0] _lower_mask_T_1 = 2'h2; // @[OneHot.scala:58:35] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[frontend.scala:322:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[frontend.scala:322:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[frontend.scala:322:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[frontend.scala:322:7] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[frontend.scala:322:7] wire [1:0] _f4_sfb_idx_T = 2'h3; // @[Mux.scala:50:70] wire [1:0] _f4_sfb_idx_T_1 = 2'h3; // @[Mux.scala:50:70] wire [1:0] f4_sfb_idx = 2'h3; // @[Mux.scala:50:70] wire [3:0] _f1_predicted_ghist_not_taken_branches_T_11 = 4'hF; // @[frontend.scala:91:45] wire [3:0] _f2_predicted_ghist_not_taken_branches_T_11 = 4'hF; // @[frontend.scala:91:45] wire [3:0] _f3_predicted_ghist_not_taken_branches_T_11 = 4'hF; // @[frontend.scala:91:45] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_15 = 8'hF0; // @[frontend.scala:722:45] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_10 = 8'hF; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_11 = 8'hF; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_12 = 8'hF; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_13 = 8'hF; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_14 = 8'hF; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_9 = 8'hE; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_8 = 8'hC; // @[util.scala:373:45] wire [7:0] lower_mask = 8'h1; // @[frontend.scala:712:28] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T = 8'h1; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_8 = 8'h1; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_9 = 8'h1; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_10 = 8'h1; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_11 = 8'h1; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_12 = 8'h1; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_13 = 8'h1; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_14 = 8'h1; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_1 = 8'h1; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_2 = 8'h1; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_3 = 8'h1; // @[util.scala:373:29] wire [7:0] lower_mask_1 = 8'h2; // @[frontend.scala:712:28] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T = 8'h2; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_1 = 8'h2; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_2 = 8'h2; // @[util.scala:373:29] wire [7:0] lower_mask_2 = 8'h4; // @[frontend.scala:712:28] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T = 8'h4; // @[util.scala:373:29] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_1 = 8'h4; // @[util.scala:373:29] wire [7:0] lower_mask_3 = 8'h8; // @[frontend.scala:712:28] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T = 8'h8; // @[util.scala:373:29] wire [4:0] _f3_fetch_bundle_sfbs_0_T_1 = 5'h10; // @[frontend.scala:720:39] wire [4:0] _f3_fetch_bundle_sfbs_1_T_1 = 5'h10; // @[frontend.scala:720:39] wire [4:0] _f3_fetch_bundle_sfbs_2_T_1 = 5'h10; // @[frontend.scala:720:39] wire [4:0] _f3_fetch_bundle_sfbs_3_T_1 = 5'h10; // @[frontend.scala:720:39] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_15 = 8'hF8; // @[frontend.scala:722:45] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_9 = 8'h7; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_10 = 8'h7; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_11 = 8'h7; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_12 = 8'h7; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_13 = 8'h7; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_14 = 8'h7; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_8 = 8'h6; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_15 = 8'hFC; // @[frontend.scala:722:45] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_8 = 8'h3; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_9 = 8'h3; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_10 = 8'h3; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_11 = 8'h3; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_12 = 8'h3; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_13 = 8'h3; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_14 = 8'h3; // @[util.scala:373:45] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_15 = 8'hFE; // @[frontend.scala:722:45] wire [119:0] s0_replay_bpd_resp_meta_0 = 120'h0; // @[frontend.scala:354:32] wire [3:0] _lower_mask_T_2 = 4'h4; // @[OneHot.scala:58:35] wire [1:0] _lower_mask_T = 2'h1; // @[OneHot.scala:58:35] wire [3:0] _lower_mask_T_3 = 4'h8; // @[OneHot.scala:58:35] wire s0_is_sfence = io_cpu_sfence_valid_0; // @[frontend.scala:322:7, :352:30] wire _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire [31:0] auto_icache_master_out_a_bits_address_0; // @[frontend.scala:322:7] wire auto_icache_master_out_a_valid_0; // @[frontend.scala:322:7] wire [31:0] io_cpu_fetchpacket_bits_uops_0_bits_inst_0; // @[frontend.scala:322:7] wire [31:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_inst_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_rvc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_pc_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_is_sfb_0; // @[frontend.scala:322:7] wire [3:0] io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_edge_inst_0; // @[frontend.scala:322:7] wire [5:0] io_cpu_fetchpacket_bits_uops_0_bits_pc_lob_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_taken_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if_0; // @[frontend.scala:322:7] wire [1:0] io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_bits_uops_0_valid_0; // @[frontend.scala:322:7] wire io_cpu_fetchpacket_valid_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_idx_valid_0; // @[frontend.scala:322:7] wire [1:0] io_cpu_get_pc_0_entry_cfi_idx_bits_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_taken_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_mispredicted_0; // @[frontend.scala:322:7] wire [2:0] io_cpu_get_pc_0_entry_cfi_type_0; // @[frontend.scala:322:7] wire [3:0] io_cpu_get_pc_0_entry_br_mask_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_is_call_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_is_ret_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_cfi_npc_plus4_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_0_entry_ras_top_0; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_0_entry_ras_idx_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_entry_start_bank_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_0_pc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_0_com_pc_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_0_next_val_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_0_next_pc_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_idx_valid_0; // @[frontend.scala:322:7] wire [1:0] io_cpu_get_pc_1_entry_cfi_idx_bits_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_taken_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_mispredicted_0; // @[frontend.scala:322:7] wire [2:0] io_cpu_get_pc_1_entry_cfi_type_0; // @[frontend.scala:322:7] wire [3:0] io_cpu_get_pc_1_entry_br_mask_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_is_call_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_is_ret_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_cfi_npc_plus4_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_1_entry_ras_top_0; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_1_entry_ras_idx_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_entry_start_bank_0; // @[frontend.scala:322:7] wire [63:0] io_cpu_get_pc_1_ghist_old_history_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_ghist_current_saw_branch_not_taken_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_ghist_new_saw_branch_not_taken_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_ghist_new_saw_branch_taken_0; // @[frontend.scala:322:7] wire [4:0] io_cpu_get_pc_1_ghist_ras_idx_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_1_pc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_1_com_pc_0; // @[frontend.scala:322:7] wire io_cpu_get_pc_1_next_val_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_get_pc_1_next_pc_0; // @[frontend.scala:322:7] wire [39:0] io_cpu_debug_fetch_pc_0_0; // @[frontend.scala:322:7] wire io_cpu_perf_acquire_0; // @[frontend.scala:322:7] wire io_cpu_perf_tlbMiss_0; // @[frontend.scala:322:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[frontend.scala:322:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[frontend.scala:322:7] wire io_ptw_req_valid_0; // @[frontend.scala:322:7] assign _io_cpu_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] assign io_cpu_perf_tlbMiss_0 = _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire [39:0] s0_vpc; // @[frontend.scala:347:30] wire [63:0] s0_ghist_old_history; // @[frontend.scala:348:30] wire s0_ghist_current_saw_branch_not_taken; // @[frontend.scala:348:30] wire s0_ghist_new_saw_branch_not_taken; // @[frontend.scala:348:30] wire s0_ghist_new_saw_branch_taken; // @[frontend.scala:348:30] wire [4:0] s0_ghist_ras_idx; // @[frontend.scala:348:30] wire [1:0] s0_tsrc; // @[frontend.scala:349:30] wire s0_valid; // @[frontend.scala:350:30] wire s0_is_replay; // @[frontend.scala:351:30] wire s0_replay_resp_pf_ld; // @[frontend.scala:353:28] wire s0_replay_resp_pf_st; // @[frontend.scala:353:28] wire s0_replay_resp_pf_inst; // @[frontend.scala:353:28] wire s0_replay_resp_gf_ld; // @[frontend.scala:353:28] wire s0_replay_resp_gf_st; // @[frontend.scala:353:28] wire s0_replay_resp_gf_inst; // @[frontend.scala:353:28] wire s0_replay_resp_ae_ld; // @[frontend.scala:353:28] wire s0_replay_resp_ae_st; // @[frontend.scala:353:28] wire s0_replay_resp_ae_inst; // @[frontend.scala:353:28] wire s0_replay_resp_ma_ld; // @[frontend.scala:353:28] wire s0_replay_resp_ma_st; // @[frontend.scala:353:28] wire s0_replay_resp_ma_inst; // @[frontend.scala:353:28] wire s0_replay_resp_miss; // @[frontend.scala:353:28] wire [31:0] s0_replay_resp_paddr; // @[frontend.scala:353:28] wire [39:0] s0_replay_resp_gpa; // @[frontend.scala:353:28] wire s0_replay_resp_gpa_is_pte; // @[frontend.scala:353:28] wire s0_replay_resp_cacheable; // @[frontend.scala:353:28] wire s0_replay_resp_must_alloc; // @[frontend.scala:353:28] wire s0_replay_resp_prefetchable; // @[frontend.scala:353:28] wire [1:0] s0_replay_resp_size; // @[frontend.scala:353:28] wire [4:0] s0_replay_resp_cmd; // @[frontend.scala:353:28] wire s0_replay_bpd_resp_preds_0_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_0_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_0_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_0_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_0_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_1_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_1_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_1_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_1_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_1_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_2_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_2_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_2_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_2_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_2_is_jal; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_3_predicted_pc_valid; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_preds_3_predicted_pc_bits; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_3_taken; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_3_is_br; // @[frontend.scala:354:32] wire s0_replay_bpd_resp_preds_3_is_jal; // @[frontend.scala:354:32] wire [39:0] s0_replay_bpd_resp_pc; // @[frontend.scala:354:32] wire [31:0] s0_replay_ppc; // @[frontend.scala:355:28] wire s0_s1_use_f3_bpd_resp; // @[frontend.scala:356:39] reg REG; // @[frontend.scala:361:16] wire _T_3 = REG & ~reset; // @[frontend.scala:361:{16,31,34}] reg [39:0] s1_vpc; // @[frontend.scala:379:29] reg s1_valid; // @[frontend.scala:380:29] reg [63:0] s1_ghist_old_history; // @[frontend.scala:381:29] reg s1_ghist_current_saw_branch_not_taken; // @[frontend.scala:381:29] reg s1_ghist_new_saw_branch_not_taken; // @[frontend.scala:381:29] reg s1_ghist_new_saw_branch_taken; // @[frontend.scala:381:29] reg [4:0] s1_ghist_ras_idx; // @[frontend.scala:381:29] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_8 = s1_ghist_ras_idx; // @[frontend.scala:124:31, :381:29] reg s1_is_replay; // @[frontend.scala:382:29] reg s1_is_sfence; // @[frontend.scala:383:29] wire f1_clear; // @[frontend.scala:384:30] reg [1:0] s1_tsrc; // @[frontend.scala:385:29] wire _tlb_io_req_valid_T = ~s1_is_replay; // @[frontend.scala:382:29, :386:41] wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[frontend.scala:380:29, :386:{38,41}] wire _tlb_io_req_valid_T_2 = ~f1_clear; // @[frontend.scala:384:30, :386:58] wire _tlb_io_req_valid_T_3 = _tlb_io_req_valid_T_1 & _tlb_io_req_valid_T_2; // @[frontend.scala:386:{38,55,58}] wire _tlb_io_req_valid_T_4 = _tlb_io_req_valid_T_3 \| s1_is_sfence; // @[frontend.scala:383:29, :386:{55,69}] reg tlb_io_sfence_REG_valid; // @[frontend.scala:393:35] reg tlb_io_sfence_REG_bits_rs1; // @[frontend.scala:393:35] reg tlb_io_sfence_REG_bits_rs2; // @[frontend.scala:393:35] reg [38:0] tlb_io_sfence_REG_bits_addr; // @[frontend.scala:393:35] reg tlb_io_sfence_REG_bits_asid; // @[frontend.scala:393:35] reg tlb_io_sfence_REG_bits_hv; // @[frontend.scala:393:35] reg tlb_io_sfence_REG_bits_hg; // @[frontend.scala:393:35] wire _s1_tlb_miss_T = ~s1_is_replay; // @[frontend.scala:382:29, :386:41, :396:21] wire s1_tlb_miss = _s1_tlb_miss_T & _tlb_io_resp_miss; // @[frontend.scala:337:19, :396:{21,35}] reg s1_tlb_resp_REG_miss; // @[frontend.scala:397:46] reg [31:0] s1_tlb_resp_REG_paddr; // @[frontend.scala:397:46] reg [39:0] s1_tlb_resp_REG_gpa; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_gpa_is_pte; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_pf_ld; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_pf_st; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_pf_inst; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_gf_ld; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_gf_st; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_gf_inst; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ae_ld; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ae_st; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ae_inst; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ma_ld; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ma_st; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_ma_inst; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_cacheable; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_must_alloc; // @[frontend.scala:397:46] reg s1_tlb_resp_REG_prefetchable; // @[frontend.scala:397:46] reg [1:0] s1_tlb_resp_REG_size; // @[frontend.scala:397:46] reg [4:0] s1_tlb_resp_REG_cmd; // @[frontend.scala:397:46] wire s1_tlb_resp_miss = s1_is_replay ? s1_tlb_resp_REG_miss : _tlb_io_resp_miss; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire [31:0] s1_tlb_resp_paddr = s1_is_replay ? s1_tlb_resp_REG_paddr : _tlb_io_resp_paddr; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire [39:0] s1_tlb_resp_gpa = s1_is_replay ? s1_tlb_resp_REG_gpa : _tlb_io_resp_gpa; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_gpa_is_pte = s1_is_replay & s1_tlb_resp_REG_gpa_is_pte; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_pf_ld = s1_is_replay ? s1_tlb_resp_REG_pf_ld : _tlb_io_resp_pf_ld; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_pf_st = s1_is_replay & s1_tlb_resp_REG_pf_st; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_pf_inst = s1_is_replay ? s1_tlb_resp_REG_pf_inst : _tlb_io_resp_pf_inst; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_gf_ld = s1_is_replay & s1_tlb_resp_REG_gf_ld; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_gf_st = s1_is_replay & s1_tlb_resp_REG_gf_st; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_gf_inst = s1_is_replay & s1_tlb_resp_REG_gf_inst; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_ae_ld = s1_is_replay ? s1_tlb_resp_REG_ae_ld : _tlb_io_resp_ae_ld; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_ae_st = s1_is_replay & s1_tlb_resp_REG_ae_st; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_ae_inst = s1_is_replay ? s1_tlb_resp_REG_ae_inst : _tlb_io_resp_ae_inst; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_ma_ld = s1_is_replay ? s1_tlb_resp_REG_ma_ld : _tlb_io_resp_ma_ld; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_ma_st = s1_is_replay & s1_tlb_resp_REG_ma_st; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_ma_inst = s1_is_replay & s1_tlb_resp_REG_ma_inst; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_cacheable = s1_is_replay ? s1_tlb_resp_REG_cacheable : _tlb_io_resp_cacheable; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire s1_tlb_resp_must_alloc = s1_is_replay & s1_tlb_resp_REG_must_alloc; // @[frontend.scala:382:29, :397:{24,46}] wire s1_tlb_resp_prefetchable = s1_is_replay ? s1_tlb_resp_REG_prefetchable : _tlb_io_resp_prefetchable; // @[frontend.scala:337:19, :382:29, :397:{24,46}] wire [1:0] s1_tlb_resp_size = s1_is_replay ? s1_tlb_resp_REG_size : 2'h3; // @[frontend.scala:382:29, :397:{24,46}] wire [4:0] s1_tlb_resp_cmd = s1_is_replay ? s1_tlb_resp_REG_cmd : 5'h0; // @[frontend.scala:382:29, :397:{24,46}] reg [31:0] s1_ppc_REG; // @[frontend.scala:398:42] wire [31:0] s1_ppc = s1_is_replay ? s1_ppc_REG : _tlb_io_resp_paddr; // @[frontend.scala:337:19, :382:29, :398:{20,42}] wire _icache_io_s1_kill_T = _tlb_io_resp_miss \| f1_clear; // @[frontend.scala:337:19, :384:30, :402:42] wire [1:0] f1_mask_idx = s1_vpc[2:1]; // @[package.scala:163:13] wire [6:0] f1_mask = 7'hF << f1_mask_idx; // @[package.scala:163:13] wire _f1_redirects_T = f1_mask[0]; // @[frontend.scala:177:31, :406:24] wire _f1_redirects_T_1 = s1_valid & _f1_redirects_T; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_2 = _f1_redirects_T_1 & _bpd_io_resp_f1_preds_0_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_3 = _bpd_io_resp_f1_preds_0_is_br & _bpd_io_resp_f1_preds_0_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_4 = _bpd_io_resp_f1_preds_0_is_jal \| _f1_redirects_T_3; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_0 = _f1_redirects_T_2 & _f1_redirects_T_4; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_5 = f1_mask[1]; // @[frontend.scala:177:31, :406:24] wire _f1_redirects_T_6 = s1_valid & _f1_redirects_T_5; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_7 = _f1_redirects_T_6 & _bpd_io_resp_f1_preds_1_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_8 = _bpd_io_resp_f1_preds_1_is_br & _bpd_io_resp_f1_preds_1_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_9 = _bpd_io_resp_f1_preds_1_is_jal \| _f1_redirects_T_8; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_1 = _f1_redirects_T_7 & _f1_redirects_T_9; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_10 = f1_mask[2]; // @[frontend.scala:177:31, :406:24] wire _f1_redirects_T_11 = s1_valid & _f1_redirects_T_10; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_12 = _f1_redirects_T_11 & _bpd_io_resp_f1_preds_2_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_13 = _bpd_io_resp_f1_preds_2_is_br & _bpd_io_resp_f1_preds_2_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_14 = _bpd_io_resp_f1_preds_2_is_jal \| _f1_redirects_T_13; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_2 = _f1_redirects_T_12 & _f1_redirects_T_14; // @[frontend.scala:406:{28,71}, :407:34] wire _f1_redirects_T_15 = f1_mask[3]; // @[frontend.scala:177:31, :406:24] wire _f1_redirects_T_16 = s1_valid & _f1_redirects_T_15; // @[frontend.scala:380:29, :406:{14,24}] wire _f1_redirects_T_17 = _f1_redirects_T_16 & _bpd_io_resp_f1_preds_3_predicted_pc_valid; // @[frontend.scala:331:19, :406:{14,28}] wire _f1_redirects_T_18 = _bpd_io_resp_f1_preds_3_is_br & _bpd_io_resp_f1_preds_3_taken; // @[frontend.scala:331:19, :408:35] wire _f1_redirects_T_19 = _bpd_io_resp_f1_preds_3_is_jal \| _f1_redirects_T_18; // @[frontend.scala:331:19, :407:34, :408:35] wire f1_redirects_3 = _f1_redirects_T_17 & _f1_redirects_T_19; // @[frontend.scala:406:{28,71}, :407:34] wire [1:0] _f1_redirect_idx_T = {1'h1, ~f1_redirects_2}; // @[Mux.scala:50:70] wire [1:0] _f1_redirect_idx_T_1 = f1_redirects_1 ? 2'h1 : _f1_redirect_idx_T; // @[Mux.scala:50:70] wire [1:0] f1_redirect_idx = f1_redirects_0 ? 2'h0 : _f1_redirect_idx_T_1; // @[Mux.scala:50:70] wire [1:0] f1_predicted_ghist_cfi_idx_fixed = f1_redirect_idx; // @[Mux.scala:50:70] wire _f1_do_redirect_T = f1_redirects_0 \| f1_redirects_1; // @[frontend.scala:406:71, :411:45] wire _f1_do_redirect_T_1 = _f1_do_redirect_T \| f1_redirects_2; // @[frontend.scala:406:71, :411:45] wire _f1_do_redirect_T_2 = _f1_do_redirect_T_1 \| f1_redirects_3; // @[frontend.scala:406:71, :411:45] wire f1_do_redirect = _f1_do_redirect_T_2; // @[frontend.scala:411:{45,50}] wire _f1_predicted_target_T = f1_redirect_idx == 2'h1; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_1 = _f1_predicted_target_T ? _bpd_io_resp_f1_preds_1_predicted_pc_bits : _bpd_io_resp_f1_preds_0_predicted_pc_bits; // @[package.scala:39:{76,86}] wire _f1_predicted_target_T_2 = f1_redirect_idx == 2'h2; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_3 = _f1_predicted_target_T_2 ? _bpd_io_resp_f1_preds_2_predicted_pc_bits : _f1_predicted_target_T_1; // @[package.scala:39:{76,86}] wire _f1_predicted_target_T_4 = &f1_redirect_idx; // @[Mux.scala:50:70] wire [39:0] _f1_predicted_target_T_5 = _f1_predicted_target_T_4 ? _bpd_io_resp_f1_preds_3_predicted_pc_bits : _f1_predicted_target_T_3; // @[package.scala:39:{76,86}] wire [39:0] _f1_predicted_target_T_6 = ~s1_vpc; // @[frontend.scala:160:33, :379:29] wire [39:0] _f1_predicted_target_T_7 = {_f1_predicted_target_T_6[39:3], 3'h7}; // @[frontend.scala:160:{33,39}] wire [39:0] _f1_predicted_target_T_8 = ~_f1_predicted_target_T_7; // @[frontend.scala:160:{31,39}] wire [40:0] _f1_predicted_target_T_9 = {1'h0, _f1_predicted_target_T_8} + 41'h8; // @[frontend.scala:160:31, :167:23] wire [39:0] _f1_predicted_target_T_10 = _f1_predicted_target_T_9[39:0]; // @[frontend.scala:167:23] wire [39:0] f1_predicted_target = f1_do_redirect ? _f1_predicted_target_T_5 : _f1_predicted_target_T_10; // @[package.scala:39:76] wire _f1_predicted_ghist_T = _bpd_io_resp_f1_preds_0_is_br & _bpd_io_resp_f1_preds_0_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_1 = _bpd_io_resp_f1_preds_1_is_br & _bpd_io_resp_f1_preds_1_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_2 = _bpd_io_resp_f1_preds_2_is_br & _bpd_io_resp_f1_preds_2_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire _f1_predicted_ghist_T_3 = _bpd_io_resp_f1_preds_3_is_br & _bpd_io_resp_f1_preds_3_predicted_pc_valid; // @[frontend.scala:331:19, :418:40] wire [1:0] f1_predicted_ghist_lo = {_f1_predicted_ghist_T_1, _f1_predicted_ghist_T}; // @[package.scala:45:27] wire [1:0] f1_predicted_ghist_hi = {_f1_predicted_ghist_T_3, _f1_predicted_ghist_T_2}; // @[package.scala:45:27] wire [3:0] _f1_predicted_ghist_T_4 = {f1_predicted_ghist_hi, f1_predicted_ghist_lo}; // @[package.scala:45:27] wire [6:0] _f1_predicted_ghist_T_5 = {3'h0, f1_mask[3:0] & _f1_predicted_ghist_T_4}; // @[package.scala:45:27] wire [3:0] _GEN = {{_bpd_io_resp_f1_preds_3_taken}, {_bpd_io_resp_f1_preds_2_taken}, {_bpd_io_resp_f1_preds_1_taken}, {_bpd_io_resp_f1_preds_0_taken}}; // @[frontend.scala:331:19, :419:46] wire [3:0] _GEN_0 = {{_bpd_io_resp_f1_preds_3_is_br}, {_bpd_io_resp_f1_preds_2_is_br}, {_bpd_io_resp_f1_preds_1_is_br}, {_bpd_io_resp_f1_preds_0_is_br}}; // @[frontend.scala:331:19, :419:46] wire _f1_predicted_ghist_T_6 = _GEN[f1_redirect_idx] & f1_do_redirect; // @[Mux.scala:50:70] wire [3:0] f1_predicted_ghist_cfi_idx_oh = 4'h1 << f1_predicted_ghist_cfi_idx_fixed; // @[OneHot.scala:58:35] wire [3:0] _f1_predicted_ghist_not_taken_branches_T = f1_predicted_ghist_cfi_idx_oh; // @[OneHot.scala:58:35] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_9; // @[frontend.scala:123:31] wire [63:0] f1_predicted_ghist_old_history; // @[frontend.scala:87:27] wire [4:0] f1_predicted_ghist_ras_idx; // @[frontend.scala:87:27] wire [3:0] _f1_predicted_ghist_not_taken_branches_T_1 = {1'h0, f1_predicted_ghist_cfi_idx_oh[3:1]}; // @[OneHot.scala:58:35] wire [3:0] _f1_predicted_ghist_not_taken_branches_T_2 = {2'h0, f1_predicted_ghist_cfi_idx_oh[3:2]}; // @[OneHot.scala:58:35] wire [3:0] _f1_predicted_ghist_not_taken_branches_T_3 = {3'h0, f1_predicted_ghist_cfi_idx_oh[3]}; // @[OneHot.scala:58:35] wire [3:0] _f1_predicted_ghist_not_taken_branches_T_4 = _f1_predicted_ghist_not_taken_branches_T \| _f1_predicted_ghist_not_taken_branches_T_1; // @[util.scala:373:{29,45}] wire [3:0] _f1_predicted_ghist_not_taken_branches_T_5 = _f1_predicted_ghist_not_taken_branches_T_4 \| _f1_predicted_ghist_not_taken_branches_T_2; // @[util.scala:373:{29,45}] wire [3:0] _f1_predicted_ghist_not_taken_branches_T_6 = _f1_predicted_ghist_not_taken_branches_T_5 \| _f1_predicted_ghist_not_taken_branches_T_3; // @[util.scala:373:{29,45}] wire _GEN_1 = _GEN_0[f1_redirect_idx] & _f1_predicted_ghist_T_6; // @[Mux.scala:50:70] wire _f1_predicted_ghist_not_taken_branches_T_7; // @[frontend.scala:90:84] assign _f1_predicted_ghist_not_taken_branches_T_7 = _GEN_1; // @[frontend.scala:90:84] wire _f1_predicted_ghist_new_history_old_history_T; // @[frontend.scala:98:48] assign _f1_predicted_ghist_new_history_old_history_T = _GEN_1; // @[frontend.scala:90:84, :98:48] wire [3:0] _f1_predicted_ghist_not_taken_branches_T_8 = _f1_predicted_ghist_not_taken_branches_T_7 ? f1_predicted_ghist_cfi_idx_oh : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _f1_predicted_ghist_not_taken_branches_T_9 = ~_f1_predicted_ghist_not_taken_branches_T_8; // @[frontend.scala:90:{69,73}] wire [3:0] _f1_predicted_ghist_not_taken_branches_T_10 = _f1_predicted_ghist_not_taken_branches_T_6 & _f1_predicted_ghist_not_taken_branches_T_9; // @[util.scala:373:45] wire [3:0] _f1_predicted_ghist_not_taken_branches_T_12 = f1_do_redirect ? _f1_predicted_ghist_not_taken_branches_T_10 : 4'hF; // @[frontend.scala:89:44, :90:67, :411:50] wire [6:0] f1_predicted_ghist_not_taken_branches = {3'h0, _f1_predicted_ghist_T_5[3:0] & _f1_predicted_ghist_not_taken_branches_T_12}; // @[frontend.scala:89:{39,44}, :418:72] wire _f1_predicted_ghist_saw_not_taken_branch_T = \|f1_predicted_ghist_not_taken_branches; // @[frontend.scala:89:39, :97:53] wire f1_predicted_ghist_saw_not_taken_branch = _f1_predicted_ghist_saw_not_taken_branch_T \| s1_ghist_current_saw_branch_not_taken; // @[frontend.scala:97:{53,61}, :381:29] wire _f1_predicted_ghist_new_history_old_history_T_1 = _f1_predicted_ghist_new_history_old_history_T & f1_do_redirect; // @[frontend.scala:98:{48,61}, :411:50] wire [64:0] _GEN_2 = {s1_ghist_old_history, 1'h0}; // @[frontend.scala:98:91, :381:29] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_2; // @[frontend.scala:98:91] assign _f1_predicted_ghist_new_history_old_history_T_2 = _GEN_2; // @[frontend.scala:98:91] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_4; // @[frontend.scala:99:91] assign _f1_predicted_ghist_new_history_old_history_T_4 = _GEN_2; // @[frontend.scala:98:91, :99:91] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_3 = {_f1_predicted_ghist_new_history_old_history_T_2[64:1], 1'h1}; // @[frontend.scala:98:{91,96}] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_5 = f1_predicted_ghist_saw_not_taken_branch ? _f1_predicted_ghist_new_history_old_history_T_4 : {1'h0, s1_ghist_old_history}; // @[frontend.scala:97:61, :99:{37,91}, :381:29] wire [64:0] _f1_predicted_ghist_new_history_old_history_T_6 = _f1_predicted_ghist_new_history_old_history_T_1 ? _f1_predicted_ghist_new_history_old_history_T_3 : _f1_predicted_ghist_new_history_old_history_T_5; // @[frontend.scala:98:{37,61,96}, :99:37] assign f1_predicted_ghist_old_history = _f1_predicted_ghist_new_history_old_history_T_6[63:0]; // @[frontend.scala:87:27, :98:{31,37}] wire [5:0] _GEN_3 = {1'h0, s1_ghist_ras_idx}; // @[util.scala:203:14] wire [5:0] _f1_predicted_ghist_new_history_ras_idx_T_1 = _GEN_3 + 6'h1; // @[util.scala:203:14] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_2 = _f1_predicted_ghist_new_history_ras_idx_T_1[4:0]; // @[util.scala:203:14] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_3 = _f1_predicted_ghist_new_history_ras_idx_T_2; // @[util.scala:203:{14,20}] wire [5:0] _f1_predicted_ghist_new_history_ras_idx_T_5 = _GEN_3 - 6'h1; // @[util.scala:203:14, :220:14] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_6 = _f1_predicted_ghist_new_history_ras_idx_T_5[4:0]; // @[util.scala:220:14] wire [4:0] _f1_predicted_ghist_new_history_ras_idx_T_7 = _f1_predicted_ghist_new_history_ras_idx_T_6; // @[util.scala:220:{14,20}] assign _f1_predicted_ghist_new_history_ras_idx_T_9 = _f1_predicted_ghist_new_history_ras_idx_T_8; // @[frontend.scala:123:31, :124:31] assign f1_predicted_ghist_ras_idx = _f1_predicted_ghist_new_history_ras_idx_T_9; // @[frontend.scala:87:27, :123:31] wire _T_5 = s1_valid & ~s1_tlb_miss; // @[frontend.scala:380:29, :396:35, :427:{18,21}] wire _s0_valid_T = s1_tlb_resp_ae_inst \| s1_tlb_resp_pf_inst; // @[frontend.scala:397:24, :429:43] wire _s0_valid_T_1 = ~_s0_valid_T; // @[frontend.scala:429:{21,43}] wire _s2_valid_T = ~f1_clear; // @[frontend.scala:384:30, :386:58, :440:38] wire _s2_valid_T_1 = s1_valid & _s2_valid_T; // @[frontend.scala:380:29, :440:{35,38}] reg s2_valid; // @[frontend.scala:440:25] reg [39:0] s2_vpc; // @[frontend.scala:441:25] reg [63:0] s2_ghist_old_history; // @[frontend.scala:442:21] reg s2_ghist_current_saw_branch_not_taken; // @[frontend.scala:442:21] reg s2_ghist_new_saw_branch_not_taken; // @[frontend.scala:442:21] reg s2_ghist_new_saw_branch_taken; // @[frontend.scala:442:21] reg [4:0] s2_ghist_ras_idx; // @[frontend.scala:442:21] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_8 = s2_ghist_ras_idx; // @[frontend.scala:124:31, :442:21] reg [31:0] s2_ppc; // @[frontend.scala:444:24] assign s0_replay_ppc = s2_ppc; // @[frontend.scala:355:28, :444:24] reg [1:0] s2_tsrc; // @[frontend.scala:445:24] wire [1:0] s2_fsrc; // @[frontend.scala:446:25] wire f2_clear; // @[frontend.scala:447:26] reg s2_tlb_resp_miss; // @[frontend.scala:448:28] assign s0_replay_resp_miss = s2_tlb_resp_miss; // @[frontend.scala:353:28, :448:28] reg [31:0] s2_tlb_resp_paddr; // @[frontend.scala:448:28] assign s0_replay_resp_paddr = s2_tlb_resp_paddr; // @[frontend.scala:353:28, :448:28] reg [39:0] s2_tlb_resp_gpa; // @[frontend.scala:448:28] assign s0_replay_resp_gpa = s2_tlb_resp_gpa; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_gpa_is_pte; // @[frontend.scala:448:28] assign s0_replay_resp_gpa_is_pte = s2_tlb_resp_gpa_is_pte; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_pf_ld; // @[frontend.scala:448:28] assign s0_replay_resp_pf_ld = s2_tlb_resp_pf_ld; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_pf_st; // @[frontend.scala:448:28] assign s0_replay_resp_pf_st = s2_tlb_resp_pf_st; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_pf_inst; // @[frontend.scala:448:28] assign s0_replay_resp_pf_inst = s2_tlb_resp_pf_inst; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_gf_ld; // @[frontend.scala:448:28] assign s0_replay_resp_gf_ld = s2_tlb_resp_gf_ld; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_gf_st; // @[frontend.scala:448:28] assign s0_replay_resp_gf_st = s2_tlb_resp_gf_st; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_gf_inst; // @[frontend.scala:448:28] assign s0_replay_resp_gf_inst = s2_tlb_resp_gf_inst; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ae_ld; // @[frontend.scala:448:28] assign s0_replay_resp_ae_ld = s2_tlb_resp_ae_ld; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ae_st; // @[frontend.scala:448:28] assign s0_replay_resp_ae_st = s2_tlb_resp_ae_st; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ae_inst; // @[frontend.scala:448:28] assign s0_replay_resp_ae_inst = s2_tlb_resp_ae_inst; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ma_ld; // @[frontend.scala:448:28] assign s0_replay_resp_ma_ld = s2_tlb_resp_ma_ld; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ma_st; // @[frontend.scala:448:28] assign s0_replay_resp_ma_st = s2_tlb_resp_ma_st; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_ma_inst; // @[frontend.scala:448:28] assign s0_replay_resp_ma_inst = s2_tlb_resp_ma_inst; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_cacheable; // @[frontend.scala:448:28] assign s0_replay_resp_cacheable = s2_tlb_resp_cacheable; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_must_alloc; // @[frontend.scala:448:28] assign s0_replay_resp_must_alloc = s2_tlb_resp_must_alloc; // @[frontend.scala:353:28, :448:28] reg s2_tlb_resp_prefetchable; // @[frontend.scala:448:28] assign s0_replay_resp_prefetchable = s2_tlb_resp_prefetchable; // @[frontend.scala:353:28, :448:28] reg [1:0] s2_tlb_resp_size; // @[frontend.scala:448:28] assign s0_replay_resp_size = s2_tlb_resp_size; // @[frontend.scala:353:28, :448:28] reg [4:0] s2_tlb_resp_cmd; // @[frontend.scala:448:28] assign s0_replay_resp_cmd = s2_tlb_resp_cmd; // @[frontend.scala:353:28, :448:28] reg s2_tlb_miss; // @[frontend.scala:449:28] reg s2_is_replay_REG; // @[frontend.scala:450:29] wire s2_is_replay = s2_is_replay_REG & s2_valid; // @[frontend.scala:440:25, :450:{29,44}] wire _GEN_4 = s2_tlb_resp_ae_inst \| s2_tlb_resp_pf_inst; // @[frontend.scala:448:28, :451:50] wire _s2_xcpt_T; // @[frontend.scala:451:50] assign _s2_xcpt_T = _GEN_4; // @[frontend.scala:451:50] wire _s0_valid_T_7; // @[frontend.scala:499:46] assign _s0_valid_T_7 = _GEN_4; // @[frontend.scala:451:50, :499:46] wire _f3_io_enq_valid_T_2; // @[frontend.scala:529:52] assign _f3_io_enq_valid_T_2 = _GEN_4; // @[frontend.scala:451:50, :529:52] wire _s2_xcpt_T_1 = s2_valid & _s2_xcpt_T; // @[frontend.scala:440:25, :451:{26,50}] wire _s2_xcpt_T_2 = ~s2_is_replay; // @[frontend.scala:450:44, :451:77] wire s2_xcpt = _s2_xcpt_T_1 & _s2_xcpt_T_2; // @[frontend.scala:451:{26,74,77}] wire f3_ready; // @[frontend.scala:452:22] wire [1:0] f2_mask_idx = s2_vpc[2:1]; // @[package.scala:163:13] wire [1:0] f3_io_enq_bits_mask_idx = s2_vpc[2:1]; // @[package.scala:163:13] wire [6:0] f2_mask = 7'hF << f2_mask_idx; // @[package.scala:163:13] wire _f2_redirects_T = f2_mask[0]; // @[frontend.scala:177:31, :459:24] wire _f2_redirects_T_1 = s2_valid & _f2_redirects_T; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_2 = _f2_redirects_T_1 & _bpd_io_resp_f2_preds_0_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_3 = _bpd_io_resp_f2_preds_0_is_br & _bpd_io_resp_f2_preds_0_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_4 = _bpd_io_resp_f2_preds_0_is_jal \| _f2_redirects_T_3; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_0 = _f2_redirects_T_2 & _f2_redirects_T_4; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_5 = f2_mask[1]; // @[frontend.scala:177:31, :459:24] wire _f2_redirects_T_6 = s2_valid & _f2_redirects_T_5; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_7 = _f2_redirects_T_6 & _bpd_io_resp_f2_preds_1_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_8 = _bpd_io_resp_f2_preds_1_is_br & _bpd_io_resp_f2_preds_1_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_9 = _bpd_io_resp_f2_preds_1_is_jal \| _f2_redirects_T_8; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_1 = _f2_redirects_T_7 & _f2_redirects_T_9; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_10 = f2_mask[2]; // @[frontend.scala:177:31, :459:24] wire _f2_redirects_T_11 = s2_valid & _f2_redirects_T_10; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_12 = _f2_redirects_T_11 & _bpd_io_resp_f2_preds_2_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_13 = _bpd_io_resp_f2_preds_2_is_br & _bpd_io_resp_f2_preds_2_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_14 = _bpd_io_resp_f2_preds_2_is_jal \| _f2_redirects_T_13; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_2 = _f2_redirects_T_12 & _f2_redirects_T_14; // @[frontend.scala:459:{28,71}, :460:34] wire _f2_redirects_T_15 = f2_mask[3]; // @[frontend.scala:177:31, :459:24] wire _f2_redirects_T_16 = s2_valid & _f2_redirects_T_15; // @[frontend.scala:440:25, :459:{14,24}] wire _f2_redirects_T_17 = _f2_redirects_T_16 & _bpd_io_resp_f2_preds_3_predicted_pc_valid; // @[frontend.scala:331:19, :459:{14,28}] wire _f2_redirects_T_18 = _bpd_io_resp_f2_preds_3_is_br & _bpd_io_resp_f2_preds_3_taken; // @[frontend.scala:331:19, :461:35] wire _f2_redirects_T_19 = _bpd_io_resp_f2_preds_3_is_jal \| _f2_redirects_T_18; // @[frontend.scala:331:19, :460:34, :461:35] wire f2_redirects_3 = _f2_redirects_T_17 & _f2_redirects_T_19; // @[frontend.scala:459:{28,71}, :460:34] wire [1:0] _f2_redirect_idx_T = {1'h1, ~f2_redirects_2}; // @[Mux.scala:50:70] wire [1:0] _f2_redirect_idx_T_1 = f2_redirects_1 ? 2'h1 : _f2_redirect_idx_T; // @[Mux.scala:50:70] wire [1:0] f2_redirect_idx = f2_redirects_0 ? 2'h0 : _f2_redirect_idx_T_1; // @[Mux.scala:50:70] wire [1:0] f2_predicted_ghist_cfi_idx_fixed = f2_redirect_idx; // @[Mux.scala:50:70] wire _f2_do_redirect_T = f2_redirects_0 \| f2_redirects_1; // @[frontend.scala:459:71, :465:45] wire _f2_do_redirect_T_1 = _f2_do_redirect_T \| f2_redirects_2; // @[frontend.scala:459:71, :465:45] wire _f2_do_redirect_T_2 = _f2_do_redirect_T_1 \| f2_redirects_3; // @[frontend.scala:459:71, :465:45] wire f2_do_redirect = _f2_do_redirect_T_2; // @[frontend.scala:465:{45,50}] wire _f2_predicted_target_T = f2_redirect_idx == 2'h1; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_1 = _f2_predicted_target_T ? _bpd_io_resp_f2_preds_1_predicted_pc_bits : _bpd_io_resp_f2_preds_0_predicted_pc_bits; // @[package.scala:39:{76,86}] wire _f2_predicted_target_T_2 = f2_redirect_idx == 2'h2; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_3 = _f2_predicted_target_T_2 ? _bpd_io_resp_f2_preds_2_predicted_pc_bits : _f2_predicted_target_T_1; // @[package.scala:39:{76,86}] wire _f2_predicted_target_T_4 = &f2_redirect_idx; // @[Mux.scala:50:70] wire [39:0] _f2_predicted_target_T_5 = _f2_predicted_target_T_4 ? _bpd_io_resp_f2_preds_3_predicted_pc_bits : _f2_predicted_target_T_3; // @[package.scala:39:{76,86}] wire [39:0] _f2_predicted_target_T_6 = ~s2_vpc; // @[frontend.scala:160:33, :441:25] wire [39:0] _f2_predicted_target_T_7 = {_f2_predicted_target_T_6[39:3], 3'h7}; // @[frontend.scala:160:{33,39}] wire [39:0] _f2_predicted_target_T_8 = ~_f2_predicted_target_T_7; // @[frontend.scala:160:{31,39}] wire [40:0] _f2_predicted_target_T_9 = {1'h0, _f2_predicted_target_T_8} + 41'h8; // @[frontend.scala:160:31, :167:23] wire [39:0] _f2_predicted_target_T_10 = _f2_predicted_target_T_9[39:0]; // @[frontend.scala:167:23] wire [39:0] f2_predicted_target = f2_do_redirect ? _f2_predicted_target_T_5 : _f2_predicted_target_T_10; // @[package.scala:39:76] wire _f2_predicted_ghist_T = _bpd_io_resp_f2_preds_0_is_br & _bpd_io_resp_f2_preds_0_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_1 = _bpd_io_resp_f2_preds_1_is_br & _bpd_io_resp_f2_preds_1_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_2 = _bpd_io_resp_f2_preds_2_is_br & _bpd_io_resp_f2_preds_2_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire _f2_predicted_ghist_T_3 = _bpd_io_resp_f2_preds_3_is_br & _bpd_io_resp_f2_preds_3_predicted_pc_valid; // @[frontend.scala:331:19, :470:40] wire [1:0] f2_predicted_ghist_lo = {_f2_predicted_ghist_T_1, _f2_predicted_ghist_T}; // @[package.scala:45:27] wire [1:0] f2_predicted_ghist_hi = {_f2_predicted_ghist_T_3, _f2_predicted_ghist_T_2}; // @[package.scala:45:27] wire [3:0] _f2_predicted_ghist_T_4 = {f2_predicted_ghist_hi, f2_predicted_ghist_lo}; // @[package.scala:45:27] wire [6:0] _f2_predicted_ghist_T_5 = {3'h0, f2_mask[3:0] & _f2_predicted_ghist_T_4}; // @[package.scala:45:27] wire [3:0] _GEN_5 = {{_bpd_io_resp_f2_preds_3_taken}, {_bpd_io_resp_f2_preds_2_taken}, {_bpd_io_resp_f2_preds_1_taken}, {_bpd_io_resp_f2_preds_0_taken}}; // @[frontend.scala:331:19, :471:46] wire [3:0] _GEN_6 = {{_bpd_io_resp_f2_preds_3_is_br}, {_bpd_io_resp_f2_preds_2_is_br}, {_bpd_io_resp_f2_preds_1_is_br}, {_bpd_io_resp_f2_preds_0_is_br}}; // @[frontend.scala:331:19, :471:46] wire _f2_predicted_ghist_T_6 = _GEN_5[f2_redirect_idx] & f2_do_redirect; // @[Mux.scala:50:70] wire [3:0] f2_predicted_ghist_cfi_idx_oh = 4'h1 << f2_predicted_ghist_cfi_idx_fixed; // @[OneHot.scala:58:35] wire [3:0] _f2_predicted_ghist_not_taken_branches_T = f2_predicted_ghist_cfi_idx_oh; // @[OneHot.scala:58:35] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_9; // @[frontend.scala:123:31] wire [63:0] f2_predicted_ghist_old_history; // @[frontend.scala:87:27] wire [4:0] f2_predicted_ghist_ras_idx; // @[frontend.scala:87:27] wire [3:0] _f2_predicted_ghist_not_taken_branches_T_1 = {1'h0, f2_predicted_ghist_cfi_idx_oh[3:1]}; // @[OneHot.scala:58:35] wire [3:0] _f2_predicted_ghist_not_taken_branches_T_2 = {2'h0, f2_predicted_ghist_cfi_idx_oh[3:2]}; // @[OneHot.scala:58:35] wire [3:0] _f2_predicted_ghist_not_taken_branches_T_3 = {3'h0, f2_predicted_ghist_cfi_idx_oh[3]}; // @[OneHot.scala:58:35] wire [3:0] _f2_predicted_ghist_not_taken_branches_T_4 = _f2_predicted_ghist_not_taken_branches_T \| _f2_predicted_ghist_not_taken_branches_T_1; // @[util.scala:373:{29,45}] wire [3:0] _f2_predicted_ghist_not_taken_branches_T_5 = _f2_predicted_ghist_not_taken_branches_T_4 \| _f2_predicted_ghist_not_taken_branches_T_2; // @[util.scala:373:{29,45}] wire [3:0] _f2_predicted_ghist_not_taken_branches_T_6 = _f2_predicted_ghist_not_taken_branches_T_5 \| _f2_predicted_ghist_not_taken_branches_T_3; // @[util.scala:373:{29,45}] wire _GEN_7 = _GEN_6[f2_redirect_idx] & _f2_predicted_ghist_T_6; // @[Mux.scala:50:70] wire _f2_predicted_ghist_not_taken_branches_T_7; // @[frontend.scala:90:84] assign _f2_predicted_ghist_not_taken_branches_T_7 = _GEN_7; // @[frontend.scala:90:84] wire _f2_predicted_ghist_new_history_old_history_T; // @[frontend.scala:98:48] assign _f2_predicted_ghist_new_history_old_history_T = _GEN_7; // @[frontend.scala:90:84, :98:48] wire [3:0] _f2_predicted_ghist_not_taken_branches_T_8 = _f2_predicted_ghist_not_taken_branches_T_7 ? f2_predicted_ghist_cfi_idx_oh : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _f2_predicted_ghist_not_taken_branches_T_9 = ~_f2_predicted_ghist_not_taken_branches_T_8; // @[frontend.scala:90:{69,73}] wire [3:0] _f2_predicted_ghist_not_taken_branches_T_10 = _f2_predicted_ghist_not_taken_branches_T_6 & _f2_predicted_ghist_not_taken_branches_T_9; // @[util.scala:373:45] wire [3:0] _f2_predicted_ghist_not_taken_branches_T_12 = f2_do_redirect ? _f2_predicted_ghist_not_taken_branches_T_10 : 4'hF; // @[frontend.scala:89:44, :90:67, :465:50] wire [6:0] f2_predicted_ghist_not_taken_branches = {3'h0, _f2_predicted_ghist_T_5[3:0] & _f2_predicted_ghist_not_taken_branches_T_12}; // @[frontend.scala:89:{39,44}, :470:72] wire _f2_predicted_ghist_saw_not_taken_branch_T = \|f2_predicted_ghist_not_taken_branches; // @[frontend.scala:89:39, :97:53] wire f2_predicted_ghist_saw_not_taken_branch = _f2_predicted_ghist_saw_not_taken_branch_T \| s2_ghist_current_saw_branch_not_taken; // @[frontend.scala:97:{53,61}, :442:21] wire _f2_predicted_ghist_new_history_old_history_T_1 = _f2_predicted_ghist_new_history_old_history_T & f2_do_redirect; // @[frontend.scala:98:{48,61}, :465:50] wire [64:0] _GEN_8 = {s2_ghist_old_history, 1'h0}; // @[frontend.scala:98:91, :442:21] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_2; // @[frontend.scala:98:91] assign _f2_predicted_ghist_new_history_old_history_T_2 = _GEN_8; // @[frontend.scala:98:91] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_4; // @[frontend.scala:99:91] assign _f2_predicted_ghist_new_history_old_history_T_4 = _GEN_8; // @[frontend.scala:98:91, :99:91] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_3 = {_f2_predicted_ghist_new_history_old_history_T_2[64:1], 1'h1}; // @[frontend.scala:98:{91,96}] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_5 = f2_predicted_ghist_saw_not_taken_branch ? _f2_predicted_ghist_new_history_old_history_T_4 : {1'h0, s2_ghist_old_history}; // @[frontend.scala:97:61, :99:{37,91}, :442:21] wire [64:0] _f2_predicted_ghist_new_history_old_history_T_6 = _f2_predicted_ghist_new_history_old_history_T_1 ? _f2_predicted_ghist_new_history_old_history_T_3 : _f2_predicted_ghist_new_history_old_history_T_5; // @[frontend.scala:98:{37,61,96}, :99:37] assign f2_predicted_ghist_old_history = _f2_predicted_ghist_new_history_old_history_T_6[63:0]; // @[frontend.scala:87:27, :98:{31,37}] wire [5:0] _GEN_9 = {1'h0, s2_ghist_ras_idx}; // @[util.scala:203:14] wire [5:0] _f2_predicted_ghist_new_history_ras_idx_T_1 = _GEN_9 + 6'h1; // @[util.scala:203:14] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_2 = _f2_predicted_ghist_new_history_ras_idx_T_1[4:0]; // @[util.scala:203:14] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_3 = _f2_predicted_ghist_new_history_ras_idx_T_2; // @[util.scala:203:{14,20}] wire [5:0] _f2_predicted_ghist_new_history_ras_idx_T_5 = _GEN_9 - 6'h1; // @[util.scala:203:14, :220:14] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_6 = _f2_predicted_ghist_new_history_ras_idx_T_5[4:0]; // @[util.scala:220:14] wire [4:0] _f2_predicted_ghist_new_history_ras_idx_T_7 = _f2_predicted_ghist_new_history_ras_idx_T_6; // @[util.scala:220:{14,20}] assign _f2_predicted_ghist_new_history_ras_idx_T_9 = _f2_predicted_ghist_new_history_ras_idx_T_8; // @[frontend.scala:123:31, :124:31] assign f2_predicted_ghist_ras_idx = _f2_predicted_ghist_new_history_ras_idx_T_9; // @[frontend.scala:87:27, :123:31] wire _f2_correct_f1_ghist_T = s1_ghist_old_history == f2_predicted_ghist_old_history; // @[frontend.scala:75:19, :87:27, :381:29] wire _f2_correct_f1_ghist_T_1 = ~s1_ghist_new_saw_branch_not_taken; // @[frontend.scala:76:32, :381:29] wire _f2_correct_f1_ghist_T_2 = _f2_correct_f1_ghist_T & _f2_correct_f1_ghist_T_1; // @[frontend.scala:75:{19,42}, :76:32] wire _f2_correct_f1_ghist_T_3 = ~s1_ghist_new_saw_branch_taken; // @[frontend.scala:77:28, :381:29] wire _f2_correct_f1_ghist_T_4 = _f2_correct_f1_ghist_T_2 & _f2_correct_f1_ghist_T_3; // @[frontend.scala:75:42, :76:68, :77:28] wire _f2_correct_f1_ghist_T_5 = ~_f2_correct_f1_ghist_T_4; // @[frontend.scala:76:68, :80:41] wire f2_correct_f1_ghist = _f2_correct_f1_ghist_T_5; // @[frontend.scala:80:41, :479:61] wire _s0_is_replay_T = s2_valid & _icache_io_resp_valid; // @[frontend.scala:299:26, :440:25, :482:19, :485:30] wire _T_11 = s2_valid & ~_icache_io_resp_valid \| _s0_is_replay_T & ~f3_ready; // @[frontend.scala:299:26, :440:25, :452:22, :481:{19,22,45}, :482:{43,46}, :485:30] wire _s0_valid_T_2 = ~s2_tlb_resp_ae_inst; // @[frontend.scala:448:28, :483:18] wire _s0_valid_T_3 = ~s2_tlb_resp_pf_inst; // @[frontend.scala:448:28, :483:42] wire _s0_valid_T_4 = _s0_valid_T_2 & _s0_valid_T_3; // @[frontend.scala:483:{18,39,42}] wire _s0_valid_T_5 = _s0_valid_T_4 \| s2_is_replay; // @[frontend.scala:450:44, :483:{39,64}] wire _s0_valid_T_6 = _s0_valid_T_5 \| s2_tlb_miss; // @[frontend.scala:449:28, :483:{64,80}] wire _s0_s1_use_f3_bpd_resp_T = ~s2_is_replay; // @[frontend.scala:450:44, :451:77, :487:30] assign s0_s1_use_f3_bpd_resp = _T_11 & _s0_s1_use_f3_bpd_resp_T; // @[frontend.scala:356:39, :481:45, :482:58, :487:{27,30}] wire _T_12 = s2_valid & f3_ready; // @[frontend.scala:440:25, :452:22, :491:25] wire _T_21 = s1_valid & (s1_vpc != f2_predicted_target \| f2_correct_f1_ghist) \| ~s1_valid; // @[frontend.scala:379:29, :380:29, :466:32, :479:61, :496:{21,32,56,81,84}] wire _GEN_10 = _T_12 & _T_21; // @[frontend.scala:384:30, :491:{25,38}, :496:{81,95}] wire _s0_valid_T_8 = ~s2_is_replay; // @[frontend.scala:450:44, :451:77, :499:73] wire _s0_valid_T_9 = _s0_valid_T_7 & _s0_valid_T_8; // @[frontend.scala:499:{46,70,73}] wire _s0_valid_T_10 = ~_s0_valid_T_9; // @[frontend.scala:499:{23,70}] wire _GEN_11 = _T_12 & _T_21; // @[frontend.scala:427:35, :491:{25,38}, :496:{81,95}, :499:20] assign s2_fsrc = _T_11 ? 2'h0 : {1'h0, _GEN_11}; // @[frontend.scala:427:35, :446:25, :481:45, :482:58, :491:38, :496:95, :499:20, :503:20] wire f3_clear; // @[frontend.scala:514:26] wire f4_ready; // @[frontend.scala:526:22] wire _f3_io_enq_valid_T = ~f2_clear; // @[frontend.scala:447:26, :528:37] wire _f3_io_enq_valid_T_1 = s2_valid & _f3_io_enq_valid_T; // @[frontend.scala:440:25, :528:{34,37}] wire _f3_io_enq_valid_T_3 = ~s2_tlb_miss; // @[frontend.scala:449:28, :529:79] wire _f3_io_enq_valid_T_4 = _f3_io_enq_valid_T_2 & _f3_io_enq_valid_T_3; // @[frontend.scala:529:{52,76,79}] wire _f3_io_enq_valid_T_5 = _icache_io_resp_valid \| _f3_io_enq_valid_T_4; // @[frontend.scala:299:26, :529:{27,76}] wire _f3_io_enq_valid_T_6 = _f3_io_enq_valid_T_1 & _f3_io_enq_valid_T_5; // @[frontend.scala:528:{34,47}, :529:27] wire [63:0] _f3_io_enq_bits_data_T = s2_xcpt ? 64'h0 : _icache_io_resp_bits_data; // @[frontend.scala:299:26, :451:74, :532:30] wire [6:0] _f3_io_enq_bits_mask_T = 7'hF << f3_io_enq_bits_mask_idx; // @[package.scala:163:13] reg [4:0] ras_read_idx; // @[frontend.scala:540:29] wire _T_26 = _f3_io_enq_ready & _f3_io_enq_valid_T_6; // @[Decoupled.scala:51:35] reg f3_bpd_resp_io_enq_valid_REG; // @[frontend.scala:549:57] wire _f3_bpd_resp_io_enq_valid_T = _f3_io_deq_valid & f3_bpd_resp_io_enq_valid_REG; // @[frontend.scala:516:11, :549:{47,57}] wire [1:0] f3_bank_mask_idx = _f3_io_deq_bits_pc[2:1]; // @[package.scala:163:13] wire [39:0] _f3_aligned_pc_T = ~_f3_io_deq_bits_pc; // @[frontend.scala:160:33, :516:11] wire [39:0] _f3_aligned_pc_T_1 = {_f3_aligned_pc_T[39:3], 3'h7}; // @[frontend.scala:160:{33,39}] wire [39:0] f3_aligned_pc = ~_f3_aligned_pc_T_1; // @[frontend.scala:160:{31,39}] wire [2:0] _f3_is_last_bank_in_block_T = f3_aligned_pc[5:3]; // @[frontend.scala:152:28, :160:31] wire _f3_is_last_bank_in_block_T_1 = &_f3_is_last_bank_in_block_T; // @[frontend.scala:152:{28,66}] wire _f3_is_rvc_0_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_1_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_2_T_1; // @[frontend.scala:592:38] wire _f3_is_rvc_3_T_1; // @[frontend.scala:592:38] wire f3_is_rvc_0; // @[frontend.scala:564:29] wire f3_is_rvc_1; // @[frontend.scala:564:29] wire f3_is_rvc_2; // @[frontend.scala:564:29] wire f3_is_rvc_3; // @[frontend.scala:564:29] wire _f3_redirects_0_T_7; // @[frontend.scala:731:40] wire _f3_redirects_1_T_7; // @[frontend.scala:731:40] wire _f3_redirects_2_T_7; // @[frontend.scala:731:40] wire _f3_redirects_3_T_7; // @[frontend.scala:731:40] wire f3_redirects_0; // @[frontend.scala:565:29] wire f3_redirects_1; // @[frontend.scala:565:29] wire f3_redirects_2; // @[frontend.scala:565:29] wire f3_redirects_3; // @[frontend.scala:565:29] wire [39:0] _f3_targs_0_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_1_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_2_T_1; // @[frontend.scala:691:26] wire [39:0] _f3_targs_3_T_1; // @[frontend.scala:691:26] wire [39:0] f3_targs_0; // @[frontend.scala:566:29] wire [39:0] f3_targs_1; // @[frontend.scala:566:29] wire [39:0] f3_targs_2; // @[frontend.scala:566:29] wire [39:0] f3_targs_3; // @[frontend.scala:566:29] wire [2:0] brsigs_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_1_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_2_cfi_type; // @[frontend.scala:613:24] wire [2:0] brsigs_3_cfi_type; // @[frontend.scala:613:24] wire [2:0] f3_cfi_types_0; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_1; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_2; // @[frontend.scala:567:29] wire [2:0] f3_cfi_types_3; // @[frontend.scala:567:29] wire [39:0] f3_predicted_target; // @[frontend.scala:784:32] wire [31:0] inst; // @[frontend.scala:660:24] wire [31:0] inst_1; // @[frontend.scala:660:24] wire [31:0] inst_2; // @[frontend.scala:660:24] wire [31:0] exp_inst; // @[consts.scala:332:8] wire [31:0] exp_inst_1; // @[consts.scala:332:8] wire [31:0] exp_inst_2; // @[consts.scala:332:8] wire _f3_fetch_bundle_sfbs_0_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_1_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_2_T_3; // @[frontend.scala:719:33] wire _f3_fetch_bundle_sfbs_3_T_3; // @[frontend.scala:719:33] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_40; // @[frontend.scala:722:68] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_40; // @[frontend.scala:722:68] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_40; // @[frontend.scala:722:68] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_40; // @[frontend.scala:722:68] wire _f3_fetch_bundle_shadowable_mask_0_T_7; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_1_T_7; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_2_T_7; // @[frontend.scala:724:62] wire _f3_fetch_bundle_shadowable_mask_3_T_7; // @[frontend.scala:724:62] wire _f3_fetch_bundle_cfi_idx_valid_T_2; // @[frontend.scala:777:57] wire [1:0] _f3_fetch_bundle_cfi_idx_bits_T_2; // @[Mux.scala:50:70] wire [1:0] f3_predicted_ghist_cfi_idx_fixed = f3_fetch_bundle_cfi_idx_bits; // @[frontend.scala:85:32, :569:29] wire _f3_predicted_target_T_3 = f3_fetch_bundle_cfi_is_ret; // @[frontend.scala:569:29, :785:36] wire [3:0] _f3_fetch_bundle_mask_T; // @[frontend.scala:576:35] wire [3:0] _f3_fetch_bundle_br_mask_T; // @[frontend.scala:577:41] wire f3_fetch_bundle_edge_inst_0; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_0; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_1; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_2; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_insts_3; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_0; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_1; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_2; // @[frontend.scala:569:29] wire [31:0] f3_fetch_bundle_exp_insts_3; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_0; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_1; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_2; // @[frontend.scala:569:29] wire f3_fetch_bundle_sfbs_3; // @[frontend.scala:569:29] wire [7:0] f3_fetch_bundle_sfb_masks_0; // @[frontend.scala:569:29] wire [7:0] f3_fetch_bundle_sfb_masks_1; // @[frontend.scala:569:29] wire [7:0] f3_fetch_bundle_sfb_masks_2; // @[frontend.scala:569:29] wire [7:0] f3_fetch_bundle_sfb_masks_3; // @[frontend.scala:569:29] wire [3:0] f3_fetch_bundle_sfb_dests_0; // @[frontend.scala:569:29] wire [3:0] f3_fetch_bundle_sfb_dests_1; // @[frontend.scala:569:29] wire [3:0] f3_fetch_bundle_sfb_dests_2; // @[frontend.scala:569:29] wire [3:0] f3_fetch_bundle_sfb_dests_3; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_0; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_1; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_2; // @[frontend.scala:569:29] wire f3_fetch_bundle_shadowable_mask_3; // @[frontend.scala:569:29] wire f3_fetch_bundle_cfi_idx_valid; // @[frontend.scala:569:29] wire [63:0] f3_fetch_bundle_ghist_old_history; // @[frontend.scala:569:29] wire f3_fetch_bundle_ghist_current_saw_branch_not_taken; // @[frontend.scala:569:29] wire f3_fetch_bundle_ghist_new_saw_branch_not_taken; // @[frontend.scala:569:29] wire f3_fetch_bundle_ghist_new_saw_branch_taken; // @[frontend.scala:569:29] wire [4:0] f3_fetch_bundle_ghist_ras_idx; // @[frontend.scala:569:29] wire f3_fetch_bundle_lhist_0; // @[frontend.scala:569:29] wire f3_fetch_bundle_end_half_valid; // @[frontend.scala:569:29] wire [15:0] f3_fetch_bundle_end_half_bits; // @[frontend.scala:569:29] wire [119:0] f3_fetch_bundle_bpd_meta_0; // @[frontend.scala:569:29] wire [39:0] f3_fetch_bundle_pc; // @[frontend.scala:569:29] wire [39:0] f3_fetch_bundle_next_pc; // @[frontend.scala:569:29] wire [2:0] f3_fetch_bundle_cfi_type; // @[frontend.scala:569:29] wire f3_fetch_bundle_cfi_is_call; // @[frontend.scala:569:29] wire f3_fetch_bundle_cfi_npc_plus4; // @[frontend.scala:569:29] wire [39:0] f3_fetch_bundle_ras_top; // @[frontend.scala:569:29] wire [3:0] f3_fetch_bundle_mask; // @[frontend.scala:569:29] wire [3:0] f3_fetch_bundle_br_mask; // @[frontend.scala:569:29] wire f3_fetch_bundle_xcpt_pf_if; // @[frontend.scala:569:29] wire f3_fetch_bundle_xcpt_ae_if; // @[frontend.scala:569:29] wire [1:0] f3_fetch_bundle_fsrc; // @[frontend.scala:569:29] wire [1:0] f3_fetch_bundle_tsrc; // @[frontend.scala:569:29] wire _f3_mask_0_T_4; // @[frontend.scala:690:71] wire _f3_mask_1_T_4; // @[frontend.scala:690:71] wire _f3_mask_2_T_4; // @[frontend.scala:690:71] wire _f3_mask_3_T_4; // @[frontend.scala:690:71] wire f3_mask_0; // @[frontend.scala:570:29] wire f3_mask_1; // @[frontend.scala:570:29] wire f3_mask_2; // @[frontend.scala:570:29] wire f3_mask_3; // @[frontend.scala:570:29] wire _f3_br_mask_0_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_1_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_2_T_1; // @[frontend.scala:736:37] wire _f3_br_mask_3_T_1; // @[frontend.scala:736:37] wire f3_br_mask_0; // @[frontend.scala:571:29] wire f3_br_mask_1; // @[frontend.scala:571:29] wire f3_br_mask_2; // @[frontend.scala:571:29] wire f3_br_mask_3; // @[frontend.scala:571:29] wire brsigs_is_call; // @[frontend.scala:613:24] wire brsigs_1_is_call; // @[frontend.scala:613:24] wire brsigs_2_is_call; // @[frontend.scala:613:24] wire brsigs_3_is_call; // @[frontend.scala:613:24] wire f3_call_mask_0; // @[frontend.scala:572:29] wire f3_call_mask_1; // @[frontend.scala:572:29] wire f3_call_mask_2; // @[frontend.scala:572:29] wire f3_call_mask_3; // @[frontend.scala:572:29] wire brsigs_is_ret; // @[frontend.scala:613:24] wire brsigs_1_is_ret; // @[frontend.scala:613:24] wire brsigs_2_is_ret; // @[frontend.scala:613:24] wire brsigs_3_is_ret; // @[frontend.scala:613:24] wire f3_ret_mask_0; // @[frontend.scala:573:29] wire f3_ret_mask_1; // @[frontend.scala:573:29] wire f3_ret_mask_2; // @[frontend.scala:573:29] wire f3_ret_mask_3; // @[frontend.scala:573:29] wire _f3_npc_plus4_mask_0_T_2; // @[frontend.scala:703:23] wire _f3_npc_plus4_mask_1_T; // @[frontend.scala:705:9] wire _f3_npc_plus4_mask_2_T; // @[frontend.scala:705:9] wire _f3_npc_plus4_mask_3_T; // @[frontend.scala:705:9] wire f3_npc_plus4_mask_0; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_1; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_2; // @[frontend.scala:574:31] wire f3_npc_plus4_mask_3; // @[frontend.scala:574:31] wire _f3_btb_mispredicts_0_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_1_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_2_T_4; // @[frontend.scala:697:61] wire _f3_btb_mispredicts_3_T_4; // @[frontend.scala:697:61] wire f3_btb_mispredicts_0; // @[frontend.scala:575:32] wire f3_btb_mispredicts_1; // @[frontend.scala:575:32] wire f3_btb_mispredicts_2; // @[frontend.scala:575:32] wire f3_btb_mispredicts_3; // @[frontend.scala:575:32] wire [1:0] f3_fetch_bundle_mask_lo = {f3_mask_1, f3_mask_0}; // @[frontend.scala:570:29, :576:35] wire [1:0] f3_fetch_bundle_mask_hi = {f3_mask_3, f3_mask_2}; // @[frontend.scala:570:29, :576:35] assign _f3_fetch_bundle_mask_T = {f3_fetch_bundle_mask_hi, f3_fetch_bundle_mask_lo}; // @[frontend.scala:576:35] assign f3_fetch_bundle_mask = _f3_fetch_bundle_mask_T; // @[frontend.scala:569:29, :576:35] wire [1:0] f3_fetch_bundle_br_mask_lo = {f3_br_mask_1, f3_br_mask_0}; // @[frontend.scala:571:29, :577:41] wire [1:0] f3_fetch_bundle_br_mask_hi = {f3_br_mask_3, f3_br_mask_2}; // @[frontend.scala:571:29, :577:41] assign _f3_fetch_bundle_br_mask_T = {f3_fetch_bundle_br_mask_hi, f3_fetch_bundle_br_mask_lo}; // @[frontend.scala:577:41] assign f3_fetch_bundle_br_mask = _f3_fetch_bundle_br_mask_T; // @[frontend.scala:569:29, :577:41] reg [15:0] f3_prev_half; // @[frontend.scala:587:28] reg f3_prev_is_half; // @[frontend.scala:589:32] assign f3_fetch_bundle_edge_inst_0 = f3_prev_is_half; // @[frontend.scala:569:29, :589:32] wire _offset_from_aligned_pc_T_2 = f3_prev_is_half; // @[frontend.scala:589:32, :710:31] wire [63:0] bank_data; // @[frontend.scala:598:29] wire _bank_mask_0_T_4; // @[frontend.scala:689:71] wire _bank_mask_1_T_4; // @[frontend.scala:689:71] wire _bank_mask_2_T_4; // @[frontend.scala:689:71] wire _bank_mask_3_T_4; // @[frontend.scala:689:71] wire bank_mask_0; // @[frontend.scala:599:26] wire bank_mask_1; // @[frontend.scala:599:26] wire bank_mask_2; // @[frontend.scala:599:26] wire bank_mask_3; // @[frontend.scala:599:26] wire [31:0] bank_insts_0; // @[frontend.scala:600:26] wire [31:0] bank_insts_1; // @[frontend.scala:600:26] wire [31:0] bank_insts_2; // @[frontend.scala:600:26] wire [31:0] bank_insts_3; // @[frontend.scala:600:26] assign f3_ret_mask_0 = brsigs_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_0 = brsigs_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_0 = brsigs_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_target; // @[frontend.scala:613:24] wire brsigs_shadowable; // @[frontend.scala:613:24] wire [15:0] _inst0_T = bank_data[15:0]; // @[frontend.scala:598:29, :615:34] wire [31:0] inst0 = {_inst0_T, f3_prev_half}; // @[frontend.scala:587:28, :615:{24,34}] wire [31:0] inst1 = bank_data[31:0]; // @[frontend.scala:598:29, :616:30] wire [31:0] exp_inst0 = _exp_inst0_rvc_exp_io_rvc ? _exp_inst0_rvc_exp_io_out_bits : inst0; // @[frontend.scala:615:24] wire [31:0] exp_inst1 = _exp_inst1_rvc_exp_io_rvc ? _exp_inst1_rvc_exp_io_out_bits : inst1; // @[frontend.scala:616:30] wire [40:0] _GEN_12 = {1'h0, f3_aligned_pc}; // @[frontend.scala:160:31, :619:34] wire [40:0] _pc0_T; // @[frontend.scala:619:34] assign _pc0_T = _GEN_12; // @[frontend.scala:619:34] wire [40:0] _pc1_T; // @[frontend.scala:620:34] assign _pc1_T = _GEN_12; // @[frontend.scala:619:34, :620:34] wire [39:0] _pc0_T_1 = _pc0_T[39:0]; // @[frontend.scala:619:34] wire [40:0] _pc0_T_2 = {1'h0, _pc0_T_1} - 41'h2; // @[frontend.scala:619:{34,69}] wire [39:0] pc0 = _pc0_T_2[39:0]; // @[frontend.scala:619:69] wire [39:0] pc1 = _pc1_T[39:0]; // @[frontend.scala:620:34] wire [31:0] _GEN_13 = f3_prev_is_half ? inst0 : inst1; // @[frontend.scala:589:32, :615:24, :616:30, :629:34, :630:40, :651:40] assign f3_fetch_bundle_insts_0 = _GEN_13; // @[frontend.scala:569:29, :629:34, :630:40, :651:40] assign bank_insts_0 = _GEN_13; // @[frontend.scala:600:26, :629:34, :630:40, :651:40] assign f3_fetch_bundle_exp_insts_0 = f3_prev_is_half ? exp_inst0 : exp_inst1; // @[frontend.scala:569:29, :589:32, :629:34, :632:40, :653:40] assign brsigs_shadowable = f3_prev_is_half ? _bpd_decoder0_io_out_shadowable : _bpd_decoder1_io_out_shadowable; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_sfb_offset_valid = f3_prev_is_half ? _bpd_decoder0_io_out_sfb_offset_valid : _bpd_decoder1_io_out_sfb_offset_valid; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_sfb_offset_bits = f3_prev_is_half ? _bpd_decoder0_io_out_sfb_offset_bits : _bpd_decoder1_io_out_sfb_offset_bits; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_cfi_type = f3_prev_is_half ? _bpd_decoder0_io_out_cfi_type : _bpd_decoder1_io_out_cfi_type; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_target = f3_prev_is_half ? _bpd_decoder0_io_out_target : _bpd_decoder1_io_out_target; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_is_call = f3_prev_is_half ? _bpd_decoder0_io_out_is_call : _bpd_decoder1_io_out_is_call; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] assign brsigs_is_ret = f3_prev_is_half ? _bpd_decoder0_io_out_is_ret : _bpd_decoder1_io_out_is_ret; // @[frontend.scala:589:32, :613:24, :622:34, :625:34, :629:34, :634:40, :655:40] wire [1:0] _f3_is_rvc_0_T = bank_insts_0[1:0]; // @[frontend.scala:592:32, :600:26] wire [1:0] _valid_T = bank_insts_0[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_0_T_1 = _f3_is_rvc_0_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_0 = _f3_is_rvc_0_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_0_T = _f3_io_deq_bits_mask[0]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_0_T = _f3_io_deq_bits_mask[0]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_0_T_1 = _f3_io_deq_valid & _bank_mask_0_T; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_0_T_2 = _bank_mask_0_T_1; // @[frontend.scala:689:{39,62}] assign _bank_mask_0_T_4 = _bank_mask_0_T_2; // @[frontend.scala:689:{62,71}] assign bank_mask_0 = _bank_mask_0_T_4; // @[frontend.scala:599:26, :689:71] wire _f3_mask_0_T_1 = _f3_io_deq_valid & _f3_mask_0_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_0_T_2 = _f3_mask_0_T_1; // @[frontend.scala:690:{39,62}] assign _f3_mask_0_T_4 = _f3_mask_0_T_2; // @[frontend.scala:690:{62,71}] assign f3_mask_0 = _f3_mask_0_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_14 = brsigs_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_0_T; // @[frontend.scala:691:43] assign _f3_targs_0_T = _GEN_14; // @[frontend.scala:691:43] wire _f3_redirects_0_T_1; // @[frontend.scala:732:56] assign _f3_redirects_0_T_1 = _GEN_14; // @[frontend.scala:691:43, :732:56] assign _f3_targs_0_T_1 = _f3_targs_0_T ? _f3_bpd_resp_io_deq_bits_preds_0_predicted_pc_bits : brsigs_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_0 = _f3_targs_0_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_15 = brsigs_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_0_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_0_T = _GEN_15; // @[frontend.scala:696:49] wire _f3_redirects_0_T; // @[frontend.scala:732:25] assign _f3_redirects_0_T = _GEN_15; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_0_T_1 = _f3_btb_mispredicts_0_T; // @[frontend.scala:696:{49,61}] wire _f3_btb_mispredicts_0_T_2 = _f3_btb_mispredicts_0_T_1 & _f3_bpd_resp_io_deq_bits_preds_0_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_0_T_3 = _f3_bpd_resp_io_deq_bits_preds_0_predicted_pc_bits != brsigs_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_0_T_4 = _f3_btb_mispredicts_0_T_2 & _f3_btb_mispredicts_0_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_0 = _f3_btb_mispredicts_0_T_4; // @[frontend.scala:575:32, :697:61] wire _f3_npc_plus4_mask_0_T = ~f3_is_rvc_0; // @[frontend.scala:564:29, :703:9] wire _f3_npc_plus4_mask_0_T_1 = ~f3_prev_is_half; // @[frontend.scala:589:32, :703:26] assign _f3_npc_plus4_mask_0_T_2 = _f3_npc_plus4_mask_0_T & _f3_npc_plus4_mask_0_T_1; // @[frontend.scala:703:{9,23,26}] assign f3_npc_plus4_mask_0 = _f3_npc_plus4_mask_0_T_2; // @[frontend.scala:574:31, :703:23] wire [7:0] _offset_from_aligned_pc_T = {2'h0, brsigs_sfb_offset_bits}; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_1 = _offset_from_aligned_pc_T[6:0]; // @[frontend.scala:708:50] wire [1:0] _offset_from_aligned_pc_T_3 = {_offset_from_aligned_pc_T_2, 1'h0}; // @[frontend.scala:710:{12,31}] wire [7:0] _offset_from_aligned_pc_T_4 = {1'h0, _offset_from_aligned_pc_T_1} - {6'h0, _offset_from_aligned_pc_T_3}; // @[frontend.scala:708:50, :709:32, :710:12] wire [6:0] offset_from_aligned_pc = _offset_from_aligned_pc_T_4[6:0]; // @[frontend.scala:709:32] wire [7:0] upper_mask; // @[frontend.scala:713:28] wire [3:0] _upper_mask_T = offset_from_aligned_pc[4:1]; // @[frontend.scala:709:32, :715:52] wire [15:0] _upper_mask_T_1 = 16'h1 << _upper_mask_T; // @[OneHot.scala:58:35] wire [22:0] _upper_mask_T_3 = {7'h0, _upper_mask_T_1}; // @[OneHot.scala:58:35] assign upper_mask = _upper_mask_T_3[7:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_0_T = f3_mask_0 & brsigs_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_0_T_2 = offset_from_aligned_pc < 7'h11; // @[frontend.scala:709:32, :720:33] assign _f3_fetch_bundle_sfbs_0_T_3 = _f3_fetch_bundle_sfbs_0_T & _f3_fetch_bundle_sfbs_0_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_0 = _f3_fetch_bundle_sfbs_0_T_3; // @[frontend.scala:569:29, :719:33] wire [8:0] _f3_fetch_bundle_sfb_masks_0_T_16 = {1'h0, upper_mask}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_17 = _f3_fetch_bundle_sfb_masks_0_T_16[7:0]; // @[util.scala:384:{30,37}] wire [8:0] _f3_fetch_bundle_sfb_masks_0_T_18 = {upper_mask, 1'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_19 = _f3_fetch_bundle_sfb_masks_0_T_18[7:0]; // @[util.scala:384:{30,37}] wire [10:0] _f3_fetch_bundle_sfb_masks_0_T_20 = {1'h0, upper_mask, 2'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_21 = _f3_fetch_bundle_sfb_masks_0_T_20[7:0]; // @[util.scala:384:{30,37}] wire [10:0] _f3_fetch_bundle_sfb_masks_0_T_22 = {upper_mask, 3'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_23 = _f3_fetch_bundle_sfb_masks_0_T_22[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_0_T_24 = {3'h0, upper_mask, 4'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_25 = _f3_fetch_bundle_sfb_masks_0_T_24[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_0_T_26 = {2'h0, upper_mask, 5'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_27 = _f3_fetch_bundle_sfb_masks_0_T_26[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_0_T_28 = {1'h0, upper_mask, 6'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_29 = _f3_fetch_bundle_sfb_masks_0_T_28[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_0_T_30 = {upper_mask, 7'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_31 = _f3_fetch_bundle_sfb_masks_0_T_30[7:0]; // @[util.scala:384:{30,37}] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_32 = _f3_fetch_bundle_sfb_masks_0_T_17 \| _f3_fetch_bundle_sfb_masks_0_T_19; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_33 = _f3_fetch_bundle_sfb_masks_0_T_32 \| _f3_fetch_bundle_sfb_masks_0_T_21; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_34 = _f3_fetch_bundle_sfb_masks_0_T_33 \| _f3_fetch_bundle_sfb_masks_0_T_23; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_35 = _f3_fetch_bundle_sfb_masks_0_T_34 \| _f3_fetch_bundle_sfb_masks_0_T_25; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_36 = _f3_fetch_bundle_sfb_masks_0_T_35 \| _f3_fetch_bundle_sfb_masks_0_T_27; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_37 = _f3_fetch_bundle_sfb_masks_0_T_36 \| _f3_fetch_bundle_sfb_masks_0_T_29; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_38 = _f3_fetch_bundle_sfb_masks_0_T_37 \| _f3_fetch_bundle_sfb_masks_0_T_31; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_0_T_39 = ~_f3_fetch_bundle_sfb_masks_0_T_38; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_0_T_40 = _f3_fetch_bundle_sfb_masks_0_T_39 & 8'hFE; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_0 = _f3_fetch_bundle_sfb_masks_0_T_40; // @[frontend.scala:569:29, :722:68] wire _GEN_16 = f3_fetch_bundle_xcpt_pf_if \| f3_fetch_bundle_xcpt_ae_if; // @[frontend.scala:569:29, :723:75] wire _f3_fetch_bundle_shadowable_mask_0_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_0_T = _GEN_16; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_1_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_1_T = _GEN_16; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_2_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_2_T = _GEN_16; // @[frontend.scala:723:75] wire _f3_fetch_bundle_shadowable_mask_3_T; // @[frontend.scala:723:75] assign _f3_fetch_bundle_shadowable_mask_3_T = _GEN_16; // @[frontend.scala:723:75] wire _s0_valid_T_11; // @[frontend.scala:831:52] assign _s0_valid_T_11 = _GEN_16; // @[frontend.scala:723:75, :831:52] wire _f3_fetch_bundle_shadowable_mask_0_T_1 = _f3_fetch_bundle_shadowable_mask_0_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_0_T_2 = _f3_fetch_bundle_shadowable_mask_0_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_0_T_3 = ~_f3_fetch_bundle_shadowable_mask_0_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_0_T_4 = _f3_fetch_bundle_shadowable_mask_0_T_3; // @[frontend.scala:723:{46,143}] wire _f3_fetch_bundle_shadowable_mask_0_T_5 = ~f3_mask_0; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_0_T_6 = brsigs_shadowable \| _f3_fetch_bundle_shadowable_mask_0_T_5; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_0_T_7 = _f3_fetch_bundle_shadowable_mask_0_T_4 & _f3_fetch_bundle_shadowable_mask_0_T_6; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_0 = _f3_fetch_bundle_shadowable_mask_0_T_7; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_0 = offset_from_aligned_pc[3:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_0_T_2 = _f3_redirects_0_T \| _f3_redirects_0_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_17 = brsigs_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_0_T_3; // @[frontend.scala:733:26] assign _f3_redirects_0_T_3 = _GEN_17; // @[frontend.scala:733:26] wire _f3_br_mask_0_T; // @[frontend.scala:736:56] assign _f3_br_mask_0_T = _GEN_17; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_0_T_4 = _f3_redirects_0_T_3 & _f3_bpd_resp_io_deq_bits_preds_0_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_0_T_5 = _f3_redirects_0_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_0_T_6 = _f3_redirects_0_T_2 \| _f3_redirects_0_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_0_T_7 = f3_mask_0 & _f3_redirects_0_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_0 = _f3_redirects_0_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_0_T_1 = f3_mask_0 & _f3_br_mask_0_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_0 = _f3_br_mask_0_T_1; // @[frontend.scala:571:29, :736:37] wire _valid_T_5; // @[frontend.scala:675:38] wire valid_1; // @[frontend.scala:605:23] assign f3_ret_mask_1 = brsigs_1_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_1 = brsigs_1_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_1 = brsigs_1_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_1_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_1_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_1_target; // @[frontend.scala:613:24] wire brsigs_1_shadowable; // @[frontend.scala:613:24] wire [31:0] _inst_T; // @[frontend.scala:674:29] assign f3_fetch_bundle_insts_1 = inst; // @[frontend.scala:569:29, :660:24] assign bank_insts_1 = inst; // @[frontend.scala:600:26, :660:24] assign exp_inst = _exp_inst_rvc_exp_io_rvc ? _exp_inst_rvc_exp_io_out_bits : inst; // @[frontend.scala:660:24] assign f3_fetch_bundle_exp_insts_1 = exp_inst; // @[frontend.scala:569:29] wire [40:0] _pc_T = _GEN_12 + 41'h2; // @[frontend.scala:619:34, :662:32] wire [39:0] pc = _pc_T[39:0]; // @[frontend.scala:662:32] assign _inst_T = bank_data[47:16]; // @[frontend.scala:598:29, :674:29] assign inst = _inst_T; // @[frontend.scala:660:24, :674:29] wire _valid_T_1 = _valid_T != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_2 = ~_valid_T_1; // @[frontend.scala:592:38, :675:59] wire _valid_T_3 = bank_mask_0 & _valid_T_2; // @[frontend.scala:599:26, :675:{56,59}] wire _valid_T_4 = ~_valid_T_3; // @[frontend.scala:675:{41,56}] assign _valid_T_5 = f3_prev_is_half \| _valid_T_4; // @[frontend.scala:589:32, :675:{38,41}] assign valid_1 = _valid_T_5; // @[frontend.scala:605:23, :675:38] wire [1:0] _f3_is_rvc_1_T = bank_insts_1[1:0]; // @[frontend.scala:592:32, :600:26] wire [1:0] _valid_T_6 = bank_insts_1[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_1_T_1 = _f3_is_rvc_1_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_1 = _f3_is_rvc_1_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_1_T = _f3_io_deq_bits_mask[1]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_1_T = _f3_io_deq_bits_mask[1]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_1_T_1 = _f3_io_deq_valid & _bank_mask_1_T; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_1_T_2 = _bank_mask_1_T_1 & valid_1; // @[frontend.scala:605:23, :689:{39,62}] wire _bank_mask_1_T_3 = ~f3_redirects_0; // @[frontend.scala:565:29, :689:74] assign _bank_mask_1_T_4 = _bank_mask_1_T_2 & _bank_mask_1_T_3; // @[frontend.scala:689:{62,71,74}] assign bank_mask_1 = _bank_mask_1_T_4; // @[frontend.scala:599:26, :689:71] wire _f3_mask_1_T_1 = _f3_io_deq_valid & _f3_mask_1_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_1_T_2 = _f3_mask_1_T_1 & valid_1; // @[frontend.scala:605:23, :690:{39,62}] wire _f3_mask_1_T_3 = ~f3_redirects_0; // @[frontend.scala:565:29, :689:74, :690:74] assign _f3_mask_1_T_4 = _f3_mask_1_T_2 & _f3_mask_1_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_1 = _f3_mask_1_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_18 = brsigs_1_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_1_T; // @[frontend.scala:691:43] assign _f3_targs_1_T = _GEN_18; // @[frontend.scala:691:43] wire _f3_redirects_1_T_1; // @[frontend.scala:732:56] assign _f3_redirects_1_T_1 = _GEN_18; // @[frontend.scala:691:43, :732:56] assign _f3_targs_1_T_1 = _f3_targs_1_T ? _f3_bpd_resp_io_deq_bits_preds_1_predicted_pc_bits : brsigs_1_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_1 = _f3_targs_1_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_19 = brsigs_1_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_1_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_1_T = _GEN_19; // @[frontend.scala:696:49] wire _f3_redirects_1_T; // @[frontend.scala:732:25] assign _f3_redirects_1_T = _GEN_19; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_1_T_1 = _f3_btb_mispredicts_1_T & valid_1; // @[frontend.scala:605:23, :696:{49,61}] wire _f3_btb_mispredicts_1_T_2 = _f3_btb_mispredicts_1_T_1 & _f3_bpd_resp_io_deq_bits_preds_1_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_1_T_3 = _f3_bpd_resp_io_deq_bits_preds_1_predicted_pc_bits != brsigs_1_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_1_T_4 = _f3_btb_mispredicts_1_T_2 & _f3_btb_mispredicts_1_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_1 = _f3_btb_mispredicts_1_T_4; // @[frontend.scala:575:32, :697:61] assign _f3_npc_plus4_mask_1_T = ~f3_is_rvc_1; // @[frontend.scala:564:29, :705:9] assign f3_npc_plus4_mask_1 = _f3_npc_plus4_mask_1_T; // @[frontend.scala:574:31, :705:9] wire [7:0] _offset_from_aligned_pc_T_5 = {2'h0, brsigs_1_sfb_offset_bits} + 8'h2; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_6 = _offset_from_aligned_pc_T_5[6:0]; // @[frontend.scala:708:50] wire [7:0] _offset_from_aligned_pc_T_9 = {1'h0, _offset_from_aligned_pc_T_6}; // @[frontend.scala:708:50, :709:32] wire [6:0] offset_from_aligned_pc_1 = _offset_from_aligned_pc_T_9[6:0]; // @[frontend.scala:709:32] wire [7:0] upper_mask_1; // @[frontend.scala:713:28] wire [3:0] _upper_mask_T_4 = offset_from_aligned_pc_1[4:1]; // @[frontend.scala:709:32, :715:52] wire [15:0] _upper_mask_T_5 = 16'h1 << _upper_mask_T_4; // @[OneHot.scala:58:35] wire [22:0] _upper_mask_T_7 = {7'h0, _upper_mask_T_5}; // @[OneHot.scala:58:35] assign upper_mask_1 = _upper_mask_T_7[7:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_1_T = f3_mask_1 & brsigs_1_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_1_T_2 = offset_from_aligned_pc_1 < 7'h11; // @[frontend.scala:709:32, :720:33] assign _f3_fetch_bundle_sfbs_1_T_3 = _f3_fetch_bundle_sfbs_1_T & _f3_fetch_bundle_sfbs_1_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_1 = _f3_fetch_bundle_sfbs_1_T_3; // @[frontend.scala:569:29, :719:33] wire [8:0] _f3_fetch_bundle_sfb_masks_1_T_16 = {1'h0, upper_mask_1}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_17 = _f3_fetch_bundle_sfb_masks_1_T_16[7:0]; // @[util.scala:384:{30,37}] wire [8:0] _f3_fetch_bundle_sfb_masks_1_T_18 = {upper_mask_1, 1'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_19 = _f3_fetch_bundle_sfb_masks_1_T_18[7:0]; // @[util.scala:384:{30,37}] wire [10:0] _f3_fetch_bundle_sfb_masks_1_T_20 = {1'h0, upper_mask_1, 2'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_21 = _f3_fetch_bundle_sfb_masks_1_T_20[7:0]; // @[util.scala:384:{30,37}] wire [10:0] _f3_fetch_bundle_sfb_masks_1_T_22 = {upper_mask_1, 3'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_23 = _f3_fetch_bundle_sfb_masks_1_T_22[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_1_T_24 = {3'h0, upper_mask_1, 4'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_25 = _f3_fetch_bundle_sfb_masks_1_T_24[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_1_T_26 = {2'h0, upper_mask_1, 5'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_27 = _f3_fetch_bundle_sfb_masks_1_T_26[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_1_T_28 = {1'h0, upper_mask_1, 6'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_29 = _f3_fetch_bundle_sfb_masks_1_T_28[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_1_T_30 = {upper_mask_1, 7'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_31 = _f3_fetch_bundle_sfb_masks_1_T_30[7:0]; // @[util.scala:384:{30,37}] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_32 = _f3_fetch_bundle_sfb_masks_1_T_17 \| _f3_fetch_bundle_sfb_masks_1_T_19; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_33 = _f3_fetch_bundle_sfb_masks_1_T_32 \| _f3_fetch_bundle_sfb_masks_1_T_21; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_34 = _f3_fetch_bundle_sfb_masks_1_T_33 \| _f3_fetch_bundle_sfb_masks_1_T_23; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_35 = _f3_fetch_bundle_sfb_masks_1_T_34 \| _f3_fetch_bundle_sfb_masks_1_T_25; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_36 = _f3_fetch_bundle_sfb_masks_1_T_35 \| _f3_fetch_bundle_sfb_masks_1_T_27; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_37 = _f3_fetch_bundle_sfb_masks_1_T_36 \| _f3_fetch_bundle_sfb_masks_1_T_29; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_38 = _f3_fetch_bundle_sfb_masks_1_T_37 \| _f3_fetch_bundle_sfb_masks_1_T_31; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_1_T_39 = ~_f3_fetch_bundle_sfb_masks_1_T_38; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_1_T_40 = _f3_fetch_bundle_sfb_masks_1_T_39 & 8'hFC; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_1 = _f3_fetch_bundle_sfb_masks_1_T_40; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_1_T_1 = _f3_fetch_bundle_shadowable_mask_1_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_1_T_2 = _f3_fetch_bundle_shadowable_mask_1_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_1_T_3 = ~_f3_fetch_bundle_shadowable_mask_1_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_1_T_4 = _f3_fetch_bundle_shadowable_mask_1_T_3; // @[frontend.scala:723:{46,143}] wire _f3_fetch_bundle_shadowable_mask_1_T_5 = ~f3_mask_1; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_1_T_6 = brsigs_1_shadowable \| _f3_fetch_bundle_shadowable_mask_1_T_5; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_1_T_7 = _f3_fetch_bundle_shadowable_mask_1_T_4 & _f3_fetch_bundle_shadowable_mask_1_T_6; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_1 = _f3_fetch_bundle_shadowable_mask_1_T_7; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_1 = offset_from_aligned_pc_1[3:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_1_T_2 = _f3_redirects_1_T \| _f3_redirects_1_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_20 = brsigs_1_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_1_T_3; // @[frontend.scala:733:26] assign _f3_redirects_1_T_3 = _GEN_20; // @[frontend.scala:733:26] wire _f3_br_mask_1_T; // @[frontend.scala:736:56] assign _f3_br_mask_1_T = _GEN_20; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_1_T_4 = _f3_redirects_1_T_3 & _f3_bpd_resp_io_deq_bits_preds_1_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_1_T_5 = _f3_redirects_1_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_1_T_6 = _f3_redirects_1_T_2 \| _f3_redirects_1_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_1_T_7 = f3_mask_1 & _f3_redirects_1_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_1 = _f3_redirects_1_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_1_T_1 = f3_mask_1 & _f3_br_mask_1_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_1 = _f3_br_mask_1_T_1; // @[frontend.scala:571:29, :736:37] wire _T_29 = f3_redirects_0 \| f3_redirects_1; // @[frontend.scala:565:29, :744:39] wire _valid_T_10; // @[frontend.scala:682:20] wire valid_2; // @[frontend.scala:605:23] assign f3_ret_mask_2 = brsigs_2_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_2 = brsigs_2_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_2 = brsigs_2_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_2_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_2_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_2_target; // @[frontend.scala:613:24] wire brsigs_2_shadowable; // @[frontend.scala:613:24] wire [31:0] _inst_T_1; // @[frontend.scala:681:29] assign f3_fetch_bundle_insts_2 = inst_1; // @[frontend.scala:569:29, :660:24] assign bank_insts_2 = inst_1; // @[frontend.scala:600:26, :660:24] assign exp_inst_1 = _exp_inst_rvc_exp_1_io_rvc ? _exp_inst_rvc_exp_1_io_out_bits : inst_1; // @[frontend.scala:660:24] assign f3_fetch_bundle_exp_insts_2 = exp_inst_1; // @[frontend.scala:569:29] wire [40:0] _pc_T_1 = _GEN_12 + 41'h4; // @[frontend.scala:619:34, :662:32] wire [39:0] pc_1 = _pc_T_1[39:0]; // @[frontend.scala:662:32] assign _inst_T_1 = bank_data[63:32]; // @[frontend.scala:598:29, :681:29] assign inst_1 = _inst_T_1; // @[frontend.scala:660:24, :681:29] wire _valid_T_7 = _valid_T_6 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_8 = ~_valid_T_7; // @[frontend.scala:592:38, :682:40] wire _valid_T_9 = bank_mask_1 & _valid_T_8; // @[frontend.scala:599:26, :682:{37,40}] assign _valid_T_10 = ~_valid_T_9; // @[frontend.scala:682:{20,37}] assign valid_2 = _valid_T_10; // @[frontend.scala:605:23, :682:20] wire [1:0] _f3_is_rvc_2_T = bank_insts_2[1:0]; // @[frontend.scala:592:32, :600:26] wire [1:0] _valid_T_11 = bank_insts_2[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_2_T_1 = _f3_is_rvc_2_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_2 = _f3_is_rvc_2_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_2_T = _f3_io_deq_bits_mask[2]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_2_T = _f3_io_deq_bits_mask[2]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_2_T_1 = _f3_io_deq_valid & _bank_mask_2_T; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_2_T_2 = _bank_mask_2_T_1 & valid_2; // @[frontend.scala:605:23, :689:{39,62}] wire _bank_mask_2_T_3 = ~_T_29; // @[frontend.scala:689:74, :744:39] assign _bank_mask_2_T_4 = _bank_mask_2_T_2 & _bank_mask_2_T_3; // @[frontend.scala:689:{62,71,74}] assign bank_mask_2 = _bank_mask_2_T_4; // @[frontend.scala:599:26, :689:71] wire _f3_mask_2_T_1 = _f3_io_deq_valid & _f3_mask_2_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_2_T_2 = _f3_mask_2_T_1 & valid_2; // @[frontend.scala:605:23, :690:{39,62}] wire _f3_mask_2_T_3 = ~_T_29; // @[frontend.scala:689:74, :690:74, :744:39] assign _f3_mask_2_T_4 = _f3_mask_2_T_2 & _f3_mask_2_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_2 = _f3_mask_2_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_21 = brsigs_2_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_2_T; // @[frontend.scala:691:43] assign _f3_targs_2_T = _GEN_21; // @[frontend.scala:691:43] wire _f3_redirects_2_T_1; // @[frontend.scala:732:56] assign _f3_redirects_2_T_1 = _GEN_21; // @[frontend.scala:691:43, :732:56] assign _f3_targs_2_T_1 = _f3_targs_2_T ? _f3_bpd_resp_io_deq_bits_preds_2_predicted_pc_bits : brsigs_2_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_2 = _f3_targs_2_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_22 = brsigs_2_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_2_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_2_T = _GEN_22; // @[frontend.scala:696:49] wire _f3_redirects_2_T; // @[frontend.scala:732:25] assign _f3_redirects_2_T = _GEN_22; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_2_T_1 = _f3_btb_mispredicts_2_T & valid_2; // @[frontend.scala:605:23, :696:{49,61}] wire _f3_btb_mispredicts_2_T_2 = _f3_btb_mispredicts_2_T_1 & _f3_bpd_resp_io_deq_bits_preds_2_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_2_T_3 = _f3_bpd_resp_io_deq_bits_preds_2_predicted_pc_bits != brsigs_2_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_2_T_4 = _f3_btb_mispredicts_2_T_2 & _f3_btb_mispredicts_2_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_2 = _f3_btb_mispredicts_2_T_4; // @[frontend.scala:575:32, :697:61] assign _f3_npc_plus4_mask_2_T = ~f3_is_rvc_2; // @[frontend.scala:564:29, :705:9] assign f3_npc_plus4_mask_2 = _f3_npc_plus4_mask_2_T; // @[frontend.scala:574:31, :705:9] wire [7:0] _offset_from_aligned_pc_T_10 = {2'h0, brsigs_2_sfb_offset_bits} + 8'h4; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_11 = _offset_from_aligned_pc_T_10[6:0]; // @[frontend.scala:708:50] wire [7:0] _offset_from_aligned_pc_T_14 = {1'h0, _offset_from_aligned_pc_T_11}; // @[frontend.scala:708:50, :709:32] wire [6:0] offset_from_aligned_pc_2 = _offset_from_aligned_pc_T_14[6:0]; // @[frontend.scala:709:32] wire [7:0] upper_mask_2; // @[frontend.scala:713:28] wire [3:0] _upper_mask_T_8 = offset_from_aligned_pc_2[4:1]; // @[frontend.scala:709:32, :715:52] wire [15:0] _upper_mask_T_9 = 16'h1 << _upper_mask_T_8; // @[OneHot.scala:58:35] wire [22:0] _upper_mask_T_11 = {7'h0, _upper_mask_T_9}; // @[OneHot.scala:58:35] assign upper_mask_2 = _upper_mask_T_11[7:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_2_T = f3_mask_2 & brsigs_2_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_2_T_2 = offset_from_aligned_pc_2 < 7'h11; // @[frontend.scala:709:32, :720:33] assign _f3_fetch_bundle_sfbs_2_T_3 = _f3_fetch_bundle_sfbs_2_T & _f3_fetch_bundle_sfbs_2_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_2 = _f3_fetch_bundle_sfbs_2_T_3; // @[frontend.scala:569:29, :719:33] wire [8:0] _f3_fetch_bundle_sfb_masks_2_T_16 = {1'h0, upper_mask_2}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_17 = _f3_fetch_bundle_sfb_masks_2_T_16[7:0]; // @[util.scala:384:{30,37}] wire [8:0] _f3_fetch_bundle_sfb_masks_2_T_18 = {upper_mask_2, 1'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_19 = _f3_fetch_bundle_sfb_masks_2_T_18[7:0]; // @[util.scala:384:{30,37}] wire [10:0] _f3_fetch_bundle_sfb_masks_2_T_20 = {1'h0, upper_mask_2, 2'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_21 = _f3_fetch_bundle_sfb_masks_2_T_20[7:0]; // @[util.scala:384:{30,37}] wire [10:0] _f3_fetch_bundle_sfb_masks_2_T_22 = {upper_mask_2, 3'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_23 = _f3_fetch_bundle_sfb_masks_2_T_22[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_2_T_24 = {3'h0, upper_mask_2, 4'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_25 = _f3_fetch_bundle_sfb_masks_2_T_24[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_2_T_26 = {2'h0, upper_mask_2, 5'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_27 = _f3_fetch_bundle_sfb_masks_2_T_26[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_2_T_28 = {1'h0, upper_mask_2, 6'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_29 = _f3_fetch_bundle_sfb_masks_2_T_28[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_2_T_30 = {upper_mask_2, 7'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_31 = _f3_fetch_bundle_sfb_masks_2_T_30[7:0]; // @[util.scala:384:{30,37}] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_32 = _f3_fetch_bundle_sfb_masks_2_T_17 \| _f3_fetch_bundle_sfb_masks_2_T_19; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_33 = _f3_fetch_bundle_sfb_masks_2_T_32 \| _f3_fetch_bundle_sfb_masks_2_T_21; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_34 = _f3_fetch_bundle_sfb_masks_2_T_33 \| _f3_fetch_bundle_sfb_masks_2_T_23; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_35 = _f3_fetch_bundle_sfb_masks_2_T_34 \| _f3_fetch_bundle_sfb_masks_2_T_25; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_36 = _f3_fetch_bundle_sfb_masks_2_T_35 \| _f3_fetch_bundle_sfb_masks_2_T_27; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_37 = _f3_fetch_bundle_sfb_masks_2_T_36 \| _f3_fetch_bundle_sfb_masks_2_T_29; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_38 = _f3_fetch_bundle_sfb_masks_2_T_37 \| _f3_fetch_bundle_sfb_masks_2_T_31; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_2_T_39 = ~_f3_fetch_bundle_sfb_masks_2_T_38; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_2_T_40 = _f3_fetch_bundle_sfb_masks_2_T_39 & 8'hF8; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_2 = _f3_fetch_bundle_sfb_masks_2_T_40; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_2_T_1 = _f3_fetch_bundle_shadowable_mask_2_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_2_T_2 = _f3_fetch_bundle_shadowable_mask_2_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_2_T_3 = ~_f3_fetch_bundle_shadowable_mask_2_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_2_T_4 = _f3_fetch_bundle_shadowable_mask_2_T_3; // @[frontend.scala:723:{46,143}] wire _f3_fetch_bundle_shadowable_mask_2_T_5 = ~f3_mask_2; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_2_T_6 = brsigs_2_shadowable \| _f3_fetch_bundle_shadowable_mask_2_T_5; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_2_T_7 = _f3_fetch_bundle_shadowable_mask_2_T_4 & _f3_fetch_bundle_shadowable_mask_2_T_6; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_2 = _f3_fetch_bundle_shadowable_mask_2_T_7; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_2 = offset_from_aligned_pc_2[3:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_2_T_2 = _f3_redirects_2_T \| _f3_redirects_2_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_23 = brsigs_2_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_2_T_3; // @[frontend.scala:733:26] assign _f3_redirects_2_T_3 = _GEN_23; // @[frontend.scala:733:26] wire _f3_br_mask_2_T; // @[frontend.scala:736:56] assign _f3_br_mask_2_T = _GEN_23; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_2_T_4 = _f3_redirects_2_T_3 & _f3_bpd_resp_io_deq_bits_preds_2_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_2_T_5 = _f3_redirects_2_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_2_T_6 = _f3_redirects_2_T_2 \| _f3_redirects_2_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_2_T_7 = f3_mask_2 & _f3_redirects_2_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_2 = _f3_redirects_2_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_2_T_1 = f3_mask_2 & _f3_br_mask_2_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_2 = _f3_br_mask_2_T_1; // @[frontend.scala:571:29, :736:37] wire _T_30 = _T_29 \| f3_redirects_2; // @[frontend.scala:565:29, :744:39] wire _valid_T_19; // @[frontend.scala:678:20] wire valid_3; // @[frontend.scala:605:23] assign f3_ret_mask_3 = brsigs_3_is_ret; // @[frontend.scala:573:29, :613:24] assign f3_call_mask_3 = brsigs_3_is_call; // @[frontend.scala:572:29, :613:24] assign f3_cfi_types_3 = brsigs_3_cfi_type; // @[frontend.scala:567:29, :613:24] wire brsigs_3_sfb_offset_valid; // @[frontend.scala:613:24] wire [5:0] brsigs_3_sfb_offset_bits; // @[frontend.scala:613:24] wire [39:0] brsigs_3_target; // @[frontend.scala:613:24] wire brsigs_3_shadowable; // @[frontend.scala:613:24] wire [31:0] _inst_T_3; // @[frontend.scala:677:23] assign f3_fetch_bundle_insts_3 = inst_2; // @[frontend.scala:569:29, :660:24] assign bank_insts_3 = inst_2; // @[frontend.scala:600:26, :660:24] assign exp_inst_2 = _exp_inst_rvc_exp_2_io_rvc ? _exp_inst_rvc_exp_2_io_out_bits : inst_2; // @[frontend.scala:660:24] assign f3_fetch_bundle_exp_insts_3 = exp_inst_2; // @[frontend.scala:569:29] wire [40:0] _pc_T_2 = _GEN_12 + 41'h6; // @[frontend.scala:619:34, :662:32] wire [39:0] pc_2 = _pc_T_2[39:0]; // @[frontend.scala:662:32] wire [15:0] _inst_T_2 = bank_data[63:48]; // @[frontend.scala:598:29, :677:44] assign _inst_T_3 = {16'h0, _inst_T_2}; // @[frontend.scala:677:{23,44}] assign inst_2 = _inst_T_3; // @[frontend.scala:660:24, :677:23] wire _valid_T_12 = _valid_T_11 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_13 = ~_valid_T_12; // @[frontend.scala:592:38, :678:41] wire _valid_T_14 = bank_mask_2 & _valid_T_13; // @[frontend.scala:599:26, :678:{38,41}] wire [1:0] _valid_T_15 = inst_2[1:0]; // @[frontend.scala:592:32, :660:24] wire _valid_T_16 = _valid_T_15 != 2'h3; // @[frontend.scala:592:{32,38}] wire _valid_T_17 = ~_valid_T_16; // @[frontend.scala:592:38, :679:13] wire _valid_T_18 = _valid_T_14 \| _valid_T_17; // @[frontend.scala:678:{38,66}, :679:13] assign _valid_T_19 = ~_valid_T_18; // @[frontend.scala:678:{20,66}] assign valid_3 = _valid_T_19; // @[frontend.scala:605:23, :678:20] wire [1:0] _f3_is_rvc_3_T = bank_insts_3[1:0]; // @[frontend.scala:592:32, :600:26] assign _f3_is_rvc_3_T_1 = _f3_is_rvc_3_T != 2'h3; // @[frontend.scala:592:{32,38}] assign f3_is_rvc_3 = _f3_is_rvc_3_T_1; // @[frontend.scala:564:29, :592:38] wire _bank_mask_3_T = _f3_io_deq_bits_mask[3]; // @[frontend.scala:516:11, :689:58] wire _f3_mask_3_T = _f3_io_deq_bits_mask[3]; // @[frontend.scala:516:11, :689:58, :690:58] wire _bank_mask_3_T_1 = _f3_io_deq_valid & _bank_mask_3_T; // @[frontend.scala:516:11, :689:{39,58}] wire _bank_mask_3_T_2 = _bank_mask_3_T_1 & valid_3; // @[frontend.scala:605:23, :689:{39,62}] wire _bank_mask_3_T_3 = ~_T_30; // @[frontend.scala:689:74, :744:39] assign _bank_mask_3_T_4 = _bank_mask_3_T_2 & _bank_mask_3_T_3; // @[frontend.scala:689:{62,71,74}] assign bank_mask_3 = _bank_mask_3_T_4; // @[frontend.scala:599:26, :689:71] wire _f3_mask_3_T_1 = _f3_io_deq_valid & _f3_mask_3_T; // @[frontend.scala:516:11, :690:{39,58}] wire _f3_mask_3_T_2 = _f3_mask_3_T_1 & valid_3; // @[frontend.scala:605:23, :690:{39,62}] wire _f3_mask_3_T_3 = ~_T_30; // @[frontend.scala:689:74, :690:74, :744:39] assign _f3_mask_3_T_4 = _f3_mask_3_T_2 & _f3_mask_3_T_3; // @[frontend.scala:690:{62,71,74}] assign f3_mask_3 = _f3_mask_3_T_4; // @[frontend.scala:570:29, :690:71] wire _GEN_24 = brsigs_3_cfi_type == 3'h3; // @[frontend.scala:613:24, :691:43] wire _f3_targs_3_T; // @[frontend.scala:691:43] assign _f3_targs_3_T = _GEN_24; // @[frontend.scala:691:43] wire _f3_redirects_3_T_1; // @[frontend.scala:732:56] assign _f3_redirects_3_T_1 = _GEN_24; // @[frontend.scala:691:43, :732:56] assign _f3_targs_3_T_1 = _f3_targs_3_T ? _f3_bpd_resp_io_deq_bits_preds_3_predicted_pc_bits : brsigs_3_target; // @[frontend.scala:521:11, :613:24, :691:{26,43}] assign f3_targs_3 = _f3_targs_3_T_1; // @[frontend.scala:566:29, :691:26] wire _GEN_25 = brsigs_3_cfi_type == 3'h2; // @[frontend.scala:613:24, :696:49] wire _f3_btb_mispredicts_3_T; // @[frontend.scala:696:49] assign _f3_btb_mispredicts_3_T = _GEN_25; // @[frontend.scala:696:49] wire _f3_redirects_3_T; // @[frontend.scala:732:25] assign _f3_redirects_3_T = _GEN_25; // @[frontend.scala:696:49, :732:25] wire _f3_btb_mispredicts_3_T_1 = _f3_btb_mispredicts_3_T & valid_3; // @[frontend.scala:605:23, :696:{49,61}] wire _f3_btb_mispredicts_3_T_2 = _f3_btb_mispredicts_3_T_1 & _f3_bpd_resp_io_deq_bits_preds_3_predicted_pc_valid; // @[frontend.scala:521:11, :696:{61,70}] wire _f3_btb_mispredicts_3_T_3 = _f3_bpd_resp_io_deq_bits_preds_3_predicted_pc_bits != brsigs_3_target; // @[frontend.scala:521:11, :613:24, :698:61] assign _f3_btb_mispredicts_3_T_4 = _f3_btb_mispredicts_3_T_2 & _f3_btb_mispredicts_3_T_3; // @[frontend.scala:696:70, :697:61, :698:61] assign f3_btb_mispredicts_3 = _f3_btb_mispredicts_3_T_4; // @[frontend.scala:575:32, :697:61] assign _f3_npc_plus4_mask_3_T = ~f3_is_rvc_3; // @[frontend.scala:564:29, :705:9] assign f3_npc_plus4_mask_3 = _f3_npc_plus4_mask_3_T; // @[frontend.scala:574:31, :705:9] wire [7:0] _offset_from_aligned_pc_T_15 = {2'h0, brsigs_3_sfb_offset_bits} + 8'h6; // @[frontend.scala:613:24, :708:50] wire [6:0] _offset_from_aligned_pc_T_16 = _offset_from_aligned_pc_T_15[6:0]; // @[frontend.scala:708:50] wire [7:0] _offset_from_aligned_pc_T_19 = {1'h0, _offset_from_aligned_pc_T_16}; // @[frontend.scala:708:50, :709:32] wire [6:0] offset_from_aligned_pc_3 = _offset_from_aligned_pc_T_19[6:0]; // @[frontend.scala:709:32] wire [7:0] upper_mask_3; // @[frontend.scala:713:28] wire [3:0] _upper_mask_T_12 = offset_from_aligned_pc_3[4:1]; // @[frontend.scala:709:32, :715:52] wire [15:0] _upper_mask_T_13 = 16'h1 << _upper_mask_T_12; // @[OneHot.scala:58:35] wire [22:0] _upper_mask_T_15 = {7'h0, _upper_mask_T_13}; // @[OneHot.scala:58:35] assign upper_mask_3 = _upper_mask_T_15[7:0]; // @[frontend.scala:713:28, :715:{18,80}] wire _f3_fetch_bundle_sfbs_3_T = f3_mask_3 & brsigs_3_sfb_offset_valid; // @[frontend.scala:570:29, :613:24, :718:20] wire _f3_fetch_bundle_sfbs_3_T_2 = offset_from_aligned_pc_3 < 7'h11; // @[frontend.scala:709:32, :720:33] assign _f3_fetch_bundle_sfbs_3_T_3 = _f3_fetch_bundle_sfbs_3_T & _f3_fetch_bundle_sfbs_3_T_2; // @[frontend.scala:718:20, :719:33, :720:33] assign f3_fetch_bundle_sfbs_3 = _f3_fetch_bundle_sfbs_3_T_3; // @[frontend.scala:569:29, :719:33] wire [8:0] _f3_fetch_bundle_sfb_masks_3_T_16 = {1'h0, upper_mask_3}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_17 = _f3_fetch_bundle_sfb_masks_3_T_16[7:0]; // @[util.scala:384:{30,37}] wire [8:0] _f3_fetch_bundle_sfb_masks_3_T_18 = {upper_mask_3, 1'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_19 = _f3_fetch_bundle_sfb_masks_3_T_18[7:0]; // @[util.scala:384:{30,37}] wire [10:0] _f3_fetch_bundle_sfb_masks_3_T_20 = {1'h0, upper_mask_3, 2'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_21 = _f3_fetch_bundle_sfb_masks_3_T_20[7:0]; // @[util.scala:384:{30,37}] wire [10:0] _f3_fetch_bundle_sfb_masks_3_T_22 = {upper_mask_3, 3'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_23 = _f3_fetch_bundle_sfb_masks_3_T_22[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_3_T_24 = {3'h0, upper_mask_3, 4'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_25 = _f3_fetch_bundle_sfb_masks_3_T_24[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_3_T_26 = {2'h0, upper_mask_3, 5'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_27 = _f3_fetch_bundle_sfb_masks_3_T_26[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_3_T_28 = {1'h0, upper_mask_3, 6'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_29 = _f3_fetch_bundle_sfb_masks_3_T_28[7:0]; // @[util.scala:384:{30,37}] wire [14:0] _f3_fetch_bundle_sfb_masks_3_T_30 = {upper_mask_3, 7'h0}; // @[util.scala:384:30] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_31 = _f3_fetch_bundle_sfb_masks_3_T_30[7:0]; // @[util.scala:384:{30,37}] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_32 = _f3_fetch_bundle_sfb_masks_3_T_17 \| _f3_fetch_bundle_sfb_masks_3_T_19; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_33 = _f3_fetch_bundle_sfb_masks_3_T_32 \| _f3_fetch_bundle_sfb_masks_3_T_21; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_34 = _f3_fetch_bundle_sfb_masks_3_T_33 \| _f3_fetch_bundle_sfb_masks_3_T_23; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_35 = _f3_fetch_bundle_sfb_masks_3_T_34 \| _f3_fetch_bundle_sfb_masks_3_T_25; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_36 = _f3_fetch_bundle_sfb_masks_3_T_35 \| _f3_fetch_bundle_sfb_masks_3_T_27; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_37 = _f3_fetch_bundle_sfb_masks_3_T_36 \| _f3_fetch_bundle_sfb_masks_3_T_29; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_38 = _f3_fetch_bundle_sfb_masks_3_T_37 \| _f3_fetch_bundle_sfb_masks_3_T_31; // @[util.scala:384:{37,54}] wire [7:0] _f3_fetch_bundle_sfb_masks_3_T_39 = ~_f3_fetch_bundle_sfb_masks_3_T_38; // @[util.scala:384:54] assign _f3_fetch_bundle_sfb_masks_3_T_40 = _f3_fetch_bundle_sfb_masks_3_T_39 & 8'hF0; // @[frontend.scala:722:{68,70}] assign f3_fetch_bundle_sfb_masks_3 = _f3_fetch_bundle_sfb_masks_3_T_40; // @[frontend.scala:569:29, :722:68] wire _f3_fetch_bundle_shadowable_mask_3_T_1 = _f3_fetch_bundle_shadowable_mask_3_T; // @[frontend.scala:723:{75,105}] wire _f3_fetch_bundle_shadowable_mask_3_T_2 = _f3_fetch_bundle_shadowable_mask_3_T_1; // @[frontend.scala:723:{105,124}] wire _f3_fetch_bundle_shadowable_mask_3_T_3 = ~_f3_fetch_bundle_shadowable_mask_3_T_2; // @[frontend.scala:723:{46,124}] wire _f3_fetch_bundle_shadowable_mask_3_T_4 = _f3_fetch_bundle_shadowable_mask_3_T_3; // @[frontend.scala:723:{46,143}] wire _f3_fetch_bundle_shadowable_mask_3_T_5 = ~f3_mask_3; // @[frontend.scala:570:29, :725:68] wire _f3_fetch_bundle_shadowable_mask_3_T_6 = brsigs_3_shadowable \| _f3_fetch_bundle_shadowable_mask_3_T_5; // @[frontend.scala:613:24, :725:{65,68}] assign _f3_fetch_bundle_shadowable_mask_3_T_7 = _f3_fetch_bundle_shadowable_mask_3_T_4 & _f3_fetch_bundle_shadowable_mask_3_T_6; // @[frontend.scala:723:143, :724:62, :725:65] assign f3_fetch_bundle_shadowable_mask_3 = _f3_fetch_bundle_shadowable_mask_3_T_7; // @[frontend.scala:569:29, :724:62] assign f3_fetch_bundle_sfb_dests_3 = offset_from_aligned_pc_3[3:0]; // @[frontend.scala:569:29, :709:32, :726:42] wire _f3_redirects_3_T_2 = _f3_redirects_3_T \| _f3_redirects_3_T_1; // @[frontend.scala:732:{25,37,56}] wire _GEN_26 = brsigs_3_cfi_type == 3'h1; // @[frontend.scala:613:24, :733:26] wire _f3_redirects_3_T_3; // @[frontend.scala:733:26] assign _f3_redirects_3_T_3 = _GEN_26; // @[frontend.scala:733:26] wire _f3_br_mask_3_T; // @[frontend.scala:736:56] assign _f3_br_mask_3_T = _GEN_26; // @[frontend.scala:733:26, :736:56] wire _f3_redirects_3_T_4 = _f3_redirects_3_T_3 & _f3_bpd_resp_io_deq_bits_preds_3_taken; // @[frontend.scala:521:11, :733:{26,37}] wire _f3_redirects_3_T_5 = _f3_redirects_3_T_4; // @[frontend.scala:733:{37,79}] wire _f3_redirects_3_T_6 = _f3_redirects_3_T_2 \| _f3_redirects_3_T_5; // @[frontend.scala:732:{37,69}, :733:79] assign _f3_redirects_3_T_7 = f3_mask_3 & _f3_redirects_3_T_6; // @[frontend.scala:570:29, :731:40, :732:69] assign f3_redirects_3 = _f3_redirects_3_T_7; // @[frontend.scala:565:29, :731:40] assign _f3_br_mask_3_T_1 = f3_mask_3 & _f3_br_mask_3_T; // @[frontend.scala:570:29, :736:{37,56}] assign f3_br_mask_3 = _f3_br_mask_3_T_1; // @[frontend.scala:571:29, :736:37] assign f3_fetch_bundle_end_half_bits = bank_insts_3[15:0]; // @[frontend.scala:569:29, :600:26, :746:40] assign f3_fetch_bundle_end_half_valid = ~(bank_mask_2 & (&(bank_insts_2[1:0]))) & (&(bank_insts_3[1:0])); // @[frontend.scala:569:29, :592:{32,38}, :599:26, :600:26, :746:40, :748:{8,33,69}] wire [3:0][2:0] _GEN_27 = {{f3_cfi_types_3}, {f3_cfi_types_2}, {f3_cfi_types_1}, {f3_cfi_types_0}}; // @[frontend.scala:567:29, :755:33] assign f3_fetch_bundle_cfi_type = _GEN_27[f3_fetch_bundle_cfi_idx_bits]; // @[frontend.scala:569:29, :755:33] wire [3:0] _GEN_28 = {{f3_call_mask_3}, {f3_call_mask_2}, {f3_call_mask_1}, {f3_call_mask_0}}; // @[frontend.scala:572:29, :756:33] assign f3_fetch_bundle_cfi_is_call = _GEN_28[f3_fetch_bundle_cfi_idx_bits]; // @[frontend.scala:569:29, :756:33] wire [3:0] _GEN_29 = {{f3_ret_mask_3}, {f3_ret_mask_2}, {f3_ret_mask_1}, {f3_ret_mask_0}}; // @[frontend.scala:573:29, :757:33] assign f3_fetch_bundle_cfi_is_ret = _GEN_29[f3_fetch_bundle_cfi_idx_bits]; // @[frontend.scala:569:29, :757:33] wire [3:0] _GEN_30 = {{f3_npc_plus4_mask_3}, {f3_npc_plus4_mask_2}, {f3_npc_plus4_mask_1}, {f3_npc_plus4_mask_0}}; // @[frontend.scala:574:31, :758:33] assign f3_fetch_bundle_cfi_npc_plus4 = _GEN_30[f3_fetch_bundle_cfi_idx_bits]; // @[frontend.scala:569:29, :758:33] wire _f4_btb_corrections_io_enq_valid_T = f4_ready & _f3_io_deq_valid; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module RecFNToIN_e8_s24_i8 : input clock : Clock input reset : Reset output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip signedOut : UInt<1>, out : UInt<8>, intExceptionFlags : UInt<3>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node magGeOne = bits(rawIn.sExp, 8, 8) node posExp = bits(rawIn.sExp, 7, 0) node _magJustBelowOne_T = eq(magGeOne, UInt<1>(0h0)) node _magJustBelowOne_T_1 = andr(posExp) node magJustBelowOne = and(_magJustBelowOne_T, _magJustBelowOne_T_1) node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _shiftedSig_T = bits(rawIn.sig, 22, 0) node _shiftedSig_T_1 = cat(magGeOne, _shiftedSig_T) node _shiftedSig_T_2 = bits(rawIn.sExp, 2, 0) node _shiftedSig_T_3 = mux(magGeOne, _shiftedSig_T_2, UInt<1>(0h0)) node shiftedSig = dshl(_shiftedSig_T_1, _shiftedSig_T_3) node _alignedSig_T = shr(shiftedSig, 22) node _alignedSig_T_1 = bits(shiftedSig, 21, 0) node _alignedSig_T_2 = orr(_alignedSig_T_1) node alignedSig = cat(_alignedSig_T, _alignedSig_T_2) node _unroundedInt_T = shr(alignedSig, 2) node unroundedInt = or(UInt<8>(0h0), _unroundedInt_T) node _common_inexact_T = bits(alignedSig, 1, 0) node _common_inexact_T_1 = orr(_common_inexact_T) node _common_inexact_T_2 = eq(rawIn.isZero, UInt<1>(0h0)) node common_inexact = mux(magGeOne, _common_inexact_T_1, _common_inexact_T_2) node _roundIncr_near_even_T = bits(alignedSig, 2, 1) node _roundIncr_near_even_T_1 = andr(_roundIncr_near_even_T) node _roundIncr_near_even_T_2 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_3 = andr(_roundIncr_near_even_T_2) node _roundIncr_near_even_T_4 = or(_roundIncr_near_even_T_1, _roundIncr_near_even_T_3) node _roundIncr_near_even_T_5 = and(magGeOne, _roundIncr_near_even_T_4) node _roundIncr_near_even_T_6 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_7 = orr(_roundIncr_near_even_T_6) node _roundIncr_near_even_T_8 = and(magJustBelowOne, _roundIncr_near_even_T_7) node roundIncr_near_even = or(_roundIncr_near_even_T_5, _roundIncr_near_even_T_8) node _roundIncr_near_maxMag_T = bits(alignedSig, 1, 1) node _roundIncr_near_maxMag_T_1 = and(magGeOne, _roundIncr_near_maxMag_T) node roundIncr_near_maxMag = or(_roundIncr_near_maxMag_T_1, magJustBelowOne) node _roundIncr_T = and(roundingMode_near_even, roundIncr_near_even) node _roundIncr_T_1 = and(roundingMode_near_maxMag, roundIncr_near_maxMag) node _roundIncr_T_2 = or(_roundIncr_T, _roundIncr_T_1) node _roundIncr_T_3 = or(roundingMode_min, roundingMode_odd) node _roundIncr_T_4 = and(rawIn.sign, common_inexact) node _roundIncr_T_5 = and(_roundIncr_T_3, _roundIncr_T_4) node _roundIncr_T_6 = or(_roundIncr_T_2, _roundIncr_T_5) node _roundIncr_T_7 = eq(rawIn.sign, UInt<1>(0h0)) node _roundIncr_T_8 = and(_roundIncr_T_7, common_inexact) node _roundIncr_T_9 = and(roundingMode_max, _roundIncr_T_8) node roundIncr = or(_roundIncr_T_6, _roundIncr_T_9) node _complUnroundedInt_T = not(unroundedInt) node complUnroundedInt = mux(rawIn.sign, _complUnroundedInt_T, unroundedInt) node _roundedInt_T = xor(roundIncr, rawIn.sign) node _roundedInt_T_1 = add(complUnroundedInt, UInt<1>(0h1)) node _roundedInt_T_2 = tail(_roundedInt_T_1, 1) node _roundedInt_T_3 = mux(_roundedInt_T, _roundedInt_T_2, complUnroundedInt) node _roundedInt_T_4 = and(roundingMode_odd, common_inexact) node roundedInt = or(_roundedInt_T_3, _roundedInt_T_4) node magGeOne_atOverflowEdge = eq(posExp, UInt<3>(0h7)) node _roundCarryBut2_T = bits(unroundedInt, 5, 0) node _roundCarryBut2_T_1 = andr(_roundCarryBut2_T) node roundCarryBut2 = and(_roundCarryBut2_T_1, roundIncr) node _common_overflow_T = geq(posExp, UInt<4>(0h8)) node _common_overflow_T_1 = bits(unroundedInt, 6, 0) node _common_overflow_T_2 = orr(_common_overflow_T_1) node _common_overflow_T_3 = or(_common_overflow_T_2, roundIncr) node _common_overflow_T_4 = and(magGeOne_atOverflowEdge, _common_overflow_T_3) node _common_overflow_T_5 = eq(posExp, UInt<3>(0h6)) node _common_overflow_T_6 = and(_common_overflow_T_5, roundCarryBut2) node _common_overflow_T_7 = or(magGeOne_atOverflowEdge, _common_overflow_T_6) node _common_overflow_T_8 = mux(rawIn.sign, _common_overflow_T_4, _common_overflow_T_7) node _common_overflow_T_9 = bits(unroundedInt, 6, 6) node _common_overflow_T_10 = and(magGeOne_atOverflowEdge, _common_overflow_T_9) node _common_overflow_T_11 = and(_common_overflow_T_10, roundCarryBut2) node _common_overflow_T_12 = or(rawIn.sign, _common_overflow_T_11) node _common_overflow_T_13 = mux(io.signedOut, _common_overflow_T_8, _common_overflow_T_12) node _common_overflow_T_14 = or(_common_overflow_T, _common_overflow_T_13) node _common_overflow_T_15 = eq(io.signedOut, UInt<1>(0h0)) node _common_overflow_T_16 = and(_common_overflow_T_15, rawIn.sign) node _common_overflow_T_17 = and(_common_overflow_T_16, roundIncr) node common_overflow = mux(magGeOne, _common_overflow_T_14, _common_overflow_T_17) node invalidExc = or(rawIn.isNaN, rawIn.isInf) node _overflow_T = eq(invalidExc, UInt<1>(0h0)) node overflow = and(_overflow_T, common_overflow) node _inexact_T = eq(invalidExc, UInt<1>(0h0)) node _inexact_T_1 = eq(common_overflow, UInt<1>(0h0)) node _inexact_T_2 = and(_inexact_T, _inexact_T_1) node inexact = and(_inexact_T_2, common_inexact) node _excSign_T = eq(rawIn.isNaN, UInt<1>(0h0)) node excSign = and(_excSign_T, rawIn.sign) node _excOut_T = eq(io.signedOut, excSign) node _excOut_T_1 = mux(_excOut_T, UInt<8>(0h80), UInt<1>(0h0)) node _excOut_T_2 = eq(excSign, UInt<1>(0h0)) node _excOut_T_3 = mux(_excOut_T_2, UInt<7>(0h7f), UInt<1>(0h0)) node excOut = or(_excOut_T_1, _excOut_T_3) node _io_out_T = or(invalidExc, common_overflow) node _io_out_T_1 = mux(_io_out_T, excOut, roundedInt) connect io.out, _io_out_T_1 node _io_intExceptionFlags_T = cat(invalidExc, overflow) node _io_intExceptionFlags_T_1 = cat(_io_intExceptionFlags_T, inexact) connect io.intExceptionFlags, _io_intExceptionFlags_T_1	module RecFNToIN_e8_s24_i8( // @[RecFNToIN.scala:46:7] input clock, // @[RecFNToIN.scala:46:7] input reset, // @[RecFNToIN.scala:46:7] input [32:0] io_in, // @[RecFNToIN.scala:49:16] output [7:0] io_out, // @[RecFNToIN.scala:49:16] output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7] wire roundingMode_minMag = 1'h0; // @[RecFNToIN.scala:68:53] wire roundingMode_min = 1'h0; // @[RecFNToIN.scala:69:53] wire roundingMode_max = 1'h0; // @[RecFNToIN.scala:70:53] wire roundingMode_near_maxMag = 1'h0; // @[RecFNToIN.scala:71:53] wire roundingMode_odd = 1'h0; // @[RecFNToIN.scala:72:53] wire _roundIncr_T_1 = 1'h0; // @[RecFNToIN.scala:99:35] wire _roundIncr_T_3 = 1'h0; // @[RecFNToIN.scala:100:28] wire _roundIncr_T_5 = 1'h0; // @[RecFNToIN.scala:100:49] wire _roundIncr_T_9 = 1'h0; // @[RecFNToIN.scala:102:27] wire _roundedInt_T_4 = 1'h0; // @[RecFNToIN.scala:108:31] wire _common_overflow_T_15 = 1'h0; // @[RecFNToIN.scala:128:13] wire _common_overflow_T_16 = 1'h0; // @[RecFNToIN.scala:128:27] wire _common_overflow_T_17 = 1'h0; // @[RecFNToIN.scala:128:41] wire io_signedOut = 1'h1; // @[RecFNToIN.scala:46:7] wire roundingMode_near_even = 1'h1; // @[RecFNToIN.scala:67:53] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToIN.scala:46:7] wire [7:0] _io_out_T_1; // @[RecFNToIN.scala:145:18] wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52] wire [7:0] io_out_0; // @[RecFNToIN.scala:46:7] wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire magGeOne = rawIn_sExp[8]; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] posExp = rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27] wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47] wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}] wire [22:0] _shiftedSig_T = rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}] wire [2:0] _shiftedSig_T_2 = rawIn_sExp[2:0]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 3'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27] wire [30:0] shiftedSig = {7'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16] wire [8:0] _alignedSig_T = shiftedSig[30:22]; // @[RecFNToIN.scala:83:49, :89:20] wire [21:0] _alignedSig_T_1 = shiftedSig[21:0]; // @[RecFNToIN.scala:83:49, :89:51] wire _alignedSig_T_2 = \|_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}] wire [9:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}] wire [7:0] _unroundedInt_T = alignedSig[9:2]; // @[RecFNToIN.scala:89:38, :90:52] wire [7:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}] wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50] wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64] wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39] wire _common_inexact_T_1 = \|_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}] wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}] wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39] wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}] wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}] wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 \| _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}] wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}] wire _roundIncr_near_even_T_7 = \|_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}] wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}] wire roundIncr_near_even = _roundIncr_near_even_T_5 \| _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26] wire _roundIncr_T = roundIncr_near_even; // @[RecFNToIN.scala:94:78, :98:35] wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56] wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}] wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 \| magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}] wire _roundIncr_T_2 = _roundIncr_T; // @[RecFNToIN.scala:98:{35,61}] wire _roundIncr_T_6 = _roundIncr_T_2; // @[RecFNToIN.scala:98:61, :99:61] wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23] wire roundIncr = _roundIncr_T_6; // @[RecFNToIN.scala:99:61, :101:46] wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}] wire [7:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45] wire [7:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23] wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 9'h1; // @[RecFNToIN.scala:103:32, :106:31] wire [7:0] _roundedInt_T_2 = _roundedInt_T_1[7:0]; // @[RecFNToIN.scala:106:31] wire [7:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31] wire [7:0] roundedInt = _roundedInt_T_3; // @[RecFNToIN.scala:105:12, :108:11] wire magGeOne_atOverflowEdge = posExp == 8'h7; // @[RecFNToIN.scala:62:28, :110:43] wire [5:0] _roundCarryBut2_T = unroundedInt[5:0]; // @[RecFNToIN.scala:90:40, :113:38] wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}] wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}] wire _common_overflow_T = \|(posExp[7:3]); // @[RecFNToIN.scala:62:28, :116:21] wire [6:0] _common_overflow_T_1 = unroundedInt[6:0]; // @[RecFNToIN.scala:90:40, :120:42] wire _common_overflow_T_2 = \|_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}] wire _common_overflow_T_3 = _common_overflow_T_2 \| roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}] wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64] wire _common_overflow_T_5 = posExp == 8'h6; // @[RecFNToIN.scala:62:28, :122:38] wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}] wire _common_overflow_T_7 = magGeOne_atOverflowEdge \| _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60] wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_13 = _common_overflow_T_8; // @[RecFNToIN.scala:117:20, :118:24] wire _common_overflow_T_9 = unroundedInt[6]; // @[RecFNToIN.scala:90:40, :126:42] wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42] wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57] wire _common_overflow_T_12 = rawIn_sign \| _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_14 = _common_overflow_T \| _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20] wire common_overflow = magGeOne & _common_overflow_T_14; // @[RecFNToIN.scala:61:30, :115:12, :116:36] wire invalidExc = rawIn_isNaN \| rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20] wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}] wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20] wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35] wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}] wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}] wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _excOut_T = excSign; // @[RecFNToIN.scala:137:32, :139:27] wire [7:0] _excOut_T_1 = {_excOut_T, 7'h0}; // @[RecFNToIN.scala:139:{12,27}] wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13] wire [6:0] _excOut_T_3 = {7{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}] wire [7:0] excOut = {_excOut_T_1[7], _excOut_T_1[6:0] \| _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12] wire _io_out_T = invalidExc \| common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30] assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}] assign io_out_0 = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18] wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40] assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}] assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52] assign io_out = io_out_0; // @[RecFNToIN.scala:46:7] assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulRawFN_22 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} inst mulFullRaw of MulFullRawFN_22 connect mulFullRaw.io.a.sig, io.a.sig connect mulFullRaw.io.a.sExp, io.a.sExp connect mulFullRaw.io.a.sign, io.a.sign connect mulFullRaw.io.a.isZero, io.a.isZero connect mulFullRaw.io.a.isInf, io.a.isInf connect mulFullRaw.io.a.isNaN, io.a.isNaN connect mulFullRaw.io.b.sig, io.b.sig connect mulFullRaw.io.b.sExp, io.b.sExp connect mulFullRaw.io.b.sign, io.b.sign connect mulFullRaw.io.b.isZero, io.b.isZero connect mulFullRaw.io.b.isInf, io.b.isInf connect mulFullRaw.io.b.isNaN, io.b.isNaN connect io.invalidExc, mulFullRaw.io.invalidExc connect io.rawOut, mulFullRaw.io.rawOut node _io_rawOut_sig_T = shr(mulFullRaw.io.rawOut.sig, 22) node _io_rawOut_sig_T_1 = bits(mulFullRaw.io.rawOut.sig, 21, 0) node _io_rawOut_sig_T_2 = orr(_io_rawOut_sig_T_1) node _io_rawOut_sig_T_3 = cat(_io_rawOut_sig_T, _io_rawOut_sig_T_2) connect io.rawOut.sig, _io_rawOut_sig_T_3	module MulRawFN_22( // @[MulRecFN.scala:75:7] input io_a_isNaN, // @[MulRecFN.scala:77:16] input io_a_isInf, // @[MulRecFN.scala:77:16] input io_a_isZero, // @[MulRecFN.scala:77:16] input io_a_sign, // @[MulRecFN.scala:77:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_a_sig, // @[MulRecFN.scala:77:16] input io_b_isNaN, // @[MulRecFN.scala:77:16] input io_b_isInf, // @[MulRecFN.scala:77:16] input io_b_isZero, // @[MulRecFN.scala:77:16] input io_b_sign, // @[MulRecFN.scala:77:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_b_sig, // @[MulRecFN.scala:77:16] output io_invalidExc, // @[MulRecFN.scala:77:16] output io_rawOut_isNaN, // @[MulRecFN.scala:77:16] output io_rawOut_isInf, // @[MulRecFN.scala:77:16] output io_rawOut_isZero, // @[MulRecFN.scala:77:16] output io_rawOut_sign, // @[MulRecFN.scala:77:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16] output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16] ); wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28] wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7] wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7] wire io_invalidExc_0; // @[MulRecFN.scala:75:7] wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15] wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37] wire _io_rawOut_sig_T_2 = \|_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}] assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10] MulFullRawFN_22 mulFullRaw ( // @[MulRecFN.scala:84:28] .io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7] .io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7] .io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7] .io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7] .io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7] .io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7] .io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7] .io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7] .io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7] .io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7] .io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7] .io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7] .io_invalidExc (io_invalidExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (_mulFullRaw_io_rawOut_sig) ); // @[MulRecFN.scala:84:28] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_174 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_430 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_174( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_430 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_16 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T = shr(io.in.a.bits.source, 2) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 2) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_12 = shr(io.in.a.bits.source, 2) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_18 = shr(io.in.a.bits.source, 2) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) wire _source_ok_WIRE : UInt<1>[4] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 connect _source_ok_WIRE[2], _source_ok_T_17 connect _source_ok_WIRE[3], _source_ok_T_23 node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2]) node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_4 = shr(io.in.a.bits.source, 2) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<2>(0h3)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_17 = shr(io.in.a.bits.source, 2) node _T_18 = eq(_T_17, UInt<1>(0h1)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_30 = shr(io.in.a.bits.source, 2) node _T_31 = eq(_T_30, UInt<2>(0h2)) node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) node _T_33 = and(_T_31, _T_32) node _T_34 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_38 = cvt(_T_37) node _T_39 = and(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = asSInt(_T_39) node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) node _T_42 = or(_T_36, _T_41) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_43 = shr(io.in.a.bits.source, 2) node _T_44 = eq(_T_43, UInt<2>(0h3)) node _T_45 = leq(UInt<1>(0h0), uncommonBits_3) node _T_46 = and(_T_44, _T_45) node _T_47 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(_T_48, UInt<1>(0h0)) node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = or(_T_49, _T_54) node _T_56 = and(_T_16, _T_29) node _T_57 = and(_T_56, _T_42) node _T_58 = and(_T_57, _T_55) node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_T_58, UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_58, UInt<1>(0h1), "") : assert_1 node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_62 : node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_65 = and(_T_63, _T_64) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_66 = shr(io.in.a.bits.source, 2) node _T_67 = eq(_T_66, UInt<1>(0h0)) node _T_68 = leq(UInt<1>(0h0), uncommonBits_4) node _T_69 = and(_T_67, _T_68) node _T_70 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_71 = and(_T_69, _T_70) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_72 = shr(io.in.a.bits.source, 2) node _T_73 = eq(_T_72, UInt<1>(0h1)) node _T_74 = leq(UInt<1>(0h0), uncommonBits_5) node _T_75 = and(_T_73, _T_74) node _T_76 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_77 = and(_T_75, _T_76) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_78 = shr(io.in.a.bits.source, 2) node _T_79 = eq(_T_78, UInt<2>(0h2)) node _T_80 = leq(UInt<1>(0h0), uncommonBits_6) node _T_81 = and(_T_79, _T_80) node _T_82 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_83 = and(_T_81, _T_82) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_84 = shr(io.in.a.bits.source, 2) node _T_85 = eq(_T_84, UInt<2>(0h3)) node _T_86 = leq(UInt<1>(0h0), uncommonBits_7) node _T_87 = and(_T_85, _T_86) node _T_88 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_89 = and(_T_87, _T_88) node _T_90 = or(_T_71, _T_77) node _T_91 = or(_T_90, _T_83) node _T_92 = or(_T_91, _T_89) node _T_93 = and(_T_65, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_96 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<14>(0h2000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<13>(0h1000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<17>(0h10000))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<18>(0h2f000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<17>(0h10000))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<13>(0h1000))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<27>(0h4000000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = or(_T_100, _T_105) node _T_137 = or(_T_136, _T_110) node _T_138 = or(_T_137, _T_115) node _T_139 = or(_T_138, _T_120) node _T_140 = or(_T_139, _T_125) node _T_141 = or(_T_140, _T_130) node _T_142 = or(_T_141, _T_135) node _T_143 = and(_T_95, _T_142) node _T_144 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_145 = or(UInt<1>(0h0), _T_144) node _T_146 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<29>(0h10000000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = or(_T_150, _T_155) node _T_157 = and(_T_145, _T_156) node _T_158 = or(UInt<1>(0h0), _T_143) node _T_159 = or(_T_158, _T_157) node _T_160 = and(_T_94, _T_159) node _T_161 = asUInt(reset) node _T_162 = eq(_T_161, UInt<1>(0h0)) when _T_162 : node _T_163 = eq(_T_160, UInt<1>(0h0)) when _T_163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_160, UInt<1>(0h1), "") : assert_2 node _T_164 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_165 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_166 = and(_T_164, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_169 = cvt(_T_168) node _T_170 = and(_T_169, asSInt(UInt<14>(0h2000))) node _T_171 = asSInt(_T_170) node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_174 = cvt(_T_173) node _T_175 = and(_T_174, asSInt(UInt<13>(0h1000))) node _T_176 = asSInt(_T_175) node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<17>(0h10000))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_184 = cvt(_T_183) node _T_185 = and(_T_184, asSInt(UInt<18>(0h2f000))) node _T_186 = asSInt(_T_185) node _T_187 = eq(_T_186, asSInt(UInt<1>(0h0))) node _T_188 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_189 = cvt(_T_188) node _T_190 = and(_T_189, asSInt(UInt<17>(0h10000))) node _T_191 = asSInt(_T_190) node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0))) node _T_193 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_194 = cvt(_T_193) node _T_195 = and(_T_194, asSInt(UInt<13>(0h1000))) node _T_196 = asSInt(_T_195) node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0))) node _T_198 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_199 = cvt(_T_198) node _T_200 = and(_T_199, asSInt(UInt<17>(0h10000))) node _T_201 = asSInt(_T_200) node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0))) node _T_203 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<27>(0h4000000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<29>(0h10000000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = or(_T_172, _T_177) node _T_219 = or(_T_218, _T_182) node _T_220 = or(_T_219, _T_187) node _T_221 = or(_T_220, _T_192) node _T_222 = or(_T_221, _T_197) node _T_223 = or(_T_222, _T_202) node _T_224 = or(_T_223, _T_207) node _T_225 = or(_T_224, _T_212) node _T_226 = or(_T_225, _T_217) node _T_227 = and(_T_167, _T_226) node _T_228 = or(UInt<1>(0h0), _T_227) node _T_229 = and(UInt<1>(0h0), _T_228) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_229, UInt<1>(0h1), "") : assert_3 node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(source_ok, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_236 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_237 = asUInt(reset) node _T_238 = eq(_T_237, UInt<1>(0h0)) when _T_238 : node _T_239 = eq(_T_236, UInt<1>(0h0)) when _T_239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_236, UInt<1>(0h1), "") : assert_5 node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(is_aligned, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_243 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_243, UInt<1>(0h1), "") : assert_7 node _T_247 = not(io.in.a.bits.mask) node _T_248 = eq(_T_247, UInt<1>(0h0)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_248, UInt<1>(0h1), "") : assert_8 node _T_252 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_253 = asUInt(reset) node _T_254 = eq(_T_253, UInt<1>(0h0)) when _T_254 : node _T_255 = eq(_T_252, UInt<1>(0h0)) when _T_255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_252, UInt<1>(0h1), "") : assert_9 node _T_256 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_256 : node _T_257 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_258 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_259 = and(_T_257, _T_258) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_260 = shr(io.in.a.bits.source, 2) node _T_261 = eq(_T_260, UInt<1>(0h0)) node _T_262 = leq(UInt<1>(0h0), uncommonBits_8) node _T_263 = and(_T_261, _T_262) node _T_264 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_265 = and(_T_263, _T_264) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_266 = shr(io.in.a.bits.source, 2) node _T_267 = eq(_T_266, UInt<1>(0h1)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_9) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_271 = and(_T_269, _T_270) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<2>(0h2)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_10) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<2>(0h3)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_11) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _T_284 = or(_T_265, _T_271) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_283) node _T_287 = and(_T_259, _T_286) node _T_288 = or(UInt<1>(0h0), _T_287) node _T_289 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<14>(0h2000))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_296 = cvt(_T_295) node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000))) node _T_298 = asSInt(_T_297) node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0))) node _T_300 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_301 = cvt(_T_300) node _T_302 = and(_T_301, asSInt(UInt<17>(0h10000))) node _T_303 = asSInt(_T_302) node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0))) node _T_305 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_306 = cvt(_T_305) node _T_307 = and(_T_306, asSInt(UInt<18>(0h2f000))) node _T_308 = asSInt(_T_307) node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0))) node _T_310 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_311 = cvt(_T_310) node _T_312 = and(_T_311, asSInt(UInt<17>(0h10000))) node _T_313 = asSInt(_T_312) node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0))) node _T_315 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<13>(0h1000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_321 = cvt(_T_320) node _T_322 = and(_T_321, asSInt(UInt<27>(0h4000000))) node _T_323 = asSInt(_T_322) node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<13>(0h1000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = or(_T_294, _T_299) node _T_331 = or(_T_330, _T_304) node _T_332 = or(_T_331, _T_309) node _T_333 = or(_T_332, _T_314) node _T_334 = or(_T_333, _T_319) node _T_335 = or(_T_334, _T_324) node _T_336 = or(_T_335, _T_329) node _T_337 = and(_T_289, _T_336) node _T_338 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_339 = or(UInt<1>(0h0), _T_338) node _T_340 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<29>(0h10000000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = or(_T_344, _T_349) node _T_351 = and(_T_339, _T_350) node _T_352 = or(UInt<1>(0h0), _T_337) node _T_353 = or(_T_352, _T_351) node _T_354 = and(_T_288, _T_353) node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_T_354, UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_354, UInt<1>(0h1), "") : assert_10 node _T_358 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_359 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<14>(0h2000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_368 = cvt(_T_367) node _T_369 = and(_T_368, asSInt(UInt<13>(0h1000))) node _T_370 = asSInt(_T_369) node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0))) node _T_372 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<17>(0h10000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<18>(0h2f000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<17>(0h10000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_388 = cvt(_T_387) node _T_389 = and(_T_388, asSInt(UInt<13>(0h1000))) node _T_390 = asSInt(_T_389) node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0))) node _T_392 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_393 = cvt(_T_392) node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000))) node _T_395 = asSInt(_T_394) node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0))) node _T_397 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<27>(0h4000000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_403 = cvt(_T_402) node _T_404 = and(_T_403, asSInt(UInt<13>(0h1000))) node _T_405 = asSInt(_T_404) node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0))) node _T_407 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_408 = cvt(_T_407) node _T_409 = and(_T_408, asSInt(UInt<29>(0h10000000))) node _T_410 = asSInt(_T_409) node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0))) node _T_412 = or(_T_366, _T_371) node _T_413 = or(_T_412, _T_376) node _T_414 = or(_T_413, _T_381) node _T_415 = or(_T_414, _T_386) node _T_416 = or(_T_415, _T_391) node _T_417 = or(_T_416, _T_396) node _T_418 = or(_T_417, _T_401) node _T_419 = or(_T_418, _T_406) node _T_420 = or(_T_419, _T_411) node _T_421 = and(_T_361, _T_420) node _T_422 = or(UInt<1>(0h0), _T_421) node _T_423 = and(UInt<1>(0h0), _T_422) node _T_424 = asUInt(reset) node _T_425 = eq(_T_424, UInt<1>(0h0)) when _T_425 : node _T_426 = eq(_T_423, UInt<1>(0h0)) when _T_426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_423, UInt<1>(0h1), "") : assert_11 node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(source_ok, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_430 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_431 = asUInt(reset) node _T_432 = eq(_T_431, UInt<1>(0h0)) when _T_432 : node _T_433 = eq(_T_430, UInt<1>(0h0)) when _T_433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_430, UInt<1>(0h1), "") : assert_13 node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(is_aligned, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_437 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_T_437, UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_437, UInt<1>(0h1), "") : assert_15 node _T_441 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_441, UInt<1>(0h1), "") : assert_16 node _T_445 = not(io.in.a.bits.mask) node _T_446 = eq(_T_445, UInt<1>(0h0)) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_446, UInt<1>(0h1), "") : assert_17 node _T_450 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_450, UInt<1>(0h1), "") : assert_18 node _T_454 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_454 : node _T_455 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_456 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_457 = and(_T_455, _T_456) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_458 = shr(io.in.a.bits.source, 2) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = leq(UInt<1>(0h0), uncommonBits_12) node _T_461 = and(_T_459, _T_460) node _T_462 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_463 = and(_T_461, _T_462) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_464 = shr(io.in.a.bits.source, 2) node _T_465 = eq(_T_464, UInt<1>(0h1)) node _T_466 = leq(UInt<1>(0h0), uncommonBits_13) node _T_467 = and(_T_465, _T_466) node _T_468 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_469 = and(_T_467, _T_468) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_470 = shr(io.in.a.bits.source, 2) node _T_471 = eq(_T_470, UInt<2>(0h2)) node _T_472 = leq(UInt<1>(0h0), uncommonBits_14) node _T_473 = and(_T_471, _T_472) node _T_474 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_475 = and(_T_473, _T_474) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_476 = shr(io.in.a.bits.source, 2) node _T_477 = eq(_T_476, UInt<2>(0h3)) node _T_478 = leq(UInt<1>(0h0), uncommonBits_15) node _T_479 = and(_T_477, _T_478) node _T_480 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_481 = and(_T_479, _T_480) node _T_482 = or(_T_463, _T_469) node _T_483 = or(_T_482, _T_475) node _T_484 = or(_T_483, _T_481) node _T_485 = and(_T_457, _T_484) node _T_486 = or(UInt<1>(0h0), _T_485) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_486, UInt<1>(0h1), "") : assert_19 node _T_490 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_491 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_492 = and(_T_490, _T_491) node _T_493 = or(UInt<1>(0h0), _T_492) node _T_494 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_495 = cvt(_T_494) node _T_496 = and(_T_495, asSInt(UInt<13>(0h1000))) node _T_497 = asSInt(_T_496) node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0))) node _T_499 = and(_T_493, _T_498) node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_502 = and(_T_500, _T_501) node _T_503 = or(UInt<1>(0h0), _T_502) node _T_504 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_505 = cvt(_T_504) node _T_506 = and(_T_505, asSInt(UInt<14>(0h2000))) node _T_507 = asSInt(_T_506) node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0))) node _T_509 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_510 = cvt(_T_509) node _T_511 = and(_T_510, asSInt(UInt<17>(0h10000))) node _T_512 = asSInt(_T_511) node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) node _T_514 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<18>(0h2f000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<17>(0h10000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_525 = cvt(_T_524) node _T_526 = and(_T_525, asSInt(UInt<13>(0h1000))) node _T_527 = asSInt(_T_526) node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0))) node _T_529 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<17>(0h10000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<27>(0h4000000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<29>(0h10000000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = or(_T_508, _T_513) node _T_550 = or(_T_549, _T_518) node _T_551 = or(_T_550, _T_523) node _T_552 = or(_T_551, _T_528) node _T_553 = or(_T_552, _T_533) node _T_554 = or(_T_553, _T_538) node _T_555 = or(_T_554, _T_543) node _T_556 = or(_T_555, _T_548) node _T_557 = and(_T_503, _T_556) node _T_558 = or(UInt<1>(0h0), _T_499) node _T_559 = or(_T_558, _T_557) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_559, UInt<1>(0h1), "") : assert_20 node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(source_ok, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(is_aligned, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_569 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_569, UInt<1>(0h1), "") : assert_23 node _T_573 = eq(io.in.a.bits.mask, mask) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_573, UInt<1>(0h1), "") : assert_24 node _T_577 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_577, UInt<1>(0h1), "") : assert_25 node _T_581 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_581 : node _T_582 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_583 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_584 = and(_T_582, _T_583) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_585 = shr(io.in.a.bits.source, 2) node _T_586 = eq(_T_585, UInt<1>(0h0)) node _T_587 = leq(UInt<1>(0h0), uncommonBits_16) node _T_588 = and(_T_586, _T_587) node _T_589 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_590 = and(_T_588, _T_589) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_591 = shr(io.in.a.bits.source, 2) node _T_592 = eq(_T_591, UInt<1>(0h1)) node _T_593 = leq(UInt<1>(0h0), uncommonBits_17) node _T_594 = and(_T_592, _T_593) node _T_595 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_596 = and(_T_594, _T_595) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_597 = shr(io.in.a.bits.source, 2) node _T_598 = eq(_T_597, UInt<2>(0h2)) node _T_599 = leq(UInt<1>(0h0), uncommonBits_18) node _T_600 = and(_T_598, _T_599) node _T_601 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_602 = and(_T_600, _T_601) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_603 = shr(io.in.a.bits.source, 2) node _T_604 = eq(_T_603, UInt<2>(0h3)) node _T_605 = leq(UInt<1>(0h0), uncommonBits_19) node _T_606 = and(_T_604, _T_605) node _T_607 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_608 = and(_T_606, _T_607) node _T_609 = or(_T_590, _T_596) node _T_610 = or(_T_609, _T_602) node _T_611 = or(_T_610, _T_608) node _T_612 = and(_T_584, _T_611) node _T_613 = or(UInt<1>(0h0), _T_612) node _T_614 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_615 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_616 = and(_T_614, _T_615) node _T_617 = or(UInt<1>(0h0), _T_616) node _T_618 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_619 = cvt(_T_618) node _T_620 = and(_T_619, asSInt(UInt<13>(0h1000))) node _T_621 = asSInt(_T_620) node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0))) node _T_623 = and(_T_617, _T_622) node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_626 = and(_T_624, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<14>(0h2000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_634 = cvt(_T_633) node _T_635 = and(_T_634, asSInt(UInt<18>(0h2f000))) node _T_636 = asSInt(_T_635) node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0))) node _T_638 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_639 = cvt(_T_638) node _T_640 = and(_T_639, asSInt(UInt<17>(0h10000))) node _T_641 = asSInt(_T_640) node _T_642 = eq(_T_641, asSInt(UInt<1>(0h0))) node _T_643 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_644 = cvt(_T_643) node _T_645 = and(_T_644, asSInt(UInt<13>(0h1000))) node _T_646 = asSInt(_T_645) node _T_647 = eq(_T_646, asSInt(UInt<1>(0h0))) node _T_648 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_649 = cvt(_T_648) node _T_650 = and(_T_649, asSInt(UInt<17>(0h10000))) node _T_651 = asSInt(_T_650) node _T_652 = eq(_T_651, asSInt(UInt<1>(0h0))) node _T_653 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<27>(0h4000000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<29>(0h10000000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = or(_T_632, _T_637) node _T_669 = or(_T_668, _T_642) node _T_670 = or(_T_669, _T_647) node _T_671 = or(_T_670, _T_652) node _T_672 = or(_T_671, _T_657) node _T_673 = or(_T_672, _T_662) node _T_674 = or(_T_673, _T_667) node _T_675 = and(_T_627, _T_674) node _T_676 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_677 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_678 = cvt(_T_677) node _T_679 = and(_T_678, asSInt(UInt<17>(0h10000))) node _T_680 = asSInt(_T_679) node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0))) node _T_682 = and(_T_676, _T_681) node _T_683 = or(UInt<1>(0h0), _T_623) node _T_684 = or(_T_683, _T_675) node _T_685 = or(_T_684, _T_682) node _T_686 = and(_T_613, _T_685) node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(_T_686, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_686, UInt<1>(0h1), "") : assert_26 node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(source_ok, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_693 = asUInt(reset) node _T_694 = eq(_T_693, UInt<1>(0h0)) when _T_694 : node _T_695 = eq(is_aligned, UInt<1>(0h0)) when _T_695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_696 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(_T_696, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_696, UInt<1>(0h1), "") : assert_29 node _T_700 = eq(io.in.a.bits.mask, mask) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_700, UInt<1>(0h1), "") : assert_30 node _T_704 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_704 : node _T_705 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_706 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_707 = and(_T_705, _T_706) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_708 = shr(io.in.a.bits.source, 2) node _T_709 = eq(_T_708, UInt<1>(0h0)) node _T_710 = leq(UInt<1>(0h0), uncommonBits_20) node _T_711 = and(_T_709, _T_710) node _T_712 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_713 = and(_T_711, _T_712) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_714 = shr(io.in.a.bits.source, 2) node _T_715 = eq(_T_714, UInt<1>(0h1)) node _T_716 = leq(UInt<1>(0h0), uncommonBits_21) node _T_717 = and(_T_715, _T_716) node _T_718 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_719 = and(_T_717, _T_718) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_720 = shr(io.in.a.bits.source, 2) node _T_721 = eq(_T_720, UInt<2>(0h2)) node _T_722 = leq(UInt<1>(0h0), uncommonBits_22) node _T_723 = and(_T_721, _T_722) node _T_724 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_725 = and(_T_723, _T_724) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_726 = shr(io.in.a.bits.source, 2) node _T_727 = eq(_T_726, UInt<2>(0h3)) node _T_728 = leq(UInt<1>(0h0), uncommonBits_23) node _T_729 = and(_T_727, _T_728) node _T_730 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_731 = and(_T_729, _T_730) node _T_732 = or(_T_713, _T_719) node _T_733 = or(_T_732, _T_725) node _T_734 = or(_T_733, _T_731) node _T_735 = and(_T_707, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_738 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_739 = and(_T_737, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = and(_T_740, _T_745) node _T_747 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_748 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<14>(0h2000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_757 = cvt(_T_756) node _T_758 = and(_T_757, asSInt(UInt<18>(0h2f000))) node _T_759 = asSInt(_T_758) node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0))) node _T_761 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_762 = cvt(_T_761) node _T_763 = and(_T_762, asSInt(UInt<17>(0h10000))) node _T_764 = asSInt(_T_763) node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0))) node _T_766 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_772 = cvt(_T_771) node _T_773 = and(_T_772, asSInt(UInt<17>(0h10000))) node _T_774 = asSInt(_T_773) node _T_775 = eq(_T_774, asSInt(UInt<1>(0h0))) node _T_776 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_777 = cvt(_T_776) node _T_778 = and(_T_777, asSInt(UInt<27>(0h4000000))) node _T_779 = asSInt(_T_778) node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0))) node _T_781 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_782 = cvt(_T_781) node _T_783 = and(_T_782, asSInt(UInt<13>(0h1000))) node _T_784 = asSInt(_T_783) node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0))) node _T_786 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_787 = cvt(_T_786) node _T_788 = and(_T_787, asSInt(UInt<29>(0h10000000))) node _T_789 = asSInt(_T_788) node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0))) node _T_791 = or(_T_755, _T_760) node _T_792 = or(_T_791, _T_765) node _T_793 = or(_T_792, _T_770) node _T_794 = or(_T_793, _T_775) node _T_795 = or(_T_794, _T_780) node _T_796 = or(_T_795, _T_785) node _T_797 = or(_T_796, _T_790) node _T_798 = and(_T_750, _T_797) node _T_799 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_800 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<17>(0h10000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = and(_T_799, _T_804) node _T_806 = or(UInt<1>(0h0), _T_746) node _T_807 = or(_T_806, _T_798) node _T_808 = or(_T_807, _T_805) node _T_809 = and(_T_736, _T_808) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_809, UInt<1>(0h1), "") : assert_31 node _T_813 = asUInt(reset) node _T_814 = eq(_T_813, UInt<1>(0h0)) when _T_814 : node _T_815 = eq(source_ok, UInt<1>(0h0)) when _T_815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_816 = asUInt(reset) node _T_817 = eq(_T_816, UInt<1>(0h0)) when _T_817 : node _T_818 = eq(is_aligned, UInt<1>(0h0)) when _T_818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_819 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_820 = asUInt(reset) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(_T_819, UInt<1>(0h0)) when _T_822 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_819, UInt<1>(0h1), "") : assert_34 node _T_823 = not(mask) node _T_824 = and(io.in.a.bits.mask, _T_823) node _T_825 = eq(_T_824, UInt<1>(0h0)) node _T_826 = asUInt(reset) node _T_827 = eq(_T_826, UInt<1>(0h0)) when _T_827 : node _T_828 = eq(_T_825, UInt<1>(0h0)) when _T_828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_825, UInt<1>(0h1), "") : assert_35 node _T_829 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_829 : node _T_830 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_831 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_832 = and(_T_830, _T_831) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_833 = shr(io.in.a.bits.source, 2) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = leq(UInt<1>(0h0), uncommonBits_24) node _T_836 = and(_T_834, _T_835) node _T_837 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_838 = and(_T_836, _T_837) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_839 = shr(io.in.a.bits.source, 2) node _T_840 = eq(_T_839, UInt<1>(0h1)) node _T_841 = leq(UInt<1>(0h0), uncommonBits_25) node _T_842 = and(_T_840, _T_841) node _T_843 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_844 = and(_T_842, _T_843) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_845 = shr(io.in.a.bits.source, 2) node _T_846 = eq(_T_845, UInt<2>(0h2)) node _T_847 = leq(UInt<1>(0h0), uncommonBits_26) node _T_848 = and(_T_846, _T_847) node _T_849 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_850 = and(_T_848, _T_849) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_851 = shr(io.in.a.bits.source, 2) node _T_852 = eq(_T_851, UInt<2>(0h3)) node _T_853 = leq(UInt<1>(0h0), uncommonBits_27) node _T_854 = and(_T_852, _T_853) node _T_855 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_856 = and(_T_854, _T_855) node _T_857 = or(_T_838, _T_844) node _T_858 = or(_T_857, _T_850) node _T_859 = or(_T_858, _T_856) node _T_860 = and(_T_832, _T_859) node _T_861 = or(UInt<1>(0h0), _T_860) node _T_862 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_863 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _T_865 = or(UInt<1>(0h0), _T_864) node _T_866 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_867 = cvt(_T_866) node _T_868 = and(_T_867, asSInt(UInt<14>(0h2000))) node _T_869 = asSInt(_T_868) node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0))) node _T_871 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_872 = cvt(_T_871) node _T_873 = and(_T_872, asSInt(UInt<13>(0h1000))) node _T_874 = asSInt(_T_873) node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0))) node _T_876 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_877 = cvt(_T_876) node _T_878 = and(_T_877, asSInt(UInt<18>(0h2f000))) node _T_879 = asSInt(_T_878) node _T_880 = eq(_T_879, asSInt(UInt<1>(0h0))) node _T_881 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_882 = cvt(_T_881) node _T_883 = and(_T_882, asSInt(UInt<17>(0h10000))) node _T_884 = asSInt(_T_883) node _T_885 = eq(_T_884, asSInt(UInt<1>(0h0))) node _T_886 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_887 = cvt(_T_886) node _T_888 = and(_T_887, asSInt(UInt<13>(0h1000))) node _T_889 = asSInt(_T_888) node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0))) node _T_891 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_892 = cvt(_T_891) node _T_893 = and(_T_892, asSInt(UInt<27>(0h4000000))) node _T_894 = asSInt(_T_893) node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0))) node _T_896 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_897 = cvt(_T_896) node _T_898 = and(_T_897, asSInt(UInt<13>(0h1000))) node _T_899 = asSInt(_T_898) node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0))) node _T_901 = or(_T_870, _T_875) node _T_902 = or(_T_901, _T_880) node _T_903 = or(_T_902, _T_885) node _T_904 = or(_T_903, _T_890) node _T_905 = or(_T_904, _T_895) node _T_906 = or(_T_905, _T_900) node _T_907 = and(_T_865, _T_906) node _T_908 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_909 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<17>(0h10000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = and(_T_908, _T_913) node _T_915 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_916 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_917 = and(_T_915, _T_916) node _T_918 = or(UInt<1>(0h0), _T_917) node _T_919 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<17>(0h10000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<29>(0h10000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = or(_T_923, _T_928) node _T_930 = and(_T_918, _T_929) node _T_931 = or(UInt<1>(0h0), _T_907) node _T_932 = or(_T_931, _T_914) node _T_933 = or(_T_932, _T_930) node _T_934 = and(_T_861, _T_933) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_934, UInt<1>(0h1), "") : assert_36 node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(source_ok, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(is_aligned, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_944 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(_T_944, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_944, UInt<1>(0h1), "") : assert_39 node _T_948 = eq(io.in.a.bits.mask, mask) node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(_T_948, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_948, UInt<1>(0h1), "") : assert_40 node _T_952 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_952 : node _T_953 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_954 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_955 = and(_T_953, _T_954) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_956 = shr(io.in.a.bits.source, 2) node _T_957 = eq(_T_956, UInt<1>(0h0)) node _T_958 = leq(UInt<1>(0h0), uncommonBits_28) node _T_959 = and(_T_957, _T_958) node _T_960 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_961 = and(_T_959, _T_960) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_962 = shr(io.in.a.bits.source, 2) node _T_963 = eq(_T_962, UInt<1>(0h1)) node _T_964 = leq(UInt<1>(0h0), uncommonBits_29) node _T_965 = and(_T_963, _T_964) node _T_966 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_967 = and(_T_965, _T_966) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_968 = shr(io.in.a.bits.source, 2) node _T_969 = eq(_T_968, UInt<2>(0h2)) node _T_970 = leq(UInt<1>(0h0), uncommonBits_30) node _T_971 = and(_T_969, _T_970) node _T_972 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_973 = and(_T_971, _T_972) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_974 = shr(io.in.a.bits.source, 2) node _T_975 = eq(_T_974, UInt<2>(0h3)) node _T_976 = leq(UInt<1>(0h0), uncommonBits_31) node _T_977 = and(_T_975, _T_976) node _T_978 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_979 = and(_T_977, _T_978) node _T_980 = or(_T_961, _T_967) node _T_981 = or(_T_980, _T_973) node _T_982 = or(_T_981, _T_979) node _T_983 = and(_T_955, _T_982) node _T_984 = or(UInt<1>(0h0), _T_983) node _T_985 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_986 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_987 = and(_T_985, _T_986) node _T_988 = or(UInt<1>(0h0), _T_987) node _T_989 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_990 = cvt(_T_989) node _T_991 = and(_T_990, asSInt(UInt<14>(0h2000))) node _T_992 = asSInt(_T_991) node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0))) node _T_994 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_995 = cvt(_T_994) node _T_996 = and(_T_995, asSInt(UInt<13>(0h1000))) node _T_997 = asSInt(_T_996) node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0))) node _T_999 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1000 = cvt(_T_999) node _T_1001 = and(_T_1000, asSInt(UInt<18>(0h2f000))) node _T_1002 = asSInt(_T_1001) node _T_1003 = eq(_T_1002, asSInt(UInt<1>(0h0))) node _T_1004 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1005 = cvt(_T_1004) node _T_1006 = and(_T_1005, asSInt(UInt<17>(0h10000))) node _T_1007 = asSInt(_T_1006) node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0))) node _T_1009 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1010 = cvt(_T_1009) node _T_1011 = and(_T_1010, asSInt(UInt<13>(0h1000))) node _T_1012 = asSInt(_T_1011) node _T_1013 = eq(_T_1012, asSInt(UInt<1>(0h0))) node _T_1014 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1015 = cvt(_T_1014) node _T_1016 = and(_T_1015, asSInt(UInt<27>(0h4000000))) node _T_1017 = asSInt(_T_1016) node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0))) node _T_1019 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1020 = cvt(_T_1019) node _T_1021 = and(_T_1020, asSInt(UInt<13>(0h1000))) node _T_1022 = asSInt(_T_1021) node _T_1023 = eq(_T_1022, asSInt(UInt<1>(0h0))) node _T_1024 = or(_T_993, _T_998) node _T_1025 = or(_T_1024, _T_1003) node _T_1026 = or(_T_1025, _T_1008) node _T_1027 = or(_T_1026, _T_1013) node _T_1028 = or(_T_1027, _T_1018) node _T_1029 = or(_T_1028, _T_1023) node _T_1030 = and(_T_988, _T_1029) node _T_1031 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1032 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1033 = cvt(_T_1032) node _T_1034 = and(_T_1033, asSInt(UInt<17>(0h10000))) node _T_1035 = asSInt(_T_1034) node _T_1036 = eq(_T_1035, asSInt(UInt<1>(0h0))) node _T_1037 = and(_T_1031, _T_1036) node _T_1038 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1039 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_1040 = and(_T_1038, _T_1039) node _T_1041 = or(UInt<1>(0h0), _T_1040) node _T_1042 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1043 = cvt(_T_1042) node _T_1044 = and(_T_1043, asSInt(UInt<17>(0h10000))) node _T_1045 = asSInt(_T_1044) node _T_1046 = eq(_T_1045, asSInt(UInt<1>(0h0))) node _T_1047 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1048 = cvt(_T_1047) node _T_1049 = and(_T_1048, asSInt(UInt<29>(0h10000000))) node _T_1050 = asSInt(_T_1049) node _T_1051 = eq(_T_1050, asSInt(UInt<1>(0h0))) node _T_1052 = or(_T_1046, _T_1051) node _T_1053 = and(_T_1041, _T_1052) node _T_1054 = or(UInt<1>(0h0), _T_1030) node _T_1055 = or(_T_1054, _T_1037) node _T_1056 = or(_T_1055, _T_1053) node _T_1057 = and(_T_984, _T_1056) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_41 node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(source_ok, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(is_aligned, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1067 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_44 node _T_1071 = eq(io.in.a.bits.mask, mask) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_45 node _T_1075 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1075 : node _T_1076 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1077 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1078 = and(_T_1076, _T_1077) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1079 = shr(io.in.a.bits.source, 2) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) node _T_1081 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1084 = and(_T_1082, _T_1083) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1085 = shr(io.in.a.bits.source, 2) node _T_1086 = eq(_T_1085, UInt<1>(0h1)) node _T_1087 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1088 = and(_T_1086, _T_1087) node _T_1089 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1090 = and(_T_1088, _T_1089) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1091 = shr(io.in.a.bits.source, 2) node _T_1092 = eq(_T_1091, UInt<2>(0h2)) node _T_1093 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1094 = and(_T_1092, _T_1093) node _T_1095 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1096 = and(_T_1094, _T_1095) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1097 = shr(io.in.a.bits.source, 2) node _T_1098 = eq(_T_1097, UInt<2>(0h3)) node _T_1099 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1102 = and(_T_1100, _T_1101) node _T_1103 = or(_T_1084, _T_1090) node _T_1104 = or(_T_1103, _T_1096) node _T_1105 = or(_T_1104, _T_1102) node _T_1106 = and(_T_1078, _T_1105) node _T_1107 = or(UInt<1>(0h0), _T_1106) node _T_1108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = or(UInt<1>(0h0), _T_1110) node _T_1112 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1113 = cvt(_T_1112) node _T_1114 = and(_T_1113, asSInt(UInt<13>(0h1000))) node _T_1115 = asSInt(_T_1114) node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0))) node _T_1117 = and(_T_1111, _T_1116) node _T_1118 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1119 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1120 = cvt(_T_1119) node _T_1121 = and(_T_1120, asSInt(UInt<14>(0h2000))) node _T_1122 = asSInt(_T_1121) node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0))) node _T_1124 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1125 = cvt(_T_1124) node _T_1126 = and(_T_1125, asSInt(UInt<17>(0h10000))) node _T_1127 = asSInt(_T_1126) node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0))) node _T_1129 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1130 = cvt(_T_1129) node _T_1131 = and(_T_1130, asSInt(UInt<18>(0h2f000))) node _T_1132 = asSInt(_T_1131) node _T_1133 = eq(_T_1132, asSInt(UInt<1>(0h0))) node _T_1134 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1135 = cvt(_T_1134) node _T_1136 = and(_T_1135, asSInt(UInt<17>(0h10000))) node _T_1137 = asSInt(_T_1136) node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0))) node _T_1139 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1140 = cvt(_T_1139) node _T_1141 = and(_T_1140, asSInt(UInt<13>(0h1000))) node _T_1142 = asSInt(_T_1141) node _T_1143 = eq(_T_1142, asSInt(UInt<1>(0h0))) node _T_1144 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<27>(0h4000000))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1150 = cvt(_T_1149) node _T_1151 = and(_T_1150, asSInt(UInt<13>(0h1000))) node _T_1152 = asSInt(_T_1151) node _T_1153 = eq(_T_1152, asSInt(UInt<1>(0h0))) node _T_1154 = or(_T_1123, _T_1128) node _T_1155 = or(_T_1154, _T_1133) node _T_1156 = or(_T_1155, _T_1138) node _T_1157 = or(_T_1156, _T_1143) node _T_1158 = or(_T_1157, _T_1148) node _T_1159 = or(_T_1158, _T_1153) node _T_1160 = and(_T_1118, _T_1159) node _T_1161 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1162 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1163 = and(_T_1161, _T_1162) node _T_1164 = or(UInt<1>(0h0), _T_1163) node _T_1165 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1166 = cvt(_T_1165) node _T_1167 = and(_T_1166, asSInt(UInt<17>(0h10000))) node _T_1168 = asSInt(_T_1167) node _T_1169 = eq(_T_1168, asSInt(UInt<1>(0h0))) node _T_1170 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1171 = cvt(_T_1170) node _T_1172 = and(_T_1171, asSInt(UInt<29>(0h10000000))) node _T_1173 = asSInt(_T_1172) node _T_1174 = eq(_T_1173, asSInt(UInt<1>(0h0))) node _T_1175 = or(_T_1169, _T_1174) node _T_1176 = and(_T_1164, _T_1175) node _T_1177 = or(UInt<1>(0h0), _T_1117) node _T_1178 = or(_T_1177, _T_1160) node _T_1179 = or(_T_1178, _T_1176) node _T_1180 = and(_T_1107, _T_1179) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_46 node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(source_ok, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(is_aligned, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1190 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_49 node _T_1194 = eq(io.in.a.bits.mask, mask) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_50 node _T_1198 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1202 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_26 = shr(io.in.d.bits.source, 2) node _source_ok_T_27 = eq(_source_ok_T_26, UInt<1>(0h0)) node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28) node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_32 = shr(io.in.d.bits.source, 2) node _source_ok_T_33 = eq(_source_ok_T_32, UInt<1>(0h1)) node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34) node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_38 = shr(io.in.d.bits.source, 2) node _source_ok_T_39 = eq(_source_ok_T_38, UInt<2>(0h2)) node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_44 = shr(io.in.d.bits.source, 2) node _source_ok_T_45 = eq(_source_ok_T_44, UInt<2>(0h3)) node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) wire _source_ok_WIRE_1 : UInt<1>[4] connect _source_ok_WIRE_1[0], _source_ok_T_31 connect _source_ok_WIRE_1[1], _source_ok_T_37 connect _source_ok_WIRE_1[2], _source_ok_T_43 connect _source_ok_WIRE_1[3], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2]) node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3]) node sink_ok = lt(io.in.d.bits.sink, UInt<8>(0h80)) node _T_1206 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1206 : node _T_1207 = asUInt(reset) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) when _T_1208 : node _T_1209 = eq(source_ok_1, UInt<1>(0h0)) when _T_1209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1210 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1211 = asUInt(reset) node _T_1212 = eq(_T_1211, UInt<1>(0h0)) when _T_1212 : node _T_1213 = eq(_T_1210, UInt<1>(0h0)) when _T_1213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1210, UInt<1>(0h1), "") : assert_54 node _T_1214 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1215 = asUInt(reset) node _T_1216 = eq(_T_1215, UInt<1>(0h0)) when _T_1216 : node _T_1217 = eq(_T_1214, UInt<1>(0h0)) when _T_1217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1214, UInt<1>(0h1), "") : assert_55 node _T_1218 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_56 node _T_1222 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1223 = asUInt(reset) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) when _T_1224 : node _T_1225 = eq(_T_1222, UInt<1>(0h0)) when _T_1225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1222, UInt<1>(0h1), "") : assert_57 node _T_1226 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1226 : node _T_1227 = asUInt(reset) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) when _T_1228 : node _T_1229 = eq(source_ok_1, UInt<1>(0h0)) when _T_1229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(sink_ok, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1233 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_60 node _T_1237 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_61 node _T_1241 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(_T_1241, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1241, UInt<1>(0h1), "") : assert_62 node _T_1245 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(_T_1245, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1245, UInt<1>(0h1), "") : assert_63 node _T_1249 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1250 = or(UInt<1>(0h1), _T_1249) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_64 node _T_1254 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1254 : node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(source_ok_1, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1258 = asUInt(reset) node _T_1259 = eq(_T_1258, UInt<1>(0h0)) when _T_1259 : node _T_1260 = eq(sink_ok, UInt<1>(0h0)) when _T_1260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1261 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(_T_1261, UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1261, UInt<1>(0h1), "") : assert_67 node _T_1265 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_68 node _T_1269 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_69 node _T_1273 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1274 = or(_T_1273, io.in.d.bits.corrupt) node _T_1275 = asUInt(reset) node _T_1276 = eq(_T_1275, UInt<1>(0h0)) when _T_1276 : node _T_1277 = eq(_T_1274, UInt<1>(0h0)) when _T_1277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1274, UInt<1>(0h1), "") : assert_70 node _T_1278 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1279 = or(UInt<1>(0h1), _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_71 node _T_1283 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1283 : node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(source_ok_1, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1287 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(_T_1287, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1287, UInt<1>(0h1), "") : assert_73 node _T_1291 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_74 node _T_1295 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1296 = or(UInt<1>(0h1), _T_1295) node _T_1297 = asUInt(reset) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) when _T_1298 : node _T_1299 = eq(_T_1296, UInt<1>(0h0)) when _T_1299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1296, UInt<1>(0h1), "") : assert_75 node _T_1300 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1300 : node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(source_ok_1, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1304 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_77 node _T_1308 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1309 = or(_T_1308, io.in.d.bits.corrupt) node _T_1310 = asUInt(reset) node _T_1311 = eq(_T_1310, UInt<1>(0h0)) when _T_1311 : node _T_1312 = eq(_T_1309, UInt<1>(0h0)) when _T_1312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1309, UInt<1>(0h1), "") : assert_78 node _T_1313 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1314 = or(UInt<1>(0h1), _T_1313) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_79 node _T_1318 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1318 : node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(source_ok_1, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1322 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_81 node _T_1326 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1327 = asUInt(reset) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) when _T_1328 : node _T_1329 = eq(_T_1326, UInt<1>(0h0)) when _T_1329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1326, UInt<1>(0h1), "") : assert_82 node _T_1330 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1331 = or(UInt<1>(0h1), _T_1330) node _T_1332 = asUInt(reset) node _T_1333 = eq(_T_1332, UInt<1>(0h0)) when _T_1333 : node _T_1334 = eq(_T_1331, UInt<1>(0h0)) when _T_1334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1331, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1335 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1336 = asUInt(reset) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(_T_1335, UInt<1>(0h0)) when _T_1338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1335, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1339 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(_T_1339, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1339, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}} connect _WIRE_4.bits.sink, UInt<7>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1343 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(_T_1343, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1343, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1347 = eq(a_first, UInt<1>(0h0)) node _T_1348 = and(io.in.a.valid, _T_1347) when _T_1348 : node _T_1349 = eq(io.in.a.bits.opcode, opcode) node _T_1350 = asUInt(reset) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) when _T_1351 : node _T_1352 = eq(_T_1349, UInt<1>(0h0)) when _T_1352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1349, UInt<1>(0h1), "") : assert_87 node _T_1353 = eq(io.in.a.bits.param, param) node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(_T_1353, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1353, UInt<1>(0h1), "") : assert_88 node _T_1357 = eq(io.in.a.bits.size, size) node _T_1358 = asUInt(reset) node _T_1359 = eq(_T_1358, UInt<1>(0h0)) when _T_1359 : node _T_1360 = eq(_T_1357, UInt<1>(0h0)) when _T_1360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1357, UInt<1>(0h1), "") : assert_89 node _T_1361 = eq(io.in.a.bits.source, source) node _T_1362 = asUInt(reset) node _T_1363 = eq(_T_1362, UInt<1>(0h0)) when _T_1363 : node _T_1364 = eq(_T_1361, UInt<1>(0h0)) when _T_1364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1361, UInt<1>(0h1), "") : assert_90 node _T_1365 = eq(io.in.a.bits.address, address) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_91 node _T_1369 = and(io.in.a.ready, io.in.a.valid) node _T_1370 = and(_T_1369, a_first) when _T_1370 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1371 = eq(d_first, UInt<1>(0h0)) node _T_1372 = and(io.in.d.valid, _T_1371) when _T_1372 : node _T_1373 = eq(io.in.d.bits.opcode, opcode_1) node _T_1374 = asUInt(reset) node _T_1375 = eq(_T_1374, UInt<1>(0h0)) when _T_1375 : node _T_1376 = eq(_T_1373, UInt<1>(0h0)) when _T_1376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1373, UInt<1>(0h1), "") : assert_92 node _T_1377 = eq(io.in.d.bits.param, param_1) node _T_1378 = asUInt(reset) node _T_1379 = eq(_T_1378, UInt<1>(0h0)) when _T_1379 : node _T_1380 = eq(_T_1377, UInt<1>(0h0)) when _T_1380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1377, UInt<1>(0h1), "") : assert_93 node _T_1381 = eq(io.in.d.bits.size, size_1) node _T_1382 = asUInt(reset) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) when _T_1383 : node _T_1384 = eq(_T_1381, UInt<1>(0h0)) when _T_1384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1381, UInt<1>(0h1), "") : assert_94 node _T_1385 = eq(io.in.d.bits.source, source_1) node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(_T_1385, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1385, UInt<1>(0h1), "") : assert_95 node _T_1389 = eq(io.in.d.bits.sink, sink) node _T_1390 = asUInt(reset) node _T_1391 = eq(_T_1390, UInt<1>(0h0)) when _T_1391 : node _T_1392 = eq(_T_1389, UInt<1>(0h0)) when _T_1392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1389, UInt<1>(0h1), "") : assert_96 node _T_1393 = eq(io.in.d.bits.denied, denied) node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(_T_1393, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1393, UInt<1>(0h1), "") : assert_97 node _T_1397 = and(io.in.d.ready, io.in.d.valid) node _T_1398 = and(_T_1397, d_first) when _T_1398 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0) regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<16> connect a_set, UInt<16>(0h0) wire a_set_wo_ready : UInt<16> connect a_set_wo_ready, UInt<16>(0h0) wire a_opcodes_set : UInt<64> connect a_opcodes_set, UInt<64>(0h0) wire a_sizes_set : UInt<128> connect a_sizes_set, UInt<128>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1399 = and(io.in.a.valid, a_first_1) node _T_1400 = and(_T_1399, UInt<1>(0h1)) when _T_1400 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1401 = and(io.in.a.ready, io.in.a.valid) node _T_1402 = and(_T_1401, a_first_1) node _T_1403 = and(_T_1402, UInt<1>(0h1)) when _T_1403 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1404 = dshr(inflight, io.in.a.bits.source) node _T_1405 = bits(_T_1404, 0, 0) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<16> connect d_clr, UInt<16>(0h0) wire d_clr_wo_ready : UInt<16> connect d_clr_wo_ready, UInt<16>(0h0) wire d_opcodes_clr : UInt<64> connect d_opcodes_clr, UInt<64>(0h0) wire d_sizes_clr : UInt<128> connect d_sizes_clr, UInt<128>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1410 = and(io.in.d.valid, d_first_1) node _T_1411 = and(_T_1410, UInt<1>(0h1)) node _T_1412 = eq(d_release_ack, UInt<1>(0h0)) node _T_1413 = and(_T_1411, _T_1412) when _T_1413 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1414 = and(io.in.d.ready, io.in.d.valid) node _T_1415 = and(_T_1414, d_first_1) node _T_1416 = and(_T_1415, UInt<1>(0h1)) node _T_1417 = eq(d_release_ack, UInt<1>(0h0)) node _T_1418 = and(_T_1416, _T_1417) when _T_1418 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1419 = and(io.in.d.valid, d_first_1) node _T_1420 = and(_T_1419, UInt<1>(0h1)) node _T_1421 = eq(d_release_ack, UInt<1>(0h0)) node _T_1422 = and(_T_1420, _T_1421) when _T_1422 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1423 = dshr(inflight, io.in.d.bits.source) node _T_1424 = bits(_T_1423, 0, 0) node _T_1425 = or(_T_1424, same_cycle_resp) node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(_T_1425, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1425, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1429 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1430 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1431 = or(_T_1429, _T_1430) node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(_T_1431, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1431, UInt<1>(0h1), "") : assert_100 node _T_1435 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(_T_1435, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1435, UInt<1>(0h1), "") : assert_101 else : node _T_1439 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1440 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1441 = or(_T_1439, _T_1440) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_102 node _T_1445 = eq(io.in.d.bits.size, a_size_lookup) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_103 node _T_1449 = and(io.in.d.valid, d_first_1) node _T_1450 = and(_T_1449, a_first_1) node _T_1451 = and(_T_1450, io.in.a.valid) node _T_1452 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1453 = and(_T_1451, _T_1452) node _T_1454 = eq(d_release_ack, UInt<1>(0h0)) node _T_1455 = and(_T_1453, _T_1454) when _T_1455 : node _T_1456 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1457 = or(_T_1456, io.in.a.ready) node _T_1458 = asUInt(reset) node _T_1459 = eq(_T_1458, UInt<1>(0h0)) when _T_1459 : node _T_1460 = eq(_T_1457, UInt<1>(0h0)) when _T_1460 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1457, UInt<1>(0h1), "") : assert_104 node _T_1461 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1462 = orr(a_set_wo_ready) node _T_1463 = eq(_T_1462, UInt<1>(0h0)) node _T_1464 = or(_T_1461, _T_1463) node _T_1465 = asUInt(reset) node _T_1466 = eq(_T_1465, UInt<1>(0h0)) when _T_1466 : node _T_1467 = eq(_T_1464, UInt<1>(0h0)) when _T_1467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1464, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_32 node _T_1468 = orr(inflight) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) node _T_1470 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1471 = or(_T_1469, _T_1470) node _T_1472 = lt(watchdog, plusarg_reader.out) node _T_1473 = or(_T_1471, _T_1472) node _T_1474 = asUInt(reset) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) when _T_1475 : node _T_1476 = eq(_T_1473, UInt<1>(0h0)) when _T_1476 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1473, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1477 = and(io.in.a.ready, io.in.a.valid) node _T_1478 = and(io.in.d.ready, io.in.d.valid) node _T_1479 = or(_T_1477, _T_1478) when _T_1479 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<16> connect c_set, UInt<16>(0h0) wire c_set_wo_ready : UInt<16> connect c_set_wo_ready, UInt<16>(0h0) wire c_opcodes_set : UInt<64> connect c_opcodes_set, UInt<64>(0h0) wire c_sizes_set : UInt<128> connect c_sizes_set, UInt<128>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1480 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1481 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1482 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1483 = and(_T_1481, _T_1482) node _T_1484 = and(_T_1480, _T_1483) when _T_1484 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1485 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1486 = and(_T_1485, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1487 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1488 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1489 = and(_T_1487, _T_1488) node _T_1490 = and(_T_1486, _T_1489) when _T_1490 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1491 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1492 = bits(_T_1491, 0, 0) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) node _T_1494 = asUInt(reset) node _T_1495 = eq(_T_1494, UInt<1>(0h0)) when _T_1495 : node _T_1496 = eq(_T_1493, UInt<1>(0h0)) when _T_1496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1493, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<16> connect d_clr_1, UInt<16>(0h0) wire d_clr_wo_ready_1 : UInt<16> connect d_clr_wo_ready_1, UInt<16>(0h0) wire d_opcodes_clr_1 : UInt<64> connect d_opcodes_clr_1, UInt<64>(0h0) wire d_sizes_clr_1 : UInt<128> connect d_sizes_clr_1, UInt<128>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1497 = and(io.in.d.valid, d_first_2) node _T_1498 = and(_T_1497, UInt<1>(0h1)) node _T_1499 = and(_T_1498, d_release_ack_1) when _T_1499 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1500 = and(io.in.d.ready, io.in.d.valid) node _T_1501 = and(_T_1500, d_first_2) node _T_1502 = and(_T_1501, UInt<1>(0h1)) node _T_1503 = and(_T_1502, d_release_ack_1) when _T_1503 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1504 = and(io.in.d.valid, d_first_2) node _T_1505 = and(_T_1504, UInt<1>(0h1)) node _T_1506 = and(_T_1505, d_release_ack_1) when _T_1506 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1507 = dshr(inflight_1, io.in.d.bits.source) node _T_1508 = bits(_T_1507, 0, 0) node _T_1509 = or(_T_1508, same_cycle_resp_1) node _T_1510 = asUInt(reset) node _T_1511 = eq(_T_1510, UInt<1>(0h0)) when _T_1511 : node _T_1512 = eq(_T_1509, UInt<1>(0h0)) when _T_1512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1509, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1513 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1514 = asUInt(reset) node _T_1515 = eq(_T_1514, UInt<1>(0h0)) when _T_1515 : node _T_1516 = eq(_T_1513, UInt<1>(0h0)) when _T_1516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1513, UInt<1>(0h1), "") : assert_109 else : node _T_1517 = eq(io.in.d.bits.size, c_size_lookup) node _T_1518 = asUInt(reset) node _T_1519 = eq(_T_1518, UInt<1>(0h0)) when _T_1519 : node _T_1520 = eq(_T_1517, UInt<1>(0h0)) when _T_1520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1517, UInt<1>(0h1), "") : assert_110 node _T_1521 = and(io.in.d.valid, d_first_2) node _T_1522 = and(_T_1521, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1523 = and(_T_1522, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1524 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1525 = and(_T_1523, _T_1524) node _T_1526 = and(_T_1525, d_release_ack_1) node _T_1527 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1528 = and(_T_1526, _T_1527) when _T_1528 : node _T_1529 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1530 = or(_T_1529, _WIRE_23.ready) node _T_1531 = asUInt(reset) node _T_1532 = eq(_T_1531, UInt<1>(0h0)) when _T_1532 : node _T_1533 = eq(_T_1530, UInt<1>(0h0)) when _T_1533 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1530, UInt<1>(0h1), "") : assert_111 node _T_1534 = orr(c_set_wo_ready) when _T_1534 : node _T_1535 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1536 = asUInt(reset) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) when _T_1537 : node _T_1538 = eq(_T_1535, UInt<1>(0h0)) when _T_1538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1535, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_33 node _T_1539 = orr(inflight_1) node _T_1540 = eq(_T_1539, UInt<1>(0h0)) node _T_1541 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1542 = or(_T_1540, _T_1541) node _T_1543 = lt(watchdog_1, plusarg_reader_1.out) node _T_1544 = or(_T_1542, _T_1543) node _T_1545 = asUInt(reset) node _T_1546 = eq(_T_1545, UInt<1>(0h0)) when _T_1546 : node _T_1547 = eq(_T_1544, UInt<1>(0h0)) when _T_1547 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1544, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1548 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1549 = and(io.in.d.ready, io.in.d.valid) node _T_1550 = or(_T_1548, _T_1549) when _T_1550 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_16( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34] wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34] wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_13 = _source_ok_T_12 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_19 = &_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_25 = _source_ok_T_24 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_25 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_0 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_33 = _source_ok_T_32 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_45 = &_source_ok_T_44; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_51 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _T_1477 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1477; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1477; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1550 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1550; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1550; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1550; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [6:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [15:0] inflight; // @[Monitor.scala:614:27] reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [127:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] a_set; // @[Monitor.scala:626:34] wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [127:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1403 = _T_1477 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1403 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1403 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1403 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1403 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1403 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [15:0] d_clr; // @[Monitor.scala:664:34] wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1449 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1449 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1418 = _T_1550 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1418 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1418 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1418 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [15:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [63:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [127:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [15:0] inflight_1; // @[Monitor.scala:726:35] wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [15:0] d_clr_1; // @[Monitor.scala:774:34] wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1521 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1521 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35] wire _T_1503 = _T_1550 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1503 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1503 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1503 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RenameMapTable : input clock : Clock input reset : Reset output io : { flip map_reqs : { lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst : UInt<6>}[3], map_resps : { prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, stale_pdst : UInt<7>}[3], flip remap_reqs : { ldst : UInt<6>, pdst : UInt<7>, valid : UInt<1>}[3], flip com_remap_reqs : { ldst : UInt<6>, pdst : UInt<7>, valid : UInt<1>}[3], flip ren_br_tags : { valid : UInt<1>, bits : UInt<4>}[4], flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip rollback : UInt<1>} wire _map_table_WIRE : UInt<7>[32] connect _map_table_WIRE[0], UInt<7>(0h0) connect _map_table_WIRE[1], UInt<7>(0h1) connect _map_table_WIRE[2], UInt<7>(0h2) connect _map_table_WIRE[3], UInt<7>(0h3) connect _map_table_WIRE[4], UInt<7>(0h4) connect _map_table_WIRE[5], UInt<7>(0h5) connect _map_table_WIRE[6], UInt<7>(0h6) connect _map_table_WIRE[7], UInt<7>(0h7) connect _map_table_WIRE[8], UInt<7>(0h8) connect _map_table_WIRE[9], UInt<7>(0h9) connect _map_table_WIRE[10], UInt<7>(0ha) connect _map_table_WIRE[11], UInt<7>(0hb) connect _map_table_WIRE[12], UInt<7>(0hc) connect _map_table_WIRE[13], UInt<7>(0hd) connect _map_table_WIRE[14], UInt<7>(0he) connect _map_table_WIRE[15], UInt<7>(0hf) connect _map_table_WIRE[16], UInt<7>(0h10) connect _map_table_WIRE[17], UInt<7>(0h11) connect _map_table_WIRE[18], UInt<7>(0h12) connect _map_table_WIRE[19], UInt<7>(0h13) connect _map_table_WIRE[20], UInt<7>(0h14) connect _map_table_WIRE[21], UInt<7>(0h15) connect _map_table_WIRE[22], UInt<7>(0h16) connect _map_table_WIRE[23], UInt<7>(0h17) connect _map_table_WIRE[24], UInt<7>(0h18) connect _map_table_WIRE[25], UInt<7>(0h19) connect _map_table_WIRE[26], UInt<7>(0h1a) connect _map_table_WIRE[27], UInt<7>(0h1b) connect _map_table_WIRE[28], UInt<7>(0h1c) connect _map_table_WIRE[29], UInt<7>(0h1d) connect _map_table_WIRE[30], UInt<7>(0h1e) connect _map_table_WIRE[31], UInt<7>(0h1f) regreset map_table : UInt<7>[32], clock, reset, _map_table_WIRE wire _com_map_table_WIRE : UInt<7>[32] connect _com_map_table_WIRE[0], UInt<7>(0h0) connect _com_map_table_WIRE[1], UInt<7>(0h1) connect _com_map_table_WIRE[2], UInt<7>(0h2) connect _com_map_table_WIRE[3], UInt<7>(0h3) connect _com_map_table_WIRE[4], UInt<7>(0h4) connect _com_map_table_WIRE[5], UInt<7>(0h5) connect _com_map_table_WIRE[6], UInt<7>(0h6) connect _com_map_table_WIRE[7], UInt<7>(0h7) connect _com_map_table_WIRE[8], UInt<7>(0h8) connect _com_map_table_WIRE[9], UInt<7>(0h9) connect _com_map_table_WIRE[10], UInt<7>(0ha) connect _com_map_table_WIRE[11], UInt<7>(0hb) connect _com_map_table_WIRE[12], UInt<7>(0hc) connect _com_map_table_WIRE[13], UInt<7>(0hd) connect _com_map_table_WIRE[14], UInt<7>(0he) connect _com_map_table_WIRE[15], UInt<7>(0hf) connect _com_map_table_WIRE[16], UInt<7>(0h10) connect _com_map_table_WIRE[17], UInt<7>(0h11) connect _com_map_table_WIRE[18], UInt<7>(0h12) connect _com_map_table_WIRE[19], UInt<7>(0h13) connect _com_map_table_WIRE[20], UInt<7>(0h14) connect _com_map_table_WIRE[21], UInt<7>(0h15) connect _com_map_table_WIRE[22], UInt<7>(0h16) connect _com_map_table_WIRE[23], UInt<7>(0h17) connect _com_map_table_WIRE[24], UInt<7>(0h18) connect _com_map_table_WIRE[25], UInt<7>(0h19) connect _com_map_table_WIRE[26], UInt<7>(0h1a) connect _com_map_table_WIRE[27], UInt<7>(0h1b) connect _com_map_table_WIRE[28], UInt<7>(0h1c) connect _com_map_table_WIRE[29], UInt<7>(0h1d) connect _com_map_table_WIRE[30], UInt<7>(0h1e) connect _com_map_table_WIRE[31], UInt<7>(0h1f) regreset com_map_table : UInt<7>[32], clock, reset, _com_map_table_WIRE reg br_snapshots : UInt<7>[32][16], clock wire remap_table : UInt<7>[32][4] wire com_remap_table : UInt<7>[32][4] node _remap_ldsts_oh_T = dshl(UInt<1>(0h1), io.remap_reqs[0].ldst) node _remap_ldsts_oh_T_1 = mux(io.remap_reqs[0].valid, UInt<32>(0hffffffff), UInt<32>(0h0)) node remap_ldsts_oh_0 = and(_remap_ldsts_oh_T, _remap_ldsts_oh_T_1) node _remap_ldsts_oh_T_2 = dshl(UInt<1>(0h1), io.remap_reqs[1].ldst) node _remap_ldsts_oh_T_3 = mux(io.remap_reqs[1].valid, UInt<32>(0hffffffff), UInt<32>(0h0)) node remap_ldsts_oh_1 = and(_remap_ldsts_oh_T_2, _remap_ldsts_oh_T_3) node _remap_ldsts_oh_T_4 = dshl(UInt<1>(0h1), io.remap_reqs[2].ldst) node _remap_ldsts_oh_T_5 = mux(io.remap_reqs[2].valid, UInt<32>(0hffffffff), UInt<32>(0h0)) node remap_ldsts_oh_2 = and(_remap_ldsts_oh_T_4, _remap_ldsts_oh_T_5) node _com_remap_ldsts_oh_T = dshl(UInt<1>(0h1), io.com_remap_reqs[0].ldst) node _com_remap_ldsts_oh_T_1 = mux(io.com_remap_reqs[0].valid, UInt<32>(0hffffffff), UInt<32>(0h0)) node com_remap_ldsts_oh_0 = and(_com_remap_ldsts_oh_T, _com_remap_ldsts_oh_T_1) node _com_remap_ldsts_oh_T_2 = dshl(UInt<1>(0h1), io.com_remap_reqs[1].ldst) node _com_remap_ldsts_oh_T_3 = mux(io.com_remap_reqs[1].valid, UInt<32>(0hffffffff), UInt<32>(0h0)) node com_remap_ldsts_oh_1 = and(_com_remap_ldsts_oh_T_2, _com_remap_ldsts_oh_T_3) node _com_remap_ldsts_oh_T_4 = dshl(UInt<1>(0h1), io.com_remap_reqs[2].ldst) node _com_remap_ldsts_oh_T_5 = mux(io.com_remap_reqs[2].valid, UInt<32>(0hffffffff), UInt<32>(0h0)) node com_remap_ldsts_oh_2 = and(_com_remap_ldsts_oh_T_4, _com_remap_ldsts_oh_T_5) node _remapped_row_T = bits(remap_ldsts_oh_0, 0, 0) node _remapped_row_T_1 = bits(remap_ldsts_oh_1, 0, 0) node _remapped_row_T_2 = bits(remap_ldsts_oh_2, 0, 0) node remapped_row_1 = mux(_remapped_row_T, io.remap_reqs[0].pdst, map_table[0]) node remapped_row_2 = mux(_remapped_row_T_1, io.remap_reqs[1].pdst, remapped_row_1) node remapped_row_3 = mux(_remapped_row_T_2, io.remap_reqs[2].pdst, remapped_row_2) node _com_remapped_row_T = bits(com_remap_ldsts_oh_0, 0, 0) node _com_remapped_row_T_1 = bits(com_remap_ldsts_oh_1, 0, 0) node _com_remapped_row_T_2 = bits(com_remap_ldsts_oh_2, 0, 0) node com_remapped_row_1 = mux(_com_remapped_row_T, io.com_remap_reqs[0].pdst, com_map_table[0]) node com_remapped_row_2 = mux(_com_remapped_row_T_1, io.com_remap_reqs[1].pdst, com_remapped_row_1) node com_remapped_row_3 = mux(_com_remapped_row_T_2, io.com_remap_reqs[2].pdst, com_remapped_row_2) connect remap_table[0][0], map_table[0] connect com_remap_table[0][0], com_map_table[0] connect remap_table[1][0], remapped_row_1 connect com_remap_table[1][0], com_remapped_row_1 connect remap_table[2][0], remapped_row_2 connect com_remap_table[2][0], com_remapped_row_2 connect remap_table[3][0], remapped_row_3 connect com_remap_table[3][0], com_remapped_row_3 node _remapped_row_T_3 = bits(remap_ldsts_oh_0, 1, 1) node _remapped_row_T_4 = bits(remap_ldsts_oh_1, 1, 1) node _remapped_row_T_5 = bits(remap_ldsts_oh_2, 1, 1) node remapped_row_1_1 = mux(_remapped_row_T_3, io.remap_reqs[0].pdst, map_table[1]) node remapped_row_2_1 = mux(_remapped_row_T_4, io.remap_reqs[1].pdst, remapped_row_1_1) node remapped_row_3_1 = mux(_remapped_row_T_5, io.remap_reqs[2].pdst, remapped_row_2_1) node _com_remapped_row_T_3 = bits(com_remap_ldsts_oh_0, 1, 1) node _com_remapped_row_T_4 = bits(com_remap_ldsts_oh_1, 1, 1) node _com_remapped_row_T_5 = bits(com_remap_ldsts_oh_2, 1, 1) node com_remapped_row_1_1 = mux(_com_remapped_row_T_3, io.com_remap_reqs[0].pdst, com_map_table[1]) node com_remapped_row_2_1 = mux(_com_remapped_row_T_4, io.com_remap_reqs[1].pdst, com_remapped_row_1_1) node com_remapped_row_3_1 = mux(_com_remapped_row_T_5, io.com_remap_reqs[2].pdst, com_remapped_row_2_1) connect remap_table[0][1], map_table[1] connect com_remap_table[0][1], com_map_table[1] connect remap_table[1][1], remapped_row_1_1 connect com_remap_table[1][1], com_remapped_row_1_1 connect remap_table[2][1], remapped_row_2_1 connect com_remap_table[2][1], com_remapped_row_2_1 connect remap_table[3][1], remapped_row_3_1 connect com_remap_table[3][1], com_remapped_row_3_1 node _remapped_row_T_6 = bits(remap_ldsts_oh_0, 2, 2) node _remapped_row_T_7 = bits(remap_ldsts_oh_1, 2, 2) node _remapped_row_T_8 = bits(remap_ldsts_oh_2, 2, 2) node remapped_row_1_2 = mux(_remapped_row_T_6, io.remap_reqs[0].pdst, map_table[2]) node remapped_row_2_2 = mux(_remapped_row_T_7, io.remap_reqs[1].pdst, remapped_row_1_2) node remapped_row_3_2 = mux(_remapped_row_T_8, io.remap_reqs[2].pdst, remapped_row_2_2) node _com_remapped_row_T_6 = bits(com_remap_ldsts_oh_0, 2, 2) node _com_remapped_row_T_7 = bits(com_remap_ldsts_oh_1, 2, 2) node _com_remapped_row_T_8 = bits(com_remap_ldsts_oh_2, 2, 2) node com_remapped_row_1_2 = mux(_com_remapped_row_T_6, io.com_remap_reqs[0].pdst, com_map_table[2]) node com_remapped_row_2_2 = mux(_com_remapped_row_T_7, io.com_remap_reqs[1].pdst, com_remapped_row_1_2) node com_remapped_row_3_2 = mux(_com_remapped_row_T_8, io.com_remap_reqs[2].pdst, com_remapped_row_2_2) connect remap_table[0][2], map_table[2] connect com_remap_table[0][2], com_map_table[2] connect remap_table[1][2], remapped_row_1_2 connect com_remap_table[1][2], com_remapped_row_1_2 connect remap_table[2][2], remapped_row_2_2 connect com_remap_table[2][2], com_remapped_row_2_2 connect remap_table[3][2], remapped_row_3_2 connect com_remap_table[3][2], com_remapped_row_3_2 node _remapped_row_T_9 = bits(remap_ldsts_oh_0, 3, 3) node _remapped_row_T_10 = bits(remap_ldsts_oh_1, 3, 3) node _remapped_row_T_11 = bits(remap_ldsts_oh_2, 3, 3) node remapped_row_1_3 = mux(_remapped_row_T_9, io.remap_reqs[0].pdst, map_table[3]) node remapped_row_2_3 = mux(_remapped_row_T_10, io.remap_reqs[1].pdst, remapped_row_1_3) node remapped_row_3_3 = mux(_remapped_row_T_11, io.remap_reqs[2].pdst, remapped_row_2_3) node _com_remapped_row_T_9 = bits(com_remap_ldsts_oh_0, 3, 3) node _com_remapped_row_T_10 = bits(com_remap_ldsts_oh_1, 3, 3) node _com_remapped_row_T_11 = bits(com_remap_ldsts_oh_2, 3, 3) node com_remapped_row_1_3 = mux(_com_remapped_row_T_9, io.com_remap_reqs[0].pdst, com_map_table[3]) node com_remapped_row_2_3 = mux(_com_remapped_row_T_10, io.com_remap_reqs[1].pdst, com_remapped_row_1_3) node com_remapped_row_3_3 = mux(_com_remapped_row_T_11, io.com_remap_reqs[2].pdst, com_remapped_row_2_3) connect remap_table[0][3], map_table[3] connect com_remap_table[0][3], com_map_table[3] connect remap_table[1][3], remapped_row_1_3 connect com_remap_table[1][3], com_remapped_row_1_3 connect remap_table[2][3], remapped_row_2_3 connect com_remap_table[2][3], com_remapped_row_2_3 connect remap_table[3][3], remapped_row_3_3 connect com_remap_table[3][3], com_remapped_row_3_3 node _remapped_row_T_12 = bits(remap_ldsts_oh_0, 4, 4) node _remapped_row_T_13 = bits(remap_ldsts_oh_1, 4, 4) node _remapped_row_T_14 = bits(remap_ldsts_oh_2, 4, 4) node remapped_row_1_4 = mux(_remapped_row_T_12, io.remap_reqs[0].pdst, map_table[4]) node remapped_row_2_4 = mux(_remapped_row_T_13, io.remap_reqs[1].pdst, remapped_row_1_4) node remapped_row_3_4 = mux(_remapped_row_T_14, io.remap_reqs[2].pdst, remapped_row_2_4) node _com_remapped_row_T_12 = bits(com_remap_ldsts_oh_0, 4, 4) node _com_remapped_row_T_13 = bits(com_remap_ldsts_oh_1, 4, 4) node _com_remapped_row_T_14 = bits(com_remap_ldsts_oh_2, 4, 4) node com_remapped_row_1_4 = mux(_com_remapped_row_T_12, io.com_remap_reqs[0].pdst, com_map_table[4]) node com_remapped_row_2_4 = mux(_com_remapped_row_T_13, io.com_remap_reqs[1].pdst, com_remapped_row_1_4) node com_remapped_row_3_4 = mux(_com_remapped_row_T_14, io.com_remap_reqs[2].pdst, com_remapped_row_2_4) connect remap_table[0][4], map_table[4] connect com_remap_table[0][4], com_map_table[4] connect remap_table[1][4], remapped_row_1_4 connect com_remap_table[1][4], com_remapped_row_1_4 connect remap_table[2][4], remapped_row_2_4 connect com_remap_table[2][4], com_remapped_row_2_4 connect remap_table[3][4], remapped_row_3_4 connect com_remap_table[3][4], com_remapped_row_3_4 node _remapped_row_T_15 = bits(remap_ldsts_oh_0, 5, 5) node _remapped_row_T_16 = bits(remap_ldsts_oh_1, 5, 5) node _remapped_row_T_17 = bits(remap_ldsts_oh_2, 5, 5) node remapped_row_1_5 = mux(_remapped_row_T_15, io.remap_reqs[0].pdst, map_table[5]) node remapped_row_2_5 = mux(_remapped_row_T_16, io.remap_reqs[1].pdst, remapped_row_1_5) node remapped_row_3_5 = mux(_remapped_row_T_17, io.remap_reqs[2].pdst, remapped_row_2_5) node _com_remapped_row_T_15 = bits(com_remap_ldsts_oh_0, 5, 5) node _com_remapped_row_T_16 = bits(com_remap_ldsts_oh_1, 5, 5) node _com_remapped_row_T_17 = bits(com_remap_ldsts_oh_2, 5, 5) node com_remapped_row_1_5 = mux(_com_remapped_row_T_15, io.com_remap_reqs[0].pdst, com_map_table[5]) node com_remapped_row_2_5 = mux(_com_remapped_row_T_16, io.com_remap_reqs[1].pdst, com_remapped_row_1_5) node com_remapped_row_3_5 = mux(_com_remapped_row_T_17, io.com_remap_reqs[2].pdst, com_remapped_row_2_5) connect remap_table[0][5], map_table[5] connect com_remap_table[0][5], com_map_table[5] connect remap_table[1][5], remapped_row_1_5 connect com_remap_table[1][5], com_remapped_row_1_5 connect remap_table[2][5], remapped_row_2_5 connect com_remap_table[2][5], com_remapped_row_2_5 connect remap_table[3][5], remapped_row_3_5 connect com_remap_table[3][5], com_remapped_row_3_5 node _remapped_row_T_18 = bits(remap_ldsts_oh_0, 6, 6) node _remapped_row_T_19 = bits(remap_ldsts_oh_1, 6, 6) node _remapped_row_T_20 = bits(remap_ldsts_oh_2, 6, 6) node remapped_row_1_6 = mux(_remapped_row_T_18, io.remap_reqs[0].pdst, map_table[6]) node remapped_row_2_6 = mux(_remapped_row_T_19, io.remap_reqs[1].pdst, remapped_row_1_6) node remapped_row_3_6 = mux(_remapped_row_T_20, io.remap_reqs[2].pdst, remapped_row_2_6) node _com_remapped_row_T_18 = bits(com_remap_ldsts_oh_0, 6, 6) node _com_remapped_row_T_19 = bits(com_remap_ldsts_oh_1, 6, 6) node _com_remapped_row_T_20 = bits(com_remap_ldsts_oh_2, 6, 6) node com_remapped_row_1_6 = mux(_com_remapped_row_T_18, io.com_remap_reqs[0].pdst, com_map_table[6]) node com_remapped_row_2_6 = mux(_com_remapped_row_T_19, io.com_remap_reqs[1].pdst, com_remapped_row_1_6) node com_remapped_row_3_6 = mux(_com_remapped_row_T_20, io.com_remap_reqs[2].pdst, com_remapped_row_2_6) connect remap_table[0][6], map_table[6] connect com_remap_table[0][6], com_map_table[6] connect remap_table[1][6], remapped_row_1_6 connect com_remap_table[1][6], com_remapped_row_1_6 connect remap_table[2][6], remapped_row_2_6 connect com_remap_table[2][6], com_remapped_row_2_6 connect remap_table[3][6], remapped_row_3_6 connect com_remap_table[3][6], com_remapped_row_3_6 node _remapped_row_T_21 = bits(remap_ldsts_oh_0, 7, 7) node _remapped_row_T_22 = bits(remap_ldsts_oh_1, 7, 7) node _remapped_row_T_23 = bits(remap_ldsts_oh_2, 7, 7) node remapped_row_1_7 = mux(_remapped_row_T_21, io.remap_reqs[0].pdst, map_table[7]) node remapped_row_2_7 = mux(_remapped_row_T_22, io.remap_reqs[1].pdst, remapped_row_1_7) node remapped_row_3_7 = mux(_remapped_row_T_23, io.remap_reqs[2].pdst, remapped_row_2_7) node _com_remapped_row_T_21 = bits(com_remap_ldsts_oh_0, 7, 7) node _com_remapped_row_T_22 = bits(com_remap_ldsts_oh_1, 7, 7) node _com_remapped_row_T_23 = bits(com_remap_ldsts_oh_2, 7, 7) node com_remapped_row_1_7 = mux(_com_remapped_row_T_21, io.com_remap_reqs[0].pdst, com_map_table[7]) node com_remapped_row_2_7 = mux(_com_remapped_row_T_22, io.com_remap_reqs[1].pdst, com_remapped_row_1_7) node com_remapped_row_3_7 = mux(_com_remapped_row_T_23, io.com_remap_reqs[2].pdst, com_remapped_row_2_7) connect remap_table[0][7], map_table[7] connect com_remap_table[0][7], com_map_table[7] connect remap_table[1][7], remapped_row_1_7 connect com_remap_table[1][7], com_remapped_row_1_7 connect remap_table[2][7], remapped_row_2_7 connect com_remap_table[2][7], com_remapped_row_2_7 connect remap_table[3][7], remapped_row_3_7 connect com_remap_table[3][7], com_remapped_row_3_7 node _remapped_row_T_24 = bits(remap_ldsts_oh_0, 8, 8) node _remapped_row_T_25 = bits(remap_ldsts_oh_1, 8, 8) node _remapped_row_T_26 = bits(remap_ldsts_oh_2, 8, 8) node remapped_row_1_8 = mux(_remapped_row_T_24, io.remap_reqs[0].pdst, map_table[8]) node remapped_row_2_8 = mux(_remapped_row_T_25, io.remap_reqs[1].pdst, remapped_row_1_8) node remapped_row_3_8 = mux(_remapped_row_T_26, io.remap_reqs[2].pdst, remapped_row_2_8) node _com_remapped_row_T_24 = bits(com_remap_ldsts_oh_0, 8, 8) node _com_remapped_row_T_25 = bits(com_remap_ldsts_oh_1, 8, 8) node _com_remapped_row_T_26 = bits(com_remap_ldsts_oh_2, 8, 8) node com_remapped_row_1_8 = mux(_com_remapped_row_T_24, io.com_remap_reqs[0].pdst, com_map_table[8]) node com_remapped_row_2_8 = mux(_com_remapped_row_T_25, io.com_remap_reqs[1].pdst, com_remapped_row_1_8) node com_remapped_row_3_8 = mux(_com_remapped_row_T_26, io.com_remap_reqs[2].pdst, com_remapped_row_2_8) connect remap_table[0][8], map_table[8] connect com_remap_table[0][8], com_map_table[8] connect remap_table[1][8], remapped_row_1_8 connect com_remap_table[1][8], com_remapped_row_1_8 connect remap_table[2][8], remapped_row_2_8 connect com_remap_table[2][8], com_remapped_row_2_8 connect remap_table[3][8], remapped_row_3_8 connect com_remap_table[3][8], com_remapped_row_3_8 node _remapped_row_T_27 = bits(remap_ldsts_oh_0, 9, 9) node _remapped_row_T_28 = bits(remap_ldsts_oh_1, 9, 9) node _remapped_row_T_29 = bits(remap_ldsts_oh_2, 9, 9) node remapped_row_1_9 = mux(_remapped_row_T_27, io.remap_reqs[0].pdst, map_table[9]) node remapped_row_2_9 = mux(_remapped_row_T_28, io.remap_reqs[1].pdst, remapped_row_1_9) node remapped_row_3_9 = mux(_remapped_row_T_29, io.remap_reqs[2].pdst, remapped_row_2_9) node _com_remapped_row_T_27 = bits(com_remap_ldsts_oh_0, 9, 9) node _com_remapped_row_T_28 = bits(com_remap_ldsts_oh_1, 9, 9) node _com_remapped_row_T_29 = bits(com_remap_ldsts_oh_2, 9, 9) node com_remapped_row_1_9 = mux(_com_remapped_row_T_27, io.com_remap_reqs[0].pdst, com_map_table[9]) node com_remapped_row_2_9 = mux(_com_remapped_row_T_28, io.com_remap_reqs[1].pdst, com_remapped_row_1_9) node com_remapped_row_3_9 = mux(_com_remapped_row_T_29, io.com_remap_reqs[2].pdst, com_remapped_row_2_9) connect remap_table[0][9], map_table[9] connect com_remap_table[0][9], com_map_table[9] connect remap_table[1][9], remapped_row_1_9 connect com_remap_table[1][9], com_remapped_row_1_9 connect remap_table[2][9], remapped_row_2_9 connect com_remap_table[2][9], com_remapped_row_2_9 connect remap_table[3][9], remapped_row_3_9 connect com_remap_table[3][9], com_remapped_row_3_9 node _remapped_row_T_30 = bits(remap_ldsts_oh_0, 10, 10) node _remapped_row_T_31 = bits(remap_ldsts_oh_1, 10, 10) node _remapped_row_T_32 = bits(remap_ldsts_oh_2, 10, 10) node remapped_row_1_10 = mux(_remapped_row_T_30, io.remap_reqs[0].pdst, map_table[10]) node remapped_row_2_10 = mux(_remapped_row_T_31, io.remap_reqs[1].pdst, remapped_row_1_10) node remapped_row_3_10 = mux(_remapped_row_T_32, io.remap_reqs[2].pdst, remapped_row_2_10) node _com_remapped_row_T_30 = bits(com_remap_ldsts_oh_0, 10, 10) node _com_remapped_row_T_31 = bits(com_remap_ldsts_oh_1, 10, 10) node _com_remapped_row_T_32 = bits(com_remap_ldsts_oh_2, 10, 10) node com_remapped_row_1_10 = mux(_com_remapped_row_T_30, io.com_remap_reqs[0].pdst, com_map_table[10]) node com_remapped_row_2_10 = mux(_com_remapped_row_T_31, io.com_remap_reqs[1].pdst, com_remapped_row_1_10) node com_remapped_row_3_10 = mux(_com_remapped_row_T_32, io.com_remap_reqs[2].pdst, com_remapped_row_2_10) connect remap_table[0][10], map_table[10] connect com_remap_table[0][10], com_map_table[10] connect remap_table[1][10], remapped_row_1_10 connect com_remap_table[1][10], com_remapped_row_1_10 connect remap_table[2][10], remapped_row_2_10 connect com_remap_table[2][10], com_remapped_row_2_10 connect remap_table[3][10], remapped_row_3_10 connect com_remap_table[3][10], com_remapped_row_3_10 node _remapped_row_T_33 = bits(remap_ldsts_oh_0, 11, 11) node _remapped_row_T_34 = bits(remap_ldsts_oh_1, 11, 11) node _remapped_row_T_35 = bits(remap_ldsts_oh_2, 11, 11) node remapped_row_1_11 = mux(_remapped_row_T_33, io.remap_reqs[0].pdst, map_table[11]) node remapped_row_2_11 = mux(_remapped_row_T_34, io.remap_reqs[1].pdst, remapped_row_1_11) node remapped_row_3_11 = mux(_remapped_row_T_35, io.remap_reqs[2].pdst, remapped_row_2_11) node _com_remapped_row_T_33 = bits(com_remap_ldsts_oh_0, 11, 11) node _com_remapped_row_T_34 = bits(com_remap_ldsts_oh_1, 11, 11) node _com_remapped_row_T_35 = bits(com_remap_ldsts_oh_2, 11, 11) node com_remapped_row_1_11 = mux(_com_remapped_row_T_33, io.com_remap_reqs[0].pdst, com_map_table[11]) node com_remapped_row_2_11 = mux(_com_remapped_row_T_34, io.com_remap_reqs[1].pdst, com_remapped_row_1_11) node com_remapped_row_3_11 = mux(_com_remapped_row_T_35, io.com_remap_reqs[2].pdst, com_remapped_row_2_11) connect remap_table[0][11], map_table[11] connect com_remap_table[0][11], com_map_table[11] connect remap_table[1][11], remapped_row_1_11 connect com_remap_table[1][11], com_remapped_row_1_11 connect remap_table[2][11], remapped_row_2_11 connect com_remap_table[2][11], com_remapped_row_2_11 connect remap_table[3][11], remapped_row_3_11 connect com_remap_table[3][11], com_remapped_row_3_11 node _remapped_row_T_36 = bits(remap_ldsts_oh_0, 12, 12) node _remapped_row_T_37 = bits(remap_ldsts_oh_1, 12, 12) node _remapped_row_T_38 = bits(remap_ldsts_oh_2, 12, 12) node remapped_row_1_12 = mux(_remapped_row_T_36, io.remap_reqs[0].pdst, map_table[12]) node remapped_row_2_12 = mux(_remapped_row_T_37, io.remap_reqs[1].pdst, remapped_row_1_12) node remapped_row_3_12 = mux(_remapped_row_T_38, io.remap_reqs[2].pdst, remapped_row_2_12) node _com_remapped_row_T_36 = bits(com_remap_ldsts_oh_0, 12, 12) node _com_remapped_row_T_37 = bits(com_remap_ldsts_oh_1, 12, 12) node _com_remapped_row_T_38 = bits(com_remap_ldsts_oh_2, 12, 12) node com_remapped_row_1_12 = mux(_com_remapped_row_T_36, io.com_remap_reqs[0].pdst, com_map_table[12]) node com_remapped_row_2_12 = mux(_com_remapped_row_T_37, io.com_remap_reqs[1].pdst, com_remapped_row_1_12) node com_remapped_row_3_12 = mux(_com_remapped_row_T_38, io.com_remap_reqs[2].pdst, com_remapped_row_2_12) connect remap_table[0][12], map_table[12] connect com_remap_table[0][12], com_map_table[12] connect remap_table[1][12], remapped_row_1_12 connect com_remap_table[1][12], com_remapped_row_1_12 connect remap_table[2][12], remapped_row_2_12 connect com_remap_table[2][12], com_remapped_row_2_12 connect remap_table[3][12], remapped_row_3_12 connect com_remap_table[3][12], com_remapped_row_3_12 node _remapped_row_T_39 = bits(remap_ldsts_oh_0, 13, 13) node _remapped_row_T_40 = bits(remap_ldsts_oh_1, 13, 13) node _remapped_row_T_41 = bits(remap_ldsts_oh_2, 13, 13) node remapped_row_1_13 = mux(_remapped_row_T_39, io.remap_reqs[0].pdst, map_table[13]) node remapped_row_2_13 = mux(_remapped_row_T_40, io.remap_reqs[1].pdst, remapped_row_1_13) node remapped_row_3_13 = mux(_remapped_row_T_41, io.remap_reqs[2].pdst, remapped_row_2_13) node _com_remapped_row_T_39 = bits(com_remap_ldsts_oh_0, 13, 13) node _com_remapped_row_T_40 = bits(com_remap_ldsts_oh_1, 13, 13) node _com_remapped_row_T_41 = bits(com_remap_ldsts_oh_2, 13, 13) node com_remapped_row_1_13 = mux(_com_remapped_row_T_39, io.com_remap_reqs[0].pdst, com_map_table[13]) node com_remapped_row_2_13 = mux(_com_remapped_row_T_40, io.com_remap_reqs[1].pdst, com_remapped_row_1_13) node com_remapped_row_3_13 = mux(_com_remapped_row_T_41, io.com_remap_reqs[2].pdst, com_remapped_row_2_13) connect remap_table[0][13], map_table[13] connect com_remap_table[0][13], com_map_table[13] connect remap_table[1][13], remapped_row_1_13 connect com_remap_table[1][13], com_remapped_row_1_13 connect remap_table[2][13], remapped_row_2_13 connect com_remap_table[2][13], com_remapped_row_2_13 connect remap_table[3][13], remapped_row_3_13 connect com_remap_table[3][13], com_remapped_row_3_13 node _remapped_row_T_42 = bits(remap_ldsts_oh_0, 14, 14) node _remapped_row_T_43 = bits(remap_ldsts_oh_1, 14, 14) node _remapped_row_T_44 = bits(remap_ldsts_oh_2, 14, 14) node remapped_row_1_14 = mux(_remapped_row_T_42, io.remap_reqs[0].pdst, map_table[14]) node remapped_row_2_14 = mux(_remapped_row_T_43, io.remap_reqs[1].pdst, remapped_row_1_14) node remapped_row_3_14 = mux(_remapped_row_T_44, io.remap_reqs[2].pdst, remapped_row_2_14) node _com_remapped_row_T_42 = bits(com_remap_ldsts_oh_0, 14, 14) node _com_remapped_row_T_43 = bits(com_remap_ldsts_oh_1, 14, 14) node _com_remapped_row_T_44 = bits(com_remap_ldsts_oh_2, 14, 14) node com_remapped_row_1_14 = mux(_com_remapped_row_T_42, io.com_remap_reqs[0].pdst, com_map_table[14]) node com_remapped_row_2_14 = mux(_com_remapped_row_T_43, io.com_remap_reqs[1].pdst, com_remapped_row_1_14) node com_remapped_row_3_14 = mux(_com_remapped_row_T_44, io.com_remap_reqs[2].pdst, com_remapped_row_2_14) connect remap_table[0][14], map_table[14] connect com_remap_table[0][14], com_map_table[14] connect remap_table[1][14], remapped_row_1_14 connect com_remap_table[1][14], com_remapped_row_1_14 connect remap_table[2][14], remapped_row_2_14 connect com_remap_table[2][14], com_remapped_row_2_14 connect remap_table[3][14], remapped_row_3_14 connect com_remap_table[3][14], com_remapped_row_3_14 node _remapped_row_T_45 = bits(remap_ldsts_oh_0, 15, 15) node _remapped_row_T_46 = bits(remap_ldsts_oh_1, 15, 15) node _remapped_row_T_47 = bits(remap_ldsts_oh_2, 15, 15) node remapped_row_1_15 = mux(_remapped_row_T_45, io.remap_reqs[0].pdst, map_table[15]) node remapped_row_2_15 = mux(_remapped_row_T_46, io.remap_reqs[1].pdst, remapped_row_1_15) node remapped_row_3_15 = mux(_remapped_row_T_47, io.remap_reqs[2].pdst, remapped_row_2_15) node _com_remapped_row_T_45 = bits(com_remap_ldsts_oh_0, 15, 15) node _com_remapped_row_T_46 = bits(com_remap_ldsts_oh_1, 15, 15) node _com_remapped_row_T_47 = bits(com_remap_ldsts_oh_2, 15, 15) node com_remapped_row_1_15 = mux(_com_remapped_row_T_45, io.com_remap_reqs[0].pdst, com_map_table[15]) node com_remapped_row_2_15 = mux(_com_remapped_row_T_46, io.com_remap_reqs[1].pdst, com_remapped_row_1_15) node com_remapped_row_3_15 = mux(_com_remapped_row_T_47, io.com_remap_reqs[2].pdst, com_remapped_row_2_15) connect remap_table[0][15], map_table[15] connect com_remap_table[0][15], com_map_table[15] connect remap_table[1][15], remapped_row_1_15 connect com_remap_table[1][15], com_remapped_row_1_15 connect remap_table[2][15], remapped_row_2_15 connect com_remap_table[2][15], com_remapped_row_2_15 connect remap_table[3][15], remapped_row_3_15 connect com_remap_table[3][15], com_remapped_row_3_15 node _remapped_row_T_48 = bits(remap_ldsts_oh_0, 16, 16) node _remapped_row_T_49 = bits(remap_ldsts_oh_1, 16, 16) node _remapped_row_T_50 = bits(remap_ldsts_oh_2, 16, 16) node remapped_row_1_16 = mux(_remapped_row_T_48, io.remap_reqs[0].pdst, map_table[16]) node remapped_row_2_16 = mux(_remapped_row_T_49, io.remap_reqs[1].pdst, remapped_row_1_16) node remapped_row_3_16 = mux(_remapped_row_T_50, io.remap_reqs[2].pdst, remapped_row_2_16) node _com_remapped_row_T_48 = bits(com_remap_ldsts_oh_0, 16, 16) node _com_remapped_row_T_49 = bits(com_remap_ldsts_oh_1, 16, 16) node _com_remapped_row_T_50 = bits(com_remap_ldsts_oh_2, 16, 16) node com_remapped_row_1_16 = mux(_com_remapped_row_T_48, io.com_remap_reqs[0].pdst, com_map_table[16]) node com_remapped_row_2_16 = mux(_com_remapped_row_T_49, io.com_remap_reqs[1].pdst, com_remapped_row_1_16) node com_remapped_row_3_16 = mux(_com_remapped_row_T_50, io.com_remap_reqs[2].pdst, com_remapped_row_2_16) connect remap_table[0][16], map_table[16] connect com_remap_table[0][16], com_map_table[16] connect remap_table[1][16], remapped_row_1_16 connect com_remap_table[1][16], com_remapped_row_1_16 connect remap_table[2][16], remapped_row_2_16 connect com_remap_table[2][16], com_remapped_row_2_16 connect remap_table[3][16], remapped_row_3_16 connect com_remap_table[3][16], com_remapped_row_3_16 node _remapped_row_T_51 = bits(remap_ldsts_oh_0, 17, 17) node _remapped_row_T_52 = bits(remap_ldsts_oh_1, 17, 17) node _remapped_row_T_53 = bits(remap_ldsts_oh_2, 17, 17) node remapped_row_1_17 = mux(_remapped_row_T_51, io.remap_reqs[0].pdst, map_table[17]) node remapped_row_2_17 = mux(_remapped_row_T_52, io.remap_reqs[1].pdst, remapped_row_1_17) node remapped_row_3_17 = mux(_remapped_row_T_53, io.remap_reqs[2].pdst, remapped_row_2_17) node _com_remapped_row_T_51 = bits(com_remap_ldsts_oh_0, 17, 17) node _com_remapped_row_T_52 = bits(com_remap_ldsts_oh_1, 17, 17) node _com_remapped_row_T_53 = bits(com_remap_ldsts_oh_2, 17, 17) node com_remapped_row_1_17 = mux(_com_remapped_row_T_51, io.com_remap_reqs[0].pdst, com_map_table[17]) node com_remapped_row_2_17 = mux(_com_remapped_row_T_52, io.com_remap_reqs[1].pdst, com_remapped_row_1_17) node com_remapped_row_3_17 = mux(_com_remapped_row_T_53, io.com_remap_reqs[2].pdst, com_remapped_row_2_17) connect remap_table[0][17], map_table[17] connect com_remap_table[0][17], com_map_table[17] connect remap_table[1][17], remapped_row_1_17 connect com_remap_table[1][17], com_remapped_row_1_17 connect remap_table[2][17], remapped_row_2_17 connect com_remap_table[2][17], com_remapped_row_2_17 connect remap_table[3][17], remapped_row_3_17 connect com_remap_table[3][17], com_remapped_row_3_17 node _remapped_row_T_54 = bits(remap_ldsts_oh_0, 18, 18) node _remapped_row_T_55 = bits(remap_ldsts_oh_1, 18, 18) node _remapped_row_T_56 = bits(remap_ldsts_oh_2, 18, 18) node remapped_row_1_18 = mux(_remapped_row_T_54, io.remap_reqs[0].pdst, map_table[18]) node remapped_row_2_18 = mux(_remapped_row_T_55, io.remap_reqs[1].pdst, remapped_row_1_18) node remapped_row_3_18 = mux(_remapped_row_T_56, io.remap_reqs[2].pdst, remapped_row_2_18) node _com_remapped_row_T_54 = bits(com_remap_ldsts_oh_0, 18, 18) node _com_remapped_row_T_55 = bits(com_remap_ldsts_oh_1, 18, 18) node _com_remapped_row_T_56 = bits(com_remap_ldsts_oh_2, 18, 18) node com_remapped_row_1_18 = mux(_com_remapped_row_T_54, io.com_remap_reqs[0].pdst, com_map_table[18]) node com_remapped_row_2_18 = mux(_com_remapped_row_T_55, io.com_remap_reqs[1].pdst, com_remapped_row_1_18) node com_remapped_row_3_18 = mux(_com_remapped_row_T_56, io.com_remap_reqs[2].pdst, com_remapped_row_2_18) connect remap_table[0][18], map_table[18] connect com_remap_table[0][18], com_map_table[18] connect remap_table[1][18], remapped_row_1_18 connect com_remap_table[1][18], com_remapped_row_1_18 connect remap_table[2][18], remapped_row_2_18 connect com_remap_table[2][18], com_remapped_row_2_18 connect remap_table[3][18], remapped_row_3_18 connect com_remap_table[3][18], com_remapped_row_3_18 node _remapped_row_T_57 = bits(remap_ldsts_oh_0, 19, 19) node _remapped_row_T_58 = bits(remap_ldsts_oh_1, 19, 19) node _remapped_row_T_59 = bits(remap_ldsts_oh_2, 19, 19) node remapped_row_1_19 = mux(_remapped_row_T_57, io.remap_reqs[0].pdst, map_table[19]) node remapped_row_2_19 = mux(_remapped_row_T_58, io.remap_reqs[1].pdst, remapped_row_1_19) node remapped_row_3_19 = mux(_remapped_row_T_59, io.remap_reqs[2].pdst, remapped_row_2_19) node _com_remapped_row_T_57 = bits(com_remap_ldsts_oh_0, 19, 19) node _com_remapped_row_T_58 = bits(com_remap_ldsts_oh_1, 19, 19) node _com_remapped_row_T_59 = bits(com_remap_ldsts_oh_2, 19, 19) node com_remapped_row_1_19 = mux(_com_remapped_row_T_57, io.com_remap_reqs[0].pdst, com_map_table[19]) node com_remapped_row_2_19 = mux(_com_remapped_row_T_58, io.com_remap_reqs[1].pdst, com_remapped_row_1_19) node com_remapped_row_3_19 = mux(_com_remapped_row_T_59, io.com_remap_reqs[2].pdst, com_remapped_row_2_19) connect remap_table[0][19], map_table[19] connect com_remap_table[0][19], com_map_table[19] connect remap_table[1][19], remapped_row_1_19 connect com_remap_table[1][19], com_remapped_row_1_19 connect remap_table[2][19], remapped_row_2_19 connect com_remap_table[2][19], com_remapped_row_2_19 connect remap_table[3][19], remapped_row_3_19 connect com_remap_table[3][19], com_remapped_row_3_19 node _remapped_row_T_60 = bits(remap_ldsts_oh_0, 20, 20) node _remapped_row_T_61 = bits(remap_ldsts_oh_1, 20, 20) node _remapped_row_T_62 = bits(remap_ldsts_oh_2, 20, 20) node remapped_row_1_20 = mux(_remapped_row_T_60, io.remap_reqs[0].pdst, map_table[20]) node remapped_row_2_20 = mux(_remapped_row_T_61, io.remap_reqs[1].pdst, remapped_row_1_20) node remapped_row_3_20 = mux(_remapped_row_T_62, io.remap_reqs[2].pdst, remapped_row_2_20) node _com_remapped_row_T_60 = bits(com_remap_ldsts_oh_0, 20, 20) node _com_remapped_row_T_61 = bits(com_remap_ldsts_oh_1, 20, 20) node _com_remapped_row_T_62 = bits(com_remap_ldsts_oh_2, 20, 20) node com_remapped_row_1_20 = mux(_com_remapped_row_T_60, io.com_remap_reqs[0].pdst, com_map_table[20]) node com_remapped_row_2_20 = mux(_com_remapped_row_T_61, io.com_remap_reqs[1].pdst, com_remapped_row_1_20) node com_remapped_row_3_20 = mux(_com_remapped_row_T_62, io.com_remap_reqs[2].pdst, com_remapped_row_2_20) connect remap_table[0][20], map_table[20] connect com_remap_table[0][20], com_map_table[20] connect remap_table[1][20], remapped_row_1_20 connect com_remap_table[1][20], com_remapped_row_1_20 connect remap_table[2][20], remapped_row_2_20 connect com_remap_table[2][20], com_remapped_row_2_20 connect remap_table[3][20], remapped_row_3_20 connect com_remap_table[3][20], com_remapped_row_3_20 node _remapped_row_T_63 = bits(remap_ldsts_oh_0, 21, 21) node _remapped_row_T_64 = bits(remap_ldsts_oh_1, 21, 21) node _remapped_row_T_65 = bits(remap_ldsts_oh_2, 21, 21) node remapped_row_1_21 = mux(_remapped_row_T_63, io.remap_reqs[0].pdst, map_table[21]) node remapped_row_2_21 = mux(_remapped_row_T_64, io.remap_reqs[1].pdst, remapped_row_1_21) node remapped_row_3_21 = mux(_remapped_row_T_65, io.remap_reqs[2].pdst, remapped_row_2_21) node _com_remapped_row_T_63 = bits(com_remap_ldsts_oh_0, 21, 21) node _com_remapped_row_T_64 = bits(com_remap_ldsts_oh_1, 21, 21) node _com_remapped_row_T_65 = bits(com_remap_ldsts_oh_2, 21, 21) node com_remapped_row_1_21 = mux(_com_remapped_row_T_63, io.com_remap_reqs[0].pdst, com_map_table[21]) node com_remapped_row_2_21 = mux(_com_remapped_row_T_64, io.com_remap_reqs[1].pdst, com_remapped_row_1_21) node com_remapped_row_3_21 = mux(_com_remapped_row_T_65, io.com_remap_reqs[2].pdst, com_remapped_row_2_21) connect remap_table[0][21], map_table[21] connect com_remap_table[0][21], com_map_table[21] connect remap_table[1][21], remapped_row_1_21 connect com_remap_table[1][21], com_remapped_row_1_21 connect remap_table[2][21], remapped_row_2_21 connect com_remap_table[2][21], com_remapped_row_2_21 connect remap_table[3][21], remapped_row_3_21 connect com_remap_table[3][21], com_remapped_row_3_21 node _remapped_row_T_66 = bits(remap_ldsts_oh_0, 22, 22) node _remapped_row_T_67 = bits(remap_ldsts_oh_1, 22, 22) node _remapped_row_T_68 = bits(remap_ldsts_oh_2, 22, 22) node remapped_row_1_22 = mux(_remapped_row_T_66, io.remap_reqs[0].pdst, map_table[22]) node remapped_row_2_22 = mux(_remapped_row_T_67, io.remap_reqs[1].pdst, remapped_row_1_22) node remapped_row_3_22 = mux(_remapped_row_T_68, io.remap_reqs[2].pdst, remapped_row_2_22) node _com_remapped_row_T_66 = bits(com_remap_ldsts_oh_0, 22, 22) node _com_remapped_row_T_67 = bits(com_remap_ldsts_oh_1, 22, 22) node _com_remapped_row_T_68 = bits(com_remap_ldsts_oh_2, 22, 22) node com_remapped_row_1_22 = mux(_com_remapped_row_T_66, io.com_remap_reqs[0].pdst, com_map_table[22]) node com_remapped_row_2_22 = mux(_com_remapped_row_T_67, io.com_remap_reqs[1].pdst, com_remapped_row_1_22) node com_remapped_row_3_22 = mux(_com_remapped_row_T_68, io.com_remap_reqs[2].pdst, com_remapped_row_2_22) connect remap_table[0][22], map_table[22] connect com_remap_table[0][22], com_map_table[22] connect remap_table[1][22], remapped_row_1_22 connect com_remap_table[1][22], com_remapped_row_1_22 connect remap_table[2][22], remapped_row_2_22 connect com_remap_table[2][22], com_remapped_row_2_22 connect remap_table[3][22], remapped_row_3_22 connect com_remap_table[3][22], com_remapped_row_3_22 node _remapped_row_T_69 = bits(remap_ldsts_oh_0, 23, 23) node _remapped_row_T_70 = bits(remap_ldsts_oh_1, 23, 23) node _remapped_row_T_71 = bits(remap_ldsts_oh_2, 23, 23) node remapped_row_1_23 = mux(_remapped_row_T_69, io.remap_reqs[0].pdst, map_table[23]) node remapped_row_2_23 = mux(_remapped_row_T_70, io.remap_reqs[1].pdst, remapped_row_1_23) node remapped_row_3_23 = mux(_remapped_row_T_71, io.remap_reqs[2].pdst, remapped_row_2_23) node _com_remapped_row_T_69 = bits(com_remap_ldsts_oh_0, 23, 23) node _com_remapped_row_T_70 = bits(com_remap_ldsts_oh_1, 23, 23) node _com_remapped_row_T_71 = bits(com_remap_ldsts_oh_2, 23, 23) node com_remapped_row_1_23 = mux(_com_remapped_row_T_69, io.com_remap_reqs[0].pdst, com_map_table[23]) node com_remapped_row_2_23 = mux(_com_remapped_row_T_70, io.com_remap_reqs[1].pdst, com_remapped_row_1_23) node com_remapped_row_3_23 = mux(_com_remapped_row_T_71, io.com_remap_reqs[2].pdst, com_remapped_row_2_23) connect remap_table[0][23], map_table[23] connect com_remap_table[0][23], com_map_table[23] connect remap_table[1][23], remapped_row_1_23 connect com_remap_table[1][23], com_remapped_row_1_23 connect remap_table[2][23], remapped_row_2_23 connect com_remap_table[2][23], com_remapped_row_2_23 connect remap_table[3][23], remapped_row_3_23 connect com_remap_table[3][23], com_remapped_row_3_23 node _remapped_row_T_72 = bits(remap_ldsts_oh_0, 24, 24) node _remapped_row_T_73 = bits(remap_ldsts_oh_1, 24, 24) node _remapped_row_T_74 = bits(remap_ldsts_oh_2, 24, 24) node remapped_row_1_24 = mux(_remapped_row_T_72, io.remap_reqs[0].pdst, map_table[24]) node remapped_row_2_24 = mux(_remapped_row_T_73, io.remap_reqs[1].pdst, remapped_row_1_24) node remapped_row_3_24 = mux(_remapped_row_T_74, io.remap_reqs[2].pdst, remapped_row_2_24) node _com_remapped_row_T_72 = bits(com_remap_ldsts_oh_0, 24, 24) node _com_remapped_row_T_73 = bits(com_remap_ldsts_oh_1, 24, 24) node _com_remapped_row_T_74 = bits(com_remap_ldsts_oh_2, 24, 24) node com_remapped_row_1_24 = mux(_com_remapped_row_T_72, io.com_remap_reqs[0].pdst, com_map_table[24]) node com_remapped_row_2_24 = mux(_com_remapped_row_T_73, io.com_remap_reqs[1].pdst, com_remapped_row_1_24) node com_remapped_row_3_24 = mux(_com_remapped_row_T_74, io.com_remap_reqs[2].pdst, com_remapped_row_2_24) connect remap_table[0][24], map_table[24] connect com_remap_table[0][24], com_map_table[24] connect remap_table[1][24], remapped_row_1_24 connect com_remap_table[1][24], com_remapped_row_1_24 connect remap_table[2][24], remapped_row_2_24 connect com_remap_table[2][24], com_remapped_row_2_24 connect remap_table[3][24], remapped_row_3_24 connect com_remap_table[3][24], com_remapped_row_3_24 node _remapped_row_T_75 = bits(remap_ldsts_oh_0, 25, 25) node _remapped_row_T_76 = bits(remap_ldsts_oh_1, 25, 25) node _remapped_row_T_77 = bits(remap_ldsts_oh_2, 25, 25) node remapped_row_1_25 = mux(_remapped_row_T_75, io.remap_reqs[0].pdst, map_table[25]) node remapped_row_2_25 = mux(_remapped_row_T_76, io.remap_reqs[1].pdst, remapped_row_1_25) node remapped_row_3_25 = mux(_remapped_row_T_77, io.remap_reqs[2].pdst, remapped_row_2_25) node _com_remapped_row_T_75 = bits(com_remap_ldsts_oh_0, 25, 25) node _com_remapped_row_T_76 = bits(com_remap_ldsts_oh_1, 25, 25) node _com_remapped_row_T_77 = bits(com_remap_ldsts_oh_2, 25, 25) node com_remapped_row_1_25 = mux(_com_remapped_row_T_75, io.com_remap_reqs[0].pdst, com_map_table[25]) node com_remapped_row_2_25 = mux(_com_remapped_row_T_76, io.com_remap_reqs[1].pdst, com_remapped_row_1_25) node com_remapped_row_3_25 = mux(_com_remapped_row_T_77, io.com_remap_reqs[2].pdst, com_remapped_row_2_25) connect remap_table[0][25], map_table[25] connect com_remap_table[0][25], com_map_table[25] connect remap_table[1][25], remapped_row_1_25 connect com_remap_table[1][25], com_remapped_row_1_25 connect remap_table[2][25], remapped_row_2_25 connect com_remap_table[2][25], com_remapped_row_2_25 connect remap_table[3][25], remapped_row_3_25 connect com_remap_table[3][25], com_remapped_row_3_25 node _remapped_row_T_78 = bits(remap_ldsts_oh_0, 26, 26) node _remapped_row_T_79 = bits(remap_ldsts_oh_1, 26, 26) node _remapped_row_T_80 = bits(remap_ldsts_oh_2, 26, 26) node remapped_row_1_26 = mux(_remapped_row_T_78, io.remap_reqs[0].pdst, map_table[26]) node remapped_row_2_26 = mux(_remapped_row_T_79, io.remap_reqs[1].pdst, remapped_row_1_26) node remapped_row_3_26 = mux(_remapped_row_T_80, io.remap_reqs[2].pdst, remapped_row_2_26) node _com_remapped_row_T_78 = bits(com_remap_ldsts_oh_0, 26, 26) node _com_remapped_row_T_79 = bits(com_remap_ldsts_oh_1, 26, 26) node _com_remapped_row_T_80 = bits(com_remap_ldsts_oh_2, 26, 26) node com_remapped_row_1_26 = mux(_com_remapped_row_T_78, io.com_remap_reqs[0].pdst, com_map_table[26]) node com_remapped_row_2_26 = mux(_com_remapped_row_T_79, io.com_remap_reqs[1].pdst, com_remapped_row_1_26) node com_remapped_row_3_26 = mux(_com_remapped_row_T_80, io.com_remap_reqs[2].pdst, com_remapped_row_2_26) connect remap_table[0][26], map_table[26] connect com_remap_table[0][26], com_map_table[26] connect remap_table[1][26], remapped_row_1_26 connect com_remap_table[1][26], com_remapped_row_1_26 connect remap_table[2][26], remapped_row_2_26 connect com_remap_table[2][26], com_remapped_row_2_26 connect remap_table[3][26], remapped_row_3_26 connect com_remap_table[3][26], com_remapped_row_3_26 node _remapped_row_T_81 = bits(remap_ldsts_oh_0, 27, 27) node _remapped_row_T_82 = bits(remap_ldsts_oh_1, 27, 27) node _remapped_row_T_83 = bits(remap_ldsts_oh_2, 27, 27) node remapped_row_1_27 = mux(_remapped_row_T_81, io.remap_reqs[0].pdst, map_table[27]) node remapped_row_2_27 = mux(_remapped_row_T_82, io.remap_reqs[1].pdst, remapped_row_1_27) node remapped_row_3_27 = mux(_remapped_row_T_83, io.remap_reqs[2].pdst, remapped_row_2_27) node _com_remapped_row_T_81 = bits(com_remap_ldsts_oh_0, 27, 27) node _com_remapped_row_T_82 = bits(com_remap_ldsts_oh_1, 27, 27) node _com_remapped_row_T_83 = bits(com_remap_ldsts_oh_2, 27, 27) node com_remapped_row_1_27 = mux(_com_remapped_row_T_81, io.com_remap_reqs[0].pdst, com_map_table[27]) node com_remapped_row_2_27 = mux(_com_remapped_row_T_82, io.com_remap_reqs[1].pdst, com_remapped_row_1_27) node com_remapped_row_3_27 = mux(_com_remapped_row_T_83, io.com_remap_reqs[2].pdst, com_remapped_row_2_27) connect remap_table[0][27], map_table[27] connect com_remap_table[0][27], com_map_table[27] connect remap_table[1][27], remapped_row_1_27 connect com_remap_table[1][27], com_remapped_row_1_27 connect remap_table[2][27], remapped_row_2_27 connect com_remap_table[2][27], com_remapped_row_2_27 connect remap_table[3][27], remapped_row_3_27 connect com_remap_table[3][27], com_remapped_row_3_27 node _remapped_row_T_84 = bits(remap_ldsts_oh_0, 28, 28) node _remapped_row_T_85 = bits(remap_ldsts_oh_1, 28, 28) node _remapped_row_T_86 = bits(remap_ldsts_oh_2, 28, 28) node remapped_row_1_28 = mux(_remapped_row_T_84, io.remap_reqs[0].pdst, map_table[28]) node remapped_row_2_28 = mux(_remapped_row_T_85, io.remap_reqs[1].pdst, remapped_row_1_28) node remapped_row_3_28 = mux(_remapped_row_T_86, io.remap_reqs[2].pdst, remapped_row_2_28) node _com_remapped_row_T_84 = bits(com_remap_ldsts_oh_0, 28, 28) node _com_remapped_row_T_85 = bits(com_remap_ldsts_oh_1, 28, 28) node _com_remapped_row_T_86 = bits(com_remap_ldsts_oh_2, 28, 28) node com_remapped_row_1_28 = mux(_com_remapped_row_T_84, io.com_remap_reqs[0].pdst, com_map_table[28]) node com_remapped_row_2_28 = mux(_com_remapped_row_T_85, io.com_remap_reqs[1].pdst, com_remapped_row_1_28) node com_remapped_row_3_28 = mux(_com_remapped_row_T_86, io.com_remap_reqs[2].pdst, com_remapped_row_2_28) connect remap_table[0][28], map_table[28] connect com_remap_table[0][28], com_map_table[28] connect remap_table[1][28], remapped_row_1_28 connect com_remap_table[1][28], com_remapped_row_1_28 connect remap_table[2][28], remapped_row_2_28 connect com_remap_table[2][28], com_remapped_row_2_28 connect remap_table[3][28], remapped_row_3_28 connect com_remap_table[3][28], com_remapped_row_3_28 node _remapped_row_T_87 = bits(remap_ldsts_oh_0, 29, 29) node _remapped_row_T_88 = bits(remap_ldsts_oh_1, 29, 29) node _remapped_row_T_89 = bits(remap_ldsts_oh_2, 29, 29) node remapped_row_1_29 = mux(_remapped_row_T_87, io.remap_reqs[0].pdst, map_table[29]) node remapped_row_2_29 = mux(_remapped_row_T_88, io.remap_reqs[1].pdst, remapped_row_1_29) node remapped_row_3_29 = mux(_remapped_row_T_89, io.remap_reqs[2].pdst, remapped_row_2_29) node _com_remapped_row_T_87 = bits(com_remap_ldsts_oh_0, 29, 29) node _com_remapped_row_T_88 = bits(com_remap_ldsts_oh_1, 29, 29) node _com_remapped_row_T_89 = bits(com_remap_ldsts_oh_2, 29, 29) node com_remapped_row_1_29 = mux(_com_remapped_row_T_87, io.com_remap_reqs[0].pdst, com_map_table[29]) node com_remapped_row_2_29 = mux(_com_remapped_row_T_88, io.com_remap_reqs[1].pdst, com_remapped_row_1_29) node com_remapped_row_3_29 = mux(_com_remapped_row_T_89, io.com_remap_reqs[2].pdst, com_remapped_row_2_29) connect remap_table[0][29], map_table[29] connect com_remap_table[0][29], com_map_table[29] connect remap_table[1][29], remapped_row_1_29 connect com_remap_table[1][29], com_remapped_row_1_29 connect remap_table[2][29], remapped_row_2_29 connect com_remap_table[2][29], com_remapped_row_2_29 connect remap_table[3][29], remapped_row_3_29 connect com_remap_table[3][29], com_remapped_row_3_29 node _remapped_row_T_90 = bits(remap_ldsts_oh_0, 30, 30) node _remapped_row_T_91 = bits(remap_ldsts_oh_1, 30, 30) node _remapped_row_T_92 = bits(remap_ldsts_oh_2, 30, 30) node remapped_row_1_30 = mux(_remapped_row_T_90, io.remap_reqs[0].pdst, map_table[30]) node remapped_row_2_30 = mux(_remapped_row_T_91, io.remap_reqs[1].pdst, remapped_row_1_30) node remapped_row_3_30 = mux(_remapped_row_T_92, io.remap_reqs[2].pdst, remapped_row_2_30) node _com_remapped_row_T_90 = bits(com_remap_ldsts_oh_0, 30, 30) node _com_remapped_row_T_91 = bits(com_remap_ldsts_oh_1, 30, 30) node _com_remapped_row_T_92 = bits(com_remap_ldsts_oh_2, 30, 30) node com_remapped_row_1_30 = mux(_com_remapped_row_T_90, io.com_remap_reqs[0].pdst, com_map_table[30]) node com_remapped_row_2_30 = mux(_com_remapped_row_T_91, io.com_remap_reqs[1].pdst, com_remapped_row_1_30) node com_remapped_row_3_30 = mux(_com_remapped_row_T_92, io.com_remap_reqs[2].pdst, com_remapped_row_2_30) connect remap_table[0][30], map_table[30] connect com_remap_table[0][30], com_map_table[30] connect remap_table[1][30], remapped_row_1_30 connect com_remap_table[1][30], com_remapped_row_1_30 connect remap_table[2][30], remapped_row_2_30 connect com_remap_table[2][30], com_remapped_row_2_30 connect remap_table[3][30], remapped_row_3_30 connect com_remap_table[3][30], com_remapped_row_3_30 node _remapped_row_T_93 = bits(remap_ldsts_oh_0, 31, 31) node _remapped_row_T_94 = bits(remap_ldsts_oh_1, 31, 31) node _remapped_row_T_95 = bits(remap_ldsts_oh_2, 31, 31) node remapped_row_1_31 = mux(_remapped_row_T_93, io.remap_reqs[0].pdst, map_table[31]) node remapped_row_2_31 = mux(_remapped_row_T_94, io.remap_reqs[1].pdst, remapped_row_1_31) node remapped_row_3_31 = mux(_remapped_row_T_95, io.remap_reqs[2].pdst, remapped_row_2_31) node _com_remapped_row_T_93 = bits(com_remap_ldsts_oh_0, 31, 31) node _com_remapped_row_T_94 = bits(com_remap_ldsts_oh_1, 31, 31) node _com_remapped_row_T_95 = bits(com_remap_ldsts_oh_2, 31, 31) node com_remapped_row_1_31 = mux(_com_remapped_row_T_93, io.com_remap_reqs[0].pdst, com_map_table[31]) node com_remapped_row_2_31 = mux(_com_remapped_row_T_94, io.com_remap_reqs[1].pdst, com_remapped_row_1_31) node com_remapped_row_3_31 = mux(_com_remapped_row_T_95, io.com_remap_reqs[2].pdst, com_remapped_row_2_31) connect remap_table[0][31], map_table[31] connect com_remap_table[0][31], com_map_table[31] connect remap_table[1][31], remapped_row_1_31 connect com_remap_table[1][31], com_remapped_row_1_31 connect remap_table[2][31], remapped_row_2_31 connect com_remap_table[2][31], com_remapped_row_2_31 connect remap_table[3][31], remapped_row_3_31 connect com_remap_table[3][31], com_remapped_row_3_31 when io.ren_br_tags[0].valid : connect br_snapshots[io.ren_br_tags[0].bits], remap_table[0] when io.ren_br_tags[1].valid : connect br_snapshots[io.ren_br_tags[1].bits], remap_table[1] when io.ren_br_tags[2].valid : connect br_snapshots[io.ren_br_tags[2].bits], remap_table[2] when io.ren_br_tags[3].valid : connect br_snapshots[io.ren_br_tags[3].bits], remap_table[3] when io.brupdate.b2.mispredict : connect map_table, br_snapshots[io.brupdate.b2.uop.br_tag] else : when io.rollback : connect map_table, com_map_table else : connect map_table, remap_table[3] connect com_map_table, com_remap_table[3] node _io_map_resps_0_prs1_T = bits(io.map_reqs[0].lrs1, 4, 0) connect io.map_resps[0].prs1, map_table[_io_map_resps_0_prs1_T] node _io_map_resps_0_prs2_T = bits(io.map_reqs[0].lrs2, 4, 0) connect io.map_resps[0].prs2, map_table[_io_map_resps_0_prs2_T] node _io_map_resps_0_prs3_T = bits(io.map_reqs[0].lrs3, 4, 0) connect io.map_resps[0].prs3, map_table[_io_map_resps_0_prs3_T] node _io_map_resps_0_stale_pdst_T = bits(io.map_reqs[0].ldst, 4, 0) connect io.map_resps[0].stale_pdst, map_table[_io_map_resps_0_stale_pdst_T] invalidate io.map_resps[0].prs3 node _io_map_resps_1_prs1_T = bits(io.map_reqs[1].lrs1, 4, 0) node _io_map_resps_1_prs1_T_1 = and(UInt<1>(0h0), io.remap_reqs[0].valid) node _io_map_resps_1_prs1_T_2 = eq(io.remap_reqs[0].ldst, io.map_reqs[1].lrs1) node _io_map_resps_1_prs1_T_3 = and(_io_map_resps_1_prs1_T_1, _io_map_resps_1_prs1_T_2) node _io_map_resps_1_prs1_T_4 = mux(_io_map_resps_1_prs1_T_3, io.remap_reqs[0].pdst, map_table[_io_map_resps_1_prs1_T]) connect io.map_resps[1].prs1, _io_map_resps_1_prs1_T_4 node _io_map_resps_1_prs2_T = bits(io.map_reqs[1].lrs2, 4, 0) node _io_map_resps_1_prs2_T_1 = and(UInt<1>(0h0), io.remap_reqs[0].valid) node _io_map_resps_1_prs2_T_2 = eq(io.remap_reqs[0].ldst, io.map_reqs[1].lrs2) node _io_map_resps_1_prs2_T_3 = and(_io_map_resps_1_prs2_T_1, _io_map_resps_1_prs2_T_2) node _io_map_resps_1_prs2_T_4 = mux(_io_map_resps_1_prs2_T_3, io.remap_reqs[0].pdst, map_table[_io_map_resps_1_prs2_T]) connect io.map_resps[1].prs2, _io_map_resps_1_prs2_T_4 node _io_map_resps_1_prs3_T = bits(io.map_reqs[1].lrs3, 4, 0) node _io_map_resps_1_prs3_T_1 = and(UInt<1>(0h0), io.remap_reqs[0].valid) node _io_map_resps_1_prs3_T_2 = eq(io.remap_reqs[0].ldst, io.map_reqs[1].lrs3) node _io_map_resps_1_prs3_T_3 = and(_io_map_resps_1_prs3_T_1, _io_map_resps_1_prs3_T_2) node _io_map_resps_1_prs3_T_4 = mux(_io_map_resps_1_prs3_T_3, io.remap_reqs[0].pdst, map_table[_io_map_resps_1_prs3_T]) connect io.map_resps[1].prs3, _io_map_resps_1_prs3_T_4 node _io_map_resps_1_stale_pdst_T = bits(io.map_reqs[1].ldst, 4, 0) node _io_map_resps_1_stale_pdst_T_1 = and(UInt<1>(0h0), io.remap_reqs[0].valid) node _io_map_resps_1_stale_pdst_T_2 = eq(io.remap_reqs[0].ldst, io.map_reqs[1].ldst) node _io_map_resps_1_stale_pdst_T_3 = and(_io_map_resps_1_stale_pdst_T_1, _io_map_resps_1_stale_pdst_T_2) node _io_map_resps_1_stale_pdst_T_4 = mux(_io_map_resps_1_stale_pdst_T_3, io.remap_reqs[0].pdst, map_table[_io_map_resps_1_stale_pdst_T]) connect io.map_resps[1].stale_pdst, _io_map_resps_1_stale_pdst_T_4 invalidate io.map_resps[1].prs3 node _io_map_resps_2_prs1_T = bits(io.map_reqs[2].lrs1, 4, 0) node _io_map_resps_2_prs1_T_1 = and(UInt<1>(0h0), io.remap_reqs[0].valid) node _io_map_resps_2_prs1_T_2 = eq(io.remap_reqs[0].ldst, io.map_reqs[2].lrs1) node _io_map_resps_2_prs1_T_3 = and(_io_map_resps_2_prs1_T_1, _io_map_resps_2_prs1_T_2) node _io_map_resps_2_prs1_T_4 = mux(_io_map_resps_2_prs1_T_3, io.remap_reqs[0].pdst, map_table[_io_map_resps_2_prs1_T]) node _io_map_resps_2_prs1_T_5 = and(UInt<1>(0h0), io.remap_reqs[1].valid) node _io_map_resps_2_prs1_T_6 = eq(io.remap_reqs[1].ldst, io.map_reqs[2].lrs1) node _io_map_resps_2_prs1_T_7 = and(_io_map_resps_2_prs1_T_5, _io_map_resps_2_prs1_T_6) node _io_map_resps_2_prs1_T_8 = mux(_io_map_resps_2_prs1_T_7, io.remap_reqs[1].pdst, _io_map_resps_2_prs1_T_4) connect io.map_resps[2].prs1, _io_map_resps_2_prs1_T_8 node _io_map_resps_2_prs2_T = bits(io.map_reqs[2].lrs2, 4, 0) node _io_map_resps_2_prs2_T_1 = and(UInt<1>(0h0), io.remap_reqs[0].valid) node _io_map_resps_2_prs2_T_2 = eq(io.remap_reqs[0].ldst, io.map_reqs[2].lrs2) node _io_map_resps_2_prs2_T_3 = and(_io_map_resps_2_prs2_T_1, _io_map_resps_2_prs2_T_2) node _io_map_resps_2_prs2_T_4 = mux(_io_map_resps_2_prs2_T_3, io.remap_reqs[0].pdst, map_table[_io_map_resps_2_prs2_T]) node _io_map_resps_2_prs2_T_5 = and(UInt<1>(0h0), io.remap_reqs[1].valid) node _io_map_resps_2_prs2_T_6 = eq(io.remap_reqs[1].ldst, io.map_reqs[2].lrs2) node _io_map_resps_2_prs2_T_7 = and(_io_map_resps_2_prs2_T_5, _io_map_resps_2_prs2_T_6) node _io_map_resps_2_prs2_T_8 = mux(_io_map_resps_2_prs2_T_7, io.remap_reqs[1].pdst, _io_map_resps_2_prs2_T_4) connect io.map_resps[2].prs2, _io_map_resps_2_prs2_T_8 node _io_map_resps_2_prs3_T = bits(io.map_reqs[2].lrs3, 4, 0) node _io_map_resps_2_prs3_T_1 = and(UInt<1>(0h0), io.remap_reqs[0].valid) node _io_map_resps_2_prs3_T_2 = eq(io.remap_reqs[0].ldst, io.map_reqs[2].lrs3) node _io_map_resps_2_prs3_T_3 = and(_io_map_resps_2_prs3_T_1, _io_map_resps_2_prs3_T_2) node _io_map_resps_2_prs3_T_4 = mux(_io_map_resps_2_prs3_T_3, io.remap_reqs[0].pdst, map_table[_io_map_resps_2_prs3_T]) node _io_map_resps_2_prs3_T_5 = and(UInt<1>(0h0), io.remap_reqs[1].valid) node _io_map_resps_2_prs3_T_6 = eq(io.remap_reqs[1].ldst, io.map_reqs[2].lrs3) node _io_map_resps_2_prs3_T_7 = and(_io_map_resps_2_prs3_T_5, _io_map_resps_2_prs3_T_6) node _io_map_resps_2_prs3_T_8 = mux(_io_map_resps_2_prs3_T_7, io.remap_reqs[1].pdst, _io_map_resps_2_prs3_T_4) connect io.map_resps[2].prs3, _io_map_resps_2_prs3_T_8 node _io_map_resps_2_stale_pdst_T = bits(io.map_reqs[2].ldst, 4, 0) node _io_map_resps_2_stale_pdst_T_1 = and(UInt<1>(0h0), io.remap_reqs[0].valid) node _io_map_resps_2_stale_pdst_T_2 = eq(io.remap_reqs[0].ldst, io.map_reqs[2].ldst) node _io_map_resps_2_stale_pdst_T_3 = and(_io_map_resps_2_stale_pdst_T_1, _io_map_resps_2_stale_pdst_T_2) node _io_map_resps_2_stale_pdst_T_4 = mux(_io_map_resps_2_stale_pdst_T_3, io.remap_reqs[0].pdst, map_table[_io_map_resps_2_stale_pdst_T]) node _io_map_resps_2_stale_pdst_T_5 = and(UInt<1>(0h0), io.remap_reqs[1].valid) node _io_map_resps_2_stale_pdst_T_6 = eq(io.remap_reqs[1].ldst, io.map_reqs[2].ldst) node _io_map_resps_2_stale_pdst_T_7 = and(_io_map_resps_2_stale_pdst_T_5, _io_map_resps_2_stale_pdst_T_6) node _io_map_resps_2_stale_pdst_T_8 = mux(_io_map_resps_2_stale_pdst_T_7, io.remap_reqs[1].pdst, _io_map_resps_2_stale_pdst_T_4) connect io.map_resps[2].stale_pdst, _io_map_resps_2_stale_pdst_T_8 invalidate io.map_resps[2].prs3 node _T = eq(io.remap_reqs[0].valid, UInt<1>(0h0)) node _T_1 = eq(map_table[0], io.remap_reqs[0].pdst) node _T_2 = eq(map_table[1], io.remap_reqs[0].pdst) node _T_3 = eq(map_table[2], io.remap_reqs[0].pdst) node _T_4 = eq(map_table[3], io.remap_reqs[0].pdst) node _T_5 = eq(map_table[4], io.remap_reqs[0].pdst) node _T_6 = eq(map_table[5], io.remap_reqs[0].pdst) node _T_7 = eq(map_table[6], io.remap_reqs[0].pdst) node _T_8 = eq(map_table[7], io.remap_reqs[0].pdst) node _T_9 = eq(map_table[8], io.remap_reqs[0].pdst) node _T_10 = eq(map_table[9], io.remap_reqs[0].pdst) node _T_11 = eq(map_table[10], io.remap_reqs[0].pdst) node _T_12 = eq(map_table[11], io.remap_reqs[0].pdst) node _T_13 = eq(map_table[12], io.remap_reqs[0].pdst) node _T_14 = eq(map_table[13], io.remap_reqs[0].pdst) node _T_15 = eq(map_table[14], io.remap_reqs[0].pdst) node _T_16 = eq(map_table[15], io.remap_reqs[0].pdst) node _T_17 = eq(map_table[16], io.remap_reqs[0].pdst) node _T_18 = eq(map_table[17], io.remap_reqs[0].pdst) node _T_19 = eq(map_table[18], io.remap_reqs[0].pdst) node _T_20 = eq(map_table[19], io.remap_reqs[0].pdst) node _T_21 = eq(map_table[20], io.remap_reqs[0].pdst) node _T_22 = eq(map_table[21], io.remap_reqs[0].pdst) node _T_23 = eq(map_table[22], io.remap_reqs[0].pdst) node _T_24 = eq(map_table[23], io.remap_reqs[0].pdst) node _T_25 = eq(map_table[24], io.remap_reqs[0].pdst) node _T_26 = eq(map_table[25], io.remap_reqs[0].pdst) node _T_27 = eq(map_table[26], io.remap_reqs[0].pdst) node _T_28 = eq(map_table[27], io.remap_reqs[0].pdst) node _T_29 = eq(map_table[28], io.remap_reqs[0].pdst) node _T_30 = eq(map_table[29], io.remap_reqs[0].pdst) node _T_31 = eq(map_table[30], io.remap_reqs[0].pdst) node _T_32 = eq(map_table[31], io.remap_reqs[0].pdst) node _T_33 = or(UInt<1>(0h0), _T_1) node _T_34 = or(_T_33, _T_2) node _T_35 = or(_T_34, _T_3) node _T_36 = or(_T_35, _T_4) node _T_37 = or(_T_36, _T_5) node _T_38 = or(_T_37, _T_6) node _T_39 = or(_T_38, _T_7) node _T_40 = or(_T_39, _T_8) node _T_41 = or(_T_40, _T_9) node _T_42 = or(_T_41, _T_10) node _T_43 = or(_T_42, _T_11) node _T_44 = or(_T_43, _T_12) node _T_45 = or(_T_44, _T_13) node _T_46 = or(_T_45, _T_14) node _T_47 = or(_T_46, _T_15) node _T_48 = or(_T_47, _T_16) node _T_49 = or(_T_48, _T_17) node _T_50 = or(_T_49, _T_18) node _T_51 = or(_T_50, _T_19) node _T_52 = or(_T_51, _T_20) node _T_53 = or(_T_52, _T_21) node _T_54 = or(_T_53, _T_22) node _T_55 = or(_T_54, _T_23) node _T_56 = or(_T_55, _T_24) node _T_57 = or(_T_56, _T_25) node _T_58 = or(_T_57, _T_26) node _T_59 = or(_T_58, _T_27) node _T_60 = or(_T_59, _T_28) node _T_61 = or(_T_60, _T_29) node _T_62 = or(_T_61, _T_30) node _T_63 = or(_T_62, _T_31) node _T_64 = or(_T_63, _T_32) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = or(_T, _T_65) node _T_67 = asUInt(reset) node _T_68 = eq(_T_67, UInt<1>(0h0)) when _T_68 : node _T_69 = eq(_T_66, UInt<1>(0h0)) when _T_69 : printf(clock, UInt<1>(0h1), "Assertion failed: [maptable] Trying to write a duplicate mapping.\n at rename-maptable.scala:145 assert (!r \|\| !map_table.contains(p), \"[maptable] Trying to write a duplicate mapping.\")}\n") : printf assert(clock, _T_66, UInt<1>(0h1), "") : assert node _T_70 = eq(io.remap_reqs[1].valid, UInt<1>(0h0)) node _T_71 = eq(map_table[0], io.remap_reqs[1].pdst) node _T_72 = eq(map_table[1], io.remap_reqs[1].pdst) node _T_73 = eq(map_table[2], io.remap_reqs[1].pdst) node _T_74 = eq(map_table[3], io.remap_reqs[1].pdst) node _T_75 = eq(map_table[4], io.remap_reqs[1].pdst) node _T_76 = eq(map_table[5], io.remap_reqs[1].pdst) node _T_77 = eq(map_table[6], io.remap_reqs[1].pdst) node _T_78 = eq(map_table[7], io.remap_reqs[1].pdst) node _T_79 = eq(map_table[8], io.remap_reqs[1].pdst) node _T_80 = eq(map_table[9], io.remap_reqs[1].pdst) node _T_81 = eq(map_table[10], io.remap_reqs[1].pdst) node _T_82 = eq(map_table[11], io.remap_reqs[1].pdst) node _T_83 = eq(map_table[12], io.remap_reqs[1].pdst) node _T_84 = eq(map_table[13], io.remap_reqs[1].pdst) node _T_85 = eq(map_table[14], io.remap_reqs[1].pdst) node _T_86 = eq(map_table[15], io.remap_reqs[1].pdst) node _T_87 = eq(map_table[16], io.remap_reqs[1].pdst) node _T_88 = eq(map_table[17], io.remap_reqs[1].pdst) node _T_89 = eq(map_table[18], io.remap_reqs[1].pdst) node _T_90 = eq(map_table[19], io.remap_reqs[1].pdst) node _T_91 = eq(map_table[20], io.remap_reqs[1].pdst) node _T_92 = eq(map_table[21], io.remap_reqs[1].pdst) node _T_93 = eq(map_table[22], io.remap_reqs[1].pdst) node _T_94 = eq(map_table[23], io.remap_reqs[1].pdst) node _T_95 = eq(map_table[24], io.remap_reqs[1].pdst) node _T_96 = eq(map_table[25], io.remap_reqs[1].pdst) node _T_97 = eq(map_table[26], io.remap_reqs[1].pdst) node _T_98 = eq(map_table[27], io.remap_reqs[1].pdst) node _T_99 = eq(map_table[28], io.remap_reqs[1].pdst) node _T_100 = eq(map_table[29], io.remap_reqs[1].pdst) node _T_101 = eq(map_table[30], io.remap_reqs[1].pdst) node _T_102 = eq(map_table[31], io.remap_reqs[1].pdst) node _T_103 = or(UInt<1>(0h0), _T_71) node _T_104 = or(_T_103, _T_72) node _T_105 = or(_T_104, _T_73) node _T_106 = or(_T_105, _T_74) node _T_107 = or(_T_106, _T_75) node _T_108 = or(_T_107, _T_76) node _T_109 = or(_T_108, _T_77) node _T_110 = or(_T_109, _T_78) node _T_111 = or(_T_110, _T_79) node _T_112 = or(_T_111, _T_80) node _T_113 = or(_T_112, _T_81) node _T_114 = or(_T_113, _T_82) node _T_115 = or(_T_114, _T_83) node _T_116 = or(_T_115, _T_84) node _T_117 = or(_T_116, _T_85) node _T_118 = or(_T_117, _T_86) node _T_119 = or(_T_118, _T_87) node _T_120 = or(_T_119, _T_88) node _T_121 = or(_T_120, _T_89) node _T_122 = or(_T_121, _T_90) node _T_123 = or(_T_122, _T_91) node _T_124 = or(_T_123, _T_92) node _T_125 = or(_T_124, _T_93) node _T_126 = or(_T_125, _T_94) node _T_127 = or(_T_126, _T_95) node _T_128 = or(_T_127, _T_96) node _T_129 = or(_T_128, _T_97) node _T_130 = or(_T_129, _T_98) node _T_131 = or(_T_130, _T_99) node _T_132 = or(_T_131, _T_100) node _T_133 = or(_T_132, _T_101) node _T_134 = or(_T_133, _T_102) node _T_135 = eq(_T_134, UInt<1>(0h0)) node _T_136 = or(_T_70, _T_135) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: [maptable] Trying to write a duplicate mapping.\n at rename-maptable.scala:145 assert (!r \|\| !map_table.contains(p), \"[maptable] Trying to write a duplicate mapping.\")}\n") : printf_1 assert(clock, _T_136, UInt<1>(0h1), "") : assert_1 node _T_140 = eq(io.remap_reqs[2].valid, UInt<1>(0h0)) node _T_141 = eq(map_table[0], io.remap_reqs[2].pdst) node _T_142 = eq(map_table[1], io.remap_reqs[2].pdst) node _T_143 = eq(map_table[2], io.remap_reqs[2].pdst) node _T_144 = eq(map_table[3], io.remap_reqs[2].pdst) node _T_145 = eq(map_table[4], io.remap_reqs[2].pdst) node _T_146 = eq(map_table[5], io.remap_reqs[2].pdst) node _T_147 = eq(map_table[6], io.remap_reqs[2].pdst) node _T_148 = eq(map_table[7], io.remap_reqs[2].pdst) node _T_149 = eq(map_table[8], io.remap_reqs[2].pdst) node _T_150 = eq(map_table[9], io.remap_reqs[2].pdst) node _T_151 = eq(map_table[10], io.remap_reqs[2].pdst) node _T_152 = eq(map_table[11], io.remap_reqs[2].pdst) node _T_153 = eq(map_table[12], io.remap_reqs[2].pdst) node _T_154 = eq(map_table[13], io.remap_reqs[2].pdst) node _T_155 = eq(map_table[14], io.remap_reqs[2].pdst) node _T_156 = eq(map_table[15], io.remap_reqs[2].pdst) node _T_157 = eq(map_table[16], io.remap_reqs[2].pdst) node _T_158 = eq(map_table[17], io.remap_reqs[2].pdst) node _T_159 = eq(map_table[18], io.remap_reqs[2].pdst) node _T_160 = eq(map_table[19], io.remap_reqs[2].pdst) node _T_161 = eq(map_table[20], io.remap_reqs[2].pdst) node _T_162 = eq(map_table[21], io.remap_reqs[2].pdst) node _T_163 = eq(map_table[22], io.remap_reqs[2].pdst) node _T_164 = eq(map_table[23], io.remap_reqs[2].pdst) node _T_165 = eq(map_table[24], io.remap_reqs[2].pdst) node _T_166 = eq(map_table[25], io.remap_reqs[2].pdst) node _T_167 = eq(map_table[26], io.remap_reqs[2].pdst) node _T_168 = eq(map_table[27], io.remap_reqs[2].pdst) node _T_169 = eq(map_table[28], io.remap_reqs[2].pdst) node _T_170 = eq(map_table[29], io.remap_reqs[2].pdst) node _T_171 = eq(map_table[30], io.remap_reqs[2].pdst) node _T_172 = eq(map_table[31], io.remap_reqs[2].pdst) node _T_173 = or(UInt<1>(0h0), _T_141) node _T_174 = or(_T_173, _T_142) node _T_175 = or(_T_174, _T_143) node _T_176 = or(_T_175, _T_144) node _T_177 = or(_T_176, _T_145) node _T_178 = or(_T_177, _T_146) node _T_179 = or(_T_178, _T_147) node _T_180 = or(_T_179, _T_148) node _T_181 = or(_T_180, _T_149) node _T_182 = or(_T_181, _T_150) node _T_183 = or(_T_182, _T_151) node _T_184 = or(_T_183, _T_152) node _T_185 = or(_T_184, _T_153) node _T_186 = or(_T_185, _T_154) node _T_187 = or(_T_186, _T_155) node _T_188 = or(_T_187, _T_156) node _T_189 = or(_T_188, _T_157) node _T_190 = or(_T_189, _T_158) node _T_191 = or(_T_190, _T_159) node _T_192 = or(_T_191, _T_160) node _T_193 = or(_T_192, _T_161) node _T_194 = or(_T_193, _T_162) node _T_195 = or(_T_194, _T_163) node _T_196 = or(_T_195, _T_164) node _T_197 = or(_T_196, _T_165) node _T_198 = or(_T_197, _T_166) node _T_199 = or(_T_198, _T_167) node _T_200 = or(_T_199, _T_168) node _T_201 = or(_T_200, _T_169) node _T_202 = or(_T_201, _T_170) node _T_203 = or(_T_202, _T_171) node _T_204 = or(_T_203, _T_172) node _T_205 = eq(_T_204, UInt<1>(0h0)) node _T_206 = or(_T_140, _T_205) node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_T_206, UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed: [maptable] Trying to write a duplicate mapping.\n at rename-maptable.scala:145 assert (!r \|\| !map_table.contains(p), \"[maptable] Trying to write a duplicate mapping.\")}\n") : printf_2 assert(clock, _T_206, UInt<1>(0h1), "") : assert_2	module RenameMapTable( // @[rename-maptable.scala:43:7] input clock, // @[rename-maptable.scala:43:7] input reset, // @[rename-maptable.scala:43:7] input [5:0] io_map_reqs_0_lrs1, // @[rename-maptable.scala:53:14] input [5:0] io_map_reqs_0_lrs2, // @[rename-maptable.scala:53:14] input [5:0] io_map_reqs_0_lrs3, // @[rename-maptable.scala:53:14] input [5:0] io_map_reqs_0_ldst, // @[rename-maptable.scala:53:14] input [5:0] io_map_reqs_1_lrs1, // @[rename-maptable.scala:53:14] input [5:0] io_map_reqs_1_lrs2, // @[rename-maptable.scala:53:14] input [5:0] io_map_reqs_1_lrs3, // @[rename-maptable.scala:53:14] input [5:0] io_map_reqs_1_ldst, // @[rename-maptable.scala:53:14] input [5:0] io_map_reqs_2_lrs1, // @[rename-maptable.scala:53:14] input [5:0] io_map_reqs_2_lrs2, // @[rename-maptable.scala:53:14] input [5:0] io_map_reqs_2_lrs3, // @[rename-maptable.scala:53:14] input [5:0] io_map_reqs_2_ldst, // @[rename-maptable.scala:53:14] output [6:0] io_map_resps_0_prs1, // @[rename-maptable.scala:53:14] output [6:0] io_map_resps_0_prs2, // @[rename-maptable.scala:53:14] output [6:0] io_map_resps_0_stale_pdst, // @[rename-maptable.scala:53:14] output [6:0] io_map_resps_1_prs1, // @[rename-maptable.scala:53:14] output [6:0] io_map_resps_1_prs2, // @[rename-maptable.scala:53:14] output [6:0] io_map_resps_1_stale_pdst, // @[rename-maptable.scala:53:14] output [6:0] io_map_resps_2_prs1, // @[rename-maptable.scala:53:14] output [6:0] io_map_resps_2_prs2, // @[rename-maptable.scala:53:14] output [6:0] io_map_resps_2_stale_pdst, // @[rename-maptable.scala:53:14] input [5:0] io_remap_reqs_0_ldst, // @[rename-maptable.scala:53:14] input [6:0] io_remap_reqs_0_pdst, // @[rename-maptable.scala:53:14] input io_remap_reqs_0_valid, // @[rename-maptable.scala:53:14] input [5:0] io_remap_reqs_1_ldst, // @[rename-maptable.scala:53:14] input [6:0] io_remap_reqs_1_pdst, // @[rename-maptable.scala:53:14] input io_remap_reqs_1_valid, // @[rename-maptable.scala:53:14] input [5:0] io_remap_reqs_2_ldst, // @[rename-maptable.scala:53:14] input [6:0] io_remap_reqs_2_pdst, // @[rename-maptable.scala:53:14] input io_remap_reqs_2_valid, // @[rename-maptable.scala:53:14] input [5:0] io_com_remap_reqs_0_ldst, // @[rename-maptable.scala:53:14] input [6:0] io_com_remap_reqs_0_pdst, // @[rename-maptable.scala:53:14] input io_com_remap_reqs_0_valid, // @[rename-maptable.scala:53:14] input [5:0] io_com_remap_reqs_1_ldst, // @[rename-maptable.scala:53:14] input [6:0] io_com_remap_reqs_1_pdst, // @[rename-maptable.scala:53:14] input io_com_remap_reqs_1_valid, // @[rename-maptable.scala:53:14] input [5:0] io_com_remap_reqs_2_ldst, // @[rename-maptable.scala:53:14] input [6:0] io_com_remap_reqs_2_pdst, // @[rename-maptable.scala:53:14] input io_com_remap_reqs_2_valid, // @[rename-maptable.scala:53:14] input io_ren_br_tags_1_valid, // @[rename-maptable.scala:53:14] input [3:0] io_ren_br_tags_1_bits, // @[rename-maptable.scala:53:14] input io_ren_br_tags_2_valid, // @[rename-maptable.scala:53:14] input [3:0] io_ren_br_tags_2_bits, // @[rename-maptable.scala:53:14] input io_ren_br_tags_3_valid, // @[rename-maptable.scala:53:14] input [3:0] io_ren_br_tags_3_bits, // @[rename-maptable.scala:53:14] input [15:0] io_brupdate_b1_resolve_mask, // @[rename-maptable.scala:53:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[rename-maptable.scala:53:14] input [31:0] io_brupdate_b2_uop_inst, // @[rename-maptable.scala:53:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_rvc, // @[rename-maptable.scala:53:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_iq_type_0, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_iq_type_1, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_iq_type_2, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_iq_type_3, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fu_code_0, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fu_code_1, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fu_code_2, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fu_code_3, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fu_code_4, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fu_code_5, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fu_code_6, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fu_code_7, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fu_code_8, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fu_code_9, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_iw_issued, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[rename-maptable.scala:53:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[rename-maptable.scala:53:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[rename-maptable.scala:53:14] input [3:0] io_brupdate_b2_uop_br_type, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_sfb, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_fence, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_fencei, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_sfence, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_amo, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_eret, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_rocc, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_mov, // @[rename-maptable.scala:53:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_edge_inst, // @[rename-maptable.scala:53:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_taken, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_imm_rename, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[rename-maptable.scala:53:14] input [4:0] io_brupdate_b2_uop_pimm, // @[rename-maptable.scala:53:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[rename-maptable.scala:53:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[rename-maptable.scala:53:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[rename-maptable.scala:53:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[rename-maptable.scala:53:14] input [6:0] io_brupdate_b2_uop_pdst, // @[rename-maptable.scala:53:14] input [6:0] io_brupdate_b2_uop_prs1, // @[rename-maptable.scala:53:14] input [6:0] io_brupdate_b2_uop_prs2, // @[rename-maptable.scala:53:14] input [6:0] io_brupdate_b2_uop_prs3, // @[rename-maptable.scala:53:14] input [4:0] io_brupdate_b2_uop_ppred, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_prs1_busy, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_prs2_busy, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_prs3_busy, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_ppred_busy, // @[rename-maptable.scala:53:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_exception, // @[rename-maptable.scala:53:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[rename-maptable.scala:53:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_mem_signed, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_uses_ldq, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_uses_stq, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_unique, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_flush_on_commit, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[rename-maptable.scala:53:14] input [5:0] io_brupdate_b2_uop_ldst, // @[rename-maptable.scala:53:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[rename-maptable.scala:53:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[rename-maptable.scala:53:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_frs3_en, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fcn_dw, // @[rename-maptable.scala:53:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_val, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_bp_debug_if, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[rename-maptable.scala:53:14] input io_brupdate_b2_mispredict, // @[rename-maptable.scala:53:14] input io_brupdate_b2_taken, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_cfi_type, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_pc_sel, // @[rename-maptable.scala:53:14] input [39:0] io_brupdate_b2_jalr_target, // @[rename-maptable.scala:53:14] input [20:0] io_brupdate_b2_target_offset, // @[rename-maptable.scala:53:14] input io_rollback // @[rename-maptable.scala:53:14] ); wire [5:0] io_map_reqs_0_lrs1_0 = io_map_reqs_0_lrs1; // @[rename-maptable.scala:43:7] wire [5:0] io_map_reqs_0_lrs2_0 = io_map_reqs_0_lrs2; // @[rename-maptable.scala:43:7] wire [5:0] io_map_reqs_0_lrs3_0 = io_map_reqs_0_lrs3; // @[rename-maptable.scala:43:7] wire [5:0] io_map_reqs_0_ldst_0 = io_map_reqs_0_ldst; // @[rename-maptable.scala:43:7] wire [5:0] io_map_reqs_1_lrs1_0 = io_map_reqs_1_lrs1; // @[rename-maptable.scala:43:7] wire [5:0] io_map_reqs_1_lrs2_0 = io_map_reqs_1_lrs2; // @[rename-maptable.scala:43:7] wire [5:0] io_map_reqs_1_lrs3_0 = io_map_reqs_1_lrs3; // @[rename-maptable.scala:43:7] wire [5:0] io_map_reqs_1_ldst_0 = io_map_reqs_1_ldst; // @[rename-maptable.scala:43:7] wire [5:0] io_map_reqs_2_lrs1_0 = io_map_reqs_2_lrs1; // @[rename-maptable.scala:43:7] wire [5:0] io_map_reqs_2_lrs2_0 = io_map_reqs_2_lrs2; // @[rename-maptable.scala:43:7] wire [5:0] io_map_reqs_2_lrs3_0 = io_map_reqs_2_lrs3; // @[rename-maptable.scala:43:7] wire [5:0] io_map_reqs_2_ldst_0 = io_map_reqs_2_ldst; // @[rename-maptable.scala:43:7] wire [5:0] io_remap_reqs_0_ldst_0 = io_remap_reqs_0_ldst; // @[rename-maptable.scala:43:7] wire [6:0] io_remap_reqs_0_pdst_0 = io_remap_reqs_0_pdst; // @[rename-maptable.scala:43:7] wire io_remap_reqs_0_valid_0 = io_remap_reqs_0_valid; // @[rename-maptable.scala:43:7] wire [5:0] io_remap_reqs_1_ldst_0 = io_remap_reqs_1_ldst; // @[rename-maptable.scala:43:7] wire [6:0] io_remap_reqs_1_pdst_0 = io_remap_reqs_1_pdst; // @[rename-maptable.scala:43:7] wire io_remap_reqs_1_valid_0 = io_remap_reqs_1_valid; // @[rename-maptable.scala:43:7] wire [5:0] io_remap_reqs_2_ldst_0 = io_remap_reqs_2_ldst; // @[rename-maptable.scala:43:7] wire [6:0] io_remap_reqs_2_pdst_0 = io_remap_reqs_2_pdst; // @[rename-maptable.scala:43:7] wire io_remap_reqs_2_valid_0 = io_remap_reqs_2_valid; // @[rename-maptable.scala:43:7] wire [5:0] io_com_remap_reqs_0_ldst_0 = io_com_remap_reqs_0_ldst; // @[rename-maptable.scala:43:7] wire [6:0] io_com_remap_reqs_0_pdst_0 = io_com_remap_reqs_0_pdst; // @[rename-maptable.scala:43:7] wire io_com_remap_reqs_0_valid_0 = io_com_remap_reqs_0_valid; // @[rename-maptable.scala:43:7] wire [5:0] io_com_remap_reqs_1_ldst_0 = io_com_remap_reqs_1_ldst; // @[rename-maptable.scala:43:7] wire [6:0] io_com_remap_reqs_1_pdst_0 = io_com_remap_reqs_1_pdst; // @[rename-maptable.scala:43:7] wire io_com_remap_reqs_1_valid_0 = io_com_remap_reqs_1_valid; // @[rename-maptable.scala:43:7] wire [5:0] io_com_remap_reqs_2_ldst_0 = io_com_remap_reqs_2_ldst; // @[rename-maptable.scala:43:7] wire [6:0] io_com_remap_reqs_2_pdst_0 = io_com_remap_reqs_2_pdst; // @[rename-maptable.scala:43:7] wire io_com_remap_reqs_2_valid_0 = io_com_remap_reqs_2_valid; // @[rename-maptable.scala:43:7] wire io_ren_br_tags_1_valid_0 = io_ren_br_tags_1_valid; // @[rename-maptable.scala:43:7] wire [3:0] io_ren_br_tags_1_bits_0 = io_ren_br_tags_1_bits; // @[rename-maptable.scala:43:7] wire io_ren_br_tags_2_valid_0 = io_ren_br_tags_2_valid; // @[rename-maptable.scala:43:7] wire [3:0] io_ren_br_tags_2_bits_0 = io_ren_br_tags_2_bits; // @[rename-maptable.scala:43:7] wire io_ren_br_tags_3_valid_0 = io_ren_br_tags_3_valid; // @[rename-maptable.scala:43:7] wire [3:0] io_ren_br_tags_3_bits_0 = io_ren_br_tags_3_bits; // @[rename-maptable.scala:43:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[rename-maptable.scala:43:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[rename-maptable.scala:43:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[rename-maptable.scala:43:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[rename-maptable.scala:43:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[rename-maptable.scala:43:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[rename-maptable.scala:43:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[rename-maptable.scala:43:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[rename-maptable.scala:43:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[rename-maptable.scala:43:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[rename-maptable.scala:43:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[rename-maptable.scala:43:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[rename-maptable.scala:43:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[rename-maptable.scala:43:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[rename-maptable.scala:43:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[rename-maptable.scala:43:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[rename-maptable.scala:43:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[rename-maptable.scala:43:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[rename-maptable.scala:43:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[rename-maptable.scala:43:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[rename-maptable.scala:43:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[rename-maptable.scala:43:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[rename-maptable.scala:43:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[rename-maptable.scala:43:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[rename-maptable.scala:43:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[rename-maptable.scala:43:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[rename-maptable.scala:43:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[rename-maptable.scala:43:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[rename-maptable.scala:43:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[rename-maptable.scala:43:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[rename-maptable.scala:43:7] wire io_rollback_0 = io_rollback; // @[rename-maptable.scala:43:7] wire [6:0] io_map_resps_0_prs3 = 7'h0; // @[rename-maptable.scala:43:7] wire [6:0] io_map_resps_1_prs3 = 7'h0; // @[rename-maptable.scala:43:7] wire [6:0] io_map_resps_2_prs3 = 7'h0; // @[rename-maptable.scala:43:7] wire [6:0] _map_table_WIRE_0 = 7'h0; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_0 = 7'h0; // @[rename-maptable.scala:72:38] wire io_ren_br_tags_0_valid = 1'h0; // @[rename-maptable.scala:43:7] wire _io_map_resps_1_prs1_T_1 = 1'h0; // @[rename-maptable.scala:131:20] wire _io_map_resps_1_prs1_T_3 = 1'h0; // @[rename-maptable.scala:131:46] wire _io_map_resps_1_prs2_T_1 = 1'h0; // @[rename-maptable.scala:133:20] wire _io_map_resps_1_prs2_T_3 = 1'h0; // @[rename-maptable.scala:133:46] wire _io_map_resps_1_prs3_T_1 = 1'h0; // @[rename-maptable.scala:135:20] wire _io_map_resps_1_prs3_T_3 = 1'h0; // @[rename-maptable.scala:135:46] wire _io_map_resps_1_stale_pdst_T_1 = 1'h0; // @[rename-maptable.scala:137:20] wire _io_map_resps_1_stale_pdst_T_3 = 1'h0; // @[rename-maptable.scala:137:46] wire _io_map_resps_2_prs1_T_1 = 1'h0; // @[rename-maptable.scala:131:20] wire _io_map_resps_2_prs1_T_3 = 1'h0; // @[rename-maptable.scala:131:46] wire _io_map_resps_2_prs1_T_5 = 1'h0; // @[rename-maptable.scala:131:20] wire _io_map_resps_2_prs1_T_7 = 1'h0; // @[rename-maptable.scala:131:46] wire _io_map_resps_2_prs2_T_1 = 1'h0; // @[rename-maptable.scala:133:20] wire _io_map_resps_2_prs2_T_3 = 1'h0; // @[rename-maptable.scala:133:46] wire _io_map_resps_2_prs2_T_5 = 1'h0; // @[rename-maptable.scala:133:20] wire _io_map_resps_2_prs2_T_7 = 1'h0; // @[rename-maptable.scala:133:46] wire _io_map_resps_2_prs3_T_1 = 1'h0; // @[rename-maptable.scala:135:20] wire _io_map_resps_2_prs3_T_3 = 1'h0; // @[rename-maptable.scala:135:46] wire _io_map_resps_2_prs3_T_5 = 1'h0; // @[rename-maptable.scala:135:20] wire _io_map_resps_2_prs3_T_7 = 1'h0; // @[rename-maptable.scala:135:46] wire _io_map_resps_2_stale_pdst_T_1 = 1'h0; // @[rename-maptable.scala:137:20] wire _io_map_resps_2_stale_pdst_T_3 = 1'h0; // @[rename-maptable.scala:137:46] wire _io_map_resps_2_stale_pdst_T_5 = 1'h0; // @[rename-maptable.scala:137:20] wire _io_map_resps_2_stale_pdst_T_7 = 1'h0; // @[rename-maptable.scala:137:46] wire [3:0] io_ren_br_tags_0_bits = 4'h0; // @[rename-maptable.scala:43:7] wire [6:0] _map_table_WIRE_31 = 7'h1F; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_31 = 7'h1F; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_30 = 7'h1E; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_30 = 7'h1E; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_29 = 7'h1D; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_29 = 7'h1D; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_28 = 7'h1C; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_28 = 7'h1C; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_27 = 7'h1B; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_27 = 7'h1B; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_26 = 7'h1A; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_26 = 7'h1A; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_25 = 7'h19; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_25 = 7'h19; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_24 = 7'h18; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_24 = 7'h18; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_23 = 7'h17; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_23 = 7'h17; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_22 = 7'h16; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_22 = 7'h16; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_21 = 7'h15; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_21 = 7'h15; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_20 = 7'h14; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_20 = 7'h14; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_19 = 7'h13; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_19 = 7'h13; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_18 = 7'h12; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_18 = 7'h12; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_17 = 7'h11; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_17 = 7'h11; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_16 = 7'h10; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_16 = 7'h10; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_15 = 7'hF; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_15 = 7'hF; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_14 = 7'hE; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_14 = 7'hE; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_13 = 7'hD; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_13 = 7'hD; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_12 = 7'hC; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_12 = 7'hC; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_11 = 7'hB; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_11 = 7'hB; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_10 = 7'hA; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_10 = 7'hA; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_9 = 7'h9; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_9 = 7'h9; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_8 = 7'h8; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_8 = 7'h8; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_7 = 7'h7; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_7 = 7'h7; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_6 = 7'h6; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_6 = 7'h6; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_5 = 7'h5; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_5 = 7'h5; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_4 = 7'h4; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_4 = 7'h4; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_3 = 7'h3; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_3 = 7'h3; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_2 = 7'h2; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_2 = 7'h2; // @[rename-maptable.scala:72:38] wire [6:0] _map_table_WIRE_1 = 7'h1; // @[rename-maptable.scala:71:34] wire [6:0] _com_map_table_WIRE_1 = 7'h1; // @[rename-maptable.scala:72:38] wire [6:0] _io_map_resps_1_prs1_T_4; // @[rename-maptable.scala:131:10] wire [6:0] _io_map_resps_1_prs2_T_4; // @[rename-maptable.scala:133:10] wire [6:0] _io_map_resps_1_stale_pdst_T_4; // @[rename-maptable.scala:137:10] wire [6:0] _io_map_resps_2_prs1_T_8; // @[rename-maptable.scala:131:10] wire [6:0] _io_map_resps_2_prs2_T_8; // @[rename-maptable.scala:133:10] wire [6:0] _io_map_resps_2_stale_pdst_T_8; // @[rename-maptable.scala:137:10] wire [6:0] io_map_resps_0_prs1_0; // @[rename-maptable.scala:43:7] wire [6:0] io_map_resps_0_prs2_0; // @[rename-maptable.scala:43:7] wire [6:0] io_map_resps_0_stale_pdst_0; // @[rename-maptable.scala:43:7] wire [6:0] io_map_resps_1_prs1_0; // @[rename-maptable.scala:43:7] wire [6:0] io_map_resps_1_prs2_0; // @[rename-maptable.scala:43:7] wire [6:0] io_map_resps_1_stale_pdst_0; // @[rename-maptable.scala:43:7] wire [6:0] io_map_resps_2_prs1_0; // @[rename-maptable.scala:43:7] wire [6:0] io_map_resps_2_prs2_0; // @[rename-maptable.scala:43:7] wire [6:0] io_map_resps_2_stale_pdst_0; // @[rename-maptable.scala:43:7] reg [6:0] map_table_0; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_0 = map_table_0; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_1; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_1 = map_table_1; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_2; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_2 = map_table_2; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_3; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_3 = map_table_3; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_4; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_4 = map_table_4; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_5; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_5 = map_table_5; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_6; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_6 = map_table_6; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_7; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_7 = map_table_7; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_8; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_8 = map_table_8; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_9; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_9 = map_table_9; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_10; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_10 = map_table_10; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_11; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_11 = map_table_11; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_12; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_12 = map_table_12; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_13; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_13 = map_table_13; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_14; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_14 = map_table_14; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_15; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_15 = map_table_15; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_16; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_16 = map_table_16; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_17; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_17 = map_table_17; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_18; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_18 = map_table_18; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_19; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_19 = map_table_19; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_20; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_20 = map_table_20; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_21; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_21 = map_table_21; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_22; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_22 = map_table_22; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_23; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_23 = map_table_23; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_24; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_24 = map_table_24; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_25; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_25 = map_table_25; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_26; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_26 = map_table_26; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_27; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_27 = map_table_27; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_28; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_28 = map_table_28; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_29; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_29 = map_table_29; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_30; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_30 = map_table_30; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] map_table_31; // @[rename-maptable.scala:71:26] wire [6:0] remap_table_0_31 = map_table_31; // @[rename-maptable.scala:71:26, :76:25] reg [6:0] com_map_table_0; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_0 = com_map_table_0; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_1; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_1 = com_map_table_1; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_2; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_2 = com_map_table_2; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_3; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_3 = com_map_table_3; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_4; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_4 = com_map_table_4; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_5; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_5 = com_map_table_5; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_6; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_6 = com_map_table_6; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_7; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_7 = com_map_table_7; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_8; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_8 = com_map_table_8; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_9; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_9 = com_map_table_9; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_10; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_10 = com_map_table_10; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_11; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_11 = com_map_table_11; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_12; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_12 = com_map_table_12; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_13; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_13 = com_map_table_13; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_14; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_14 = com_map_table_14; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_15; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_15 = com_map_table_15; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_16; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_16 = com_map_table_16; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_17; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_17 = com_map_table_17; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_18; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_18 = com_map_table_18; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_19; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_19 = com_map_table_19; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_20; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_20 = com_map_table_20; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_21; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_21 = com_map_table_21; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_22; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_22 = com_map_table_22; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_23; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_23 = com_map_table_23; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_24; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_24 = com_map_table_24; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_25; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_25 = com_map_table_25; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_26; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_26 = com_map_table_26; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_27; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_27 = com_map_table_27; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_28; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_28 = com_map_table_28; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_29; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_29 = com_map_table_29; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_30; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_30 = com_map_table_30; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] com_map_table_31; // @[rename-maptable.scala:72:30] wire [6:0] com_remap_table_0_31 = com_map_table_31; // @[rename-maptable.scala:72:30, :77:29] reg [6:0] br_snapshots_0_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_0_31; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_1_31; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_2_31; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_3_31; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_4_31; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_5_31; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_6_31; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_7_31; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_8_31; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_9_31; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_10_31; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_11_31; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_12_31; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_13_31; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_14_31; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_0; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_1; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_2; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_3; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_4; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_5; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_6; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_7; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_8; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_9; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_10; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_11; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_12; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_13; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_14; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_15; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_16; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_17; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_18; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_19; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_20; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_21; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_22; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_23; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_24; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_25; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_26; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_27; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_28; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_29; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_30; // @[rename-maptable.scala:73:25] reg [6:0] br_snapshots_15_31; // @[rename-maptable.scala:73:25] wire [6:0] remapped_row_1; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_1; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_2; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_3; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_4; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_5; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_6; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_7; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_8; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_9; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_10; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_11; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_12; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_13; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_14; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_15; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_16; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_17; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_18; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_19; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_20; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_21; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_22; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_23; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_24; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_25; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_26; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_27; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_28; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_29; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_30; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_1_31; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_1; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_2; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_3; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_4; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_5; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_6; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_7; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_8; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_9; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_10; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_11; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_12; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_13; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_14; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_15; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_16; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_17; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_18; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_19; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_20; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_21; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_22; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_23; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_24; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_25; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_26; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_27; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_28; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_29; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_30; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_2_31; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_1; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_2; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_3; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_4; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_5; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_6; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_7; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_8; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_9; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_10; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_11; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_12; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_13; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_14; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_15; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_16; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_17; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_18; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_19; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_20; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_21; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_22; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_23; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_24; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_25; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_26; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_27; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_28; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_29; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_30; // @[rename-maptable.scala:89:68] wire [6:0] remapped_row_3_31; // @[rename-maptable.scala:89:68] wire [6:0] remap_table_1_0; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_1; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_2; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_3; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_4; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_5; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_6; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_7; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_8; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_9; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_10; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_11; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_12; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_13; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_14; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_15; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_16; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_17; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_18; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_19; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_20; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_21; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_22; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_23; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_24; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_25; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_26; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_27; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_28; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_29; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_30; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_1_31; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_0; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_1; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_2; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_3; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_4; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_5; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_6; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_7; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_8; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_9; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_10; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_11; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_12; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_13; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_14; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_15; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_16; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_17; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_18; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_19; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_20; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_21; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_22; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_23; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_24; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_25; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_26; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_27; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_28; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_29; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_30; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_2_31; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_0; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_1; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_2; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_3; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_4; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_5; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_6; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_7; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_8; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_9; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_10; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_11; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_12; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_13; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_14; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_15; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_16; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_17; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_18; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_19; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_20; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_21; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_22; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_23; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_24; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_25; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_26; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_27; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_28; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_29; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_30; // @[rename-maptable.scala:76:25] wire [6:0] remap_table_3_31; // @[rename-maptable.scala:76:25] wire [6:0] com_remapped_row_1; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_1; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_2; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_3; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_4; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_5; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_6; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_7; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_8; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_9; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_10; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_11; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_12; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_13; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_14; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_15; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_16; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_17; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_18; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_19; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_20; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_21; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_22; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_23; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_24; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_25; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_26; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_27; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_28; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_29; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_30; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_1_31; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_1; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_2; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_3; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_4; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_5; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_6; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_7; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_8; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_9; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_10; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_11; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_12; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_13; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_14; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_15; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_16; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_17; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_18; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_19; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_20; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_21; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_22; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_23; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_24; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_25; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_26; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_27; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_28; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_29; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_30; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_2_31; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_1; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_2; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_3; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_4; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_5; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_6; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_7; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_8; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_9; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_10; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_11; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_12; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_13; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_14; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_15; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_16; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_17; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_18; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_19; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_20; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_21; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_22; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_23; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_24; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_25; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_26; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_27; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_28; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_29; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_30; // @[rename-maptable.scala:92:72] wire [6:0] com_remapped_row_3_31; // @[rename-maptable.scala:92:72] wire [6:0] com_remap_table_1_0; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_1; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_2; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_3; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_4; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_5; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_6; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_7; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_8; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_9; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_10; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_11; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_12; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_13; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_14; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_15; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_16; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_17; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_18; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_19; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_20; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_21; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_22; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_23; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_24; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_25; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_26; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_27; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_28; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_29; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_30; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_1_31; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_0; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_1; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_2; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_3; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_4; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_5; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_6; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_7; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_8; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_9; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_10; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_11; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_12; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_13; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_14; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_15; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_16; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_17; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_18; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_19; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_20; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_21; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_22; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_23; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_24; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_25; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_26; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_27; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_28; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_29; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_30; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_2_31; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_0; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_1; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_2; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_3; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_4; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_5; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_6; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_7; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_8; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_9; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_10; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_11; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_12; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_13; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_14; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_15; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_16; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_17; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_18; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_19; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_20; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_21; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_22; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_23; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_24; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_25; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_26; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_27; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_28; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_29; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_30; // @[rename-maptable.scala:77:29] wire [6:0] com_remap_table_3_31; // @[rename-maptable.scala:77:29] wire [63:0] _remap_ldsts_oh_T = 64'h1 << io_remap_reqs_0_ldst_0; // @[OneHot.scala:58:35] wire [31:0] _remap_ldsts_oh_T_1 = {32{io_remap_reqs_0_valid_0}}; // @[rename-maptable.scala:43:7, :81:75] wire [63:0] remap_ldsts_oh_0 = {32'h0, _remap_ldsts_oh_T[31:0] & _remap_ldsts_oh_T_1}; // @[OneHot.scala:58:35] wire [63:0] _remap_ldsts_oh_T_2 = 64'h1 << io_remap_reqs_1_ldst_0; // @[OneHot.scala:58:35] wire [31:0] _remap_ldsts_oh_T_3 = {32{io_remap_reqs_1_valid_0}}; // @[rename-maptable.scala:43:7, :81:75] wire [63:0] remap_ldsts_oh_1 = {32'h0, _remap_ldsts_oh_T_2[31:0] & _remap_ldsts_oh_T_3}; // @[OneHot.scala:58:35] wire [63:0] _remap_ldsts_oh_T_4 = 64'h1 << io_remap_reqs_2_ldst_0; // @[OneHot.scala:58:35] wire [31:0] _remap_ldsts_oh_T_5 = {32{io_remap_reqs_2_valid_0}}; // @[rename-maptable.scala:43:7, :81:75] wire [63:0] remap_ldsts_oh_2 = {32'h0, _remap_ldsts_oh_T_4[31:0] & _remap_ldsts_oh_T_5}; // @[OneHot.scala:58:35] wire [63:0] _com_remap_ldsts_oh_T = 64'h1 << io_com_remap_reqs_0_ldst_0; // @[OneHot.scala:58:35] wire [31:0] _com_remap_ldsts_oh_T_1 = {32{io_com_remap_reqs_0_valid_0}}; // @[rename-maptable.scala:43:7, :84:83] wire [63:0] com_remap_ldsts_oh_0 = {32'h0, _com_remap_ldsts_oh_T[31:0] & _com_remap_ldsts_oh_T_1}; // @[OneHot.scala:58:35] wire [63:0] _com_remap_ldsts_oh_T_2 = 64'h1 << io_com_remap_reqs_1_ldst_0; // @[OneHot.scala:58:35] wire [31:0] _com_remap_ldsts_oh_T_3 = {32{io_com_remap_reqs_1_valid_0}}; // @[rename-maptable.scala:43:7, :84:83] wire [63:0] com_remap_ldsts_oh_1 = {32'h0, _com_remap_ldsts_oh_T_2[31:0] & _com_remap_ldsts_oh_T_3}; // @[OneHot.scala:58:35] wire [63:0] _com_remap_ldsts_oh_T_4 = 64'h1 << io_com_remap_reqs_2_ldst_0; // @[OneHot.scala:58:35] wire [31:0] _com_remap_ldsts_oh_T_5 = {32{io_com_remap_reqs_2_valid_0}}; // @[rename-maptable.scala:43:7, :84:83] wire [63:0] com_remap_ldsts_oh_2 = {32'h0, _com_remap_ldsts_oh_T_4[31:0] & _com_remap_ldsts_oh_T_5}; // @[OneHot.scala:58:35] wire _remapped_row_T = remap_ldsts_oh_0[0]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_1 = remap_ldsts_oh_1[0]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_2 = remap_ldsts_oh_2[0]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1 = _remapped_row_T ? io_remap_reqs_0_pdst_0 : map_table_0; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_0 = remapped_row_1; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2 = _remapped_row_T_1 ? io_remap_reqs_1_pdst_0 : remapped_row_1; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_0 = remapped_row_2; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3 = _remapped_row_T_2 ? io_remap_reqs_2_pdst_0 : remapped_row_2; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_0 = remapped_row_3; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T = com_remap_ldsts_oh_0[0]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_1 = com_remap_ldsts_oh_1[0]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_2 = com_remap_ldsts_oh_2[0]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1 = _com_remapped_row_T ? io_com_remap_reqs_0_pdst_0 : com_map_table_0; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_0 = com_remapped_row_1; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2 = _com_remapped_row_T_1 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_0 = com_remapped_row_2; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3 = _com_remapped_row_T_2 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_0 = com_remapped_row_3; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_3 = remap_ldsts_oh_0[1]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_4 = remap_ldsts_oh_1[1]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_5 = remap_ldsts_oh_2[1]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_1 = _remapped_row_T_3 ? io_remap_reqs_0_pdst_0 : map_table_1; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_1 = remapped_row_1_1; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_1 = _remapped_row_T_4 ? io_remap_reqs_1_pdst_0 : remapped_row_1_1; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_1 = remapped_row_2_1; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_1 = _remapped_row_T_5 ? io_remap_reqs_2_pdst_0 : remapped_row_2_1; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_1 = remapped_row_3_1; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_3 = com_remap_ldsts_oh_0[1]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_4 = com_remap_ldsts_oh_1[1]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_5 = com_remap_ldsts_oh_2[1]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_1 = _com_remapped_row_T_3 ? io_com_remap_reqs_0_pdst_0 : com_map_table_1; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_1 = com_remapped_row_1_1; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_1 = _com_remapped_row_T_4 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_1; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_1 = com_remapped_row_2_1; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_1 = _com_remapped_row_T_5 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_1; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_1 = com_remapped_row_3_1; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_6 = remap_ldsts_oh_0[2]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_7 = remap_ldsts_oh_1[2]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_8 = remap_ldsts_oh_2[2]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_2 = _remapped_row_T_6 ? io_remap_reqs_0_pdst_0 : map_table_2; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_2 = remapped_row_1_2; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_2 = _remapped_row_T_7 ? io_remap_reqs_1_pdst_0 : remapped_row_1_2; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_2 = remapped_row_2_2; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_2 = _remapped_row_T_8 ? io_remap_reqs_2_pdst_0 : remapped_row_2_2; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_2 = remapped_row_3_2; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_6 = com_remap_ldsts_oh_0[2]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_7 = com_remap_ldsts_oh_1[2]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_8 = com_remap_ldsts_oh_2[2]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_2 = _com_remapped_row_T_6 ? io_com_remap_reqs_0_pdst_0 : com_map_table_2; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_2 = com_remapped_row_1_2; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_2 = _com_remapped_row_T_7 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_2; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_2 = com_remapped_row_2_2; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_2 = _com_remapped_row_T_8 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_2; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_2 = com_remapped_row_3_2; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_9 = remap_ldsts_oh_0[3]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_10 = remap_ldsts_oh_1[3]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_11 = remap_ldsts_oh_2[3]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_3 = _remapped_row_T_9 ? io_remap_reqs_0_pdst_0 : map_table_3; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_3 = remapped_row_1_3; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_3 = _remapped_row_T_10 ? io_remap_reqs_1_pdst_0 : remapped_row_1_3; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_3 = remapped_row_2_3; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_3 = _remapped_row_T_11 ? io_remap_reqs_2_pdst_0 : remapped_row_2_3; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_3 = remapped_row_3_3; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_9 = com_remap_ldsts_oh_0[3]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_10 = com_remap_ldsts_oh_1[3]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_11 = com_remap_ldsts_oh_2[3]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_3 = _com_remapped_row_T_9 ? io_com_remap_reqs_0_pdst_0 : com_map_table_3; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_3 = com_remapped_row_1_3; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_3 = _com_remapped_row_T_10 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_3; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_3 = com_remapped_row_2_3; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_3 = _com_remapped_row_T_11 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_3; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_3 = com_remapped_row_3_3; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_12 = remap_ldsts_oh_0[4]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_13 = remap_ldsts_oh_1[4]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_14 = remap_ldsts_oh_2[4]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_4 = _remapped_row_T_12 ? io_remap_reqs_0_pdst_0 : map_table_4; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_4 = remapped_row_1_4; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_4 = _remapped_row_T_13 ? io_remap_reqs_1_pdst_0 : remapped_row_1_4; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_4 = remapped_row_2_4; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_4 = _remapped_row_T_14 ? io_remap_reqs_2_pdst_0 : remapped_row_2_4; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_4 = remapped_row_3_4; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_12 = com_remap_ldsts_oh_0[4]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_13 = com_remap_ldsts_oh_1[4]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_14 = com_remap_ldsts_oh_2[4]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_4 = _com_remapped_row_T_12 ? io_com_remap_reqs_0_pdst_0 : com_map_table_4; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_4 = com_remapped_row_1_4; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_4 = _com_remapped_row_T_13 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_4; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_4 = com_remapped_row_2_4; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_4 = _com_remapped_row_T_14 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_4; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_4 = com_remapped_row_3_4; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_15 = remap_ldsts_oh_0[5]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_16 = remap_ldsts_oh_1[5]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_17 = remap_ldsts_oh_2[5]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_5 = _remapped_row_T_15 ? io_remap_reqs_0_pdst_0 : map_table_5; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_5 = remapped_row_1_5; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_5 = _remapped_row_T_16 ? io_remap_reqs_1_pdst_0 : remapped_row_1_5; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_5 = remapped_row_2_5; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_5 = _remapped_row_T_17 ? io_remap_reqs_2_pdst_0 : remapped_row_2_5; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_5 = remapped_row_3_5; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_15 = com_remap_ldsts_oh_0[5]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_16 = com_remap_ldsts_oh_1[5]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_17 = com_remap_ldsts_oh_2[5]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_5 = _com_remapped_row_T_15 ? io_com_remap_reqs_0_pdst_0 : com_map_table_5; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_5 = com_remapped_row_1_5; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_5 = _com_remapped_row_T_16 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_5; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_5 = com_remapped_row_2_5; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_5 = _com_remapped_row_T_17 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_5; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_5 = com_remapped_row_3_5; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_18 = remap_ldsts_oh_0[6]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_19 = remap_ldsts_oh_1[6]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_20 = remap_ldsts_oh_2[6]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_6 = _remapped_row_T_18 ? io_remap_reqs_0_pdst_0 : map_table_6; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_6 = remapped_row_1_6; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_6 = _remapped_row_T_19 ? io_remap_reqs_1_pdst_0 : remapped_row_1_6; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_6 = remapped_row_2_6; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_6 = _remapped_row_T_20 ? io_remap_reqs_2_pdst_0 : remapped_row_2_6; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_6 = remapped_row_3_6; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_18 = com_remap_ldsts_oh_0[6]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_19 = com_remap_ldsts_oh_1[6]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_20 = com_remap_ldsts_oh_2[6]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_6 = _com_remapped_row_T_18 ? io_com_remap_reqs_0_pdst_0 : com_map_table_6; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_6 = com_remapped_row_1_6; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_6 = _com_remapped_row_T_19 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_6; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_6 = com_remapped_row_2_6; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_6 = _com_remapped_row_T_20 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_6; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_6 = com_remapped_row_3_6; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_21 = remap_ldsts_oh_0[7]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_22 = remap_ldsts_oh_1[7]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_23 = remap_ldsts_oh_2[7]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_7 = _remapped_row_T_21 ? io_remap_reqs_0_pdst_0 : map_table_7; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_7 = remapped_row_1_7; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_7 = _remapped_row_T_22 ? io_remap_reqs_1_pdst_0 : remapped_row_1_7; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_7 = remapped_row_2_7; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_7 = _remapped_row_T_23 ? io_remap_reqs_2_pdst_0 : remapped_row_2_7; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_7 = remapped_row_3_7; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_21 = com_remap_ldsts_oh_0[7]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_22 = com_remap_ldsts_oh_1[7]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_23 = com_remap_ldsts_oh_2[7]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_7 = _com_remapped_row_T_21 ? io_com_remap_reqs_0_pdst_0 : com_map_table_7; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_7 = com_remapped_row_1_7; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_7 = _com_remapped_row_T_22 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_7; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_7 = com_remapped_row_2_7; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_7 = _com_remapped_row_T_23 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_7; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_7 = com_remapped_row_3_7; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_24 = remap_ldsts_oh_0[8]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_25 = remap_ldsts_oh_1[8]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_26 = remap_ldsts_oh_2[8]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_8 = _remapped_row_T_24 ? io_remap_reqs_0_pdst_0 : map_table_8; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_8 = remapped_row_1_8; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_8 = _remapped_row_T_25 ? io_remap_reqs_1_pdst_0 : remapped_row_1_8; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_8 = remapped_row_2_8; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_8 = _remapped_row_T_26 ? io_remap_reqs_2_pdst_0 : remapped_row_2_8; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_8 = remapped_row_3_8; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_24 = com_remap_ldsts_oh_0[8]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_25 = com_remap_ldsts_oh_1[8]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_26 = com_remap_ldsts_oh_2[8]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_8 = _com_remapped_row_T_24 ? io_com_remap_reqs_0_pdst_0 : com_map_table_8; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_8 = com_remapped_row_1_8; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_8 = _com_remapped_row_T_25 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_8; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_8 = com_remapped_row_2_8; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_8 = _com_remapped_row_T_26 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_8; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_8 = com_remapped_row_3_8; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_27 = remap_ldsts_oh_0[9]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_28 = remap_ldsts_oh_1[9]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_29 = remap_ldsts_oh_2[9]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_9 = _remapped_row_T_27 ? io_remap_reqs_0_pdst_0 : map_table_9; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_9 = remapped_row_1_9; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_9 = _remapped_row_T_28 ? io_remap_reqs_1_pdst_0 : remapped_row_1_9; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_9 = remapped_row_2_9; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_9 = _remapped_row_T_29 ? io_remap_reqs_2_pdst_0 : remapped_row_2_9; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_9 = remapped_row_3_9; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_27 = com_remap_ldsts_oh_0[9]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_28 = com_remap_ldsts_oh_1[9]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_29 = com_remap_ldsts_oh_2[9]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_9 = _com_remapped_row_T_27 ? io_com_remap_reqs_0_pdst_0 : com_map_table_9; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_9 = com_remapped_row_1_9; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_9 = _com_remapped_row_T_28 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_9; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_9 = com_remapped_row_2_9; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_9 = _com_remapped_row_T_29 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_9; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_9 = com_remapped_row_3_9; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_30 = remap_ldsts_oh_0[10]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_31 = remap_ldsts_oh_1[10]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_32 = remap_ldsts_oh_2[10]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_10 = _remapped_row_T_30 ? io_remap_reqs_0_pdst_0 : map_table_10; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_10 = remapped_row_1_10; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_10 = _remapped_row_T_31 ? io_remap_reqs_1_pdst_0 : remapped_row_1_10; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_10 = remapped_row_2_10; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_10 = _remapped_row_T_32 ? io_remap_reqs_2_pdst_0 : remapped_row_2_10; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_10 = remapped_row_3_10; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_30 = com_remap_ldsts_oh_0[10]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_31 = com_remap_ldsts_oh_1[10]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_32 = com_remap_ldsts_oh_2[10]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_10 = _com_remapped_row_T_30 ? io_com_remap_reqs_0_pdst_0 : com_map_table_10; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_10 = com_remapped_row_1_10; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_10 = _com_remapped_row_T_31 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_10; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_10 = com_remapped_row_2_10; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_10 = _com_remapped_row_T_32 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_10; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_10 = com_remapped_row_3_10; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_33 = remap_ldsts_oh_0[11]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_34 = remap_ldsts_oh_1[11]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_35 = remap_ldsts_oh_2[11]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_11 = _remapped_row_T_33 ? io_remap_reqs_0_pdst_0 : map_table_11; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_11 = remapped_row_1_11; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_11 = _remapped_row_T_34 ? io_remap_reqs_1_pdst_0 : remapped_row_1_11; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_11 = remapped_row_2_11; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_11 = _remapped_row_T_35 ? io_remap_reqs_2_pdst_0 : remapped_row_2_11; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_11 = remapped_row_3_11; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_33 = com_remap_ldsts_oh_0[11]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_34 = com_remap_ldsts_oh_1[11]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_35 = com_remap_ldsts_oh_2[11]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_11 = _com_remapped_row_T_33 ? io_com_remap_reqs_0_pdst_0 : com_map_table_11; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_11 = com_remapped_row_1_11; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_11 = _com_remapped_row_T_34 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_11; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_11 = com_remapped_row_2_11; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_11 = _com_remapped_row_T_35 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_11; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_11 = com_remapped_row_3_11; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_36 = remap_ldsts_oh_0[12]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_37 = remap_ldsts_oh_1[12]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_38 = remap_ldsts_oh_2[12]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_12 = _remapped_row_T_36 ? io_remap_reqs_0_pdst_0 : map_table_12; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_12 = remapped_row_1_12; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_12 = _remapped_row_T_37 ? io_remap_reqs_1_pdst_0 : remapped_row_1_12; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_12 = remapped_row_2_12; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_12 = _remapped_row_T_38 ? io_remap_reqs_2_pdst_0 : remapped_row_2_12; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_12 = remapped_row_3_12; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_36 = com_remap_ldsts_oh_0[12]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_37 = com_remap_ldsts_oh_1[12]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_38 = com_remap_ldsts_oh_2[12]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_12 = _com_remapped_row_T_36 ? io_com_remap_reqs_0_pdst_0 : com_map_table_12; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_12 = com_remapped_row_1_12; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_12 = _com_remapped_row_T_37 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_12; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_12 = com_remapped_row_2_12; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_12 = _com_remapped_row_T_38 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_12; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_12 = com_remapped_row_3_12; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_39 = remap_ldsts_oh_0[13]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_40 = remap_ldsts_oh_1[13]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_41 = remap_ldsts_oh_2[13]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_13 = _remapped_row_T_39 ? io_remap_reqs_0_pdst_0 : map_table_13; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_13 = remapped_row_1_13; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_13 = _remapped_row_T_40 ? io_remap_reqs_1_pdst_0 : remapped_row_1_13; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_13 = remapped_row_2_13; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_13 = _remapped_row_T_41 ? io_remap_reqs_2_pdst_0 : remapped_row_2_13; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_13 = remapped_row_3_13; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_39 = com_remap_ldsts_oh_0[13]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_40 = com_remap_ldsts_oh_1[13]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_41 = com_remap_ldsts_oh_2[13]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_13 = _com_remapped_row_T_39 ? io_com_remap_reqs_0_pdst_0 : com_map_table_13; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_13 = com_remapped_row_1_13; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_13 = _com_remapped_row_T_40 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_13; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_13 = com_remapped_row_2_13; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_13 = _com_remapped_row_T_41 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_13; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_13 = com_remapped_row_3_13; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_42 = remap_ldsts_oh_0[14]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_43 = remap_ldsts_oh_1[14]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_44 = remap_ldsts_oh_2[14]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_14 = _remapped_row_T_42 ? io_remap_reqs_0_pdst_0 : map_table_14; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_14 = remapped_row_1_14; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_14 = _remapped_row_T_43 ? io_remap_reqs_1_pdst_0 : remapped_row_1_14; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_14 = remapped_row_2_14; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_14 = _remapped_row_T_44 ? io_remap_reqs_2_pdst_0 : remapped_row_2_14; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_14 = remapped_row_3_14; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_42 = com_remap_ldsts_oh_0[14]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_43 = com_remap_ldsts_oh_1[14]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_44 = com_remap_ldsts_oh_2[14]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_14 = _com_remapped_row_T_42 ? io_com_remap_reqs_0_pdst_0 : com_map_table_14; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_14 = com_remapped_row_1_14; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_14 = _com_remapped_row_T_43 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_14; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_14 = com_remapped_row_2_14; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_14 = _com_remapped_row_T_44 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_14; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_14 = com_remapped_row_3_14; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_45 = remap_ldsts_oh_0[15]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_46 = remap_ldsts_oh_1[15]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_47 = remap_ldsts_oh_2[15]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_15 = _remapped_row_T_45 ? io_remap_reqs_0_pdst_0 : map_table_15; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_15 = remapped_row_1_15; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_15 = _remapped_row_T_46 ? io_remap_reqs_1_pdst_0 : remapped_row_1_15; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_15 = remapped_row_2_15; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_15 = _remapped_row_T_47 ? io_remap_reqs_2_pdst_0 : remapped_row_2_15; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_15 = remapped_row_3_15; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_45 = com_remap_ldsts_oh_0[15]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_46 = com_remap_ldsts_oh_1[15]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_47 = com_remap_ldsts_oh_2[15]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_15 = _com_remapped_row_T_45 ? io_com_remap_reqs_0_pdst_0 : com_map_table_15; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_15 = com_remapped_row_1_15; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_15 = _com_remapped_row_T_46 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_15; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_15 = com_remapped_row_2_15; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_15 = _com_remapped_row_T_47 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_15; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_15 = com_remapped_row_3_15; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_48 = remap_ldsts_oh_0[16]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_49 = remap_ldsts_oh_1[16]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_50 = remap_ldsts_oh_2[16]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_16 = _remapped_row_T_48 ? io_remap_reqs_0_pdst_0 : map_table_16; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_16 = remapped_row_1_16; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_16 = _remapped_row_T_49 ? io_remap_reqs_1_pdst_0 : remapped_row_1_16; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_16 = remapped_row_2_16; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_16 = _remapped_row_T_50 ? io_remap_reqs_2_pdst_0 : remapped_row_2_16; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_16 = remapped_row_3_16; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_48 = com_remap_ldsts_oh_0[16]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_49 = com_remap_ldsts_oh_1[16]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_50 = com_remap_ldsts_oh_2[16]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_16 = _com_remapped_row_T_48 ? io_com_remap_reqs_0_pdst_0 : com_map_table_16; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_16 = com_remapped_row_1_16; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_16 = _com_remapped_row_T_49 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_16; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_16 = com_remapped_row_2_16; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_16 = _com_remapped_row_T_50 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_16; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_16 = com_remapped_row_3_16; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_51 = remap_ldsts_oh_0[17]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_52 = remap_ldsts_oh_1[17]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_53 = remap_ldsts_oh_2[17]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_17 = _remapped_row_T_51 ? io_remap_reqs_0_pdst_0 : map_table_17; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_17 = remapped_row_1_17; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_17 = _remapped_row_T_52 ? io_remap_reqs_1_pdst_0 : remapped_row_1_17; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_17 = remapped_row_2_17; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_17 = _remapped_row_T_53 ? io_remap_reqs_2_pdst_0 : remapped_row_2_17; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_17 = remapped_row_3_17; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_51 = com_remap_ldsts_oh_0[17]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_52 = com_remap_ldsts_oh_1[17]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_53 = com_remap_ldsts_oh_2[17]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_17 = _com_remapped_row_T_51 ? io_com_remap_reqs_0_pdst_0 : com_map_table_17; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_17 = com_remapped_row_1_17; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_17 = _com_remapped_row_T_52 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_17; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_17 = com_remapped_row_2_17; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_17 = _com_remapped_row_T_53 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_17; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_17 = com_remapped_row_3_17; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_54 = remap_ldsts_oh_0[18]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_55 = remap_ldsts_oh_1[18]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_56 = remap_ldsts_oh_2[18]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_18 = _remapped_row_T_54 ? io_remap_reqs_0_pdst_0 : map_table_18; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_18 = remapped_row_1_18; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_18 = _remapped_row_T_55 ? io_remap_reqs_1_pdst_0 : remapped_row_1_18; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_18 = remapped_row_2_18; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_18 = _remapped_row_T_56 ? io_remap_reqs_2_pdst_0 : remapped_row_2_18; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_18 = remapped_row_3_18; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_54 = com_remap_ldsts_oh_0[18]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_55 = com_remap_ldsts_oh_1[18]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_56 = com_remap_ldsts_oh_2[18]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_18 = _com_remapped_row_T_54 ? io_com_remap_reqs_0_pdst_0 : com_map_table_18; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_18 = com_remapped_row_1_18; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_18 = _com_remapped_row_T_55 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_18; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_18 = com_remapped_row_2_18; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_18 = _com_remapped_row_T_56 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_18; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_18 = com_remapped_row_3_18; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_57 = remap_ldsts_oh_0[19]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_58 = remap_ldsts_oh_1[19]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_59 = remap_ldsts_oh_2[19]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_19 = _remapped_row_T_57 ? io_remap_reqs_0_pdst_0 : map_table_19; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_19 = remapped_row_1_19; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_19 = _remapped_row_T_58 ? io_remap_reqs_1_pdst_0 : remapped_row_1_19; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_19 = remapped_row_2_19; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_19 = _remapped_row_T_59 ? io_remap_reqs_2_pdst_0 : remapped_row_2_19; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_19 = remapped_row_3_19; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_57 = com_remap_ldsts_oh_0[19]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_58 = com_remap_ldsts_oh_1[19]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_59 = com_remap_ldsts_oh_2[19]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_19 = _com_remapped_row_T_57 ? io_com_remap_reqs_0_pdst_0 : com_map_table_19; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_19 = com_remapped_row_1_19; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_19 = _com_remapped_row_T_58 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_19; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_19 = com_remapped_row_2_19; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_19 = _com_remapped_row_T_59 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_19; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_19 = com_remapped_row_3_19; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_60 = remap_ldsts_oh_0[20]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_61 = remap_ldsts_oh_1[20]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_62 = remap_ldsts_oh_2[20]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_20 = _remapped_row_T_60 ? io_remap_reqs_0_pdst_0 : map_table_20; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_20 = remapped_row_1_20; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_20 = _remapped_row_T_61 ? io_remap_reqs_1_pdst_0 : remapped_row_1_20; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_20 = remapped_row_2_20; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_20 = _remapped_row_T_62 ? io_remap_reqs_2_pdst_0 : remapped_row_2_20; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_20 = remapped_row_3_20; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_60 = com_remap_ldsts_oh_0[20]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_61 = com_remap_ldsts_oh_1[20]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_62 = com_remap_ldsts_oh_2[20]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_20 = _com_remapped_row_T_60 ? io_com_remap_reqs_0_pdst_0 : com_map_table_20; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_20 = com_remapped_row_1_20; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_20 = _com_remapped_row_T_61 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_20; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_20 = com_remapped_row_2_20; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_20 = _com_remapped_row_T_62 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_20; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_20 = com_remapped_row_3_20; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_63 = remap_ldsts_oh_0[21]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_64 = remap_ldsts_oh_1[21]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_65 = remap_ldsts_oh_2[21]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_21 = _remapped_row_T_63 ? io_remap_reqs_0_pdst_0 : map_table_21; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_21 = remapped_row_1_21; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_21 = _remapped_row_T_64 ? io_remap_reqs_1_pdst_0 : remapped_row_1_21; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_21 = remapped_row_2_21; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_21 = _remapped_row_T_65 ? io_remap_reqs_2_pdst_0 : remapped_row_2_21; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_21 = remapped_row_3_21; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_63 = com_remap_ldsts_oh_0[21]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_64 = com_remap_ldsts_oh_1[21]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_65 = com_remap_ldsts_oh_2[21]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_21 = _com_remapped_row_T_63 ? io_com_remap_reqs_0_pdst_0 : com_map_table_21; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_21 = com_remapped_row_1_21; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_21 = _com_remapped_row_T_64 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_21; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_21 = com_remapped_row_2_21; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_21 = _com_remapped_row_T_65 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_21; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_21 = com_remapped_row_3_21; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_66 = remap_ldsts_oh_0[22]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_67 = remap_ldsts_oh_1[22]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_68 = remap_ldsts_oh_2[22]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_22 = _remapped_row_T_66 ? io_remap_reqs_0_pdst_0 : map_table_22; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_22 = remapped_row_1_22; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_22 = _remapped_row_T_67 ? io_remap_reqs_1_pdst_0 : remapped_row_1_22; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_22 = remapped_row_2_22; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_22 = _remapped_row_T_68 ? io_remap_reqs_2_pdst_0 : remapped_row_2_22; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_22 = remapped_row_3_22; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_66 = com_remap_ldsts_oh_0[22]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_67 = com_remap_ldsts_oh_1[22]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_68 = com_remap_ldsts_oh_2[22]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_22 = _com_remapped_row_T_66 ? io_com_remap_reqs_0_pdst_0 : com_map_table_22; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_22 = com_remapped_row_1_22; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_22 = _com_remapped_row_T_67 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_22; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_22 = com_remapped_row_2_22; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_22 = _com_remapped_row_T_68 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_22; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_22 = com_remapped_row_3_22; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_69 = remap_ldsts_oh_0[23]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_70 = remap_ldsts_oh_1[23]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_71 = remap_ldsts_oh_2[23]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_23 = _remapped_row_T_69 ? io_remap_reqs_0_pdst_0 : map_table_23; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_23 = remapped_row_1_23; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_23 = _remapped_row_T_70 ? io_remap_reqs_1_pdst_0 : remapped_row_1_23; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_23 = remapped_row_2_23; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_23 = _remapped_row_T_71 ? io_remap_reqs_2_pdst_0 : remapped_row_2_23; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_23 = remapped_row_3_23; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_69 = com_remap_ldsts_oh_0[23]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_70 = com_remap_ldsts_oh_1[23]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_71 = com_remap_ldsts_oh_2[23]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_23 = _com_remapped_row_T_69 ? io_com_remap_reqs_0_pdst_0 : com_map_table_23; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_23 = com_remapped_row_1_23; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_23 = _com_remapped_row_T_70 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_23; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_23 = com_remapped_row_2_23; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_23 = _com_remapped_row_T_71 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_23; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_23 = com_remapped_row_3_23; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_72 = remap_ldsts_oh_0[24]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_73 = remap_ldsts_oh_1[24]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_74 = remap_ldsts_oh_2[24]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_24 = _remapped_row_T_72 ? io_remap_reqs_0_pdst_0 : map_table_24; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_24 = remapped_row_1_24; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_24 = _remapped_row_T_73 ? io_remap_reqs_1_pdst_0 : remapped_row_1_24; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_24 = remapped_row_2_24; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_24 = _remapped_row_T_74 ? io_remap_reqs_2_pdst_0 : remapped_row_2_24; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_24 = remapped_row_3_24; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_72 = com_remap_ldsts_oh_0[24]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_73 = com_remap_ldsts_oh_1[24]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_74 = com_remap_ldsts_oh_2[24]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_24 = _com_remapped_row_T_72 ? io_com_remap_reqs_0_pdst_0 : com_map_table_24; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_24 = com_remapped_row_1_24; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_24 = _com_remapped_row_T_73 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_24; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_24 = com_remapped_row_2_24; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_24 = _com_remapped_row_T_74 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_24; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_24 = com_remapped_row_3_24; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_75 = remap_ldsts_oh_0[25]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_76 = remap_ldsts_oh_1[25]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_77 = remap_ldsts_oh_2[25]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_25 = _remapped_row_T_75 ? io_remap_reqs_0_pdst_0 : map_table_25; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_25 = remapped_row_1_25; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_25 = _remapped_row_T_76 ? io_remap_reqs_1_pdst_0 : remapped_row_1_25; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_25 = remapped_row_2_25; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_25 = _remapped_row_T_77 ? io_remap_reqs_2_pdst_0 : remapped_row_2_25; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_25 = remapped_row_3_25; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_75 = com_remap_ldsts_oh_0[25]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_76 = com_remap_ldsts_oh_1[25]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_77 = com_remap_ldsts_oh_2[25]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_25 = _com_remapped_row_T_75 ? io_com_remap_reqs_0_pdst_0 : com_map_table_25; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_25 = com_remapped_row_1_25; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_25 = _com_remapped_row_T_76 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_25; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_25 = com_remapped_row_2_25; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_25 = _com_remapped_row_T_77 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_25; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_25 = com_remapped_row_3_25; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_78 = remap_ldsts_oh_0[26]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_79 = remap_ldsts_oh_1[26]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_80 = remap_ldsts_oh_2[26]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_26 = _remapped_row_T_78 ? io_remap_reqs_0_pdst_0 : map_table_26; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_26 = remapped_row_1_26; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_26 = _remapped_row_T_79 ? io_remap_reqs_1_pdst_0 : remapped_row_1_26; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_26 = remapped_row_2_26; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_26 = _remapped_row_T_80 ? io_remap_reqs_2_pdst_0 : remapped_row_2_26; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_26 = remapped_row_3_26; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_78 = com_remap_ldsts_oh_0[26]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_79 = com_remap_ldsts_oh_1[26]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_80 = com_remap_ldsts_oh_2[26]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_26 = _com_remapped_row_T_78 ? io_com_remap_reqs_0_pdst_0 : com_map_table_26; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_26 = com_remapped_row_1_26; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_26 = _com_remapped_row_T_79 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_26; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_26 = com_remapped_row_2_26; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_26 = _com_remapped_row_T_80 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_26; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_26 = com_remapped_row_3_26; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_81 = remap_ldsts_oh_0[27]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_82 = remap_ldsts_oh_1[27]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_83 = remap_ldsts_oh_2[27]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_27 = _remapped_row_T_81 ? io_remap_reqs_0_pdst_0 : map_table_27; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_27 = remapped_row_1_27; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_27 = _remapped_row_T_82 ? io_remap_reqs_1_pdst_0 : remapped_row_1_27; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_27 = remapped_row_2_27; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_27 = _remapped_row_T_83 ? io_remap_reqs_2_pdst_0 : remapped_row_2_27; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_27 = remapped_row_3_27; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_81 = com_remap_ldsts_oh_0[27]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_82 = com_remap_ldsts_oh_1[27]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_83 = com_remap_ldsts_oh_2[27]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_27 = _com_remapped_row_T_81 ? io_com_remap_reqs_0_pdst_0 : com_map_table_27; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_27 = com_remapped_row_1_27; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_27 = _com_remapped_row_T_82 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_27; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_27 = com_remapped_row_2_27; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_27 = _com_remapped_row_T_83 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_27; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_27 = com_remapped_row_3_27; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_84 = remap_ldsts_oh_0[28]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_85 = remap_ldsts_oh_1[28]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_86 = remap_ldsts_oh_2[28]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_28 = _remapped_row_T_84 ? io_remap_reqs_0_pdst_0 : map_table_28; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_28 = remapped_row_1_28; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_28 = _remapped_row_T_85 ? io_remap_reqs_1_pdst_0 : remapped_row_1_28; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_28 = remapped_row_2_28; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_28 = _remapped_row_T_86 ? io_remap_reqs_2_pdst_0 : remapped_row_2_28; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_28 = remapped_row_3_28; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_84 = com_remap_ldsts_oh_0[28]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_85 = com_remap_ldsts_oh_1[28]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_86 = com_remap_ldsts_oh_2[28]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_28 = _com_remapped_row_T_84 ? io_com_remap_reqs_0_pdst_0 : com_map_table_28; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_28 = com_remapped_row_1_28; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_28 = _com_remapped_row_T_85 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_28; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_28 = com_remapped_row_2_28; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_28 = _com_remapped_row_T_86 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_28; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_28 = com_remapped_row_3_28; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_87 = remap_ldsts_oh_0[29]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_88 = remap_ldsts_oh_1[29]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_89 = remap_ldsts_oh_2[29]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_29 = _remapped_row_T_87 ? io_remap_reqs_0_pdst_0 : map_table_29; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_29 = remapped_row_1_29; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_29 = _remapped_row_T_88 ? io_remap_reqs_1_pdst_0 : remapped_row_1_29; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_29 = remapped_row_2_29; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_29 = _remapped_row_T_89 ? io_remap_reqs_2_pdst_0 : remapped_row_2_29; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_29 = remapped_row_3_29; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_87 = com_remap_ldsts_oh_0[29]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_88 = com_remap_ldsts_oh_1[29]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_89 = com_remap_ldsts_oh_2[29]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_29 = _com_remapped_row_T_87 ? io_com_remap_reqs_0_pdst_0 : com_map_table_29; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_29 = com_remapped_row_1_29; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_29 = _com_remapped_row_T_88 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_29; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_29 = com_remapped_row_2_29; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_29 = _com_remapped_row_T_89 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_29; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_29 = com_remapped_row_3_29; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_90 = remap_ldsts_oh_0[30]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_91 = remap_ldsts_oh_1[30]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_92 = remap_ldsts_oh_2[30]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_30 = _remapped_row_T_90 ? io_remap_reqs_0_pdst_0 : map_table_30; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_30 = remapped_row_1_30; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_30 = _remapped_row_T_91 ? io_remap_reqs_1_pdst_0 : remapped_row_1_30; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_30 = remapped_row_2_30; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_30 = _remapped_row_T_92 ? io_remap_reqs_2_pdst_0 : remapped_row_2_30; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_30 = remapped_row_3_30; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_90 = com_remap_ldsts_oh_0[30]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_91 = com_remap_ldsts_oh_1[30]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_92 = com_remap_ldsts_oh_2[30]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_30 = _com_remapped_row_T_90 ? io_com_remap_reqs_0_pdst_0 : com_map_table_30; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_30 = com_remapped_row_1_30; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_30 = _com_remapped_row_T_91 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_30; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_30 = com_remapped_row_2_30; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_30 = _com_remapped_row_T_92 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_30; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_30 = com_remapped_row_3_30; // @[rename-maptable.scala:77:29, :92:72] wire _remapped_row_T_93 = remap_ldsts_oh_0[31]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_94 = remap_ldsts_oh_1[31]; // @[rename-maptable.scala:81:69, :88:56] wire _remapped_row_T_95 = remap_ldsts_oh_2[31]; // @[rename-maptable.scala:81:69, :88:56] assign remapped_row_1_31 = _remapped_row_T_93 ? io_remap_reqs_0_pdst_0 : map_table_31; // @[rename-maptable.scala:43:7, :71:26, :88:56, :89:68] assign remap_table_1_31 = remapped_row_1_31; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_2_31 = _remapped_row_T_94 ? io_remap_reqs_1_pdst_0 : remapped_row_1_31; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_2_31 = remapped_row_2_31; // @[rename-maptable.scala:76:25, :89:68] assign remapped_row_3_31 = _remapped_row_T_95 ? io_remap_reqs_2_pdst_0 : remapped_row_2_31; // @[rename-maptable.scala:43:7, :88:56, :89:68] assign remap_table_3_31 = remapped_row_3_31; // @[rename-maptable.scala:76:25, :89:68] wire _com_remapped_row_T_93 = com_remap_ldsts_oh_0[31]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_94 = com_remap_ldsts_oh_1[31]; // @[rename-maptable.scala:84:77, :91:64] wire _com_remapped_row_T_95 = com_remap_ldsts_oh_2[31]; // @[rename-maptable.scala:84:77, :91:64] assign com_remapped_row_1_31 = _com_remapped_row_T_93 ? io_com_remap_reqs_0_pdst_0 : com_map_table_31; // @[rename-maptable.scala:43:7, :72:30, :91:64, :92:72] assign com_remap_table_1_31 = com_remapped_row_1_31; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_2_31 = _com_remapped_row_T_94 ? io_com_remap_reqs_1_pdst_0 : com_remapped_row_1_31; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_2_31 = com_remapped_row_2_31; // @[rename-maptable.scala:77:29, :92:72] assign com_remapped_row_3_31 = _com_remapped_row_T_95 ? io_com_remap_reqs_2_pdst_0 : com_remapped_row_2_31; // @[rename-maptable.scala:43:7, :91:64, :92:72] assign com_remap_table_3_31 = com_remapped_row_3_31; // @[rename-maptable.scala:77:29, :92:72] wire [4:0] _io_map_resps_0_prs1_T = io_map_reqs_0_lrs1_0[4:0]; // @[rename-maptable.scala:43:7] wire [31:0][6:0] _GEN = {{map_table_31}, {map_table_30}, {map_table_29}, {map_table_28}, {map_table_27}, {map_table_26}, {map_table_25}, {map_table_24}, {map_table_23}, {map_table_22}, {map_table_21}, {map_table_20}, {map_table_19}, {map_table_18}, {map_table_17}, {map_table_16}, {map_table_15}, {map_table_14}, {map_table_13}, {map_table_12}, {map_table_11}, {map_table_10}, {map_table_9}, {map_table_8}, {map_table_7}, {map_table_6}, {map_table_5}, {map_table_4}, {map_table_3}, {map_table_2}, {map_table_1}, {map_table_0}}; // @[rename-maptable.scala:71:26, :130:32] assign io_map_resps_0_prs1_0 = _GEN[_io_map_resps_0_prs1_T]; // @[rename-maptable.scala:43:7, :130:32] wire [4:0] _io_map_resps_0_prs2_T = io_map_reqs_0_lrs2_0[4:0]; // @[rename-maptable.scala:43:7] assign io_map_resps_0_prs2_0 = _GEN[_io_map_resps_0_prs2_T]; // @[rename-maptable.scala:43:7, :130:32, :132:32] wire [4:0] _io_map_resps_0_prs3_T = io_map_reqs_0_lrs3_0[4:0]; // @[rename-maptable.scala:43:7] wire [4:0] _io_map_resps_0_stale_pdst_T = io_map_reqs_0_ldst_0[4:0]; // @[rename-maptable.scala:43:7] assign io_map_resps_0_stale_pdst_0 = _GEN[_io_map_resps_0_stale_pdst_T]; // @[rename-maptable.scala:43:7, :130:32, :136:32] wire [4:0] _io_map_resps_1_prs1_T = io_map_reqs_1_lrs1_0[4:0]; // @[rename-maptable.scala:43:7] wire _io_map_resps_1_prs1_T_2 = io_remap_reqs_0_ldst_0 == io_map_reqs_1_lrs1_0; // @[rename-maptable.scala:43:7, :131:71] assign _io_map_resps_1_prs1_T_4 = _GEN[_io_map_resps_1_prs1_T]; // @[rename-maptable.scala:130:32, :131:10] assign io_map_resps_1_prs1_0 = _io_map_resps_1_prs1_T_4; // @[rename-maptable.scala:43:7, :131:10] wire [4:0] _io_map_resps_1_prs2_T = io_map_reqs_1_lrs2_0[4:0]; // @[rename-maptable.scala:43:7] wire _io_map_resps_1_prs2_T_2 = io_remap_reqs_0_ldst_0 == io_map_reqs_1_lrs2_0; // @[rename-maptable.scala:43:7, :133:71] assign _io_map_resps_1_prs2_T_4 = _GEN[_io_map_resps_1_prs2_T]; // @[rename-maptable.scala:130:32, :133:10] assign io_map_resps_1_prs2_0 = _io_map_resps_1_prs2_T_4; // @[rename-maptable.scala:43:7, :133:10] wire [4:0] _io_map_resps_1_prs3_T = io_map_reqs_1_lrs3_0[4:0]; // @[rename-maptable.scala:43:7] wire _io_map_resps_1_prs3_T_2 = io_remap_reqs_0_ldst_0 == io_map_reqs_1_lrs3_0; // @[rename-maptable.scala:43:7, :135:71] wire [6:0] _io_map_resps_1_prs3_T_4 = _GEN[_io_map_resps_1_prs3_T]; // @[rename-maptable.scala:130:32, :135:10] wire [4:0] _io_map_resps_1_stale_pdst_T = io_map_reqs_1_ldst_0[4:0]; // @[rename-maptable.scala:43:7] wire _io_map_resps_1_stale_pdst_T_2 = io_remap_reqs_0_ldst_0 == io_map_reqs_1_ldst_0; // @[rename-maptable.scala:43:7, :137:71] assign _io_map_resps_1_stale_pdst_T_4 = _GEN[_io_map_resps_1_stale_pdst_T]; // @[rename-maptable.scala:130:32, :137:10] assign io_map_resps_1_stale_pdst_0 = _io_map_resps_1_stale_pdst_T_4; // @[rename-maptable.scala:43:7, :137:10] wire [4:0] _io_map_resps_2_prs1_T = io_map_reqs_2_lrs1_0[4:0]; // @[rename-maptable.scala:43:7] wire _io_map_resps_2_prs1_T_2 = io_remap_reqs_0_ldst_0 == io_map_reqs_2_lrs1_0; // @[rename-maptable.scala:43:7, :131:71] wire [6:0] _io_map_resps_2_prs1_T_4 = _GEN[_io_map_resps_2_prs1_T]; // @[rename-maptable.scala:130:32, :131:10] assign _io_map_resps_2_prs1_T_8 = _io_map_resps_2_prs1_T_4; // @[rename-maptable.scala:131:10] wire _io_map_resps_2_prs1_T_6 = io_remap_reqs_1_ldst_0 == io_map_reqs_2_lrs1_0; // @[rename-maptable.scala:43:7, :131:71] assign io_map_resps_2_prs1_0 = _io_map_resps_2_prs1_T_8; // @[rename-maptable.scala:43:7, :131:10] wire [4:0] _io_map_resps_2_prs2_T = io_map_reqs_2_lrs2_0[4:0]; // @[rename-maptable.scala:43:7] wire _io_map_resps_2_prs2_T_2 = io_remap_reqs_0_ldst_0 == io_map_reqs_2_lrs2_0; // @[rename-maptable.scala:43:7, :133:71] wire [6:0] _io_map_resps_2_prs2_T_4 = _GEN[_io_map_resps_2_prs2_T]; // @[rename-maptable.scala:130:32, :133:10] assign _io_map_resps_2_prs2_T_8 = _io_map_resps_2_prs2_T_4; // @[rename-maptable.scala:133:10] wire _io_map_resps_2_prs2_T_6 = io_remap_reqs_1_ldst_0 == io_map_reqs_2_lrs2_0; // @[rename-maptable.scala:43:7, :133:71] assign io_map_resps_2_prs2_0 = _io_map_resps_2_prs2_T_8; // @[rename-maptable.scala:43:7, :133:10] wire [4:0] _io_map_resps_2_prs3_T = io_map_reqs_2_lrs3_0[4:0]; // @[rename-maptable.scala:43:7] wire _io_map_resps_2_prs3_T_2 = io_remap_reqs_0_ldst_0 == io_map_reqs_2_lrs3_0; // @[rename-maptable.scala:43:7, :135:71] wire [6:0] _io_map_resps_2_prs3_T_4 = _GEN[_io_map_resps_2_prs3_T]; // @[rename-maptable.scala:130:32, :135:10] wire [6:0] _io_map_resps_2_prs3_T_8 = _io_map_resps_2_prs3_T_4; // @[rename-maptable.scala:135:10] wire _io_map_resps_2_prs3_T_6 = io_remap_reqs_1_ldst_0 == io_map_reqs_2_lrs3_0; // @[rename-maptable.scala:43:7, :135:71] wire [4:0] _io_map_resps_2_stale_pdst_T = io_map_reqs_2_ldst_0[4:0]; // @[rename-maptable.scala:43:7] wire _io_map_resps_2_stale_pdst_T_2 = io_remap_reqs_0_ldst_0 == io_map_reqs_2_ldst_0; // @[rename-maptable.scala:43:7, :137:71] wire [6:0] _io_map_resps_2_stale_pdst_T_4 = _GEN[_io_map_resps_2_stale_pdst_T]; // @[rename-maptable.scala:130:32, :137:10] assign _io_map_resps_2_stale_pdst_T_8 = _io_map_resps_2_stale_pdst_T_4; // @[rename-maptable.scala:137:10] wire _io_map_resps_2_stale_pdst_T_6 = io_remap_reqs_1_ldst_0 == io_map_reqs_2_ldst_0; // @[rename-maptable.scala:43:7, :137:71] assign io_map_resps_2_stale_pdst_0 = _io_map_resps_2_stale_pdst_T_8; // @[rename-maptable.scala:43:7, :137:10]
Generate the Verilog code corresponding to this FIRRTL code module PE_332 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_76 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_332( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_76 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_44 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T = shr(io.in.a.bits.source, 2) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h2)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _source_ok_T_7 = eq(io.in.a.bits.source, UInt<3>(0h4)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_7 node _source_ok_T_8 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_8, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_4 = shr(io.in.a.bits.source, 2) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<2>(0h2)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_28 = cvt(_T_27) node _T_29 = and(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = asSInt(_T_29) node _T_31 = eq(_T_30, asSInt(UInt<1>(0h0))) node _T_32 = or(_T_26, _T_31) node _T_33 = and(_T_16, _T_24) node _T_34 = and(_T_33, _T_32) node _T_35 = asUInt(reset) node _T_36 = eq(_T_35, UInt<1>(0h0)) when _T_36 : node _T_37 = eq(_T_34, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_34, UInt<1>(0h1), "") : assert_1 node _T_38 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_38 : node _T_39 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_40 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_41 = and(_T_39, _T_40) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_42 = shr(io.in.a.bits.source, 2) node _T_43 = eq(_T_42, UInt<1>(0h0)) node _T_44 = leq(UInt<1>(0h0), uncommonBits_1) node _T_45 = and(_T_43, _T_44) node _T_46 = leq(uncommonBits_1, UInt<2>(0h2)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_49 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_50 = or(_T_47, _T_48) node _T_51 = or(_T_50, _T_49) node _T_52 = and(_T_41, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_55 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<14>(0h2000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<13>(0h1000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<18>(0h2f000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<17>(0h10000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<27>(0h4000000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<13>(0h1000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_59, _T_64) node _T_96 = or(_T_95, _T_69) node _T_97 = or(_T_96, _T_74) node _T_98 = or(_T_97, _T_79) node _T_99 = or(_T_98, _T_84) node _T_100 = or(_T_99, _T_89) node _T_101 = or(_T_100, _T_94) node _T_102 = and(_T_54, _T_101) node _T_103 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = or(_T_109, _T_114) node _T_116 = and(_T_104, _T_115) node _T_117 = or(UInt<1>(0h0), _T_102) node _T_118 = or(_T_117, _T_116) node _T_119 = and(_T_53, _T_118) node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(_T_119, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_119, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_123 = shr(io.in.a.bits.source, 2) node _T_124 = eq(_T_123, UInt<1>(0h0)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_2) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_2, UInt<2>(0h2)) node _T_128 = and(_T_126, _T_127) node _T_129 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_130 = eq(io.in.a.bits.source, UInt<3>(0h4)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_128 connect _WIRE[1], _T_129 connect _WIRE[2], _T_130 node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_132 = mux(_WIRE[0], _T_131, UInt<1>(0h0)) node _T_133 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_135 = or(_T_132, _T_133) node _T_136 = or(_T_135, _T_134) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_136 node _T_137 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_138 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_139 = and(_T_137, _T_138) node _T_140 = or(UInt<1>(0h0), _T_139) node _T_141 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<14>(0h2000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<18>(0h2f000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<27>(0h4000000))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_182 = cvt(_T_181) node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000))) node _T_184 = asSInt(_T_183) node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0))) node _T_186 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<29>(0h10000000))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_145, _T_150) node _T_192 = or(_T_191, _T_155) node _T_193 = or(_T_192, _T_160) node _T_194 = or(_T_193, _T_165) node _T_195 = or(_T_194, _T_170) node _T_196 = or(_T_195, _T_175) node _T_197 = or(_T_196, _T_180) node _T_198 = or(_T_197, _T_185) node _T_199 = or(_T_198, _T_190) node _T_200 = and(_T_140, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = and(_WIRE_1, _T_201) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_202, UInt<1>(0h1), "") : assert_3 node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(source_ok, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_209 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_209, UInt<1>(0h1), "") : assert_5 node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(is_aligned, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_216, UInt<1>(0h1), "") : assert_7 node _T_220 = not(io.in.a.bits.mask) node _T_221 = eq(_T_220, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_221, UInt<1>(0h1), "") : assert_8 node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_225, UInt<1>(0h1), "") : assert_9 node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_229 : node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_233 = shr(io.in.a.bits.source, 2) node _T_234 = eq(_T_233, UInt<1>(0h0)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_3) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_3, UInt<2>(0h2)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_240 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_241 = or(_T_238, _T_239) node _T_242 = or(_T_241, _T_240) node _T_243 = and(_T_232, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<14>(0h2000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<18>(0h2f000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<17>(0h10000))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<27>(0h4000000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_250, _T_255) node _T_287 = or(_T_286, _T_260) node _T_288 = or(_T_287, _T_265) node _T_289 = or(_T_288, _T_270) node _T_290 = or(_T_289, _T_275) node _T_291 = or(_T_290, _T_280) node _T_292 = or(_T_291, _T_285) node _T_293 = and(_T_245, _T_292) node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_293) node _T_309 = or(_T_308, _T_307) node _T_310 = and(_T_244, _T_309) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_310, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_314 = shr(io.in.a.bits.source, 2) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = leq(UInt<1>(0h0), uncommonBits_4) node _T_317 = and(_T_315, _T_316) node _T_318 = leq(uncommonBits_4, UInt<2>(0h2)) node _T_319 = and(_T_317, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_321 = eq(io.in.a.bits.source, UInt<3>(0h4)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_319 connect _WIRE_2[1], _T_320 connect _WIRE_2[2], _T_321 node _T_322 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_323 = mux(_WIRE_2[0], _T_322, UInt<1>(0h0)) node _T_324 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_325 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_326 = or(_T_323, _T_324) node _T_327 = or(_T_326, _T_325) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_327 node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_329 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_330 = and(_T_328, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<14>(0h2000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<13>(0h1000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<18>(0h2f000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<17>(0h10000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_358 = cvt(_T_357) node _T_359 = and(_T_358, asSInt(UInt<13>(0h1000))) node _T_360 = asSInt(_T_359) node _T_361 = eq(_T_360, asSInt(UInt<1>(0h0))) node _T_362 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_368 = cvt(_T_367) node _T_369 = and(_T_368, asSInt(UInt<27>(0h4000000))) node _T_370 = asSInt(_T_369) node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0))) node _T_372 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<29>(0h10000000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = or(_T_336, _T_341) node _T_383 = or(_T_382, _T_346) node _T_384 = or(_T_383, _T_351) node _T_385 = or(_T_384, _T_356) node _T_386 = or(_T_385, _T_361) node _T_387 = or(_T_386, _T_366) node _T_388 = or(_T_387, _T_371) node _T_389 = or(_T_388, _T_376) node _T_390 = or(_T_389, _T_381) node _T_391 = and(_T_331, _T_390) node _T_392 = or(UInt<1>(0h0), _T_391) node _T_393 = and(_WIRE_3, _T_392) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_393, UInt<1>(0h1), "") : assert_11 node _T_397 = asUInt(reset) node _T_398 = eq(_T_397, UInt<1>(0h0)) when _T_398 : node _T_399 = eq(source_ok, UInt<1>(0h0)) when _T_399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_400 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_400, UInt<1>(0h1), "") : assert_13 node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(is_aligned, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_407 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_407, UInt<1>(0h1), "") : assert_15 node _T_411 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_411, UInt<1>(0h1), "") : assert_16 node _T_415 = not(io.in.a.bits.mask) node _T_416 = eq(_T_415, UInt<1>(0h0)) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_416, UInt<1>(0h1), "") : assert_17 node _T_420 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_420, UInt<1>(0h1), "") : assert_18 node _T_424 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_424 : node _T_425 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_426 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_427 = and(_T_425, _T_426) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_428 = shr(io.in.a.bits.source, 2) node _T_429 = eq(_T_428, UInt<1>(0h0)) node _T_430 = leq(UInt<1>(0h0), uncommonBits_5) node _T_431 = and(_T_429, _T_430) node _T_432 = leq(uncommonBits_5, UInt<2>(0h2)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_435 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_436 = or(_T_433, _T_434) node _T_437 = or(_T_436, _T_435) node _T_438 = and(_T_427, _T_437) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_439, UInt<1>(0h1), "") : assert_19 node _T_443 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_444 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_445 = and(_T_443, _T_444) node _T_446 = or(UInt<1>(0h0), _T_445) node _T_447 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = and(_T_446, _T_451) node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_454 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_455 = and(_T_453, _T_454) node _T_456 = or(UInt<1>(0h0), _T_455) node _T_457 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<14>(0h2000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<18>(0h2f000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<17>(0h10000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<13>(0h1000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<17>(0h10000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<27>(0h4000000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<29>(0h10000000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = or(_T_461, _T_466) node _T_503 = or(_T_502, _T_471) node _T_504 = or(_T_503, _T_476) node _T_505 = or(_T_504, _T_481) node _T_506 = or(_T_505, _T_486) node _T_507 = or(_T_506, _T_491) node _T_508 = or(_T_507, _T_496) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_456, _T_509) node _T_511 = or(UInt<1>(0h0), _T_452) node _T_512 = or(_T_511, _T_510) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_512, UInt<1>(0h1), "") : assert_20 node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(source_ok, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(is_aligned, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_522, UInt<1>(0h1), "") : assert_23 node _T_526 = eq(io.in.a.bits.mask, mask) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_526, UInt<1>(0h1), "") : assert_24 node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_530, UInt<1>(0h1), "") : assert_25 node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_534 : node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_538 = shr(io.in.a.bits.source, 2) node _T_539 = eq(_T_538, UInt<1>(0h0)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_6) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_6, UInt<2>(0h2)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_545 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_546 = or(_T_543, _T_544) node _T_547 = or(_T_546, _T_545) node _T_548 = and(_T_537, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_551 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_552 = and(_T_550, _T_551) node _T_553 = or(UInt<1>(0h0), _T_552) node _T_554 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = and(_T_553, _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<14>(0h2000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_570 = cvt(_T_569) node _T_571 = and(_T_570, asSInt(UInt<18>(0h2f000))) node _T_572 = asSInt(_T_571) node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0))) node _T_574 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<17>(0h10000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<27>(0h4000000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<29>(0h10000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = or(_T_568, _T_573) node _T_605 = or(_T_604, _T_578) node _T_606 = or(_T_605, _T_583) node _T_607 = or(_T_606, _T_588) node _T_608 = or(_T_607, _T_593) node _T_609 = or(_T_608, _T_598) node _T_610 = or(_T_609, _T_603) node _T_611 = and(_T_563, _T_610) node _T_612 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_614 = cvt(_T_613) node _T_615 = and(_T_614, asSInt(UInt<17>(0h10000))) node _T_616 = asSInt(_T_615) node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) node _T_618 = and(_T_612, _T_617) node _T_619 = or(UInt<1>(0h0), _T_559) node _T_620 = or(_T_619, _T_611) node _T_621 = or(_T_620, _T_618) node _T_622 = and(_T_549, _T_621) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_622, UInt<1>(0h1), "") : assert_26 node _T_626 = asUInt(reset) node _T_627 = eq(_T_626, UInt<1>(0h0)) when _T_627 : node _T_628 = eq(source_ok, UInt<1>(0h0)) when _T_628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(is_aligned, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_632 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_632, UInt<1>(0h1), "") : assert_29 node _T_636 = eq(io.in.a.bits.mask, mask) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_636, UInt<1>(0h1), "") : assert_30 node _T_640 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_640 : node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_643 = and(_T_641, _T_642) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_644 = shr(io.in.a.bits.source, 2) node _T_645 = eq(_T_644, UInt<1>(0h0)) node _T_646 = leq(UInt<1>(0h0), uncommonBits_7) node _T_647 = and(_T_645, _T_646) node _T_648 = leq(uncommonBits_7, UInt<2>(0h2)) node _T_649 = and(_T_647, _T_648) node _T_650 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_651 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_652 = or(_T_649, _T_650) node _T_653 = or(_T_652, _T_651) node _T_654 = and(_T_643, _T_653) node _T_655 = or(UInt<1>(0h0), _T_654) node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_658 = and(_T_656, _T_657) node _T_659 = or(UInt<1>(0h0), _T_658) node _T_660 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = and(_T_659, _T_664) node _T_666 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_667 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_668 = and(_T_666, _T_667) node _T_669 = or(UInt<1>(0h0), _T_668) node _T_670 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<14>(0h2000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<18>(0h2f000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<17>(0h10000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_686 = cvt(_T_685) node _T_687 = and(_T_686, asSInt(UInt<13>(0h1000))) node _T_688 = asSInt(_T_687) node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0))) node _T_690 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_691 = cvt(_T_690) node _T_692 = and(_T_691, asSInt(UInt<17>(0h10000))) node _T_693 = asSInt(_T_692) node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) node _T_695 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_696 = cvt(_T_695) node _T_697 = and(_T_696, asSInt(UInt<27>(0h4000000))) node _T_698 = asSInt(_T_697) node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0))) node _T_700 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_701 = cvt(_T_700) node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000))) node _T_703 = asSInt(_T_702) node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) node _T_705 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<29>(0h10000000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = or(_T_674, _T_679) node _T_711 = or(_T_710, _T_684) node _T_712 = or(_T_711, _T_689) node _T_713 = or(_T_712, _T_694) node _T_714 = or(_T_713, _T_699) node _T_715 = or(_T_714, _T_704) node _T_716 = or(_T_715, _T_709) node _T_717 = and(_T_669, _T_716) node _T_718 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_719 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_720 = cvt(_T_719) node _T_721 = and(_T_720, asSInt(UInt<17>(0h10000))) node _T_722 = asSInt(_T_721) node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0))) node _T_724 = and(_T_718, _T_723) node _T_725 = or(UInt<1>(0h0), _T_665) node _T_726 = or(_T_725, _T_717) node _T_727 = or(_T_726, _T_724) node _T_728 = and(_T_655, _T_727) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_728, UInt<1>(0h1), "") : assert_31 node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(source_ok, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(is_aligned, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_738 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_738, UInt<1>(0h1), "") : assert_34 node _T_742 = not(mask) node _T_743 = and(io.in.a.bits.mask, _T_742) node _T_744 = eq(_T_743, UInt<1>(0h0)) node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(_T_744, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_744, UInt<1>(0h1), "") : assert_35 node _T_748 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_748 : node _T_749 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_750 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_752 = shr(io.in.a.bits.source, 2) node _T_753 = eq(_T_752, UInt<1>(0h0)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_8) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_8, UInt<2>(0h2)) node _T_757 = and(_T_755, _T_756) node _T_758 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_759 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_760 = or(_T_757, _T_758) node _T_761 = or(_T_760, _T_759) node _T_762 = and(_T_751, _T_761) node _T_763 = or(UInt<1>(0h0), _T_762) node _T_764 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_765 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_766 = and(_T_764, _T_765) node _T_767 = or(UInt<1>(0h0), _T_766) node _T_768 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_769 = cvt(_T_768) node _T_770 = and(_T_769, asSInt(UInt<14>(0h2000))) node _T_771 = asSInt(_T_770) node _T_772 = eq(_T_771, asSInt(UInt<1>(0h0))) node _T_773 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_774 = cvt(_T_773) node _T_775 = and(_T_774, asSInt(UInt<13>(0h1000))) node _T_776 = asSInt(_T_775) node _T_777 = eq(_T_776, asSInt(UInt<1>(0h0))) node _T_778 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<18>(0h2f000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_784 = cvt(_T_783) node _T_785 = and(_T_784, asSInt(UInt<17>(0h10000))) node _T_786 = asSInt(_T_785) node _T_787 = eq(_T_786, asSInt(UInt<1>(0h0))) node _T_788 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_789 = cvt(_T_788) node _T_790 = and(_T_789, asSInt(UInt<13>(0h1000))) node _T_791 = asSInt(_T_790) node _T_792 = eq(_T_791, asSInt(UInt<1>(0h0))) node _T_793 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_794 = cvt(_T_793) node _T_795 = and(_T_794, asSInt(UInt<17>(0h10000))) node _T_796 = asSInt(_T_795) node _T_797 = eq(_T_796, asSInt(UInt<1>(0h0))) node _T_798 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_799 = cvt(_T_798) node _T_800 = and(_T_799, asSInt(UInt<27>(0h4000000))) node _T_801 = asSInt(_T_800) node _T_802 = eq(_T_801, asSInt(UInt<1>(0h0))) node _T_803 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<13>(0h1000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_809 = cvt(_T_808) node _T_810 = and(_T_809, asSInt(UInt<29>(0h10000000))) node _T_811 = asSInt(_T_810) node _T_812 = eq(_T_811, asSInt(UInt<1>(0h0))) node _T_813 = or(_T_772, _T_777) node _T_814 = or(_T_813, _T_782) node _T_815 = or(_T_814, _T_787) node _T_816 = or(_T_815, _T_792) node _T_817 = or(_T_816, _T_797) node _T_818 = or(_T_817, _T_802) node _T_819 = or(_T_818, _T_807) node _T_820 = or(_T_819, _T_812) node _T_821 = and(_T_767, _T_820) node _T_822 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_823 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_824 = cvt(_T_823) node _T_825 = and(_T_824, asSInt(UInt<17>(0h10000))) node _T_826 = asSInt(_T_825) node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0))) node _T_828 = and(_T_822, _T_827) node _T_829 = or(UInt<1>(0h0), _T_821) node _T_830 = or(_T_829, _T_828) node _T_831 = and(_T_763, _T_830) node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_T_831, UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_831, UInt<1>(0h1), "") : assert_36 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(source_ok, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(is_aligned, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_841 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_842 = asUInt(reset) node _T_843 = eq(_T_842, UInt<1>(0h0)) when _T_843 : node _T_844 = eq(_T_841, UInt<1>(0h0)) when _T_844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_841, UInt<1>(0h1), "") : assert_39 node _T_845 = eq(io.in.a.bits.mask, mask) node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(_T_845, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_845, UInt<1>(0h1), "") : assert_40 node _T_849 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_849 : node _T_850 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_851 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_852 = and(_T_850, _T_851) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<1>(0h0)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_9) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_9, UInt<2>(0h2)) node _T_858 = and(_T_856, _T_857) node _T_859 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_860 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_861 = or(_T_858, _T_859) node _T_862 = or(_T_861, _T_860) node _T_863 = and(_T_852, _T_862) node _T_864 = or(UInt<1>(0h0), _T_863) node _T_865 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_866 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_867 = and(_T_865, _T_866) node _T_868 = or(UInt<1>(0h0), _T_867) node _T_869 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<14>(0h2000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<18>(0h2f000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<17>(0h10000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<13>(0h1000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<17>(0h10000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<29>(0h10000000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = or(_T_873, _T_878) node _T_915 = or(_T_914, _T_883) node _T_916 = or(_T_915, _T_888) node _T_917 = or(_T_916, _T_893) node _T_918 = or(_T_917, _T_898) node _T_919 = or(_T_918, _T_903) node _T_920 = or(_T_919, _T_908) node _T_921 = or(_T_920, _T_913) node _T_922 = and(_T_868, _T_921) node _T_923 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_924 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<17>(0h10000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = and(_T_923, _T_928) node _T_930 = or(UInt<1>(0h0), _T_922) node _T_931 = or(_T_930, _T_929) node _T_932 = and(_T_864, _T_931) node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(_T_932, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_932, UInt<1>(0h1), "") : assert_41 node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(source_ok, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(is_aligned, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_942 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_942, UInt<1>(0h1), "") : assert_44 node _T_946 = eq(io.in.a.bits.mask, mask) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_946, UInt<1>(0h1), "") : assert_45 node _T_950 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_950 : node _T_951 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_952 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_953 = and(_T_951, _T_952) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_954 = shr(io.in.a.bits.source, 2) node _T_955 = eq(_T_954, UInt<1>(0h0)) node _T_956 = leq(UInt<1>(0h0), uncommonBits_10) node _T_957 = and(_T_955, _T_956) node _T_958 = leq(uncommonBits_10, UInt<2>(0h2)) node _T_959 = and(_T_957, _T_958) node _T_960 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_961 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_962 = or(_T_959, _T_960) node _T_963 = or(_T_962, _T_961) node _T_964 = and(_T_953, _T_963) node _T_965 = or(UInt<1>(0h0), _T_964) node _T_966 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_967 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_968 = and(_T_966, _T_967) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_971 = cvt(_T_970) node _T_972 = and(_T_971, asSInt(UInt<13>(0h1000))) node _T_973 = asSInt(_T_972) node _T_974 = eq(_T_973, asSInt(UInt<1>(0h0))) node _T_975 = and(_T_969, _T_974) node _T_976 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_977 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_978 = cvt(_T_977) node _T_979 = and(_T_978, asSInt(UInt<14>(0h2000))) node _T_980 = asSInt(_T_979) node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0))) node _T_982 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_983 = cvt(_T_982) node _T_984 = and(_T_983, asSInt(UInt<17>(0h10000))) node _T_985 = asSInt(_T_984) node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0))) node _T_987 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<18>(0h2f000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<13>(0h1000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<27>(0h4000000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = or(_T_981, _T_986) node _T_1013 = or(_T_1012, _T_991) node _T_1014 = or(_T_1013, _T_996) node _T_1015 = or(_T_1014, _T_1001) node _T_1016 = or(_T_1015, _T_1006) node _T_1017 = or(_T_1016, _T_1011) node _T_1018 = and(_T_976, _T_1017) node _T_1019 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1020 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1021 = and(_T_1019, _T_1020) node _T_1022 = or(UInt<1>(0h0), _T_1021) node _T_1023 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1024 = cvt(_T_1023) node _T_1025 = and(_T_1024, asSInt(UInt<17>(0h10000))) node _T_1026 = asSInt(_T_1025) node _T_1027 = eq(_T_1026, asSInt(UInt<1>(0h0))) node _T_1028 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1029 = cvt(_T_1028) node _T_1030 = and(_T_1029, asSInt(UInt<29>(0h10000000))) node _T_1031 = asSInt(_T_1030) node _T_1032 = eq(_T_1031, asSInt(UInt<1>(0h0))) node _T_1033 = or(_T_1027, _T_1032) node _T_1034 = and(_T_1022, _T_1033) node _T_1035 = or(UInt<1>(0h0), _T_975) node _T_1036 = or(_T_1035, _T_1018) node _T_1037 = or(_T_1036, _T_1034) node _T_1038 = and(_T_965, _T_1037) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_46 node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(source_ok, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(is_aligned, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1048 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_49 node _T_1052 = eq(io.in.a.bits.mask, mask) node _T_1053 = asUInt(reset) node _T_1054 = eq(_T_1053, UInt<1>(0h0)) when _T_1054 : node _T_1055 = eq(_T_1052, UInt<1>(0h0)) when _T_1055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1052, UInt<1>(0h1), "") : assert_50 node _T_1056 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1060 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_9 = shr(io.in.d.bits.source, 2) node _source_ok_T_10 = eq(_source_ok_T_9, UInt<1>(0h0)) node _source_ok_T_11 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = leq(source_ok_uncommonBits_1, UInt<2>(0h2)) node _source_ok_T_14 = and(_source_ok_T_12, _source_ok_T_13) node _source_ok_T_15 = eq(io.in.d.bits.source, UInt<2>(0h3)) node _source_ok_T_16 = eq(io.in.d.bits.source, UInt<3>(0h4)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_14 connect _source_ok_WIRE_1[1], _source_ok_T_15 connect _source_ok_WIRE_1[2], _source_ok_T_16 node _source_ok_T_17 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_17, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1064 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1064 : node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(source_ok_1, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1068 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_54 node _T_1072 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_55 node _T_1076 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_56 node _T_1080 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_57 node _T_1084 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1084 : node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(source_ok_1, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(sink_ok, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1091 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1092 = asUInt(reset) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) when _T_1093 : node _T_1094 = eq(_T_1091, UInt<1>(0h0)) when _T_1094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1091, UInt<1>(0h1), "") : assert_60 node _T_1095 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1096 = asUInt(reset) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(_T_1095, UInt<1>(0h0)) when _T_1098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1095, UInt<1>(0h1), "") : assert_61 node _T_1099 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_62 node _T_1103 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(_T_1103, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1103, UInt<1>(0h1), "") : assert_63 node _T_1107 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1108 = or(UInt<1>(0h1), _T_1107) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_64 node _T_1112 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1112 : node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(source_ok_1, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(sink_ok, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1119 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_67 node _T_1123 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_68 node _T_1127 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(_T_1127, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1127, UInt<1>(0h1), "") : assert_69 node _T_1131 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1132 = or(_T_1131, io.in.d.bits.corrupt) node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(_T_1132, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1132, UInt<1>(0h1), "") : assert_70 node _T_1136 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1137 = or(UInt<1>(0h1), _T_1136) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_71 node _T_1141 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1141 : node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(source_ok_1, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1145 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_73 node _T_1149 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_74 node _T_1153 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1154 = or(UInt<1>(0h1), _T_1153) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_75 node _T_1158 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1158 : node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(source_ok_1, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1162 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_77 node _T_1166 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1167 = or(_T_1166, io.in.d.bits.corrupt) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_78 node _T_1171 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1172 = or(UInt<1>(0h1), _T_1171) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_79 node _T_1176 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1176 : node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(source_ok_1, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1180 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_81 node _T_1184 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_82 node _T_1188 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1189 = or(UInt<1>(0h1), _T_1188) node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(_T_1189, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1189, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1193 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1194 = asUInt(reset) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) when _T_1195 : node _T_1196 = eq(_T_1193, UInt<1>(0h0)) when _T_1196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1193, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_1197 = shr(io.in.b.bits.source, 2) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = leq(UInt<1>(0h0), uncommonBits_11) node _T_1200 = and(_T_1198, _T_1199) node _T_1201 = leq(uncommonBits_11, UInt<2>(0h2)) node _T_1202 = and(_T_1200, _T_1201) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) node _T_1204 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1205 = cvt(_T_1204) node _T_1206 = and(_T_1205, asSInt(UInt<1>(0h0))) node _T_1207 = asSInt(_T_1206) node _T_1208 = eq(_T_1207, asSInt(UInt<1>(0h0))) node _T_1209 = or(_T_1203, _T_1208) node _T_1210 = eq(io.in.b.bits.source, UInt<2>(0h3)) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) node _T_1212 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1213 = cvt(_T_1212) node _T_1214 = and(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = asSInt(_T_1214) node _T_1216 = eq(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = or(_T_1211, _T_1216) node _T_1218 = eq(io.in.b.bits.source, UInt<3>(0h4)) node _T_1219 = eq(_T_1218, UInt<1>(0h0)) node _T_1220 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<1>(0h0))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = or(_T_1219, _T_1224) node _T_1226 = and(_T_1209, _T_1217) node _T_1227 = and(_T_1226, _T_1225) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T = shr(io.in.b.bits.source, 2) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<2>(0h2)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<2>(0h3)) node _legal_source_T_7 = eq(io.in.b.bits.source, UInt<3>(0h4)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_7 node _legal_source_T_8 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_9 = mux(_legal_source_WIRE[1], UInt<2>(0h3), UInt<1>(0h0)) node _legal_source_T_10 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_11 = or(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_12 = or(_legal_source_T_11, _legal_source_T_10) wire _legal_source_WIRE_1 : UInt<3> connect _legal_source_WIRE_1, _legal_source_T_12 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1231 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1231 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_1232 = shr(io.in.b.bits.source, 2) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) node _T_1234 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1235 = and(_T_1233, _T_1234) node _T_1236 = leq(uncommonBits_12, UInt<2>(0h2)) node _T_1237 = and(_T_1235, _T_1236) node _T_1238 = eq(io.in.b.bits.source, UInt<2>(0h3)) node _T_1239 = eq(io.in.b.bits.source, UInt<3>(0h4)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1237 connect _WIRE_4[1], _T_1238 connect _WIRE_4[2], _T_1239 node _T_1240 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1241 = mux(_WIRE_4[0], _T_1240, UInt<1>(0h0)) node _T_1242 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1243 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1242) node _T_1245 = or(_T_1244, _T_1243) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1245 node _T_1246 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1247 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1248 = and(_T_1246, _T_1247) node _T_1249 = or(UInt<1>(0h0), _T_1248) node _T_1250 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1251 = cvt(_T_1250) node _T_1252 = and(_T_1251, asSInt(UInt<14>(0h2000))) node _T_1253 = asSInt(_T_1252) node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0))) node _T_1255 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1256 = cvt(_T_1255) node _T_1257 = and(_T_1256, asSInt(UInt<13>(0h1000))) node _T_1258 = asSInt(_T_1257) node _T_1259 = eq(_T_1258, asSInt(UInt<1>(0h0))) node _T_1260 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1261 = cvt(_T_1260) node _T_1262 = and(_T_1261, asSInt(UInt<17>(0h10000))) node _T_1263 = asSInt(_T_1262) node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0))) node _T_1265 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1266 = cvt(_T_1265) node _T_1267 = and(_T_1266, asSInt(UInt<18>(0h2f000))) node _T_1268 = asSInt(_T_1267) node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0))) node _T_1270 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1271 = cvt(_T_1270) node _T_1272 = and(_T_1271, asSInt(UInt<17>(0h10000))) node _T_1273 = asSInt(_T_1272) node _T_1274 = eq(_T_1273, asSInt(UInt<1>(0h0))) node _T_1275 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1276 = cvt(_T_1275) node _T_1277 = and(_T_1276, asSInt(UInt<13>(0h1000))) node _T_1278 = asSInt(_T_1277) node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0))) node _T_1280 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1281 = cvt(_T_1280) node _T_1282 = and(_T_1281, asSInt(UInt<17>(0h10000))) node _T_1283 = asSInt(_T_1282) node _T_1284 = eq(_T_1283, asSInt(UInt<1>(0h0))) node _T_1285 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1286 = cvt(_T_1285) node _T_1287 = and(_T_1286, asSInt(UInt<27>(0h4000000))) node _T_1288 = asSInt(_T_1287) node _T_1289 = eq(_T_1288, asSInt(UInt<1>(0h0))) node _T_1290 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1291 = cvt(_T_1290) node _T_1292 = and(_T_1291, asSInt(UInt<13>(0h1000))) node _T_1293 = asSInt(_T_1292) node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0))) node _T_1295 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1296 = cvt(_T_1295) node _T_1297 = and(_T_1296, asSInt(UInt<29>(0h10000000))) node _T_1298 = asSInt(_T_1297) node _T_1299 = eq(_T_1298, asSInt(UInt<1>(0h0))) node _T_1300 = or(_T_1254, _T_1259) node _T_1301 = or(_T_1300, _T_1264) node _T_1302 = or(_T_1301, _T_1269) node _T_1303 = or(_T_1302, _T_1274) node _T_1304 = or(_T_1303, _T_1279) node _T_1305 = or(_T_1304, _T_1284) node _T_1306 = or(_T_1305, _T_1289) node _T_1307 = or(_T_1306, _T_1294) node _T_1308 = or(_T_1307, _T_1299) node _T_1309 = and(_T_1249, _T_1308) node _T_1310 = or(UInt<1>(0h0), _T_1309) node _T_1311 = and(_WIRE_5, _T_1310) node _T_1312 = asUInt(reset) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(_T_1311, UInt<1>(0h0)) when _T_1314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1311, UInt<1>(0h1), "") : assert_86 node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(address_ok, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1318 = asUInt(reset) node _T_1319 = eq(_T_1318, UInt<1>(0h0)) when _T_1319 : node _T_1320 = eq(legal_source, UInt<1>(0h0)) when _T_1320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1321 = asUInt(reset) node _T_1322 = eq(_T_1321, UInt<1>(0h0)) when _T_1322 : node _T_1323 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1324 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_90 node _T_1328 = eq(io.in.b.bits.mask, mask_1) node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(_T_1328, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1328, UInt<1>(0h1), "") : assert_91 node _T_1332 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1333 = asUInt(reset) node _T_1334 = eq(_T_1333, UInt<1>(0h0)) when _T_1334 : node _T_1335 = eq(_T_1332, UInt<1>(0h0)) when _T_1335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1332, UInt<1>(0h1), "") : assert_92 node _T_1336 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1336 : node _T_1337 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1338 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1339 = and(_T_1337, _T_1338) node _T_1340 = or(UInt<1>(0h0), _T_1339) node _T_1341 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1342 = cvt(_T_1341) node _T_1343 = and(_T_1342, asSInt(UInt<14>(0h2000))) node _T_1344 = asSInt(_T_1343) node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0))) node _T_1346 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1347 = cvt(_T_1346) node _T_1348 = and(_T_1347, asSInt(UInt<13>(0h1000))) node _T_1349 = asSInt(_T_1348) node _T_1350 = eq(_T_1349, asSInt(UInt<1>(0h0))) node _T_1351 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1352 = cvt(_T_1351) node _T_1353 = and(_T_1352, asSInt(UInt<17>(0h10000))) node _T_1354 = asSInt(_T_1353) node _T_1355 = eq(_T_1354, asSInt(UInt<1>(0h0))) node _T_1356 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1357 = cvt(_T_1356) node _T_1358 = and(_T_1357, asSInt(UInt<18>(0h2f000))) node _T_1359 = asSInt(_T_1358) node _T_1360 = eq(_T_1359, asSInt(UInt<1>(0h0))) node _T_1361 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1362 = cvt(_T_1361) node _T_1363 = and(_T_1362, asSInt(UInt<17>(0h10000))) node _T_1364 = asSInt(_T_1363) node _T_1365 = eq(_T_1364, asSInt(UInt<1>(0h0))) node _T_1366 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1367 = cvt(_T_1366) node _T_1368 = and(_T_1367, asSInt(UInt<13>(0h1000))) node _T_1369 = asSInt(_T_1368) node _T_1370 = eq(_T_1369, asSInt(UInt<1>(0h0))) node _T_1371 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1372 = cvt(_T_1371) node _T_1373 = and(_T_1372, asSInt(UInt<17>(0h10000))) node _T_1374 = asSInt(_T_1373) node _T_1375 = eq(_T_1374, asSInt(UInt<1>(0h0))) node _T_1376 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1377 = cvt(_T_1376) node _T_1378 = and(_T_1377, asSInt(UInt<27>(0h4000000))) node _T_1379 = asSInt(_T_1378) node _T_1380 = eq(_T_1379, asSInt(UInt<1>(0h0))) node _T_1381 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1382 = cvt(_T_1381) node _T_1383 = and(_T_1382, asSInt(UInt<13>(0h1000))) node _T_1384 = asSInt(_T_1383) node _T_1385 = eq(_T_1384, asSInt(UInt<1>(0h0))) node _T_1386 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1387 = cvt(_T_1386) node _T_1388 = and(_T_1387, asSInt(UInt<29>(0h10000000))) node _T_1389 = asSInt(_T_1388) node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0))) node _T_1391 = or(_T_1345, _T_1350) node _T_1392 = or(_T_1391, _T_1355) node _T_1393 = or(_T_1392, _T_1360) node _T_1394 = or(_T_1393, _T_1365) node _T_1395 = or(_T_1394, _T_1370) node _T_1396 = or(_T_1395, _T_1375) node _T_1397 = or(_T_1396, _T_1380) node _T_1398 = or(_T_1397, _T_1385) node _T_1399 = or(_T_1398, _T_1390) node _T_1400 = and(_T_1340, _T_1399) node _T_1401 = or(UInt<1>(0h0), _T_1400) node _T_1402 = and(UInt<1>(0h0), _T_1401) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_93 node _T_1406 = asUInt(reset) node _T_1407 = eq(_T_1406, UInt<1>(0h0)) when _T_1407 : node _T_1408 = eq(address_ok, UInt<1>(0h0)) when _T_1408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1409 = asUInt(reset) node _T_1410 = eq(_T_1409, UInt<1>(0h0)) when _T_1410 : node _T_1411 = eq(legal_source, UInt<1>(0h0)) when _T_1411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1412 = asUInt(reset) node _T_1413 = eq(_T_1412, UInt<1>(0h0)) when _T_1413 : node _T_1414 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1415 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1416 = asUInt(reset) node _T_1417 = eq(_T_1416, UInt<1>(0h0)) when _T_1417 : node _T_1418 = eq(_T_1415, UInt<1>(0h0)) when _T_1418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1415, UInt<1>(0h1), "") : assert_97 node _T_1419 = eq(io.in.b.bits.mask, mask_1) node _T_1420 = asUInt(reset) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) when _T_1421 : node _T_1422 = eq(_T_1419, UInt<1>(0h0)) when _T_1422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1419, UInt<1>(0h1), "") : assert_98 node _T_1423 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1424 = asUInt(reset) node _T_1425 = eq(_T_1424, UInt<1>(0h0)) when _T_1425 : node _T_1426 = eq(_T_1423, UInt<1>(0h0)) when _T_1426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1423, UInt<1>(0h1), "") : assert_99 node _T_1427 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1427 : node _T_1428 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1429 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1430 = and(_T_1428, _T_1429) node _T_1431 = or(UInt<1>(0h0), _T_1430) node _T_1432 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1433 = cvt(_T_1432) node _T_1434 = and(_T_1433, asSInt(UInt<14>(0h2000))) node _T_1435 = asSInt(_T_1434) node _T_1436 = eq(_T_1435, asSInt(UInt<1>(0h0))) node _T_1437 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1438 = cvt(_T_1437) node _T_1439 = and(_T_1438, asSInt(UInt<13>(0h1000))) node _T_1440 = asSInt(_T_1439) node _T_1441 = eq(_T_1440, asSInt(UInt<1>(0h0))) node _T_1442 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1443 = cvt(_T_1442) node _T_1444 = and(_T_1443, asSInt(UInt<17>(0h10000))) node _T_1445 = asSInt(_T_1444) node _T_1446 = eq(_T_1445, asSInt(UInt<1>(0h0))) node _T_1447 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1448 = cvt(_T_1447) node _T_1449 = and(_T_1448, asSInt(UInt<18>(0h2f000))) node _T_1450 = asSInt(_T_1449) node _T_1451 = eq(_T_1450, asSInt(UInt<1>(0h0))) node _T_1452 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1453 = cvt(_T_1452) node _T_1454 = and(_T_1453, asSInt(UInt<17>(0h10000))) node _T_1455 = asSInt(_T_1454) node _T_1456 = eq(_T_1455, asSInt(UInt<1>(0h0))) node _T_1457 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1458 = cvt(_T_1457) node _T_1459 = and(_T_1458, asSInt(UInt<13>(0h1000))) node _T_1460 = asSInt(_T_1459) node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0))) node _T_1462 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1463 = cvt(_T_1462) node _T_1464 = and(_T_1463, asSInt(UInt<17>(0h10000))) node _T_1465 = asSInt(_T_1464) node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0))) node _T_1467 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1468 = cvt(_T_1467) node _T_1469 = and(_T_1468, asSInt(UInt<27>(0h4000000))) node _T_1470 = asSInt(_T_1469) node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0))) node _T_1472 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1473 = cvt(_T_1472) node _T_1474 = and(_T_1473, asSInt(UInt<13>(0h1000))) node _T_1475 = asSInt(_T_1474) node _T_1476 = eq(_T_1475, asSInt(UInt<1>(0h0))) node _T_1477 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1478 = cvt(_T_1477) node _T_1479 = and(_T_1478, asSInt(UInt<29>(0h10000000))) node _T_1480 = asSInt(_T_1479) node _T_1481 = eq(_T_1480, asSInt(UInt<1>(0h0))) node _T_1482 = or(_T_1436, _T_1441) node _T_1483 = or(_T_1482, _T_1446) node _T_1484 = or(_T_1483, _T_1451) node _T_1485 = or(_T_1484, _T_1456) node _T_1486 = or(_T_1485, _T_1461) node _T_1487 = or(_T_1486, _T_1466) node _T_1488 = or(_T_1487, _T_1471) node _T_1489 = or(_T_1488, _T_1476) node _T_1490 = or(_T_1489, _T_1481) node _T_1491 = and(_T_1431, _T_1490) node _T_1492 = or(UInt<1>(0h0), _T_1491) node _T_1493 = and(UInt<1>(0h0), _T_1492) node _T_1494 = asUInt(reset) node _T_1495 = eq(_T_1494, UInt<1>(0h0)) when _T_1495 : node _T_1496 = eq(_T_1493, UInt<1>(0h0)) when _T_1496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1493, UInt<1>(0h1), "") : assert_100 node _T_1497 = asUInt(reset) node _T_1498 = eq(_T_1497, UInt<1>(0h0)) when _T_1498 : node _T_1499 = eq(address_ok, UInt<1>(0h0)) when _T_1499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1500 = asUInt(reset) node _T_1501 = eq(_T_1500, UInt<1>(0h0)) when _T_1501 : node _T_1502 = eq(legal_source, UInt<1>(0h0)) when _T_1502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1503 = asUInt(reset) node _T_1504 = eq(_T_1503, UInt<1>(0h0)) when _T_1504 : node _T_1505 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1506 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1507 = asUInt(reset) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) when _T_1508 : node _T_1509 = eq(_T_1506, UInt<1>(0h0)) when _T_1509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1506, UInt<1>(0h1), "") : assert_104 node _T_1510 = eq(io.in.b.bits.mask, mask_1) node _T_1511 = asUInt(reset) node _T_1512 = eq(_T_1511, UInt<1>(0h0)) when _T_1512 : node _T_1513 = eq(_T_1510, UInt<1>(0h0)) when _T_1513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1510, UInt<1>(0h1), "") : assert_105 node _T_1514 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1514 : node _T_1515 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1516 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1517 = and(_T_1515, _T_1516) node _T_1518 = or(UInt<1>(0h0), _T_1517) node _T_1519 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1520 = cvt(_T_1519) node _T_1521 = and(_T_1520, asSInt(UInt<14>(0h2000))) node _T_1522 = asSInt(_T_1521) node _T_1523 = eq(_T_1522, asSInt(UInt<1>(0h0))) node _T_1524 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1525 = cvt(_T_1524) node _T_1526 = and(_T_1525, asSInt(UInt<13>(0h1000))) node _T_1527 = asSInt(_T_1526) node _T_1528 = eq(_T_1527, asSInt(UInt<1>(0h0))) node _T_1529 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1530 = cvt(_T_1529) node _T_1531 = and(_T_1530, asSInt(UInt<17>(0h10000))) node _T_1532 = asSInt(_T_1531) node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0))) node _T_1534 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1535 = cvt(_T_1534) node _T_1536 = and(_T_1535, asSInt(UInt<18>(0h2f000))) node _T_1537 = asSInt(_T_1536) node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1540 = cvt(_T_1539) node _T_1541 = and(_T_1540, asSInt(UInt<17>(0h10000))) node _T_1542 = asSInt(_T_1541) node _T_1543 = eq(_T_1542, asSInt(UInt<1>(0h0))) node _T_1544 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1545 = cvt(_T_1544) node _T_1546 = and(_T_1545, asSInt(UInt<13>(0h1000))) node _T_1547 = asSInt(_T_1546) node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0))) node _T_1549 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1550 = cvt(_T_1549) node _T_1551 = and(_T_1550, asSInt(UInt<17>(0h10000))) node _T_1552 = asSInt(_T_1551) node _T_1553 = eq(_T_1552, asSInt(UInt<1>(0h0))) node _T_1554 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1555 = cvt(_T_1554) node _T_1556 = and(_T_1555, asSInt(UInt<27>(0h4000000))) node _T_1557 = asSInt(_T_1556) node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0))) node _T_1559 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1560 = cvt(_T_1559) node _T_1561 = and(_T_1560, asSInt(UInt<13>(0h1000))) node _T_1562 = asSInt(_T_1561) node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0))) node _T_1564 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1565 = cvt(_T_1564) node _T_1566 = and(_T_1565, asSInt(UInt<29>(0h10000000))) node _T_1567 = asSInt(_T_1566) node _T_1568 = eq(_T_1567, asSInt(UInt<1>(0h0))) node _T_1569 = or(_T_1523, _T_1528) node _T_1570 = or(_T_1569, _T_1533) node _T_1571 = or(_T_1570, _T_1538) node _T_1572 = or(_T_1571, _T_1543) node _T_1573 = or(_T_1572, _T_1548) node _T_1574 = or(_T_1573, _T_1553) node _T_1575 = or(_T_1574, _T_1558) node _T_1576 = or(_T_1575, _T_1563) node _T_1577 = or(_T_1576, _T_1568) node _T_1578 = and(_T_1518, _T_1577) node _T_1579 = or(UInt<1>(0h0), _T_1578) node _T_1580 = and(UInt<1>(0h0), _T_1579) node _T_1581 = asUInt(reset) node _T_1582 = eq(_T_1581, UInt<1>(0h0)) when _T_1582 : node _T_1583 = eq(_T_1580, UInt<1>(0h0)) when _T_1583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1580, UInt<1>(0h1), "") : assert_106 node _T_1584 = asUInt(reset) node _T_1585 = eq(_T_1584, UInt<1>(0h0)) when _T_1585 : node _T_1586 = eq(address_ok, UInt<1>(0h0)) when _T_1586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1587 = asUInt(reset) node _T_1588 = eq(_T_1587, UInt<1>(0h0)) when _T_1588 : node _T_1589 = eq(legal_source, UInt<1>(0h0)) when _T_1589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1593 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(_T_1593, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1593, UInt<1>(0h1), "") : assert_110 node _T_1597 = not(mask_1) node _T_1598 = and(io.in.b.bits.mask, _T_1597) node _T_1599 = eq(_T_1598, UInt<1>(0h0)) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_111 node _T_1603 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1603 : node _T_1604 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1605 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1606 = and(_T_1604, _T_1605) node _T_1607 = or(UInt<1>(0h0), _T_1606) node _T_1608 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1609 = cvt(_T_1608) node _T_1610 = and(_T_1609, asSInt(UInt<14>(0h2000))) node _T_1611 = asSInt(_T_1610) node _T_1612 = eq(_T_1611, asSInt(UInt<1>(0h0))) node _T_1613 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1614 = cvt(_T_1613) node _T_1615 = and(_T_1614, asSInt(UInt<13>(0h1000))) node _T_1616 = asSInt(_T_1615) node _T_1617 = eq(_T_1616, asSInt(UInt<1>(0h0))) node _T_1618 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1619 = cvt(_T_1618) node _T_1620 = and(_T_1619, asSInt(UInt<17>(0h10000))) node _T_1621 = asSInt(_T_1620) node _T_1622 = eq(_T_1621, asSInt(UInt<1>(0h0))) node _T_1623 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1624 = cvt(_T_1623) node _T_1625 = and(_T_1624, asSInt(UInt<18>(0h2f000))) node _T_1626 = asSInt(_T_1625) node _T_1627 = eq(_T_1626, asSInt(UInt<1>(0h0))) node _T_1628 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1629 = cvt(_T_1628) node _T_1630 = and(_T_1629, asSInt(UInt<17>(0h10000))) node _T_1631 = asSInt(_T_1630) node _T_1632 = eq(_T_1631, asSInt(UInt<1>(0h0))) node _T_1633 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1634 = cvt(_T_1633) node _T_1635 = and(_T_1634, asSInt(UInt<13>(0h1000))) node _T_1636 = asSInt(_T_1635) node _T_1637 = eq(_T_1636, asSInt(UInt<1>(0h0))) node _T_1638 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1639 = cvt(_T_1638) node _T_1640 = and(_T_1639, asSInt(UInt<17>(0h10000))) node _T_1641 = asSInt(_T_1640) node _T_1642 = eq(_T_1641, asSInt(UInt<1>(0h0))) node _T_1643 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1644 = cvt(_T_1643) node _T_1645 = and(_T_1644, asSInt(UInt<27>(0h4000000))) node _T_1646 = asSInt(_T_1645) node _T_1647 = eq(_T_1646, asSInt(UInt<1>(0h0))) node _T_1648 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1649 = cvt(_T_1648) node _T_1650 = and(_T_1649, asSInt(UInt<13>(0h1000))) node _T_1651 = asSInt(_T_1650) node _T_1652 = eq(_T_1651, asSInt(UInt<1>(0h0))) node _T_1653 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1654 = cvt(_T_1653) node _T_1655 = and(_T_1654, asSInt(UInt<29>(0h10000000))) node _T_1656 = asSInt(_T_1655) node _T_1657 = eq(_T_1656, asSInt(UInt<1>(0h0))) node _T_1658 = or(_T_1612, _T_1617) node _T_1659 = or(_T_1658, _T_1622) node _T_1660 = or(_T_1659, _T_1627) node _T_1661 = or(_T_1660, _T_1632) node _T_1662 = or(_T_1661, _T_1637) node _T_1663 = or(_T_1662, _T_1642) node _T_1664 = or(_T_1663, _T_1647) node _T_1665 = or(_T_1664, _T_1652) node _T_1666 = or(_T_1665, _T_1657) node _T_1667 = and(_T_1607, _T_1666) node _T_1668 = or(UInt<1>(0h0), _T_1667) node _T_1669 = and(UInt<1>(0h0), _T_1668) node _T_1670 = asUInt(reset) node _T_1671 = eq(_T_1670, UInt<1>(0h0)) when _T_1671 : node _T_1672 = eq(_T_1669, UInt<1>(0h0)) when _T_1672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1669, UInt<1>(0h1), "") : assert_112 node _T_1673 = asUInt(reset) node _T_1674 = eq(_T_1673, UInt<1>(0h0)) when _T_1674 : node _T_1675 = eq(address_ok, UInt<1>(0h0)) when _T_1675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1676 = asUInt(reset) node _T_1677 = eq(_T_1676, UInt<1>(0h0)) when _T_1677 : node _T_1678 = eq(legal_source, UInt<1>(0h0)) when _T_1678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1679 = asUInt(reset) node _T_1680 = eq(_T_1679, UInt<1>(0h0)) when _T_1680 : node _T_1681 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1682 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1683 = asUInt(reset) node _T_1684 = eq(_T_1683, UInt<1>(0h0)) when _T_1684 : node _T_1685 = eq(_T_1682, UInt<1>(0h0)) when _T_1685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1682, UInt<1>(0h1), "") : assert_116 node _T_1686 = eq(io.in.b.bits.mask, mask_1) node _T_1687 = asUInt(reset) node _T_1688 = eq(_T_1687, UInt<1>(0h0)) when _T_1688 : node _T_1689 = eq(_T_1686, UInt<1>(0h0)) when _T_1689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1686, UInt<1>(0h1), "") : assert_117 node _T_1690 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1690 : node _T_1691 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1692 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1693 = and(_T_1691, _T_1692) node _T_1694 = or(UInt<1>(0h0), _T_1693) node _T_1695 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1696 = cvt(_T_1695) node _T_1697 = and(_T_1696, asSInt(UInt<14>(0h2000))) node _T_1698 = asSInt(_T_1697) node _T_1699 = eq(_T_1698, asSInt(UInt<1>(0h0))) node _T_1700 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1701 = cvt(_T_1700) node _T_1702 = and(_T_1701, asSInt(UInt<13>(0h1000))) node _T_1703 = asSInt(_T_1702) node _T_1704 = eq(_T_1703, asSInt(UInt<1>(0h0))) node _T_1705 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1706 = cvt(_T_1705) node _T_1707 = and(_T_1706, asSInt(UInt<17>(0h10000))) node _T_1708 = asSInt(_T_1707) node _T_1709 = eq(_T_1708, asSInt(UInt<1>(0h0))) node _T_1710 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1711 = cvt(_T_1710) node _T_1712 = and(_T_1711, asSInt(UInt<18>(0h2f000))) node _T_1713 = asSInt(_T_1712) node _T_1714 = eq(_T_1713, asSInt(UInt<1>(0h0))) node _T_1715 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1716 = cvt(_T_1715) node _T_1717 = and(_T_1716, asSInt(UInt<17>(0h10000))) node _T_1718 = asSInt(_T_1717) node _T_1719 = eq(_T_1718, asSInt(UInt<1>(0h0))) node _T_1720 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1721 = cvt(_T_1720) node _T_1722 = and(_T_1721, asSInt(UInt<13>(0h1000))) node _T_1723 = asSInt(_T_1722) node _T_1724 = eq(_T_1723, asSInt(UInt<1>(0h0))) node _T_1725 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1726 = cvt(_T_1725) node _T_1727 = and(_T_1726, asSInt(UInt<17>(0h10000))) node _T_1728 = asSInt(_T_1727) node _T_1729 = eq(_T_1728, asSInt(UInt<1>(0h0))) node _T_1730 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1731 = cvt(_T_1730) node _T_1732 = and(_T_1731, asSInt(UInt<27>(0h4000000))) node _T_1733 = asSInt(_T_1732) node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0))) node _T_1735 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1736 = cvt(_T_1735) node _T_1737 = and(_T_1736, asSInt(UInt<13>(0h1000))) node _T_1738 = asSInt(_T_1737) node _T_1739 = eq(_T_1738, asSInt(UInt<1>(0h0))) node _T_1740 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1741 = cvt(_T_1740) node _T_1742 = and(_T_1741, asSInt(UInt<29>(0h10000000))) node _T_1743 = asSInt(_T_1742) node _T_1744 = eq(_T_1743, asSInt(UInt<1>(0h0))) node _T_1745 = or(_T_1699, _T_1704) node _T_1746 = or(_T_1745, _T_1709) node _T_1747 = or(_T_1746, _T_1714) node _T_1748 = or(_T_1747, _T_1719) node _T_1749 = or(_T_1748, _T_1724) node _T_1750 = or(_T_1749, _T_1729) node _T_1751 = or(_T_1750, _T_1734) node _T_1752 = or(_T_1751, _T_1739) node _T_1753 = or(_T_1752, _T_1744) node _T_1754 = and(_T_1694, _T_1753) node _T_1755 = or(UInt<1>(0h0), _T_1754) node _T_1756 = and(UInt<1>(0h0), _T_1755) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_118 node _T_1760 = asUInt(reset) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) when _T_1761 : node _T_1762 = eq(address_ok, UInt<1>(0h0)) when _T_1762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(legal_source, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1769 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_122 node _T_1773 = eq(io.in.b.bits.mask, mask_1) node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(_T_1773, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1773, UInt<1>(0h1), "") : assert_123 node _T_1777 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1777 : node _T_1778 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1779 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1780 = and(_T_1778, _T_1779) node _T_1781 = or(UInt<1>(0h0), _T_1780) node _T_1782 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1783 = cvt(_T_1782) node _T_1784 = and(_T_1783, asSInt(UInt<14>(0h2000))) node _T_1785 = asSInt(_T_1784) node _T_1786 = eq(_T_1785, asSInt(UInt<1>(0h0))) node _T_1787 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1788 = cvt(_T_1787) node _T_1789 = and(_T_1788, asSInt(UInt<13>(0h1000))) node _T_1790 = asSInt(_T_1789) node _T_1791 = eq(_T_1790, asSInt(UInt<1>(0h0))) node _T_1792 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1793 = cvt(_T_1792) node _T_1794 = and(_T_1793, asSInt(UInt<17>(0h10000))) node _T_1795 = asSInt(_T_1794) node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0))) node _T_1797 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1798 = cvt(_T_1797) node _T_1799 = and(_T_1798, asSInt(UInt<18>(0h2f000))) node _T_1800 = asSInt(_T_1799) node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0))) node _T_1802 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1803 = cvt(_T_1802) node _T_1804 = and(_T_1803, asSInt(UInt<17>(0h10000))) node _T_1805 = asSInt(_T_1804) node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0))) node _T_1807 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1808 = cvt(_T_1807) node _T_1809 = and(_T_1808, asSInt(UInt<13>(0h1000))) node _T_1810 = asSInt(_T_1809) node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0))) node _T_1812 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<27>(0h4000000))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1823 = cvt(_T_1822) node _T_1824 = and(_T_1823, asSInt(UInt<13>(0h1000))) node _T_1825 = asSInt(_T_1824) node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0))) node _T_1827 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1828 = cvt(_T_1827) node _T_1829 = and(_T_1828, asSInt(UInt<29>(0h10000000))) node _T_1830 = asSInt(_T_1829) node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0))) node _T_1832 = or(_T_1786, _T_1791) node _T_1833 = or(_T_1832, _T_1796) node _T_1834 = or(_T_1833, _T_1801) node _T_1835 = or(_T_1834, _T_1806) node _T_1836 = or(_T_1835, _T_1811) node _T_1837 = or(_T_1836, _T_1816) node _T_1838 = or(_T_1837, _T_1821) node _T_1839 = or(_T_1838, _T_1826) node _T_1840 = or(_T_1839, _T_1831) node _T_1841 = and(_T_1781, _T_1840) node _T_1842 = or(UInt<1>(0h0), _T_1841) node _T_1843 = and(UInt<1>(0h0), _T_1842) node _T_1844 = asUInt(reset) node _T_1845 = eq(_T_1844, UInt<1>(0h0)) when _T_1845 : node _T_1846 = eq(_T_1843, UInt<1>(0h0)) when _T_1846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1843, UInt<1>(0h1), "") : assert_124 node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(address_ok, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1850 = asUInt(reset) node _T_1851 = eq(_T_1850, UInt<1>(0h0)) when _T_1851 : node _T_1852 = eq(legal_source, UInt<1>(0h0)) when _T_1852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1853 = asUInt(reset) node _T_1854 = eq(_T_1853, UInt<1>(0h0)) when _T_1854 : node _T_1855 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1855 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1856 = eq(io.in.b.bits.mask, mask_1) node _T_1857 = asUInt(reset) node _T_1858 = eq(_T_1857, UInt<1>(0h0)) when _T_1858 : node _T_1859 = eq(_T_1856, UInt<1>(0h0)) when _T_1859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1856, UInt<1>(0h1), "") : assert_128 node _T_1860 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1861 = asUInt(reset) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : node _T_1863 = eq(_T_1860, UInt<1>(0h0)) when _T_1863 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1860, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1864 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(_T_1864, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1864, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_18 = shr(io.in.c.bits.source, 2) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_2, UInt<2>(0h2)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_T_24 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _source_ok_T_25 = eq(io.in.c.bits.source, UInt<3>(0h4)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_23 connect _source_ok_WIRE_2[1], _source_ok_T_24 connect _source_ok_WIRE_2[2], _source_ok_T_25 node _source_ok_T_26 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_26, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_1868 = shr(io.in.c.bits.source, 2) node _T_1869 = eq(_T_1868, UInt<1>(0h0)) node _T_1870 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1871 = and(_T_1869, _T_1870) node _T_1872 = leq(uncommonBits_13, UInt<2>(0h2)) node _T_1873 = and(_T_1871, _T_1872) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) node _T_1875 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1876 = cvt(_T_1875) node _T_1877 = and(_T_1876, asSInt(UInt<1>(0h0))) node _T_1878 = asSInt(_T_1877) node _T_1879 = eq(_T_1878, asSInt(UInt<1>(0h0))) node _T_1880 = or(_T_1874, _T_1879) node _T_1881 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_1882 = eq(_T_1881, UInt<1>(0h0)) node _T_1883 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1884 = cvt(_T_1883) node _T_1885 = and(_T_1884, asSInt(UInt<1>(0h0))) node _T_1886 = asSInt(_T_1885) node _T_1887 = eq(_T_1886, asSInt(UInt<1>(0h0))) node _T_1888 = or(_T_1882, _T_1887) node _T_1889 = eq(io.in.c.bits.source, UInt<3>(0h4)) node _T_1890 = eq(_T_1889, UInt<1>(0h0)) node _T_1891 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1892 = cvt(_T_1891) node _T_1893 = and(_T_1892, asSInt(UInt<1>(0h0))) node _T_1894 = asSInt(_T_1893) node _T_1895 = eq(_T_1894, asSInt(UInt<1>(0h0))) node _T_1896 = or(_T_1890, _T_1895) node _T_1897 = and(_T_1880, _T_1888) node _T_1898 = and(_T_1897, _T_1896) node _T_1899 = asUInt(reset) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) when _T_1900 : node _T_1901 = eq(_T_1898, UInt<1>(0h0)) when _T_1901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1898, UInt<1>(0h1), "") : assert_131 node _T_1902 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1902 : node _T_1903 = asUInt(reset) node _T_1904 = eq(_T_1903, UInt<1>(0h0)) when _T_1904 : node _T_1905 = eq(address_ok_1, UInt<1>(0h0)) when _T_1905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1906 = asUInt(reset) node _T_1907 = eq(_T_1906, UInt<1>(0h0)) when _T_1907 : node _T_1908 = eq(source_ok_2, UInt<1>(0h0)) when _T_1908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1909 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1910 = asUInt(reset) node _T_1911 = eq(_T_1910, UInt<1>(0h0)) when _T_1911 : node _T_1912 = eq(_T_1909, UInt<1>(0h0)) when _T_1912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1909, UInt<1>(0h1), "") : assert_134 node _T_1913 = asUInt(reset) node _T_1914 = eq(_T_1913, UInt<1>(0h0)) when _T_1914 : node _T_1915 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1916 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1917 = asUInt(reset) node _T_1918 = eq(_T_1917, UInt<1>(0h0)) when _T_1918 : node _T_1919 = eq(_T_1916, UInt<1>(0h0)) when _T_1919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1916, UInt<1>(0h1), "") : assert_136 node _T_1920 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1921 = asUInt(reset) node _T_1922 = eq(_T_1921, UInt<1>(0h0)) when _T_1922 : node _T_1923 = eq(_T_1920, UInt<1>(0h0)) when _T_1923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1920, UInt<1>(0h1), "") : assert_137 node _T_1924 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1924 : node _T_1925 = asUInt(reset) node _T_1926 = eq(_T_1925, UInt<1>(0h0)) when _T_1926 : node _T_1927 = eq(address_ok_1, UInt<1>(0h0)) when _T_1927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1928 = asUInt(reset) node _T_1929 = eq(_T_1928, UInt<1>(0h0)) when _T_1929 : node _T_1930 = eq(source_ok_2, UInt<1>(0h0)) when _T_1930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1931 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1932 = asUInt(reset) node _T_1933 = eq(_T_1932, UInt<1>(0h0)) when _T_1933 : node _T_1934 = eq(_T_1931, UInt<1>(0h0)) when _T_1934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1931, UInt<1>(0h1), "") : assert_140 node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1938 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1939 = asUInt(reset) node _T_1940 = eq(_T_1939, UInt<1>(0h0)) when _T_1940 : node _T_1941 = eq(_T_1938, UInt<1>(0h0)) when _T_1941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1938, UInt<1>(0h1), "") : assert_142 node _T_1942 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1942 : node _T_1943 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1944 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1945 = and(_T_1943, _T_1944) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_1946 = shr(io.in.c.bits.source, 2) node _T_1947 = eq(_T_1946, UInt<1>(0h0)) node _T_1948 = leq(UInt<1>(0h0), uncommonBits_14) node _T_1949 = and(_T_1947, _T_1948) node _T_1950 = leq(uncommonBits_14, UInt<2>(0h2)) node _T_1951 = and(_T_1949, _T_1950) node _T_1952 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_1953 = eq(io.in.c.bits.source, UInt<3>(0h4)) node _T_1954 = or(_T_1951, _T_1952) node _T_1955 = or(_T_1954, _T_1953) node _T_1956 = and(_T_1945, _T_1955) node _T_1957 = or(UInt<1>(0h0), _T_1956) node _T_1958 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1959 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1960 = cvt(_T_1959) node _T_1961 = and(_T_1960, asSInt(UInt<14>(0h2000))) node _T_1962 = asSInt(_T_1961) node _T_1963 = eq(_T_1962, asSInt(UInt<1>(0h0))) node _T_1964 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1965 = cvt(_T_1964) node _T_1966 = and(_T_1965, asSInt(UInt<13>(0h1000))) node _T_1967 = asSInt(_T_1966) node _T_1968 = eq(_T_1967, asSInt(UInt<1>(0h0))) node _T_1969 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1970 = cvt(_T_1969) node _T_1971 = and(_T_1970, asSInt(UInt<17>(0h10000))) node _T_1972 = asSInt(_T_1971) node _T_1973 = eq(_T_1972, asSInt(UInt<1>(0h0))) node _T_1974 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1975 = cvt(_T_1974) node _T_1976 = and(_T_1975, asSInt(UInt<18>(0h2f000))) node _T_1977 = asSInt(_T_1976) node _T_1978 = eq(_T_1977, asSInt(UInt<1>(0h0))) node _T_1979 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1980 = cvt(_T_1979) node _T_1981 = and(_T_1980, asSInt(UInt<17>(0h10000))) node _T_1982 = asSInt(_T_1981) node _T_1983 = eq(_T_1982, asSInt(UInt<1>(0h0))) node _T_1984 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1985 = cvt(_T_1984) node _T_1986 = and(_T_1985, asSInt(UInt<13>(0h1000))) node _T_1987 = asSInt(_T_1986) node _T_1988 = eq(_T_1987, asSInt(UInt<1>(0h0))) node _T_1989 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1990 = cvt(_T_1989) node _T_1991 = and(_T_1990, asSInt(UInt<27>(0h4000000))) node _T_1992 = asSInt(_T_1991) node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0))) node _T_1994 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1995 = cvt(_T_1994) node _T_1996 = and(_T_1995, asSInt(UInt<13>(0h1000))) node _T_1997 = asSInt(_T_1996) node _T_1998 = eq(_T_1997, asSInt(UInt<1>(0h0))) node _T_1999 = or(_T_1963, _T_1968) node _T_2000 = or(_T_1999, _T_1973) node _T_2001 = or(_T_2000, _T_1978) node _T_2002 = or(_T_2001, _T_1983) node _T_2003 = or(_T_2002, _T_1988) node _T_2004 = or(_T_2003, _T_1993) node _T_2005 = or(_T_2004, _T_1998) node _T_2006 = and(_T_1958, _T_2005) node _T_2007 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2008 = or(UInt<1>(0h0), _T_2007) node _T_2009 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2010 = cvt(_T_2009) node _T_2011 = and(_T_2010, asSInt(UInt<17>(0h10000))) node _T_2012 = asSInt(_T_2011) node _T_2013 = eq(_T_2012, asSInt(UInt<1>(0h0))) node _T_2014 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2015 = cvt(_T_2014) node _T_2016 = and(_T_2015, asSInt(UInt<29>(0h10000000))) node _T_2017 = asSInt(_T_2016) node _T_2018 = eq(_T_2017, asSInt(UInt<1>(0h0))) node _T_2019 = or(_T_2013, _T_2018) node _T_2020 = and(_T_2008, _T_2019) node _T_2021 = or(UInt<1>(0h0), _T_2006) node _T_2022 = or(_T_2021, _T_2020) node _T_2023 = and(_T_1957, _T_2022) node _T_2024 = asUInt(reset) node _T_2025 = eq(_T_2024, UInt<1>(0h0)) when _T_2025 : node _T_2026 = eq(_T_2023, UInt<1>(0h0)) when _T_2026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2023, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_2027 = shr(io.in.c.bits.source, 2) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) node _T_2029 = leq(UInt<1>(0h0), uncommonBits_15) node _T_2030 = and(_T_2028, _T_2029) node _T_2031 = leq(uncommonBits_15, UInt<2>(0h2)) node _T_2032 = and(_T_2030, _T_2031) node _T_2033 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_2034 = eq(io.in.c.bits.source, UInt<3>(0h4)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_2032 connect _WIRE_6[1], _T_2033 connect _WIRE_6[2], _T_2034 node _T_2035 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2036 = mux(_WIRE_6[0], _T_2035, UInt<1>(0h0)) node _T_2037 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2038 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2039 = or(_T_2036, _T_2037) node _T_2040 = or(_T_2039, _T_2038) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2040 node _T_2041 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2042 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2043 = and(_T_2041, _T_2042) node _T_2044 = or(UInt<1>(0h0), _T_2043) node _T_2045 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2046 = cvt(_T_2045) node _T_2047 = and(_T_2046, asSInt(UInt<14>(0h2000))) node _T_2048 = asSInt(_T_2047) node _T_2049 = eq(_T_2048, asSInt(UInt<1>(0h0))) node _T_2050 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2051 = cvt(_T_2050) node _T_2052 = and(_T_2051, asSInt(UInt<13>(0h1000))) node _T_2053 = asSInt(_T_2052) node _T_2054 = eq(_T_2053, asSInt(UInt<1>(0h0))) node _T_2055 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2056 = cvt(_T_2055) node _T_2057 = and(_T_2056, asSInt(UInt<17>(0h10000))) node _T_2058 = asSInt(_T_2057) node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0))) node _T_2060 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<18>(0h2f000))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2066 = cvt(_T_2065) node _T_2067 = and(_T_2066, asSInt(UInt<17>(0h10000))) node _T_2068 = asSInt(_T_2067) node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) node _T_2070 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<13>(0h1000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<17>(0h10000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<27>(0h4000000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<29>(0h10000000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = or(_T_2049, _T_2054) node _T_2096 = or(_T_2095, _T_2059) node _T_2097 = or(_T_2096, _T_2064) node _T_2098 = or(_T_2097, _T_2069) node _T_2099 = or(_T_2098, _T_2074) node _T_2100 = or(_T_2099, _T_2079) node _T_2101 = or(_T_2100, _T_2084) node _T_2102 = or(_T_2101, _T_2089) node _T_2103 = or(_T_2102, _T_2094) node _T_2104 = and(_T_2044, _T_2103) node _T_2105 = or(UInt<1>(0h0), _T_2104) node _T_2106 = and(_WIRE_7, _T_2105) node _T_2107 = asUInt(reset) node _T_2108 = eq(_T_2107, UInt<1>(0h0)) when _T_2108 : node _T_2109 = eq(_T_2106, UInt<1>(0h0)) when _T_2109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2106, UInt<1>(0h1), "") : assert_144 node _T_2110 = asUInt(reset) node _T_2111 = eq(_T_2110, UInt<1>(0h0)) when _T_2111 : node _T_2112 = eq(source_ok_2, UInt<1>(0h0)) when _T_2112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2113 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2114 = asUInt(reset) node _T_2115 = eq(_T_2114, UInt<1>(0h0)) when _T_2115 : node _T_2116 = eq(_T_2113, UInt<1>(0h0)) when _T_2116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2113, UInt<1>(0h1), "") : assert_146 node _T_2117 = asUInt(reset) node _T_2118 = eq(_T_2117, UInt<1>(0h0)) when _T_2118 : node _T_2119 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2120 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2121 = asUInt(reset) node _T_2122 = eq(_T_2121, UInt<1>(0h0)) when _T_2122 : node _T_2123 = eq(_T_2120, UInt<1>(0h0)) when _T_2123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2120, UInt<1>(0h1), "") : assert_148 node _T_2124 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2125 = asUInt(reset) node _T_2126 = eq(_T_2125, UInt<1>(0h0)) when _T_2126 : node _T_2127 = eq(_T_2124, UInt<1>(0h0)) when _T_2127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2124, UInt<1>(0h1), "") : assert_149 node _T_2128 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2128 : node _T_2129 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2130 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2131 = and(_T_2129, _T_2130) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_2132 = shr(io.in.c.bits.source, 2) node _T_2133 = eq(_T_2132, UInt<1>(0h0)) node _T_2134 = leq(UInt<1>(0h0), uncommonBits_16) node _T_2135 = and(_T_2133, _T_2134) node _T_2136 = leq(uncommonBits_16, UInt<2>(0h2)) node _T_2137 = and(_T_2135, _T_2136) node _T_2138 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_2139 = eq(io.in.c.bits.source, UInt<3>(0h4)) node _T_2140 = or(_T_2137, _T_2138) node _T_2141 = or(_T_2140, _T_2139) node _T_2142 = and(_T_2131, _T_2141) node _T_2143 = or(UInt<1>(0h0), _T_2142) node _T_2144 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2145 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2146 = cvt(_T_2145) node _T_2147 = and(_T_2146, asSInt(UInt<14>(0h2000))) node _T_2148 = asSInt(_T_2147) node _T_2149 = eq(_T_2148, asSInt(UInt<1>(0h0))) node _T_2150 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2151 = cvt(_T_2150) node _T_2152 = and(_T_2151, asSInt(UInt<13>(0h1000))) node _T_2153 = asSInt(_T_2152) node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0))) node _T_2155 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2156 = cvt(_T_2155) node _T_2157 = and(_T_2156, asSInt(UInt<17>(0h10000))) node _T_2158 = asSInt(_T_2157) node _T_2159 = eq(_T_2158, asSInt(UInt<1>(0h0))) node _T_2160 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2161 = cvt(_T_2160) node _T_2162 = and(_T_2161, asSInt(UInt<18>(0h2f000))) node _T_2163 = asSInt(_T_2162) node _T_2164 = eq(_T_2163, asSInt(UInt<1>(0h0))) node _T_2165 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2166 = cvt(_T_2165) node _T_2167 = and(_T_2166, asSInt(UInt<17>(0h10000))) node _T_2168 = asSInt(_T_2167) node _T_2169 = eq(_T_2168, asSInt(UInt<1>(0h0))) node _T_2170 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2171 = cvt(_T_2170) node _T_2172 = and(_T_2171, asSInt(UInt<13>(0h1000))) node _T_2173 = asSInt(_T_2172) node _T_2174 = eq(_T_2173, asSInt(UInt<1>(0h0))) node _T_2175 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2176 = cvt(_T_2175) node _T_2177 = and(_T_2176, asSInt(UInt<27>(0h4000000))) node _T_2178 = asSInt(_T_2177) node _T_2179 = eq(_T_2178, asSInt(UInt<1>(0h0))) node _T_2180 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2181 = cvt(_T_2180) node _T_2182 = and(_T_2181, asSInt(UInt<13>(0h1000))) node _T_2183 = asSInt(_T_2182) node _T_2184 = eq(_T_2183, asSInt(UInt<1>(0h0))) node _T_2185 = or(_T_2149, _T_2154) node _T_2186 = or(_T_2185, _T_2159) node _T_2187 = or(_T_2186, _T_2164) node _T_2188 = or(_T_2187, _T_2169) node _T_2189 = or(_T_2188, _T_2174) node _T_2190 = or(_T_2189, _T_2179) node _T_2191 = or(_T_2190, _T_2184) node _T_2192 = and(_T_2144, _T_2191) node _T_2193 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2194 = or(UInt<1>(0h0), _T_2193) node _T_2195 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2196 = cvt(_T_2195) node _T_2197 = and(_T_2196, asSInt(UInt<17>(0h10000))) node _T_2198 = asSInt(_T_2197) node _T_2199 = eq(_T_2198, asSInt(UInt<1>(0h0))) node _T_2200 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2201 = cvt(_T_2200) node _T_2202 = and(_T_2201, asSInt(UInt<29>(0h10000000))) node _T_2203 = asSInt(_T_2202) node _T_2204 = eq(_T_2203, asSInt(UInt<1>(0h0))) node _T_2205 = or(_T_2199, _T_2204) node _T_2206 = and(_T_2194, _T_2205) node _T_2207 = or(UInt<1>(0h0), _T_2192) node _T_2208 = or(_T_2207, _T_2206) node _T_2209 = and(_T_2143, _T_2208) node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : node _T_2212 = eq(_T_2209, UInt<1>(0h0)) when _T_2212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2209, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_2213 = shr(io.in.c.bits.source, 2) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) node _T_2215 = leq(UInt<1>(0h0), uncommonBits_17) node _T_2216 = and(_T_2214, _T_2215) node _T_2217 = leq(uncommonBits_17, UInt<2>(0h2)) node _T_2218 = and(_T_2216, _T_2217) node _T_2219 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_2220 = eq(io.in.c.bits.source, UInt<3>(0h4)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2218 connect _WIRE_8[1], _T_2219 connect _WIRE_8[2], _T_2220 node _T_2221 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2222 = mux(_WIRE_8[0], _T_2221, UInt<1>(0h0)) node _T_2223 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2224 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2225 = or(_T_2222, _T_2223) node _T_2226 = or(_T_2225, _T_2224) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2226 node _T_2227 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2228 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2229 = and(_T_2227, _T_2228) node _T_2230 = or(UInt<1>(0h0), _T_2229) node _T_2231 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2232 = cvt(_T_2231) node _T_2233 = and(_T_2232, asSInt(UInt<14>(0h2000))) node _T_2234 = asSInt(_T_2233) node _T_2235 = eq(_T_2234, asSInt(UInt<1>(0h0))) node _T_2236 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2237 = cvt(_T_2236) node _T_2238 = and(_T_2237, asSInt(UInt<13>(0h1000))) node _T_2239 = asSInt(_T_2238) node _T_2240 = eq(_T_2239, asSInt(UInt<1>(0h0))) node _T_2241 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2242 = cvt(_T_2241) node _T_2243 = and(_T_2242, asSInt(UInt<17>(0h10000))) node _T_2244 = asSInt(_T_2243) node _T_2245 = eq(_T_2244, asSInt(UInt<1>(0h0))) node _T_2246 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2247 = cvt(_T_2246) node _T_2248 = and(_T_2247, asSInt(UInt<18>(0h2f000))) node _T_2249 = asSInt(_T_2248) node _T_2250 = eq(_T_2249, asSInt(UInt<1>(0h0))) node _T_2251 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2252 = cvt(_T_2251) node _T_2253 = and(_T_2252, asSInt(UInt<17>(0h10000))) node _T_2254 = asSInt(_T_2253) node _T_2255 = eq(_T_2254, asSInt(UInt<1>(0h0))) node _T_2256 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2257 = cvt(_T_2256) node _T_2258 = and(_T_2257, asSInt(UInt<13>(0h1000))) node _T_2259 = asSInt(_T_2258) node _T_2260 = eq(_T_2259, asSInt(UInt<1>(0h0))) node _T_2261 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2262 = cvt(_T_2261) node _T_2263 = and(_T_2262, asSInt(UInt<17>(0h10000))) node _T_2264 = asSInt(_T_2263) node _T_2265 = eq(_T_2264, asSInt(UInt<1>(0h0))) node _T_2266 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2267 = cvt(_T_2266) node _T_2268 = and(_T_2267, asSInt(UInt<27>(0h4000000))) node _T_2269 = asSInt(_T_2268) node _T_2270 = eq(_T_2269, asSInt(UInt<1>(0h0))) node _T_2271 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2272 = cvt(_T_2271) node _T_2273 = and(_T_2272, asSInt(UInt<13>(0h1000))) node _T_2274 = asSInt(_T_2273) node _T_2275 = eq(_T_2274, asSInt(UInt<1>(0h0))) node _T_2276 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2277 = cvt(_T_2276) node _T_2278 = and(_T_2277, asSInt(UInt<29>(0h10000000))) node _T_2279 = asSInt(_T_2278) node _T_2280 = eq(_T_2279, asSInt(UInt<1>(0h0))) node _T_2281 = or(_T_2235, _T_2240) node _T_2282 = or(_T_2281, _T_2245) node _T_2283 = or(_T_2282, _T_2250) node _T_2284 = or(_T_2283, _T_2255) node _T_2285 = or(_T_2284, _T_2260) node _T_2286 = or(_T_2285, _T_2265) node _T_2287 = or(_T_2286, _T_2270) node _T_2288 = or(_T_2287, _T_2275) node _T_2289 = or(_T_2288, _T_2280) node _T_2290 = and(_T_2230, _T_2289) node _T_2291 = or(UInt<1>(0h0), _T_2290) node _T_2292 = and(_WIRE_9, _T_2291) node _T_2293 = asUInt(reset) node _T_2294 = eq(_T_2293, UInt<1>(0h0)) when _T_2294 : node _T_2295 = eq(_T_2292, UInt<1>(0h0)) when _T_2295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2292, UInt<1>(0h1), "") : assert_151 node _T_2296 = asUInt(reset) node _T_2297 = eq(_T_2296, UInt<1>(0h0)) when _T_2297 : node _T_2298 = eq(source_ok_2, UInt<1>(0h0)) when _T_2298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2299 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2300 = asUInt(reset) node _T_2301 = eq(_T_2300, UInt<1>(0h0)) when _T_2301 : node _T_2302 = eq(_T_2299, UInt<1>(0h0)) when _T_2302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2299, UInt<1>(0h1), "") : assert_153 node _T_2303 = asUInt(reset) node _T_2304 = eq(_T_2303, UInt<1>(0h0)) when _T_2304 : node _T_2305 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2306 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2307 = asUInt(reset) node _T_2308 = eq(_T_2307, UInt<1>(0h0)) when _T_2308 : node _T_2309 = eq(_T_2306, UInt<1>(0h0)) when _T_2309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2306, UInt<1>(0h1), "") : assert_155 node _T_2310 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2310 : node _T_2311 = asUInt(reset) node _T_2312 = eq(_T_2311, UInt<1>(0h0)) when _T_2312 : node _T_2313 = eq(address_ok_1, UInt<1>(0h0)) when _T_2313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2314 = asUInt(reset) node _T_2315 = eq(_T_2314, UInt<1>(0h0)) when _T_2315 : node _T_2316 = eq(source_ok_2, UInt<1>(0h0)) when _T_2316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2317 = asUInt(reset) node _T_2318 = eq(_T_2317, UInt<1>(0h0)) when _T_2318 : node _T_2319 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2320 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2321 = asUInt(reset) node _T_2322 = eq(_T_2321, UInt<1>(0h0)) when _T_2322 : node _T_2323 = eq(_T_2320, UInt<1>(0h0)) when _T_2323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2320, UInt<1>(0h1), "") : assert_159 node _T_2324 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2325 = asUInt(reset) node _T_2326 = eq(_T_2325, UInt<1>(0h0)) when _T_2326 : node _T_2327 = eq(_T_2324, UInt<1>(0h0)) when _T_2327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2324, UInt<1>(0h1), "") : assert_160 node _T_2328 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2328 : node _T_2329 = asUInt(reset) node _T_2330 = eq(_T_2329, UInt<1>(0h0)) when _T_2330 : node _T_2331 = eq(address_ok_1, UInt<1>(0h0)) when _T_2331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2332 = asUInt(reset) node _T_2333 = eq(_T_2332, UInt<1>(0h0)) when _T_2333 : node _T_2334 = eq(source_ok_2, UInt<1>(0h0)) when _T_2334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2335 = asUInt(reset) node _T_2336 = eq(_T_2335, UInt<1>(0h0)) when _T_2336 : node _T_2337 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2338 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2339 = asUInt(reset) node _T_2340 = eq(_T_2339, UInt<1>(0h0)) when _T_2340 : node _T_2341 = eq(_T_2338, UInt<1>(0h0)) when _T_2341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2338, UInt<1>(0h1), "") : assert_164 node _T_2342 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2342 : node _T_2343 = asUInt(reset) node _T_2344 = eq(_T_2343, UInt<1>(0h0)) when _T_2344 : node _T_2345 = eq(address_ok_1, UInt<1>(0h0)) when _T_2345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2346 = asUInt(reset) node _T_2347 = eq(_T_2346, UInt<1>(0h0)) when _T_2347 : node _T_2348 = eq(source_ok_2, UInt<1>(0h0)) when _T_2348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2349 = asUInt(reset) node _T_2350 = eq(_T_2349, UInt<1>(0h0)) when _T_2350 : node _T_2351 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2352 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2353 = asUInt(reset) node _T_2354 = eq(_T_2353, UInt<1>(0h0)) when _T_2354 : node _T_2355 = eq(_T_2352, UInt<1>(0h0)) when _T_2355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2352, UInt<1>(0h1), "") : assert_168 node _T_2356 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2357 = asUInt(reset) node _T_2358 = eq(_T_2357, UInt<1>(0h0)) when _T_2358 : node _T_2359 = eq(_T_2356, UInt<1>(0h0)) when _T_2359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2356, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2360 = asUInt(reset) node _T_2361 = eq(_T_2360, UInt<1>(0h0)) when _T_2361 : node _T_2362 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2363 = eq(a_first, UInt<1>(0h0)) node _T_2364 = and(io.in.a.valid, _T_2363) when _T_2364 : node _T_2365 = eq(io.in.a.bits.opcode, opcode) node _T_2366 = asUInt(reset) node _T_2367 = eq(_T_2366, UInt<1>(0h0)) when _T_2367 : node _T_2368 = eq(_T_2365, UInt<1>(0h0)) when _T_2368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2365, UInt<1>(0h1), "") : assert_171 node _T_2369 = eq(io.in.a.bits.param, param) node _T_2370 = asUInt(reset) node _T_2371 = eq(_T_2370, UInt<1>(0h0)) when _T_2371 : node _T_2372 = eq(_T_2369, UInt<1>(0h0)) when _T_2372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2369, UInt<1>(0h1), "") : assert_172 node _T_2373 = eq(io.in.a.bits.size, size) node _T_2374 = asUInt(reset) node _T_2375 = eq(_T_2374, UInt<1>(0h0)) when _T_2375 : node _T_2376 = eq(_T_2373, UInt<1>(0h0)) when _T_2376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2373, UInt<1>(0h1), "") : assert_173 node _T_2377 = eq(io.in.a.bits.source, source) node _T_2378 = asUInt(reset) node _T_2379 = eq(_T_2378, UInt<1>(0h0)) when _T_2379 : node _T_2380 = eq(_T_2377, UInt<1>(0h0)) when _T_2380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2377, UInt<1>(0h1), "") : assert_174 node _T_2381 = eq(io.in.a.bits.address, address) node _T_2382 = asUInt(reset) node _T_2383 = eq(_T_2382, UInt<1>(0h0)) when _T_2383 : node _T_2384 = eq(_T_2381, UInt<1>(0h0)) when _T_2384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2381, UInt<1>(0h1), "") : assert_175 node _T_2385 = and(io.in.a.ready, io.in.a.valid) node _T_2386 = and(_T_2385, a_first) when _T_2386 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2387 = eq(d_first, UInt<1>(0h0)) node _T_2388 = and(io.in.d.valid, _T_2387) when _T_2388 : node _T_2389 = eq(io.in.d.bits.opcode, opcode_1) node _T_2390 = asUInt(reset) node _T_2391 = eq(_T_2390, UInt<1>(0h0)) when _T_2391 : node _T_2392 = eq(_T_2389, UInt<1>(0h0)) when _T_2392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2389, UInt<1>(0h1), "") : assert_176 node _T_2393 = eq(io.in.d.bits.param, param_1) node _T_2394 = asUInt(reset) node _T_2395 = eq(_T_2394, UInt<1>(0h0)) when _T_2395 : node _T_2396 = eq(_T_2393, UInt<1>(0h0)) when _T_2396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2393, UInt<1>(0h1), "") : assert_177 node _T_2397 = eq(io.in.d.bits.size, size_1) node _T_2398 = asUInt(reset) node _T_2399 = eq(_T_2398, UInt<1>(0h0)) when _T_2399 : node _T_2400 = eq(_T_2397, UInt<1>(0h0)) when _T_2400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2397, UInt<1>(0h1), "") : assert_178 node _T_2401 = eq(io.in.d.bits.source, source_1) node _T_2402 = asUInt(reset) node _T_2403 = eq(_T_2402, UInt<1>(0h0)) when _T_2403 : node _T_2404 = eq(_T_2401, UInt<1>(0h0)) when _T_2404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2401, UInt<1>(0h1), "") : assert_179 node _T_2405 = eq(io.in.d.bits.sink, sink) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_180 node _T_2409 = eq(io.in.d.bits.denied, denied) node _T_2410 = asUInt(reset) node _T_2411 = eq(_T_2410, UInt<1>(0h0)) when _T_2411 : node _T_2412 = eq(_T_2409, UInt<1>(0h0)) when _T_2412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2409, UInt<1>(0h1), "") : assert_181 node _T_2413 = and(io.in.d.ready, io.in.d.valid) node _T_2414 = and(_T_2413, d_first) when _T_2414 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2415 = eq(b_first, UInt<1>(0h0)) node _T_2416 = and(io.in.b.valid, _T_2415) when _T_2416 : node _T_2417 = eq(io.in.b.bits.opcode, opcode_2) node _T_2418 = asUInt(reset) node _T_2419 = eq(_T_2418, UInt<1>(0h0)) when _T_2419 : node _T_2420 = eq(_T_2417, UInt<1>(0h0)) when _T_2420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2417, UInt<1>(0h1), "") : assert_182 node _T_2421 = eq(io.in.b.bits.param, param_2) node _T_2422 = asUInt(reset) node _T_2423 = eq(_T_2422, UInt<1>(0h0)) when _T_2423 : node _T_2424 = eq(_T_2421, UInt<1>(0h0)) when _T_2424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2421, UInt<1>(0h1), "") : assert_183 node _T_2425 = eq(io.in.b.bits.size, size_2) node _T_2426 = asUInt(reset) node _T_2427 = eq(_T_2426, UInt<1>(0h0)) when _T_2427 : node _T_2428 = eq(_T_2425, UInt<1>(0h0)) when _T_2428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2425, UInt<1>(0h1), "") : assert_184 node _T_2429 = eq(io.in.b.bits.source, source_2) node _T_2430 = asUInt(reset) node _T_2431 = eq(_T_2430, UInt<1>(0h0)) when _T_2431 : node _T_2432 = eq(_T_2429, UInt<1>(0h0)) when _T_2432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2429, UInt<1>(0h1), "") : assert_185 node _T_2433 = eq(io.in.b.bits.address, address_1) node _T_2434 = asUInt(reset) node _T_2435 = eq(_T_2434, UInt<1>(0h0)) when _T_2435 : node _T_2436 = eq(_T_2433, UInt<1>(0h0)) when _T_2436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2433, UInt<1>(0h1), "") : assert_186 node _T_2437 = and(io.in.b.ready, io.in.b.valid) node _T_2438 = and(_T_2437, b_first) when _T_2438 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2439 = eq(c_first, UInt<1>(0h0)) node _T_2440 = and(io.in.c.valid, _T_2439) when _T_2440 : node _T_2441 = eq(io.in.c.bits.opcode, opcode_3) node _T_2442 = asUInt(reset) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) when _T_2443 : node _T_2444 = eq(_T_2441, UInt<1>(0h0)) when _T_2444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2441, UInt<1>(0h1), "") : assert_187 node _T_2445 = eq(io.in.c.bits.param, param_3) node _T_2446 = asUInt(reset) node _T_2447 = eq(_T_2446, UInt<1>(0h0)) when _T_2447 : node _T_2448 = eq(_T_2445, UInt<1>(0h0)) when _T_2448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2445, UInt<1>(0h1), "") : assert_188 node _T_2449 = eq(io.in.c.bits.size, size_3) node _T_2450 = asUInt(reset) node _T_2451 = eq(_T_2450, UInt<1>(0h0)) when _T_2451 : node _T_2452 = eq(_T_2449, UInt<1>(0h0)) when _T_2452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2449, UInt<1>(0h1), "") : assert_189 node _T_2453 = eq(io.in.c.bits.source, source_3) node _T_2454 = asUInt(reset) node _T_2455 = eq(_T_2454, UInt<1>(0h0)) when _T_2455 : node _T_2456 = eq(_T_2453, UInt<1>(0h0)) when _T_2456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2453, UInt<1>(0h1), "") : assert_190 node _T_2457 = eq(io.in.c.bits.address, address_2) node _T_2458 = asUInt(reset) node _T_2459 = eq(_T_2458, UInt<1>(0h0)) when _T_2459 : node _T_2460 = eq(_T_2457, UInt<1>(0h0)) when _T_2460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2457, UInt<1>(0h1), "") : assert_191 node _T_2461 = and(io.in.c.ready, io.in.c.valid) node _T_2462 = and(_T_2461, c_first) when _T_2462 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<5>, clock, reset, UInt<5>(0h0) regreset inflight_opcodes : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<5> connect a_set, UInt<5>(0h0) wire a_set_wo_ready : UInt<5> connect a_set_wo_ready, UInt<5>(0h0) wire a_opcodes_set : UInt<20> connect a_opcodes_set, UInt<20>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2463 = and(io.in.a.valid, a_first_1) node _T_2464 = and(_T_2463, UInt<1>(0h1)) when _T_2464 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2465 = and(io.in.a.ready, io.in.a.valid) node _T_2466 = and(_T_2465, a_first_1) node _T_2467 = and(_T_2466, UInt<1>(0h1)) when _T_2467 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2468 = dshr(inflight, io.in.a.bits.source) node _T_2469 = bits(_T_2468, 0, 0) node _T_2470 = eq(_T_2469, UInt<1>(0h0)) node _T_2471 = asUInt(reset) node _T_2472 = eq(_T_2471, UInt<1>(0h0)) when _T_2472 : node _T_2473 = eq(_T_2470, UInt<1>(0h0)) when _T_2473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2470, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<5> connect d_clr, UInt<5>(0h0) wire d_clr_wo_ready : UInt<5> connect d_clr_wo_ready, UInt<5>(0h0) wire d_opcodes_clr : UInt<20> connect d_opcodes_clr, UInt<20>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2474 = and(io.in.d.valid, d_first_1) node _T_2475 = and(_T_2474, UInt<1>(0h1)) node _T_2476 = eq(d_release_ack, UInt<1>(0h0)) node _T_2477 = and(_T_2475, _T_2476) when _T_2477 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2478 = and(io.in.d.ready, io.in.d.valid) node _T_2479 = and(_T_2478, d_first_1) node _T_2480 = and(_T_2479, UInt<1>(0h1)) node _T_2481 = eq(d_release_ack, UInt<1>(0h0)) node _T_2482 = and(_T_2480, _T_2481) when _T_2482 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2483 = and(io.in.d.valid, d_first_1) node _T_2484 = and(_T_2483, UInt<1>(0h1)) node _T_2485 = eq(d_release_ack, UInt<1>(0h0)) node _T_2486 = and(_T_2484, _T_2485) when _T_2486 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2487 = dshr(inflight, io.in.d.bits.source) node _T_2488 = bits(_T_2487, 0, 0) node _T_2489 = or(_T_2488, same_cycle_resp) node _T_2490 = asUInt(reset) node _T_2491 = eq(_T_2490, UInt<1>(0h0)) when _T_2491 : node _T_2492 = eq(_T_2489, UInt<1>(0h0)) when _T_2492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2489, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2493 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2494 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2495 = or(_T_2493, _T_2494) node _T_2496 = asUInt(reset) node _T_2497 = eq(_T_2496, UInt<1>(0h0)) when _T_2497 : node _T_2498 = eq(_T_2495, UInt<1>(0h0)) when _T_2498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2495, UInt<1>(0h1), "") : assert_194 node _T_2499 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2500 = asUInt(reset) node _T_2501 = eq(_T_2500, UInt<1>(0h0)) when _T_2501 : node _T_2502 = eq(_T_2499, UInt<1>(0h0)) when _T_2502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2499, UInt<1>(0h1), "") : assert_195 else : node _T_2503 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2504 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2505 = or(_T_2503, _T_2504) node _T_2506 = asUInt(reset) node _T_2507 = eq(_T_2506, UInt<1>(0h0)) when _T_2507 : node _T_2508 = eq(_T_2505, UInt<1>(0h0)) when _T_2508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2505, UInt<1>(0h1), "") : assert_196 node _T_2509 = eq(io.in.d.bits.size, a_size_lookup) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_197 node _T_2513 = and(io.in.d.valid, d_first_1) node _T_2514 = and(_T_2513, a_first_1) node _T_2515 = and(_T_2514, io.in.a.valid) node _T_2516 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2517 = and(_T_2515, _T_2516) node _T_2518 = eq(d_release_ack, UInt<1>(0h0)) node _T_2519 = and(_T_2517, _T_2518) when _T_2519 : node _T_2520 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2521 = or(_T_2520, io.in.a.ready) node _T_2522 = asUInt(reset) node _T_2523 = eq(_T_2522, UInt<1>(0h0)) when _T_2523 : node _T_2524 = eq(_T_2521, UInt<1>(0h0)) when _T_2524 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2521, UInt<1>(0h1), "") : assert_198 node _T_2525 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2526 = orr(a_set_wo_ready) node _T_2527 = eq(_T_2526, UInt<1>(0h0)) node _T_2528 = or(_T_2525, _T_2527) node _T_2529 = asUInt(reset) node _T_2530 = eq(_T_2529, UInt<1>(0h0)) when _T_2530 : node _T_2531 = eq(_T_2528, UInt<1>(0h0)) when _T_2531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2528, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_88 node _T_2532 = orr(inflight) node _T_2533 = eq(_T_2532, UInt<1>(0h0)) node _T_2534 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2535 = or(_T_2533, _T_2534) node _T_2536 = lt(watchdog, plusarg_reader.out) node _T_2537 = or(_T_2535, _T_2536) node _T_2538 = asUInt(reset) node _T_2539 = eq(_T_2538, UInt<1>(0h0)) when _T_2539 : node _T_2540 = eq(_T_2537, UInt<1>(0h0)) when _T_2540 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2537, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2541 = and(io.in.a.ready, io.in.a.valid) node _T_2542 = and(io.in.d.ready, io.in.d.valid) node _T_2543 = or(_T_2541, _T_2542) when _T_2543 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<5>, clock, reset, UInt<5>(0h0) regreset inflight_opcodes_1 : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<5> connect c_set, UInt<5>(0h0) wire c_set_wo_ready : UInt<5> connect c_set_wo_ready, UInt<5>(0h0) wire c_opcodes_set : UInt<20> connect c_opcodes_set, UInt<20>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2544 = and(io.in.c.valid, c_first_1) node _T_2545 = bits(io.in.c.bits.opcode, 2, 2) node _T_2546 = bits(io.in.c.bits.opcode, 1, 1) node _T_2547 = and(_T_2545, _T_2546) node _T_2548 = and(_T_2544, _T_2547) when _T_2548 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2549 = and(io.in.c.ready, io.in.c.valid) node _T_2550 = and(_T_2549, c_first_1) node _T_2551 = bits(io.in.c.bits.opcode, 2, 2) node _T_2552 = bits(io.in.c.bits.opcode, 1, 1) node _T_2553 = and(_T_2551, _T_2552) node _T_2554 = and(_T_2550, _T_2553) when _T_2554 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2555 = dshr(inflight_1, io.in.c.bits.source) node _T_2556 = bits(_T_2555, 0, 0) node _T_2557 = eq(_T_2556, UInt<1>(0h0)) node _T_2558 = asUInt(reset) node _T_2559 = eq(_T_2558, UInt<1>(0h0)) when _T_2559 : node _T_2560 = eq(_T_2557, UInt<1>(0h0)) when _T_2560 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2557, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<5> connect d_clr_1, UInt<5>(0h0) wire d_clr_wo_ready_1 : UInt<5> connect d_clr_wo_ready_1, UInt<5>(0h0) wire d_opcodes_clr_1 : UInt<20> connect d_opcodes_clr_1, UInt<20>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2561 = and(io.in.d.valid, d_first_2) node _T_2562 = and(_T_2561, UInt<1>(0h1)) node _T_2563 = and(_T_2562, d_release_ack_1) when _T_2563 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2564 = and(io.in.d.ready, io.in.d.valid) node _T_2565 = and(_T_2564, d_first_2) node _T_2566 = and(_T_2565, UInt<1>(0h1)) node _T_2567 = and(_T_2566, d_release_ack_1) when _T_2567 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2568 = and(io.in.d.valid, d_first_2) node _T_2569 = and(_T_2568, UInt<1>(0h1)) node _T_2570 = and(_T_2569, d_release_ack_1) when _T_2570 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2571 = dshr(inflight_1, io.in.d.bits.source) node _T_2572 = bits(_T_2571, 0, 0) node _T_2573 = or(_T_2572, same_cycle_resp_1) node _T_2574 = asUInt(reset) node _T_2575 = eq(_T_2574, UInt<1>(0h0)) when _T_2575 : node _T_2576 = eq(_T_2573, UInt<1>(0h0)) when _T_2576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2573, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2577 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2578 = asUInt(reset) node _T_2579 = eq(_T_2578, UInt<1>(0h0)) when _T_2579 : node _T_2580 = eq(_T_2577, UInt<1>(0h0)) when _T_2580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2577, UInt<1>(0h1), "") : assert_203 else : node _T_2581 = eq(io.in.d.bits.size, c_size_lookup) node _T_2582 = asUInt(reset) node _T_2583 = eq(_T_2582, UInt<1>(0h0)) when _T_2583 : node _T_2584 = eq(_T_2581, UInt<1>(0h0)) when _T_2584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2581, UInt<1>(0h1), "") : assert_204 node _T_2585 = and(io.in.d.valid, d_first_2) node _T_2586 = and(_T_2585, c_first_1) node _T_2587 = and(_T_2586, io.in.c.valid) node _T_2588 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2589 = and(_T_2587, _T_2588) node _T_2590 = and(_T_2589, d_release_ack_1) node _T_2591 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2592 = and(_T_2590, _T_2591) when _T_2592 : node _T_2593 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2594 = or(_T_2593, io.in.c.ready) node _T_2595 = asUInt(reset) node _T_2596 = eq(_T_2595, UInt<1>(0h0)) when _T_2596 : node _T_2597 = eq(_T_2594, UInt<1>(0h0)) when _T_2597 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2594, UInt<1>(0h1), "") : assert_205 node _T_2598 = orr(c_set_wo_ready) when _T_2598 : node _T_2599 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2600 = asUInt(reset) node _T_2601 = eq(_T_2600, UInt<1>(0h0)) when _T_2601 : node _T_2602 = eq(_T_2599, UInt<1>(0h0)) when _T_2602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2599, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_89 node _T_2603 = orr(inflight_1) node _T_2604 = eq(_T_2603, UInt<1>(0h0)) node _T_2605 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2606 = or(_T_2604, _T_2605) node _T_2607 = lt(watchdog_1, plusarg_reader_1.out) node _T_2608 = or(_T_2606, _T_2607) node _T_2609 = asUInt(reset) node _T_2610 = eq(_T_2609, UInt<1>(0h0)) when _T_2610 : node _T_2611 = eq(_T_2608, UInt<1>(0h0)) when _T_2611 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2608, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2612 = and(io.in.c.ready, io.in.c.valid) node _T_2613 = and(io.in.d.ready, io.in.d.valid) node _T_2614 = or(_T_2612, _T_2613) when _T_2614 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2615 = and(io.in.d.ready, io.in.d.valid) node _T_2616 = and(_T_2615, d_first_3) node _T_2617 = bits(io.in.d.bits.opcode, 2, 2) node _T_2618 = bits(io.in.d.bits.opcode, 1, 1) node _T_2619 = eq(_T_2618, UInt<1>(0h0)) node _T_2620 = and(_T_2617, _T_2619) node _T_2621 = and(_T_2616, _T_2620) when _T_2621 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2622 = dshr(inflight_2, io.in.d.bits.sink) node _T_2623 = bits(_T_2622, 0, 0) node _T_2624 = eq(_T_2623, UInt<1>(0h0)) node _T_2625 = asUInt(reset) node _T_2626 = eq(_T_2625, UInt<1>(0h0)) when _T_2626 : node _T_2627 = eq(_T_2624, UInt<1>(0h0)) when _T_2627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2624, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2628 = and(io.in.e.ready, io.in.e.valid) node _T_2629 = and(_T_2628, UInt<1>(0h1)) node _T_2630 = and(_T_2629, UInt<1>(0h1)) when _T_2630 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2631 = or(d_set, inflight_2) node _T_2632 = dshr(_T_2631, io.in.e.bits.sink) node _T_2633 = bits(_T_2632, 0, 0) node _T_2634 = asUInt(reset) node _T_2635 = eq(_T_2634, UInt<1>(0h0)) when _T_2635 : node _T_2636 = eq(_T_2633, UInt<1>(0h0)) when _T_2636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2633, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8	module TLMonitor_44( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_8 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [2:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [2:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [2:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [2:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[2]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = ~_source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 3'h3; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = io_in_a_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_7; // @[Parameters.scala:1138:31] wire _source_ok_T_8 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_8 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_9 = io_in_d_bits_source_0[2]; // @[Monitor.scala:36:7] wire _source_ok_T_10 = ~_source_ok_T_9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_13 = source_ok_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_14 = _source_ok_T_12 & _source_ok_T_13; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_14; // @[Parameters.scala:1138:31] wire _source_ok_T_15 = io_in_d_bits_source_0 == 3'h3; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_15; // @[Parameters.scala:1138:31] wire _source_ok_T_16 = io_in_d_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_16; // @[Parameters.scala:1138:31] wire _source_ok_T_17 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_17 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T = io_in_b_bits_source_0[2]; // @[Monitor.scala:36:7] wire _legal_source_T_6 = io_in_b_bits_source_0 == 3'h3; // @[Monitor.scala:36:7] wire _legal_source_T_7 = io_in_b_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire [1:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_1 = ~_legal_source_T; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_3 = _legal_source_T_1; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_4 = legal_source_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_3 & _legal_source_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_7; // @[Parameters.scala:1138:31] wire [1:0] _legal_source_T_9 = {2{_legal_source_WIRE_1}}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_11 = _legal_source_T_9; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_10 = {_legal_source_WIRE_2, 2'h0}; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_12 = {1'h0, _legal_source_T_11} \| _legal_source_T_10; // @[Mux.scala:30:73] wire [2:0] _legal_source_WIRE_1_0 = _legal_source_T_12; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = io_in_c_bits_source_0[2]; // @[Monitor.scala:36:7] wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_22 = source_ok_uncommonBits_2 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = io_in_c_bits_source_0 == 3'h3; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_c_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_26 \| _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire _T_2541 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2541; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2541; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [2:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2615 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2615; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2615; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2615; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2615; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [2:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2612 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2612; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2612; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [2:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [4:0] inflight; // @[Monitor.scala:614:27] reg [19:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [4:0] a_set; // @[Monitor.scala:626:34] wire [4:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [19:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [5:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [5:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [5:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [5:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [5:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [19:0] _a_opcode_lookup_T_6 = {16'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [19:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [5:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [5:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [5:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [5:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [5:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {32'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [7:0] _GEN_21 = 8'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [7:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2467 = _T_2541 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2467 ? _a_set_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2467 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2467 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [5:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [66:0] _a_opcodes_set_T_1 = {63'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2467 ? _a_opcodes_set_T_1[19:0] : 20'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [5:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [67:0] _a_sizes_set_T_1 = {63'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2467 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [4:0] d_clr; // @[Monitor.scala:664:34] wire [4:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [19:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2513 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [7:0] _GEN_23 = 8'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2513 & ~d_release_ack ? _d_clr_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2482 = _T_2615 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2482 ? _d_clr_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [78:0] _d_opcodes_clr_T_5 = 79'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2482 ? _d_opcodes_clr_T_5[19:0] : 20'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [78:0] _d_sizes_clr_T_5 = 79'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2482 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [4:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [19:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [4:0] inflight_1; // @[Monitor.scala:726:35] reg [19:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [4:0] c_set; // @[Monitor.scala:738:34] wire [4:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [19:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [19:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [19:0] _c_opcode_lookup_T_6 = {16'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [19:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[19:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {32'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [7:0] _GEN_24 = 8'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [7:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2554 = _T_2612 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2554 ? _c_set_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2554 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2554 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [5:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [66:0] _c_opcodes_set_T_1 = {63'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2554 ? _c_opcodes_set_T_1[19:0] : 20'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [5:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [67:0] _c_sizes_set_T_1 = {63'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2554 ? _c_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [4:0] d_clr_1; // @[Monitor.scala:774:34] wire [4:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [19:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2585 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2585 & d_release_ack_1 ? _d_clr_wo_ready_T_1[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2567 = _T_2615 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2567 ? _d_clr_T_1[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [78:0] _d_opcodes_clr_T_11 = 79'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2567 ? _d_opcodes_clr_T_11[19:0] : 20'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [78:0] _d_sizes_clr_T_11 = 79'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2567 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [4:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [4:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [19:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [19:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2621 = _T_2615 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_25 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2621 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2630 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_26 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2630 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_69 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_69( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_55 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_20 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_21 = and(_T_19, _T_20) node _T_22 = or(UInt<1>(0h0), _T_21) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = and(_T_22, _T_27) node _T_29 = or(UInt<1>(0h0), _T_28) node _T_30 = and(_T_18, _T_29) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_30, UInt<1>(0h1), "") : assert_2 node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = or(UInt<1>(0h0), _T_36) node _T_38 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = and(_T_37, _T_42) node _T_44 = or(UInt<1>(0h0), _T_43) node _T_45 = and(UInt<1>(0h0), _T_44) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_45, UInt<1>(0h1), "") : assert_3 node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_52 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_52, UInt<1>(0h1), "") : assert_5 node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(is_aligned, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_59 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_60 = asUInt(reset) node _T_61 = eq(_T_60, UInt<1>(0h0)) when _T_61 : node _T_62 = eq(_T_59, UInt<1>(0h0)) when _T_62 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_59, UInt<1>(0h1), "") : assert_7 node _T_63 = not(io.in.a.bits.mask) node _T_64 = eq(_T_63, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_64, UInt<1>(0h1), "") : assert_8 node _T_68 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_68, UInt<1>(0h1), "") : assert_9 node _T_72 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_72 : node _T_73 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_74 = and(UInt<1>(0h0), _T_73) node _T_75 = or(UInt<1>(0h0), _T_74) node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_77 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_78 = and(_T_76, _T_77) node _T_79 = or(UInt<1>(0h0), _T_78) node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = and(_T_79, _T_84) node _T_86 = or(UInt<1>(0h0), _T_85) node _T_87 = and(_T_75, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_87, UInt<1>(0h1), "") : assert_10 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_102, UInt<1>(0h1), "") : assert_11 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_109, UInt<1>(0h1), "") : assert_13 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_116, UInt<1>(0h1), "") : assert_15 node _T_120 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_120, UInt<1>(0h1), "") : assert_16 node _T_124 = not(io.in.a.bits.mask) node _T_125 = eq(_T_124, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_125, UInt<1>(0h1), "") : assert_17 node _T_129 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_130 = asUInt(reset) node _T_131 = eq(_T_130, UInt<1>(0h0)) when _T_131 : node _T_132 = eq(_T_129, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_129, UInt<1>(0h1), "") : assert_18 node _T_133 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_133 : node _T_134 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_135 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_136 = and(_T_134, _T_135) node _T_137 = or(UInt<1>(0h0), _T_136) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_137, UInt<1>(0h1), "") : assert_19 node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_142 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_143 = and(_T_141, _T_142) node _T_144 = or(UInt<1>(0h0), _T_143) node _T_145 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = and(_T_144, _T_149) node _T_151 = or(UInt<1>(0h0), _T_150) node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(_T_151, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_151, UInt<1>(0h1), "") : assert_20 node _T_155 = asUInt(reset) node _T_156 = eq(_T_155, UInt<1>(0h0)) when _T_156 : node _T_157 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_158 = asUInt(reset) node _T_159 = eq(_T_158, UInt<1>(0h0)) when _T_159 : node _T_160 = eq(is_aligned, UInt<1>(0h0)) when _T_160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_161 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_162 = asUInt(reset) node _T_163 = eq(_T_162, UInt<1>(0h0)) when _T_163 : node _T_164 = eq(_T_161, UInt<1>(0h0)) when _T_164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_161, UInt<1>(0h1), "") : assert_23 node _T_165 = eq(io.in.a.bits.mask, mask) node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(_T_165, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_165, UInt<1>(0h1), "") : assert_24 node _T_169 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_169, UInt<1>(0h1), "") : assert_25 node _T_173 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_175 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_176 = and(_T_174, _T_175) node _T_177 = or(UInt<1>(0h0), _T_176) node _T_178 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_179 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_180 = and(_T_178, _T_179) node _T_181 = or(UInt<1>(0h0), _T_180) node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = and(_T_181, _T_186) node _T_188 = or(UInt<1>(0h0), _T_187) node _T_189 = and(_T_177, _T_188) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_189, UInt<1>(0h1), "") : assert_26 node _T_193 = asUInt(reset) node _T_194 = eq(_T_193, UInt<1>(0h0)) when _T_194 : node _T_195 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_196 = asUInt(reset) node _T_197 = eq(_T_196, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(is_aligned, UInt<1>(0h0)) when _T_198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_199 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_200 = asUInt(reset) node _T_201 = eq(_T_200, UInt<1>(0h0)) when _T_201 : node _T_202 = eq(_T_199, UInt<1>(0h0)) when _T_202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_199, UInt<1>(0h1), "") : assert_29 node _T_203 = eq(io.in.a.bits.mask, mask) node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : node _T_206 = eq(_T_203, UInt<1>(0h0)) when _T_206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_203, UInt<1>(0h1), "") : assert_30 node _T_207 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_207 : node _T_208 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_209 = and(UInt<1>(0h0), _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_212 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_213 = and(_T_211, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = and(_T_214, _T_219) node _T_221 = or(UInt<1>(0h0), _T_220) node _T_222 = and(_T_210, _T_221) node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_T_222, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_222, UInt<1>(0h1), "") : assert_31 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(is_aligned, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_232 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_232, UInt<1>(0h1), "") : assert_34 node _T_236 = not(mask) node _T_237 = and(io.in.a.bits.mask, _T_236) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(_T_238, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_238, UInt<1>(0h1), "") : assert_35 node _T_242 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_242 : node _T_243 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_244 = and(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_247 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_248 = cvt(_T_247) node _T_249 = and(_T_248, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_250 = asSInt(_T_249) node _T_251 = eq(_T_250, asSInt(UInt<1>(0h0))) node _T_252 = and(_T_246, _T_251) node _T_253 = or(UInt<1>(0h0), _T_252) node _T_254 = and(_T_245, _T_253) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_254, UInt<1>(0h1), "") : assert_36 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(is_aligned, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_264 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(_T_264, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_264, UInt<1>(0h1), "") : assert_39 node _T_268 = eq(io.in.a.bits.mask, mask) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_268, UInt<1>(0h1), "") : assert_40 node _T_272 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_272 : node _T_273 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_274 = and(UInt<1>(0h0), _T_273) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_277 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_278 = cvt(_T_277) node _T_279 = and(_T_278, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_280 = asSInt(_T_279) node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = and(_T_276, _T_281) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = and(_T_275, _T_283) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_284, UInt<1>(0h1), "") : assert_41 node _T_288 = asUInt(reset) node _T_289 = eq(_T_288, UInt<1>(0h0)) when _T_289 : node _T_290 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(is_aligned, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_294 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_294, UInt<1>(0h1), "") : assert_44 node _T_298 = eq(io.in.a.bits.mask, mask) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_298, UInt<1>(0h1), "") : assert_45 node _T_302 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_302 : node _T_303 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_304 = and(UInt<1>(0h0), _T_303) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_307 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_308 = and(_T_306, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_311 = cvt(_T_310) node _T_312 = and(_T_311, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_313 = asSInt(_T_312) node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0))) node _T_315 = and(_T_309, _T_314) node _T_316 = or(UInt<1>(0h0), _T_315) node _T_317 = and(_T_305, _T_316) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_317, UInt<1>(0h1), "") : assert_46 node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : node _T_326 = eq(is_aligned, UInt<1>(0h0)) when _T_326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_327 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_327, UInt<1>(0h1), "") : assert_49 node _T_331 = eq(io.in.a.bits.mask, mask) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_331, UInt<1>(0h1), "") : assert_50 node _T_335 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_T_335, UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_335, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_339 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_339, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h1)) node _T_343 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_343 : node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_347 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_347, UInt<1>(0h1), "") : assert_54 node _T_351 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_351, UInt<1>(0h1), "") : assert_55 node _T_355 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_355, UInt<1>(0h1), "") : assert_56 node _T_359 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_359, UInt<1>(0h1), "") : assert_57 node _T_363 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_363 : node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(sink_ok, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_370 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(_T_370, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_370, UInt<1>(0h1), "") : assert_60 node _T_374 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_374, UInt<1>(0h1), "") : assert_61 node _T_378 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_378, UInt<1>(0h1), "") : assert_62 node _T_382 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_382, UInt<1>(0h1), "") : assert_63 node _T_386 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_387 = or(UInt<1>(0h1), _T_386) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_387, UInt<1>(0h1), "") : assert_64 node _T_391 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_391 : node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(sink_ok, UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_398, UInt<1>(0h1), "") : assert_67 node _T_402 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_402, UInt<1>(0h1), "") : assert_68 node _T_406 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_406, UInt<1>(0h1), "") : assert_69 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = or(_T_410, io.in.d.bits.corrupt) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_411, UInt<1>(0h1), "") : assert_70 node _T_415 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_416 = or(UInt<1>(0h1), _T_415) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_416, UInt<1>(0h1), "") : assert_71 node _T_420 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_420 : node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_424 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_424, UInt<1>(0h1), "") : assert_73 node _T_428 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_428, UInt<1>(0h1), "") : assert_74 node _T_432 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_433 = or(UInt<1>(0h1), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_433, UInt<1>(0h1), "") : assert_75 node _T_437 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_437 : node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_441 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_441, UInt<1>(0h1), "") : assert_77 node _T_445 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_446 = or(_T_445, io.in.d.bits.corrupt) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_446, UInt<1>(0h1), "") : assert_78 node _T_450 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_451 = or(UInt<1>(0h1), _T_450) node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(_T_451, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_451, UInt<1>(0h1), "") : assert_79 node _T_455 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_455 : node _T_456 = asUInt(reset) node _T_457 = eq(_T_456, UInt<1>(0h0)) when _T_457 : node _T_458 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_459 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_459, UInt<1>(0h1), "") : assert_81 node _T_463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_463, UInt<1>(0h1), "") : assert_82 node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_468 = or(UInt<1>(0h1), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_468, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<128>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_472 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_472, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<128>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_476 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_476, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_480 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_480, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_484 = eq(a_first, UInt<1>(0h0)) node _T_485 = and(io.in.a.valid, _T_484) when _T_485 : node _T_486 = eq(io.in.a.bits.opcode, opcode) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_486, UInt<1>(0h1), "") : assert_87 node _T_490 = eq(io.in.a.bits.param, param) node _T_491 = asUInt(reset) node _T_492 = eq(_T_491, UInt<1>(0h0)) when _T_492 : node _T_493 = eq(_T_490, UInt<1>(0h0)) when _T_493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_490, UInt<1>(0h1), "") : assert_88 node _T_494 = eq(io.in.a.bits.size, size) node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(_T_494, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_494, UInt<1>(0h1), "") : assert_89 node _T_498 = eq(io.in.a.bits.source, source) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_498, UInt<1>(0h1), "") : assert_90 node _T_502 = eq(io.in.a.bits.address, address) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_502, UInt<1>(0h1), "") : assert_91 node _T_506 = and(io.in.a.ready, io.in.a.valid) node _T_507 = and(_T_506, a_first) when _T_507 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_508 = eq(d_first, UInt<1>(0h0)) node _T_509 = and(io.in.d.valid, _T_508) when _T_509 : node _T_510 = eq(io.in.d.bits.opcode, opcode_1) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_510, UInt<1>(0h1), "") : assert_92 node _T_514 = eq(io.in.d.bits.param, param_1) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_514, UInt<1>(0h1), "") : assert_93 node _T_518 = eq(io.in.d.bits.size, size_1) node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(_T_518, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_518, UInt<1>(0h1), "") : assert_94 node _T_522 = eq(io.in.d.bits.source, source_1) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_522, UInt<1>(0h1), "") : assert_95 node _T_526 = eq(io.in.d.bits.sink, sink) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_526, UInt<1>(0h1), "") : assert_96 node _T_530 = eq(io.in.d.bits.denied, denied) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_530, UInt<1>(0h1), "") : assert_97 node _T_534 = and(io.in.d.ready, io.in.d.valid) node _T_535 = and(_T_534, d_first) when _T_535 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_536 = and(io.in.a.valid, a_first_1) node _T_537 = and(_T_536, UInt<1>(0h1)) when _T_537 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_538 = and(io.in.a.ready, io.in.a.valid) node _T_539 = and(_T_538, a_first_1) node _T_540 = and(_T_539, UInt<1>(0h1)) when _T_540 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_541 = dshr(inflight, io.in.a.bits.source) node _T_542 = bits(_T_541, 0, 0) node _T_543 = eq(_T_542, UInt<1>(0h0)) node _T_544 = asUInt(reset) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(_T_543, UInt<1>(0h0)) when _T_546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_543, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_547 = and(io.in.d.valid, d_first_1) node _T_548 = and(_T_547, UInt<1>(0h1)) node _T_549 = eq(d_release_ack, UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) when _T_550 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_551 = and(io.in.d.ready, io.in.d.valid) node _T_552 = and(_T_551, d_first_1) node _T_553 = and(_T_552, UInt<1>(0h1)) node _T_554 = eq(d_release_ack, UInt<1>(0h0)) node _T_555 = and(_T_553, _T_554) when _T_555 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_556 = and(io.in.d.valid, d_first_1) node _T_557 = and(_T_556, UInt<1>(0h1)) node _T_558 = eq(d_release_ack, UInt<1>(0h0)) node _T_559 = and(_T_557, _T_558) when _T_559 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_560 = dshr(inflight, io.in.d.bits.source) node _T_561 = bits(_T_560, 0, 0) node _T_562 = or(_T_561, same_cycle_resp) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_562, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_566 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_567 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_568 = or(_T_566, _T_567) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_568, UInt<1>(0h1), "") : assert_100 node _T_572 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_572, UInt<1>(0h1), "") : assert_101 else : node _T_576 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_577 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_578 = or(_T_576, _T_577) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_578, UInt<1>(0h1), "") : assert_102 node _T_582 = eq(io.in.d.bits.size, a_size_lookup) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_582, UInt<1>(0h1), "") : assert_103 node _T_586 = and(io.in.d.valid, d_first_1) node _T_587 = and(_T_586, a_first_1) node _T_588 = and(_T_587, io.in.a.valid) node _T_589 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_590 = and(_T_588, _T_589) node _T_591 = eq(d_release_ack, UInt<1>(0h0)) node _T_592 = and(_T_590, _T_591) when _T_592 : node _T_593 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_594 = or(_T_593, io.in.a.ready) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_594, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_111 node _T_598 = orr(inflight) node _T_599 = eq(_T_598, UInt<1>(0h0)) node _T_600 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_601 = or(_T_599, _T_600) node _T_602 = lt(watchdog, plusarg_reader.out) node _T_603 = or(_T_601, _T_602) node _T_604 = asUInt(reset) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(_T_603, UInt<1>(0h0)) when _T_606 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_603, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_607 = and(io.in.a.ready, io.in.a.valid) node _T_608 = and(io.in.d.ready, io.in.d.valid) node _T_609 = or(_T_607, _T_608) when _T_609 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<128>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<128>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<128>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_610 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<128>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_611 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_612 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_613 = and(_T_611, _T_612) node _T_614 = and(_T_610, _T_613) when _T_614 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<128>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_615 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_616 = and(_T_615, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<128>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_617 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_618 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_619 = and(_T_617, _T_618) node _T_620 = and(_T_616, _T_619) when _T_620 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<128>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<128>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_621 = dshr(inflight_1, _WIRE_15.bits.source) node _T_622 = bits(_T_621, 0, 0) node _T_623 = eq(_T_622, UInt<1>(0h0)) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_623, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_627 = and(io.in.d.valid, d_first_2) node _T_628 = and(_T_627, UInt<1>(0h1)) node _T_629 = and(_T_628, d_release_ack_1) when _T_629 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_630 = and(io.in.d.ready, io.in.d.valid) node _T_631 = and(_T_630, d_first_2) node _T_632 = and(_T_631, UInt<1>(0h1)) node _T_633 = and(_T_632, d_release_ack_1) when _T_633 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_634 = and(io.in.d.valid, d_first_2) node _T_635 = and(_T_634, UInt<1>(0h1)) node _T_636 = and(_T_635, d_release_ack_1) when _T_636 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_637 = dshr(inflight_1, io.in.d.bits.source) node _T_638 = bits(_T_637, 0, 0) node _T_639 = or(_T_638, same_cycle_resp_1) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_639, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<128>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_643 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(_T_643, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_643, UInt<1>(0h1), "") : assert_108 else : node _T_647 = eq(io.in.d.bits.size, c_size_lookup) node _T_648 = asUInt(reset) node _T_649 = eq(_T_648, UInt<1>(0h0)) when _T_649 : node _T_650 = eq(_T_647, UInt<1>(0h0)) when _T_650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_647, UInt<1>(0h1), "") : assert_109 node _T_651 = and(io.in.d.valid, d_first_2) node _T_652 = and(_T_651, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<128>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_653 = and(_T_652, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<128>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_654 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_655 = and(_T_653, _T_654) node _T_656 = and(_T_655, d_release_ack_1) node _T_657 = eq(c_probe_ack, UInt<1>(0h0)) node _T_658 = and(_T_656, _T_657) when _T_658 : node _T_659 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<128>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_660 = or(_T_659, _WIRE_23.ready) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_660, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_112 node _T_664 = orr(inflight_1) node _T_665 = eq(_T_664, UInt<1>(0h0)) node _T_666 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_667 = or(_T_665, _T_666) node _T_668 = lt(watchdog_1, plusarg_reader_1.out) node _T_669 = or(_T_667, _T_668) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_669, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_673 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_674 = and(io.in.d.ready, io.in.d.valid) node _T_675 = or(_T_673, _T_674) when _T_675 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_55( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [127:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_50 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<10>(0h200))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = and(_T_19, _T_24) node _T_26 = or(UInt<1>(0h0), _T_25) node _T_27 = and(_T_18, _T_26) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_27, UInt<1>(0h1), "") : assert_2 node _T_31 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_32 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_33 = and(_T_31, _T_32) node _T_34 = or(UInt<1>(0h0), _T_33) node _T_35 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<10>(0h200))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = and(_T_34, _T_39) node _T_41 = or(UInt<1>(0h0), _T_40) node _T_42 = and(UInt<1>(0h0), _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_42, UInt<1>(0h1), "") : assert_3 node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_49 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_50 = asUInt(reset) node _T_51 = eq(_T_50, UInt<1>(0h0)) when _T_51 : node _T_52 = eq(_T_49, UInt<1>(0h0)) when _T_52 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_49, UInt<1>(0h1), "") : assert_5 node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(is_aligned, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_56 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_56, UInt<1>(0h1), "") : assert_7 node _T_60 = not(io.in.a.bits.mask) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : node _T_64 = eq(_T_61, UInt<1>(0h0)) when _T_64 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_61, UInt<1>(0h1), "") : assert_8 node _T_65 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_69 : node _T_70 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_71 = and(UInt<1>(0h0), _T_70) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<10>(0h200))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = and(_T_73, _T_78) node _T_80 = or(UInt<1>(0h0), _T_79) node _T_81 = and(_T_72, _T_80) node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(_T_81, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_81, UInt<1>(0h1), "") : assert_10 node _T_85 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_86 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_87 = and(_T_85, _T_86) node _T_88 = or(UInt<1>(0h0), _T_87) node _T_89 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<10>(0h200))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = and(_T_88, _T_93) node _T_95 = or(UInt<1>(0h0), _T_94) node _T_96 = and(UInt<1>(0h0), _T_95) node _T_97 = asUInt(reset) node _T_98 = eq(_T_97, UInt<1>(0h0)) when _T_98 : node _T_99 = eq(_T_96, UInt<1>(0h0)) when _T_99 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_96, UInt<1>(0h1), "") : assert_11 node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_103 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_103, UInt<1>(0h1), "") : assert_13 node _T_107 = asUInt(reset) node _T_108 = eq(_T_107, UInt<1>(0h0)) when _T_108 : node _T_109 = eq(is_aligned, UInt<1>(0h0)) when _T_109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_110 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : node _T_113 = eq(_T_110, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_110, UInt<1>(0h1), "") : assert_15 node _T_114 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_114, UInt<1>(0h1), "") : assert_16 node _T_118 = not(io.in.a.bits.mask) node _T_119 = eq(_T_118, UInt<1>(0h0)) node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(_T_119, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_119, UInt<1>(0h1), "") : assert_17 node _T_123 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : node _T_126 = eq(_T_123, UInt<1>(0h0)) when _T_126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_123, UInt<1>(0h1), "") : assert_18 node _T_127 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_127 : node _T_128 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_129 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_130 = and(_T_128, _T_129) node _T_131 = or(UInt<1>(0h0), _T_130) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_131, UInt<1>(0h1), "") : assert_19 node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_136 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_137 = and(_T_135, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<10>(0h200))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = and(_T_138, _T_143) node _T_145 = or(UInt<1>(0h0), _T_144) node _T_146 = asUInt(reset) node _T_147 = eq(_T_146, UInt<1>(0h0)) when _T_147 : node _T_148 = eq(_T_145, UInt<1>(0h0)) when _T_148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_145, UInt<1>(0h1), "") : assert_20 node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(is_aligned, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_155 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_155, UInt<1>(0h1), "") : assert_23 node _T_159 = eq(io.in.a.bits.mask, mask) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_159, UInt<1>(0h1), "") : assert_24 node _T_163 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_163, UInt<1>(0h1), "") : assert_25 node _T_167 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_169 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_170 = and(_T_168, _T_169) node _T_171 = or(UInt<1>(0h0), _T_170) node _T_172 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_173 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_174 = and(_T_172, _T_173) node _T_175 = or(UInt<1>(0h0), _T_174) node _T_176 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<10>(0h200))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = and(_T_175, _T_180) node _T_182 = or(UInt<1>(0h0), _T_181) node _T_183 = and(_T_171, _T_182) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_183, UInt<1>(0h1), "") : assert_26 node _T_187 = asUInt(reset) node _T_188 = eq(_T_187, UInt<1>(0h0)) when _T_188 : node _T_189 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(is_aligned, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_193 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_193, UInt<1>(0h1), "") : assert_29 node _T_197 = eq(io.in.a.bits.mask, mask) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_197, UInt<1>(0h1), "") : assert_30 node _T_201 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_201 : node _T_202 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_203 = and(UInt<1>(0h0), _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_206 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_207 = and(_T_205, _T_206) node _T_208 = or(UInt<1>(0h0), _T_207) node _T_209 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_210 = cvt(_T_209) node _T_211 = and(_T_210, asSInt(UInt<10>(0h200))) node _T_212 = asSInt(_T_211) node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0))) node _T_214 = and(_T_208, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(_T_204, _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_216, UInt<1>(0h1), "") : assert_31 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(is_aligned, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_226 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(_T_226, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_226, UInt<1>(0h1), "") : assert_34 node _T_230 = not(mask) node _T_231 = and(io.in.a.bits.mask, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_232, UInt<1>(0h1), "") : assert_35 node _T_236 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_236 : node _T_237 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_238 = and(UInt<1>(0h0), _T_237) node _T_239 = or(UInt<1>(0h0), _T_238) node _T_240 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_241 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<10>(0h200))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = and(_T_240, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = and(_T_239, _T_247) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_248, UInt<1>(0h1), "") : assert_36 node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(is_aligned, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_258 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_258, UInt<1>(0h1), "") : assert_39 node _T_262 = eq(io.in.a.bits.mask, mask) node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_T_262, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_262, UInt<1>(0h1), "") : assert_40 node _T_266 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_266 : node _T_267 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_268 = and(UInt<1>(0h0), _T_267) node _T_269 = or(UInt<1>(0h0), _T_268) node _T_270 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_271 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<10>(0h200))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = and(_T_270, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = and(_T_269, _T_277) node _T_279 = asUInt(reset) node _T_280 = eq(_T_279, UInt<1>(0h0)) when _T_280 : node _T_281 = eq(_T_278, UInt<1>(0h0)) when _T_281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_278, UInt<1>(0h1), "") : assert_41 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : node _T_284 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(is_aligned, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_288 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_288, UInt<1>(0h1), "") : assert_44 node _T_292 = eq(io.in.a.bits.mask, mask) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_292, UInt<1>(0h1), "") : assert_45 node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_296 : node _T_297 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_298 = and(UInt<1>(0h0), _T_297) node _T_299 = or(UInt<1>(0h0), _T_298) node _T_300 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_301 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<10>(0h200))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = and(_T_300, _T_305) node _T_307 = or(UInt<1>(0h0), _T_306) node _T_308 = and(_T_299, _T_307) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_308, UInt<1>(0h1), "") : assert_46 node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_315 = asUInt(reset) node _T_316 = eq(_T_315, UInt<1>(0h0)) when _T_316 : node _T_317 = eq(is_aligned, UInt<1>(0h0)) when _T_317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_318 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_318, UInt<1>(0h1), "") : assert_49 node _T_322 = eq(io.in.a.bits.mask, mask) node _T_323 = asUInt(reset) node _T_324 = eq(_T_323, UInt<1>(0h0)) when _T_324 : node _T_325 = eq(_T_322, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_322, UInt<1>(0h1), "") : assert_50 node _T_326 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_327 = asUInt(reset) node _T_328 = eq(_T_327, UInt<1>(0h0)) when _T_328 : node _T_329 = eq(_T_326, UInt<1>(0h0)) when _T_329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_326, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_330 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_331 = asUInt(reset) node _T_332 = eq(_T_331, UInt<1>(0h0)) when _T_332 : node _T_333 = eq(_T_330, UInt<1>(0h0)) when _T_333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_330, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_334 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_334 : node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_338 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_338, UInt<1>(0h1), "") : assert_54 node _T_342 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_342, UInt<1>(0h1), "") : assert_55 node _T_346 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_346, UInt<1>(0h1), "") : assert_56 node _T_350 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_351 = asUInt(reset) node _T_352 = eq(_T_351, UInt<1>(0h0)) when _T_352 : node _T_353 = eq(_T_350, UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_350, UInt<1>(0h1), "") : assert_57 node _T_354 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_354 : node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(sink_ok, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_361 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_361, UInt<1>(0h1), "") : assert_60 node _T_365 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(_T_365, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_365, UInt<1>(0h1), "") : assert_61 node _T_369 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_369, UInt<1>(0h1), "") : assert_62 node _T_373 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_373, UInt<1>(0h1), "") : assert_63 node _T_377 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_378 = or(UInt<1>(0h1), _T_377) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_378, UInt<1>(0h1), "") : assert_64 node _T_382 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_382 : node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(sink_ok, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_389 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_389, UInt<1>(0h1), "") : assert_67 node _T_393 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_393, UInt<1>(0h1), "") : assert_68 node _T_397 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_397, UInt<1>(0h1), "") : assert_69 node _T_401 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_402 = or(_T_401, io.in.d.bits.corrupt) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_402, UInt<1>(0h1), "") : assert_70 node _T_406 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_407 = or(UInt<1>(0h1), _T_406) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_407, UInt<1>(0h1), "") : assert_71 node _T_411 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_411 : node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_415 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_415, UInt<1>(0h1), "") : assert_73 node _T_419 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(_T_419, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_419, UInt<1>(0h1), "") : assert_74 node _T_423 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_424 = or(UInt<1>(0h1), _T_423) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_424, UInt<1>(0h1), "") : assert_75 node _T_428 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_428 : node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_432 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_432, UInt<1>(0h1), "") : assert_77 node _T_436 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_437 = or(_T_436, io.in.d.bits.corrupt) node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_T_437, UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_437, UInt<1>(0h1), "") : assert_78 node _T_441 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_442 = or(UInt<1>(0h1), _T_441) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_442, UInt<1>(0h1), "") : assert_79 node _T_446 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_450 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_450, UInt<1>(0h1), "") : assert_81 node _T_454 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_454, UInt<1>(0h1), "") : assert_82 node _T_458 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_459 = or(UInt<1>(0h1), _T_458) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_459, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_463 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_463, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_467 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_467, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_471 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_471, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_475 = eq(a_first, UInt<1>(0h0)) node _T_476 = and(io.in.a.valid, _T_475) when _T_476 : node _T_477 = eq(io.in.a.bits.opcode, opcode) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_477, UInt<1>(0h1), "") : assert_87 node _T_481 = eq(io.in.a.bits.param, param) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_481, UInt<1>(0h1), "") : assert_88 node _T_485 = eq(io.in.a.bits.size, size) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_485, UInt<1>(0h1), "") : assert_89 node _T_489 = eq(io.in.a.bits.source, source) node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_T_489, UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_489, UInt<1>(0h1), "") : assert_90 node _T_493 = eq(io.in.a.bits.address, address) node _T_494 = asUInt(reset) node _T_495 = eq(_T_494, UInt<1>(0h0)) when _T_495 : node _T_496 = eq(_T_493, UInt<1>(0h0)) when _T_496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_493, UInt<1>(0h1), "") : assert_91 node _T_497 = and(io.in.a.ready, io.in.a.valid) node _T_498 = and(_T_497, a_first) when _T_498 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_499 = eq(d_first, UInt<1>(0h0)) node _T_500 = and(io.in.d.valid, _T_499) when _T_500 : node _T_501 = eq(io.in.d.bits.opcode, opcode_1) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_501, UInt<1>(0h1), "") : assert_92 node _T_505 = eq(io.in.d.bits.param, param_1) node _T_506 = asUInt(reset) node _T_507 = eq(_T_506, UInt<1>(0h0)) when _T_507 : node _T_508 = eq(_T_505, UInt<1>(0h0)) when _T_508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_505, UInt<1>(0h1), "") : assert_93 node _T_509 = eq(io.in.d.bits.size, size_1) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_509, UInt<1>(0h1), "") : assert_94 node _T_513 = eq(io.in.d.bits.source, source_1) node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_T_513, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_513, UInt<1>(0h1), "") : assert_95 node _T_517 = eq(io.in.d.bits.sink, sink) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_517, UInt<1>(0h1), "") : assert_96 node _T_521 = eq(io.in.d.bits.denied, denied) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_521, UInt<1>(0h1), "") : assert_97 node _T_525 = and(io.in.d.ready, io.in.d.valid) node _T_526 = and(_T_525, d_first) when _T_526 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_527 = and(io.in.a.valid, a_first_1) node _T_528 = and(_T_527, UInt<1>(0h1)) when _T_528 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_529 = and(io.in.a.ready, io.in.a.valid) node _T_530 = and(_T_529, a_first_1) node _T_531 = and(_T_530, UInt<1>(0h1)) when _T_531 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_532 = dshr(inflight, io.in.a.bits.source) node _T_533 = bits(_T_532, 0, 0) node _T_534 = eq(_T_533, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_534, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_538 = and(io.in.d.valid, d_first_1) node _T_539 = and(_T_538, UInt<1>(0h1)) node _T_540 = eq(d_release_ack, UInt<1>(0h0)) node _T_541 = and(_T_539, _T_540) when _T_541 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_542 = and(io.in.d.ready, io.in.d.valid) node _T_543 = and(_T_542, d_first_1) node _T_544 = and(_T_543, UInt<1>(0h1)) node _T_545 = eq(d_release_ack, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) when _T_546 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_547 = and(io.in.d.valid, d_first_1) node _T_548 = and(_T_547, UInt<1>(0h1)) node _T_549 = eq(d_release_ack, UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) when _T_550 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_551 = dshr(inflight, io.in.d.bits.source) node _T_552 = bits(_T_551, 0, 0) node _T_553 = or(_T_552, same_cycle_resp) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_553, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_557 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_558 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_559 = or(_T_557, _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_559, UInt<1>(0h1), "") : assert_100 node _T_563 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_563, UInt<1>(0h1), "") : assert_101 else : node _T_567 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_568 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_569 = or(_T_567, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_569, UInt<1>(0h1), "") : assert_102 node _T_573 = eq(io.in.d.bits.size, a_size_lookup) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_573, UInt<1>(0h1), "") : assert_103 node _T_577 = and(io.in.d.valid, d_first_1) node _T_578 = and(_T_577, a_first_1) node _T_579 = and(_T_578, io.in.a.valid) node _T_580 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_581 = and(_T_579, _T_580) node _T_582 = eq(d_release_ack, UInt<1>(0h0)) node _T_583 = and(_T_581, _T_582) when _T_583 : node _T_584 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_585 = or(_T_584, io.in.a.ready) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_585, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_101 node _T_589 = orr(inflight) node _T_590 = eq(_T_589, UInt<1>(0h0)) node _T_591 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_592 = or(_T_590, _T_591) node _T_593 = lt(watchdog, plusarg_reader.out) node _T_594 = or(_T_592, _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_594, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_598 = and(io.in.a.ready, io.in.a.valid) node _T_599 = and(io.in.d.ready, io.in.d.valid) node _T_600 = or(_T_598, _T_599) when _T_600 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_601 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_602 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_603 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_604 = and(_T_602, _T_603) node _T_605 = and(_T_601, _T_604) when _T_605 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_606 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_607 = and(_T_606, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_608 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_609 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_610 = and(_T_608, _T_609) node _T_611 = and(_T_607, _T_610) when _T_611 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_612 = dshr(inflight_1, _WIRE_15.bits.source) node _T_613 = bits(_T_612, 0, 0) node _T_614 = eq(_T_613, UInt<1>(0h0)) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_614, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_618 = and(io.in.d.valid, d_first_2) node _T_619 = and(_T_618, UInt<1>(0h1)) node _T_620 = and(_T_619, d_release_ack_1) when _T_620 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_621 = and(io.in.d.ready, io.in.d.valid) node _T_622 = and(_T_621, d_first_2) node _T_623 = and(_T_622, UInt<1>(0h1)) node _T_624 = and(_T_623, d_release_ack_1) when _T_624 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_625 = and(io.in.d.valid, d_first_2) node _T_626 = and(_T_625, UInt<1>(0h1)) node _T_627 = and(_T_626, d_release_ack_1) when _T_627 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_628 = dshr(inflight_1, io.in.d.bits.source) node _T_629 = bits(_T_628, 0, 0) node _T_630 = or(_T_629, same_cycle_resp_1) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_630, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_634 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_634, UInt<1>(0h1), "") : assert_108 else : node _T_638 = eq(io.in.d.bits.size, c_size_lookup) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_638, UInt<1>(0h1), "") : assert_109 node _T_642 = and(io.in.d.valid, d_first_2) node _T_643 = and(_T_642, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_644 = and(_T_643, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_645 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_646 = and(_T_644, _T_645) node _T_647 = and(_T_646, d_release_ack_1) node _T_648 = eq(c_probe_ack, UInt<1>(0h0)) node _T_649 = and(_T_647, _T_648) when _T_649 : node _T_650 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_651 = or(_T_650, _WIRE_23.ready) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_651, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_102 node _T_655 = orr(inflight_1) node _T_656 = eq(_T_655, UInt<1>(0h0)) node _T_657 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_658 = or(_T_656, _T_657) node _T_659 = lt(watchdog_1, plusarg_reader_1.out) node _T_660 = or(_T_658, _T_659) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_660, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_664 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_665 = and(io.in.d.ready, io.in.d.valid) node _T_666 = or(_T_664, _T_665) when _T_666 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_50( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_598 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_598; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_598; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_666 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_666; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_666; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_666; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_528 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_528; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_528; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_598 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_577 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_577 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_666 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_642 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_642 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_666 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLAtomicAutomata_pbus : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.user.amba_prot.fetch invalidate nodeIn.a.bits.user.amba_prot.secure invalidate nodeIn.a.bits.user.amba_prot.privileged invalidate nodeIn.a.bits.user.amba_prot.writealloc invalidate nodeIn.a.bits.user.amba_prot.readalloc invalidate nodeIn.a.bits.user.amba_prot.modifiable invalidate nodeIn.a.bits.user.amba_prot.bufferable invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_4 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.user.amba_prot.fetch, nodeIn.a.bits.user.amba_prot.fetch connect monitor.io.in.a.bits.user.amba_prot.secure, nodeIn.a.bits.user.amba_prot.secure connect monitor.io.in.a.bits.user.amba_prot.privileged, nodeIn.a.bits.user.amba_prot.privileged connect monitor.io.in.a.bits.user.amba_prot.writealloc, nodeIn.a.bits.user.amba_prot.writealloc connect monitor.io.in.a.bits.user.amba_prot.readalloc, nodeIn.a.bits.user.amba_prot.readalloc connect monitor.io.in.a.bits.user.amba_prot.modifiable, nodeIn.a.bits.user.amba_prot.modifiable connect monitor.io.in.a.bits.user.amba_prot.bufferable, nodeIn.a.bits.user.amba_prot.bufferable connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.user.amba_prot.fetch invalidate nodeOut.a.bits.user.amba_prot.secure invalidate nodeOut.a.bits.user.amba_prot.privileged invalidate nodeOut.a.bits.user.amba_prot.writealloc invalidate nodeOut.a.bits.user.amba_prot.readalloc invalidate nodeOut.a.bits.user.amba_prot.modifiable invalidate nodeOut.a.bits.user.amba_prot.bufferable invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in wire initval : { state : UInt<2>} connect initval.state, UInt<1>(0h0) wire _cam_s_WIRE : { state : UInt<2>}[1] connect _cam_s_WIRE[0], initval regreset cam_s : { state : UInt<2>}[1], clock, reset, _cam_s_WIRE reg cam_a : { bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, fifoId : UInt<1>, lut : UInt<4>}[1], clock reg cam_d : { data : UInt<64>, denied : UInt<1>, corrupt : UInt<1>}[1], clock node cam_free_0 = eq(cam_s[0].state, UInt<1>(0h0)) node cam_amo_0 = eq(cam_s[0].state, UInt<2>(0h2)) node _cam_abusy_T = eq(cam_s[0].state, UInt<2>(0h3)) node _cam_abusy_T_1 = eq(cam_s[0].state, UInt<2>(0h2)) node cam_abusy_0 = or(_cam_abusy_T, _cam_abusy_T_1) node cam_dmatch_0 = neq(cam_s[0].state, UInt<1>(0h0)) node _a_canLogical_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _a_canLogical_T_1 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _a_canLogical_T_2 = cvt(_a_canLogical_T_1) node _a_canLogical_T_3 = and(_a_canLogical_T_2, asSInt(UInt<1>(0h0))) node _a_canLogical_T_4 = asSInt(_a_canLogical_T_3) node _a_canLogical_T_5 = eq(_a_canLogical_T_4, asSInt(UInt<1>(0h0))) node _a_canLogical_T_6 = and(_a_canLogical_T, _a_canLogical_T_5) node _a_canLogical_T_7 = or(UInt<1>(0h0), _a_canLogical_T_6) node a_canLogical = and(UInt<1>(0h1), _a_canLogical_T_7) node _a_canArithmetic_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _a_canArithmetic_T_1 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _a_canArithmetic_T_2 = cvt(_a_canArithmetic_T_1) node _a_canArithmetic_T_3 = and(_a_canArithmetic_T_2, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_4 = asSInt(_a_canArithmetic_T_3) node _a_canArithmetic_T_5 = eq(_a_canArithmetic_T_4, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_6 = and(_a_canArithmetic_T, _a_canArithmetic_T_5) node _a_canArithmetic_T_7 = or(UInt<1>(0h0), _a_canArithmetic_T_6) node a_canArithmetic = and(UInt<1>(0h1), _a_canArithmetic_T_7) node a_isLogical = eq(nodeIn.a.bits.opcode, UInt<2>(0h3)) node a_isArithmetic = eq(nodeIn.a.bits.opcode, UInt<2>(0h2)) node _a_isSupported_T = mux(a_isArithmetic, a_canArithmetic, UInt<1>(0h1)) node a_isSupported = mux(a_isLogical, a_canLogical, _a_isSupported_T) node _a_cam_por_put_T = or(UInt<1>(0h0), cam_amo_0) node _a_cam_sel_put_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node a_cam_sel_put_0 = and(cam_amo_0, _a_cam_sel_put_T) node _a_fifoId_T = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _a_fifoId_T_1 = cvt(_a_fifoId_T) node _a_fifoId_T_2 = and(_a_fifoId_T_1, asSInt(UInt<1>(0h0))) node _a_fifoId_T_3 = asSInt(_a_fifoId_T_2) node _a_fifoId_T_4 = eq(_a_fifoId_T_3, asSInt(UInt<1>(0h0))) node _a_cam_busy_T = eq(cam_a[0].fifoId, UInt<1>(0h0)) node a_cam_busy = and(cam_abusy_0, _a_cam_busy_T) node _a_cam_por_free_T = or(UInt<1>(0h0), cam_free_0) node _a_cam_sel_free_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node a_cam_sel_free_0 = and(cam_free_0, _a_cam_sel_free_T) node _indexes_T = bits(cam_a[0].bits.data, 0, 0) node _indexes_T_1 = bits(cam_d[0].data, 0, 0) node indexes_0 = cat(_indexes_T, _indexes_T_1) node _indexes_T_2 = bits(cam_a[0].bits.data, 1, 1) node _indexes_T_3 = bits(cam_d[0].data, 1, 1) node indexes_1 = cat(_indexes_T_2, _indexes_T_3) node _indexes_T_4 = bits(cam_a[0].bits.data, 2, 2) node _indexes_T_5 = bits(cam_d[0].data, 2, 2) node indexes_2 = cat(_indexes_T_4, _indexes_T_5) node _indexes_T_6 = bits(cam_a[0].bits.data, 3, 3) node _indexes_T_7 = bits(cam_d[0].data, 3, 3) node indexes_3 = cat(_indexes_T_6, _indexes_T_7) node _indexes_T_8 = bits(cam_a[0].bits.data, 4, 4) node _indexes_T_9 = bits(cam_d[0].data, 4, 4) node indexes_4 = cat(_indexes_T_8, _indexes_T_9) node _indexes_T_10 = bits(cam_a[0].bits.data, 5, 5) node _indexes_T_11 = bits(cam_d[0].data, 5, 5) node indexes_5 = cat(_indexes_T_10, _indexes_T_11) node _indexes_T_12 = bits(cam_a[0].bits.data, 6, 6) node _indexes_T_13 = bits(cam_d[0].data, 6, 6) node indexes_6 = cat(_indexes_T_12, _indexes_T_13) node _indexes_T_14 = bits(cam_a[0].bits.data, 7, 7) node _indexes_T_15 = bits(cam_d[0].data, 7, 7) node indexes_7 = cat(_indexes_T_14, _indexes_T_15) node _indexes_T_16 = bits(cam_a[0].bits.data, 8, 8) node _indexes_T_17 = bits(cam_d[0].data, 8, 8) node indexes_8 = cat(_indexes_T_16, _indexes_T_17) node _indexes_T_18 = bits(cam_a[0].bits.data, 9, 9) node _indexes_T_19 = bits(cam_d[0].data, 9, 9) node indexes_9 = cat(_indexes_T_18, _indexes_T_19) node _indexes_T_20 = bits(cam_a[0].bits.data, 10, 10) node _indexes_T_21 = bits(cam_d[0].data, 10, 10) node indexes_10 = cat(_indexes_T_20, _indexes_T_21) node _indexes_T_22 = bits(cam_a[0].bits.data, 11, 11) node _indexes_T_23 = bits(cam_d[0].data, 11, 11) node indexes_11 = cat(_indexes_T_22, _indexes_T_23) node _indexes_T_24 = bits(cam_a[0].bits.data, 12, 12) node _indexes_T_25 = bits(cam_d[0].data, 12, 12) node indexes_12 = cat(_indexes_T_24, _indexes_T_25) node _indexes_T_26 = bits(cam_a[0].bits.data, 13, 13) node _indexes_T_27 = bits(cam_d[0].data, 13, 13) node indexes_13 = cat(_indexes_T_26, _indexes_T_27) node _indexes_T_28 = bits(cam_a[0].bits.data, 14, 14) node _indexes_T_29 = bits(cam_d[0].data, 14, 14) node indexes_14 = cat(_indexes_T_28, _indexes_T_29) node _indexes_T_30 = bits(cam_a[0].bits.data, 15, 15) node _indexes_T_31 = bits(cam_d[0].data, 15, 15) node indexes_15 = cat(_indexes_T_30, _indexes_T_31) node _indexes_T_32 = bits(cam_a[0].bits.data, 16, 16) node _indexes_T_33 = bits(cam_d[0].data, 16, 16) node indexes_16 = cat(_indexes_T_32, _indexes_T_33) node _indexes_T_34 = bits(cam_a[0].bits.data, 17, 17) node _indexes_T_35 = bits(cam_d[0].data, 17, 17) node indexes_17 = cat(_indexes_T_34, _indexes_T_35) node _indexes_T_36 = bits(cam_a[0].bits.data, 18, 18) node _indexes_T_37 = bits(cam_d[0].data, 18, 18) node indexes_18 = cat(_indexes_T_36, _indexes_T_37) node _indexes_T_38 = bits(cam_a[0].bits.data, 19, 19) node _indexes_T_39 = bits(cam_d[0].data, 19, 19) node indexes_19 = cat(_indexes_T_38, _indexes_T_39) node _indexes_T_40 = bits(cam_a[0].bits.data, 20, 20) node _indexes_T_41 = bits(cam_d[0].data, 20, 20) node indexes_20 = cat(_indexes_T_40, _indexes_T_41) node _indexes_T_42 = bits(cam_a[0].bits.data, 21, 21) node _indexes_T_43 = bits(cam_d[0].data, 21, 21) node indexes_21 = cat(_indexes_T_42, _indexes_T_43) node _indexes_T_44 = bits(cam_a[0].bits.data, 22, 22) node _indexes_T_45 = bits(cam_d[0].data, 22, 22) node indexes_22 = cat(_indexes_T_44, _indexes_T_45) node _indexes_T_46 = bits(cam_a[0].bits.data, 23, 23) node _indexes_T_47 = bits(cam_d[0].data, 23, 23) node indexes_23 = cat(_indexes_T_46, _indexes_T_47) node _indexes_T_48 = bits(cam_a[0].bits.data, 24, 24) node _indexes_T_49 = bits(cam_d[0].data, 24, 24) node indexes_24 = cat(_indexes_T_48, _indexes_T_49) node _indexes_T_50 = bits(cam_a[0].bits.data, 25, 25) node _indexes_T_51 = bits(cam_d[0].data, 25, 25) node indexes_25 = cat(_indexes_T_50, _indexes_T_51) node _indexes_T_52 = bits(cam_a[0].bits.data, 26, 26) node _indexes_T_53 = bits(cam_d[0].data, 26, 26) node indexes_26 = cat(_indexes_T_52, _indexes_T_53) node _indexes_T_54 = bits(cam_a[0].bits.data, 27, 27) node _indexes_T_55 = bits(cam_d[0].data, 27, 27) node indexes_27 = cat(_indexes_T_54, _indexes_T_55) node _indexes_T_56 = bits(cam_a[0].bits.data, 28, 28) node _indexes_T_57 = bits(cam_d[0].data, 28, 28) node indexes_28 = cat(_indexes_T_56, _indexes_T_57) node _indexes_T_58 = bits(cam_a[0].bits.data, 29, 29) node _indexes_T_59 = bits(cam_d[0].data, 29, 29) node indexes_29 = cat(_indexes_T_58, _indexes_T_59) node _indexes_T_60 = bits(cam_a[0].bits.data, 30, 30) node _indexes_T_61 = bits(cam_d[0].data, 30, 30) node indexes_30 = cat(_indexes_T_60, _indexes_T_61) node _indexes_T_62 = bits(cam_a[0].bits.data, 31, 31) node _indexes_T_63 = bits(cam_d[0].data, 31, 31) node indexes_31 = cat(_indexes_T_62, _indexes_T_63) node _indexes_T_64 = bits(cam_a[0].bits.data, 32, 32) node _indexes_T_65 = bits(cam_d[0].data, 32, 32) node indexes_32 = cat(_indexes_T_64, _indexes_T_65) node _indexes_T_66 = bits(cam_a[0].bits.data, 33, 33) node _indexes_T_67 = bits(cam_d[0].data, 33, 33) node indexes_33 = cat(_indexes_T_66, _indexes_T_67) node _indexes_T_68 = bits(cam_a[0].bits.data, 34, 34) node _indexes_T_69 = bits(cam_d[0].data, 34, 34) node indexes_34 = cat(_indexes_T_68, _indexes_T_69) node _indexes_T_70 = bits(cam_a[0].bits.data, 35, 35) node _indexes_T_71 = bits(cam_d[0].data, 35, 35) node indexes_35 = cat(_indexes_T_70, _indexes_T_71) node _indexes_T_72 = bits(cam_a[0].bits.data, 36, 36) node _indexes_T_73 = bits(cam_d[0].data, 36, 36) node indexes_36 = cat(_indexes_T_72, _indexes_T_73) node _indexes_T_74 = bits(cam_a[0].bits.data, 37, 37) node _indexes_T_75 = bits(cam_d[0].data, 37, 37) node indexes_37 = cat(_indexes_T_74, _indexes_T_75) node _indexes_T_76 = bits(cam_a[0].bits.data, 38, 38) node _indexes_T_77 = bits(cam_d[0].data, 38, 38) node indexes_38 = cat(_indexes_T_76, _indexes_T_77) node _indexes_T_78 = bits(cam_a[0].bits.data, 39, 39) node _indexes_T_79 = bits(cam_d[0].data, 39, 39) node indexes_39 = cat(_indexes_T_78, _indexes_T_79) node _indexes_T_80 = bits(cam_a[0].bits.data, 40, 40) node _indexes_T_81 = bits(cam_d[0].data, 40, 40) node indexes_40 = cat(_indexes_T_80, _indexes_T_81) node _indexes_T_82 = bits(cam_a[0].bits.data, 41, 41) node _indexes_T_83 = bits(cam_d[0].data, 41, 41) node indexes_41 = cat(_indexes_T_82, _indexes_T_83) node _indexes_T_84 = bits(cam_a[0].bits.data, 42, 42) node _indexes_T_85 = bits(cam_d[0].data, 42, 42) node indexes_42 = cat(_indexes_T_84, _indexes_T_85) node _indexes_T_86 = bits(cam_a[0].bits.data, 43, 43) node _indexes_T_87 = bits(cam_d[0].data, 43, 43) node indexes_43 = cat(_indexes_T_86, _indexes_T_87) node _indexes_T_88 = bits(cam_a[0].bits.data, 44, 44) node _indexes_T_89 = bits(cam_d[0].data, 44, 44) node indexes_44 = cat(_indexes_T_88, _indexes_T_89) node _indexes_T_90 = bits(cam_a[0].bits.data, 45, 45) node _indexes_T_91 = bits(cam_d[0].data, 45, 45) node indexes_45 = cat(_indexes_T_90, _indexes_T_91) node _indexes_T_92 = bits(cam_a[0].bits.data, 46, 46) node _indexes_T_93 = bits(cam_d[0].data, 46, 46) node indexes_46 = cat(_indexes_T_92, _indexes_T_93) node _indexes_T_94 = bits(cam_a[0].bits.data, 47, 47) node _indexes_T_95 = bits(cam_d[0].data, 47, 47) node indexes_47 = cat(_indexes_T_94, _indexes_T_95) node _indexes_T_96 = bits(cam_a[0].bits.data, 48, 48) node _indexes_T_97 = bits(cam_d[0].data, 48, 48) node indexes_48 = cat(_indexes_T_96, _indexes_T_97) node _indexes_T_98 = bits(cam_a[0].bits.data, 49, 49) node _indexes_T_99 = bits(cam_d[0].data, 49, 49) node indexes_49 = cat(_indexes_T_98, _indexes_T_99) node _indexes_T_100 = bits(cam_a[0].bits.data, 50, 50) node _indexes_T_101 = bits(cam_d[0].data, 50, 50) node indexes_50 = cat(_indexes_T_100, _indexes_T_101) node _indexes_T_102 = bits(cam_a[0].bits.data, 51, 51) node _indexes_T_103 = bits(cam_d[0].data, 51, 51) node indexes_51 = cat(_indexes_T_102, _indexes_T_103) node _indexes_T_104 = bits(cam_a[0].bits.data, 52, 52) node _indexes_T_105 = bits(cam_d[0].data, 52, 52) node indexes_52 = cat(_indexes_T_104, _indexes_T_105) node _indexes_T_106 = bits(cam_a[0].bits.data, 53, 53) node _indexes_T_107 = bits(cam_d[0].data, 53, 53) node indexes_53 = cat(_indexes_T_106, _indexes_T_107) node _indexes_T_108 = bits(cam_a[0].bits.data, 54, 54) node _indexes_T_109 = bits(cam_d[0].data, 54, 54) node indexes_54 = cat(_indexes_T_108, _indexes_T_109) node _indexes_T_110 = bits(cam_a[0].bits.data, 55, 55) node _indexes_T_111 = bits(cam_d[0].data, 55, 55) node indexes_55 = cat(_indexes_T_110, _indexes_T_111) node _indexes_T_112 = bits(cam_a[0].bits.data, 56, 56) node _indexes_T_113 = bits(cam_d[0].data, 56, 56) node indexes_56 = cat(_indexes_T_112, _indexes_T_113) node _indexes_T_114 = bits(cam_a[0].bits.data, 57, 57) node _indexes_T_115 = bits(cam_d[0].data, 57, 57) node indexes_57 = cat(_indexes_T_114, _indexes_T_115) node _indexes_T_116 = bits(cam_a[0].bits.data, 58, 58) node _indexes_T_117 = bits(cam_d[0].data, 58, 58) node indexes_58 = cat(_indexes_T_116, _indexes_T_117) node _indexes_T_118 = bits(cam_a[0].bits.data, 59, 59) node _indexes_T_119 = bits(cam_d[0].data, 59, 59) node indexes_59 = cat(_indexes_T_118, _indexes_T_119) node _indexes_T_120 = bits(cam_a[0].bits.data, 60, 60) node _indexes_T_121 = bits(cam_d[0].data, 60, 60) node indexes_60 = cat(_indexes_T_120, _indexes_T_121) node _indexes_T_122 = bits(cam_a[0].bits.data, 61, 61) node _indexes_T_123 = bits(cam_d[0].data, 61, 61) node indexes_61 = cat(_indexes_T_122, _indexes_T_123) node _indexes_T_124 = bits(cam_a[0].bits.data, 62, 62) node _indexes_T_125 = bits(cam_d[0].data, 62, 62) node indexes_62 = cat(_indexes_T_124, _indexes_T_125) node _indexes_T_126 = bits(cam_a[0].bits.data, 63, 63) node _indexes_T_127 = bits(cam_d[0].data, 63, 63) node indexes_63 = cat(_indexes_T_126, _indexes_T_127) node _logic_out_T = dshr(cam_a[0].lut, indexes_0) node _logic_out_T_1 = bits(_logic_out_T, 0, 0) node _logic_out_T_2 = dshr(cam_a[0].lut, indexes_1) node _logic_out_T_3 = bits(_logic_out_T_2, 0, 0) node _logic_out_T_4 = dshr(cam_a[0].lut, indexes_2) node _logic_out_T_5 = bits(_logic_out_T_4, 0, 0) node _logic_out_T_6 = dshr(cam_a[0].lut, indexes_3) node _logic_out_T_7 = bits(_logic_out_T_6, 0, 0) node _logic_out_T_8 = dshr(cam_a[0].lut, indexes_4) node _logic_out_T_9 = bits(_logic_out_T_8, 0, 0) node _logic_out_T_10 = dshr(cam_a[0].lut, indexes_5) node _logic_out_T_11 = bits(_logic_out_T_10, 0, 0) node _logic_out_T_12 = dshr(cam_a[0].lut, indexes_6) node _logic_out_T_13 = bits(_logic_out_T_12, 0, 0) node _logic_out_T_14 = dshr(cam_a[0].lut, indexes_7) node _logic_out_T_15 = bits(_logic_out_T_14, 0, 0) node _logic_out_T_16 = dshr(cam_a[0].lut, indexes_8) node _logic_out_T_17 = bits(_logic_out_T_16, 0, 0) node _logic_out_T_18 = dshr(cam_a[0].lut, indexes_9) node _logic_out_T_19 = bits(_logic_out_T_18, 0, 0) node _logic_out_T_20 = dshr(cam_a[0].lut, indexes_10) node _logic_out_T_21 = bits(_logic_out_T_20, 0, 0) node _logic_out_T_22 = dshr(cam_a[0].lut, indexes_11) node _logic_out_T_23 = bits(_logic_out_T_22, 0, 0) node _logic_out_T_24 = dshr(cam_a[0].lut, indexes_12) node _logic_out_T_25 = bits(_logic_out_T_24, 0, 0) node _logic_out_T_26 = dshr(cam_a[0].lut, indexes_13) node _logic_out_T_27 = bits(_logic_out_T_26, 0, 0) node _logic_out_T_28 = dshr(cam_a[0].lut, indexes_14) node _logic_out_T_29 = bits(_logic_out_T_28, 0, 0) node _logic_out_T_30 = dshr(cam_a[0].lut, indexes_15) node _logic_out_T_31 = bits(_logic_out_T_30, 0, 0) node _logic_out_T_32 = dshr(cam_a[0].lut, indexes_16) node _logic_out_T_33 = bits(_logic_out_T_32, 0, 0) node _logic_out_T_34 = dshr(cam_a[0].lut, indexes_17) node _logic_out_T_35 = bits(_logic_out_T_34, 0, 0) node _logic_out_T_36 = dshr(cam_a[0].lut, indexes_18) node _logic_out_T_37 = bits(_logic_out_T_36, 0, 0) node _logic_out_T_38 = dshr(cam_a[0].lut, indexes_19) node _logic_out_T_39 = bits(_logic_out_T_38, 0, 0) node _logic_out_T_40 = dshr(cam_a[0].lut, indexes_20) node _logic_out_T_41 = bits(_logic_out_T_40, 0, 0) node _logic_out_T_42 = dshr(cam_a[0].lut, indexes_21) node _logic_out_T_43 = bits(_logic_out_T_42, 0, 0) node _logic_out_T_44 = dshr(cam_a[0].lut, indexes_22) node _logic_out_T_45 = bits(_logic_out_T_44, 0, 0) node _logic_out_T_46 = dshr(cam_a[0].lut, indexes_23) node _logic_out_T_47 = bits(_logic_out_T_46, 0, 0) node _logic_out_T_48 = dshr(cam_a[0].lut, indexes_24) node _logic_out_T_49 = bits(_logic_out_T_48, 0, 0) node _logic_out_T_50 = dshr(cam_a[0].lut, indexes_25) node _logic_out_T_51 = bits(_logic_out_T_50, 0, 0) node _logic_out_T_52 = dshr(cam_a[0].lut, indexes_26) node _logic_out_T_53 = bits(_logic_out_T_52, 0, 0) node _logic_out_T_54 = dshr(cam_a[0].lut, indexes_27) node _logic_out_T_55 = bits(_logic_out_T_54, 0, 0) node _logic_out_T_56 = dshr(cam_a[0].lut, indexes_28) node _logic_out_T_57 = bits(_logic_out_T_56, 0, 0) node _logic_out_T_58 = dshr(cam_a[0].lut, indexes_29) node _logic_out_T_59 = bits(_logic_out_T_58, 0, 0) node _logic_out_T_60 = dshr(cam_a[0].lut, indexes_30) node _logic_out_T_61 = bits(_logic_out_T_60, 0, 0) node _logic_out_T_62 = dshr(cam_a[0].lut, indexes_31) node _logic_out_T_63 = bits(_logic_out_T_62, 0, 0) node _logic_out_T_64 = dshr(cam_a[0].lut, indexes_32) node _logic_out_T_65 = bits(_logic_out_T_64, 0, 0) node _logic_out_T_66 = dshr(cam_a[0].lut, indexes_33) node _logic_out_T_67 = bits(_logic_out_T_66, 0, 0) node _logic_out_T_68 = dshr(cam_a[0].lut, indexes_34) node _logic_out_T_69 = bits(_logic_out_T_68, 0, 0) node _logic_out_T_70 = dshr(cam_a[0].lut, indexes_35) node _logic_out_T_71 = bits(_logic_out_T_70, 0, 0) node _logic_out_T_72 = dshr(cam_a[0].lut, indexes_36) node _logic_out_T_73 = bits(_logic_out_T_72, 0, 0) node _logic_out_T_74 = dshr(cam_a[0].lut, indexes_37) node _logic_out_T_75 = bits(_logic_out_T_74, 0, 0) node _logic_out_T_76 = dshr(cam_a[0].lut, indexes_38) node _logic_out_T_77 = bits(_logic_out_T_76, 0, 0) node _logic_out_T_78 = dshr(cam_a[0].lut, indexes_39) node _logic_out_T_79 = bits(_logic_out_T_78, 0, 0) node _logic_out_T_80 = dshr(cam_a[0].lut, indexes_40) node _logic_out_T_81 = bits(_logic_out_T_80, 0, 0) node _logic_out_T_82 = dshr(cam_a[0].lut, indexes_41) node _logic_out_T_83 = bits(_logic_out_T_82, 0, 0) node _logic_out_T_84 = dshr(cam_a[0].lut, indexes_42) node _logic_out_T_85 = bits(_logic_out_T_84, 0, 0) node _logic_out_T_86 = dshr(cam_a[0].lut, indexes_43) node _logic_out_T_87 = bits(_logic_out_T_86, 0, 0) node _logic_out_T_88 = dshr(cam_a[0].lut, indexes_44) node _logic_out_T_89 = bits(_logic_out_T_88, 0, 0) node _logic_out_T_90 = dshr(cam_a[0].lut, indexes_45) node _logic_out_T_91 = bits(_logic_out_T_90, 0, 0) node _logic_out_T_92 = dshr(cam_a[0].lut, indexes_46) node _logic_out_T_93 = bits(_logic_out_T_92, 0, 0) node _logic_out_T_94 = dshr(cam_a[0].lut, indexes_47) node _logic_out_T_95 = bits(_logic_out_T_94, 0, 0) node _logic_out_T_96 = dshr(cam_a[0].lut, indexes_48) node _logic_out_T_97 = bits(_logic_out_T_96, 0, 0) node _logic_out_T_98 = dshr(cam_a[0].lut, indexes_49) node _logic_out_T_99 = bits(_logic_out_T_98, 0, 0) node _logic_out_T_100 = dshr(cam_a[0].lut, indexes_50) node _logic_out_T_101 = bits(_logic_out_T_100, 0, 0) node _logic_out_T_102 = dshr(cam_a[0].lut, indexes_51) node _logic_out_T_103 = bits(_logic_out_T_102, 0, 0) node _logic_out_T_104 = dshr(cam_a[0].lut, indexes_52) node _logic_out_T_105 = bits(_logic_out_T_104, 0, 0) node _logic_out_T_106 = dshr(cam_a[0].lut, indexes_53) node _logic_out_T_107 = bits(_logic_out_T_106, 0, 0) node _logic_out_T_108 = dshr(cam_a[0].lut, indexes_54) node _logic_out_T_109 = bits(_logic_out_T_108, 0, 0) node _logic_out_T_110 = dshr(cam_a[0].lut, indexes_55) node _logic_out_T_111 = bits(_logic_out_T_110, 0, 0) node _logic_out_T_112 = dshr(cam_a[0].lut, indexes_56) node _logic_out_T_113 = bits(_logic_out_T_112, 0, 0) node _logic_out_T_114 = dshr(cam_a[0].lut, indexes_57) node _logic_out_T_115 = bits(_logic_out_T_114, 0, 0) node _logic_out_T_116 = dshr(cam_a[0].lut, indexes_58) node _logic_out_T_117 = bits(_logic_out_T_116, 0, 0) node _logic_out_T_118 = dshr(cam_a[0].lut, indexes_59) node _logic_out_T_119 = bits(_logic_out_T_118, 0, 0) node _logic_out_T_120 = dshr(cam_a[0].lut, indexes_60) node _logic_out_T_121 = bits(_logic_out_T_120, 0, 0) node _logic_out_T_122 = dshr(cam_a[0].lut, indexes_61) node _logic_out_T_123 = bits(_logic_out_T_122, 0, 0) node _logic_out_T_124 = dshr(cam_a[0].lut, indexes_62) node _logic_out_T_125 = bits(_logic_out_T_124, 0, 0) node _logic_out_T_126 = dshr(cam_a[0].lut, indexes_63) node _logic_out_T_127 = bits(_logic_out_T_126, 0, 0) node logic_out_lo_lo_lo_lo_lo = cat(_logic_out_T_3, _logic_out_T_1) node logic_out_lo_lo_lo_lo_hi = cat(_logic_out_T_7, _logic_out_T_5) node logic_out_lo_lo_lo_lo = cat(logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo) node logic_out_lo_lo_lo_hi_lo = cat(_logic_out_T_11, _logic_out_T_9) node logic_out_lo_lo_lo_hi_hi = cat(_logic_out_T_15, _logic_out_T_13) node logic_out_lo_lo_lo_hi = cat(logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo) node logic_out_lo_lo_lo = cat(logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo) node logic_out_lo_lo_hi_lo_lo = cat(_logic_out_T_19, _logic_out_T_17) node logic_out_lo_lo_hi_lo_hi = cat(_logic_out_T_23, _logic_out_T_21) node logic_out_lo_lo_hi_lo = cat(logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo) node logic_out_lo_lo_hi_hi_lo = cat(_logic_out_T_27, _logic_out_T_25) node logic_out_lo_lo_hi_hi_hi = cat(_logic_out_T_31, _logic_out_T_29) node logic_out_lo_lo_hi_hi = cat(logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo) node logic_out_lo_lo_hi = cat(logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo) node logic_out_lo_lo = cat(logic_out_lo_lo_hi, logic_out_lo_lo_lo) node logic_out_lo_hi_lo_lo_lo = cat(_logic_out_T_35, _logic_out_T_33) node logic_out_lo_hi_lo_lo_hi = cat(_logic_out_T_39, _logic_out_T_37) node logic_out_lo_hi_lo_lo = cat(logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo) node logic_out_lo_hi_lo_hi_lo = cat(_logic_out_T_43, _logic_out_T_41) node logic_out_lo_hi_lo_hi_hi = cat(_logic_out_T_47, _logic_out_T_45) node logic_out_lo_hi_lo_hi = cat(logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo) node logic_out_lo_hi_lo = cat(logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo) node logic_out_lo_hi_hi_lo_lo = cat(_logic_out_T_51, _logic_out_T_49) node logic_out_lo_hi_hi_lo_hi = cat(_logic_out_T_55, _logic_out_T_53) node logic_out_lo_hi_hi_lo = cat(logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo) node logic_out_lo_hi_hi_hi_lo = cat(_logic_out_T_59, _logic_out_T_57) node logic_out_lo_hi_hi_hi_hi = cat(_logic_out_T_63, _logic_out_T_61) node logic_out_lo_hi_hi_hi = cat(logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo) node logic_out_lo_hi_hi = cat(logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo) node logic_out_lo_hi = cat(logic_out_lo_hi_hi, logic_out_lo_hi_lo) node logic_out_lo = cat(logic_out_lo_hi, logic_out_lo_lo) node logic_out_hi_lo_lo_lo_lo = cat(_logic_out_T_67, _logic_out_T_65) node logic_out_hi_lo_lo_lo_hi = cat(_logic_out_T_71, _logic_out_T_69) node logic_out_hi_lo_lo_lo = cat(logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo) node logic_out_hi_lo_lo_hi_lo = cat(_logic_out_T_75, _logic_out_T_73) node logic_out_hi_lo_lo_hi_hi = cat(_logic_out_T_79, _logic_out_T_77) node logic_out_hi_lo_lo_hi = cat(logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo) node logic_out_hi_lo_lo = cat(logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo) node logic_out_hi_lo_hi_lo_lo = cat(_logic_out_T_83, _logic_out_T_81) node logic_out_hi_lo_hi_lo_hi = cat(_logic_out_T_87, _logic_out_T_85) node logic_out_hi_lo_hi_lo = cat(logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo) node logic_out_hi_lo_hi_hi_lo = cat(_logic_out_T_91, _logic_out_T_89) node logic_out_hi_lo_hi_hi_hi = cat(_logic_out_T_95, _logic_out_T_93) node logic_out_hi_lo_hi_hi = cat(logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo) node logic_out_hi_lo_hi = cat(logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo) node logic_out_hi_lo = cat(logic_out_hi_lo_hi, logic_out_hi_lo_lo) node logic_out_hi_hi_lo_lo_lo = cat(_logic_out_T_99, _logic_out_T_97) node logic_out_hi_hi_lo_lo_hi = cat(_logic_out_T_103, _logic_out_T_101) node logic_out_hi_hi_lo_lo = cat(logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo) node logic_out_hi_hi_lo_hi_lo = cat(_logic_out_T_107, _logic_out_T_105) node logic_out_hi_hi_lo_hi_hi = cat(_logic_out_T_111, _logic_out_T_109) node logic_out_hi_hi_lo_hi = cat(logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo) node logic_out_hi_hi_lo = cat(logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo) node logic_out_hi_hi_hi_lo_lo = cat(_logic_out_T_115, _logic_out_T_113) node logic_out_hi_hi_hi_lo_hi = cat(_logic_out_T_119, _logic_out_T_117) node logic_out_hi_hi_hi_lo = cat(logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo) node logic_out_hi_hi_hi_hi_lo = cat(_logic_out_T_123, _logic_out_T_121) node logic_out_hi_hi_hi_hi_hi = cat(_logic_out_T_127, _logic_out_T_125) node logic_out_hi_hi_hi_hi = cat(logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo) node logic_out_hi_hi_hi = cat(logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo) node logic_out_hi_hi = cat(logic_out_hi_hi_hi, logic_out_hi_hi_lo) node logic_out_hi = cat(logic_out_hi_hi, logic_out_hi_lo) node logic_out = cat(logic_out_hi, logic_out_lo) node unsigned = bits(cam_a[0].bits.param, 1, 1) node take_max = bits(cam_a[0].bits.param, 0, 0) node adder = bits(cam_a[0].bits.param, 2, 2) node _signSel_T = not(cam_a[0].bits.mask) node _signSel_T_1 = shr(cam_a[0].bits.mask, 1) node _signSel_T_2 = or(_signSel_T, _signSel_T_1) node signSel = not(_signSel_T_2) node _signbits_a_T = bits(cam_a[0].bits.data, 7, 7) node _signbits_a_T_1 = bits(cam_a[0].bits.data, 15, 15) node _signbits_a_T_2 = bits(cam_a[0].bits.data, 23, 23) node _signbits_a_T_3 = bits(cam_a[0].bits.data, 31, 31) node _signbits_a_T_4 = bits(cam_a[0].bits.data, 39, 39) node _signbits_a_T_5 = bits(cam_a[0].bits.data, 47, 47) node _signbits_a_T_6 = bits(cam_a[0].bits.data, 55, 55) node _signbits_a_T_7 = bits(cam_a[0].bits.data, 63, 63) node signbits_a_lo_lo = cat(_signbits_a_T_1, _signbits_a_T) node signbits_a_lo_hi = cat(_signbits_a_T_3, _signbits_a_T_2) node signbits_a_lo = cat(signbits_a_lo_hi, signbits_a_lo_lo) node signbits_a_hi_lo = cat(_signbits_a_T_5, _signbits_a_T_4) node signbits_a_hi_hi = cat(_signbits_a_T_7, _signbits_a_T_6) node signbits_a_hi = cat(signbits_a_hi_hi, signbits_a_hi_lo) node signbits_a = cat(signbits_a_hi, signbits_a_lo) node _signbits_d_T = bits(cam_d[0].data, 7, 7) node _signbits_d_T_1 = bits(cam_d[0].data, 15, 15) node _signbits_d_T_2 = bits(cam_d[0].data, 23, 23) node _signbits_d_T_3 = bits(cam_d[0].data, 31, 31) node _signbits_d_T_4 = bits(cam_d[0].data, 39, 39) node _signbits_d_T_5 = bits(cam_d[0].data, 47, 47) node _signbits_d_T_6 = bits(cam_d[0].data, 55, 55) node _signbits_d_T_7 = bits(cam_d[0].data, 63, 63) node signbits_d_lo_lo = cat(_signbits_d_T_1, _signbits_d_T) node signbits_d_lo_hi = cat(_signbits_d_T_3, _signbits_d_T_2) node signbits_d_lo = cat(signbits_d_lo_hi, signbits_d_lo_lo) node signbits_d_hi_lo = cat(_signbits_d_T_5, _signbits_d_T_4) node signbits_d_hi_hi = cat(_signbits_d_T_7, _signbits_d_T_6) node signbits_d_hi = cat(signbits_d_hi_hi, signbits_d_hi_lo) node signbits_d = cat(signbits_d_hi, signbits_d_lo) node _signbit_a_T = and(signbits_a, signSel) node _signbit_a_T_1 = shl(_signbit_a_T, 1) node signbit_a = bits(_signbit_a_T_1, 7, 0) node _signbit_d_T = and(signbits_d, signSel) node _signbit_d_T_1 = shl(_signbit_d_T, 1) node signbit_d = bits(_signbit_d_T_1, 7, 0) node _signext_a_T = shl(signbit_a, 1) node _signext_a_T_1 = bits(_signext_a_T, 7, 0) node _signext_a_T_2 = or(signbit_a, _signext_a_T_1) node _signext_a_T_3 = shl(_signext_a_T_2, 2) node _signext_a_T_4 = bits(_signext_a_T_3, 7, 0) node _signext_a_T_5 = or(_signext_a_T_2, _signext_a_T_4) node _signext_a_T_6 = shl(_signext_a_T_5, 4) node _signext_a_T_7 = bits(_signext_a_T_6, 7, 0) node _signext_a_T_8 = or(_signext_a_T_5, _signext_a_T_7) node _signext_a_T_9 = bits(_signext_a_T_8, 7, 0) node _signext_a_T_10 = bits(_signext_a_T_9, 0, 0) node _signext_a_T_11 = bits(_signext_a_T_9, 1, 1) node _signext_a_T_12 = bits(_signext_a_T_9, 2, 2) node _signext_a_T_13 = bits(_signext_a_T_9, 3, 3) node _signext_a_T_14 = bits(_signext_a_T_9, 4, 4) node _signext_a_T_15 = bits(_signext_a_T_9, 5, 5) node _signext_a_T_16 = bits(_signext_a_T_9, 6, 6) node _signext_a_T_17 = bits(_signext_a_T_9, 7, 7) node _signext_a_T_18 = mux(_signext_a_T_10, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_19 = mux(_signext_a_T_11, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_20 = mux(_signext_a_T_12, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_21 = mux(_signext_a_T_13, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_22 = mux(_signext_a_T_14, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_23 = mux(_signext_a_T_15, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_24 = mux(_signext_a_T_16, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_25 = mux(_signext_a_T_17, UInt<8>(0hff), UInt<8>(0h0)) node signext_a_lo_lo = cat(_signext_a_T_19, _signext_a_T_18) node signext_a_lo_hi = cat(_signext_a_T_21, _signext_a_T_20) node signext_a_lo = cat(signext_a_lo_hi, signext_a_lo_lo) node signext_a_hi_lo = cat(_signext_a_T_23, _signext_a_T_22) node signext_a_hi_hi = cat(_signext_a_T_25, _signext_a_T_24) node signext_a_hi = cat(signext_a_hi_hi, signext_a_hi_lo) node signext_a = cat(signext_a_hi, signext_a_lo) node _signext_d_T = shl(signbit_d, 1) node _signext_d_T_1 = bits(_signext_d_T, 7, 0) node _signext_d_T_2 = or(signbit_d, _signext_d_T_1) node _signext_d_T_3 = shl(_signext_d_T_2, 2) node _signext_d_T_4 = bits(_signext_d_T_3, 7, 0) node _signext_d_T_5 = or(_signext_d_T_2, _signext_d_T_4) node _signext_d_T_6 = shl(_signext_d_T_5, 4) node _signext_d_T_7 = bits(_signext_d_T_6, 7, 0) node _signext_d_T_8 = or(_signext_d_T_5, _signext_d_T_7) node _signext_d_T_9 = bits(_signext_d_T_8, 7, 0) node _signext_d_T_10 = bits(_signext_d_T_9, 0, 0) node _signext_d_T_11 = bits(_signext_d_T_9, 1, 1) node _signext_d_T_12 = bits(_signext_d_T_9, 2, 2) node _signext_d_T_13 = bits(_signext_d_T_9, 3, 3) node _signext_d_T_14 = bits(_signext_d_T_9, 4, 4) node _signext_d_T_15 = bits(_signext_d_T_9, 5, 5) node _signext_d_T_16 = bits(_signext_d_T_9, 6, 6) node _signext_d_T_17 = bits(_signext_d_T_9, 7, 7) node _signext_d_T_18 = mux(_signext_d_T_10, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_19 = mux(_signext_d_T_11, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_20 = mux(_signext_d_T_12, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_21 = mux(_signext_d_T_13, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_22 = mux(_signext_d_T_14, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_23 = mux(_signext_d_T_15, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_24 = mux(_signext_d_T_16, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_25 = mux(_signext_d_T_17, UInt<8>(0hff), UInt<8>(0h0)) node signext_d_lo_lo = cat(_signext_d_T_19, _signext_d_T_18) node signext_d_lo_hi = cat(_signext_d_T_21, _signext_d_T_20) node signext_d_lo = cat(signext_d_lo_hi, signext_d_lo_lo) node signext_d_hi_lo = cat(_signext_d_T_23, _signext_d_T_22) node signext_d_hi_hi = cat(_signext_d_T_25, _signext_d_T_24) node signext_d_hi = cat(signext_d_hi_hi, signext_d_hi_lo) node signext_d = cat(signext_d_hi, signext_d_lo) node _wide_mask_T = bits(cam_a[0].bits.mask, 0, 0) node _wide_mask_T_1 = bits(cam_a[0].bits.mask, 1, 1) node _wide_mask_T_2 = bits(cam_a[0].bits.mask, 2, 2) node _wide_mask_T_3 = bits(cam_a[0].bits.mask, 3, 3) node _wide_mask_T_4 = bits(cam_a[0].bits.mask, 4, 4) node _wide_mask_T_5 = bits(cam_a[0].bits.mask, 5, 5) node _wide_mask_T_6 = bits(cam_a[0].bits.mask, 6, 6) node _wide_mask_T_7 = bits(cam_a[0].bits.mask, 7, 7) node _wide_mask_T_8 = mux(_wide_mask_T, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_9 = mux(_wide_mask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_10 = mux(_wide_mask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_11 = mux(_wide_mask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_12 = mux(_wide_mask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_13 = mux(_wide_mask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_14 = mux(_wide_mask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_15 = mux(_wide_mask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node wide_mask_lo_lo = cat(_wide_mask_T_9, _wide_mask_T_8) node wide_mask_lo_hi = cat(_wide_mask_T_11, _wide_mask_T_10) node wide_mask_lo = cat(wide_mask_lo_hi, wide_mask_lo_lo) node wide_mask_hi_lo = cat(_wide_mask_T_13, _wide_mask_T_12) node wide_mask_hi_hi = cat(_wide_mask_T_15, _wide_mask_T_14) node wide_mask_hi = cat(wide_mask_hi_hi, wide_mask_hi_lo) node wide_mask = cat(wide_mask_hi, wide_mask_lo) node _a_a_ext_T = and(cam_a[0].bits.data, wide_mask) node a_a_ext = or(_a_a_ext_T, signext_a) node _a_d_ext_T = and(cam_d[0].data, wide_mask) node a_d_ext = or(_a_d_ext_T, signext_d) node _a_d_inv_T = not(a_d_ext) node a_d_inv = mux(adder, a_d_ext, _a_d_inv_T) node _adder_out_T = add(a_a_ext, a_d_inv) node adder_out = tail(_adder_out_T, 1) node _a_bigger_uneq_T = bits(a_a_ext, 63, 63) node a_bigger_uneq = eq(unsigned, _a_bigger_uneq_T) node _a_bigger_T = bits(a_a_ext, 63, 63) node _a_bigger_T_1 = bits(a_d_ext, 63, 63) node _a_bigger_T_2 = eq(_a_bigger_T, _a_bigger_T_1) node _a_bigger_T_3 = bits(adder_out, 63, 63) node _a_bigger_T_4 = eq(_a_bigger_T_3, UInt<1>(0h0)) node a_bigger = mux(_a_bigger_T_2, _a_bigger_T_4, a_bigger_uneq) node pick_a = eq(take_max, a_bigger) node _arith_out_T = mux(pick_a, cam_a[0].bits.data, cam_d[0].data) node arith_out = mux(adder, adder_out, _arith_out_T) node _amo_data_T = bits(cam_a[0].bits.opcode, 0, 0) node amo_data = mux(_amo_data_T, logic_out, arith_out) wire source_i : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} node _a_allow_T = eq(a_cam_busy, UInt<1>(0h0)) node _a_allow_T_1 = or(a_isSupported, cam_free_0) node a_allow = and(_a_allow_T, _a_allow_T_1) node _nodeIn_a_ready_T = and(source_i.ready, a_allow) connect nodeIn.a.ready, _nodeIn_a_ready_T node _source_i_valid_T = and(nodeIn.a.valid, a_allow) connect source_i.valid, _source_i_valid_T connect source_i.bits, nodeIn.a.bits node _T = eq(a_isSupported, UInt<1>(0h0)) when _T : connect source_i.bits.opcode, UInt<3>(0h4) connect source_i.bits.param, UInt<1>(0h0) wire source_c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect source_c.valid, cam_amo_0 node _source_c_bits_T = or(cam_a[0].bits.corrupt, cam_d[0].corrupt) node _source_c_bits_legal_T = leq(UInt<1>(0h0), cam_a[0].bits.size) node _source_c_bits_legal_T_1 = leq(cam_a[0].bits.size, UInt<3>(0h6)) node _source_c_bits_legal_T_2 = and(_source_c_bits_legal_T, _source_c_bits_legal_T_1) node _source_c_bits_legal_T_3 = or(UInt<1>(0h0), _source_c_bits_legal_T_2) node _source_c_bits_legal_T_4 = xor(cam_a[0].bits.address, UInt<1>(0h0)) node _source_c_bits_legal_T_5 = cvt(_source_c_bits_legal_T_4) node _source_c_bits_legal_T_6 = and(_source_c_bits_legal_T_5, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_7 = asSInt(_source_c_bits_legal_T_6) node _source_c_bits_legal_T_8 = eq(_source_c_bits_legal_T_7, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_9 = and(_source_c_bits_legal_T_3, _source_c_bits_legal_T_8) node source_c_bits_legal = or(UInt<1>(0h0), _source_c_bits_legal_T_9) wire source_c_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect source_c_bits_a.opcode, UInt<1>(0h0) connect source_c_bits_a.param, UInt<1>(0h0) connect source_c_bits_a.size, cam_a[0].bits.size connect source_c_bits_a.source, cam_a[0].bits.source connect source_c_bits_a.address, cam_a[0].bits.address invalidate source_c_bits_a.user.amba_prot.fetch invalidate source_c_bits_a.user.amba_prot.secure invalidate source_c_bits_a.user.amba_prot.privileged invalidate source_c_bits_a.user.amba_prot.writealloc invalidate source_c_bits_a.user.amba_prot.readalloc invalidate source_c_bits_a.user.amba_prot.modifiable invalidate source_c_bits_a.user.amba_prot.bufferable node _source_c_bits_a_mask_sizeOH_T = or(cam_a[0].bits.size, UInt<3>(0h0)) node source_c_bits_a_mask_sizeOH_shiftAmount = bits(_source_c_bits_a_mask_sizeOH_T, 1, 0) node _source_c_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), source_c_bits_a_mask_sizeOH_shiftAmount) node _source_c_bits_a_mask_sizeOH_T_2 = bits(_source_c_bits_a_mask_sizeOH_T_1, 2, 0) node source_c_bits_a_mask_sizeOH = or(_source_c_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node source_c_bits_a_mask_sub_sub_sub_0_1 = geq(cam_a[0].bits.size, UInt<2>(0h3)) node source_c_bits_a_mask_sub_sub_size = bits(source_c_bits_a_mask_sizeOH, 2, 2) node source_c_bits_a_mask_sub_sub_bit = bits(cam_a[0].bits.address, 2, 2) node source_c_bits_a_mask_sub_sub_nbit = eq(source_c_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node source_c_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_nbit) node _source_c_bits_a_mask_sub_sub_acc_T = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_0_2) node source_c_bits_a_mask_sub_sub_0_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T) node source_c_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_bit) node _source_c_bits_a_mask_sub_sub_acc_T_1 = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_1_2) node source_c_bits_a_mask_sub_sub_1_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T_1) node source_c_bits_a_mask_sub_size = bits(source_c_bits_a_mask_sizeOH, 1, 1) node source_c_bits_a_mask_sub_bit = bits(cam_a[0].bits.address, 1, 1) node source_c_bits_a_mask_sub_nbit = eq(source_c_bits_a_mask_sub_bit, UInt<1>(0h0)) node source_c_bits_a_mask_sub_0_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_nbit) node _source_c_bits_a_mask_sub_acc_T = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_0_2) node source_c_bits_a_mask_sub_0_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T) node source_c_bits_a_mask_sub_1_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_bit) node _source_c_bits_a_mask_sub_acc_T_1 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_1_2) node source_c_bits_a_mask_sub_1_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T_1) node source_c_bits_a_mask_sub_2_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_nbit) node _source_c_bits_a_mask_sub_acc_T_2 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_2_2) node source_c_bits_a_mask_sub_2_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_2) node source_c_bits_a_mask_sub_3_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_bit) node _source_c_bits_a_mask_sub_acc_T_3 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_3_2) node source_c_bits_a_mask_sub_3_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_3) node source_c_bits_a_mask_size = bits(source_c_bits_a_mask_sizeOH, 0, 0) node source_c_bits_a_mask_bit = bits(cam_a[0].bits.address, 0, 0) node source_c_bits_a_mask_nbit = eq(source_c_bits_a_mask_bit, UInt<1>(0h0)) node source_c_bits_a_mask_eq = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq) node source_c_bits_a_mask_acc = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T) node source_c_bits_a_mask_eq_1 = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_1 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_1) node source_c_bits_a_mask_acc_1 = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T_1) node source_c_bits_a_mask_eq_2 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T_2 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_2) node source_c_bits_a_mask_acc_2 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_2) node source_c_bits_a_mask_eq_3 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_3 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_3) node source_c_bits_a_mask_acc_3 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_3) node source_c_bits_a_mask_eq_4 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T_4 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_4) node source_c_bits_a_mask_acc_4 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_4) node source_c_bits_a_mask_eq_5 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_5 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_5) node source_c_bits_a_mask_acc_5 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_5) node source_c_bits_a_mask_eq_6 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T_6 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_6) node source_c_bits_a_mask_acc_6 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_6) node source_c_bits_a_mask_eq_7 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_7 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_7) node source_c_bits_a_mask_acc_7 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_7) node source_c_bits_a_mask_lo_lo = cat(source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc) node source_c_bits_a_mask_lo_hi = cat(source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2) node source_c_bits_a_mask_lo = cat(source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo) node source_c_bits_a_mask_hi_lo = cat(source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4) node source_c_bits_a_mask_hi_hi = cat(source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6) node source_c_bits_a_mask_hi = cat(source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo) node _source_c_bits_a_mask_T = cat(source_c_bits_a_mask_hi, source_c_bits_a_mask_lo) connect source_c_bits_a.mask, _source_c_bits_a_mask_T connect source_c_bits_a.data, amo_data connect source_c_bits_a.corrupt, _source_c_bits_T connect source_c.bits, source_c_bits_a connect source_c.bits.user.amba_prot.fetch, cam_a[0].bits.user.amba_prot.fetch connect source_c.bits.user.amba_prot.secure, cam_a[0].bits.user.amba_prot.secure connect source_c.bits.user.amba_prot.privileged, cam_a[0].bits.user.amba_prot.privileged connect source_c.bits.user.amba_prot.writealloc, cam_a[0].bits.user.amba_prot.writealloc connect source_c.bits.user.amba_prot.readalloc, cam_a[0].bits.user.amba_prot.readalloc connect source_c.bits.user.amba_prot.modifiable, cam_a[0].bits.user.amba_prot.modifiable connect source_c.bits.user.amba_prot.bufferable, cam_a[0].bits.user.amba_prot.bufferable node _decode_T = dshl(UInt<6>(0h3f), nodeIn.a.bits.size) node _decode_T_1 = bits(_decode_T, 5, 0) node _decode_T_2 = not(_decode_T_1) node decode = shr(_decode_T_2, 3) node _opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node opdata = eq(_opdata_T, UInt<1>(0h0)) node _T_1 = mux(opdata, decode, UInt<1>(0h0)) regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, nodeOut.a.ready) node _readys_T = cat(source_i.valid, source_c.valid) node _readys_T_1 = shl(_readys_T, 1) node _readys_T_2 = bits(_readys_T_1, 1, 0) node _readys_T_3 = or(_readys_T, _readys_T_2) node _readys_T_4 = bits(_readys_T_3, 1, 0) node _readys_T_5 = shl(_readys_T_4, 1) node _readys_T_6 = bits(_readys_T_5, 1, 0) node _readys_T_7 = not(_readys_T_6) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], source_c.valid) node _winner_T_1 = and(readys[1], source_i.valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_3 = eq(winner[0], UInt<1>(0h0)) node _T_4 = or(_T_2, _T_3) node _T_5 = eq(prefixOR_1, UInt<1>(0h0)) node _T_6 = eq(winner[1], UInt<1>(0h0)) node _T_7 = or(_T_5, _T_6) node _T_8 = and(_T_4, _T_7) node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : node _T_11 = eq(_T_8, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf assert(clock, _T_8, UInt<1>(0h1), "") : assert node _T_12 = or(source_c.valid, source_i.valid) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = or(winner[0], winner[1]) node _T_15 = or(_T_13, _T_14) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_1 assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], UInt<1>(0h0), UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], _T_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _source_c_ready_T = and(nodeOut.a.ready, allowed[0]) connect source_c.ready, _source_c_ready_T node _source_i_ready_T = and(nodeOut.a.ready, allowed[1]) connect source_i.ready, _source_i_ready_T node _nodeOut_a_valid_T = or(source_c.valid, source_i.valid) node _nodeOut_a_valid_T_1 = mux(state[0], source_c.valid, UInt<1>(0h0)) node _nodeOut_a_valid_T_2 = mux(state[1], source_i.valid, UInt<1>(0h0)) node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2) wire _nodeOut_a_valid_WIRE : UInt<1> connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3 node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE) connect nodeOut.a.valid, _nodeOut_a_valid_T_4 wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _nodeOut_a_bits_T = mux(muxState[0], source_c.bits.corrupt, UInt<1>(0h0)) node _nodeOut_a_bits_T_1 = mux(muxState[1], source_i.bits.corrupt, UInt<1>(0h0)) node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1) wire _nodeOut_a_bits_WIRE_1 : UInt<1> connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2 connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1 node _nodeOut_a_bits_T_3 = mux(muxState[0], source_c.bits.data, UInt<1>(0h0)) node _nodeOut_a_bits_T_4 = mux(muxState[1], source_i.bits.data, UInt<1>(0h0)) node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4) wire _nodeOut_a_bits_WIRE_2 : UInt<64> connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5 connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2 node _nodeOut_a_bits_T_6 = mux(muxState[0], source_c.bits.mask, UInt<1>(0h0)) node _nodeOut_a_bits_T_7 = mux(muxState[1], source_i.bits.mask, UInt<1>(0h0)) node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7) wire _nodeOut_a_bits_WIRE_3 : UInt<8> connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8 connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3 wire _nodeOut_a_bits_WIRE_4 : { } connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4 wire _nodeOut_a_bits_WIRE_5 : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}} wire _nodeOut_a_bits_WIRE_6 : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>} node _nodeOut_a_bits_T_9 = mux(muxState[0], source_c.bits.user.amba_prot.fetch, UInt<1>(0h0)) node _nodeOut_a_bits_T_10 = mux(muxState[1], source_i.bits.user.amba_prot.fetch, UInt<1>(0h0)) node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10) wire _nodeOut_a_bits_WIRE_7 : UInt<1> connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_11 connect _nodeOut_a_bits_WIRE_6.fetch, _nodeOut_a_bits_WIRE_7 node _nodeOut_a_bits_T_12 = mux(muxState[0], source_c.bits.user.amba_prot.secure, UInt<1>(0h0)) node _nodeOut_a_bits_T_13 = mux(muxState[1], source_i.bits.user.amba_prot.secure, UInt<1>(0h0)) node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13) wire _nodeOut_a_bits_WIRE_8 : UInt<1> connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_14 connect _nodeOut_a_bits_WIRE_6.secure, _nodeOut_a_bits_WIRE_8 node _nodeOut_a_bits_T_15 = mux(muxState[0], source_c.bits.user.amba_prot.privileged, UInt<1>(0h0)) node _nodeOut_a_bits_T_16 = mux(muxState[1], source_i.bits.user.amba_prot.privileged, UInt<1>(0h0)) node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16) wire _nodeOut_a_bits_WIRE_9 : UInt<1> connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_17 connect _nodeOut_a_bits_WIRE_6.privileged, _nodeOut_a_bits_WIRE_9 node _nodeOut_a_bits_T_18 = mux(muxState[0], source_c.bits.user.amba_prot.writealloc, UInt<1>(0h0)) node _nodeOut_a_bits_T_19 = mux(muxState[1], source_i.bits.user.amba_prot.writealloc, UInt<1>(0h0)) node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19) wire _nodeOut_a_bits_WIRE_10 : UInt<1> connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_20 connect _nodeOut_a_bits_WIRE_6.writealloc, _nodeOut_a_bits_WIRE_10 node _nodeOut_a_bits_T_21 = mux(muxState[0], source_c.bits.user.amba_prot.readalloc, UInt<1>(0h0)) node _nodeOut_a_bits_T_22 = mux(muxState[1], source_i.bits.user.amba_prot.readalloc, UInt<1>(0h0)) node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22) wire _nodeOut_a_bits_WIRE_11 : UInt<1> connect _nodeOut_a_bits_WIRE_11, _nodeOut_a_bits_T_23 connect _nodeOut_a_bits_WIRE_6.readalloc, _nodeOut_a_bits_WIRE_11 node _nodeOut_a_bits_T_24 = mux(muxState[0], source_c.bits.user.amba_prot.modifiable, UInt<1>(0h0)) node _nodeOut_a_bits_T_25 = mux(muxState[1], source_i.bits.user.amba_prot.modifiable, UInt<1>(0h0)) node _nodeOut_a_bits_T_26 = or(_nodeOut_a_bits_T_24, _nodeOut_a_bits_T_25) wire _nodeOut_a_bits_WIRE_12 : UInt<1> connect _nodeOut_a_bits_WIRE_12, _nodeOut_a_bits_T_26 connect _nodeOut_a_bits_WIRE_6.modifiable, _nodeOut_a_bits_WIRE_12 node _nodeOut_a_bits_T_27 = mux(muxState[0], source_c.bits.user.amba_prot.bufferable, UInt<1>(0h0)) node _nodeOut_a_bits_T_28 = mux(muxState[1], source_i.bits.user.amba_prot.bufferable, UInt<1>(0h0)) node _nodeOut_a_bits_T_29 = or(_nodeOut_a_bits_T_27, _nodeOut_a_bits_T_28) wire _nodeOut_a_bits_WIRE_13 : UInt<1> connect _nodeOut_a_bits_WIRE_13, _nodeOut_a_bits_T_29 connect _nodeOut_a_bits_WIRE_6.bufferable, _nodeOut_a_bits_WIRE_13 connect _nodeOut_a_bits_WIRE_5.amba_prot, _nodeOut_a_bits_WIRE_6 connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5 node _nodeOut_a_bits_T_30 = mux(muxState[0], source_c.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_T_31 = mux(muxState[1], source_i.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_T_32 = or(_nodeOut_a_bits_T_30, _nodeOut_a_bits_T_31) wire _nodeOut_a_bits_WIRE_14 : UInt<29> connect _nodeOut_a_bits_WIRE_14, _nodeOut_a_bits_T_32 connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_14 node _nodeOut_a_bits_T_33 = mux(muxState[0], source_c.bits.source, UInt<1>(0h0)) node _nodeOut_a_bits_T_34 = mux(muxState[1], source_i.bits.source, UInt<1>(0h0)) node _nodeOut_a_bits_T_35 = or(_nodeOut_a_bits_T_33, _nodeOut_a_bits_T_34) wire _nodeOut_a_bits_WIRE_15 : UInt<7> connect _nodeOut_a_bits_WIRE_15, _nodeOut_a_bits_T_35 connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_15 node _nodeOut_a_bits_T_36 = mux(muxState[0], source_c.bits.size, UInt<1>(0h0)) node _nodeOut_a_bits_T_37 = mux(muxState[1], source_i.bits.size, UInt<1>(0h0)) node _nodeOut_a_bits_T_38 = or(_nodeOut_a_bits_T_36, _nodeOut_a_bits_T_37) wire _nodeOut_a_bits_WIRE_16 : UInt<3> connect _nodeOut_a_bits_WIRE_16, _nodeOut_a_bits_T_38 connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_16 node _nodeOut_a_bits_T_39 = mux(muxState[0], source_c.bits.param, UInt<1>(0h0)) node _nodeOut_a_bits_T_40 = mux(muxState[1], source_i.bits.param, UInt<1>(0h0)) node _nodeOut_a_bits_T_41 = or(_nodeOut_a_bits_T_39, _nodeOut_a_bits_T_40) wire _nodeOut_a_bits_WIRE_17 : UInt<3> connect _nodeOut_a_bits_WIRE_17, _nodeOut_a_bits_T_41 connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_17 node _nodeOut_a_bits_T_42 = mux(muxState[0], source_c.bits.opcode, UInt<1>(0h0)) node _nodeOut_a_bits_T_43 = mux(muxState[1], source_i.bits.opcode, UInt<1>(0h0)) node _nodeOut_a_bits_T_44 = or(_nodeOut_a_bits_T_42, _nodeOut_a_bits_T_43) wire _nodeOut_a_bits_WIRE_18 : UInt<3> connect _nodeOut_a_bits_WIRE_18, _nodeOut_a_bits_T_44 connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_18 connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask connect nodeOut.a.bits.user.amba_prot.fetch, _nodeOut_a_bits_WIRE.user.amba_prot.fetch connect nodeOut.a.bits.user.amba_prot.secure, _nodeOut_a_bits_WIRE.user.amba_prot.secure connect nodeOut.a.bits.user.amba_prot.privileged, _nodeOut_a_bits_WIRE.user.amba_prot.privileged connect nodeOut.a.bits.user.amba_prot.writealloc, _nodeOut_a_bits_WIRE.user.amba_prot.writealloc connect nodeOut.a.bits.user.amba_prot.readalloc, _nodeOut_a_bits_WIRE.user.amba_prot.readalloc connect nodeOut.a.bits.user.amba_prot.modifiable, _nodeOut_a_bits_WIRE.user.amba_prot.modifiable connect nodeOut.a.bits.user.amba_prot.bufferable, _nodeOut_a_bits_WIRE.user.amba_prot.bufferable connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode node _T_19 = and(source_i.ready, source_i.valid) node _T_20 = eq(a_isSupported, UInt<1>(0h0)) node _T_21 = and(_T_19, _T_20) when _T_21 : when a_cam_sel_free_0 : connect cam_a[0].fifoId, UInt<1>(0h0) connect cam_a[0].bits.corrupt, nodeIn.a.bits.corrupt connect cam_a[0].bits.data, nodeIn.a.bits.data connect cam_a[0].bits.mask, nodeIn.a.bits.mask connect cam_a[0].bits.user, nodeIn.a.bits.user connect cam_a[0].bits.address, nodeIn.a.bits.address connect cam_a[0].bits.source, nodeIn.a.bits.source connect cam_a[0].bits.size, nodeIn.a.bits.size connect cam_a[0].bits.param, nodeIn.a.bits.param connect cam_a[0].bits.opcode, nodeIn.a.bits.opcode node _cam_a_0_lut_T = bits(nodeIn.a.bits.param, 1, 0) node _cam_a_0_lut_T_1 = eq(UInt<3>(0h1), _cam_a_0_lut_T) node _cam_a_0_lut_T_2 = mux(_cam_a_0_lut_T_1, UInt<4>(0he), UInt<4>(0h8)) node _cam_a_0_lut_T_3 = eq(UInt<3>(0h0), _cam_a_0_lut_T) node _cam_a_0_lut_T_4 = mux(_cam_a_0_lut_T_3, UInt<3>(0h6), _cam_a_0_lut_T_2) node _cam_a_0_lut_T_5 = eq(UInt<3>(0h3), _cam_a_0_lut_T) node _cam_a_0_lut_T_6 = mux(_cam_a_0_lut_T_5, UInt<4>(0hc), _cam_a_0_lut_T_4) connect cam_a[0].lut, _cam_a_0_lut_T_6 when a_cam_sel_free_0 : connect cam_s[0].state, UInt<2>(0h3) node _T_22 = and(source_c.ready, source_c.valid) when _T_22 : when a_cam_sel_put_0 : connect cam_s[0].state, UInt<1>(0h1) node _d_first_T = and(nodeOut.d.ready, nodeOut.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), nodeOut.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T node d_cam_sel_raw_0 = eq(cam_a[0].bits.source, nodeIn.d.bits.source) node d_cam_sel_match_0 = and(d_cam_sel_raw_0, cam_dmatch_0) node d_cam_sel_0 = mux(UInt<1>(0h0), a_cam_sel_free_0, d_cam_sel_match_0) node d_cam_sel_any = or(UInt<1>(0h0), d_cam_sel_match_0) node d_ackd = eq(nodeOut.d.bits.opcode, UInt<1>(0h1)) node d_ack = eq(nodeOut.d.bits.opcode, UInt<1>(0h0)) node _T_23 = and(nodeOut.d.ready, nodeOut.d.valid) node _T_24 = and(_T_23, d_first) when _T_24 : node _T_25 = and(d_cam_sel_0, d_ackd) when _T_25 : connect cam_d[0].data, nodeOut.d.bits.data connect cam_d[0].denied, nodeOut.d.bits.denied connect cam_d[0].corrupt, nodeOut.d.bits.corrupt when d_cam_sel_0 : node _cam_s_0_state_T = mux(d_ackd, UInt<2>(0h2), UInt<1>(0h0)) connect cam_s[0].state, _cam_s_0_state_T node _d_drop_T = and(d_first, d_ackd) node d_drop = and(_d_drop_T, d_cam_sel_any) node _d_replace_T = and(d_first, d_ack) node d_replace = and(_d_replace_T, d_cam_sel_match_0) node _nodeIn_d_valid_T = eq(d_drop, UInt<1>(0h0)) node _nodeIn_d_valid_T_1 = and(nodeOut.d.valid, _nodeIn_d_valid_T) connect nodeIn.d.valid, _nodeIn_d_valid_T_1 node _nodeOut_d_ready_T = or(nodeIn.d.ready, d_drop) connect nodeOut.d.ready, _nodeOut_d_ready_T connect nodeIn.d.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn.d.bits.data, nodeOut.d.bits.data connect nodeIn.d.bits.denied, nodeOut.d.bits.denied connect nodeIn.d.bits.sink, nodeOut.d.bits.sink connect nodeIn.d.bits.source, nodeOut.d.bits.source connect nodeIn.d.bits.size, nodeOut.d.bits.size connect nodeIn.d.bits.param, nodeOut.d.bits.param connect nodeIn.d.bits.opcode, nodeOut.d.bits.opcode when d_replace : connect nodeIn.d.bits.opcode, UInt<1>(0h1) connect nodeIn.d.bits.data, cam_d[0].data node _nodeIn_d_bits_corrupt_T = or(cam_d[0].corrupt, nodeOut.d.bits.denied) connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_corrupt_T node _nodeIn_d_bits_denied_T = or(cam_d[0].denied, nodeOut.d.bits.denied) connect nodeIn.d.bits.denied, _nodeIn_d_bits_denied_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_10 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_11 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLAtomicAutomata_pbus( // @[AtomicAutomata.scala:36:9] input clock, // @[AtomicAutomata.scala:36:9] input reset, // @[AtomicAutomata.scala:36:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire source_i_ready; // @[Arbiter.scala:94:31] reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28] reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24] reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24] reg [2:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24] reg [6:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24] reg [28:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_user_amba_prot_bufferable; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_user_amba_prot_modifiable; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_user_amba_prot_readalloc; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_user_amba_prot_writealloc; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_user_amba_prot_privileged; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_user_amba_prot_secure; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_user_amba_prot_fetch; // @[AtomicAutomata.scala:83:24] reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24] reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24] reg cam_d_0_denied; // @[AtomicAutomata.scala:84:24] reg cam_d_0_corrupt; // @[AtomicAutomata.scala:84:24] wire cam_free_0 = cam_s_0_state == 2'h0; // @[AtomicAutomata.scala:82:28, :86:44] wire winner_0 = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44] wire a_isSupported = auto_in_a_bits_opcode != 3'h3 & auto_in_a_bits_opcode != 3'h2; // @[AtomicAutomata.scala:36:9, :95:45, :96:47, :97:47, :98:{32,63}] wire [3:0] _logic_out_T = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[0], cam_d_0_data[0]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_2 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[1], cam_d_0_data[1]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_4 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[2], cam_d_0_data[2]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_6 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[3], cam_d_0_data[3]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_8 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[4], cam_d_0_data[4]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_10 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[5], cam_d_0_data[5]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_12 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[6], cam_d_0_data[6]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_14 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[7], cam_d_0_data[7]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_16 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[8], cam_d_0_data[8]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_18 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[9], cam_d_0_data[9]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_20 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[10], cam_d_0_data[10]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_22 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[11], cam_d_0_data[11]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_24 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[12], cam_d_0_data[12]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_26 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[13], cam_d_0_data[13]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_28 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[14], cam_d_0_data[14]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_30 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[15], cam_d_0_data[15]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_32 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[16], cam_d_0_data[16]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_34 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[17], cam_d_0_data[17]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_36 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[18], cam_d_0_data[18]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_38 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[19], cam_d_0_data[19]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_40 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[20], cam_d_0_data[20]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_42 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[21], cam_d_0_data[21]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_44 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[22], cam_d_0_data[22]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_46 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[23], cam_d_0_data[23]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_48 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[24], cam_d_0_data[24]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_50 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[25], cam_d_0_data[25]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_52 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[26], cam_d_0_data[26]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_54 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[27], cam_d_0_data[27]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_56 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[28], cam_d_0_data[28]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_58 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[29], cam_d_0_data[29]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_60 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[30], cam_d_0_data[30]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_62 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[31], cam_d_0_data[31]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_64 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[32], cam_d_0_data[32]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_66 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[33], cam_d_0_data[33]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_68 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[34], cam_d_0_data[34]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_70 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[35], cam_d_0_data[35]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_72 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[36], cam_d_0_data[36]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_74 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[37], cam_d_0_data[37]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_76 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[38], cam_d_0_data[38]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_78 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[39], cam_d_0_data[39]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_80 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[40], cam_d_0_data[40]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_82 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[41], cam_d_0_data[41]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_84 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[42], cam_d_0_data[42]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_86 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[43], cam_d_0_data[43]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_88 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[44], cam_d_0_data[44]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_90 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[45], cam_d_0_data[45]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_92 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[46], cam_d_0_data[46]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_94 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[47], cam_d_0_data[47]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_96 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[48], cam_d_0_data[48]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_98 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[49], cam_d_0_data[49]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_100 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[50], cam_d_0_data[50]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_102 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[51], cam_d_0_data[51]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_104 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[52], cam_d_0_data[52]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_106 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[53], cam_d_0_data[53]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_108 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[54], cam_d_0_data[54]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_110 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[55], cam_d_0_data[55]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_112 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[56], cam_d_0_data[56]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_114 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[57], cam_d_0_data[57]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_116 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[58], cam_d_0_data[58]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_118 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[59], cam_d_0_data[59]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_120 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[60], cam_d_0_data[60]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_122 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[61], cam_d_0_data[61]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_124 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[62], cam_d_0_data[62]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_126 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[63], cam_d_0_data[63]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [6:0] _GEN = ~(cam_a_0_bits_mask[6:0]) \| cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:{25,31,39}] wire [6:0] _signbit_a_T = {cam_a_0_bits_data[55], cam_a_0_bits_data[47], cam_a_0_bits_data[39], cam_a_0_bits_data[31], cam_a_0_bits_data[23], cam_a_0_bits_data[15], cam_a_0_bits_data[7]} & ~_GEN; // @[AtomicAutomata.scala:83:24, :119:63, :127:{23,31}, :128:29, :131:38] wire [6:0] _signbit_d_T = {cam_d_0_data[55], cam_d_0_data[47], cam_d_0_data[39], cam_d_0_data[31], cam_d_0_data[23], cam_d_0_data[15], cam_d_0_data[7]} & ~_GEN; // @[AtomicAutomata.scala:84:24, :119:73, :127:{23,31}, :129:29, :132:38] wire [5:0] _GEN_0 = _signbit_a_T[6:1] \| _signbit_a_T[5:0]; // @[package.scala:253:{43,53}] wire [3:0] _GEN_1 = _GEN_0[5:2] \| _GEN_0[3:0]; // @[package.scala:253:{43,53}] wire _signext_a_T_13 = _GEN_0[1] \| _signbit_a_T[0]; // @[package.scala:253:43] wire [5:0] _GEN_2 = _signbit_d_T[6:1] \| _signbit_d_T[5:0]; // @[package.scala:253:{43,53}] wire [3:0] _GEN_3 = _GEN_2[5:2] \| _GEN_2[3:0]; // @[package.scala:253:{43,53}] wire _signext_d_T_13 = _GEN_2[1] \| _signbit_d_T[0]; // @[package.scala:253:43] wire [63:0] wide_mask = {{8{cam_a_0_bits_mask[7]}}, {8{cam_a_0_bits_mask[6]}}, {8{cam_a_0_bits_mask[5]}}, {8{cam_a_0_bits_mask[4]}}, {8{cam_a_0_bits_mask[3]}}, {8{cam_a_0_bits_mask[2]}}, {8{cam_a_0_bits_mask[1]}}, {8{cam_a_0_bits_mask[0]}}}; // @[AtomicAutomata.scala:83:24, :136:40] wire [63:0] a_a_ext = cam_a_0_bits_data & wide_mask \| {{8{_GEN_1[3] \| _signext_a_T_13}}, {8{_GEN_1[2] \| _GEN_0[0]}}, {8{_GEN_1[1] \| _signbit_a_T[0]}}, {8{_GEN_1[0]}}, {8{_signext_a_T_13}}, {8{_GEN_0[0]}}, {8{_signbit_a_T[0]}}, 8'h0}; // @[package.scala:253:43] wire [63:0] a_d_ext = cam_d_0_data & wide_mask \| {{8{_GEN_3[3] \| _signext_d_T_13}}, {8{_GEN_3[2] \| _GEN_2[0]}}, {8{_GEN_3[1] \| _signbit_d_T[0]}}, {8{_GEN_3[0]}}, {8{_signext_d_T_13}}, {8{_GEN_2[0]}}, {8{_signbit_d_T[0]}}, 8'h0}; // @[package.scala:253:43] wire [63:0] _adder_out_T = a_a_ext + ({64{~(cam_a_0_bits_param[2])}} ^ a_d_ext); // @[AtomicAutomata.scala:83:24, :125:39, :137:41, :138:41, :139:26, :140:33] wire a_allow = ~((&cam_s_0_state) \| winner_0) & (a_isSupported \| cam_free_0); // @[AtomicAutomata.scala:82:28, :86:44, :87:44, :88:{49,57}, :98:32, :155:{23,35,53}] wire nodeIn_a_ready = source_i_ready & a_allow; // @[AtomicAutomata.scala:155:35, :156:38] wire source_i_valid = auto_in_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38] wire source_c_bits_a_mask_sub_sub_sub_0_1 = cam_a_0_bits_size > 3'h2; // @[Misc.scala:206:21] wire source_c_bits_a_mask_sub_sub_size = cam_a_0_bits_size[1:0] == 2'h2; // @[OneHot.scala:64:49] wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 \| source_c_bits_a_mask_sub_sub_size & ~(cam_a_0_bits_address[2]); // @[Misc.scala:206:21, :209:26, :210:26, :211:20, :215:{29,38}] wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 \| source_c_bits_a_mask_sub_sub_size & cam_a_0_bits_address[2]; // @[Misc.scala:206:21, :209:26, :210:26, :215:{29,38}] wire source_c_bits_a_mask_sub_size = cam_a_0_bits_size[1:0] == 2'h1; // @[OneHot.scala:64:49] wire source_c_bits_a_mask_sub_0_2 = ~(cam_a_0_bits_address[2]) & ~(cam_a_0_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27] wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 \| source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire source_c_bits_a_mask_sub_1_2 = ~(cam_a_0_bits_address[2]) & cam_a_0_bits_address[1]; // @[Misc.scala:210:26, :211:20, :214:27] wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 \| source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire source_c_bits_a_mask_sub_2_2 = cam_a_0_bits_address[2] & ~(cam_a_0_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27] wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 \| source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire source_c_bits_a_mask_sub_3_2 = cam_a_0_bits_address[2] & cam_a_0_bits_address[1]; // @[Misc.scala:210:26, :214:27] wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 \| source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[AtomicAutomata.scala:36:9] wire winner_1 = ~winner_0 & source_i_valid; // @[AtomicAutomata.scala:87:44, :157:38] wire _nodeOut_a_valid_T = winner_0 \| source_i_valid; // @[AtomicAutomata.scala:87:44, :157:38]
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s4k3z4c_1 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_17 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s4k3z4c connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s4k3z4c connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready inst nodeIn_b_q of Queue2_TLBundleB_a32d64s4k3z4c connect nodeIn_b_q.clock, clock connect nodeIn_b_q.reset, reset connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready inst nodeOut_c_q of Queue2_TLBundleC_a32d64s4k3z4c connect nodeOut_c_q.clock, clock connect nodeOut_c_q.reset, reset connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready inst nodeOut_e_q of Queue2_TLBundleE_a32d64s4k3z4c connect nodeOut_e_q.clock, clock connect nodeOut_e_q.reset, reset connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready	module TLBuffer_a32d64s4k3z4c_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9] wire [63:0] auto_out_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_17 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s4k3z4c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s4k3z4c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d64s4k3z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d64s4k3z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d64s4k3z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_MasterXbar_BoomTile_i2_o1_a32d64s3k3z4c_1 : input clock : Clock input reset : Reset output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate anonIn.e.bits.sink invalidate anonIn.e.valid invalidate anonIn.e.ready invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.c.bits.corrupt invalidate anonIn.c.bits.data invalidate anonIn.c.bits.address invalidate anonIn.c.bits.source invalidate anonIn.c.bits.size invalidate anonIn.c.bits.param invalidate anonIn.c.bits.opcode invalidate anonIn.c.valid invalidate anonIn.c.ready invalidate anonIn.b.bits.corrupt invalidate anonIn.b.bits.data invalidate anonIn.b.bits.mask invalidate anonIn.b.bits.address invalidate anonIn.b.bits.source invalidate anonIn.b.bits.size invalidate anonIn.b.bits.param invalidate anonIn.b.bits.opcode invalidate anonIn.b.valid invalidate anonIn.b.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn_1.d.bits.corrupt invalidate anonIn_1.d.bits.data invalidate anonIn_1.d.bits.denied invalidate anonIn_1.d.bits.sink invalidate anonIn_1.d.bits.source invalidate anonIn_1.d.bits.size invalidate anonIn_1.d.bits.param invalidate anonIn_1.d.bits.opcode invalidate anonIn_1.d.valid invalidate anonIn_1.d.ready invalidate anonIn_1.a.bits.corrupt invalidate anonIn_1.a.bits.data invalidate anonIn_1.a.bits.mask invalidate anonIn_1.a.bits.address invalidate anonIn_1.a.bits.source invalidate anonIn_1.a.bits.size invalidate anonIn_1.a.bits.param invalidate anonIn_1.a.bits.opcode invalidate anonIn_1.a.valid invalidate anonIn_1.a.ready inst monitor of TLMonitor_42 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, anonIn.e.bits.sink connect monitor.io.in.e.valid, anonIn.e.valid connect monitor.io.in.e.ready, anonIn.e.ready connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.c.bits.corrupt, anonIn.c.bits.corrupt connect monitor.io.in.c.bits.data, anonIn.c.bits.data connect monitor.io.in.c.bits.address, anonIn.c.bits.address connect monitor.io.in.c.bits.source, anonIn.c.bits.source connect monitor.io.in.c.bits.size, anonIn.c.bits.size connect monitor.io.in.c.bits.param, anonIn.c.bits.param connect monitor.io.in.c.bits.opcode, anonIn.c.bits.opcode connect monitor.io.in.c.valid, anonIn.c.valid connect monitor.io.in.c.ready, anonIn.c.ready connect monitor.io.in.b.bits.corrupt, anonIn.b.bits.corrupt connect monitor.io.in.b.bits.data, anonIn.b.bits.data connect monitor.io.in.b.bits.mask, anonIn.b.bits.mask connect monitor.io.in.b.bits.address, anonIn.b.bits.address connect monitor.io.in.b.bits.source, anonIn.b.bits.source connect monitor.io.in.b.bits.size, anonIn.b.bits.size connect monitor.io.in.b.bits.param, anonIn.b.bits.param connect monitor.io.in.b.bits.opcode, anonIn.b.bits.opcode connect monitor.io.in.b.valid, anonIn.b.valid connect monitor.io.in.b.ready, anonIn.b.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready inst monitor_1 of TLMonitor_43 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, anonIn_1.d.valid connect monitor_1.io.in.d.ready, anonIn_1.d.ready connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, anonIn_1.a.valid connect monitor_1.io.in.a.ready, anonIn_1.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate anonOut.e.bits.sink invalidate anonOut.e.valid invalidate anonOut.e.ready invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.c.bits.corrupt invalidate anonOut.c.bits.data invalidate anonOut.c.bits.address invalidate anonOut.c.bits.source invalidate anonOut.c.bits.size invalidate anonOut.c.bits.param invalidate anonOut.c.bits.opcode invalidate anonOut.c.valid invalidate anonOut.c.ready invalidate anonOut.b.bits.corrupt invalidate anonOut.b.bits.data invalidate anonOut.b.bits.mask invalidate anonOut.b.bits.address invalidate anonOut.b.bits.source invalidate anonOut.b.bits.size invalidate anonOut.b.bits.param invalidate anonOut.b.bits.opcode invalidate anonOut.b.valid invalidate anonOut.b.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[2] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T connect anonIn.b.bits.corrupt, in[0].b.bits.corrupt connect anonIn.b.bits.data, in[0].b.bits.data connect anonIn.b.bits.mask, in[0].b.bits.mask connect anonIn.b.bits.address, in[0].b.bits.address connect anonIn.b.bits.source, in[0].b.bits.source connect anonIn.b.bits.size, in[0].b.bits.size connect anonIn.b.bits.param, in[0].b.bits.param connect anonIn.b.bits.opcode, in[0].b.bits.opcode connect anonIn.b.valid, in[0].b.valid connect in[0].b.ready, anonIn.b.ready node _anonIn_b_bits_source_T = bits(in[0].b.bits.source, 1, 0) connect anonIn.b.bits.source, _anonIn_b_bits_source_T connect in[0].c.bits.corrupt, anonIn.c.bits.corrupt connect in[0].c.bits.data, anonIn.c.bits.data connect in[0].c.bits.address, anonIn.c.bits.address connect in[0].c.bits.source, anonIn.c.bits.source connect in[0].c.bits.size, anonIn.c.bits.size connect in[0].c.bits.param, anonIn.c.bits.param connect in[0].c.bits.opcode, anonIn.c.bits.opcode connect in[0].c.valid, anonIn.c.valid connect anonIn.c.ready, in[0].c.ready node _in_0_c_bits_source_T = or(anonIn.c.bits.source, UInt<1>(0h0)) connect in[0].c.bits.source, _in_0_c_bits_source_T connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 1, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T connect in[0].e.bits.sink, anonIn.e.bits.sink connect in[0].e.valid, anonIn.e.valid connect anonIn.e.ready, in[0].e.ready connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt connect in[1].a.bits.data, anonIn_1.a.bits.data connect in[1].a.bits.mask, anonIn_1.a.bits.mask connect in[1].a.bits.address, anonIn_1.a.bits.address connect in[1].a.bits.source, anonIn_1.a.bits.source connect in[1].a.bits.size, anonIn_1.a.bits.size connect in[1].a.bits.param, anonIn_1.a.bits.param connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode connect in[1].a.valid, anonIn_1.a.valid connect anonIn_1.a.ready, in[1].a.ready node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<3>(0h4)) connect in[1].a.bits.source, _in_1_a_bits_source_T invalidate in[1].b.bits.corrupt invalidate in[1].b.bits.data invalidate in[1].b.bits.mask invalidate in[1].b.bits.address invalidate in[1].b.bits.source invalidate in[1].b.bits.size invalidate in[1].b.bits.param invalidate in[1].b.bits.opcode invalidate in[1].b.valid invalidate in[1].b.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready connect in[1].b.ready, UInt<1>(0h1) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) invalidate in[1].c.bits.corrupt invalidate in[1].c.bits.data invalidate in[1].c.bits.address invalidate in[1].c.bits.source invalidate in[1].c.bits.size invalidate in[1].c.bits.param invalidate in[1].c.bits.opcode invalidate in[1].c.valid invalidate in[1].c.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<1>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<3>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready invalidate _WIRE_5.bits.corrupt invalidate _WIRE_5.bits.data invalidate _WIRE_5.bits.address invalidate _WIRE_5.bits.source invalidate _WIRE_5.bits.size invalidate _WIRE_5.bits.param invalidate _WIRE_5.bits.opcode invalidate _WIRE_5.valid invalidate _WIRE_5.ready connect in[1].c.valid, UInt<1>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt connect anonIn_1.d.bits.data, in[1].d.bits.data connect anonIn_1.d.bits.denied, in[1].d.bits.denied connect anonIn_1.d.bits.sink, in[1].d.bits.sink connect anonIn_1.d.bits.source, in[1].d.bits.source connect anonIn_1.d.bits.size, in[1].d.bits.size connect anonIn_1.d.bits.param, in[1].d.bits.param connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode connect anonIn_1.d.valid, in[1].d.valid connect in[1].d.ready, anonIn_1.d.ready connect anonIn_1.d.bits.source, UInt<1>(0h0) invalidate in[1].e.bits.sink invalidate in[1].e.valid invalidate in[1].e.ready wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_8.bits.sink, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.sink invalidate _WIRE_9.valid invalidate _WIRE_9.ready connect in[1].e.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[1] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready connect out[0].b.bits.corrupt, anonOut.b.bits.corrupt connect out[0].b.bits.data, anonOut.b.bits.data connect out[0].b.bits.mask, anonOut.b.bits.mask connect out[0].b.bits.address, anonOut.b.bits.address connect out[0].b.bits.source, anonOut.b.bits.source connect out[0].b.bits.size, anonOut.b.bits.size connect out[0].b.bits.param, anonOut.b.bits.param connect out[0].b.bits.opcode, anonOut.b.bits.opcode connect out[0].b.valid, anonOut.b.valid connect anonOut.b.ready, out[0].b.ready connect anonOut.c.bits.corrupt, out[0].c.bits.corrupt connect anonOut.c.bits.data, out[0].c.bits.data connect anonOut.c.bits.address, out[0].c.bits.address connect anonOut.c.bits.source, out[0].c.bits.source connect anonOut.c.bits.size, out[0].c.bits.size connect anonOut.c.bits.param, out[0].c.bits.param connect anonOut.c.bits.opcode, out[0].c.bits.opcode connect anonOut.c.valid, out[0].c.valid connect out[0].c.ready, anonOut.c.ready connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T connect anonOut.e.bits.sink, out[0].e.bits.sink connect anonOut.e.valid, out[0].e.valid connect out[0].e.ready, anonOut.e.ready node _anonOut_e_bits_sink_T = bits(out[0].e.bits.sink, 2, 0) connect anonOut.e.bits.sink, _anonOut_e_bits_sink_T node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9) node _requestCIO_T = xor(in[0].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(in[1].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9) node _requestBOI_uncommonBits_T = or(out[0].b.bits.source, UInt<2>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 1, 0) node _requestBOI_T = shr(out[0].b.bits.source, 2) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<2>(0h3)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) node requestBOI_0_1 = eq(out[0].b.bits.source, UInt<3>(0h4)) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<2>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 1, 0) node _requestDOI_T = shr(out[0].d.bits.source, 2) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<2>(0h3)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node requestDOI_0_1 = eq(out[0].d.bits.source, UInt<3>(0h4)) node _requestEIO_uncommonBits_T = or(in[0].e.bits.sink, UInt<3>(0h0)) node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 2, 0) node _requestEIO_T = shr(in[0].e.bits.sink, 3) node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0)) node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits) node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2) node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<3>(0h7)) node requestEIO_0_0 = and(_requestEIO_T_3, _requestEIO_T_4) node _requestEIO_uncommonBits_T_1 = or(in[1].e.bits.sink, UInt<3>(0h0)) node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 2, 0) node _requestEIO_T_5 = shr(in[1].e.bits.sink, 3) node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0)) node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1) node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7) node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<3>(0h7)) node requestEIO_1_0 = and(_requestEIO_T_8, _requestEIO_T_9) node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3) node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) node _beatsBO_decode_T = dshl(UInt<12>(0hfff), out[0].b.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(out[0].b.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) node _beatsCI_decode_T = dshl(UInt<12>(0hfff), in[0].c.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(in[0].c.bits.opcode, 0, 0) node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0)) node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].c.bits.size) node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3) node beatsCI_opdata_1 = bits(in[1].c.bits.opcode, 0, 0) node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect in[0].a.ready, portsAOI_filtered[0].ready wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsAOI_filtered_1[0].bits, in[1].a.bits node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1)) node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 connect in[1].a.ready, portsAOI_filtered_1[0].ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsBIO_filtered[0].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[0].bits.data, out[0].b.bits.data connect portsBIO_filtered[0].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[0].bits.address, out[0].b.bits.address connect portsBIO_filtered[0].bits.source, out[0].b.bits.source connect portsBIO_filtered[0].bits.size, out[0].b.bits.size connect portsBIO_filtered[0].bits.param, out[0].b.bits.param connect portsBIO_filtered[0].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect portsBIO_filtered[1].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[1].bits.data, out[0].b.bits.data connect portsBIO_filtered[1].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[1].bits.address, out[0].b.bits.address connect portsBIO_filtered[1].bits.source, out[0].b.bits.source connect portsBIO_filtered[1].bits.size, out[0].b.bits.size connect portsBIO_filtered[1].bits.param, out[0].b.bits.param connect portsBIO_filtered[1].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_1_valid_T) connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 node _portsBIO_out_0_b_ready_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_2 = or(_portsBIO_out_0_b_ready_T, _portsBIO_out_0_b_ready_T_1) wire _portsBIO_out_0_b_ready_WIRE : UInt<1> connect _portsBIO_out_0_b_ready_WIRE, _portsBIO_out_0_b_ready_T_2 connect out[0].b.ready, _portsBIO_out_0_b_ready_WIRE wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsCOI_filtered[0].bits, in[0].c.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) node _portsCOI_filtered_0_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect in[0].c.ready, portsCOI_filtered[0].ready wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsCOI_filtered_1[0].bits, in[1].c.bits node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1)) node _portsCOI_filtered_0_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_0_valid_T_2) connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 connect in[1].c.ready, portsCOI_filtered_1[0].ready wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[1].bits.data, out[0].d.bits.data connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[1].bits.source, out[0].d.bits.source connect portsDIO_filtered[1].bits.size, out[0].d.bits.size connect portsDIO_filtered[1].bits.param, out[0].d.bits.param connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) wire _portsDIO_out_0_d_ready_WIRE : UInt<1> connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2 connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[1] connect portsEOI_filtered[0].bits, in[0].e.bits node _portsEOI_filtered_0_valid_T = or(requestEIO_0_0, UInt<1>(0h1)) node _portsEOI_filtered_0_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect in[0].e.ready, portsEOI_filtered[0].ready wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[1] connect portsEOI_filtered_1[0].bits, in[1].e.bits node _portsEOI_filtered_0_valid_T_2 = or(requestEIO_1_0, UInt<1>(0h1)) node _portsEOI_filtered_0_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_0_valid_T_2) connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 connect in[1].e.ready, portsEOI_filtered_1[0].ready regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, out[0].a.ready) node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsAOI_filtered[0].valid) node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) connect portsAOI_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2) wire _out_0_a_valid_WIRE : UInt<1> connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3 node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE) connect out[0].a.valid, _out_0_a_valid_T_4 wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) wire _out_0_a_bits_WIRE_1 : UInt<1> connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2 connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4) wire _out_0_a_bits_WIRE_2 : UInt<64> connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5 connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7) wire _out_0_a_bits_WIRE_3 : UInt<8> connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8 connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 wire _out_0_a_bits_WIRE_4 : { } connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 wire _out_0_a_bits_WIRE_5 : { } connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) wire _out_0_a_bits_WIRE_6 : UInt<32> connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11 connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6 node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13) wire _out_0_a_bits_WIRE_7 : UInt<3> connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14 connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7 node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16) wire _out_0_a_bits_WIRE_8 : UInt<4> connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17 connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8 node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) wire _out_0_a_bits_WIRE_9 : UInt<3> connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20 connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9 node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22) wire _out_0_a_bits_WIRE_10 : UInt<3> connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23 connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10 connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt connect out[0].a.bits.data, _out_0_a_bits_WIRE.data connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask connect out[0].a.bits.address, _out_0_a_bits_WIRE.address connect out[0].a.bits.source, _out_0_a_bits_WIRE.source connect out[0].a.bits.size, _out_0_a_bits_WIRE.size connect out[0].a.bits.param, _out_0_a_bits_WIRE.param connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode connect out[0].c, portsCOI_filtered[0] connect out[0].e, portsEOI_filtered[0] connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) connect in[0].b, portsBIO_filtered[0] connect in[0].d, portsDIO_filtered[0] invalidate in[1].b.bits.corrupt invalidate in[1].b.bits.data invalidate in[1].b.bits.mask invalidate in[1].b.bits.address invalidate in[1].b.bits.source invalidate in[1].b.bits.size invalidate in[1].b.bits.param invalidate in[1].b.bits.opcode connect in[1].d, portsDIO_filtered[1] connect portsBIO_filtered[1].ready, UInt<1>(0h0)	module TLXbar_MasterXbar_BoomTile_i2_o1_a32d64s3k3z4c_1( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_0_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire [2:0] out_0_e_bits_sink; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [2:0] in_0_c_bits_source; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_ready_0 = auto_anon_in_0_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_valid_0 = auto_anon_in_0_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_c_bits_opcode_0 = auto_anon_in_0_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_c_bits_param_0 = auto_anon_in_0_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_c_bits_size_0 = auto_anon_in_0_c_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_c_bits_source_0 = auto_anon_in_0_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_c_bits_address_0 = auto_anon_in_0_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_c_bits_data_0 = auto_anon_in_0_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_e_valid_0 = auto_anon_in_0_e_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_e_bits_sink_0 = auto_anon_in_0_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_b_valid_0 = auto_anon_out_b_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_b_bits_opcode_0 = auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_b_bits_param_0 = auto_anon_out_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_b_bits_size_0 = auto_anon_out_b_bits_size; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_b_bits_source_0 = auto_anon_out_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_b_bits_address_0 = auto_anon_out_b_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_b_bits_mask_0 = auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_b_bits_data_0 = auto_anon_out_b_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_b_bits_corrupt_0 = auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_c_ready_0 = auto_anon_out_c_ready; // @[Xbar.scala:74:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_e_ready_0 = auto_anon_out_e_ready; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [2:0] auto_anon_in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = 3'h4; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_source = 3'h4; // @[Xbar.scala:159:18] wire [2:0] _in_1_a_bits_source_T = 3'h4; // @[Xbar.scala:166:55] wire [2:0] portsAOI_filtered_1_0_bits_opcode = 3'h4; // @[Xbar.scala:352:24] wire [2:0] portsAOI_filtered_1_0_bits_source = 3'h4; // @[Xbar.scala:352:24] wire [2:0] auto_anon_in_1_a_bits_param = 3'h0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_b_bits_source = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_source = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_e_bits_sink = 3'h0; // @[Xbar.scala:159:18] wire [2:0] _requestEIO_uncommonBits_T_1 = 3'h0; // @[Parameters.scala:52:29] wire [2:0] requestEIO_uncommonBits_1 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] portsAOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_source = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsEOI_filtered_1_0_bits_sink = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _out_0_a_bits_T_19 = 3'h0; // @[Mux.scala:30:73] wire [3:0] auto_anon_in_1_a_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] in_1_a_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] portsAOI_filtered_1_0_bits_size = 4'h6; // @[Xbar.scala:352:24] wire auto_anon_in_1_a_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_b_valid = 1'h0; // @[Xbar.scala:159:18] wire in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_ready = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_valid = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_e_ready = 1'h0; // @[Xbar.scala:159:18] wire in_1_e_valid = 1'h0; // @[Xbar.scala:159:18] wire out_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10] wire beatsAI_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire portsAOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_out_0_b_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _out_0_a_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire [7:0] auto_anon_in_1_a_bits_mask = 8'hFF; // @[Xbar.scala:74:9] wire [7:0] anonIn_1_a_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire [7:0] in_1_a_bits_mask = 8'hFF; // @[Xbar.scala:159:18] wire [7:0] portsAOI_filtered_1_0_bits_mask = 8'hFF; // @[Xbar.scala:352:24] wire [63:0] auto_anon_in_1_a_bits_data = 64'h0; // @[Xbar.scala:74:9] wire [63:0] anonIn_1_a_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] in_1_a_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] in_1_b_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] in_1_c_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] portsAOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _out_0_a_bits_T_4 = 64'h0; // @[Mux.scala:30:73] wire auto_anon_in_1_d_ready = 1'h1; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = 1'h1; // @[MixedNode.scala:551:17] wire in_1_b_ready = 1'h1; // @[Xbar.scala:159:18] wire in_1_d_ready = 1'h1; // @[Xbar.scala:159:18] wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _beatsAI_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire portsDIO_filtered_1_ready = 1'h1; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [8:0] beatsAI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69] wire [31:0] in_1_b_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] in_1_c_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [3:0] in_1_b_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] in_1_c_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [8:0] beatsAI_decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] _beatsAI_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _beatsAI_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _beatsAI_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [7:0] in_1_b_bits_mask = 8'h0; // @[Xbar.scala:159:18] wire [1:0] in_1_b_bits_param = 2'h0; // @[Xbar.scala:159:18] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_b_ready = auto_anon_in_0_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_c_ready; // @[MixedNode.scala:551:17] wire anonIn_c_valid = auto_anon_in_0_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_c_bits_opcode = auto_anon_in_0_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_c_bits_param = auto_anon_in_0_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_c_bits_size = auto_anon_in_0_c_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_c_bits_source = auto_anon_in_0_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_c_bits_address = auto_anon_in_0_c_bits_address_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_c_bits_data = auto_anon_in_0_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_e_ready; // @[MixedNode.scala:551:17] wire anonIn_e_valid = auto_anon_in_0_e_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_e_bits_sink = auto_anon_in_0_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_b_ready; // @[MixedNode.scala:542:17] wire anonOut_b_valid = auto_anon_out_b_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_b_bits_opcode = auto_anon_out_b_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_b_bits_param = auto_anon_out_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_b_bits_size = auto_anon_out_b_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_b_bits_source = auto_anon_out_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonOut_b_bits_address = auto_anon_out_b_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonOut_b_bits_mask = auto_anon_out_b_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_b_bits_data = auto_anon_out_b_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_b_bits_corrupt = auto_anon_out_b_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_c_ready = auto_anon_out_c_ready_0; // @[Xbar.scala:74:9] wire anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [2:0] anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_e_ready = auto_anon_out_e_ready_0; // @[Xbar.scala:74:9] wire anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_b_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_b_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_b_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_0_b_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_b_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_e_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_b_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_c_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_c_bits_address_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_c_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_c_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_e_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_out_e_valid_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [1:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_b_ready = anonIn_b_ready; // @[Xbar.scala:159:18] wire in_0_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_valid_0 = anonIn_b_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_b_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_opcode_0 = anonIn_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_param_0 = anonIn_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_b_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_size_0 = anonIn_b_bits_size; // @[Xbar.scala:74:9] wire [1:0] _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_b_bits_source_0 = anonIn_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_0_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_address_0 = anonIn_b_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_0_b_bits_mask; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_mask_0 = anonIn_b_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_0_b_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_data_0 = anonIn_b_bits_data; // @[Xbar.scala:74:9] wire in_0_b_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_corrupt_0 = anonIn_b_bits_corrupt; // @[Xbar.scala:74:9] wire in_0_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_c_ready_0 = anonIn_c_ready; // @[Xbar.scala:74:9] wire in_0_c_valid = anonIn_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_opcode = anonIn_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_param = anonIn_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_c_bits_size = anonIn_c_bits_size; // @[Xbar.scala:159:18] wire [1:0] _in_0_c_bits_source_T = anonIn_c_bits_source; // @[Xbar.scala:187:55] wire [31:0] in_0_c_bits_address = anonIn_c_bits_address; // @[Xbar.scala:159:18] wire [63:0] in_0_c_bits_data = anonIn_c_bits_data; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_0_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_e_ready_0 = anonIn_e_ready; // @[Xbar.scala:74:9] wire in_0_e_valid = anonIn_e_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_e_bits_sink = anonIn_e_bits_sink; // @[Xbar.scala:159:18] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_b_ready; // @[Xbar.scala:216:19] assign auto_anon_out_b_ready_0 = anonOut_b_ready; // @[Xbar.scala:74:9] wire out_0_b_valid = anonOut_b_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_b_bits_opcode = anonOut_b_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_b_bits_param = anonOut_b_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_b_bits_size = anonOut_b_bits_size; // @[Xbar.scala:216:19] wire [2:0] out_0_b_bits_source = anonOut_b_bits_source; // @[Xbar.scala:216:19] wire [31:0] out_0_b_bits_address = anonOut_b_bits_address; // @[Xbar.scala:216:19] wire [7:0] out_0_b_bits_mask = anonOut_b_bits_mask; // @[Xbar.scala:216:19] wire [63:0] out_0_b_bits_data = anonOut_b_bits_data; // @[Xbar.scala:216:19] wire out_0_b_bits_corrupt = anonOut_b_bits_corrupt; // @[Xbar.scala:216:19] wire out_0_c_ready = anonOut_c_ready; // @[Xbar.scala:216:19] wire out_0_c_valid; // @[Xbar.scala:216:19] assign auto_anon_out_c_valid_0 = anonOut_c_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_opcode_0 = anonOut_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_c_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_param_0 = anonOut_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_c_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_size_0 = anonOut_c_bits_size; // @[Xbar.scala:74:9] wire [2:0] out_0_c_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_source_0 = anonOut_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_c_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_address_0 = anonOut_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] out_0_c_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_data_0 = anonOut_c_bits_data; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [2:0] _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_0_e_ready = anonOut_e_ready; // @[Xbar.scala:216:19] wire out_0_e_valid; // @[Xbar.scala:216:19] assign auto_anon_out_e_valid_0 = anonOut_e_valid; // @[Xbar.scala:74:9] wire [2:0] _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] assign auto_anon_out_e_bits_sink_0 = anonOut_e_bits_sink; // @[Xbar.scala:74:9] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_0_ready = in_0_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_b_valid = in_0_b_valid; // @[Xbar.scala:159:18] wire [2:0] portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_b_bits_opcode = in_0_b_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_b_bits_param = in_0_b_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsBIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_b_bits_size = in_0_b_bits_size; // @[Xbar.scala:159:18] wire [2:0] portsBIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24] assign anonIn_b_bits_address = in_0_b_bits_address; // @[Xbar.scala:159:18] wire [7:0] portsBIO_filtered_0_bits_mask; // @[Xbar.scala:352:24] assign anonIn_b_bits_mask = in_0_b_bits_mask; // @[Xbar.scala:159:18] wire [63:0] portsBIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_b_bits_data = in_0_b_bits_data; // @[Xbar.scala:159:18] wire portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_b_bits_corrupt = in_0_b_bits_corrupt; // @[Xbar.scala:159:18] wire portsCOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_c_ready = in_0_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_1 = in_0_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_0_bits_opcode = in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_0_bits_param = in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_0_bits_size = in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_0_bits_source = in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T = in_0_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_0_bits_address = in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsCOI_filtered_0_bits_data = in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire [2:0] portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire portsEOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_e_ready = in_0_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_0_valid_T_1 = in_0_e_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] _requestEIO_uncommonBits_T = in_0_e_bits_sink; // @[Xbar.scala:159:18] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] wire [2:0] portsEOI_filtered_0_bits_sink = in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40] wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24] wire [2:0] portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire [2:0] in_0_b_bits_source; // @[Xbar.scala:159:18] wire [2:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [2:0] in_1_d_bits_source; // @[Xbar.scala:159:18] assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_b_bits_source_T = in_0_b_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_b_bits_source = _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign in_0_c_bits_source = {1'h0, _in_0_c_bits_source_T}; // @[Xbar.scala:159:18, :187:{29,55}] assign _anonIn_d_bits_source_T = in_0_d_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_b_ready = out_0_b_ready; // @[Xbar.scala:216:19] assign portsBIO_filtered_0_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsBIO_filtered_1_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsBIO_filtered_1_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24] wire [2:0] _requestBOI_uncommonBits_T = out_0_b_bits_source; // @[Xbar.scala:216:19] assign portsBIO_filtered_0_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsBIO_filtered_1_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsBIO_filtered_1_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24] wire [7:0] portsBIO_filtered_1_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsBIO_filtered_1_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsBIO_filtered_1_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsCOI_filtered_0_ready = out_0_c_ready; // @[Xbar.scala:216:19, :352:24] wire portsCOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_c_valid = out_0_c_valid; // @[Xbar.scala:216:19] assign anonOut_c_bits_opcode = out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_c_bits_param = out_0_c_bits_param; // @[Xbar.scala:216:19] assign anonOut_c_bits_size = out_0_c_bits_size; // @[Xbar.scala:216:19] assign anonOut_c_bits_source = out_0_c_bits_source; // @[Xbar.scala:216:19] assign anonOut_c_bits_address = out_0_c_bits_address; // @[Xbar.scala:216:19] assign anonOut_c_bits_data = out_0_c_bits_data; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [2:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsEOI_filtered_0_ready = out_0_e_ready; // @[Xbar.scala:216:19, :352:24] wire portsEOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_e_valid = out_0_e_valid; // @[Xbar.scala:216:19] assign _anonOut_e_bits_sink_T = out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19] assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign anonOut_e_bits_sink = _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_1 = {1'h0, _requestCIO_T}; // @[Parameters.scala:137:{31,41}] wire [1:0] requestBOI_uncommonBits = _requestBOI_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _requestBOI_T = out_0_b_bits_source[2]; // @[Xbar.scala:216:19] wire _requestBOI_T_1 = ~_requestBOI_T; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_3 = _requestBOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestBOI_0_0 = _requestBOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_0_valid_T = requestBOI_0_0; // @[Xbar.scala:355:54] wire requestBOI_0_1 = out_0_b_bits_source == 3'h4; // @[Xbar.scala:216:19] wire _portsBIO_filtered_1_valid_T = requestBOI_0_1; // @[Xbar.scala:355:54] wire [1:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T = out_0_d_bits_source[2]; // @[Xbar.scala:216:19] wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire requestDOI_0_1 = out_0_d_bits_source == 3'h4; // @[Xbar.scala:216:19] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1; // @[Mux.scala:30:73] wire [2:0] requestEIO_uncommonBits = _requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsBO_decode_T = 27'hFFF << out_0_b_bits_size; // @[package.scala:243:71] wire [11:0] _beatsBO_decode_T_1 = _beatsBO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsBO_decode_T_2 = ~_beatsBO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsBO_decode = _beatsBO_decode_T_2[11:3]; // @[package.scala:243:46] wire _beatsBO_opdata_T = out_0_b_bits_opcode[2]; // @[Xbar.scala:216:19] wire beatsBO_opdata = ~_beatsBO_opdata_T; // @[Edges.scala:97:{28,37}] wire [26:0] _beatsCI_decode_T = 27'hFFF << in_0_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_1 = _beatsCI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_2 = ~_beatsCI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsCI_decode = _beatsCI_decode_T_2[11:3]; // @[package.scala:243:46] wire beatsCI_opdata = in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [8:0] beatsCI_0 = beatsCI_opdata ? beatsCI_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_b_valid = portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_opcode = portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_param = portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_size = portsBIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_source = portsBIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_address = portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_mask = portsBIO_filtered_0_bits_mask; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_data = portsBIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_corrupt = portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire portsBIO_filtered_1_valid; // @[Xbar.scala:352:24] assign _portsBIO_filtered_0_valid_T_1 = out_0_b_valid & _portsBIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_0_valid = _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_1_valid_T_1 = out_0_b_valid & _portsBIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_valid = _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsBIO_out_0_b_ready_T = requestBOI_0_0 & portsBIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_2 = _portsBIO_out_0_b_ready_T; // @[Mux.scala:30:73] assign _portsBIO_out_0_b_ready_WIRE = _portsBIO_out_0_b_ready_T_2; // @[Mux.scala:30:73] assign out_0_b_ready = _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73] assign in_0_c_ready = portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign out_0_c_valid = portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_opcode = portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_param = portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_size = portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_source = portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_address = portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_data = portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsCOI_filtered_0_valid = _portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T \| _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign in_0_e_ready = portsEOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign out_0_e_valid = portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_e_bits_sink = portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsEOI_filtered_0_valid = _portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] \| _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} \| _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = \|readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T \| _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid \| portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to this FIRRTL code module InputBuffer_3 : input clock : Clock input reset : Reset output io : { flip enq : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>}}[8]} cmem mem : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>} [16] wire _heads_WIRE : UInt<4>[8] connect _heads_WIRE[0], UInt<4>(0h0) connect _heads_WIRE[1], UInt<4>(0h0) connect _heads_WIRE[2], UInt<4>(0h0) connect _heads_WIRE[3], UInt<4>(0h0) connect _heads_WIRE[4], UInt<4>(0h0) connect _heads_WIRE[5], UInt<4>(0h4) connect _heads_WIRE[6], UInt<4>(0h8) connect _heads_WIRE[7], UInt<4>(0hc) regreset heads : UInt<4>[8], clock, reset, _heads_WIRE wire _tails_WIRE : UInt<4>[8] connect _tails_WIRE[0], UInt<4>(0h0) connect _tails_WIRE[1], UInt<4>(0h0) connect _tails_WIRE[2], UInt<4>(0h0) connect _tails_WIRE[3], UInt<4>(0h0) connect _tails_WIRE[4], UInt<4>(0h0) connect _tails_WIRE[5], UInt<4>(0h4) connect _tails_WIRE[6], UInt<4>(0h8) connect _tails_WIRE[7], UInt<4>(0hc) regreset tails : UInt<4>[8], clock, reset, _tails_WIRE node empty_0 = eq(heads[0], tails[0]) node empty_1 = eq(heads[1], tails[1]) node empty_2 = eq(heads[2], tails[2]) node empty_3 = eq(heads[3], tails[3]) node empty_4 = eq(heads[4], tails[4]) node empty_5 = eq(heads[5], tails[5]) node empty_6 = eq(heads[6], tails[6]) node empty_7 = eq(heads[7], tails[7]) inst qs_0 of Queue1_BaseFlit_24 connect qs_0.clock, clock connect qs_0.reset, reset inst qs_1 of Queue1_BaseFlit_25 connect qs_1.clock, clock connect qs_1.reset, reset inst qs_2 of Queue1_BaseFlit_26 connect qs_2.clock, clock connect qs_2.reset, reset inst qs_3 of Queue1_BaseFlit_27 connect qs_3.clock, clock connect qs_3.reset, reset inst qs_4 of Queue1_BaseFlit_28 connect qs_4.clock, clock connect qs_4.reset, reset inst qs_5 of Queue1_BaseFlit_29 connect qs_5.clock, clock connect qs_5.reset, reset inst qs_6 of Queue1_BaseFlit_30 connect qs_6.clock, clock connect qs_6.reset, reset inst qs_7 of Queue1_BaseFlit_31 connect qs_7.clock, clock connect qs_7.reset, reset connect qs_0.io.enq.valid, UInt<1>(0h0) connect qs_1.io.enq.valid, UInt<1>(0h0) connect qs_2.io.enq.valid, UInt<1>(0h0) connect qs_3.io.enq.valid, UInt<1>(0h0) connect qs_4.io.enq.valid, UInt<1>(0h0) connect qs_5.io.enq.valid, UInt<1>(0h0) connect qs_6.io.enq.valid, UInt<1>(0h0) connect qs_7.io.enq.valid, UInt<1>(0h0) invalidate qs_0.io.enq.bits.payload invalidate qs_0.io.enq.bits.tail invalidate qs_0.io.enq.bits.head invalidate qs_1.io.enq.bits.payload invalidate qs_1.io.enq.bits.tail invalidate qs_1.io.enq.bits.head invalidate qs_2.io.enq.bits.payload invalidate qs_2.io.enq.bits.tail invalidate qs_2.io.enq.bits.head invalidate qs_3.io.enq.bits.payload invalidate qs_3.io.enq.bits.tail invalidate qs_3.io.enq.bits.head invalidate qs_4.io.enq.bits.payload invalidate qs_4.io.enq.bits.tail invalidate qs_4.io.enq.bits.head invalidate qs_5.io.enq.bits.payload invalidate qs_5.io.enq.bits.tail invalidate qs_5.io.enq.bits.head invalidate qs_6.io.enq.bits.payload invalidate qs_6.io.enq.bits.tail invalidate qs_6.io.enq.bits.head invalidate qs_7.io.enq.bits.payload invalidate qs_7.io.enq.bits.tail invalidate qs_7.io.enq.bits.head node vc_sel = dshl(UInt<1>(0h1), io.enq[0].bits.virt_channel_id) wire flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>} node _direct_to_q_T = bits(vc_sel, 0, 0) node _direct_to_q_T_1 = bits(vc_sel, 1, 1) node _direct_to_q_T_2 = bits(vc_sel, 2, 2) node _direct_to_q_T_3 = bits(vc_sel, 3, 3) node _direct_to_q_T_4 = bits(vc_sel, 4, 4) node _direct_to_q_T_5 = bits(vc_sel, 5, 5) node _direct_to_q_T_6 = bits(vc_sel, 6, 6) node _direct_to_q_T_7 = bits(vc_sel, 7, 7) node _direct_to_q_T_8 = mux(_direct_to_q_T, qs_0.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_9 = mux(_direct_to_q_T_1, qs_1.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_10 = mux(_direct_to_q_T_2, qs_2.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_11 = mux(_direct_to_q_T_3, qs_3.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_12 = mux(_direct_to_q_T_4, qs_4.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_13 = mux(_direct_to_q_T_5, qs_5.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_14 = mux(_direct_to_q_T_6, qs_6.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_15 = mux(_direct_to_q_T_7, qs_7.io.enq.ready, UInt<1>(0h0)) node _direct_to_q_T_16 = or(_direct_to_q_T_8, _direct_to_q_T_9) node _direct_to_q_T_17 = or(_direct_to_q_T_16, _direct_to_q_T_10) node _direct_to_q_T_18 = or(_direct_to_q_T_17, _direct_to_q_T_11) node _direct_to_q_T_19 = or(_direct_to_q_T_18, _direct_to_q_T_12) node _direct_to_q_T_20 = or(_direct_to_q_T_19, _direct_to_q_T_13) node _direct_to_q_T_21 = or(_direct_to_q_T_20, _direct_to_q_T_14) node _direct_to_q_T_22 = or(_direct_to_q_T_21, _direct_to_q_T_15) wire _direct_to_q_WIRE : UInt<1> connect _direct_to_q_WIRE, _direct_to_q_T_22 node _direct_to_q_T_23 = bits(vc_sel, 0, 0) node _direct_to_q_T_24 = bits(vc_sel, 1, 1) node _direct_to_q_T_25 = bits(vc_sel, 2, 2) node _direct_to_q_T_26 = bits(vc_sel, 3, 3) node _direct_to_q_T_27 = bits(vc_sel, 4, 4) node _direct_to_q_T_28 = bits(vc_sel, 5, 5) node _direct_to_q_T_29 = bits(vc_sel, 6, 6) node _direct_to_q_T_30 = bits(vc_sel, 7, 7) node _direct_to_q_T_31 = mux(_direct_to_q_T_23, empty_0, UInt<1>(0h0)) node _direct_to_q_T_32 = mux(_direct_to_q_T_24, empty_1, UInt<1>(0h0)) node _direct_to_q_T_33 = mux(_direct_to_q_T_25, empty_2, UInt<1>(0h0)) node _direct_to_q_T_34 = mux(_direct_to_q_T_26, empty_3, UInt<1>(0h0)) node _direct_to_q_T_35 = mux(_direct_to_q_T_27, empty_4, UInt<1>(0h0)) node _direct_to_q_T_36 = mux(_direct_to_q_T_28, empty_5, UInt<1>(0h0)) node _direct_to_q_T_37 = mux(_direct_to_q_T_29, empty_6, UInt<1>(0h0)) node _direct_to_q_T_38 = mux(_direct_to_q_T_30, empty_7, UInt<1>(0h0)) node _direct_to_q_T_39 = or(_direct_to_q_T_31, _direct_to_q_T_32) node _direct_to_q_T_40 = or(_direct_to_q_T_39, _direct_to_q_T_33) node _direct_to_q_T_41 = or(_direct_to_q_T_40, _direct_to_q_T_34) node _direct_to_q_T_42 = or(_direct_to_q_T_41, _direct_to_q_T_35) node _direct_to_q_T_43 = or(_direct_to_q_T_42, _direct_to_q_T_36) node _direct_to_q_T_44 = or(_direct_to_q_T_43, _direct_to_q_T_37) node _direct_to_q_T_45 = or(_direct_to_q_T_44, _direct_to_q_T_38) wire _direct_to_q_WIRE_1 : UInt<1> connect _direct_to_q_WIRE_1, _direct_to_q_T_45 node _direct_to_q_T_46 = and(_direct_to_q_WIRE, _direct_to_q_WIRE_1) node direct_to_q = and(_direct_to_q_T_46, UInt<1>(0h1)) connect flit.head, io.enq[0].bits.head connect flit.tail, io.enq[0].bits.tail connect flit.payload, io.enq[0].bits.payload node _T = eq(direct_to_q, UInt<1>(0h0)) node _T_1 = and(io.enq[0].valid, _T) when _T_1 : write mport MPORT = mem[tails[io.enq[0].bits.virt_channel_id]], clock connect MPORT, flit node _tails_T = bits(vc_sel, 0, 0) node _tails_T_1 = bits(vc_sel, 1, 1) node _tails_T_2 = bits(vc_sel, 2, 2) node _tails_T_3 = bits(vc_sel, 3, 3) node _tails_T_4 = bits(vc_sel, 4, 4) node _tails_T_5 = bits(vc_sel, 5, 5) node _tails_T_6 = bits(vc_sel, 6, 6) node _tails_T_7 = bits(vc_sel, 7, 7) node _tails_T_8 = mux(_tails_T, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_9 = mux(_tails_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_10 = mux(_tails_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_11 = mux(_tails_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_12 = mux(_tails_T_4, UInt<2>(0h3), UInt<1>(0h0)) node _tails_T_13 = mux(_tails_T_5, UInt<3>(0h7), UInt<1>(0h0)) node _tails_T_14 = mux(_tails_T_6, UInt<4>(0hb), UInt<1>(0h0)) node _tails_T_15 = mux(_tails_T_7, UInt<4>(0hf), UInt<1>(0h0)) node _tails_T_16 = or(_tails_T_8, _tails_T_9) node _tails_T_17 = or(_tails_T_16, _tails_T_10) node _tails_T_18 = or(_tails_T_17, _tails_T_11) node _tails_T_19 = or(_tails_T_18, _tails_T_12) node _tails_T_20 = or(_tails_T_19, _tails_T_13) node _tails_T_21 = or(_tails_T_20, _tails_T_14) node _tails_T_22 = or(_tails_T_21, _tails_T_15) wire _tails_WIRE_1 : UInt<4> connect _tails_WIRE_1, _tails_T_22 node _tails_T_23 = eq(tails[io.enq[0].bits.virt_channel_id], _tails_WIRE_1) node _tails_T_24 = bits(vc_sel, 0, 0) node _tails_T_25 = bits(vc_sel, 1, 1) node _tails_T_26 = bits(vc_sel, 2, 2) node _tails_T_27 = bits(vc_sel, 3, 3) node _tails_T_28 = bits(vc_sel, 4, 4) node _tails_T_29 = bits(vc_sel, 5, 5) node _tails_T_30 = bits(vc_sel, 6, 6) node _tails_T_31 = bits(vc_sel, 7, 7) node _tails_T_32 = mux(_tails_T_24, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_33 = mux(_tails_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_34 = mux(_tails_T_26, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_35 = mux(_tails_T_27, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_36 = mux(_tails_T_28, UInt<1>(0h0), UInt<1>(0h0)) node _tails_T_37 = mux(_tails_T_29, UInt<3>(0h4), UInt<1>(0h0)) node _tails_T_38 = mux(_tails_T_30, UInt<4>(0h8), UInt<1>(0h0)) node _tails_T_39 = mux(_tails_T_31, UInt<4>(0hc), UInt<1>(0h0)) node _tails_T_40 = or(_tails_T_32, _tails_T_33) node _tails_T_41 = or(_tails_T_40, _tails_T_34) node _tails_T_42 = or(_tails_T_41, _tails_T_35) node _tails_T_43 = or(_tails_T_42, _tails_T_36) node _tails_T_44 = or(_tails_T_43, _tails_T_37) node _tails_T_45 = or(_tails_T_44, _tails_T_38) node _tails_T_46 = or(_tails_T_45, _tails_T_39) wire _tails_WIRE_2 : UInt<4> connect _tails_WIRE_2, _tails_T_46 node _tails_T_47 = add(tails[io.enq[0].bits.virt_channel_id], UInt<1>(0h1)) node _tails_T_48 = tail(_tails_T_47, 1) node _tails_T_49 = mux(_tails_T_23, _tails_WIRE_2, _tails_T_48) connect tails[io.enq[0].bits.virt_channel_id], _tails_T_49 else : node _T_2 = and(io.enq[0].valid, direct_to_q) when _T_2 : node _T_3 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h0)) when _T_3 : connect qs_0.io.enq.valid, UInt<1>(0h1) connect qs_0.io.enq.bits.payload, flit.payload connect qs_0.io.enq.bits.tail, flit.tail connect qs_0.io.enq.bits.head, flit.head node _T_4 = eq(io.enq[0].bits.virt_channel_id, UInt<1>(0h1)) when _T_4 : connect qs_1.io.enq.valid, UInt<1>(0h1) connect qs_1.io.enq.bits.payload, flit.payload connect qs_1.io.enq.bits.tail, flit.tail connect qs_1.io.enq.bits.head, flit.head node _T_5 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h2)) when _T_5 : connect qs_2.io.enq.valid, UInt<1>(0h1) connect qs_2.io.enq.bits.payload, flit.payload connect qs_2.io.enq.bits.tail, flit.tail connect qs_2.io.enq.bits.head, flit.head node _T_6 = eq(io.enq[0].bits.virt_channel_id, UInt<2>(0h3)) when _T_6 : connect qs_3.io.enq.valid, UInt<1>(0h1) connect qs_3.io.enq.bits.payload, flit.payload connect qs_3.io.enq.bits.tail, flit.tail connect qs_3.io.enq.bits.head, flit.head node _T_7 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h4)) when _T_7 : connect qs_4.io.enq.valid, UInt<1>(0h1) connect qs_4.io.enq.bits.payload, flit.payload connect qs_4.io.enq.bits.tail, flit.tail connect qs_4.io.enq.bits.head, flit.head node _T_8 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h5)) when _T_8 : connect qs_5.io.enq.valid, UInt<1>(0h1) connect qs_5.io.enq.bits.payload, flit.payload connect qs_5.io.enq.bits.tail, flit.tail connect qs_5.io.enq.bits.head, flit.head node _T_9 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h6)) when _T_9 : connect qs_6.io.enq.valid, UInt<1>(0h1) connect qs_6.io.enq.bits.payload, flit.payload connect qs_6.io.enq.bits.tail, flit.tail connect qs_6.io.enq.bits.head, flit.head node _T_10 = eq(io.enq[0].bits.virt_channel_id, UInt<3>(0h7)) when _T_10 : connect qs_7.io.enq.valid, UInt<1>(0h1) connect qs_7.io.enq.bits.payload, flit.payload connect qs_7.io.enq.bits.tail, flit.tail connect qs_7.io.enq.bits.head, flit.head node _can_to_q_T = eq(empty_0, UInt<1>(0h0)) node can_to_q_0 = and(_can_to_q_T, qs_0.io.enq.ready) node _can_to_q_T_1 = eq(empty_1, UInt<1>(0h0)) node can_to_q_1 = and(_can_to_q_T_1, qs_1.io.enq.ready) node _can_to_q_T_2 = eq(empty_2, UInt<1>(0h0)) node can_to_q_2 = and(_can_to_q_T_2, qs_2.io.enq.ready) node _can_to_q_T_3 = eq(empty_3, UInt<1>(0h0)) node can_to_q_3 = and(_can_to_q_T_3, qs_3.io.enq.ready) node _can_to_q_T_4 = eq(empty_4, UInt<1>(0h0)) node can_to_q_4 = and(_can_to_q_T_4, qs_4.io.enq.ready) node _can_to_q_T_5 = eq(empty_5, UInt<1>(0h0)) node can_to_q_5 = and(_can_to_q_T_5, qs_5.io.enq.ready) node _can_to_q_T_6 = eq(empty_6, UInt<1>(0h0)) node can_to_q_6 = and(_can_to_q_T_6, qs_6.io.enq.ready) node _can_to_q_T_7 = eq(empty_7, UInt<1>(0h0)) node can_to_q_7 = and(_can_to_q_T_7, qs_7.io.enq.ready) node _to_q_oh_enc_T = mux(can_to_q_7, UInt<8>(0h80), UInt<8>(0h0)) node _to_q_oh_enc_T_1 = mux(can_to_q_6, UInt<8>(0h40), _to_q_oh_enc_T) node _to_q_oh_enc_T_2 = mux(can_to_q_5, UInt<8>(0h20), _to_q_oh_enc_T_1) node _to_q_oh_enc_T_3 = mux(can_to_q_4, UInt<8>(0h10), _to_q_oh_enc_T_2) node _to_q_oh_enc_T_4 = mux(can_to_q_3, UInt<8>(0h8), _to_q_oh_enc_T_3) node _to_q_oh_enc_T_5 = mux(can_to_q_2, UInt<8>(0h4), _to_q_oh_enc_T_4) node _to_q_oh_enc_T_6 = mux(can_to_q_1, UInt<8>(0h2), _to_q_oh_enc_T_5) node to_q_oh_enc = mux(can_to_q_0, UInt<8>(0h1), _to_q_oh_enc_T_6) node to_q_oh_0 = bits(to_q_oh_enc, 0, 0) node to_q_oh_1 = bits(to_q_oh_enc, 1, 1) node to_q_oh_2 = bits(to_q_oh_enc, 2, 2) node to_q_oh_3 = bits(to_q_oh_enc, 3, 3) node to_q_oh_4 = bits(to_q_oh_enc, 4, 4) node to_q_oh_5 = bits(to_q_oh_enc, 5, 5) node to_q_oh_6 = bits(to_q_oh_enc, 6, 6) node to_q_oh_7 = bits(to_q_oh_enc, 7, 7) node to_q_lo_lo = cat(to_q_oh_1, to_q_oh_0) node to_q_lo_hi = cat(to_q_oh_3, to_q_oh_2) node to_q_lo = cat(to_q_lo_hi, to_q_lo_lo) node to_q_hi_lo = cat(to_q_oh_5, to_q_oh_4) node to_q_hi_hi = cat(to_q_oh_7, to_q_oh_6) node to_q_hi = cat(to_q_hi_hi, to_q_hi_lo) node _to_q_T = cat(to_q_hi, to_q_lo) node to_q_hi_1 = bits(_to_q_T, 7, 4) node to_q_lo_1 = bits(_to_q_T, 3, 0) node _to_q_T_1 = orr(to_q_hi_1) node _to_q_T_2 = or(to_q_hi_1, to_q_lo_1) node to_q_hi_2 = bits(_to_q_T_2, 3, 2) node to_q_lo_2 = bits(_to_q_T_2, 1, 0) node _to_q_T_3 = orr(to_q_hi_2) node _to_q_T_4 = or(to_q_hi_2, to_q_lo_2) node _to_q_T_5 = bits(_to_q_T_4, 1, 1) node _to_q_T_6 = cat(_to_q_T_3, _to_q_T_5) node to_q = cat(_to_q_T_1, _to_q_T_6) node _T_11 = or(can_to_q_0, can_to_q_1) node _T_12 = or(_T_11, can_to_q_2) node _T_13 = or(_T_12, can_to_q_3) node _T_14 = or(_T_13, can_to_q_4) node _T_15 = or(_T_14, can_to_q_5) node _T_16 = or(_T_15, can_to_q_6) node _T_17 = or(_T_16, can_to_q_7) when _T_17 : node _head_T = mux(to_q_oh_0, heads[0], UInt<1>(0h0)) node _head_T_1 = mux(to_q_oh_1, heads[1], UInt<1>(0h0)) node _head_T_2 = mux(to_q_oh_2, heads[2], UInt<1>(0h0)) node _head_T_3 = mux(to_q_oh_3, heads[3], UInt<1>(0h0)) node _head_T_4 = mux(to_q_oh_4, heads[4], UInt<1>(0h0)) node _head_T_5 = mux(to_q_oh_5, heads[5], UInt<1>(0h0)) node _head_T_6 = mux(to_q_oh_6, heads[6], UInt<1>(0h0)) node _head_T_7 = mux(to_q_oh_7, heads[7], UInt<1>(0h0)) node _head_T_8 = or(_head_T, _head_T_1) node _head_T_9 = or(_head_T_8, _head_T_2) node _head_T_10 = or(_head_T_9, _head_T_3) node _head_T_11 = or(_head_T_10, _head_T_4) node _head_T_12 = or(_head_T_11, _head_T_5) node _head_T_13 = or(_head_T_12, _head_T_6) node _head_T_14 = or(_head_T_13, _head_T_7) wire head : UInt<4> connect head, _head_T_14 node _heads_T = mux(to_q_oh_0, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_1 = mux(to_q_oh_1, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_2 = mux(to_q_oh_2, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_3 = mux(to_q_oh_3, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_4 = mux(to_q_oh_4, UInt<2>(0h3), UInt<1>(0h0)) node _heads_T_5 = mux(to_q_oh_5, UInt<3>(0h7), UInt<1>(0h0)) node _heads_T_6 = mux(to_q_oh_6, UInt<4>(0hb), UInt<1>(0h0)) node _heads_T_7 = mux(to_q_oh_7, UInt<4>(0hf), UInt<1>(0h0)) node _heads_T_8 = or(_heads_T, _heads_T_1) node _heads_T_9 = or(_heads_T_8, _heads_T_2) node _heads_T_10 = or(_heads_T_9, _heads_T_3) node _heads_T_11 = or(_heads_T_10, _heads_T_4) node _heads_T_12 = or(_heads_T_11, _heads_T_5) node _heads_T_13 = or(_heads_T_12, _heads_T_6) node _heads_T_14 = or(_heads_T_13, _heads_T_7) wire _heads_WIRE_1 : UInt<4> connect _heads_WIRE_1, _heads_T_14 node _heads_T_15 = eq(head, _heads_WIRE_1) node _heads_T_16 = mux(to_q_oh_0, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_17 = mux(to_q_oh_1, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_18 = mux(to_q_oh_2, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_19 = mux(to_q_oh_3, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_20 = mux(to_q_oh_4, UInt<1>(0h0), UInt<1>(0h0)) node _heads_T_21 = mux(to_q_oh_5, UInt<3>(0h4), UInt<1>(0h0)) node _heads_T_22 = mux(to_q_oh_6, UInt<4>(0h8), UInt<1>(0h0)) node _heads_T_23 = mux(to_q_oh_7, UInt<4>(0hc), UInt<1>(0h0)) node _heads_T_24 = or(_heads_T_16, _heads_T_17) node _heads_T_25 = or(_heads_T_24, _heads_T_18) node _heads_T_26 = or(_heads_T_25, _heads_T_19) node _heads_T_27 = or(_heads_T_26, _heads_T_20) node _heads_T_28 = or(_heads_T_27, _heads_T_21) node _heads_T_29 = or(_heads_T_28, _heads_T_22) node _heads_T_30 = or(_heads_T_29, _heads_T_23) wire _heads_WIRE_2 : UInt<4> connect _heads_WIRE_2, _heads_T_30 node _heads_T_31 = add(head, UInt<1>(0h1)) node _heads_T_32 = tail(_heads_T_31, 1) node _heads_T_33 = mux(_heads_T_15, _heads_WIRE_2, _heads_T_32) connect heads[to_q], _heads_T_33 when to_q_oh_0 : connect qs_0.io.enq.valid, UInt<1>(0h1) read mport qs_0_io_enq_bits_MPORT = mem[head], clock connect qs_0.io.enq.bits.payload, qs_0_io_enq_bits_MPORT.payload connect qs_0.io.enq.bits.tail, qs_0_io_enq_bits_MPORT.tail connect qs_0.io.enq.bits.head, qs_0_io_enq_bits_MPORT.head when to_q_oh_1 : connect qs_1.io.enq.valid, UInt<1>(0h1) read mport qs_1_io_enq_bits_MPORT = mem[head], clock connect qs_1.io.enq.bits.payload, qs_1_io_enq_bits_MPORT.payload connect qs_1.io.enq.bits.tail, qs_1_io_enq_bits_MPORT.tail connect qs_1.io.enq.bits.head, qs_1_io_enq_bits_MPORT.head when to_q_oh_2 : connect qs_2.io.enq.valid, UInt<1>(0h1) read mport qs_2_io_enq_bits_MPORT = mem[head], clock connect qs_2.io.enq.bits.payload, qs_2_io_enq_bits_MPORT.payload connect qs_2.io.enq.bits.tail, qs_2_io_enq_bits_MPORT.tail connect qs_2.io.enq.bits.head, qs_2_io_enq_bits_MPORT.head when to_q_oh_3 : connect qs_3.io.enq.valid, UInt<1>(0h1) read mport qs_3_io_enq_bits_MPORT = mem[head], clock connect qs_3.io.enq.bits.payload, qs_3_io_enq_bits_MPORT.payload connect qs_3.io.enq.bits.tail, qs_3_io_enq_bits_MPORT.tail connect qs_3.io.enq.bits.head, qs_3_io_enq_bits_MPORT.head when to_q_oh_4 : connect qs_4.io.enq.valid, UInt<1>(0h1) read mport qs_4_io_enq_bits_MPORT = mem[head], clock connect qs_4.io.enq.bits.payload, qs_4_io_enq_bits_MPORT.payload connect qs_4.io.enq.bits.tail, qs_4_io_enq_bits_MPORT.tail connect qs_4.io.enq.bits.head, qs_4_io_enq_bits_MPORT.head when to_q_oh_5 : connect qs_5.io.enq.valid, UInt<1>(0h1) read mport qs_5_io_enq_bits_MPORT = mem[head], clock connect qs_5.io.enq.bits.payload, qs_5_io_enq_bits_MPORT.payload connect qs_5.io.enq.bits.tail, qs_5_io_enq_bits_MPORT.tail connect qs_5.io.enq.bits.head, qs_5_io_enq_bits_MPORT.head when to_q_oh_6 : connect qs_6.io.enq.valid, UInt<1>(0h1) read mport qs_6_io_enq_bits_MPORT = mem[head], clock connect qs_6.io.enq.bits.payload, qs_6_io_enq_bits_MPORT.payload connect qs_6.io.enq.bits.tail, qs_6_io_enq_bits_MPORT.tail connect qs_6.io.enq.bits.head, qs_6_io_enq_bits_MPORT.head when to_q_oh_7 : connect qs_7.io.enq.valid, UInt<1>(0h1) read mport qs_7_io_enq_bits_MPORT = mem[head], clock connect qs_7.io.enq.bits.payload, qs_7_io_enq_bits_MPORT.payload connect qs_7.io.enq.bits.tail, qs_7_io_enq_bits_MPORT.tail connect qs_7.io.enq.bits.head, qs_7_io_enq_bits_MPORT.head connect io.deq[0].bits, qs_0.io.deq.bits connect io.deq[0].valid, qs_0.io.deq.valid connect qs_0.io.deq.ready, io.deq[0].ready connect io.deq[1].bits, qs_1.io.deq.bits connect io.deq[1].valid, qs_1.io.deq.valid connect qs_1.io.deq.ready, io.deq[1].ready connect io.deq[2].bits, qs_2.io.deq.bits connect io.deq[2].valid, qs_2.io.deq.valid connect qs_2.io.deq.ready, io.deq[2].ready connect io.deq[3].bits, qs_3.io.deq.bits connect io.deq[3].valid, qs_3.io.deq.valid connect qs_3.io.deq.ready, io.deq[3].ready connect io.deq[4].bits, qs_4.io.deq.bits connect io.deq[4].valid, qs_4.io.deq.valid connect qs_4.io.deq.ready, io.deq[4].ready connect io.deq[5].bits, qs_5.io.deq.bits connect io.deq[5].valid, qs_5.io.deq.valid connect qs_5.io.deq.ready, io.deq[5].ready connect io.deq[6].bits, qs_6.io.deq.bits connect io.deq[6].valid, qs_6.io.deq.valid connect qs_6.io.deq.ready, io.deq[6].ready connect io.deq[7].bits, qs_7.io.deq.bits connect io.deq[7].valid, qs_7.io.deq.valid connect qs_7.io.deq.ready, io.deq[7].ready	module InputBuffer_3( // @[InputUnit.scala:49:7] input clock, // @[InputUnit.scala:49:7] input reset, // @[InputUnit.scala:49:7] input io_enq_0_valid, // @[InputUnit.scala:51:14] input io_enq_0_bits_head, // @[InputUnit.scala:51:14] input io_enq_0_bits_tail, // @[InputUnit.scala:51:14] input [72:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14] input [2:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14] output io_deq_0_bits_head, // @[InputUnit.scala:51:14] output io_deq_0_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14] output io_deq_1_bits_head, // @[InputUnit.scala:51:14] output io_deq_1_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14] output io_deq_2_bits_head, // @[InputUnit.scala:51:14] output io_deq_2_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14] output io_deq_3_bits_head, // @[InputUnit.scala:51:14] output io_deq_3_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_3_bits_payload, // @[InputUnit.scala:51:14] input io_deq_4_ready, // @[InputUnit.scala:51:14] output io_deq_4_valid, // @[InputUnit.scala:51:14] output io_deq_4_bits_head, // @[InputUnit.scala:51:14] output io_deq_4_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_4_bits_payload, // @[InputUnit.scala:51:14] input io_deq_5_ready, // @[InputUnit.scala:51:14] output io_deq_5_valid, // @[InputUnit.scala:51:14] output io_deq_5_bits_head, // @[InputUnit.scala:51:14] output io_deq_5_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_5_bits_payload, // @[InputUnit.scala:51:14] input io_deq_6_ready, // @[InputUnit.scala:51:14] output io_deq_6_valid, // @[InputUnit.scala:51:14] output io_deq_6_bits_head, // @[InputUnit.scala:51:14] output io_deq_6_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_6_bits_payload, // @[InputUnit.scala:51:14] input io_deq_7_ready, // @[InputUnit.scala:51:14] output io_deq_7_valid, // @[InputUnit.scala:51:14] output io_deq_7_bits_head, // @[InputUnit.scala:51:14] output io_deq_7_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_7_bits_payload // @[InputUnit.scala:51:14] ); wire _qs_7_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_6_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_5_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_4_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49] wire [74:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R4_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R5_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R6_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R7_data; // @[InputUnit.scala:85:18] reg [3:0] heads_0; // @[InputUnit.scala:86:24] reg [3:0] heads_1; // @[InputUnit.scala:86:24] reg [3:0] heads_2; // @[InputUnit.scala:86:24] reg [3:0] heads_3; // @[InputUnit.scala:86:24] reg [3:0] heads_4; // @[InputUnit.scala:86:24] reg [3:0] heads_5; // @[InputUnit.scala:86:24] reg [3:0] heads_6; // @[InputUnit.scala:86:24] reg [3:0] heads_7; // @[InputUnit.scala:86:24] reg [3:0] tails_0; // @[InputUnit.scala:87:24] reg [3:0] tails_1; // @[InputUnit.scala:87:24] reg [3:0] tails_2; // @[InputUnit.scala:87:24] reg [3:0] tails_3; // @[InputUnit.scala:87:24] reg [3:0] tails_4; // @[InputUnit.scala:87:24] reg [3:0] tails_5; // @[InputUnit.scala:87:24] reg [3:0] tails_6; // @[InputUnit.scala:87:24] reg [3:0] tails_7; // @[InputUnit.scala:87:24] wire _tails_T_24 = io_enq_0_bits_virt_channel_id == 3'h0; // @[Mux.scala:32:36] wire _tails_T_25 = io_enq_0_bits_virt_channel_id == 3'h1; // @[Mux.scala:32:36] wire _tails_T_26 = io_enq_0_bits_virt_channel_id == 3'h2; // @[Mux.scala:32:36] wire _tails_T_27 = io_enq_0_bits_virt_channel_id == 3'h3; // @[Mux.scala:32:36] wire _tails_T_28 = io_enq_0_bits_virt_channel_id == 3'h4; // @[Mux.scala:32:36] wire _tails_T_29 = io_enq_0_bits_virt_channel_id == 3'h5; // @[Mux.scala:32:36] wire _tails_T_30 = io_enq_0_bits_virt_channel_id == 3'h6; // @[Mux.scala:32:36] wire direct_to_q = (_tails_T_24 & _qs_0_io_enq_ready \| _tails_T_25 & _qs_1_io_enq_ready \| _tails_T_26 & _qs_2_io_enq_ready \| _tails_T_27 & _qs_3_io_enq_ready \| _tails_T_28 & _qs_4_io_enq_ready \| _tails_T_29 & _qs_5_io_enq_ready \| _tails_T_30 & _qs_6_io_enq_ready \| (&io_enq_0_bits_virt_channel_id) & _qs_7_io_enq_ready) & (_tails_T_24 & heads_0 == tails_0 \| _tails_T_25 & heads_1 == tails_1 \| _tails_T_26 & heads_2 == tails_2 \| _tails_T_27 & heads_3 == tails_3 \| _tails_T_28 & heads_4 == tails_4 \| _tails_T_29 & heads_5 == tails_5 \| _tails_T_30 & heads_6 == tails_6 \| (&io_enq_0_bits_virt_channel_id) & heads_7 == tails_7); // @[Mux.scala:30:73, :32:36] wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}] wire [7:0][3:0] _GEN = {{tails_7}, {tails_6}, {tails_5}, {tails_4}, {tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16] wire _GEN_0 = io_enq_0_bits_virt_channel_id == 3'h0; // @[InputUnit.scala:103:45] wire _GEN_1 = io_enq_0_bits_virt_channel_id == 3'h1; // @[InputUnit.scala:103:45] wire _GEN_2 = io_enq_0_bits_virt_channel_id == 3'h2; // @[InputUnit.scala:103:45] wire _GEN_3 = io_enq_0_bits_virt_channel_id == 3'h3; // @[InputUnit.scala:103:45] wire _GEN_4 = io_enq_0_bits_virt_channel_id == 3'h4; // @[InputUnit.scala:103:45] wire _GEN_5 = io_enq_0_bits_virt_channel_id == 3'h5; // @[InputUnit.scala:103:45] wire _GEN_6 = io_enq_0_bits_virt_channel_id == 3'h6; // @[InputUnit.scala:103:45] wire _GEN_7 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34] wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_4 = heads_4 != tails_4 & _qs_4_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_5 = heads_5 != tails_5 & _qs_5_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_6 = heads_6 != tails_6 & _qs_6_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_7 = heads_7 != tails_7 & _qs_7_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire [7:0] to_q_oh_enc = can_to_q_0 ? 8'h1 : can_to_q_1 ? 8'h2 : can_to_q_2 ? 8'h4 : can_to_q_3 ? 8'h8 : can_to_q_4 ? 8'h10 : can_to_q_5 ? 8'h20 : can_to_q_6 ? 8'h40 : {can_to_q_7, 7'h0}; // @[OneHot.scala:58:35] wire _GEN_8 = can_to_q_0 \| can_to_q_1 \| can_to_q_2 \| can_to_q_3 \| can_to_q_4 \| can_to_q_5 \| can_to_q_6 \| can_to_q_7; // @[package.scala:81:59] wire [3:0] head = (to_q_oh_enc[0] ? heads_0 : 4'h0) \| (to_q_oh_enc[1] ? heads_1 : 4'h0) \| (to_q_oh_enc[2] ? heads_2 : 4'h0) \| (to_q_oh_enc[3] ? heads_3 : 4'h0) \| (to_q_oh_enc[4] ? heads_4 : 4'h0) \| (to_q_oh_enc[5] ? heads_5 : 4'h0) \| (to_q_oh_enc[6] ? heads_6 : 4'h0) \| (to_q_oh_enc[7] ? heads_7 : 4'h0); // @[OneHot.scala:83:30] wire _GEN_9 = _GEN_8 & to_q_oh_enc[0]; // @[OneHot.scala:83:30] wire _GEN_10 = _GEN_8 & to_q_oh_enc[1]; // @[OneHot.scala:83:30] wire _GEN_11 = _GEN_8 & to_q_oh_enc[2]; // @[OneHot.scala:83:30] wire _GEN_12 = _GEN_8 & to_q_oh_enc[3]; // @[OneHot.scala:83:30] wire _GEN_13 = _GEN_8 & to_q_oh_enc[4]; // @[OneHot.scala:83:30] wire _GEN_14 = _GEN_8 & to_q_oh_enc[5]; // @[OneHot.scala:83:30] wire _GEN_15 = _GEN_8 & to_q_oh_enc[6]; // @[OneHot.scala:83:30] wire _GEN_16 = _GEN_8 & to_q_oh_enc[7]; // @[OneHot.scala:83:30] wire [3:0] _tails_T_49 = _GEN[io_enq_0_bits_virt_channel_id] == ({1'h0, {1'h0, {2{_tails_T_28}}} \| {3{_tails_T_29}}} \| (_tails_T_30 ? 4'hB : 4'h0) \| {4{&io_enq_0_bits_virt_channel_id}}) ? {_tails_T_30, _tails_T_29, 2'h0} \| ((&io_enq_0_bits_virt_channel_id) ? 4'hC : 4'h0) : _GEN[io_enq_0_bits_virt_channel_id] + 4'h1; // @[Mux.scala:30:73, :32:36] wire [2:0] _to_q_T_2 = to_q_oh_enc[7:5] \| to_q_oh_enc[3:1]; // @[OneHot.scala:30:18, :31:18, :32:28] wire _to_q_T_4 = _to_q_T_2[2] \| _to_q_T_2[0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] to_q = {\|(to_q_oh_enc[7:4]), \|(_to_q_T_2[2:1]), _to_q_T_4}; // @[OneHot.scala:30:18, :32:{10,14,28}] wire [3:0] _heads_T_33 = head == ({1'h0, {1'h0, {2{to_q_oh_enc[4]}}} \| {3{to_q_oh_enc[5]}}} \| (to_q_oh_enc[6] ? 4'hB : 4'h0) \| {4{to_q_oh_enc[7]}}) ? {to_q_oh_enc[6:5], 2'h0} \| (to_q_oh_enc[7] ? 4'hC : 4'h0) : head + 4'h1; // @[OneHot.scala:83:30] always @(posedge clock) begin // @[InputUnit.scala:49:7] if (reset) begin // @[InputUnit.scala:49:7] heads_0 <= 4'h0; // @[InputUnit.scala:86:24] heads_1 <= 4'h0; // @[InputUnit.scala:86:24] heads_2 <= 4'h0; // @[InputUnit.scala:86:24] heads_3 <= 4'h0; // @[InputUnit.scala:86:24] heads_4 <= 4'h0; // @[InputUnit.scala:86:24] heads_5 <= 4'h4; // @[InputUnit.scala:86:24] heads_6 <= 4'h8; // @[InputUnit.scala:86:24] heads_7 <= 4'hC; // @[InputUnit.scala:86:24] tails_0 <= 4'h0; // @[InputUnit.scala:87:24] tails_1 <= 4'h0; // @[InputUnit.scala:87:24] tails_2 <= 4'h0; // @[InputUnit.scala:87:24] tails_3 <= 4'h0; // @[InputUnit.scala:87:24] tails_4 <= 4'h0; // @[InputUnit.scala:87:24] tails_5 <= 4'h4; // @[InputUnit.scala:87:24] tails_6 <= 4'h8; // @[InputUnit.scala:87:24] tails_7 <= 4'hC; // @[InputUnit.scala:87:24] end else begin // @[InputUnit.scala:49:7] if (_GEN_8 & {to_q_oh_enc[7:4], \|(_to_q_T_2[2:1]), _to_q_T_4} == 6'h0) // @[OneHot.scala:30:18, :32:{10,14,28}] heads_0 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (_GEN_8 & to_q == 3'h1) // @[OneHot.scala:32:10] heads_1 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (_GEN_8 & to_q == 3'h2) // @[OneHot.scala:32:10] heads_2 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (_GEN_8 & to_q == 3'h3) // @[OneHot.scala:32:10] heads_3 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (_GEN_8 & to_q == 3'h4) // @[OneHot.scala:32:10] heads_4 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (_GEN_8 & to_q == 3'h5) // @[OneHot.scala:32:10] heads_5 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (_GEN_8 & to_q == 3'h6) // @[OneHot.scala:32:10] heads_6 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (_GEN_8 & (&to_q)) // @[OneHot.scala:32:10] heads_7 <= _heads_T_33; // @[InputUnit.scala:86:24, :122:27] if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_0 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_1 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_2 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_3) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_3 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_4) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_4 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_5) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_5 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_6) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_6 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & (&io_enq_0_bits_virt_channel_id)) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_7 <= _tails_T_49; // @[InputUnit.scala:87:24, :103:51] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module Queue1_RegMapperInput_i9_m8_3 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<7>, size : UInt<3>}}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<7>, size : UInt<3>}}}}, count : UInt<1>} cmem ram : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<7>, size : UInt<3>}}} [1] wire enq_ptr_value : UInt connect enq_ptr_value, UInt<1>(0h0) wire deq_ptr_value : UInt connect deq_ptr_value, UInt<1>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _empty_T = eq(maybe_full, UInt<1>(0h0)) node empty = and(ptr_match, _empty_T) node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> connect do_enq, _do_enq_T node _do_deq_T = and(io.deq.ready, io.deq.valid) wire do_deq : UInt<1> connect do_deq, _do_deq_T when do_enq : wire _WIRE : UInt connect _WIRE, UInt<1>(0h0) infer mport MPORT = ram[_WIRE], clock connect MPORT.extra, io.enq.bits.extra connect MPORT.mask, io.enq.bits.mask connect MPORT.data, io.enq.bits.data connect MPORT.index, io.enq.bits.index connect MPORT.read, io.enq.bits.read when do_deq : skip node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq when UInt<1>(0h0) : connect enq_ptr_value, UInt<1>(0h0) connect deq_ptr_value, UInt<1>(0h0) connect maybe_full, UInt<1>(0h0) node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire _io_deq_bits_WIRE : UInt connect _io_deq_bits_WIRE, UInt<1>(0h0) infer mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock connect io.deq.bits, io_deq_bits_MPORT node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = and(maybe_full, ptr_match) node _io_count_T_1 = mux(_io_count_T, UInt<1>(0h1), UInt<1>(0h0)) node _io_count_T_2 = or(_io_count_T_1, ptr_diff) connect io.count, _io_count_T_2	module Queue1_RegMapperInput_i9_m8_3( // @[RegMapper.scala:71:32] input clock, // @[RegMapper.scala:71:32] input reset, // @[RegMapper.scala:71:32] output io_enq_ready, // @[Decoupled.scala:255:14] input io_enq_valid, // @[Decoupled.scala:255:14] input io_enq_bits_read, // @[Decoupled.scala:255:14] input [8:0] io_enq_bits_index, // @[Decoupled.scala:255:14] input [63:0] io_enq_bits_data, // @[Decoupled.scala:255:14] input [7:0] io_enq_bits_mask, // @[Decoupled.scala:255:14] input [6:0] io_enq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14] input [2:0] io_enq_bits_extra_tlrr_extra_size, // @[Decoupled.scala:255:14] input io_deq_ready, // @[Decoupled.scala:255:14] output io_deq_valid, // @[Decoupled.scala:255:14] output io_deq_bits_read, // @[Decoupled.scala:255:14] output [8:0] io_deq_bits_index, // @[Decoupled.scala:255:14] output [63:0] io_deq_bits_data, // @[Decoupled.scala:255:14] output [7:0] io_deq_bits_mask, // @[Decoupled.scala:255:14] output [6:0] io_deq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14] output [2:0] io_deq_bits_extra_tlrr_extra_size // @[Decoupled.scala:255:14] ); wire io_enq_valid_0 = io_enq_valid; // @[RegMapper.scala:71:32] wire io_enq_bits_read_0 = io_enq_bits_read; // @[RegMapper.scala:71:32] wire [8:0] io_enq_bits_index_0 = io_enq_bits_index; // @[RegMapper.scala:71:32] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[RegMapper.scala:71:32] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[RegMapper.scala:71:32] wire [6:0] io_enq_bits_extra_tlrr_extra_source_0 = io_enq_bits_extra_tlrr_extra_source; // @[RegMapper.scala:71:32] wire [2:0] io_enq_bits_extra_tlrr_extra_size_0 = io_enq_bits_extra_tlrr_extra_size; // @[RegMapper.scala:71:32] wire io_deq_ready_0 = io_deq_ready; // @[RegMapper.scala:71:32] wire ptr_match = 1'h1; // @[Decoupled.scala:260:33] wire [1:0] _ptr_diff_T = 2'h0; // @[Decoupled.scala:309:32] wire enq_ptr_value = 1'h0; // @[Counter.scala:61:73] wire deq_ptr_value = 1'h0; // @[Counter.scala:61:73] wire _io_enq_ready_T; // @[Decoupled.scala:286:19] wire _io_deq_bits_WIRE = 1'h0; // @[Decoupled.scala:293:23] wire ptr_diff = 1'h0; // @[Decoupled.scala:309:32] wire _io_deq_valid_T; // @[Decoupled.scala:285:19] wire _io_count_T_2; // @[Decoupled.scala:312:62] wire io_enq_ready_0; // @[RegMapper.scala:71:32] wire [6:0] io_deq_bits_extra_tlrr_extra_source_0; // @[RegMapper.scala:71:32] wire [2:0] io_deq_bits_extra_tlrr_extra_size_0; // @[RegMapper.scala:71:32] wire io_deq_bits_read_0; // @[RegMapper.scala:71:32] wire [8:0] io_deq_bits_index_0; // @[RegMapper.scala:71:32] wire [63:0] io_deq_bits_data_0; // @[RegMapper.scala:71:32] wire [7:0] io_deq_bits_mask_0; // @[RegMapper.scala:71:32] wire io_deq_valid_0; // @[RegMapper.scala:71:32] wire io_count; // @[RegMapper.scala:71:32] reg [91:0] ram; // @[Decoupled.scala:256:91] assign io_deq_bits_read_0 = ram[0]; // @[Decoupled.scala:256:91] assign io_deq_bits_index_0 = ram[9:1]; // @[Decoupled.scala:256:91] assign io_deq_bits_data_0 = ram[73:10]; // @[Decoupled.scala:256:91] assign io_deq_bits_mask_0 = ram[81:74]; // @[Decoupled.scala:256:91] assign io_deq_bits_extra_tlrr_extra_source_0 = ram[88:82]; // @[Decoupled.scala:256:91] assign io_deq_bits_extra_tlrr_extra_size_0 = ram[91:89]; // @[Decoupled.scala:256:91] reg maybe_full; // @[Decoupled.scala:259:27] wire full = maybe_full; // @[Decoupled.scala:259:27, :262:24] wire _io_count_T = maybe_full; // @[Decoupled.scala:259:27, :312:32] wire _empty_T = ~maybe_full; // @[Decoupled.scala:259:27, :261:28] wire empty = _empty_T; // @[Decoupled.scala:261:{25,28}] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35, :263:27] wire _do_deq_T = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35] wire do_deq = _do_deq_T; // @[Decoupled.scala:51:35, :264:27] assign _io_deq_valid_T = ~empty; // @[Decoupled.scala:261:25, :285:19] assign io_deq_valid_0 = _io_deq_valid_T; // @[Decoupled.scala:285:19] assign _io_enq_ready_T = ~full; // @[Decoupled.scala:262:24, :286:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[Decoupled.scala:286:19] wire _io_count_T_1 = _io_count_T; // @[Decoupled.scala:312:{20,32}] assign _io_count_T_2 = _io_count_T_1; // @[Decoupled.scala:312:{20,62}] assign io_count = _io_count_T_2; // @[Decoupled.scala:312:62] always @(posedge clock) begin // @[RegMapper.scala:71:32] if (do_enq) // @[Decoupled.scala:263:27] ram <= {io_enq_bits_extra_tlrr_extra_size_0, io_enq_bits_extra_tlrr_extra_source_0, io_enq_bits_mask_0, io_enq_bits_data_0, io_enq_bits_index_0, io_enq_bits_read_0}; // @[Decoupled.scala:256:91] if (reset) // @[RegMapper.scala:71:32] maybe_full <= 1'h0; // @[Decoupled.scala:259:27] else if (~(do_enq == do_deq)) // @[Decoupled.scala:259:27, :263:27, :264:27, :276:{15,27}, :277:16] maybe_full <= do_enq; // @[Decoupled.scala:259:27, :263:27] always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[RegMapper.scala:71:32] assign io_deq_valid = io_deq_valid_0; // @[RegMapper.scala:71:32] assign io_deq_bits_read = io_deq_bits_read_0; // @[RegMapper.scala:71:32] assign io_deq_bits_index = io_deq_bits_index_0; // @[RegMapper.scala:71:32] assign io_deq_bits_data = io_deq_bits_data_0; // @[RegMapper.scala:71:32] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[RegMapper.scala:71:32] assign io_deq_bits_extra_tlrr_extra_source = io_deq_bits_extra_tlrr_extra_source_0; // @[RegMapper.scala:71:32] assign io_deq_bits_extra_tlrr_extra_size = io_deq_bits_extra_tlrr_extra_size_0; // @[RegMapper.scala:71:32] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_60 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData_60( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a29d64s8k1z4u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_30 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a29d64s8k1z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a29d64s8k1z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_94 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_95 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLBuffer_a29d64s8k1z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [7:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_30 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a29d64s8k1z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a29d64s8k1z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRawFN_small_e8_s24_3 : input clock : Clock input reset : Reset output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} regreset cycleNum : UInt<5>, clock, reset, UInt<5>(0h0) regreset inReady : UInt<1>, clock, reset, UInt<1>(0h1) regreset rawOutValid : UInt<1>, clock, reset, UInt<1>(0h0) reg sqrtOp_Z : UInt<1>, clock reg majorExc_Z : UInt<1>, clock reg isNaN_Z : UInt<1>, clock reg isInf_Z : UInt<1>, clock reg isZero_Z : UInt<1>, clock reg sign_Z : UInt<1>, clock reg sExp_Z : SInt<10>, clock reg fractB_Z : UInt<24>, clock reg roundingMode_Z : UInt<3>, clock reg rem_Z : UInt<26>, clock reg notZeroRem_Z : UInt<1>, clock reg sigX_Z : UInt<26>, clock node _notSigNaNIn_invalidExc_S_div_T = and(io.a.isZero, io.b.isZero) node _notSigNaNIn_invalidExc_S_div_T_1 = and(io.a.isInf, io.b.isInf) node notSigNaNIn_invalidExc_S_div = or(_notSigNaNIn_invalidExc_S_div_T, _notSigNaNIn_invalidExc_S_div_T_1) node _notSigNaNIn_invalidExc_S_sqrt_T = eq(io.a.isNaN, UInt<1>(0h0)) node _notSigNaNIn_invalidExc_S_sqrt_T_1 = eq(io.a.isZero, UInt<1>(0h0)) node _notSigNaNIn_invalidExc_S_sqrt_T_2 = and(_notSigNaNIn_invalidExc_S_sqrt_T, _notSigNaNIn_invalidExc_S_sqrt_T_1) node notSigNaNIn_invalidExc_S_sqrt = and(_notSigNaNIn_invalidExc_S_sqrt_T_2, io.a.sign) node _majorExc_S_T = bits(io.a.sig, 22, 22) node _majorExc_S_T_1 = eq(_majorExc_S_T, UInt<1>(0h0)) node _majorExc_S_T_2 = and(io.a.isNaN, _majorExc_S_T_1) node _majorExc_S_T_3 = or(_majorExc_S_T_2, notSigNaNIn_invalidExc_S_sqrt) node _majorExc_S_T_4 = bits(io.a.sig, 22, 22) node _majorExc_S_T_5 = eq(_majorExc_S_T_4, UInt<1>(0h0)) node _majorExc_S_T_6 = and(io.a.isNaN, _majorExc_S_T_5) node _majorExc_S_T_7 = bits(io.b.sig, 22, 22) node _majorExc_S_T_8 = eq(_majorExc_S_T_7, UInt<1>(0h0)) node _majorExc_S_T_9 = and(io.b.isNaN, _majorExc_S_T_8) node _majorExc_S_T_10 = or(_majorExc_S_T_6, _majorExc_S_T_9) node _majorExc_S_T_11 = or(_majorExc_S_T_10, notSigNaNIn_invalidExc_S_div) node _majorExc_S_T_12 = eq(io.a.isNaN, UInt<1>(0h0)) node _majorExc_S_T_13 = eq(io.a.isInf, UInt<1>(0h0)) node _majorExc_S_T_14 = and(_majorExc_S_T_12, _majorExc_S_T_13) node _majorExc_S_T_15 = and(_majorExc_S_T_14, io.b.isZero) node _majorExc_S_T_16 = or(_majorExc_S_T_11, _majorExc_S_T_15) node majorExc_S = mux(io.sqrtOp, _majorExc_S_T_3, _majorExc_S_T_16) node _isNaN_S_T = or(io.a.isNaN, notSigNaNIn_invalidExc_S_sqrt) node _isNaN_S_T_1 = or(io.a.isNaN, io.b.isNaN) node _isNaN_S_T_2 = or(_isNaN_S_T_1, notSigNaNIn_invalidExc_S_div) node isNaN_S = mux(io.sqrtOp, _isNaN_S_T, _isNaN_S_T_2) node _isInf_S_T = or(io.a.isInf, io.b.isZero) node isInf_S = mux(io.sqrtOp, io.a.isInf, _isInf_S_T) node _isZero_S_T = or(io.a.isZero, io.b.isInf) node isZero_S = mux(io.sqrtOp, io.a.isZero, _isZero_S_T) node _sign_S_T = eq(io.sqrtOp, UInt<1>(0h0)) node _sign_S_T_1 = and(_sign_S_T, io.b.sign) node sign_S = xor(io.a.sign, _sign_S_T_1) node _specialCaseA_S_T = or(io.a.isNaN, io.a.isInf) node specialCaseA_S = or(_specialCaseA_S_T, io.a.isZero) node _specialCaseB_S_T = or(io.b.isNaN, io.b.isInf) node specialCaseB_S = or(_specialCaseB_S_T, io.b.isZero) node _normalCase_S_div_T = eq(specialCaseA_S, UInt<1>(0h0)) node _normalCase_S_div_T_1 = eq(specialCaseB_S, UInt<1>(0h0)) node normalCase_S_div = and(_normalCase_S_div_T, _normalCase_S_div_T_1) node _normalCase_S_sqrt_T = eq(specialCaseA_S, UInt<1>(0h0)) node _normalCase_S_sqrt_T_1 = eq(io.a.sign, UInt<1>(0h0)) node normalCase_S_sqrt = and(_normalCase_S_sqrt_T, _normalCase_S_sqrt_T_1) node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) node _sExpQuot_S_div_T = bits(io.b.sExp, 8, 8) node _sExpQuot_S_div_T_1 = bits(io.b.sExp, 7, 0) node _sExpQuot_S_div_T_2 = not(_sExpQuot_S_div_T_1) node _sExpQuot_S_div_T_3 = cat(_sExpQuot_S_div_T, _sExpQuot_S_div_T_2) node _sExpQuot_S_div_T_4 = asSInt(_sExpQuot_S_div_T_3) node sExpQuot_S_div = add(io.a.sExp, _sExpQuot_S_div_T_4) node _sSatExpQuot_S_div_T = leq(asSInt(UInt<10>(0h1c0)), sExpQuot_S_div) node _sSatExpQuot_S_div_T_1 = bits(sExpQuot_S_div, 9, 6) node _sSatExpQuot_S_div_T_2 = mux(_sSatExpQuot_S_div_T, UInt<3>(0h6), _sSatExpQuot_S_div_T_1) node _sSatExpQuot_S_div_T_3 = bits(sExpQuot_S_div, 5, 0) node _sSatExpQuot_S_div_T_4 = cat(_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3) node sSatExpQuot_S_div = asSInt(_sSatExpQuot_S_div_T_4) node _evenSqrt_S_T = bits(io.a.sExp, 0, 0) node _evenSqrt_S_T_1 = eq(_evenSqrt_S_T, UInt<1>(0h0)) node evenSqrt_S = and(io.sqrtOp, _evenSqrt_S_T_1) node _oddSqrt_S_T = bits(io.a.sExp, 0, 0) node oddSqrt_S = and(io.sqrtOp, _oddSqrt_S_T) node idle = eq(cycleNum, UInt<1>(0h0)) node entering = and(inReady, io.inValid) node entering_normalCase = and(entering, normalCase_S) node _processTwoBits_T = geq(cycleNum, UInt<2>(0h3)) node processTwoBits = and(_processTwoBits_T, UInt<1>(0h0)) node _skipCycle2_T = eq(cycleNum, UInt<2>(0h3)) node _skipCycle2_T_1 = bits(sigX_Z, 25, 25) node _skipCycle2_T_2 = and(_skipCycle2_T, _skipCycle2_T_1) node skipCycle2 = and(_skipCycle2_T_2, UInt<1>(0h1)) node _T = eq(idle, UInt<1>(0h0)) node _T_1 = or(_T, entering) when _T_1 : node _inReady_T = eq(normalCase_S, UInt<1>(0h0)) node _inReady_T_1 = and(entering, _inReady_T) node _inReady_T_2 = leq(UInt<1>(0h1), UInt<1>(0h1)) node _inReady_T_3 = mux(_inReady_T_1, _inReady_T_2, UInt<1>(0h0)) node _inReady_T_4 = bits(io.a.sExp, 0, 0) node _inReady_T_5 = leq(UInt<5>(0h18), UInt<1>(0h1)) node _inReady_T_6 = leq(UInt<5>(0h19), UInt<1>(0h1)) node _inReady_T_7 = mux(_inReady_T_4, _inReady_T_5, _inReady_T_6) node _inReady_T_8 = leq(UInt<5>(0h1a), UInt<1>(0h1)) node _inReady_T_9 = mux(io.sqrtOp, _inReady_T_7, _inReady_T_8) node _inReady_T_10 = mux(entering_normalCase, _inReady_T_9, UInt<1>(0h0)) node _inReady_T_11 = or(_inReady_T_3, _inReady_T_10) node _inReady_T_12 = eq(entering, UInt<1>(0h0)) node _inReady_T_13 = eq(skipCycle2, UInt<1>(0h0)) node _inReady_T_14 = and(_inReady_T_12, _inReady_T_13) node _inReady_T_15 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1)) node _inReady_T_16 = sub(cycleNum, _inReady_T_15) node _inReady_T_17 = tail(_inReady_T_16, 1) node _inReady_T_18 = leq(_inReady_T_17, UInt<1>(0h1)) node _inReady_T_19 = mux(_inReady_T_14, _inReady_T_18, UInt<1>(0h0)) node _inReady_T_20 = or(_inReady_T_11, _inReady_T_19) node _inReady_T_21 = leq(UInt<1>(0h1), UInt<1>(0h1)) node _inReady_T_22 = mux(skipCycle2, _inReady_T_21, UInt<1>(0h0)) node _inReady_T_23 = or(_inReady_T_20, _inReady_T_22) node _inReady_T_24 = bits(_inReady_T_23, 0, 0) connect inReady, _inReady_T_24 node _rawOutValid_T = eq(normalCase_S, UInt<1>(0h0)) node _rawOutValid_T_1 = and(entering, _rawOutValid_T) node _rawOutValid_T_2 = eq(UInt<1>(0h1), UInt<1>(0h1)) node _rawOutValid_T_3 = mux(_rawOutValid_T_1, _rawOutValid_T_2, UInt<1>(0h0)) node _rawOutValid_T_4 = bits(io.a.sExp, 0, 0) node _rawOutValid_T_5 = eq(UInt<5>(0h18), UInt<1>(0h1)) node _rawOutValid_T_6 = eq(UInt<5>(0h19), UInt<1>(0h1)) node _rawOutValid_T_7 = mux(_rawOutValid_T_4, _rawOutValid_T_5, _rawOutValid_T_6) node _rawOutValid_T_8 = eq(UInt<5>(0h1a), UInt<1>(0h1)) node _rawOutValid_T_9 = mux(io.sqrtOp, _rawOutValid_T_7, _rawOutValid_T_8) node _rawOutValid_T_10 = mux(entering_normalCase, _rawOutValid_T_9, UInt<1>(0h0)) node _rawOutValid_T_11 = or(_rawOutValid_T_3, _rawOutValid_T_10) node _rawOutValid_T_12 = eq(entering, UInt<1>(0h0)) node _rawOutValid_T_13 = eq(skipCycle2, UInt<1>(0h0)) node _rawOutValid_T_14 = and(_rawOutValid_T_12, _rawOutValid_T_13) node _rawOutValid_T_15 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1)) node _rawOutValid_T_16 = sub(cycleNum, _rawOutValid_T_15) node _rawOutValid_T_17 = tail(_rawOutValid_T_16, 1) node _rawOutValid_T_18 = eq(_rawOutValid_T_17, UInt<1>(0h1)) node _rawOutValid_T_19 = mux(_rawOutValid_T_14, _rawOutValid_T_18, UInt<1>(0h0)) node _rawOutValid_T_20 = or(_rawOutValid_T_11, _rawOutValid_T_19) node _rawOutValid_T_21 = eq(UInt<1>(0h1), UInt<1>(0h1)) node _rawOutValid_T_22 = mux(skipCycle2, _rawOutValid_T_21, UInt<1>(0h0)) node _rawOutValid_T_23 = or(_rawOutValid_T_20, _rawOutValid_T_22) node _rawOutValid_T_24 = bits(_rawOutValid_T_23, 0, 0) connect rawOutValid, _rawOutValid_T_24 node _cycleNum_T = eq(normalCase_S, UInt<1>(0h0)) node _cycleNum_T_1 = and(entering, _cycleNum_T) node _cycleNum_T_2 = mux(_cycleNum_T_1, UInt<1>(0h1), UInt<1>(0h0)) node _cycleNum_T_3 = bits(io.a.sExp, 0, 0) node _cycleNum_T_4 = mux(_cycleNum_T_3, UInt<5>(0h18), UInt<5>(0h19)) node _cycleNum_T_5 = mux(io.sqrtOp, _cycleNum_T_4, UInt<5>(0h1a)) node _cycleNum_T_6 = mux(entering_normalCase, _cycleNum_T_5, UInt<1>(0h0)) node _cycleNum_T_7 = or(_cycleNum_T_2, _cycleNum_T_6) node _cycleNum_T_8 = eq(entering, UInt<1>(0h0)) node _cycleNum_T_9 = eq(skipCycle2, UInt<1>(0h0)) node _cycleNum_T_10 = and(_cycleNum_T_8, _cycleNum_T_9) node _cycleNum_T_11 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1)) node _cycleNum_T_12 = sub(cycleNum, _cycleNum_T_11) node _cycleNum_T_13 = tail(_cycleNum_T_12, 1) node _cycleNum_T_14 = mux(_cycleNum_T_10, _cycleNum_T_13, UInt<1>(0h0)) node _cycleNum_T_15 = or(_cycleNum_T_7, _cycleNum_T_14) node _cycleNum_T_16 = mux(skipCycle2, UInt<1>(0h1), UInt<1>(0h0)) node _cycleNum_T_17 = or(_cycleNum_T_15, _cycleNum_T_16) connect cycleNum, _cycleNum_T_17 connect io.inReady, inReady when entering : connect sqrtOp_Z, io.sqrtOp connect majorExc_Z, majorExc_S connect isNaN_Z, isNaN_S connect isInf_Z, isInf_S connect isZero_Z, isZero_S connect sign_Z, sign_S node _sExp_Z_T = shr(io.a.sExp, 1) node _sExp_Z_T_1 = add(_sExp_Z_T, asSInt(UInt<9>(0h80))) node _sExp_Z_T_2 = mux(io.sqrtOp, _sExp_Z_T_1, sSatExpQuot_S_div) connect sExp_Z, _sExp_Z_T_2 connect roundingMode_Z, io.roundingMode node _T_2 = eq(inReady, UInt<1>(0h0)) node _T_3 = and(_T_2, sqrtOp_Z) node _T_4 = or(entering, _T_3) when _T_4 : node _fractB_Z_T = eq(io.sqrtOp, UInt<1>(0h0)) node _fractB_Z_T_1 = and(inReady, _fractB_Z_T) node _fractB_Z_T_2 = bits(io.b.sig, 22, 0) node _fractB_Z_T_3 = shl(_fractB_Z_T_2, 1) node _fractB_Z_T_4 = mux(_fractB_Z_T_1, _fractB_Z_T_3, UInt<1>(0h0)) node _fractB_Z_T_5 = and(inReady, io.sqrtOp) node _fractB_Z_T_6 = bits(io.a.sExp, 0, 0) node _fractB_Z_T_7 = and(_fractB_Z_T_5, _fractB_Z_T_6) node _fractB_Z_T_8 = mux(_fractB_Z_T_7, UInt<23>(0h400000), UInt<1>(0h0)) node _fractB_Z_T_9 = or(_fractB_Z_T_4, _fractB_Z_T_8) node _fractB_Z_T_10 = and(inReady, io.sqrtOp) node _fractB_Z_T_11 = bits(io.a.sExp, 0, 0) node _fractB_Z_T_12 = eq(_fractB_Z_T_11, UInt<1>(0h0)) node _fractB_Z_T_13 = and(_fractB_Z_T_10, _fractB_Z_T_12) node _fractB_Z_T_14 = mux(_fractB_Z_T_13, UInt<24>(0h800000), UInt<1>(0h0)) node _fractB_Z_T_15 = or(_fractB_Z_T_9, _fractB_Z_T_14) node _fractB_Z_T_16 = eq(inReady, UInt<1>(0h0)) node _fractB_Z_T_17 = and(_fractB_Z_T_16, processTwoBits) node _fractB_Z_T_18 = shr(fractB_Z, 2) node _fractB_Z_T_19 = mux(_fractB_Z_T_17, _fractB_Z_T_18, UInt<1>(0h0)) node _fractB_Z_T_20 = or(_fractB_Z_T_15, _fractB_Z_T_19) node _fractB_Z_T_21 = eq(inReady, UInt<1>(0h0)) node _fractB_Z_T_22 = eq(processTwoBits, UInt<1>(0h0)) node _fractB_Z_T_23 = and(_fractB_Z_T_21, _fractB_Z_T_22) node _fractB_Z_T_24 = shr(fractB_Z, 1) node _fractB_Z_T_25 = mux(_fractB_Z_T_23, _fractB_Z_T_24, UInt<1>(0h0)) node _fractB_Z_T_26 = or(_fractB_Z_T_20, _fractB_Z_T_25) connect fractB_Z, _fractB_Z_T_26 node _rem_T = eq(oddSqrt_S, UInt<1>(0h0)) node _rem_T_1 = and(inReady, _rem_T) node _rem_T_2 = shl(io.a.sig, 1) node _rem_T_3 = mux(_rem_T_1, _rem_T_2, UInt<1>(0h0)) node _rem_T_4 = and(inReady, oddSqrt_S) node _rem_T_5 = bits(io.a.sig, 23, 22) node _rem_T_6 = sub(_rem_T_5, UInt<1>(0h1)) node _rem_T_7 = tail(_rem_T_6, 1) node _rem_T_8 = bits(io.a.sig, 21, 0) node _rem_T_9 = shl(_rem_T_8, 3) node _rem_T_10 = cat(_rem_T_7, _rem_T_9) node _rem_T_11 = mux(_rem_T_4, _rem_T_10, UInt<1>(0h0)) node _rem_T_12 = or(_rem_T_3, _rem_T_11) node _rem_T_13 = eq(inReady, UInt<1>(0h0)) node _rem_T_14 = shl(rem_Z, 1) node _rem_T_15 = mux(_rem_T_13, _rem_T_14, UInt<1>(0h0)) node rem = or(_rem_T_12, _rem_T_15) node _bitMask_T = dshl(UInt<1>(0h1), cycleNum) node bitMask = shr(_bitMask_T, 2) node _trialTerm_T = eq(io.sqrtOp, UInt<1>(0h0)) node _trialTerm_T_1 = and(inReady, _trialTerm_T) node _trialTerm_T_2 = shl(io.b.sig, 1) node _trialTerm_T_3 = mux(_trialTerm_T_1, _trialTerm_T_2, UInt<1>(0h0)) node _trialTerm_T_4 = and(inReady, evenSqrt_S) node _trialTerm_T_5 = mux(_trialTerm_T_4, UInt<25>(0h1000000), UInt<1>(0h0)) node _trialTerm_T_6 = or(_trialTerm_T_3, _trialTerm_T_5) node _trialTerm_T_7 = and(inReady, oddSqrt_S) node _trialTerm_T_8 = mux(_trialTerm_T_7, UInt<26>(0h2800000), UInt<1>(0h0)) node _trialTerm_T_9 = or(_trialTerm_T_6, _trialTerm_T_8) node _trialTerm_T_10 = eq(inReady, UInt<1>(0h0)) node _trialTerm_T_11 = mux(_trialTerm_T_10, fractB_Z, UInt<1>(0h0)) node _trialTerm_T_12 = or(_trialTerm_T_9, _trialTerm_T_11) node _trialTerm_T_13 = eq(inReady, UInt<1>(0h0)) node _trialTerm_T_14 = eq(sqrtOp_Z, UInt<1>(0h0)) node _trialTerm_T_15 = and(_trialTerm_T_13, _trialTerm_T_14) node _trialTerm_T_16 = shl(UInt<1>(0h1), 24) node _trialTerm_T_17 = mux(_trialTerm_T_15, _trialTerm_T_16, UInt<1>(0h0)) node _trialTerm_T_18 = or(_trialTerm_T_12, _trialTerm_T_17) node _trialTerm_T_19 = eq(inReady, UInt<1>(0h0)) node _trialTerm_T_20 = and(_trialTerm_T_19, sqrtOp_Z) node _trialTerm_T_21 = shl(sigX_Z, 1) node _trialTerm_T_22 = mux(_trialTerm_T_20, _trialTerm_T_21, UInt<1>(0h0)) node trialTerm = or(_trialTerm_T_18, _trialTerm_T_22) node _trialRem_T = cvt(rem) node _trialRem_T_1 = cvt(trialTerm) node trialRem = sub(_trialRem_T, _trialRem_T_1) node newBit = leq(asSInt(UInt<1>(0h0)), trialRem) node _nextRem_Z_T = asUInt(trialRem) node _nextRem_Z_T_1 = mux(newBit, _nextRem_Z_T, rem) node nextRem_Z = bits(_nextRem_Z_T_1, 25, 0) node rem2 = shl(nextRem_Z, 1) node _trialTerm2_newBit0_T = shr(fractB_Z, 1) node _trialTerm2_newBit0_T_1 = shl(sigX_Z, 1) node _trialTerm2_newBit0_T_2 = or(_trialTerm2_newBit0_T, _trialTerm2_newBit0_T_1) node _trialTerm2_newBit0_T_3 = shl(UInt<1>(0h1), 24) node _trialTerm2_newBit0_T_4 = or(fractB_Z, _trialTerm2_newBit0_T_3) node trialTerm2_newBit0 = mux(sqrtOp_Z, _trialTerm2_newBit0_T_2, _trialTerm2_newBit0_T_4) node _trialTerm2_newBit1_T = shl(fractB_Z, 1) node _trialTerm2_newBit1_T_1 = mux(sqrtOp_Z, _trialTerm2_newBit1_T, UInt<1>(0h0)) node trialTerm2_newBit1 = or(trialTerm2_newBit0, _trialTerm2_newBit1_T_1) node _trialRem2_T = shl(trialRem, 1) node _trialRem2_T_1 = cvt(trialTerm2_newBit1) node _trialRem2_T_2 = sub(_trialRem2_T, _trialRem2_T_1) node _trialRem2_T_3 = tail(_trialRem2_T_2, 1) node _trialRem2_T_4 = asSInt(_trialRem2_T_3) node _trialRem2_T_5 = shl(rem_Z, 2) node _trialRem2_T_6 = bits(_trialRem2_T_5, 26, 0) node _trialRem2_T_7 = cvt(_trialRem2_T_6) node _trialRem2_T_8 = cvt(trialTerm2_newBit0) node _trialRem2_T_9 = sub(_trialRem2_T_7, _trialRem2_T_8) node _trialRem2_T_10 = tail(_trialRem2_T_9, 1) node _trialRem2_T_11 = asSInt(_trialRem2_T_10) node trialRem2 = mux(newBit, _trialRem2_T_4, _trialRem2_T_11) node newBit2 = leq(asSInt(UInt<1>(0h0)), trialRem2) node _nextNotZeroRem_Z_T = or(inReady, newBit) node _nextNotZeroRem_Z_T_1 = neq(trialRem, asSInt(UInt<1>(0h0))) node nextNotZeroRem_Z = mux(_nextNotZeroRem_Z_T, _nextNotZeroRem_Z_T_1, notZeroRem_Z) node _nextNotZeroRem_Z_2_T = and(processTwoBits, newBit) node _nextNotZeroRem_Z_2_T_1 = shl(trialRem, 1) node _nextNotZeroRem_Z_2_T_2 = cvt(trialTerm2_newBit1) node _nextNotZeroRem_Z_2_T_3 = sub(_nextNotZeroRem_Z_2_T_1, _nextNotZeroRem_Z_2_T_2) node _nextNotZeroRem_Z_2_T_4 = tail(_nextNotZeroRem_Z_2_T_3, 1) node _nextNotZeroRem_Z_2_T_5 = asSInt(_nextNotZeroRem_Z_2_T_4) node _nextNotZeroRem_Z_2_T_6 = lt(asSInt(UInt<1>(0h0)), _nextNotZeroRem_Z_2_T_5) node _nextNotZeroRem_Z_2_T_7 = and(_nextNotZeroRem_Z_2_T, _nextNotZeroRem_Z_2_T_6) node _nextNotZeroRem_Z_2_T_8 = eq(newBit, UInt<1>(0h0)) node _nextNotZeroRem_Z_2_T_9 = and(processTwoBits, _nextNotZeroRem_Z_2_T_8) node _nextNotZeroRem_Z_2_T_10 = shl(rem_Z, 2) node _nextNotZeroRem_Z_2_T_11 = bits(_nextNotZeroRem_Z_2_T_10, 26, 0) node _nextNotZeroRem_Z_2_T_12 = cvt(_nextNotZeroRem_Z_2_T_11) node _nextNotZeroRem_Z_2_T_13 = cvt(trialTerm2_newBit0) node _nextNotZeroRem_Z_2_T_14 = sub(_nextNotZeroRem_Z_2_T_12, _nextNotZeroRem_Z_2_T_13) node _nextNotZeroRem_Z_2_T_15 = tail(_nextNotZeroRem_Z_2_T_14, 1) node _nextNotZeroRem_Z_2_T_16 = asSInt(_nextNotZeroRem_Z_2_T_15) node _nextNotZeroRem_Z_2_T_17 = lt(asSInt(UInt<1>(0h0)), _nextNotZeroRem_Z_2_T_16) node _nextNotZeroRem_Z_2_T_18 = and(_nextNotZeroRem_Z_2_T_9, _nextNotZeroRem_Z_2_T_17) node _nextNotZeroRem_Z_2_T_19 = or(_nextNotZeroRem_Z_2_T_7, _nextNotZeroRem_Z_2_T_18) node _nextNotZeroRem_Z_2_T_20 = and(processTwoBits, newBit2) node _nextNotZeroRem_Z_2_T_21 = eq(_nextNotZeroRem_Z_2_T_20, UInt<1>(0h0)) node _nextNotZeroRem_Z_2_T_22 = and(_nextNotZeroRem_Z_2_T_21, nextNotZeroRem_Z) node nextNotZeroRem_Z_2 = or(_nextNotZeroRem_Z_2_T_19, _nextNotZeroRem_Z_2_T_22) node _nextRem_Z_2_T = and(processTwoBits, newBit2) node _nextRem_Z_2_T_1 = asUInt(trialRem2) node _nextRem_Z_2_T_2 = bits(_nextRem_Z_2_T_1, 25, 0) node _nextRem_Z_2_T_3 = mux(_nextRem_Z_2_T, _nextRem_Z_2_T_2, UInt<1>(0h0)) node _nextRem_Z_2_T_4 = eq(newBit2, UInt<1>(0h0)) node _nextRem_Z_2_T_5 = and(processTwoBits, _nextRem_Z_2_T_4) node _nextRem_Z_2_T_6 = bits(rem2, 25, 0) node _nextRem_Z_2_T_7 = mux(_nextRem_Z_2_T_5, _nextRem_Z_2_T_6, UInt<1>(0h0)) node _nextRem_Z_2_T_8 = or(_nextRem_Z_2_T_3, _nextRem_Z_2_T_7) node _nextRem_Z_2_T_9 = eq(processTwoBits, UInt<1>(0h0)) node _nextRem_Z_2_T_10 = mux(_nextRem_Z_2_T_9, nextRem_Z, UInt<1>(0h0)) node nextRem_Z_2 = or(_nextRem_Z_2_T_8, _nextRem_Z_2_T_10) node _T_5 = eq(inReady, UInt<1>(0h0)) node _T_6 = or(entering, _T_5) when _T_6 : connect notZeroRem_Z, nextNotZeroRem_Z_2 connect rem_Z, nextRem_Z_2 node _sigX_Z_T = eq(io.sqrtOp, UInt<1>(0h0)) node _sigX_Z_T_1 = and(inReady, _sigX_Z_T) node _sigX_Z_T_2 = shl(newBit, 25) node _sigX_Z_T_3 = mux(_sigX_Z_T_1, _sigX_Z_T_2, UInt<1>(0h0)) node _sigX_Z_T_4 = and(inReady, io.sqrtOp) node _sigX_Z_T_5 = mux(_sigX_Z_T_4, UInt<25>(0h1000000), UInt<1>(0h0)) node _sigX_Z_T_6 = or(_sigX_Z_T_3, _sigX_Z_T_5) node _sigX_Z_T_7 = and(inReady, oddSqrt_S) node _sigX_Z_T_8 = shl(newBit, 23) node _sigX_Z_T_9 = mux(_sigX_Z_T_7, _sigX_Z_T_8, UInt<1>(0h0)) node _sigX_Z_T_10 = or(_sigX_Z_T_6, _sigX_Z_T_9) node _sigX_Z_T_11 = eq(inReady, UInt<1>(0h0)) node _sigX_Z_T_12 = mux(_sigX_Z_T_11, sigX_Z, UInt<1>(0h0)) node _sigX_Z_T_13 = or(_sigX_Z_T_10, _sigX_Z_T_12) node _sigX_Z_T_14 = eq(inReady, UInt<1>(0h0)) node _sigX_Z_T_15 = and(_sigX_Z_T_14, newBit) node _sigX_Z_T_16 = mux(_sigX_Z_T_15, bitMask, UInt<1>(0h0)) node _sigX_Z_T_17 = or(_sigX_Z_T_13, _sigX_Z_T_16) node _sigX_Z_T_18 = and(processTwoBits, newBit2) node _sigX_Z_T_19 = shr(bitMask, 1) node _sigX_Z_T_20 = mux(_sigX_Z_T_18, _sigX_Z_T_19, UInt<1>(0h0)) node _sigX_Z_T_21 = or(_sigX_Z_T_17, _sigX_Z_T_20) connect sigX_Z, _sigX_Z_T_21 node _io_rawOutValid_div_T = eq(sqrtOp_Z, UInt<1>(0h0)) node _io_rawOutValid_div_T_1 = and(rawOutValid, _io_rawOutValid_div_T) connect io.rawOutValid_div, _io_rawOutValid_div_T_1 node _io_rawOutValid_sqrt_T = and(rawOutValid, sqrtOp_Z) connect io.rawOutValid_sqrt, _io_rawOutValid_sqrt_T connect io.roundingModeOut, roundingMode_Z node _io_invalidExc_T = and(majorExc_Z, isNaN_Z) connect io.invalidExc, _io_invalidExc_T node _io_infiniteExc_T = eq(isNaN_Z, UInt<1>(0h0)) node _io_infiniteExc_T_1 = and(majorExc_Z, _io_infiniteExc_T) connect io.infiniteExc, _io_infiniteExc_T_1 connect io.rawOut.isNaN, isNaN_Z connect io.rawOut.isInf, isInf_Z connect io.rawOut.isZero, isZero_Z connect io.rawOut.sign, sign_Z connect io.rawOut.sExp, sExp_Z node _io_rawOut_sig_T = shl(sigX_Z, 1) node _io_rawOut_sig_T_1 = or(_io_rawOut_sig_T, notZeroRem_Z) connect io.rawOut.sig, _io_rawOut_sig_T_1	module DivSqrtRawFN_small_e8_s24_3( // @[DivSqrtRecFN_small.scala:199:5] input clock, // @[DivSqrtRecFN_small.scala:199:5] input reset, // @[DivSqrtRecFN_small.scala:199:5] output io_inReady, // @[DivSqrtRecFN_small.scala:203:16] input io_inValid, // @[DivSqrtRecFN_small.scala:203:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:203:16] input io_a_isNaN, // @[DivSqrtRecFN_small.scala:203:16] input io_a_isInf, // @[DivSqrtRecFN_small.scala:203:16] input io_a_isZero, // @[DivSqrtRecFN_small.scala:203:16] input io_a_sign, // @[DivSqrtRecFN_small.scala:203:16] input [9:0] io_a_sExp, // @[DivSqrtRecFN_small.scala:203:16] input [24:0] io_a_sig, // @[DivSqrtRecFN_small.scala:203:16] input io_b_isNaN, // @[DivSqrtRecFN_small.scala:203:16] input io_b_isInf, // @[DivSqrtRecFN_small.scala:203:16] input io_b_isZero, // @[DivSqrtRecFN_small.scala:203:16] input io_b_sign, // @[DivSqrtRecFN_small.scala:203:16] input [9:0] io_b_sExp, // @[DivSqrtRecFN_small.scala:203:16] input [24:0] io_b_sig, // @[DivSqrtRecFN_small.scala:203:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:203:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:203:16] output io_invalidExc, // @[DivSqrtRecFN_small.scala:203:16] output io_infiniteExc, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:203:16] output [9:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:203:16] output [26:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:203:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:199:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_isNaN_0 = io_a_isNaN; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_isInf_0 = io_a_isInf; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_isZero_0 = io_a_isZero; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_sign_0 = io_a_sign; // @[DivSqrtRecFN_small.scala:199:5] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[DivSqrtRecFN_small.scala:199:5] wire [24:0] io_a_sig_0 = io_a_sig; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_isNaN_0 = io_b_isNaN; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_isInf_0 = io_b_isInf; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_isZero_0 = io_b_isZero; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_sign_0 = io_b_sign; // @[DivSqrtRecFN_small.scala:199:5] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[DivSqrtRecFN_small.scala:199:5] wire [24:0] io_b_sig_0 = io_b_sig; // @[DivSqrtRecFN_small.scala:199:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:199:5] wire [1:0] _inReady_T_15 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61] wire [1:0] _rawOutValid_T_15 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61] wire [1:0] _cycleNum_T_11 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61] wire [21:0] _fractB_Z_T_19 = 22'h0; // @[DivSqrtRecFN_small.scala:345:16] wire [24:0] _trialTerm_T_16 = 25'h1000000; // @[DivSqrtRecFN_small.scala:366:42] wire [24:0] _trialTerm2_newBit0_T_3 = 25'h1000000; // @[DivSqrtRecFN_small.scala:373:85] wire [25:0] _nextRem_Z_2_T_3 = 26'h0; // @[DivSqrtRecFN_small.scala:386:12] wire [25:0] _nextRem_Z_2_T_7 = 26'h0; // @[DivSqrtRecFN_small.scala:387:12] wire [25:0] _nextRem_Z_2_T_8 = 26'h0; // @[DivSqrtRecFN_small.scala:386:81] wire _inReady_T_2 = 1'h1; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:317:38] wire _rawOutValid_T_2 = 1'h1; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:318:42] wire _fractB_Z_T_22 = 1'h1; // @[DivSqrtRecFN_small.scala:346:45] wire _nextNotZeroRem_Z_2_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:384:9] wire _nextRem_Z_2_T_9 = 1'h1; // @[DivSqrtRecFN_small.scala:388:13] wire processTwoBits = 1'h0; // @[DivSqrtRecFN_small.scala:300:42] wire _inReady_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_6 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:308:24] wire _inReady_T_8 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:307:20] wire _inReady_T_10 = 1'h0; // @[DivSqrtRecFN_small.scala:306:16] wire _rawOutValid_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_6 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:308:24] wire _rawOutValid_T_8 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:307:20] wire _rawOutValid_T_10 = 1'h0; // @[DivSqrtRecFN_small.scala:306:16] wire _fractB_Z_T_17 = 1'h0; // @[DivSqrtRecFN_small.scala:345:42] wire _nextNotZeroRem_Z_2_T = 1'h0; // @[DivSqrtRecFN_small.scala:382:24] wire _nextNotZeroRem_Z_2_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:382:34] wire _nextNotZeroRem_Z_2_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:383:24] wire _nextNotZeroRem_Z_2_T_18 = 1'h0; // @[DivSqrtRecFN_small.scala:383:35] wire _nextNotZeroRem_Z_2_T_19 = 1'h0; // @[DivSqrtRecFN_small.scala:382:85] wire _nextNotZeroRem_Z_2_T_20 = 1'h0; // @[DivSqrtRecFN_small.scala:384:26] wire _nextRem_Z_2_T = 1'h0; // @[DivSqrtRecFN_small.scala:386:28] wire _nextRem_Z_2_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:387:28] wire _sigX_Z_T_18 = 1'h0; // @[DivSqrtRecFN_small.scala:399:32] wire [28:0] _sigX_Z_T_20 = 29'h0; // @[DivSqrtRecFN_small.scala:399:16] wire _io_rawOutValid_div_T_1; // @[DivSqrtRecFN_small.scala:404:40] wire _io_rawOutValid_sqrt_T; // @[DivSqrtRecFN_small.scala:405:40] wire _io_invalidExc_T; // @[DivSqrtRecFN_small.scala:407:36] wire _io_infiniteExc_T_1; // @[DivSqrtRecFN_small.scala:408:36] wire [26:0] _io_rawOut_sig_T_1; // @[DivSqrtRecFN_small.scala:414:35] wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:199:5] wire [9:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:199:5] wire [26:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:199:5] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:199:5] reg [4:0] cycleNum; // @[DivSqrtRecFN_small.scala:224:33] reg inReady; // @[DivSqrtRecFN_small.scala:225:33] assign io_inReady_0 = inReady; // @[DivSqrtRecFN_small.scala:199:5, :225:33] reg rawOutValid; // @[DivSqrtRecFN_small.scala:226:33] reg sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29] reg majorExc_Z; // @[DivSqrtRecFN_small.scala:229:29] reg isNaN_Z; // @[DivSqrtRecFN_small.scala:231:29] assign io_rawOut_isNaN_0 = isNaN_Z; // @[DivSqrtRecFN_small.scala:199:5, :231:29] reg isInf_Z; // @[DivSqrtRecFN_small.scala:232:29] assign io_rawOut_isInf_0 = isInf_Z; // @[DivSqrtRecFN_small.scala:199:5, :232:29] reg isZero_Z; // @[DivSqrtRecFN_small.scala:233:29] assign io_rawOut_isZero_0 = isZero_Z; // @[DivSqrtRecFN_small.scala:199:5, :233:29] reg sign_Z; // @[DivSqrtRecFN_small.scala:234:29] assign io_rawOut_sign_0 = sign_Z; // @[DivSqrtRecFN_small.scala:199:5, :234:29] reg [9:0] sExp_Z; // @[DivSqrtRecFN_small.scala:235:29] assign io_rawOut_sExp_0 = sExp_Z; // @[DivSqrtRecFN_small.scala:199:5, :235:29] reg [23:0] fractB_Z; // @[DivSqrtRecFN_small.scala:236:29] reg [2:0] roundingMode_Z; // @[DivSqrtRecFN_small.scala:237:29] assign io_roundingModeOut_0 = roundingMode_Z; // @[DivSqrtRecFN_small.scala:199:5, :237:29] reg [25:0] rem_Z; // @[DivSqrtRecFN_small.scala:243:29] reg notZeroRem_Z; // @[DivSqrtRecFN_small.scala:244:29] reg [25:0] sigX_Z; // @[DivSqrtRecFN_small.scala:245:29] wire _notSigNaNIn_invalidExc_S_div_T = io_a_isZero_0 & io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :254:24] wire _notSigNaNIn_invalidExc_S_div_T_1 = io_a_isInf_0 & io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :254:59] wire notSigNaNIn_invalidExc_S_div = _notSigNaNIn_invalidExc_S_div_T \| _notSigNaNIn_invalidExc_S_div_T_1; // @[DivSqrtRecFN_small.scala:254:{24,42,59}] wire _notSigNaNIn_invalidExc_S_sqrt_T = ~io_a_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :256:9] wire _notSigNaNIn_invalidExc_S_sqrt_T_1 = ~io_a_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :256:27] wire _notSigNaNIn_invalidExc_S_sqrt_T_2 = _notSigNaNIn_invalidExc_S_sqrt_T & _notSigNaNIn_invalidExc_S_sqrt_T_1; // @[DivSqrtRecFN_small.scala:256:{9,24,27}] wire notSigNaNIn_invalidExc_S_sqrt = _notSigNaNIn_invalidExc_S_sqrt_T_2 & io_a_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :256:{24,43}] wire _majorExc_S_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _majorExc_S_T_4 = io_a_sig_0[22]; // @[common.scala:82:56] wire _majorExc_S_T_1 = ~_majorExc_S_T; // @[common.scala:82:{49,56}] wire _majorExc_S_T_2 = io_a_isNaN_0 & _majorExc_S_T_1; // @[common.scala:82:{46,49}] wire _majorExc_S_T_3 = _majorExc_S_T_2 \| notSigNaNIn_invalidExc_S_sqrt; // @[common.scala:82:46] wire _majorExc_S_T_5 = ~_majorExc_S_T_4; // @[common.scala:82:{49,56}] wire _majorExc_S_T_6 = io_a_isNaN_0 & _majorExc_S_T_5; // @[common.scala:82:{46,49}] wire _majorExc_S_T_7 = io_b_sig_0[22]; // @[common.scala:82:56] wire _majorExc_S_T_8 = ~_majorExc_S_T_7; // @[common.scala:82:{49,56}] wire _majorExc_S_T_9 = io_b_isNaN_0 & _majorExc_S_T_8; // @[common.scala:82:{46,49}] wire _majorExc_S_T_10 = _majorExc_S_T_6 \| _majorExc_S_T_9; // @[common.scala:82:46] wire _majorExc_S_T_11 = _majorExc_S_T_10 \| notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecFN_small.scala:254:42, :260:{38,66}] wire _majorExc_S_T_12 = ~io_a_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :256:9, :262:18] wire _majorExc_S_T_13 = ~io_a_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :262:36] wire _majorExc_S_T_14 = _majorExc_S_T_12 & _majorExc_S_T_13; // @[DivSqrtRecFN_small.scala:262:{18,33,36}] wire _majorExc_S_T_15 = _majorExc_S_T_14 & io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :262:{33,51}] wire _majorExc_S_T_16 = _majorExc_S_T_11 \| _majorExc_S_T_15; // @[DivSqrtRecFN_small.scala:260:66, :261:46, :262:51] wire majorExc_S = io_sqrtOp_0 ? _majorExc_S_T_3 : _majorExc_S_T_16; // @[DivSqrtRecFN_small.scala:199:5, :258:12, :259:38, :261:46] wire _isNaN_S_T = io_a_isNaN_0 \| notSigNaNIn_invalidExc_S_sqrt; // @[DivSqrtRecFN_small.scala:199:5, :256:43, :266:26] wire _isNaN_S_T_1 = io_a_isNaN_0 \| io_b_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :267:26] wire _isNaN_S_T_2 = _isNaN_S_T_1 \| notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecFN_small.scala:254:42, :267:{26,42}] wire isNaN_S = io_sqrtOp_0 ? _isNaN_S_T : _isNaN_S_T_2; // @[DivSqrtRecFN_small.scala:199:5, :265:12, :266:26, :267:42] wire _isInf_S_T = io_a_isInf_0 \| io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :269:63] wire isInf_S = io_sqrtOp_0 ? io_a_isInf_0 : _isInf_S_T; // @[DivSqrtRecFN_small.scala:199:5, :269:{23,63}] wire _isZero_S_T = io_a_isZero_0 \| io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :270:64] wire isZero_S = io_sqrtOp_0 ? io_a_isZero_0 : _isZero_S_T; // @[DivSqrtRecFN_small.scala:199:5, :270:{23,64}] wire _sign_S_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33] wire _sign_S_T_1 = _sign_S_T & io_b_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :271:{33,45}] wire sign_S = io_a_sign_0 ^ _sign_S_T_1; // @[DivSqrtRecFN_small.scala:199:5, :271:{30,45}] wire _specialCaseA_S_T = io_a_isNaN_0 \| io_a_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :273:39] wire specialCaseA_S = _specialCaseA_S_T \| io_a_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :273:{39,55}] wire _specialCaseB_S_T = io_b_isNaN_0 \| io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :274:39] wire specialCaseB_S = _specialCaseB_S_T \| io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :274:{39,55}] wire _normalCase_S_div_T = ~specialCaseA_S; // @[DivSqrtRecFN_small.scala:273:55, :275:28] wire _normalCase_S_div_T_1 = ~specialCaseB_S; // @[DivSqrtRecFN_small.scala:274:55, :275:48] wire normalCase_S_div = _normalCase_S_div_T & _normalCase_S_div_T_1; // @[DivSqrtRecFN_small.scala:275:{28,45,48}] wire _normalCase_S_sqrt_T = ~specialCaseA_S; // @[DivSqrtRecFN_small.scala:273:55, :275:28, :276:29] wire _normalCase_S_sqrt_T_1 = ~io_a_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :276:49] wire normalCase_S_sqrt = _normalCase_S_sqrt_T & _normalCase_S_sqrt_T_1; // @[DivSqrtRecFN_small.scala:276:{29,46,49}] wire normalCase_S = io_sqrtOp_0 ? normalCase_S_sqrt : normalCase_S_div; // @[DivSqrtRecFN_small.scala:199:5, :275:45, :276:46, :277:27] wire _sExpQuot_S_div_T = io_b_sExp_0[8]; // @[DivSqrtRecFN_small.scala:199:5, :281:28] wire [7:0] _sExpQuot_S_div_T_1 = io_b_sExp_0[7:0]; // @[DivSqrtRecFN_small.scala:199:5, :281:52] wire [7:0] _sExpQuot_S_div_T_2 = ~_sExpQuot_S_div_T_1; // @[DivSqrtRecFN_small.scala:281:{40,52}] wire [8:0] _sExpQuot_S_div_T_3 = {_sExpQuot_S_div_T, _sExpQuot_S_div_T_2}; // @[DivSqrtRecFN_small.scala:281:{16,28,40}] wire [8:0] _sExpQuot_S_div_T_4 = _sExpQuot_S_div_T_3; // @[DivSqrtRecFN_small.scala:281:{16,71}] wire [10:0] sExpQuot_S_div = {io_a_sExp_0[9], io_a_sExp_0} + {{2{_sExpQuot_S_div_T_4[8]}}, _sExpQuot_S_div_T_4}; // @[DivSqrtRecFN_small.scala:199:5, :280:21, :281:71] wire _sSatExpQuot_S_div_T = $signed(sExpQuot_S_div) > 11'sh1BF; // @[DivSqrtRecFN_small.scala:280:21, :284:48] wire [3:0] _sSatExpQuot_S_div_T_1 = sExpQuot_S_div[9:6]; // @[DivSqrtRecFN_small.scala:280:21, :286:31] wire [3:0] _sSatExpQuot_S_div_T_2 = _sSatExpQuot_S_div_T ? 4'h6 : _sSatExpQuot_S_div_T_1; // @[DivSqrtRecFN_small.scala:284:{16,48}, :286:31] wire [5:0] _sSatExpQuot_S_div_T_3 = sExpQuot_S_div[5:0]; // @[DivSqrtRecFN_small.scala:280:21, :288:27] wire [9:0] _sSatExpQuot_S_div_T_4 = {_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3}; // @[DivSqrtRecFN_small.scala:284:{12,16}, :288:27] wire [9:0] sSatExpQuot_S_div = _sSatExpQuot_S_div_T_4; // @[DivSqrtRecFN_small.scala:284:12, :289:11] wire _evenSqrt_S_T = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48] wire _oddSqrt_S_T = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :292:48] wire _inReady_T_4 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36] wire _rawOutValid_T_4 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36] wire _cycleNum_T_3 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36] wire _fractB_Z_T_6 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :343:52] wire _fractB_Z_T_11 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :344:54] wire _evenSqrt_S_T_1 = ~_evenSqrt_S_T; // @[DivSqrtRecFN_small.scala:291:{35,48}] wire evenSqrt_S = io_sqrtOp_0 & _evenSqrt_S_T_1; // @[DivSqrtRecFN_small.scala:199:5, :291:{32,35}] wire oddSqrt_S = io_sqrtOp_0 & _oddSqrt_S_T; // @[DivSqrtRecFN_small.scala:199:5, :292:{32,48}] wire idle = cycleNum == 5'h0; // @[DivSqrtRecFN_small.scala:224:33, :296:25] wire entering = inReady & io_inValid_0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :297:28] wire entering_normalCase = entering & normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :297:28, :298:40] wire _processTwoBits_T = cycleNum > 5'h2; // @[DivSqrtRecFN_small.scala:224:33, :300:35] wire _skipCycle2_T = cycleNum == 5'h3; // @[DivSqrtRecFN_small.scala:224:33, :301:31] wire _skipCycle2_T_1 = sigX_Z[25]; // @[DivSqrtRecFN_small.scala:245:29, :301:48] wire _skipCycle2_T_2 = _skipCycle2_T & _skipCycle2_T_1; // @[DivSqrtRecFN_small.scala:301:{31,39,48}] wire skipCycle2 = _skipCycle2_T_2; // @[DivSqrtRecFN_small.scala:301:{39,63}] wire _inReady_T_22 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16] wire _rawOutValid_T_22 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16] wire _cycleNum_T_16 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16] wire _inReady_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28] wire _inReady_T_1 = entering & _inReady_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}] wire _inReady_T_3 = _inReady_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}] wire _inReady_T_11 = _inReady_T_3; // @[DivSqrtRecFN_small.scala:305:{16,57}] wire _inReady_T_12 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17] wire _inReady_T_13 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31] wire _inReady_T_14 = _inReady_T_12 & _inReady_T_13; // @[DivSqrtRecFN_small.scala:313:{17,28,31}] wire [5:0] _GEN = {1'h0, cycleNum} - 6'h1; // @[DivSqrtRecFN_small.scala:224:33, :313:56] wire [5:0] _inReady_T_16; // @[DivSqrtRecFN_small.scala:313:56] assign _inReady_T_16 = _GEN; // @[DivSqrtRecFN_small.scala:313:56] wire [5:0] _rawOutValid_T_16; // @[DivSqrtRecFN_small.scala:313:56] assign _rawOutValid_T_16 = _GEN; // @[DivSqrtRecFN_small.scala:313:56] wire [5:0] _cycleNum_T_12; // @[DivSqrtRecFN_small.scala:313:56] assign _cycleNum_T_12 = _GEN; // @[DivSqrtRecFN_small.scala:313:56] wire [4:0] _inReady_T_17 = _inReady_T_16[4:0]; // @[DivSqrtRecFN_small.scala:313:56] wire _inReady_T_18 = _inReady_T_17 < 5'h2; // @[DivSqrtRecFN_small.scala:313:56, :317:38] wire _inReady_T_19 = _inReady_T_14 & _inReady_T_18; // @[DivSqrtRecFN_small.scala:313:{16,28}, :317:38] wire _inReady_T_20 = _inReady_T_11 \| _inReady_T_19; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16] wire _inReady_T_23 = _inReady_T_20 \| _inReady_T_22; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16] wire _inReady_T_24 = _inReady_T_23; // @[DivSqrtRecFN_small.scala:313:95, :317:46] wire _rawOutValid_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28] wire _rawOutValid_T_1 = entering & _rawOutValid_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}] wire _rawOutValid_T_3 = _rawOutValid_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}] wire _rawOutValid_T_11 = _rawOutValid_T_3; // @[DivSqrtRecFN_small.scala:305:{16,57}] wire _rawOutValid_T_12 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17] wire _rawOutValid_T_13 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31] wire _rawOutValid_T_14 = _rawOutValid_T_12 & _rawOutValid_T_13; // @[DivSqrtRecFN_small.scala:313:{17,28,31}] wire [4:0] _rawOutValid_T_17 = _rawOutValid_T_16[4:0]; // @[DivSqrtRecFN_small.scala:313:56] wire _rawOutValid_T_18 = _rawOutValid_T_17 == 5'h1; // @[DivSqrtRecFN_small.scala:313:56, :318:42] wire _rawOutValid_T_19 = _rawOutValid_T_14 & _rawOutValid_T_18; // @[DivSqrtRecFN_small.scala:313:{16,28}, :318:42] wire _rawOutValid_T_20 = _rawOutValid_T_11 \| _rawOutValid_T_19; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16] wire _rawOutValid_T_23 = _rawOutValid_T_20 \| _rawOutValid_T_22; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16] wire _rawOutValid_T_24 = _rawOutValid_T_23; // @[DivSqrtRecFN_small.scala:313:95, :318:51] wire _cycleNum_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28] wire _cycleNum_T_1 = entering & _cycleNum_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}] wire _cycleNum_T_2 = _cycleNum_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}] wire [4:0] _cycleNum_T_4 = {4'hC, ~_cycleNum_T_3}; // @[DivSqrtRecFN_small.scala:308:{24,36}] wire [4:0] _cycleNum_T_5 = io_sqrtOp_0 ? _cycleNum_T_4 : 5'h1A; // @[DivSqrtRecFN_small.scala:199:5, :307:20, :308:24] wire [4:0] _cycleNum_T_6 = entering_normalCase ? _cycleNum_T_5 : 5'h0; // @[DivSqrtRecFN_small.scala:298:40, :306:16, :307:20] wire [4:0] _cycleNum_T_7 = {4'h0, _cycleNum_T_2} \| _cycleNum_T_6; // @[DivSqrtRecFN_small.scala:305:{16,57}, :306:16, :313:56] wire _cycleNum_T_8 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17] wire _cycleNum_T_9 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31] wire _cycleNum_T_10 = _cycleNum_T_8 & _cycleNum_T_9; // @[DivSqrtRecFN_small.scala:313:{17,28,31}] wire [4:0] _cycleNum_T_13 = _cycleNum_T_12[4:0]; // @[DivSqrtRecFN_small.scala:313:56] wire [4:0] _cycleNum_T_14 = _cycleNum_T_10 ? _cycleNum_T_13 : 5'h0; // @[DivSqrtRecFN_small.scala:313:{16,28,56}] wire [4:0] _cycleNum_T_15 = _cycleNum_T_7 \| _cycleNum_T_14; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16] wire [4:0] _cycleNum_T_17 = {_cycleNum_T_15[4:1], _cycleNum_T_15[0] \| _cycleNum_T_16}; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16] wire [8:0] _sExp_Z_T = io_a_sExp_0[9:1]; // @[DivSqrtRecFN_small.scala:199:5, :335:29] wire [9:0] _sExp_Z_T_1 = {_sExp_Z_T[8], _sExp_Z_T} + 10'h80; // @[DivSqrtRecFN_small.scala:335:{29,34}] wire [9:0] _sExp_Z_T_2 = io_sqrtOp_0 ? _sExp_Z_T_1 : sSatExpQuot_S_div; // @[DivSqrtRecFN_small.scala:199:5, :289:11, :334:16, :335:34] wire _fractB_Z_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :342:28] wire _fractB_Z_T_1 = inReady & _fractB_Z_T; // @[DivSqrtRecFN_small.scala:225:33, :342:{25,28}] wire [22:0] _fractB_Z_T_2 = io_b_sig_0[22:0]; // @[DivSqrtRecFN_small.scala:199:5, :342:73] wire [23:0] _fractB_Z_T_3 = {_fractB_Z_T_2, 1'h0}; // @[DivSqrtRecFN_small.scala:342:{73,90}] wire [23:0] _fractB_Z_T_4 = _fractB_Z_T_1 ? _fractB_Z_T_3 : 24'h0; // @[DivSqrtRecFN_small.scala:342:{16,25,90}] wire _GEN_0 = inReady & io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :343:25] wire _fractB_Z_T_5; // @[DivSqrtRecFN_small.scala:343:25] assign _fractB_Z_T_5 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25] wire _fractB_Z_T_10; // @[DivSqrtRecFN_small.scala:344:25] assign _fractB_Z_T_10 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25, :344:25] wire _sigX_Z_T_4; // @[DivSqrtRecFN_small.scala:395:25] assign _sigX_Z_T_4 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25, :395:25] wire _fractB_Z_T_7 = _fractB_Z_T_5 & _fractB_Z_T_6; // @[DivSqrtRecFN_small.scala:343:{25,38,52}] wire [22:0] _fractB_Z_T_8 = {_fractB_Z_T_7, 22'h0}; // @[DivSqrtRecFN_small.scala:343:{16,38}] wire [23:0] _fractB_Z_T_9 = {_fractB_Z_T_4[23], _fractB_Z_T_4[22:0] \| _fractB_Z_T_8}; // @[DivSqrtRecFN_small.scala:342:{16,100}, :343:16] wire _fractB_Z_T_12 = ~_fractB_Z_T_11; // @[DivSqrtRecFN_small.scala:344:{41,54}] wire _fractB_Z_T_13 = _fractB_Z_T_10 & _fractB_Z_T_12; // @[DivSqrtRecFN_small.scala:344:{25,38,41}] wire [23:0] _fractB_Z_T_14 = {_fractB_Z_T_13, 23'h0}; // @[DivSqrtRecFN_small.scala:344:{16,38}] wire [23:0] _fractB_Z_T_15 = _fractB_Z_T_9 \| _fractB_Z_T_14; // @[DivSqrtRecFN_small.scala:342:100, :343:100, :344:16] wire [23:0] _fractB_Z_T_20 = _fractB_Z_T_15; // @[DivSqrtRecFN_small.scala:343:100, :344:100] wire _fractB_Z_T_16 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :345:17] wire [21:0] _fractB_Z_T_18 = fractB_Z[23:2]; // @[DivSqrtRecFN_small.scala:236:29, :345:71] wire _fractB_Z_T_21 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :346:17] wire _fractB_Z_T_23 = _fractB_Z_T_21; // @[DivSqrtRecFN_small.scala:346:{17,42}] wire [22:0] _fractB_Z_T_24 = fractB_Z[23:1]; // @[DivSqrtRecFN_small.scala:236:29, :346:71] wire [22:0] _trialTerm2_newBit0_T = fractB_Z[23:1]; // @[DivSqrtRecFN_small.scala:236:29, :346:71, :373:52] wire [22:0] _fractB_Z_T_25 = _fractB_Z_T_23 ? _fractB_Z_T_24 : 23'h0; // @[DivSqrtRecFN_small.scala:346:{16,42,71}] wire [23:0] _fractB_Z_T_26 = {_fractB_Z_T_20[23], _fractB_Z_T_20[22:0] \| _fractB_Z_T_25}; // @[DivSqrtRecFN_small.scala:344:100, :345:100, :346:16] wire _rem_T = ~oddSqrt_S; // @[DivSqrtRecFN_small.scala:292:32, :352:24] wire _rem_T_1 = inReady & _rem_T; // @[DivSqrtRecFN_small.scala:225:33, :352:{21,24}] wire [25:0] _rem_T_2 = {io_a_sig_0, 1'h0}; // @[DivSqrtRecFN_small.scala:199:5, :352:47] wire [25:0] _rem_T_3 = _rem_T_1 ? _rem_T_2 : 26'h0; // @[DivSqrtRecFN_small.scala:352:{12,21,47}] wire _GEN_1 = inReady & oddSqrt_S; // @[DivSqrtRecFN_small.scala:225:33, :292:32, :353:21] wire _rem_T_4; // @[DivSqrtRecFN_small.scala:353:21] assign _rem_T_4 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21] wire _trialTerm_T_7; // @[DivSqrtRecFN_small.scala:364:21] assign _trialTerm_T_7 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21, :364:21] wire _sigX_Z_T_7; // @[DivSqrtRecFN_small.scala:396:25] assign _sigX_Z_T_7 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21, :396:25] wire [1:0] _rem_T_5 = io_a_sig_0[23:22]; // @[DivSqrtRecFN_small.scala:199:5, :354:27] wire [2:0] _rem_T_6 = {1'h0, _rem_T_5} - 3'h1; // @[DivSqrtRecFN_small.scala:354:{27,56}] wire [1:0] _rem_T_7 = _rem_T_6[1:0]; // @[DivSqrtRecFN_small.scala:354:56] wire [21:0] _rem_T_8 = io_a_sig_0[21:0]; // @[DivSqrtRecFN_small.scala:199:5, :355:27] wire [24:0] _rem_T_9 = {_rem_T_8, 3'h0}; // @[DivSqrtRecFN_small.scala:300:35, :355:{27,44}] wire [26:0] _rem_T_10 = {_rem_T_7, _rem_T_9}; // @[DivSqrtRecFN_small.scala:354:{16,56}, :355:44] wire [26:0] _rem_T_11 = _rem_T_4 ? _rem_T_10 : 27'h0; // @[DivSqrtRecFN_small.scala:353:{12,21}, :354:16] wire [26:0] _rem_T_12 = {1'h0, _rem_T_3} \| _rem_T_11; // @[DivSqrtRecFN_small.scala:352:{12,57}, :353:12] wire _rem_T_13 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :359:13] wire [26:0] _rem_T_14 = {rem_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:243:29, :359:29] wire [26:0] _rem_T_15 = _rem_T_13 ? _rem_T_14 : 27'h0; // @[DivSqrtRecFN_small.scala:359:{12,13,29}] wire [26:0] rem = _rem_T_12 \| _rem_T_15; // @[DivSqrtRecFN_small.scala:352:57, :358:11, :359:12] wire [31:0] _bitMask_T = 32'h1 << cycleNum; // @[DivSqrtRecFN_small.scala:224:33, :360:23] wire [29:0] bitMask = _bitMask_T[31:2]; // @[DivSqrtRecFN_small.scala:360:{23,34}] wire _trialTerm_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :362:24] wire _trialTerm_T_1 = inReady & _trialTerm_T; // @[DivSqrtRecFN_small.scala:225:33, :362:{21,24}] wire [25:0] _trialTerm_T_2 = {io_b_sig_0, 1'h0}; // @[DivSqrtRecFN_small.scala:199:5, :362:48] wire [25:0] _trialTerm_T_3 = _trialTerm_T_1 ? _trialTerm_T_2 : 26'h0; // @[DivSqrtRecFN_small.scala:362:{12,21,48}] wire _trialTerm_T_4 = inReady & evenSqrt_S; // @[DivSqrtRecFN_small.scala:225:33, :291:32, :363:21] wire [24:0] _trialTerm_T_5 = {_trialTerm_T_4, 24'h0}; // @[DivSqrtRecFN_small.scala:363:{12,21}] wire [25:0] _trialTerm_T_6 = {_trialTerm_T_3[25], _trialTerm_T_3[24:0] \| _trialTerm_T_5}; // @[DivSqrtRecFN_small.scala:362:{12,74}, :363:12] wire [25:0] _trialTerm_T_8 = _trialTerm_T_7 ? 26'h2800000 : 26'h0; // @[DivSqrtRecFN_small.scala:364:{12,21}] wire [25:0] _trialTerm_T_9 = _trialTerm_T_6 \| _trialTerm_T_8; // @[DivSqrtRecFN_small.scala:362:74, :363:74, :364:12] wire _trialTerm_T_10 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :365:13] wire [23:0] _trialTerm_T_11 = _trialTerm_T_10 ? fractB_Z : 24'h0; // @[DivSqrtRecFN_small.scala:236:29, :365:{12,13}] wire [25:0] _trialTerm_T_12 = {_trialTerm_T_9[25:24], _trialTerm_T_9[23:0] \| _trialTerm_T_11}; // @[DivSqrtRecFN_small.scala:363:74, :364:74, :365:12] wire _trialTerm_T_13 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :366:13] wire _trialTerm_T_14 = ~sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :366:26] wire _trialTerm_T_15 = _trialTerm_T_13 & _trialTerm_T_14; // @[DivSqrtRecFN_small.scala:366:{13,23,26}] wire [24:0] _trialTerm_T_17 = {_trialTerm_T_15, 24'h0}; // @[DivSqrtRecFN_small.scala:366:{12,23}] wire [25:0] _trialTerm_T_18 = {_trialTerm_T_12[25], _trialTerm_T_12[24:0] \| _trialTerm_T_17}; // @[DivSqrtRecFN_small.scala:364:74, :365:74, :366:12] wire _trialTerm_T_19 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :367:13] wire _trialTerm_T_20 = _trialTerm_T_19 & sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :367:{13,23}] wire [26:0] _GEN_2 = {sigX_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:245:29, :367:44] wire [26:0] _trialTerm_T_21; // @[DivSqrtRecFN_small.scala:367:44] assign _trialTerm_T_21 = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44] wire [26:0] _trialTerm2_newBit0_T_1; // @[DivSqrtRecFN_small.scala:373:64] assign _trialTerm2_newBit0_T_1 = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44, :373:64] wire [26:0] _io_rawOut_sig_T; // @[DivSqrtRecFN_small.scala:414:31] assign _io_rawOut_sig_T = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44, :414:31] wire [26:0] _trialTerm_T_22 = _trialTerm_T_20 ? _trialTerm_T_21 : 27'h0; // @[DivSqrtRecFN_small.scala:367:{12,23,44}] wire [26:0] trialTerm = {1'h0, _trialTerm_T_18} \| _trialTerm_T_22; // @[DivSqrtRecFN_small.scala:365:74, :366:74, :367:12] wire [27:0] _trialRem_T = {1'h0, rem}; // @[DivSqrtRecFN_small.scala:358:11, :368:24] wire [27:0] _trialRem_T_1 = {1'h0, trialTerm}; // @[DivSqrtRecFN_small.scala:366:74, :368:42] wire [28:0] trialRem = {_trialRem_T[27], _trialRem_T} - {_trialRem_T_1[27], _trialRem_T_1}; // @[DivSqrtRecFN_small.scala:368:{24,29,42}] wire [28:0] _nextRem_Z_T = trialRem; // @[DivSqrtRecFN_small.scala:368:29, :371:42] wire newBit = $signed(trialRem) > -29'sh1; // @[DivSqrtRecFN_small.scala:368:29, :369:23] wire [28:0] _nextRem_Z_T_1 = newBit ? _nextRem_Z_T : {2'h0, rem}; // @[DivSqrtRecFN_small.scala:354:56, :358:11, :369:23, :371:{24,42}] wire [25:0] nextRem_Z = _nextRem_Z_T_1[25:0]; // @[DivSqrtRecFN_small.scala:371:{24,54}] wire [25:0] _nextRem_Z_2_T_10 = nextRem_Z; // @[DivSqrtRecFN_small.scala:371:54, :388:12] wire [26:0] rem2 = {nextRem_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:371:54, :372:25] wire [26:0] _trialTerm2_newBit0_T_2 = {4'h0, _trialTerm2_newBit0_T} \| _trialTerm2_newBit0_T_1; // @[DivSqrtRecFN_small.scala:313:56, :373:{52,56,64}] wire [24:0] _trialTerm2_newBit0_T_4 = {1'h1, fractB_Z}; // @[DivSqrtRecFN_small.scala:236:29, :373:78] wire [26:0] trialTerm2_newBit0 = sqrtOp_Z ? _trialTerm2_newBit0_T_2 : {2'h0, _trialTerm2_newBit0_T_4}; // @[DivSqrtRecFN_small.scala:228:29, :354:56, :373:{33,56,78}] wire [24:0] _trialTerm2_newBit1_T = {fractB_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:236:29, :374:73] wire [24:0] _trialTerm2_newBit1_T_1 = sqrtOp_Z ? _trialTerm2_newBit1_T : 25'h0; // @[DivSqrtRecFN_small.scala:228:29, :374:{54,73}] wire [26:0] trialTerm2_newBit1 = {trialTerm2_newBit0[26:25], trialTerm2_newBit0[24:0] \| _trialTerm2_newBit1_T_1}; // @[DivSqrtRecFN_small.scala:373:33, :374:{49,54}] wire [29:0] _GEN_3 = {trialRem, 1'h0}; // @[DivSqrtRecFN_small.scala:368:29, :377:22] wire [29:0] _trialRem2_T; // @[DivSqrtRecFN_small.scala:377:22] assign _trialRem2_T = _GEN_3; // @[DivSqrtRecFN_small.scala:377:22] wire [29:0] _nextNotZeroRem_Z_2_T_1; // @[DivSqrtRecFN_small.scala:382:53] assign _nextNotZeroRem_Z_2_T_1 = _GEN_3; // @[DivSqrtRecFN_small.scala:377:22, :382:53] wire [27:0] _GEN_4 = {1'h0, trialTerm2_newBit1}; // @[DivSqrtRecFN_small.scala:374:49, :377:48] wire [27:0] _trialRem2_T_1; // @[DivSqrtRecFN_small.scala:377:48] assign _trialRem2_T_1 = _GEN_4; // @[DivSqrtRecFN_small.scala:377:48] wire [27:0] _nextNotZeroRem_Z_2_T_2; // @[DivSqrtRecFN_small.scala:382:79] assign _nextNotZeroRem_Z_2_T_2 = _GEN_4; // @[DivSqrtRecFN_small.scala:377:48, :382:79] wire [30:0] _trialRem2_T_2 = {_trialRem2_T[29], _trialRem2_T} - {{3{_trialRem2_T_1[27]}}, _trialRem2_T_1}; // @[DivSqrtRecFN_small.scala:377:{22,27,48}] wire [29:0] _trialRem2_T_3 = _trialRem2_T_2[29:0]; // @[DivSqrtRecFN_small.scala:377:27] wire [29:0] _trialRem2_T_4 = _trialRem2_T_3; // @[DivSqrtRecFN_small.scala:377:27] wire [27:0] _GEN_5 = {rem_Z, 2'h0}; // @[DivSqrtRecFN_small.scala:243:29, :354:56, :378:19] wire [27:0] _trialRem2_T_5; // @[DivSqrtRecFN_small.scala:378:19] assign _trialRem2_T_5 = _GEN_5; // @[DivSqrtRecFN_small.scala:378:19] wire [27:0] _nextNotZeroRem_Z_2_T_10; // @[DivSqrtRecFN_small.scala:383:51] assign _nextNotZeroRem_Z_2_T_10 = _GEN_5; // @[DivSqrtRecFN_small.scala:378:19, :383:51] wire [26:0] _trialRem2_T_6 = _trialRem2_T_5[26:0]; // @[DivSqrtRecFN_small.scala:378:{19,23}] wire [27:0] _trialRem2_T_7 = {1'h0, _trialRem2_T_6}; // @[DivSqrtRecFN_small.scala:378:{23,39}] wire [27:0] _GEN_6 = {1'h0, trialTerm2_newBit0}; // @[DivSqrtRecFN_small.scala:373:33, :378:65] wire [27:0] _trialRem2_T_8; // @[DivSqrtRecFN_small.scala:378:65] assign _trialRem2_T_8 = _GEN_6; // @[DivSqrtRecFN_small.scala:378:65] wire [27:0] _nextNotZeroRem_Z_2_T_13; // @[DivSqrtRecFN_small.scala:383:97] assign _nextNotZeroRem_Z_2_T_13 = _GEN_6; // @[DivSqrtRecFN_small.scala:378:65, :383:97] wire [28:0] _trialRem2_T_9 = {_trialRem2_T_7[27], _trialRem2_T_7} - {_trialRem2_T_8[27], _trialRem2_T_8}; // @[DivSqrtRecFN_small.scala:378:{39,44,65}] wire [27:0] _trialRem2_T_10 = _trialRem2_T_9[27:0]; // @[DivSqrtRecFN_small.scala:378:44] wire [27:0] _trialRem2_T_11 = _trialRem2_T_10; // @[DivSqrtRecFN_small.scala:378:44] wire [29:0] trialRem2 = newBit ? _trialRem2_T_4 : {{2{_trialRem2_T_11[27]}}, _trialRem2_T_11}; // @[DivSqrtRecFN_small.scala:369:23, :376:12, :377:27, :378:44] wire [29:0] _nextRem_Z_2_T_1 = trialRem2; // @[DivSqrtRecFN_small.scala:376:12, :386:51] wire newBit2 = $signed(trialRem2) > -30'sh1; // @[DivSqrtRecFN_small.scala:376:12, :379:24] wire _nextNotZeroRem_Z_T = inReady \| newBit; // @[DivSqrtRecFN_small.scala:225:33, :369:23, :380:40] wire _nextNotZeroRem_Z_T_1 = \|trialRem; // @[DivSqrtRecFN_small.scala:368:29, :380:60] wire nextNotZeroRem_Z = _nextNotZeroRem_Z_T ? _nextNotZeroRem_Z_T_1 : notZeroRem_Z; // @[DivSqrtRecFN_small.scala:244:29, :380:{31,40,60}] wire _nextNotZeroRem_Z_2_T_22 = nextNotZeroRem_Z; // @[DivSqrtRecFN_small.scala:380:31, :384:38] wire [30:0] _nextNotZeroRem_Z_2_T_3 = {_nextNotZeroRem_Z_2_T_1[29], _nextNotZeroRem_Z_2_T_1} - {{3{_nextNotZeroRem_Z_2_T_2[27]}}, _nextNotZeroRem_Z_2_T_2}; // @[DivSqrtRecFN_small.scala:382:{53,58,79}] wire [29:0] _nextNotZeroRem_Z_2_T_4 = _nextNotZeroRem_Z_2_T_3[29:0]; // @[DivSqrtRecFN_small.scala:382:58] wire [29:0] _nextNotZeroRem_Z_2_T_5 = _nextNotZeroRem_Z_2_T_4; // @[DivSqrtRecFN_small.scala:382:58] wire _nextNotZeroRem_Z_2_T_6 = $signed(_nextNotZeroRem_Z_2_T_5) > 30'sh0; // @[DivSqrtRecFN_small.scala:379:24, :382:{42,58}] wire _nextNotZeroRem_Z_2_T_8 = ~newBit; // @[DivSqrtRecFN_small.scala:369:23, :383:27] wire [26:0] _nextNotZeroRem_Z_2_T_11 = _nextNotZeroRem_Z_2_T_10[26:0]; // @[DivSqrtRecFN_small.scala:383:{51,55}] wire [27:0] _nextNotZeroRem_Z_2_T_12 = {1'h0, _nextNotZeroRem_Z_2_T_11}; // @[DivSqrtRecFN_small.scala:383:{55,71}] wire [28:0] _nextNotZeroRem_Z_2_T_14 = {_nextNotZeroRem_Z_2_T_12[27], _nextNotZeroRem_Z_2_T_12} - {_nextNotZeroRem_Z_2_T_13[27], _nextNotZeroRem_Z_2_T_13}; // @[DivSqrtRecFN_small.scala:383:{71,76,97}] wire [27:0] _nextNotZeroRem_Z_2_T_15 = _nextNotZeroRem_Z_2_T_14[27:0]; // @[DivSqrtRecFN_small.scala:383:76] wire [27:0] _nextNotZeroRem_Z_2_T_16 = _nextNotZeroRem_Z_2_T_15; // @[DivSqrtRecFN_small.scala:383:76] wire _nextNotZeroRem_Z_2_T_17 = $signed(_nextNotZeroRem_Z_2_T_16) > 28'sh0; // @[DivSqrtRecFN_small.scala:383:{43,76}] wire nextNotZeroRem_Z_2 = _nextNotZeroRem_Z_2_T_22; // @[DivSqrtRecFN_small.scala:383:103, :384:38] wire [25:0] _nextRem_Z_2_T_2 = _nextRem_Z_2_T_1[25:0]; // @[DivSqrtRecFN_small.scala:386:{51,57}] wire _nextRem_Z_2_T_4 = ~newBit2; // @[DivSqrtRecFN_small.scala:379:24, :387:31] wire [25:0] _nextRem_Z_2_T_6 = rem2[25:0]; // @[DivSqrtRecFN_small.scala:372:25, :387:45] wire [25:0] nextRem_Z_2 = _nextRem_Z_2_T_10; // @[DivSqrtRecFN_small.scala:387:83, :388:12] wire _sigX_Z_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :394:28] wire _sigX_Z_T_1 = inReady & _sigX_Z_T; // @[DivSqrtRecFN_small.scala:225:33, :394:{25,28}] wire [25:0] _sigX_Z_T_2 = {newBit, 25'h0}; // @[DivSqrtRecFN_small.scala:369:23, :394:50] wire [25:0] _sigX_Z_T_3 = _sigX_Z_T_1 ? _sigX_Z_T_2 : 26'h0; // @[DivSqrtRecFN_small.scala:394:{16,25,50}] wire [24:0] _sigX_Z_T_5 = {_sigX_Z_T_4, 24'h0}; // @[DivSqrtRecFN_small.scala:395:{16,25}] wire [25:0] _sigX_Z_T_6 = {_sigX_Z_T_3[25], _sigX_Z_T_3[24:0] \| _sigX_Z_T_5}; // @[DivSqrtRecFN_small.scala:394:{16,74}, :395:16] wire [23:0] _sigX_Z_T_8 = {newBit, 23'h0}; // @[DivSqrtRecFN_small.scala:369:23, :396:50] wire [23:0] _sigX_Z_T_9 = _sigX_Z_T_7 ? _sigX_Z_T_8 : 24'h0; // @[DivSqrtRecFN_small.scala:396:{16,25,50}] wire [25:0] _sigX_Z_T_10 = {_sigX_Z_T_6[25:24], _sigX_Z_T_6[23:0] \| _sigX_Z_T_9}; // @[DivSqrtRecFN_small.scala:394:74, :395:74, :396:16] wire _sigX_Z_T_11 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :397:17] wire [25:0] _sigX_Z_T_12 = _sigX_Z_T_11 ? sigX_Z : 26'h0; // @[DivSqrtRecFN_small.scala:245:29, :397:{16,17}] wire [25:0] _sigX_Z_T_13 = _sigX_Z_T_10 \| _sigX_Z_T_12; // @[DivSqrtRecFN_small.scala:395:74, :396:74, :397:16] wire _sigX_Z_T_14 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :398:17] wire _sigX_Z_T_15 = _sigX_Z_T_14 & newBit; // @[DivSqrtRecFN_small.scala:369:23, :398:{17,27}] wire [29:0] _sigX_Z_T_16 = _sigX_Z_T_15 ? bitMask : 30'h0; // @[DivSqrtRecFN_small.scala:360:34, :379:24, :398:{16,27}] wire [29:0] _sigX_Z_T_17 = {4'h0, _sigX_Z_T_13} \| _sigX_Z_T_16; // @[DivSqrtRecFN_small.scala:313:56, :396:74, :397:74, :398:16] wire [29:0] _sigX_Z_T_21 = _sigX_Z_T_17; // @[DivSqrtRecFN_small.scala:397:74, :398:74] wire [28:0] _sigX_Z_T_19 = bitMask[29:1]; // @[DivSqrtRecFN_small.scala:360:34, :399:51] wire _io_rawOutValid_div_T = ~sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :366:26, :404:43] assign _io_rawOutValid_div_T_1 = rawOutValid & _io_rawOutValid_div_T; // @[DivSqrtRecFN_small.scala:226:33, :404:{40,43}] assign io_rawOutValid_div_0 = _io_rawOutValid_div_T_1; // @[DivSqrtRecFN_small.scala:199:5, :404:40] assign _io_rawOutValid_sqrt_T = rawOutValid & sqrtOp_Z; // @[DivSqrtRecFN_small.scala:226:33, :228:29, :405:40] assign io_rawOutValid_sqrt_0 = _io_rawOutValid_sqrt_T; // @[DivSqrtRecFN_small.scala:199:5, :405:40] assign _io_invalidExc_T = majorExc_Z & isNaN_Z; // @[DivSqrtRecFN_small.scala:229:29, :231:29, :407:36] assign io_invalidExc_0 = _io_invalidExc_T; // @[DivSqrtRecFN_small.scala:199:5, :407:36] wire _io_infiniteExc_T = ~isNaN_Z; // @[DivSqrtRecFN_small.scala:231:29, :408:39] assign _io_infiniteExc_T_1 = majorExc_Z & _io_infiniteExc_T; // @[DivSqrtRecFN_small.scala:229:29, :408:{36,39}] assign io_infiniteExc_0 = _io_infiniteExc_T_1; // @[DivSqrtRecFN_small.scala:199:5, :408:36] assign _io_rawOut_sig_T_1 = {_io_rawOut_sig_T[26:1], _io_rawOut_sig_T[0] \| notZeroRem_Z}; // @[DivSqrtRecFN_small.scala:244:29, :414:{31,35}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_1; // @[DivSqrtRecFN_small.scala:199:5, :414:35] always @(posedge clock) begin // @[DivSqrtRecFN_small.scala:199:5] if (reset) begin // @[DivSqrtRecFN_small.scala:199:5] cycleNum <= 5'h0; // @[DivSqrtRecFN_small.scala:224:33] inReady <= 1'h1; // @[DivSqrtRecFN_small.scala:225:33] rawOutValid <= 1'h0; // @[DivSqrtRecFN_small.scala:226:33] end else if (~idle \| entering) begin // @[DivSqrtRecFN_small.scala:296:25, :297:28, :303:{11,18}] cycleNum <= _cycleNum_T_17; // @[DivSqrtRecFN_small.scala:224:33, :313:95] inReady <= _inReady_T_24; // @[DivSqrtRecFN_small.scala:225:33, :317:46] rawOutValid <= _rawOutValid_T_24; // @[DivSqrtRecFN_small.scala:226:33, :318:51] end if (entering) begin // @[DivSqrtRecFN_small.scala:297:28] sqrtOp_Z <= io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :228:29] majorExc_Z <= majorExc_S; // @[DivSqrtRecFN_small.scala:229:29, :258:12] isNaN_Z <= isNaN_S; // @[DivSqrtRecFN_small.scala:231:29, :265:12] isInf_Z <= isInf_S; // @[DivSqrtRecFN_small.scala:232:29, :269:23] isZero_Z <= isZero_S; // @[DivSqrtRecFN_small.scala:233:29, :270:23] sign_Z <= sign_S; // @[DivSqrtRecFN_small.scala:234:29, :271:30] sExp_Z <= _sExp_Z_T_2; // @[DivSqrtRecFN_small.scala:235:29, :334:16] roundingMode_Z <= io_roundingMode_0; // @[DivSqrtRecFN_small.scala:199:5, :237:29] end if (entering \| ~inReady & sqrtOp_Z) // @[DivSqrtRecFN_small.scala:225:33, :228:29, :297:28, :340:{20,23,33}] fractB_Z <= _fractB_Z_T_26; // @[DivSqrtRecFN_small.scala:236:29, :345:100] if (entering \| ~inReady) begin // @[DivSqrtRecFN_small.scala:225:33, :297:28, :340:23, :390:20] rem_Z <= nextRem_Z_2; // @[DivSqrtRecFN_small.scala:243:29, :387:83] notZeroRem_Z <= nextNotZeroRem_Z_2; // @[DivSqrtRecFN_small.scala:244:29, :383:103] sigX_Z <= _sigX_Z_T_21[25:0]; // @[DivSqrtRecFN_small.scala:245:29, :393:16, :398:74] end always @(posedge) assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:199:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_39 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T	module MulAddRecFNToRaw_postMul_e8_s24_39( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] _CDom_reduced4SigExtra_T_4 = 3'h7; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = 9'h1FE; // @[primitives.scala:76:56] wire [3:0] _CDom_reduced4SigExtra_T_6 = 4'hF; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = 4'hF; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_7 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = 2'h3; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_5 = 6'h3F; // @[primitives.scala:77:20, :78:22] wire [5:0] _CDom_reduced4SigExtra_T_20 = 6'h3F; // @[primitives.scala:77:20, :78:22] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_3 = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16, :223:51] wire [4:0] io_fromPreMul_CDom_CAlignDist = 5'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA = 1'h1; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd = 1'h1; // @[MulAddRecFN.scala:169:7] wire _CDom_reduced4SigExtra_T_8 = 1'h1; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = 1'h1; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = 1'h1; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = 1'h1; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_17 = 1'h1; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = 1'h1; // @[primitives.scala:77:20] wire _notNaN_addZeros_T = 1'h1; // @[MulAddRecFN.scala:267:32] wire _io_invalidExc_T_4 = 1'h1; // @[MulAddRecFN.scala:274:10] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire _io_rawOut_sign_T_9 = 1'h1; // @[MulAddRecFN.scala:290:37] wire io_fromPreMul_isNaNAOrB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire notNaN_isInfProd = 1'h0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31] wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32] wire _io_invalidExc_T_5 = 1'h0; // @[MulAddRecFN.scala:275:36] wire _io_invalidExc_T_6 = 1'h0; // @[MulAddRecFN.scala:274:36] wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61] wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35] wire _io_rawOut_sign_T = 1'h0; // @[MulAddRecFN.scala:285:27] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35] wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] wire notNaN_isInfOut = io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :265:44] wire notNaN_addZeros = io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:58] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = ~io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = \|_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = \|_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum}; // @[MulAddRecFN.scala:205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}, :223:51] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = \|_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = \|_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = \|_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = \|_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = \|_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = \|_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = \|_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0]}; // @[primitives.scala:124:20] wire CDom_reduced4SigExtra = \|_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = \|_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 \| CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 \| CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = \|_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = \|_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 \| notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = ~notCDom_signSigSum; // @[MulAddRecFN.scala:232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57] assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros \| _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:54, :286:31] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4; // @[MulAddRecFN.scala:287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 \| _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 \| _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a28d64s6k1z3u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_48 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a28d64s6k1z3u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a28d64s6k1z3u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<6>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLBuffer_a28d64s6k1z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [5:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_48 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a28d64s6k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a28d64s6k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLCToNoC_9 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<129>, egress_id : UInt}}} inst q of Queue1_TLBundleC_a32d128s7k6z4c_9 connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 4) node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 4) node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T) node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_5 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_4) node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_5) node _io_flit_bits_egress_id_requestOH_T_6 = xor(q.io.deq.bits.address, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_7 = cvt(_io_flit_bits_egress_id_requestOH_T_6) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_7, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_9 = asSInt(_io_flit_bits_egress_id_requestOH_T_8) node _io_flit_bits_egress_id_requestOH_T_10 = eq(_io_flit_bits_egress_id_requestOH_T_9, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_11 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_10) node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_11) node _io_flit_bits_egress_id_requestOH_T_12 = xor(q.io.deq.bits.address, UInt<7>(0h40)) node _io_flit_bits_egress_id_requestOH_T_13 = cvt(_io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = and(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_15 = asSInt(_io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16) node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<8>(0h80)) node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18) node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20) node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_23 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_22) node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_23) node _io_flit_bits_egress_id_requestOH_T_24 = xor(q.io.deq.bits.address, UInt<8>(0hc0)) node _io_flit_bits_egress_id_requestOH_T_25 = cvt(_io_flit_bits_egress_id_requestOH_T_24) node _io_flit_bits_egress_id_requestOH_T_26 = and(_io_flit_bits_egress_id_requestOH_T_25, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_27 = asSInt(_io_flit_bits_egress_id_requestOH_T_26) node _io_flit_bits_egress_id_requestOH_T_28 = eq(_io_flit_bits_egress_id_requestOH_T_27, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28) node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0he), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<5>(0h10), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h12), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h14), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h16), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4) wire _io_flit_bits_egress_id_WIRE : UInt<5> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) connect has_body, has_body_opdata connect q.io.enq, io.protocol node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<6>(0h2c)) connect q.io.enq.bits.source, _q_io_enq_bits_source_T	module TLCToNoC_9( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [128:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [7:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire [7:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0; // @[package.scala:243:{46,71,76}] reg [7:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 8'h1 \| tail_beats1 == 8'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 8'h0; // @[Edges.scala:229:27] tail_counter <= 8'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0) : head_counter - 8'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 8'h0 ? tail_beats1 : tail_counter - 8'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_128 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_220 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_128( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_220 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TileClockGater : input clock : Clock input reset : Reset output auto : { flip clock_gater_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_gater_in_0 : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_gater_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}} wire clock_gaterOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clock_gaterOut.member.allClocks_uncore.reset invalidate clock_gaterOut.member.allClocks_uncore.clock wire clock_gaterIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clock_gaterIn.member.allClocks_uncore.reset invalidate clock_gaterIn.member.allClocks_uncore.clock connect clock_gaterOut, clock_gaterIn wire clock_gaterIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate clock_gaterIn_1.d.bits.corrupt invalidate clock_gaterIn_1.d.bits.data invalidate clock_gaterIn_1.d.bits.denied invalidate clock_gaterIn_1.d.bits.sink invalidate clock_gaterIn_1.d.bits.source invalidate clock_gaterIn_1.d.bits.size invalidate clock_gaterIn_1.d.bits.param invalidate clock_gaterIn_1.d.bits.opcode invalidate clock_gaterIn_1.d.valid invalidate clock_gaterIn_1.d.ready invalidate clock_gaterIn_1.a.bits.corrupt invalidate clock_gaterIn_1.a.bits.data invalidate clock_gaterIn_1.a.bits.mask invalidate clock_gaterIn_1.a.bits.address invalidate clock_gaterIn_1.a.bits.source invalidate clock_gaterIn_1.a.bits.size invalidate clock_gaterIn_1.a.bits.param invalidate clock_gaterIn_1.a.bits.opcode invalidate clock_gaterIn_1.a.valid invalidate clock_gaterIn_1.a.ready inst monitor of TLMonitor_83 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, clock_gaterIn_1.d.bits.corrupt connect monitor.io.in.d.bits.data, clock_gaterIn_1.d.bits.data connect monitor.io.in.d.bits.denied, clock_gaterIn_1.d.bits.denied connect monitor.io.in.d.bits.sink, clock_gaterIn_1.d.bits.sink connect monitor.io.in.d.bits.source, clock_gaterIn_1.d.bits.source connect monitor.io.in.d.bits.size, clock_gaterIn_1.d.bits.size connect monitor.io.in.d.bits.param, clock_gaterIn_1.d.bits.param connect monitor.io.in.d.bits.opcode, clock_gaterIn_1.d.bits.opcode connect monitor.io.in.d.valid, clock_gaterIn_1.d.valid connect monitor.io.in.d.ready, clock_gaterIn_1.d.ready connect monitor.io.in.a.bits.corrupt, clock_gaterIn_1.a.bits.corrupt connect monitor.io.in.a.bits.data, clock_gaterIn_1.a.bits.data connect monitor.io.in.a.bits.mask, clock_gaterIn_1.a.bits.mask connect monitor.io.in.a.bits.address, clock_gaterIn_1.a.bits.address connect monitor.io.in.a.bits.source, clock_gaterIn_1.a.bits.source connect monitor.io.in.a.bits.size, clock_gaterIn_1.a.bits.size connect monitor.io.in.a.bits.param, clock_gaterIn_1.a.bits.param connect monitor.io.in.a.bits.opcode, clock_gaterIn_1.a.bits.opcode connect monitor.io.in.a.valid, clock_gaterIn_1.a.valid connect monitor.io.in.a.ready, clock_gaterIn_1.a.ready connect auto.clock_gater_out, clock_gaterOut connect clock_gaterIn, auto.clock_gater_in_0 connect clock_gaterIn_1, auto.clock_gater_in_1 inst regs_0 of AsyncResetRegVec_w1_i1 connect regs_0.clock, clock connect regs_0.reset, clock_gaterIn.member.allClocks_uncore.reset connect clock_gaterOut.member.allClocks_uncore, clock_gaterIn.member.allClocks_uncore wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(clock_gaterIn_1.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(clock_gaterIn_1.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, clock_gaterIn_1.a.bits.data connect in.bits.mask, clock_gaterIn_1.a.bits.mask connect in.bits.extra.tlrr_extra.source, clock_gaterIn_1.a.bits.source connect in.bits.extra.tlrr_extra.size, clock_gaterIn_1.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[1] wire out_wivalid : UInt<1>[1] wire out_roready : UInt<1>[1] wire out_woready : UInt<1>[1] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 0, 0) connect regs_0.io.en, out_f_woready connect regs_0.io.d, _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(regs_0.io.q, UInt<1>(0h0)) node _out_T_8 = bits(_out_T_7, 0, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<1>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_8 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, clock_gaterIn_1.a.valid connect clock_gaterIn_1.a.ready, in.ready connect clock_gaterIn_1.d.valid, out.valid connect out.ready, clock_gaterIn_1.d.ready wire clock_gaterIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect clock_gaterIn_d_bits_d.opcode, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.param, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect clock_gaterIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect clock_gaterIn_d_bits_d.sink, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.denied, UInt<1>(0h0) invalidate clock_gaterIn_d_bits_d.data connect clock_gaterIn_d_bits_d.corrupt, UInt<1>(0h0) connect clock_gaterIn_1.d.bits.corrupt, clock_gaterIn_d_bits_d.corrupt connect clock_gaterIn_1.d.bits.data, clock_gaterIn_d_bits_d.data connect clock_gaterIn_1.d.bits.denied, clock_gaterIn_d_bits_d.denied connect clock_gaterIn_1.d.bits.sink, clock_gaterIn_d_bits_d.sink connect clock_gaterIn_1.d.bits.source, clock_gaterIn_d_bits_d.source connect clock_gaterIn_1.d.bits.size, clock_gaterIn_d_bits_d.size connect clock_gaterIn_1.d.bits.param, clock_gaterIn_d_bits_d.param connect clock_gaterIn_1.d.bits.opcode, clock_gaterIn_d_bits_d.opcode connect clock_gaterIn_1.d.bits.data, out.bits.data node _clock_gaterIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect clock_gaterIn_1.d.bits.opcode, _clock_gaterIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) extmodule plusarg_reader_183 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_184 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TileClockGater( // @[TileClockGater.scala:27:25] input clock, // @[TileClockGater.scala:27:25] input reset, // @[TileClockGater.scala:27:25] output auto_clock_gater_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_clock_gater_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_clock_gater_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_clock_gater_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_clock_gater_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_clock_gater_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_clock_gater_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_clock_gater_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_clock_gater_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_clock_gater_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_reset // @[LazyModuleImp.scala:107:25] ); wire _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _regs_0_io_q; // @[TileClockGater.scala:33:53] wire in_bits_read = auto_clock_gater_in_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire _out_T_1 = auto_clock_gater_in_1_a_bits_address[11:3] == 9'h0; // @[RegisterRouter.scala:75:19, :87:24] assign _out_wofireMux_T_1 = ~in_bits_read; // @[RegisterRouter.scala:74:36, :87:24] wire [2:0] monitor_io_in_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] TLMonitor_83 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_clock_gater_in_1_d_ready), .io_in_a_valid (auto_clock_gater_in_1_a_valid), .io_in_a_bits_opcode (auto_clock_gater_in_1_a_bits_opcode), .io_in_a_bits_param (auto_clock_gater_in_1_a_bits_param), .io_in_a_bits_size (auto_clock_gater_in_1_a_bits_size), .io_in_a_bits_source (auto_clock_gater_in_1_a_bits_source), .io_in_a_bits_address (auto_clock_gater_in_1_a_bits_address), .io_in_a_bits_mask (auto_clock_gater_in_1_a_bits_mask), .io_in_a_bits_corrupt (auto_clock_gater_in_1_a_bits_corrupt), .io_in_d_ready (auto_clock_gater_in_1_d_ready), .io_in_d_valid (auto_clock_gater_in_1_a_valid), .io_in_d_bits_opcode (monitor_io_in_d_bits_opcode), // @[RegisterRouter.scala:105:19] .io_in_d_bits_size (auto_clock_gater_in_1_a_bits_size), .io_in_d_bits_source (auto_clock_gater_in_1_a_bits_source) ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i1 regs_0 ( // @[TileClockGater.scala:33:53] .clock (clock), .reset (auto_clock_gater_in_0_member_allClocks_uncore_reset), .io_d (auto_clock_gater_in_1_a_bits_data[0]), // @[RegisterRouter.scala:87:24] .io_q (_regs_0_io_q), .io_en (auto_clock_gater_in_1_a_valid & auto_clock_gater_in_1_d_ready & _out_wofireMux_T_1 & _out_T_1 & auto_clock_gater_in_1_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] ); // @[TileClockGater.scala:33:53] assign auto_clock_gater_in_1_a_ready = auto_clock_gater_in_1_d_ready; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_valid = auto_clock_gater_in_1_a_valid; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_opcode = monitor_io_in_d_bits_opcode; // @[RegisterRouter.scala:105:19] assign auto_clock_gater_in_1_d_bits_size = auto_clock_gater_in_1_a_bits_size; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_source = auto_clock_gater_in_1_a_bits_source; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_data = {63'h0, _out_T_1 & _regs_0_io_q}; // @[RegisterRouter.scala:87:24] assign auto_clock_gater_out_member_allClocks_uncore_clock = auto_clock_gater_in_0_member_allClocks_uncore_clock; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_reset = auto_clock_gater_in_0_member_allClocks_uncore_reset; // @[TileClockGater.scala:27:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_47 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) when io.en : connect reg, io.d connect io.q, reg	module AsyncResetRegVec_w1_i0_47( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_80 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<5>, vc_free : UInt<5>}} wire _in_flight_WIRE : UInt<1>[5] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) regreset in_flight : UInt<1>[5], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = or(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_16 = or(_T_15, UInt<1>(0h0)) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_21 = or(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_21, UInt<1>(0h1), "") : assert_4 node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_27 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_28 = and(_T_26, _T_27) node _T_29 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_32 = and(_T_30, _T_31) node _T_33 = or(_T_25, _T_32) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_33, UInt<1>(0h1), "") : assert_5	module NoCMonitor_80( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_17 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_17 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_17( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_17 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_1 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<6>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<6>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<6>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<6>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<6>, clock reg probes_toN : UInt<6>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<6>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_T = eq(request.source, UInt<6>(0h24)) node _req_clientBit_T_1 = eq(request.source, UInt<6>(0h2e)) node _req_clientBit_T_2 = eq(request.source, UInt<6>(0h2c)) node _req_clientBit_T_3 = eq(request.source, UInt<6>(0h2a)) node _req_clientBit_T_4 = eq(request.source, UInt<6>(0h28)) node _req_clientBit_T_5 = eq(request.source, UInt<6>(0h20)) node req_clientBit_lo_hi = cat(_req_clientBit_T_2, _req_clientBit_T_1) node req_clientBit_lo = cat(req_clientBit_lo_hi, _req_clientBit_T) node req_clientBit_hi_hi = cat(_req_clientBit_T_5, _req_clientBit_T_4) node req_clientBit_hi = cat(req_clientBit_hi_hi, _req_clientBit_T_3) node req_clientBit = cat(req_clientBit_hi, req_clientBit_lo) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<6>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<6>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node _probe_bit_T = eq(io.sinkc.bits.source, UInt<6>(0h24)) node _probe_bit_T_1 = eq(io.sinkc.bits.source, UInt<6>(0h2e)) node _probe_bit_T_2 = eq(io.sinkc.bits.source, UInt<6>(0h2c)) node _probe_bit_T_3 = eq(io.sinkc.bits.source, UInt<6>(0h2a)) node _probe_bit_T_4 = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _probe_bit_T_5 = eq(io.sinkc.bits.source, UInt<6>(0h20)) node probe_bit_lo_hi = cat(_probe_bit_T_2, _probe_bit_T_1) node probe_bit_lo = cat(probe_bit_lo_hi, _probe_bit_T) node probe_bit_hi_hi = cat(_probe_bit_T_5, _probe_bit_T_4) node probe_bit_hi = cat(probe_bit_hi_hi, _probe_bit_T_3) node probe_bit = cat(probe_bit_hi, probe_bit_lo) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_T = eq(new_request.source, UInt<6>(0h24)) node _new_clientBit_T_1 = eq(new_request.source, UInt<6>(0h2e)) node _new_clientBit_T_2 = eq(new_request.source, UInt<6>(0h2c)) node _new_clientBit_T_3 = eq(new_request.source, UInt<6>(0h2a)) node _new_clientBit_T_4 = eq(new_request.source, UInt<6>(0h28)) node _new_clientBit_T_5 = eq(new_request.source, UInt<6>(0h20)) node new_clientBit_lo_hi = cat(_new_clientBit_T_2, _new_clientBit_T_1) node new_clientBit_lo = cat(new_clientBit_lo_hi, _new_clientBit_T) node new_clientBit_hi_hi = cat(_new_clientBit_T_5, _new_clientBit_T_4) node new_clientBit_hi = cat(new_clientBit_hi_hi, _new_clientBit_T_3) node new_clientBit = cat(new_clientBit_hi, new_clientBit_lo) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_1( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [5:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [5:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [5:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [5:0] invalid_clients = 6'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [5:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [5:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [5:0] meta_clients; // @[MSHR.scala:100:17] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [5:0] probes_done; // @[MSHR.scala:150:24] reg [5:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [5:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire _req_clientBit_T = request_source == 6'h24; // @[Parameters.scala:46:9] wire _req_clientBit_T_1 = request_source == 6'h2E; // @[Parameters.scala:46:9] wire _req_clientBit_T_2 = request_source == 6'h2C; // @[Parameters.scala:46:9] wire _req_clientBit_T_3 = request_source == 6'h2A; // @[Parameters.scala:46:9] wire _req_clientBit_T_4 = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_clientBit_T_5 = request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_lo_hi = {_req_clientBit_T_2, _req_clientBit_T_1}; // @[Parameters.scala:46:9] wire [2:0] req_clientBit_lo = {req_clientBit_lo_hi, _req_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_hi_hi = {_req_clientBit_T_5, _req_clientBit_T_4}; // @[Parameters.scala:46:9] wire [2:0] req_clientBit_hi = {req_clientBit_hi_hi, _req_clientBit_T_3}; // @[Parameters.scala:46:9] wire [5:0] req_clientBit = {req_clientBit_hi, req_clientBit_lo}; // @[Parameters.scala:201:10] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = \|meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [5:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 6'h0; // @[Parameters.scala:201:10, :282:66] wire [5:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [5:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [5:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [5:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [5:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [5:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [5:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 6'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [5:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 6'h0; // @[Parameters.scala:201:10] wire [5:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [5:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [5:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 6'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [5:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = \|_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire [5:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 6'h0; // @[Parameters.scala:201:10] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire [5:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 6'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _probe_bit_T = io_sinkc_bits_source_0 == 6'h24; // @[Parameters.scala:46:9] wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 6'h2E; // @[Parameters.scala:46:9] wire _probe_bit_T_2 = io_sinkc_bits_source_0 == 6'h2C; // @[Parameters.scala:46:9] wire _probe_bit_T_3 = io_sinkc_bits_source_0 == 6'h2A; // @[Parameters.scala:46:9] wire _probe_bit_T_4 = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _probe_bit_T_5 = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9] wire [1:0] probe_bit_lo_hi = {_probe_bit_T_2, _probe_bit_T_1}; // @[Parameters.scala:46:9] wire [2:0] probe_bit_lo = {probe_bit_lo_hi, _probe_bit_T}; // @[Parameters.scala:46:9] wire [1:0] probe_bit_hi_hi = {_probe_bit_T_5, _probe_bit_T_4}; // @[Parameters.scala:46:9] wire [2:0] probe_bit_hi = {probe_bit_hi_hi, _probe_bit_T_3}; // @[Parameters.scala:46:9] wire [5:0] probe_bit = {probe_bit_hi, probe_bit_lo}; // @[Parameters.scala:201:10] wire [5:0] _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:201:10] wire [5:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [5:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire [5:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire [5:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [5:0] _probes_toN_T = probe_toN ? probe_bit : 6'h0; // @[Parameters.scala:201:10, :282:66] wire [5:0] _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [5:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _new_clientBit_T = new_request_source == 6'h24; // @[Parameters.scala:46:9] wire _new_clientBit_T_1 = new_request_source == 6'h2E; // @[Parameters.scala:46:9] wire _new_clientBit_T_2 = new_request_source == 6'h2C; // @[Parameters.scala:46:9] wire _new_clientBit_T_3 = new_request_source == 6'h2A; // @[Parameters.scala:46:9] wire _new_clientBit_T_4 = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_clientBit_T_5 = new_request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_lo_hi = {_new_clientBit_T_2, _new_clientBit_T_1}; // @[Parameters.scala:46:9] wire [2:0] new_clientBit_lo = {new_clientBit_lo_hi, _new_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_hi_hi = {_new_clientBit_T_5, _new_clientBit_T_4}; // @[Parameters.scala:46:9] wire [2:0] new_clientBit_hi = {new_clientBit_hi_hi, _new_clientBit_T_3}; // @[Parameters.scala:46:9] wire [5:0] new_clientBit = {new_clientBit_hi, new_clientBit_lo}; // @[Parameters.scala:201:10] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [5:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 6'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_TileResetSetter : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_45 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) reg dOrig : UInt, clock regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) node dFragnum = bits(anonOut.d.bits.source, 2, 0) node dFirst = eq(acknum, UInt<1>(0h0)) node dLast = eq(dFragnum, UInt<1>(0h0)) node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) node dsizeOH = bits(_dsizeOH_T, 3, 0) node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) node dsizeOH1 = not(_dsizeOH1_T_1) node dHasData = bits(anonOut.d.bits.opcode, 0, 0) node acknum_fragment = shl(dFragnum, 0) node acknum_size = shr(dsizeOH1, 3) node _T = eq(anonOut.d.valid, UInt<1>(0h0)) node _T_1 = and(acknum_fragment, acknum_size) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = or(_T, _T_2) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) node _ack_decrement_T = shr(dsizeOH, 3) node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) node _dFirst_size_T = shl(dFragnum, 3) node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) node _dFirst_size_T_5 = not(_dFirst_size_T_4) node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) node _dFirst_size_T_7 = orr(dFirst_size_hi) node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) node _dFirst_size_T_9 = orr(dFirst_size_hi_1) node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) node _T_7 = and(anonOut.d.ready, anonOut.d.valid) when _T_7 : node _acknum_T = sub(acknum, ack_decrement) node _acknum_T_1 = tail(_acknum_T, 1) node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) connect acknum, _acknum_T_2 when dFirst : connect dOrig, dFirst_size node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) connect dToggle, _dToggle_T node _drop_T = eq(dHasData, UInt<1>(0h0)) node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) node drop = and(_drop_T, _drop_T_2) node _anonOut_d_ready_T = or(anonIn.d.ready, drop) connect anonOut.d.ready, _anonOut_d_ready_T node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) connect anonIn.d.valid, _anonIn_d_valid_T_1 connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) connect anonIn.d.bits.source, _anonIn_d_bits_source_T node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) connect anonIn.d.bits.size, _anonIn_d_bits_size_T inst repeater of Repeater_TLBundleA_a21d64s7k1z3u_1 connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) node _find_T_1 = cvt(_find_T) node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) node _find_T_3 = asSInt(_find_T_2) node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) wire find : UInt<1>[1] connect find[0], _find_T_4 node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) node _aFrag_T = gt(repeater.io.deq.bits.size, limit) node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) node aOrigOH1 = not(_aOrigOH1_T_1) node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) node aFragOH1 = not(_aFragOH1_T_1) node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) node aFirst = eq(gennum, UInt<1>(0h0)) node _old_gennum1_T = shr(aOrigOH1, 3) node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) node _new_gennum_T = not(old_gennum1) node _new_gennum_T_1 = shr(aMask, 3) node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) node new_gennum = not(_new_gennum_T_2) node _aFragnum_T = shr(old_gennum1, 0) node _aFragnum_T_1 = not(_aFragnum_T) node _aFragnum_T_2 = shr(aFragOH1, 3) node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) node aFragnum = not(_aFragnum_T_3) node aLast = eq(aFragnum, UInt<1>(0h0)) reg aToggle_r : UInt<1>, clock when aFirst : connect aToggle_r, dToggle node _aToggle_T = mux(aFirst, dToggle, aToggle_r) node aToggle = eq(_aToggle_T, UInt<1>(0h0)) node _T_8 = and(anonOut.a.ready, anonOut.a.valid) when _T_8 : connect gennum, new_gennum node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) connect repeater.io.repeat, _repeater_io_repeat_T_2 connect anonOut.a.bits, repeater.io.deq.bits connect anonOut.a.valid, repeater.io.deq.valid connect repeater.io.deq.ready, anonOut.a.ready node _anonOut_a_bits_address_T = shl(old_gennum1, 3) node _anonOut_a_bits_address_T_1 = not(aOrigOH1) node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) connect anonOut.a.bits.source, _anonOut_a_bits_source_T connect anonOut.a.bits.size, aFrag node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) node _T_10 = eq(aHasData, UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full \|\| !aHasData)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 connect anonOut.a.bits.data, anonIn.a.bits.data node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) node _T_17 = or(_T_15, _T_16) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full \|\| in_a.bits.mask === fullMask)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T wire anonOut_a_bits_user_out : { } wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLFragmenter_TileResetSetter( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_anon_out_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [20:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9] wire [6:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9] wire [20:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9] wire [10:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_d_bits_data = 64'h0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_d_bits_data = 64'h0; // @[Fragmenter.scala:92:9] wire [63:0] anonIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] anonOut_d_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36] wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50] wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50] wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84] wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49] wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59] wire find_0 = 1'h1; // @[Parameters.scala:616:12] wire [21:0] _find_T_2 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _find_T_3 = 22'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [6:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [20:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [10:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [10:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [6:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [10:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [20:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9] assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9] wire [6:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9] wire [10:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9] wire [20:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire [2:0] dFragnum = anonOut_d_bits_source[2:0]; // @[Fragmenter.scala:204:41] wire [2:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala:204:41, :206:30] wire _drop_T_1 = dLast; // @[Fragmenter.scala:206:30, :234:37] wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] dsizeOH = _dsizeOH_T; // @[OneHot.scala:65:{12,27}] wire [5:0] _dsizeOH1_T = 6'h7 << anonOut_d_bits_size; // @[package.scala:243:71] wire [2:0] _dsizeOH1_T_1 = _dsizeOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}] wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45] wire _ack_decrement_T = dsizeOH[3]; // @[OneHot.scala:65:27] wire ack_decrement = dHasData \| _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}] wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala:204:41, :218:47] wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:3], _dFirst_size_T[2:0] \| dsizeOH1}; // @[package.scala:243:46] wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35] wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}] wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53] wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}] wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}] wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18] wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18] wire _dFirst_size_T_7 = \|dFirst_size_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} \| dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28] wire _dFirst_size_T_9 = \|dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 \| dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28] wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}] wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}] wire [3:0] _acknum_T = {1'h0, acknum} - {3'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55] wire [2:0] _acknum_T_1 = _acknum_T[2:0]; // @[Fragmenter.scala:221:55] wire [2:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}] wire _dToggle_T = anonOut_d_bits_source[3]; // @[Fragmenter.scala:224:41] wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20] wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}] wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}] assign _anonOut_d_ready_T = anonIn_d_ready \| drop; // @[Fragmenter.scala:234:30, :235:35] assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39] assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}] assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign _anonIn_d_bits_source_T = anonOut_d_bits_source[10:4]; // @[Fragmenter.scala:238:47] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] wire [20:0] _find_T; // @[Parameters.scala:137:31] wire [21:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}] wire _limit_T = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49] wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31] wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}] wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71] wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}] wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30] wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46] wire [3:0] _old_gennum1_T_1 = {1'h0, gennum} - 4'h1; // @[Fragmenter.scala:303:29, :305:79] wire [2:0] _old_gennum1_T_2 = _old_gennum1_T_1[2:0]; // @[Fragmenter.scala:305:79] wire [2:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}] wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40] wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28] wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}] wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}] wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}] wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}] wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}] wire aLast = ~(\|aFragnum); // @[Fragmenter.scala:307:24, :308:30] reg aToggle_r; // @[Fragmenter.scala:309:54] wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}] wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}] wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31] wire _repeater_io_repeat_T_1 = \|aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53] wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}] wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65] wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T \| _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}] wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] \| aFragOH1}; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}] wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}] assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[20:6], _repeater_io_deq_bits_address[5:0] \| _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}] assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] wire [7:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aToggle}; // @[Fragmenter.scala:274:30, :309:23, :317:33] assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, aFragnum}; // @[Fragmenter.scala:307:24, :317:33] assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25]
Generate the Verilog code corresponding to this FIRRTL code module L2MemHelperLatencyInjection : input clock : Clock input reset : Reset output auto : { master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}} output io : { flip userif : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip latency_inject_cycles : UInt<64>, flip sfence : UInt<1>, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip status : { valid : UInt<1>, bits : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}} invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready connect auto.master_out, masterNodeOut wire request_input : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}} connect request_input, io.userif.req wire response_output : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}} connect io.userif.resp, response_output reg status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock when io.status.valid : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "[fhdr_writer] setting status.dprv to: %x compare %x\n", io.status.bits.dprv, UInt<2>(0h3)) : printf_1 connect status, io.status.bits inst tlb of DTLB_2 connect tlb.clock, clock connect tlb.reset, reset connect tlb.io.req.valid, request_input.valid connect tlb.io.req.bits.vaddr, request_input.bits.addr connect tlb.io.req.bits.size, request_input.bits.size connect tlb.io.req.bits.cmd, request_input.bits.cmd connect tlb.io.req.bits.passthrough, UInt<1>(0h0) node _tlb_ready_T = eq(tlb.io.resp.miss, UInt<1>(0h0)) node tlb_ready = and(tlb.io.req.ready, _tlb_ready_T) invalidate tlb.io.req.bits.prv invalidate tlb.io.req.bits.v invalidate tlb.io.sfence.bits.hv invalidate tlb.io.sfence.bits.hg connect tlb.io.ptw.customCSRs, io.ptw.customCSRs connect tlb.io.ptw.pmp[0], io.ptw.pmp[0] connect tlb.io.ptw.pmp[1], io.ptw.pmp[1] connect tlb.io.ptw.pmp[2], io.ptw.pmp[2] connect tlb.io.ptw.pmp[3], io.ptw.pmp[3] connect tlb.io.ptw.pmp[4], io.ptw.pmp[4] connect tlb.io.ptw.pmp[5], io.ptw.pmp[5] connect tlb.io.ptw.pmp[6], io.ptw.pmp[6] connect tlb.io.ptw.pmp[7], io.ptw.pmp[7] connect tlb.io.ptw.gstatus, io.ptw.gstatus connect tlb.io.ptw.hstatus, io.ptw.hstatus connect tlb.io.ptw.status, io.ptw.status connect tlb.io.ptw.vsatp, io.ptw.vsatp connect tlb.io.ptw.hgatp, io.ptw.hgatp connect tlb.io.ptw.ptbr, io.ptw.ptbr connect tlb.io.ptw.resp, io.ptw.resp connect io.ptw.req.bits, tlb.io.ptw.req.bits connect io.ptw.req.valid, tlb.io.ptw.req.valid connect tlb.io.ptw.req.ready, io.ptw.req.ready connect tlb.io.ptw.status.uie, status.uie connect tlb.io.ptw.status.sie, status.sie connect tlb.io.ptw.status.hie, status.hie connect tlb.io.ptw.status.mie, status.mie connect tlb.io.ptw.status.upie, status.upie connect tlb.io.ptw.status.spie, status.spie connect tlb.io.ptw.status.ube, status.ube connect tlb.io.ptw.status.mpie, status.mpie connect tlb.io.ptw.status.spp, status.spp connect tlb.io.ptw.status.vs, status.vs connect tlb.io.ptw.status.mpp, status.mpp connect tlb.io.ptw.status.fs, status.fs connect tlb.io.ptw.status.xs, status.xs connect tlb.io.ptw.status.mprv, status.mprv connect tlb.io.ptw.status.sum, status.sum connect tlb.io.ptw.status.mxr, status.mxr connect tlb.io.ptw.status.tvm, status.tvm connect tlb.io.ptw.status.tw, status.tw connect tlb.io.ptw.status.tsr, status.tsr connect tlb.io.ptw.status.zero1, status.zero1 connect tlb.io.ptw.status.sd_rv32, status.sd_rv32 connect tlb.io.ptw.status.uxl, status.uxl connect tlb.io.ptw.status.sxl, status.sxl connect tlb.io.ptw.status.sbe, status.sbe connect tlb.io.ptw.status.mbe, status.mbe connect tlb.io.ptw.status.gva, status.gva connect tlb.io.ptw.status.mpv, status.mpv connect tlb.io.ptw.status.zero2, status.zero2 connect tlb.io.ptw.status.sd, status.sd connect tlb.io.ptw.status.v, status.v connect tlb.io.ptw.status.prv, status.prv connect tlb.io.ptw.status.dv, status.dv connect tlb.io.ptw.status.dprv, status.dprv connect tlb.io.ptw.status.isa, status.isa connect tlb.io.ptw.status.wfi, status.wfi connect tlb.io.ptw.status.cease, status.cease connect tlb.io.ptw.status.debug, status.debug connect tlb.io.sfence.valid, io.sfence connect tlb.io.sfence.bits.rs1, UInt<1>(0h0) connect tlb.io.sfence.bits.rs2, UInt<1>(0h0) connect tlb.io.sfence.bits.addr, UInt<1>(0h0) connect tlb.io.sfence.bits.asid, UInt<1>(0h0) connect tlb.io.kill, UInt<1>(0h0) inst outstanding_req_addr of Queue16_L2InternalTracking connect outstanding_req_addr.clock, clock connect outstanding_req_addr.reset, reset inst tags_for_issue_Q of Queue8_UInt2 connect tags_for_issue_Q.clock, clock connect tags_for_issue_Q.reset, reset connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h0) invalidate tags_for_issue_Q.io.enq.bits regreset tags_init_reg : UInt<3>, clock, reset, UInt<3>(0h0) node _T_4 = neq(tags_init_reg, UInt<3>(0h4)) when _T_4 : connect tags_for_issue_Q.io.enq.bits, tags_init_reg connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h1) when tags_for_issue_Q.io.enq.ready : regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "[fhdr_writer] tags_for_issue_Q init with value %d\n", tags_for_issue_Q.io.enq.bits) : printf_3 node _tags_init_reg_T = add(tags_init_reg, UInt<1>(0h1)) node _tags_init_reg_T_1 = tail(_tags_init_reg_T, 1) connect tags_init_reg, _tags_init_reg_T_1 node _addr_mask_check_T = dshl(UInt<64>(0h1), request_input.bits.size) node _addr_mask_check_T_1 = sub(_addr_mask_check_T, UInt<1>(0h1)) node addr_mask_check = tail(_addr_mask_check_T_1, 1) node _assertcheck_T = eq(request_input.valid, UInt<1>(0h0)) node _assertcheck_T_1 = and(request_input.bits.addr, addr_mask_check) node _assertcheck_T_2 = eq(_assertcheck_T_1, UInt<1>(0h0)) node _assertcheck_T_3 = or(_assertcheck_T, _assertcheck_T_2) reg assertcheck : UInt<1>, clock connect assertcheck, _assertcheck_T_3 node _T_9 = eq(assertcheck, UInt<1>(0h0)) when _T_9 : regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "[fhdr_writer] L2IF: access addr must be aligned to write width\n") : printf_5 node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(assertcheck, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed: [fhdr_writer] L2IF: access addr must be aligned to write width\n\n at L2MemHelperLatencyInjection.scala:114 assert(assertcheck,\n") : printf_6 assert(clock, assertcheck, UInt<1>(0h1), "") : assert regreset global_memop_accepted : UInt<64>, clock, reset, UInt<64>(0h0) node _T_17 = and(io.userif.req.ready, io.userif.req.valid) when _T_17 : node _global_memop_accepted_T = add(global_memop_accepted, UInt<1>(0h1)) node _global_memop_accepted_T_1 = tail(_global_memop_accepted_T, 1) connect global_memop_accepted, _global_memop_accepted_T_1 regreset global_memop_sent : UInt<64>, clock, reset, UInt<64>(0h0) regreset global_memop_ackd : UInt<64>, clock, reset, UInt<64>(0h0) regreset global_memop_resp_to_user : UInt<64>, clock, reset, UInt<64>(0h0) node _io_userif_no_memops_inflight_T = eq(global_memop_accepted, global_memop_ackd) connect io.userif.no_memops_inflight, _io_userif_no_memops_inflight_T node _free_outstanding_op_slots_T = sub(global_memop_sent, global_memop_ackd) node _free_outstanding_op_slots_T_1 = tail(_free_outstanding_op_slots_T, 1) node free_outstanding_op_slots = lt(_free_outstanding_op_slots_T_1, UInt<3>(0h4)) node _assert_free_outstanding_op_slots_T = sub(global_memop_sent, global_memop_ackd) node _assert_free_outstanding_op_slots_T_1 = tail(_assert_free_outstanding_op_slots_T, 1) node assert_free_outstanding_op_slots = leq(_assert_free_outstanding_op_slots_T_1, UInt<3>(0h4)) node _T_18 = eq(assert_free_outstanding_op_slots, UInt<1>(0h0)) when _T_18 : regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_7 node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "[fhdr_writer] L2IF: Too many outstanding requests for tag count.\n") : printf_8 node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(assert_free_outstanding_op_slots, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed: [fhdr_writer] L2IF: Too many outstanding requests for tag count.\n\n at L2MemHelperLatencyInjection.scala:136 assert(assert_free_outstanding_op_slots,\n") : printf_9 assert(clock, assert_free_outstanding_op_slots, UInt<1>(0h1), "") : assert_1 node _T_26 = and(request_input.ready, request_input.valid) when _T_26 : node _global_memop_sent_T = add(global_memop_sent, UInt<1>(0h1)) node _global_memop_sent_T_1 = tail(_global_memop_sent_T, 1) connect global_memop_sent, _global_memop_sent_T_1 regreset cur_cycle : UInt<64>, clock, reset, UInt<64>(0h0) node _cur_cycle_T = add(cur_cycle, UInt<1>(0h1)) node _cur_cycle_T_1 = tail(_cur_cycle_T, 1) connect cur_cycle, _cur_cycle_T_1 inst request_latency_injection_q of LatencyInjectionQueue connect request_latency_injection_q.clock, clock connect request_latency_injection_q.reset, reset connect request_latency_injection_q.io.latency_cycles, io.latency_inject_cycles invalidate request_latency_injection_q.io.enq.bits.corrupt invalidate request_latency_injection_q.io.enq.bits.data invalidate request_latency_injection_q.io.enq.bits.mask invalidate request_latency_injection_q.io.enq.bits.address invalidate request_latency_injection_q.io.enq.bits.source invalidate request_latency_injection_q.io.enq.bits.size invalidate request_latency_injection_q.io.enq.bits.param invalidate request_latency_injection_q.io.enq.bits.opcode node _T_27 = eq(request_input.bits.cmd, UInt<1>(0h0)) when _T_27 : node _legal_T = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_1 = leq(request_input.bits.size, UInt<4>(0hc)) node _legal_T_2 = and(_legal_T, _legal_T_1) node _legal_T_3 = or(UInt<1>(0h0), _legal_T_2) node _legal_T_4 = xor(tlb.io.resp.paddr, UInt<14>(0h3000)) node _legal_T_5 = cvt(_legal_T_4) node _legal_T_6 = and(_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _legal_T_7 = asSInt(_legal_T_6) node _legal_T_8 = eq(_legal_T_7, asSInt(UInt<1>(0h0))) node _legal_T_9 = and(_legal_T_3, _legal_T_8) node _legal_T_10 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_11 = leq(request_input.bits.size, UInt<3>(0h6)) node _legal_T_12 = and(_legal_T_10, _legal_T_11) node _legal_T_13 = or(UInt<1>(0h0), _legal_T_12) node _legal_T_14 = xor(tlb.io.resp.paddr, UInt<1>(0h0)) node _legal_T_15 = cvt(_legal_T_14) node _legal_T_16 = and(_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _legal_T_17 = asSInt(_legal_T_16) node _legal_T_18 = eq(_legal_T_17, asSInt(UInt<1>(0h0))) node _legal_T_19 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_20 = cvt(_legal_T_19) node _legal_T_21 = and(_legal_T_20, asSInt(UInt<33>(0h98013000))) node _legal_T_22 = asSInt(_legal_T_21) node _legal_T_23 = eq(_legal_T_22, asSInt(UInt<1>(0h0))) node _legal_T_24 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_25 = cvt(_legal_T_24) node _legal_T_26 = and(_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _legal_T_27 = asSInt(_legal_T_26) node _legal_T_28 = eq(_legal_T_27, asSInt(UInt<1>(0h0))) node _legal_T_29 = xor(tlb.io.resp.paddr, UInt<26>(0h2000000)) node _legal_T_30 = cvt(_legal_T_29) node _legal_T_31 = and(_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _legal_T_32 = asSInt(_legal_T_31) node _legal_T_33 = eq(_legal_T_32, asSInt(UInt<1>(0h0))) node _legal_T_34 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_35 = cvt(_legal_T_34) node _legal_T_36 = and(_legal_T_35, asSInt(UInt<33>(0h98000000))) node _legal_T_37 = asSInt(_legal_T_36) node _legal_T_38 = eq(_legal_T_37, asSInt(UInt<1>(0h0))) node _legal_T_39 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_40 = cvt(_legal_T_39) node _legal_T_41 = and(_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _legal_T_42 = asSInt(_legal_T_41) node _legal_T_43 = eq(_legal_T_42, asSInt(UInt<1>(0h0))) node _legal_T_44 = xor(tlb.io.resp.paddr, UInt<29>(0h10000000)) node _legal_T_45 = cvt(_legal_T_44) node _legal_T_46 = and(_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _legal_T_47 = asSInt(_legal_T_46) node _legal_T_48 = eq(_legal_T_47, asSInt(UInt<1>(0h0))) node _legal_T_49 = xor(tlb.io.resp.paddr, UInt<32>(0h80000000)) node _legal_T_50 = cvt(_legal_T_49) node _legal_T_51 = and(_legal_T_50, asSInt(UInt<33>(0h90000000))) node _legal_T_52 = asSInt(_legal_T_51) node _legal_T_53 = eq(_legal_T_52, asSInt(UInt<1>(0h0))) node _legal_T_54 = or(_legal_T_18, _legal_T_23) node _legal_T_55 = or(_legal_T_54, _legal_T_28) node _legal_T_56 = or(_legal_T_55, _legal_T_33) node _legal_T_57 = or(_legal_T_56, _legal_T_38) node _legal_T_58 = or(_legal_T_57, _legal_T_43) node _legal_T_59 = or(_legal_T_58, _legal_T_48) node _legal_T_60 = or(_legal_T_59, _legal_T_53) node _legal_T_61 = and(_legal_T_13, _legal_T_60) node _legal_T_62 = or(UInt<1>(0h0), _legal_T_9) node legal = or(_legal_T_62, _legal_T_61) wire bundle : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>} connect bundle.opcode, UInt<3>(0h4) connect bundle.param, UInt<1>(0h0) connect bundle.size, request_input.bits.size connect bundle.source, tags_for_issue_Q.io.deq.bits connect bundle.address, tlb.io.resp.paddr node _a_mask_sizeOH_T = or(request_input.bits.size, UInt<5>(0h0)) node _a_mask_sizeOH_shiftAmount_T = pad(_a_mask_sizeOH_T, 3) node a_mask_sizeOH_shiftAmount = bits(_a_mask_sizeOH_shiftAmount_T, 2, 0) node _a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount) node _a_mask_sizeOH_T_2 = bits(_a_mask_sizeOH_T_1, 4, 0) node a_mask_sizeOH = or(_a_mask_sizeOH_T_2, UInt<1>(0h1)) node a_mask_sub_sub_sub_sub_sub_0_1 = geq(request_input.bits.size, UInt<3>(0h5)) node a_mask_sub_sub_sub_sub_size = bits(a_mask_sizeOH, 4, 4) node a_mask_sub_sub_sub_sub_bit = bits(tlb.io.resp.paddr, 4, 4) node a_mask_sub_sub_sub_sub_nbit = eq(a_mask_sub_sub_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_sub_sub_0_2 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_sub_acc_T = and(a_mask_sub_sub_sub_sub_size, a_mask_sub_sub_sub_sub_0_2) node a_mask_sub_sub_sub_sub_0_1 = or(a_mask_sub_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_sub_acc_T) node a_mask_sub_sub_sub_sub_1_2 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_bit) node _a_mask_sub_sub_sub_sub_acc_T_1 = and(a_mask_sub_sub_sub_sub_size, a_mask_sub_sub_sub_sub_1_2) node a_mask_sub_sub_sub_sub_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_sub_acc_T_1) node a_mask_sub_sub_sub_size = bits(a_mask_sizeOH, 3, 3) node a_mask_sub_sub_sub_bit = bits(tlb.io.resp.paddr, 3, 3) node a_mask_sub_sub_sub_nbit = eq(a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_sub_0_2 = and(a_mask_sub_sub_sub_sub_0_2, a_mask_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_acc_T = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_0_2) node a_mask_sub_sub_sub_0_1 = or(a_mask_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_acc_T) node a_mask_sub_sub_sub_1_2 = and(a_mask_sub_sub_sub_sub_0_2, a_mask_sub_sub_sub_bit) node _a_mask_sub_sub_sub_acc_T_1 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_1_2) node a_mask_sub_sub_sub_1_1 = or(a_mask_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_acc_T_1) node a_mask_sub_sub_sub_2_2 = and(a_mask_sub_sub_sub_sub_1_2, a_mask_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_acc_T_2 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_2_2) node a_mask_sub_sub_sub_2_1 = or(a_mask_sub_sub_sub_sub_1_1, _a_mask_sub_sub_sub_acc_T_2) node a_mask_sub_sub_sub_3_2 = and(a_mask_sub_sub_sub_sub_1_2, a_mask_sub_sub_sub_bit) node _a_mask_sub_sub_sub_acc_T_3 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_3_2) node a_mask_sub_sub_sub_3_1 = or(a_mask_sub_sub_sub_sub_1_1, _a_mask_sub_sub_sub_acc_T_3) node a_mask_sub_sub_size = bits(a_mask_sizeOH, 2, 2) node a_mask_sub_sub_bit = bits(tlb.io.resp.paddr, 2, 2) node a_mask_sub_sub_nbit = eq(a_mask_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_0_2 = and(a_mask_sub_sub_sub_0_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T = and(a_mask_sub_sub_size, a_mask_sub_sub_0_2) node a_mask_sub_sub_0_1 = or(a_mask_sub_sub_sub_0_1, _a_mask_sub_sub_acc_T) node a_mask_sub_sub_1_2 = and(a_mask_sub_sub_sub_0_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_1 = and(a_mask_sub_sub_size, a_mask_sub_sub_1_2) node a_mask_sub_sub_1_1 = or(a_mask_sub_sub_sub_0_1, _a_mask_sub_sub_acc_T_1) node a_mask_sub_sub_2_2 = and(a_mask_sub_sub_sub_1_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_2 = and(a_mask_sub_sub_size, a_mask_sub_sub_2_2) node a_mask_sub_sub_2_1 = or(a_mask_sub_sub_sub_1_1, _a_mask_sub_sub_acc_T_2) node a_mask_sub_sub_3_2 = and(a_mask_sub_sub_sub_1_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_3 = and(a_mask_sub_sub_size, a_mask_sub_sub_3_2) node a_mask_sub_sub_3_1 = or(a_mask_sub_sub_sub_1_1, _a_mask_sub_sub_acc_T_3) node a_mask_sub_sub_4_2 = and(a_mask_sub_sub_sub_2_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_4 = and(a_mask_sub_sub_size, a_mask_sub_sub_4_2) node a_mask_sub_sub_4_1 = or(a_mask_sub_sub_sub_2_1, _a_mask_sub_sub_acc_T_4) node a_mask_sub_sub_5_2 = and(a_mask_sub_sub_sub_2_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_5 = and(a_mask_sub_sub_size, a_mask_sub_sub_5_2) node a_mask_sub_sub_5_1 = or(a_mask_sub_sub_sub_2_1, _a_mask_sub_sub_acc_T_5) node a_mask_sub_sub_6_2 = and(a_mask_sub_sub_sub_3_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_6 = and(a_mask_sub_sub_size, a_mask_sub_sub_6_2) node a_mask_sub_sub_6_1 = or(a_mask_sub_sub_sub_3_1, _a_mask_sub_sub_acc_T_6) node a_mask_sub_sub_7_2 = and(a_mask_sub_sub_sub_3_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_7 = and(a_mask_sub_sub_size, a_mask_sub_sub_7_2) node a_mask_sub_sub_7_1 = or(a_mask_sub_sub_sub_3_1, _a_mask_sub_sub_acc_T_7) node a_mask_sub_size = bits(a_mask_sizeOH, 1, 1) node a_mask_sub_bit = bits(tlb.io.resp.paddr, 1, 1) node a_mask_sub_nbit = eq(a_mask_sub_bit, UInt<1>(0h0)) node a_mask_sub_0_2 = and(a_mask_sub_sub_0_2, a_mask_sub_nbit) node _a_mask_sub_acc_T = and(a_mask_sub_size, a_mask_sub_0_2) node a_mask_sub_0_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T) node a_mask_sub_1_2 = and(a_mask_sub_sub_0_2, a_mask_sub_bit) node _a_mask_sub_acc_T_1 = and(a_mask_sub_size, a_mask_sub_1_2) node a_mask_sub_1_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T_1) node a_mask_sub_2_2 = and(a_mask_sub_sub_1_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_2 = and(a_mask_sub_size, a_mask_sub_2_2) node a_mask_sub_2_1 = or(a_mask_sub_sub_1_1, _a_mask_sub_acc_T_2) node a_mask_sub_3_2 = and(a_mask_sub_sub_1_2, a_mask_sub_bit) node _a_mask_sub_acc_T_3 = and(a_mask_sub_size, a_mask_sub_3_2) node a_mask_sub_3_1 = or(a_mask_sub_sub_1_1, _a_mask_sub_acc_T_3) node a_mask_sub_4_2 = and(a_mask_sub_sub_2_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_4 = and(a_mask_sub_size, a_mask_sub_4_2) node a_mask_sub_4_1 = or(a_mask_sub_sub_2_1, _a_mask_sub_acc_T_4) node a_mask_sub_5_2 = and(a_mask_sub_sub_2_2, a_mask_sub_bit) node _a_mask_sub_acc_T_5 = and(a_mask_sub_size, a_mask_sub_5_2) node a_mask_sub_5_1 = or(a_mask_sub_sub_2_1, _a_mask_sub_acc_T_5) node a_mask_sub_6_2 = and(a_mask_sub_sub_3_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_6 = and(a_mask_sub_size, a_mask_sub_6_2) node a_mask_sub_6_1 = or(a_mask_sub_sub_3_1, _a_mask_sub_acc_T_6) node a_mask_sub_7_2 = and(a_mask_sub_sub_3_2, a_mask_sub_bit) node _a_mask_sub_acc_T_7 = and(a_mask_sub_size, a_mask_sub_7_2) node a_mask_sub_7_1 = or(a_mask_sub_sub_3_1, _a_mask_sub_acc_T_7) node a_mask_sub_8_2 = and(a_mask_sub_sub_4_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_8 = and(a_mask_sub_size, a_mask_sub_8_2) node a_mask_sub_8_1 = or(a_mask_sub_sub_4_1, _a_mask_sub_acc_T_8) node a_mask_sub_9_2 = and(a_mask_sub_sub_4_2, a_mask_sub_bit) node _a_mask_sub_acc_T_9 = and(a_mask_sub_size, a_mask_sub_9_2) node a_mask_sub_9_1 = or(a_mask_sub_sub_4_1, _a_mask_sub_acc_T_9) node a_mask_sub_10_2 = and(a_mask_sub_sub_5_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_10 = and(a_mask_sub_size, a_mask_sub_10_2) node a_mask_sub_10_1 = or(a_mask_sub_sub_5_1, _a_mask_sub_acc_T_10) node a_mask_sub_11_2 = and(a_mask_sub_sub_5_2, a_mask_sub_bit) node _a_mask_sub_acc_T_11 = and(a_mask_sub_size, a_mask_sub_11_2) node a_mask_sub_11_1 = or(a_mask_sub_sub_5_1, _a_mask_sub_acc_T_11) node a_mask_sub_12_2 = and(a_mask_sub_sub_6_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_12 = and(a_mask_sub_size, a_mask_sub_12_2) node a_mask_sub_12_1 = or(a_mask_sub_sub_6_1, _a_mask_sub_acc_T_12) node a_mask_sub_13_2 = and(a_mask_sub_sub_6_2, a_mask_sub_bit) node _a_mask_sub_acc_T_13 = and(a_mask_sub_size, a_mask_sub_13_2) node a_mask_sub_13_1 = or(a_mask_sub_sub_6_1, _a_mask_sub_acc_T_13) node a_mask_sub_14_2 = and(a_mask_sub_sub_7_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_14 = and(a_mask_sub_size, a_mask_sub_14_2) node a_mask_sub_14_1 = or(a_mask_sub_sub_7_1, _a_mask_sub_acc_T_14) node a_mask_sub_15_2 = and(a_mask_sub_sub_7_2, a_mask_sub_bit) node _a_mask_sub_acc_T_15 = and(a_mask_sub_size, a_mask_sub_15_2) node a_mask_sub_15_1 = or(a_mask_sub_sub_7_1, _a_mask_sub_acc_T_15) node a_mask_size = bits(a_mask_sizeOH, 0, 0) node a_mask_bit = bits(tlb.io.resp.paddr, 0, 0) node a_mask_nbit = eq(a_mask_bit, UInt<1>(0h0)) node a_mask_eq = and(a_mask_sub_0_2, a_mask_nbit) node _a_mask_acc_T = and(a_mask_size, a_mask_eq) node a_mask_acc = or(a_mask_sub_0_1, _a_mask_acc_T) node a_mask_eq_1 = and(a_mask_sub_0_2, a_mask_bit) node _a_mask_acc_T_1 = and(a_mask_size, a_mask_eq_1) node a_mask_acc_1 = or(a_mask_sub_0_1, _a_mask_acc_T_1) node a_mask_eq_2 = and(a_mask_sub_1_2, a_mask_nbit) node _a_mask_acc_T_2 = and(a_mask_size, a_mask_eq_2) node a_mask_acc_2 = or(a_mask_sub_1_1, _a_mask_acc_T_2) node a_mask_eq_3 = and(a_mask_sub_1_2, a_mask_bit) node _a_mask_acc_T_3 = and(a_mask_size, a_mask_eq_3) node a_mask_acc_3 = or(a_mask_sub_1_1, _a_mask_acc_T_3) node a_mask_eq_4 = and(a_mask_sub_2_2, a_mask_nbit) node _a_mask_acc_T_4 = and(a_mask_size, a_mask_eq_4) node a_mask_acc_4 = or(a_mask_sub_2_1, _a_mask_acc_T_4) node a_mask_eq_5 = and(a_mask_sub_2_2, a_mask_bit) node _a_mask_acc_T_5 = and(a_mask_size, a_mask_eq_5) node a_mask_acc_5 = or(a_mask_sub_2_1, _a_mask_acc_T_5) node a_mask_eq_6 = and(a_mask_sub_3_2, a_mask_nbit) node _a_mask_acc_T_6 = and(a_mask_size, a_mask_eq_6) node a_mask_acc_6 = or(a_mask_sub_3_1, _a_mask_acc_T_6) node a_mask_eq_7 = and(a_mask_sub_3_2, a_mask_bit) node _a_mask_acc_T_7 = and(a_mask_size, a_mask_eq_7) node a_mask_acc_7 = or(a_mask_sub_3_1, _a_mask_acc_T_7) node a_mask_eq_8 = and(a_mask_sub_4_2, a_mask_nbit) node _a_mask_acc_T_8 = and(a_mask_size, a_mask_eq_8) node a_mask_acc_8 = or(a_mask_sub_4_1, _a_mask_acc_T_8) node a_mask_eq_9 = and(a_mask_sub_4_2, a_mask_bit) node _a_mask_acc_T_9 = and(a_mask_size, a_mask_eq_9) node a_mask_acc_9 = or(a_mask_sub_4_1, _a_mask_acc_T_9) node a_mask_eq_10 = and(a_mask_sub_5_2, a_mask_nbit) node _a_mask_acc_T_10 = and(a_mask_size, a_mask_eq_10) node a_mask_acc_10 = or(a_mask_sub_5_1, _a_mask_acc_T_10) node a_mask_eq_11 = and(a_mask_sub_5_2, a_mask_bit) node _a_mask_acc_T_11 = and(a_mask_size, a_mask_eq_11) node a_mask_acc_11 = or(a_mask_sub_5_1, _a_mask_acc_T_11) node a_mask_eq_12 = and(a_mask_sub_6_2, a_mask_nbit) node _a_mask_acc_T_12 = and(a_mask_size, a_mask_eq_12) node a_mask_acc_12 = or(a_mask_sub_6_1, _a_mask_acc_T_12) node a_mask_eq_13 = and(a_mask_sub_6_2, a_mask_bit) node _a_mask_acc_T_13 = and(a_mask_size, a_mask_eq_13) node a_mask_acc_13 = or(a_mask_sub_6_1, _a_mask_acc_T_13) node a_mask_eq_14 = and(a_mask_sub_7_2, a_mask_nbit) node _a_mask_acc_T_14 = and(a_mask_size, a_mask_eq_14) node a_mask_acc_14 = or(a_mask_sub_7_1, _a_mask_acc_T_14) node a_mask_eq_15 = and(a_mask_sub_7_2, a_mask_bit) node _a_mask_acc_T_15 = and(a_mask_size, a_mask_eq_15) node a_mask_acc_15 = or(a_mask_sub_7_1, _a_mask_acc_T_15) node a_mask_eq_16 = and(a_mask_sub_8_2, a_mask_nbit) node _a_mask_acc_T_16 = and(a_mask_size, a_mask_eq_16) node a_mask_acc_16 = or(a_mask_sub_8_1, _a_mask_acc_T_16) node a_mask_eq_17 = and(a_mask_sub_8_2, a_mask_bit) node _a_mask_acc_T_17 = and(a_mask_size, a_mask_eq_17) node a_mask_acc_17 = or(a_mask_sub_8_1, _a_mask_acc_T_17) node a_mask_eq_18 = and(a_mask_sub_9_2, a_mask_nbit) node _a_mask_acc_T_18 = and(a_mask_size, a_mask_eq_18) node a_mask_acc_18 = or(a_mask_sub_9_1, _a_mask_acc_T_18) node a_mask_eq_19 = and(a_mask_sub_9_2, a_mask_bit) node _a_mask_acc_T_19 = and(a_mask_size, a_mask_eq_19) node a_mask_acc_19 = or(a_mask_sub_9_1, _a_mask_acc_T_19) node a_mask_eq_20 = and(a_mask_sub_10_2, a_mask_nbit) node _a_mask_acc_T_20 = and(a_mask_size, a_mask_eq_20) node a_mask_acc_20 = or(a_mask_sub_10_1, _a_mask_acc_T_20) node a_mask_eq_21 = and(a_mask_sub_10_2, a_mask_bit) node _a_mask_acc_T_21 = and(a_mask_size, a_mask_eq_21) node a_mask_acc_21 = or(a_mask_sub_10_1, _a_mask_acc_T_21) node a_mask_eq_22 = and(a_mask_sub_11_2, a_mask_nbit) node _a_mask_acc_T_22 = and(a_mask_size, a_mask_eq_22) node a_mask_acc_22 = or(a_mask_sub_11_1, _a_mask_acc_T_22) node a_mask_eq_23 = and(a_mask_sub_11_2, a_mask_bit) node _a_mask_acc_T_23 = and(a_mask_size, a_mask_eq_23) node a_mask_acc_23 = or(a_mask_sub_11_1, _a_mask_acc_T_23) node a_mask_eq_24 = and(a_mask_sub_12_2, a_mask_nbit) node _a_mask_acc_T_24 = and(a_mask_size, a_mask_eq_24) node a_mask_acc_24 = or(a_mask_sub_12_1, _a_mask_acc_T_24) node a_mask_eq_25 = and(a_mask_sub_12_2, a_mask_bit) node _a_mask_acc_T_25 = and(a_mask_size, a_mask_eq_25) node a_mask_acc_25 = or(a_mask_sub_12_1, _a_mask_acc_T_25) node a_mask_eq_26 = and(a_mask_sub_13_2, a_mask_nbit) node _a_mask_acc_T_26 = and(a_mask_size, a_mask_eq_26) node a_mask_acc_26 = or(a_mask_sub_13_1, _a_mask_acc_T_26) node a_mask_eq_27 = and(a_mask_sub_13_2, a_mask_bit) node _a_mask_acc_T_27 = and(a_mask_size, a_mask_eq_27) node a_mask_acc_27 = or(a_mask_sub_13_1, _a_mask_acc_T_27) node a_mask_eq_28 = and(a_mask_sub_14_2, a_mask_nbit) node _a_mask_acc_T_28 = and(a_mask_size, a_mask_eq_28) node a_mask_acc_28 = or(a_mask_sub_14_1, _a_mask_acc_T_28) node a_mask_eq_29 = and(a_mask_sub_14_2, a_mask_bit) node _a_mask_acc_T_29 = and(a_mask_size, a_mask_eq_29) node a_mask_acc_29 = or(a_mask_sub_14_1, _a_mask_acc_T_29) node a_mask_eq_30 = and(a_mask_sub_15_2, a_mask_nbit) node _a_mask_acc_T_30 = and(a_mask_size, a_mask_eq_30) node a_mask_acc_30 = or(a_mask_sub_15_1, _a_mask_acc_T_30) node a_mask_eq_31 = and(a_mask_sub_15_2, a_mask_bit) node _a_mask_acc_T_31 = and(a_mask_size, a_mask_eq_31) node a_mask_acc_31 = or(a_mask_sub_15_1, _a_mask_acc_T_31) node a_mask_lo_lo_lo_lo = cat(a_mask_acc_1, a_mask_acc) node a_mask_lo_lo_lo_hi = cat(a_mask_acc_3, a_mask_acc_2) node a_mask_lo_lo_lo = cat(a_mask_lo_lo_lo_hi, a_mask_lo_lo_lo_lo) node a_mask_lo_lo_hi_lo = cat(a_mask_acc_5, a_mask_acc_4) node a_mask_lo_lo_hi_hi = cat(a_mask_acc_7, a_mask_acc_6) node a_mask_lo_lo_hi = cat(a_mask_lo_lo_hi_hi, a_mask_lo_lo_hi_lo) node a_mask_lo_lo = cat(a_mask_lo_lo_hi, a_mask_lo_lo_lo) node a_mask_lo_hi_lo_lo = cat(a_mask_acc_9, a_mask_acc_8) node a_mask_lo_hi_lo_hi = cat(a_mask_acc_11, a_mask_acc_10) node a_mask_lo_hi_lo = cat(a_mask_lo_hi_lo_hi, a_mask_lo_hi_lo_lo) node a_mask_lo_hi_hi_lo = cat(a_mask_acc_13, a_mask_acc_12) node a_mask_lo_hi_hi_hi = cat(a_mask_acc_15, a_mask_acc_14) node a_mask_lo_hi_hi = cat(a_mask_lo_hi_hi_hi, a_mask_lo_hi_hi_lo) node a_mask_lo_hi = cat(a_mask_lo_hi_hi, a_mask_lo_hi_lo) node a_mask_lo = cat(a_mask_lo_hi, a_mask_lo_lo) node a_mask_hi_lo_lo_lo = cat(a_mask_acc_17, a_mask_acc_16) node a_mask_hi_lo_lo_hi = cat(a_mask_acc_19, a_mask_acc_18) node a_mask_hi_lo_lo = cat(a_mask_hi_lo_lo_hi, a_mask_hi_lo_lo_lo) node a_mask_hi_lo_hi_lo = cat(a_mask_acc_21, a_mask_acc_20) node a_mask_hi_lo_hi_hi = cat(a_mask_acc_23, a_mask_acc_22) node a_mask_hi_lo_hi = cat(a_mask_hi_lo_hi_hi, a_mask_hi_lo_hi_lo) node a_mask_hi_lo = cat(a_mask_hi_lo_hi, a_mask_hi_lo_lo) node a_mask_hi_hi_lo_lo = cat(a_mask_acc_25, a_mask_acc_24) node a_mask_hi_hi_lo_hi = cat(a_mask_acc_27, a_mask_acc_26) node a_mask_hi_hi_lo = cat(a_mask_hi_hi_lo_hi, a_mask_hi_hi_lo_lo) node a_mask_hi_hi_hi_lo = cat(a_mask_acc_29, a_mask_acc_28) node a_mask_hi_hi_hi_hi = cat(a_mask_acc_31, a_mask_acc_30) node a_mask_hi_hi_hi = cat(a_mask_hi_hi_hi_hi, a_mask_hi_hi_hi_lo) node a_mask_hi_hi = cat(a_mask_hi_hi_hi, a_mask_hi_hi_lo) node a_mask_hi = cat(a_mask_hi_hi, a_mask_hi_lo) node _a_mask_T = cat(a_mask_hi, a_mask_lo) connect bundle.mask, _a_mask_T invalidate bundle.data connect bundle.corrupt, UInt<1>(0h0) connect request_latency_injection_q.io.enq.bits.corrupt, bundle.corrupt connect request_latency_injection_q.io.enq.bits.data, bundle.data connect request_latency_injection_q.io.enq.bits.mask, bundle.mask connect request_latency_injection_q.io.enq.bits.address, bundle.address connect request_latency_injection_q.io.enq.bits.source, bundle.source connect request_latency_injection_q.io.enq.bits.size, bundle.size connect request_latency_injection_q.io.enq.bits.param, bundle.param connect request_latency_injection_q.io.enq.bits.opcode, bundle.opcode else : node _T_28 = eq(request_input.bits.cmd, UInt<1>(0h1)) when _T_28 : node _T_29 = bits(request_input.bits.addr, 4, 0) node _T_30 = shl(_T_29, 3) node _T_31 = dshl(request_input.bits.data, _T_30) node _legal_T_63 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_64 = leq(request_input.bits.size, UInt<4>(0hc)) node _legal_T_65 = and(_legal_T_63, _legal_T_64) node _legal_T_66 = or(UInt<1>(0h0), _legal_T_65) node _legal_T_67 = xor(tlb.io.resp.paddr, UInt<14>(0h3000)) node _legal_T_68 = cvt(_legal_T_67) node _legal_T_69 = and(_legal_T_68, asSInt(UInt<33>(0h9a113000))) node _legal_T_70 = asSInt(_legal_T_69) node _legal_T_71 = eq(_legal_T_70, asSInt(UInt<1>(0h0))) node _legal_T_72 = and(_legal_T_66, _legal_T_71) node _legal_T_73 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_74 = leq(request_input.bits.size, UInt<3>(0h6)) node _legal_T_75 = and(_legal_T_73, _legal_T_74) node _legal_T_76 = or(UInt<1>(0h0), _legal_T_75) node _legal_T_77 = xor(tlb.io.resp.paddr, UInt<1>(0h0)) node _legal_T_78 = cvt(_legal_T_77) node _legal_T_79 = and(_legal_T_78, asSInt(UInt<33>(0h9a112000))) node _legal_T_80 = asSInt(_legal_T_79) node _legal_T_81 = eq(_legal_T_80, asSInt(UInt<1>(0h0))) node _legal_T_82 = xor(tlb.io.resp.paddr, UInt<21>(0h100000)) node _legal_T_83 = cvt(_legal_T_82) node _legal_T_84 = and(_legal_T_83, asSInt(UInt<33>(0h9a103000))) node _legal_T_85 = asSInt(_legal_T_84) node _legal_T_86 = eq(_legal_T_85, asSInt(UInt<1>(0h0))) node _legal_T_87 = xor(tlb.io.resp.paddr, UInt<26>(0h2000000)) node _legal_T_88 = cvt(_legal_T_87) node _legal_T_89 = and(_legal_T_88, asSInt(UInt<33>(0h9a110000))) node _legal_T_90 = asSInt(_legal_T_89) node _legal_T_91 = eq(_legal_T_90, asSInt(UInt<1>(0h0))) node _legal_T_92 = xor(tlb.io.resp.paddr, UInt<26>(0h2010000)) node _legal_T_93 = cvt(_legal_T_92) node _legal_T_94 = and(_legal_T_93, asSInt(UInt<33>(0h9a113000))) node _legal_T_95 = asSInt(_legal_T_94) node _legal_T_96 = eq(_legal_T_95, asSInt(UInt<1>(0h0))) node _legal_T_97 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_98 = cvt(_legal_T_97) node _legal_T_99 = and(_legal_T_98, asSInt(UInt<33>(0h98000000))) node _legal_T_100 = asSInt(_legal_T_99) node _legal_T_101 = eq(_legal_T_100, asSInt(UInt<1>(0h0))) node _legal_T_102 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_103 = cvt(_legal_T_102) node _legal_T_104 = and(_legal_T_103, asSInt(UInt<33>(0h9a110000))) node _legal_T_105 = asSInt(_legal_T_104) node _legal_T_106 = eq(_legal_T_105, asSInt(UInt<1>(0h0))) node _legal_T_107 = xor(tlb.io.resp.paddr, UInt<29>(0h10000000)) node _legal_T_108 = cvt(_legal_T_107) node _legal_T_109 = and(_legal_T_108, asSInt(UInt<33>(0h9a113000))) node _legal_T_110 = asSInt(_legal_T_109) node _legal_T_111 = eq(_legal_T_110, asSInt(UInt<1>(0h0))) node _legal_T_112 = xor(tlb.io.resp.paddr, UInt<32>(0h80000000)) node _legal_T_113 = cvt(_legal_T_112) node _legal_T_114 = and(_legal_T_113, asSInt(UInt<33>(0h90000000))) node _legal_T_115 = asSInt(_legal_T_114) node _legal_T_116 = eq(_legal_T_115, asSInt(UInt<1>(0h0))) node _legal_T_117 = or(_legal_T_81, _legal_T_86) node _legal_T_118 = or(_legal_T_117, _legal_T_91) node _legal_T_119 = or(_legal_T_118, _legal_T_96) node _legal_T_120 = or(_legal_T_119, _legal_T_101) node _legal_T_121 = or(_legal_T_120, _legal_T_106) node _legal_T_122 = or(_legal_T_121, _legal_T_111) node _legal_T_123 = or(_legal_T_122, _legal_T_116) node _legal_T_124 = and(_legal_T_76, _legal_T_123) node _legal_T_125 = or(UInt<1>(0h0), UInt<1>(0h0)) node _legal_T_126 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_127 = cvt(_legal_T_126) node _legal_T_128 = and(_legal_T_127, asSInt(UInt<33>(0h9a110000))) node _legal_T_129 = asSInt(_legal_T_128) node _legal_T_130 = eq(_legal_T_129, asSInt(UInt<1>(0h0))) node _legal_T_131 = and(_legal_T_125, _legal_T_130) node _legal_T_132 = or(UInt<1>(0h0), _legal_T_72) node _legal_T_133 = or(_legal_T_132, _legal_T_124) node legal_1 = or(_legal_T_133, _legal_T_131) wire bundle_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>} connect bundle_1.opcode, UInt<1>(0h0) connect bundle_1.param, UInt<1>(0h0) connect bundle_1.size, request_input.bits.size connect bundle_1.source, tags_for_issue_Q.io.deq.bits connect bundle_1.address, tlb.io.resp.paddr node _a_mask_sizeOH_T_3 = or(request_input.bits.size, UInt<5>(0h0)) node _a_mask_sizeOH_shiftAmount_T_1 = pad(_a_mask_sizeOH_T_3, 3) node a_mask_sizeOH_shiftAmount_1 = bits(_a_mask_sizeOH_shiftAmount_T_1, 2, 0) node _a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount_1) node _a_mask_sizeOH_T_5 = bits(_a_mask_sizeOH_T_4, 4, 0) node a_mask_sizeOH_1 = or(_a_mask_sizeOH_T_5, UInt<1>(0h1)) node a_mask_sub_sub_sub_sub_sub_0_1_1 = geq(request_input.bits.size, UInt<3>(0h5)) node a_mask_sub_sub_sub_sub_size_1 = bits(a_mask_sizeOH_1, 4, 4) node a_mask_sub_sub_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 4, 4) node a_mask_sub_sub_sub_sub_nbit_1 = eq(a_mask_sub_sub_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_sub_acc_T_2 = and(a_mask_sub_sub_sub_sub_size_1, a_mask_sub_sub_sub_sub_0_2_1) node a_mask_sub_sub_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_sub_acc_T_2) node a_mask_sub_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_sub_acc_T_3 = and(a_mask_sub_sub_sub_sub_size_1, a_mask_sub_sub_sub_sub_1_2_1) node a_mask_sub_sub_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_sub_acc_T_3) node a_mask_sub_sub_sub_size_1 = bits(a_mask_sizeOH_1, 3, 3) node a_mask_sub_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 3, 3) node a_mask_sub_sub_sub_nbit_1 = eq(a_mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_sub_0_2_1 = and(a_mask_sub_sub_sub_sub_0_2_1, a_mask_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_acc_T_4 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_0_2_1) node a_mask_sub_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_acc_T_4) node a_mask_sub_sub_sub_1_2_1 = and(a_mask_sub_sub_sub_sub_0_2_1, a_mask_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_acc_T_5 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_1_2_1) node a_mask_sub_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_acc_T_5) node a_mask_sub_sub_sub_2_2_1 = and(a_mask_sub_sub_sub_sub_1_2_1, a_mask_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_acc_T_6 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_2_2_1) node a_mask_sub_sub_sub_2_1_1 = or(a_mask_sub_sub_sub_sub_1_1_1, _a_mask_sub_sub_sub_acc_T_6) node a_mask_sub_sub_sub_3_2_1 = and(a_mask_sub_sub_sub_sub_1_2_1, a_mask_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_acc_T_7 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_3_2_1) node a_mask_sub_sub_sub_3_1_1 = or(a_mask_sub_sub_sub_sub_1_1_1, _a_mask_sub_sub_sub_acc_T_7) node a_mask_sub_sub_size_1 = bits(a_mask_sizeOH_1, 2, 2) node a_mask_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 2, 2) node a_mask_sub_sub_nbit_1 = eq(a_mask_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_0_2_1 = and(a_mask_sub_sub_sub_0_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_8 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_0_2_1) node a_mask_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_0_1_1, _a_mask_sub_sub_acc_T_8) node a_mask_sub_sub_1_2_1 = and(a_mask_sub_sub_sub_0_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_9 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_1_2_1) node a_mask_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_0_1_1, _a_mask_sub_sub_acc_T_9) node a_mask_sub_sub_2_2_1 = and(a_mask_sub_sub_sub_1_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_10 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_2_2_1) node a_mask_sub_sub_2_1_1 = or(a_mask_sub_sub_sub_1_1_1, _a_mask_sub_sub_acc_T_10) node a_mask_sub_sub_3_2_1 = and(a_mask_sub_sub_sub_1_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_11 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_3_2_1) node a_mask_sub_sub_3_1_1 = or(a_mask_sub_sub_sub_1_1_1, _a_mask_sub_sub_acc_T_11) node a_mask_sub_sub_4_2_1 = and(a_mask_sub_sub_sub_2_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_12 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_4_2_1) node a_mask_sub_sub_4_1_1 = or(a_mask_sub_sub_sub_2_1_1, _a_mask_sub_sub_acc_T_12) node a_mask_sub_sub_5_2_1 = and(a_mask_sub_sub_sub_2_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_13 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_5_2_1) node a_mask_sub_sub_5_1_1 = or(a_mask_sub_sub_sub_2_1_1, _a_mask_sub_sub_acc_T_13) node a_mask_sub_sub_6_2_1 = and(a_mask_sub_sub_sub_3_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_14 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_6_2_1) node a_mask_sub_sub_6_1_1 = or(a_mask_sub_sub_sub_3_1_1, _a_mask_sub_sub_acc_T_14) node a_mask_sub_sub_7_2_1 = and(a_mask_sub_sub_sub_3_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_15 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_7_2_1) node a_mask_sub_sub_7_1_1 = or(a_mask_sub_sub_sub_3_1_1, _a_mask_sub_sub_acc_T_15) node a_mask_sub_size_1 = bits(a_mask_sizeOH_1, 1, 1) node a_mask_sub_bit_1 = bits(tlb.io.resp.paddr, 1, 1) node a_mask_sub_nbit_1 = eq(a_mask_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_0_2_1 = and(a_mask_sub_sub_0_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_16 = and(a_mask_sub_size_1, a_mask_sub_0_2_1) node a_mask_sub_0_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_16) node a_mask_sub_1_2_1 = and(a_mask_sub_sub_0_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_17 = and(a_mask_sub_size_1, a_mask_sub_1_2_1) node a_mask_sub_1_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_17) node a_mask_sub_2_2_1 = and(a_mask_sub_sub_1_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_18 = and(a_mask_sub_size_1, a_mask_sub_2_2_1) node a_mask_sub_2_1_1 = or(a_mask_sub_sub_1_1_1, _a_mask_sub_acc_T_18) node a_mask_sub_3_2_1 = and(a_mask_sub_sub_1_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_19 = and(a_mask_sub_size_1, a_mask_sub_3_2_1) node a_mask_sub_3_1_1 = or(a_mask_sub_sub_1_1_1, _a_mask_sub_acc_T_19) node a_mask_sub_4_2_1 = and(a_mask_sub_sub_2_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_20 = and(a_mask_sub_size_1, a_mask_sub_4_2_1) node a_mask_sub_4_1_1 = or(a_mask_sub_sub_2_1_1, _a_mask_sub_acc_T_20) node a_mask_sub_5_2_1 = and(a_mask_sub_sub_2_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_21 = and(a_mask_sub_size_1, a_mask_sub_5_2_1) node a_mask_sub_5_1_1 = or(a_mask_sub_sub_2_1_1, _a_mask_sub_acc_T_21) node a_mask_sub_6_2_1 = and(a_mask_sub_sub_3_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_22 = and(a_mask_sub_size_1, a_mask_sub_6_2_1) node a_mask_sub_6_1_1 = or(a_mask_sub_sub_3_1_1, _a_mask_sub_acc_T_22) node a_mask_sub_7_2_1 = and(a_mask_sub_sub_3_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_23 = and(a_mask_sub_size_1, a_mask_sub_7_2_1) node a_mask_sub_7_1_1 = or(a_mask_sub_sub_3_1_1, _a_mask_sub_acc_T_23) node a_mask_sub_8_2_1 = and(a_mask_sub_sub_4_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_24 = and(a_mask_sub_size_1, a_mask_sub_8_2_1) node a_mask_sub_8_1_1 = or(a_mask_sub_sub_4_1_1, _a_mask_sub_acc_T_24) node a_mask_sub_9_2_1 = and(a_mask_sub_sub_4_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_25 = and(a_mask_sub_size_1, a_mask_sub_9_2_1) node a_mask_sub_9_1_1 = or(a_mask_sub_sub_4_1_1, _a_mask_sub_acc_T_25) node a_mask_sub_10_2_1 = and(a_mask_sub_sub_5_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_26 = and(a_mask_sub_size_1, a_mask_sub_10_2_1) node a_mask_sub_10_1_1 = or(a_mask_sub_sub_5_1_1, _a_mask_sub_acc_T_26) node a_mask_sub_11_2_1 = and(a_mask_sub_sub_5_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_27 = and(a_mask_sub_size_1, a_mask_sub_11_2_1) node a_mask_sub_11_1_1 = or(a_mask_sub_sub_5_1_1, _a_mask_sub_acc_T_27) node a_mask_sub_12_2_1 = and(a_mask_sub_sub_6_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_28 = and(a_mask_sub_size_1, a_mask_sub_12_2_1) node a_mask_sub_12_1_1 = or(a_mask_sub_sub_6_1_1, _a_mask_sub_acc_T_28) node a_mask_sub_13_2_1 = and(a_mask_sub_sub_6_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_29 = and(a_mask_sub_size_1, a_mask_sub_13_2_1) node a_mask_sub_13_1_1 = or(a_mask_sub_sub_6_1_1, _a_mask_sub_acc_T_29) node a_mask_sub_14_2_1 = and(a_mask_sub_sub_7_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_30 = and(a_mask_sub_size_1, a_mask_sub_14_2_1) node a_mask_sub_14_1_1 = or(a_mask_sub_sub_7_1_1, _a_mask_sub_acc_T_30) node a_mask_sub_15_2_1 = and(a_mask_sub_sub_7_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_31 = and(a_mask_sub_size_1, a_mask_sub_15_2_1) node a_mask_sub_15_1_1 = or(a_mask_sub_sub_7_1_1, _a_mask_sub_acc_T_31) node a_mask_size_1 = bits(a_mask_sizeOH_1, 0, 0) node a_mask_bit_1 = bits(tlb.io.resp.paddr, 0, 0) node a_mask_nbit_1 = eq(a_mask_bit_1, UInt<1>(0h0)) node a_mask_eq_32 = and(a_mask_sub_0_2_1, a_mask_nbit_1) node _a_mask_acc_T_32 = and(a_mask_size_1, a_mask_eq_32) node a_mask_acc_32 = or(a_mask_sub_0_1_1, _a_mask_acc_T_32) node a_mask_eq_33 = and(a_mask_sub_0_2_1, a_mask_bit_1) node _a_mask_acc_T_33 = and(a_mask_size_1, a_mask_eq_33) node a_mask_acc_33 = or(a_mask_sub_0_1_1, _a_mask_acc_T_33) node a_mask_eq_34 = and(a_mask_sub_1_2_1, a_mask_nbit_1) node _a_mask_acc_T_34 = and(a_mask_size_1, a_mask_eq_34) node a_mask_acc_34 = or(a_mask_sub_1_1_1, _a_mask_acc_T_34) node a_mask_eq_35 = and(a_mask_sub_1_2_1, a_mask_bit_1) node _a_mask_acc_T_35 = and(a_mask_size_1, a_mask_eq_35) node a_mask_acc_35 = or(a_mask_sub_1_1_1, _a_mask_acc_T_35) node a_mask_eq_36 = and(a_mask_sub_2_2_1, a_mask_nbit_1) node _a_mask_acc_T_36 = and(a_mask_size_1, a_mask_eq_36) node a_mask_acc_36 = or(a_mask_sub_2_1_1, _a_mask_acc_T_36) node a_mask_eq_37 = and(a_mask_sub_2_2_1, a_mask_bit_1) node _a_mask_acc_T_37 = and(a_mask_size_1, a_mask_eq_37) node a_mask_acc_37 = or(a_mask_sub_2_1_1, _a_mask_acc_T_37) node a_mask_eq_38 = and(a_mask_sub_3_2_1, a_mask_nbit_1) node _a_mask_acc_T_38 = and(a_mask_size_1, a_mask_eq_38) node a_mask_acc_38 = or(a_mask_sub_3_1_1, _a_mask_acc_T_38) node a_mask_eq_39 = and(a_mask_sub_3_2_1, a_mask_bit_1) node _a_mask_acc_T_39 = and(a_mask_size_1, a_mask_eq_39) node a_mask_acc_39 = or(a_mask_sub_3_1_1, _a_mask_acc_T_39) node a_mask_eq_40 = and(a_mask_sub_4_2_1, a_mask_nbit_1) node _a_mask_acc_T_40 = and(a_mask_size_1, a_mask_eq_40) node a_mask_acc_40 = or(a_mask_sub_4_1_1, _a_mask_acc_T_40) node a_mask_eq_41 = and(a_mask_sub_4_2_1, a_mask_bit_1) node _a_mask_acc_T_41 = and(a_mask_size_1, a_mask_eq_41) node a_mask_acc_41 = or(a_mask_sub_4_1_1, _a_mask_acc_T_41) node a_mask_eq_42 = and(a_mask_sub_5_2_1, a_mask_nbit_1) node _a_mask_acc_T_42 = and(a_mask_size_1, a_mask_eq_42) node a_mask_acc_42 = or(a_mask_sub_5_1_1, _a_mask_acc_T_42) node a_mask_eq_43 = and(a_mask_sub_5_2_1, a_mask_bit_1) node _a_mask_acc_T_43 = and(a_mask_size_1, a_mask_eq_43) node a_mask_acc_43 = or(a_mask_sub_5_1_1, _a_mask_acc_T_43) node a_mask_eq_44 = and(a_mask_sub_6_2_1, a_mask_nbit_1) node _a_mask_acc_T_44 = and(a_mask_size_1, a_mask_eq_44) node a_mask_acc_44 = or(a_mask_sub_6_1_1, _a_mask_acc_T_44) node a_mask_eq_45 = and(a_mask_sub_6_2_1, a_mask_bit_1) node _a_mask_acc_T_45 = and(a_mask_size_1, a_mask_eq_45) node a_mask_acc_45 = or(a_mask_sub_6_1_1, _a_mask_acc_T_45) node a_mask_eq_46 = and(a_mask_sub_7_2_1, a_mask_nbit_1) node _a_mask_acc_T_46 = and(a_mask_size_1, a_mask_eq_46) node a_mask_acc_46 = or(a_mask_sub_7_1_1, _a_mask_acc_T_46) node a_mask_eq_47 = and(a_mask_sub_7_2_1, a_mask_bit_1) node _a_mask_acc_T_47 = and(a_mask_size_1, a_mask_eq_47) node a_mask_acc_47 = or(a_mask_sub_7_1_1, _a_mask_acc_T_47) node a_mask_eq_48 = and(a_mask_sub_8_2_1, a_mask_nbit_1) node _a_mask_acc_T_48 = and(a_mask_size_1, a_mask_eq_48) node a_mask_acc_48 = or(a_mask_sub_8_1_1, _a_mask_acc_T_48) node a_mask_eq_49 = and(a_mask_sub_8_2_1, a_mask_bit_1) node _a_mask_acc_T_49 = and(a_mask_size_1, a_mask_eq_49) node a_mask_acc_49 = or(a_mask_sub_8_1_1, _a_mask_acc_T_49) node a_mask_eq_50 = and(a_mask_sub_9_2_1, a_mask_nbit_1) node _a_mask_acc_T_50 = and(a_mask_size_1, a_mask_eq_50) node a_mask_acc_50 = or(a_mask_sub_9_1_1, _a_mask_acc_T_50) node a_mask_eq_51 = and(a_mask_sub_9_2_1, a_mask_bit_1) node _a_mask_acc_T_51 = and(a_mask_size_1, a_mask_eq_51) node a_mask_acc_51 = or(a_mask_sub_9_1_1, _a_mask_acc_T_51) node a_mask_eq_52 = and(a_mask_sub_10_2_1, a_mask_nbit_1) node _a_mask_acc_T_52 = and(a_mask_size_1, a_mask_eq_52) node a_mask_acc_52 = or(a_mask_sub_10_1_1, _a_mask_acc_T_52) node a_mask_eq_53 = and(a_mask_sub_10_2_1, a_mask_bit_1) node _a_mask_acc_T_53 = and(a_mask_size_1, a_mask_eq_53) node a_mask_acc_53 = or(a_mask_sub_10_1_1, _a_mask_acc_T_53) node a_mask_eq_54 = and(a_mask_sub_11_2_1, a_mask_nbit_1) node _a_mask_acc_T_54 = and(a_mask_size_1, a_mask_eq_54) node a_mask_acc_54 = or(a_mask_sub_11_1_1, _a_mask_acc_T_54) node a_mask_eq_55 = and(a_mask_sub_11_2_1, a_mask_bit_1) node _a_mask_acc_T_55 = and(a_mask_size_1, a_mask_eq_55) node a_mask_acc_55 = or(a_mask_sub_11_1_1, _a_mask_acc_T_55) node a_mask_eq_56 = and(a_mask_sub_12_2_1, a_mask_nbit_1) node _a_mask_acc_T_56 = and(a_mask_size_1, a_mask_eq_56) node a_mask_acc_56 = or(a_mask_sub_12_1_1, _a_mask_acc_T_56) node a_mask_eq_57 = and(a_mask_sub_12_2_1, a_mask_bit_1) node _a_mask_acc_T_57 = and(a_mask_size_1, a_mask_eq_57) node a_mask_acc_57 = or(a_mask_sub_12_1_1, _a_mask_acc_T_57) node a_mask_eq_58 = and(a_mask_sub_13_2_1, a_mask_nbit_1) node _a_mask_acc_T_58 = and(a_mask_size_1, a_mask_eq_58) node a_mask_acc_58 = or(a_mask_sub_13_1_1, _a_mask_acc_T_58) node a_mask_eq_59 = and(a_mask_sub_13_2_1, a_mask_bit_1) node _a_mask_acc_T_59 = and(a_mask_size_1, a_mask_eq_59) node a_mask_acc_59 = or(a_mask_sub_13_1_1, _a_mask_acc_T_59) node a_mask_eq_60 = and(a_mask_sub_14_2_1, a_mask_nbit_1) node _a_mask_acc_T_60 = and(a_mask_size_1, a_mask_eq_60) node a_mask_acc_60 = or(a_mask_sub_14_1_1, _a_mask_acc_T_60) node a_mask_eq_61 = and(a_mask_sub_14_2_1, a_mask_bit_1) node _a_mask_acc_T_61 = and(a_mask_size_1, a_mask_eq_61) node a_mask_acc_61 = or(a_mask_sub_14_1_1, _a_mask_acc_T_61) node a_mask_eq_62 = and(a_mask_sub_15_2_1, a_mask_nbit_1) node _a_mask_acc_T_62 = and(a_mask_size_1, a_mask_eq_62) node a_mask_acc_62 = or(a_mask_sub_15_1_1, _a_mask_acc_T_62) node a_mask_eq_63 = and(a_mask_sub_15_2_1, a_mask_bit_1) node _a_mask_acc_T_63 = and(a_mask_size_1, a_mask_eq_63) node a_mask_acc_63 = or(a_mask_sub_15_1_1, _a_mask_acc_T_63) node a_mask_lo_lo_lo_lo_1 = cat(a_mask_acc_33, a_mask_acc_32) node a_mask_lo_lo_lo_hi_1 = cat(a_mask_acc_35, a_mask_acc_34) node a_mask_lo_lo_lo_1 = cat(a_mask_lo_lo_lo_hi_1, a_mask_lo_lo_lo_lo_1) node a_mask_lo_lo_hi_lo_1 = cat(a_mask_acc_37, a_mask_acc_36) node a_mask_lo_lo_hi_hi_1 = cat(a_mask_acc_39, a_mask_acc_38) node a_mask_lo_lo_hi_1 = cat(a_mask_lo_lo_hi_hi_1, a_mask_lo_lo_hi_lo_1) node a_mask_lo_lo_1 = cat(a_mask_lo_lo_hi_1, a_mask_lo_lo_lo_1) node a_mask_lo_hi_lo_lo_1 = cat(a_mask_acc_41, a_mask_acc_40) node a_mask_lo_hi_lo_hi_1 = cat(a_mask_acc_43, a_mask_acc_42) node a_mask_lo_hi_lo_1 = cat(a_mask_lo_hi_lo_hi_1, a_mask_lo_hi_lo_lo_1) node a_mask_lo_hi_hi_lo_1 = cat(a_mask_acc_45, a_mask_acc_44) node a_mask_lo_hi_hi_hi_1 = cat(a_mask_acc_47, a_mask_acc_46) node a_mask_lo_hi_hi_1 = cat(a_mask_lo_hi_hi_hi_1, a_mask_lo_hi_hi_lo_1) node a_mask_lo_hi_1 = cat(a_mask_lo_hi_hi_1, a_mask_lo_hi_lo_1) node a_mask_lo_1 = cat(a_mask_lo_hi_1, a_mask_lo_lo_1) node a_mask_hi_lo_lo_lo_1 = cat(a_mask_acc_49, a_mask_acc_48) node a_mask_hi_lo_lo_hi_1 = cat(a_mask_acc_51, a_mask_acc_50) node a_mask_hi_lo_lo_1 = cat(a_mask_hi_lo_lo_hi_1, a_mask_hi_lo_lo_lo_1) node a_mask_hi_lo_hi_lo_1 = cat(a_mask_acc_53, a_mask_acc_52) node a_mask_hi_lo_hi_hi_1 = cat(a_mask_acc_55, a_mask_acc_54) node a_mask_hi_lo_hi_1 = cat(a_mask_hi_lo_hi_hi_1, a_mask_hi_lo_hi_lo_1) node a_mask_hi_lo_1 = cat(a_mask_hi_lo_hi_1, a_mask_hi_lo_lo_1) node a_mask_hi_hi_lo_lo_1 = cat(a_mask_acc_57, a_mask_acc_56) node a_mask_hi_hi_lo_hi_1 = cat(a_mask_acc_59, a_mask_acc_58) node a_mask_hi_hi_lo_1 = cat(a_mask_hi_hi_lo_hi_1, a_mask_hi_hi_lo_lo_1) node a_mask_hi_hi_hi_lo_1 = cat(a_mask_acc_61, a_mask_acc_60) node a_mask_hi_hi_hi_hi_1 = cat(a_mask_acc_63, a_mask_acc_62) node a_mask_hi_hi_hi_1 = cat(a_mask_hi_hi_hi_hi_1, a_mask_hi_hi_hi_lo_1) node a_mask_hi_hi_1 = cat(a_mask_hi_hi_hi_1, a_mask_hi_hi_lo_1) node a_mask_hi_1 = cat(a_mask_hi_hi_1, a_mask_hi_lo_1) node _a_mask_T_1 = cat(a_mask_hi_1, a_mask_lo_1) connect bundle_1.mask, _a_mask_T_1 connect bundle_1.data, _T_31 connect bundle_1.corrupt, UInt<1>(0h0) connect request_latency_injection_q.io.enq.bits.corrupt, bundle_1.corrupt connect request_latency_injection_q.io.enq.bits.data, bundle_1.data connect request_latency_injection_q.io.enq.bits.mask, bundle_1.mask connect request_latency_injection_q.io.enq.bits.address, bundle_1.address connect request_latency_injection_q.io.enq.bits.source, bundle_1.source connect request_latency_injection_q.io.enq.bits.size, bundle_1.size connect request_latency_injection_q.io.enq.bits.param, bundle_1.param connect request_latency_injection_q.io.enq.bits.opcode, bundle_1.opcode else : when request_input.valid : regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_10 node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : printf(clock, UInt<1>(0h1), "[fhdr_writer] ERR") : printf_11 node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed: ERR\n at L2MemHelperLatencyInjection.scala:178 assert(false.B, \"ERR\")\n") : printf_12 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_2 inst Queue4_L2RespInternal of Queue4_L2RespInternal connect Queue4_L2RespInternal.clock, clock connect Queue4_L2RespInternal.reset, reset inst Queue4_L2RespInternal_1 of Queue4_L2RespInternal_1 connect Queue4_L2RespInternal_1.clock, clock connect Queue4_L2RespInternal_1.reset, reset inst Queue4_L2RespInternal_2 of Queue4_L2RespInternal_2 connect Queue4_L2RespInternal_2.clock, clock connect Queue4_L2RespInternal_2.reset, reset inst Queue4_L2RespInternal_3 of Queue4_L2RespInternal_3 connect Queue4_L2RespInternal_3.clock, clock connect Queue4_L2RespInternal_3.reset, reset node _current_request_tag_has_response_space_T = eq(UInt<1>(0h0), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_1 = and(Queue4_L2RespInternal.io.enq.ready, _current_request_tag_has_response_space_T) node _current_request_tag_has_response_space_T_2 = eq(UInt<1>(0h1), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_3 = and(Queue4_L2RespInternal_1.io.enq.ready, _current_request_tag_has_response_space_T_2) node _current_request_tag_has_response_space_T_4 = eq(UInt<2>(0h2), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_5 = and(Queue4_L2RespInternal_2.io.enq.ready, _current_request_tag_has_response_space_T_4) node _current_request_tag_has_response_space_T_6 = eq(UInt<2>(0h3), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_7 = and(Queue4_L2RespInternal_3.io.enq.ready, _current_request_tag_has_response_space_T_6) node _current_request_tag_has_response_space_T_8 = or(_current_request_tag_has_response_space_T_1, _current_request_tag_has_response_space_T_3) node _current_request_tag_has_response_space_T_9 = or(_current_request_tag_has_response_space_T_8, _current_request_tag_has_response_space_T_5) node current_request_tag_has_response_space = or(_current_request_tag_has_response_space_T_9, _current_request_tag_has_response_space_T_7) node _outstanding_req_addr_io_enq_bits_addrindex_T = and(request_input.bits.addr, UInt<5>(0h1f)) connect outstanding_req_addr.io.enq.bits.addrindex, _outstanding_req_addr_io_enq_bits_addrindex_T connect outstanding_req_addr.io.enq.bits.tag, tags_for_issue_Q.io.deq.bits node _request_latency_injection_q_io_enq_valid_T = and(request_input.valid, tlb_ready) node _request_latency_injection_q_io_enq_valid_T_1 = and(_request_latency_injection_q_io_enq_valid_T, outstanding_req_addr.io.enq.ready) node _request_latency_injection_q_io_enq_valid_T_2 = and(_request_latency_injection_q_io_enq_valid_T_1, free_outstanding_op_slots) node _request_latency_injection_q_io_enq_valid_T_3 = and(_request_latency_injection_q_io_enq_valid_T_2, tags_for_issue_Q.io.deq.valid) node _request_latency_injection_q_io_enq_valid_T_4 = and(_request_latency_injection_q_io_enq_valid_T_3, current_request_tag_has_response_space) connect request_latency_injection_q.io.enq.valid, _request_latency_injection_q_io_enq_valid_T_4 node _request_input_ready_T = and(request_latency_injection_q.io.enq.ready, tlb_ready) node _request_input_ready_T_1 = and(_request_input_ready_T, outstanding_req_addr.io.enq.ready) node _request_input_ready_T_2 = and(_request_input_ready_T_1, free_outstanding_op_slots) node _request_input_ready_T_3 = and(_request_input_ready_T_2, tags_for_issue_Q.io.deq.valid) node _request_input_ready_T_4 = and(_request_input_ready_T_3, current_request_tag_has_response_space) connect request_input.ready, _request_input_ready_T_4 node _outstanding_req_addr_io_enq_valid_T = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _outstanding_req_addr_io_enq_valid_T_1 = and(_outstanding_req_addr_io_enq_valid_T, tlb_ready) node _outstanding_req_addr_io_enq_valid_T_2 = and(_outstanding_req_addr_io_enq_valid_T_1, free_outstanding_op_slots) node _outstanding_req_addr_io_enq_valid_T_3 = and(_outstanding_req_addr_io_enq_valid_T_2, tags_for_issue_Q.io.deq.valid) node _outstanding_req_addr_io_enq_valid_T_4 = and(_outstanding_req_addr_io_enq_valid_T_3, current_request_tag_has_response_space) connect outstanding_req_addr.io.enq.valid, _outstanding_req_addr_io_enq_valid_T_4 node _tags_for_issue_Q_io_deq_ready_T = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _tags_for_issue_Q_io_deq_ready_T_1 = and(_tags_for_issue_Q_io_deq_ready_T, tlb_ready) node _tags_for_issue_Q_io_deq_ready_T_2 = and(_tags_for_issue_Q_io_deq_ready_T_1, outstanding_req_addr.io.enq.ready) node _tags_for_issue_Q_io_deq_ready_T_3 = and(_tags_for_issue_Q_io_deq_ready_T_2, free_outstanding_op_slots) node _tags_for_issue_Q_io_deq_ready_T_4 = and(_tags_for_issue_Q_io_deq_ready_T_3, current_request_tag_has_response_space) connect tags_for_issue_Q.io.deq.ready, _tags_for_issue_Q_io_deq_ready_T_4 connect masterNodeOut.a.bits, request_latency_injection_q.io.deq.bits connect masterNodeOut.a.valid, request_latency_injection_q.io.deq.valid connect request_latency_injection_q.io.deq.ready, masterNodeOut.a.ready node _T_39 = and(masterNodeOut.a.ready, masterNodeOut.a.valid) when _T_39 : node _T_40 = eq(request_input.bits.cmd, UInt<1>(0h0)) when _T_40 : regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_13 node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : printf(clock, UInt<1>(0h1), "[fhdr_writer] L2IF: req(read) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, global_memop_sent, tags_for_issue_Q.io.deq.bits) : printf_14 node _T_45 = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _T_46 = and(_T_45, tlb_ready) node _T_47 = and(_T_46, outstanding_req_addr.io.enq.ready) node _T_48 = and(_T_47, free_outstanding_op_slots) node _T_49 = and(_T_48, tags_for_issue_Q.io.deq.valid) node _T_50 = and(_T_49, current_request_tag_has_response_space) when _T_50 : node _T_51 = eq(request_input.bits.cmd, UInt<1>(0h1)) when _T_51 : regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _printf_T = asUInt(reset) node _printf_T_1 = eq(_printf_T, UInt<1>(0h0)) when _printf_T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_15 node _T_52 = asUInt(reset) node _T_53 = eq(_T_52, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "") : printf_16 node _printf_T_2 = asUInt(reset) node _printf_T_3 = eq(_printf_T_2, UInt<1>(0h0)) when _printf_T_3 : printf(clock, UInt<1>(0h1), "[fhdr_writer] L2IF: req(write) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, data: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, request_input.bits.data, global_memop_sent, tags_for_issue_Q.io.deq.bits) : printf_17 node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "") : printf_18 node _T_56 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_57 = lt(UInt<1>(0h0), _T_56) when _T_57 : node _T_58 = add(request_input.bits.addr, UInt<1>(0h0)) node _T_59 = tail(_T_58, 1) node _T_60 = dshr(request_input.bits.data, UInt<1>(0h0)) node _T_61 = bits(_T_60, 7, 0) regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_19 node _T_64 = asUInt(reset) node _T_65 = eq(_T_64, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_59, _T_61) : printf_20 node _T_66 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_67 = lt(UInt<1>(0h1), _T_66) when _T_67 : node _T_68 = add(request_input.bits.addr, UInt<1>(0h1)) node _T_69 = tail(_T_68, 1) node _T_70 = dshr(request_input.bits.data, UInt<4>(0h8)) node _T_71 = bits(_T_70, 7, 0) regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_21 node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_69, _T_71) : printf_22 node _T_76 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_77 = lt(UInt<2>(0h2), _T_76) when _T_77 : node _T_78 = add(request_input.bits.addr, UInt<2>(0h2)) node _T_79 = tail(_T_78, 1) node _T_80 = dshr(request_input.bits.data, UInt<5>(0h10)) node _T_81 = bits(_T_80, 7, 0) regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_23 node _T_84 = asUInt(reset) node _T_85 = eq(_T_84, UInt<1>(0h0)) when _T_85 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_79, _T_81) : printf_24 node _T_86 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_87 = lt(UInt<2>(0h3), _T_86) when _T_87 : node _T_88 = add(request_input.bits.addr, UInt<2>(0h3)) node _T_89 = tail(_T_88, 1) node _T_90 = dshr(request_input.bits.data, UInt<5>(0h18)) node _T_91 = bits(_T_90, 7, 0) regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_92 = asUInt(reset) node _T_93 = eq(_T_92, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_25 node _T_94 = asUInt(reset) node _T_95 = eq(_T_94, UInt<1>(0h0)) when _T_95 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_89, _T_91) : printf_26 node _T_96 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_97 = lt(UInt<3>(0h4), _T_96) when _T_97 : node _T_98 = add(request_input.bits.addr, UInt<3>(0h4)) node _T_99 = tail(_T_98, 1) node _T_100 = dshr(request_input.bits.data, UInt<6>(0h20)) node _T_101 = bits(_T_100, 7, 0) regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1)) node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1) connect loginfo_cycles_11, _loginfo_cycles_T_23 node _T_102 = asUInt(reset) node _T_103 = eq(_T_102, UInt<1>(0h0)) when _T_103 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_27 node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_99, _T_101) : printf_28 node _T_106 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_107 = lt(UInt<3>(0h5), _T_106) when _T_107 : node _T_108 = add(request_input.bits.addr, UInt<3>(0h5)) node _T_109 = tail(_T_108, 1) node _T_110 = dshr(request_input.bits.data, UInt<6>(0h28)) node _T_111 = bits(_T_110, 7, 0) regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1)) node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1) connect loginfo_cycles_12, _loginfo_cycles_T_25 node _T_112 = asUInt(reset) node _T_113 = eq(_T_112, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_29 node _T_114 = asUInt(reset) node _T_115 = eq(_T_114, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_109, _T_111) : printf_30 node _T_116 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_117 = lt(UInt<3>(0h6), _T_116) when _T_117 : node _T_118 = add(request_input.bits.addr, UInt<3>(0h6)) node _T_119 = tail(_T_118, 1) node _T_120 = dshr(request_input.bits.data, UInt<6>(0h30)) node _T_121 = bits(_T_120, 7, 0) regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1)) node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1) connect loginfo_cycles_13, _loginfo_cycles_T_27 node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_31 node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_119, _T_121) : printf_32 node _T_126 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_127 = lt(UInt<3>(0h7), _T_126) when _T_127 : node _T_128 = add(request_input.bits.addr, UInt<3>(0h7)) node _T_129 = tail(_T_128, 1) node _T_130 = dshr(request_input.bits.data, UInt<6>(0h38)) node _T_131 = bits(_T_130, 7, 0) regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1)) node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1) connect loginfo_cycles_14, _loginfo_cycles_T_29 node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_33 node _T_134 = asUInt(reset) node _T_135 = eq(_T_134, UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_129, _T_131) : printf_34 node _T_136 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_137 = lt(UInt<4>(0h8), _T_136) when _T_137 : node _T_138 = add(request_input.bits.addr, UInt<4>(0h8)) node _T_139 = tail(_T_138, 1) node _T_140 = dshr(request_input.bits.data, UInt<7>(0h40)) node _T_141 = bits(_T_140, 7, 0) regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1)) node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1) connect loginfo_cycles_15, _loginfo_cycles_T_31 node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_35 node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_139, _T_141) : printf_36 node _T_146 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_147 = lt(UInt<4>(0h9), _T_146) when _T_147 : node _T_148 = add(request_input.bits.addr, UInt<4>(0h9)) node _T_149 = tail(_T_148, 1) node _T_150 = dshr(request_input.bits.data, UInt<7>(0h48)) node _T_151 = bits(_T_150, 7, 0) regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1)) node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1) connect loginfo_cycles_16, _loginfo_cycles_T_33 node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_37 node _T_154 = asUInt(reset) node _T_155 = eq(_T_154, UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_149, _T_151) : printf_38 node _T_156 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_157 = lt(UInt<4>(0ha), _T_156) when _T_157 : node _T_158 = add(request_input.bits.addr, UInt<4>(0ha)) node _T_159 = tail(_T_158, 1) node _T_160 = dshr(request_input.bits.data, UInt<7>(0h50)) node _T_161 = bits(_T_160, 7, 0) regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1)) node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1) connect loginfo_cycles_17, _loginfo_cycles_T_35 node _T_162 = asUInt(reset) node _T_163 = eq(_T_162, UInt<1>(0h0)) when _T_163 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_39 node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_159, _T_161) : printf_40 node _T_166 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_167 = lt(UInt<4>(0hb), _T_166) when _T_167 : node _T_168 = add(request_input.bits.addr, UInt<4>(0hb)) node _T_169 = tail(_T_168, 1) node _T_170 = dshr(request_input.bits.data, UInt<7>(0h58)) node _T_171 = bits(_T_170, 7, 0) regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1)) node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1) connect loginfo_cycles_18, _loginfo_cycles_T_37 node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_41 node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_169, _T_171) : printf_42 node _T_176 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_177 = lt(UInt<4>(0hc), _T_176) when _T_177 : node _T_178 = add(request_input.bits.addr, UInt<4>(0hc)) node _T_179 = tail(_T_178, 1) node _T_180 = dshr(request_input.bits.data, UInt<7>(0h60)) node _T_181 = bits(_T_180, 7, 0) regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1)) node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1) connect loginfo_cycles_19, _loginfo_cycles_T_39 node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_43 node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_179, _T_181) : printf_44 node _T_186 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_187 = lt(UInt<4>(0hd), _T_186) when _T_187 : node _T_188 = add(request_input.bits.addr, UInt<4>(0hd)) node _T_189 = tail(_T_188, 1) node _T_190 = dshr(request_input.bits.data, UInt<7>(0h68)) node _T_191 = bits(_T_190, 7, 0) regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1)) node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1) connect loginfo_cycles_20, _loginfo_cycles_T_41 node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_45 node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_189, _T_191) : printf_46 node _T_196 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_197 = lt(UInt<4>(0he), _T_196) when _T_197 : node _T_198 = add(request_input.bits.addr, UInt<4>(0he)) node _T_199 = tail(_T_198, 1) node _T_200 = dshr(request_input.bits.data, UInt<7>(0h70)) node _T_201 = bits(_T_200, 7, 0) regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1)) node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1) connect loginfo_cycles_21, _loginfo_cycles_T_43 node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_47 node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_199, _T_201) : printf_48 node _T_206 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_207 = lt(UInt<4>(0hf), _T_206) when _T_207 : node _T_208 = add(request_input.bits.addr, UInt<4>(0hf)) node _T_209 = tail(_T_208, 1) node _T_210 = dshr(request_input.bits.data, UInt<7>(0h78)) node _T_211 = bits(_T_210, 7, 0) regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1)) node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1) connect loginfo_cycles_22, _loginfo_cycles_T_45 node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_49 node _T_214 = asUInt(reset) node _T_215 = eq(_T_214, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_209, _T_211) : printf_50 node _T_216 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_217 = lt(UInt<5>(0h10), _T_216) when _T_217 : node _T_218 = add(request_input.bits.addr, UInt<5>(0h10)) node _T_219 = tail(_T_218, 1) node _T_220 = dshr(request_input.bits.data, UInt<8>(0h80)) node _T_221 = bits(_T_220, 7, 0) regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1)) node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1) connect loginfo_cycles_23, _loginfo_cycles_T_47 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_51 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_219, _T_221) : printf_52 node _T_226 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_227 = lt(UInt<5>(0h11), _T_226) when _T_227 : node _T_228 = add(request_input.bits.addr, UInt<5>(0h11)) node _T_229 = tail(_T_228, 1) node _T_230 = dshr(request_input.bits.data, UInt<8>(0h88)) node _T_231 = bits(_T_230, 7, 0) regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1)) node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1) connect loginfo_cycles_24, _loginfo_cycles_T_49 node _T_232 = asUInt(reset) node _T_233 = eq(_T_232, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_53 node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_229, _T_231) : printf_54 node _T_236 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_237 = lt(UInt<5>(0h12), _T_236) when _T_237 : node _T_238 = add(request_input.bits.addr, UInt<5>(0h12)) node _T_239 = tail(_T_238, 1) node _T_240 = dshr(request_input.bits.data, UInt<8>(0h90)) node _T_241 = bits(_T_240, 7, 0) regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1)) node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1) connect loginfo_cycles_25, _loginfo_cycles_T_51 node _T_242 = asUInt(reset) node _T_243 = eq(_T_242, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_55 node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_239, _T_241) : printf_56 node _T_246 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_247 = lt(UInt<5>(0h13), _T_246) when _T_247 : node _T_248 = add(request_input.bits.addr, UInt<5>(0h13)) node _T_249 = tail(_T_248, 1) node _T_250 = dshr(request_input.bits.data, UInt<8>(0h98)) node _T_251 = bits(_T_250, 7, 0) regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1)) node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1) connect loginfo_cycles_26, _loginfo_cycles_T_53 node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_57 node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_249, _T_251) : printf_58 node _T_256 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_257 = lt(UInt<5>(0h14), _T_256) when _T_257 : node _T_258 = add(request_input.bits.addr, UInt<5>(0h14)) node _T_259 = tail(_T_258, 1) node _T_260 = dshr(request_input.bits.data, UInt<8>(0ha0)) node _T_261 = bits(_T_260, 7, 0) regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1)) node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1) connect loginfo_cycles_27, _loginfo_cycles_T_55 node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_59 node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_259, _T_261) : printf_60 node _T_266 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_267 = lt(UInt<5>(0h15), _T_266) when _T_267 : node _T_268 = add(request_input.bits.addr, UInt<5>(0h15)) node _T_269 = tail(_T_268, 1) node _T_270 = dshr(request_input.bits.data, UInt<8>(0ha8)) node _T_271 = bits(_T_270, 7, 0) regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1)) node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1) connect loginfo_cycles_28, _loginfo_cycles_T_57 node _T_272 = asUInt(reset) node _T_273 = eq(_T_272, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_61 node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_269, _T_271) : printf_62 node _T_276 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_277 = lt(UInt<5>(0h16), _T_276) when _T_277 : node _T_278 = add(request_input.bits.addr, UInt<5>(0h16)) node _T_279 = tail(_T_278, 1) node _T_280 = dshr(request_input.bits.data, UInt<8>(0hb0)) node _T_281 = bits(_T_280, 7, 0) regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1)) node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1) connect loginfo_cycles_29, _loginfo_cycles_T_59 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_63 node _T_284 = asUInt(reset) node _T_285 = eq(_T_284, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_279, _T_281) : printf_64 node _T_286 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_287 = lt(UInt<5>(0h17), _T_286) when _T_287 : node _T_288 = add(request_input.bits.addr, UInt<5>(0h17)) node _T_289 = tail(_T_288, 1) node _T_290 = dshr(request_input.bits.data, UInt<8>(0hb8)) node _T_291 = bits(_T_290, 7, 0) regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1)) node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1) connect loginfo_cycles_30, _loginfo_cycles_T_61 node _T_292 = asUInt(reset) node _T_293 = eq(_T_292, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_65 node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_289, _T_291) : printf_66 node _T_296 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_297 = lt(UInt<5>(0h18), _T_296) when _T_297 : node _T_298 = add(request_input.bits.addr, UInt<5>(0h18)) node _T_299 = tail(_T_298, 1) node _T_300 = dshr(request_input.bits.data, UInt<8>(0hc0)) node _T_301 = bits(_T_300, 7, 0) regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1)) node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1) connect loginfo_cycles_31, _loginfo_cycles_T_63 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_67 node _T_304 = asUInt(reset) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_299, _T_301) : printf_68 node _T_306 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_307 = lt(UInt<5>(0h19), _T_306) when _T_307 : node _T_308 = add(request_input.bits.addr, UInt<5>(0h19)) node _T_309 = tail(_T_308, 1) node _T_310 = dshr(request_input.bits.data, UInt<8>(0hc8)) node _T_311 = bits(_T_310, 7, 0) regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1)) node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1) connect loginfo_cycles_32, _loginfo_cycles_T_65 node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_69 node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_309, _T_311) : printf_70 node _T_316 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_317 = lt(UInt<5>(0h1a), _T_316) when _T_317 : node _T_318 = add(request_input.bits.addr, UInt<5>(0h1a)) node _T_319 = tail(_T_318, 1) node _T_320 = dshr(request_input.bits.data, UInt<8>(0hd0)) node _T_321 = bits(_T_320, 7, 0) regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1)) node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1) connect loginfo_cycles_33, _loginfo_cycles_T_67 node _T_322 = asUInt(reset) node _T_323 = eq(_T_322, UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_71 node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_319, _T_321) : printf_72 node _T_326 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_327 = lt(UInt<5>(0h1b), _T_326) when _T_327 : node _T_328 = add(request_input.bits.addr, UInt<5>(0h1b)) node _T_329 = tail(_T_328, 1) node _T_330 = dshr(request_input.bits.data, UInt<8>(0hd8)) node _T_331 = bits(_T_330, 7, 0) regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1)) node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1) connect loginfo_cycles_34, _loginfo_cycles_T_69 node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_73 node _T_334 = asUInt(reset) node _T_335 = eq(_T_334, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_329, _T_331) : printf_74 node _T_336 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_337 = lt(UInt<5>(0h1c), _T_336) when _T_337 : node _T_338 = add(request_input.bits.addr, UInt<5>(0h1c)) node _T_339 = tail(_T_338, 1) node _T_340 = dshr(request_input.bits.data, UInt<8>(0he0)) node _T_341 = bits(_T_340, 7, 0) regreset loginfo_cycles_35 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_70 = add(loginfo_cycles_35, UInt<1>(0h1)) node _loginfo_cycles_T_71 = tail(_loginfo_cycles_T_70, 1) connect loginfo_cycles_35, _loginfo_cycles_T_71 node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_35) : printf_75 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_339, _T_341) : printf_76 node _T_346 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_347 = lt(UInt<5>(0h1d), _T_346) when _T_347 : node _T_348 = add(request_input.bits.addr, UInt<5>(0h1d)) node _T_349 = tail(_T_348, 1) node _T_350 = dshr(request_input.bits.data, UInt<8>(0he8)) node _T_351 = bits(_T_350, 7, 0) regreset loginfo_cycles_36 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_72 = add(loginfo_cycles_36, UInt<1>(0h1)) node _loginfo_cycles_T_73 = tail(_loginfo_cycles_T_72, 1) connect loginfo_cycles_36, _loginfo_cycles_T_73 node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_36) : printf_77 node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_349, _T_351) : printf_78 node _T_356 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_357 = lt(UInt<5>(0h1e), _T_356) when _T_357 : node _T_358 = add(request_input.bits.addr, UInt<5>(0h1e)) node _T_359 = tail(_T_358, 1) node _T_360 = dshr(request_input.bits.data, UInt<8>(0hf0)) node _T_361 = bits(_T_360, 7, 0) regreset loginfo_cycles_37 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_74 = add(loginfo_cycles_37, UInt<1>(0h1)) node _loginfo_cycles_T_75 = tail(_loginfo_cycles_T_74, 1) connect loginfo_cycles_37, _loginfo_cycles_T_75 node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_37) : printf_79 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_359, _T_361) : printf_80 node _T_366 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_367 = lt(UInt<5>(0h1f), _T_366) when _T_367 : node _T_368 = add(request_input.bits.addr, UInt<5>(0h1f)) node _T_369 = tail(_T_368, 1) node _T_370 = dshr(request_input.bits.data, UInt<8>(0hf8)) node _T_371 = bits(_T_370, 7, 0) regreset loginfo_cycles_38 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_76 = add(loginfo_cycles_38, UInt<1>(0h1)) node _loginfo_cycles_T_77 = tail(_loginfo_cycles_T_76, 1) connect loginfo_cycles_38, _loginfo_cycles_T_77 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_38) : printf_81 node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [fhdr_writer]\n", _T_369, _T_371) : printf_82 inst response_latency_injection_q of LatencyInjectionQueue_1 connect response_latency_injection_q.clock, clock connect response_latency_injection_q.reset, reset connect response_latency_injection_q.io.latency_cycles, io.latency_inject_cycles connect response_latency_injection_q.io.enq, masterNodeOut.d node _selectQready_T = eq(UInt<1>(0h0), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_1 = and(Queue4_L2RespInternal.io.enq.ready, _selectQready_T) node _selectQready_T_2 = eq(UInt<1>(0h1), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_3 = and(Queue4_L2RespInternal_1.io.enq.ready, _selectQready_T_2) node _selectQready_T_4 = eq(UInt<2>(0h2), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_5 = and(Queue4_L2RespInternal_2.io.enq.ready, _selectQready_T_4) node _selectQready_T_6 = eq(UInt<2>(0h3), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_7 = and(Queue4_L2RespInternal_3.io.enq.ready, _selectQready_T_6) node _selectQready_T_8 = or(_selectQready_T_1, _selectQready_T_3) node _selectQready_T_9 = or(_selectQready_T_8, _selectQready_T_5) node selectQready = or(_selectQready_T_9, _selectQready_T_7) node _T_376 = and(selectQready, response_latency_injection_q.io.deq.valid) when _T_376 : connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h1) connect tags_for_issue_Q.io.enq.bits, response_latency_injection_q.io.deq.bits.source node _T_377 = and(selectQready, response_latency_injection_q.io.deq.valid) node _T_378 = and(_T_377, tags_for_issue_Q.io.enq.valid) when _T_378 : regreset loginfo_cycles_39 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_78 = add(loginfo_cycles_39, UInt<1>(0h1)) node _loginfo_cycles_T_79 = tail(_loginfo_cycles_T_78, 1) connect loginfo_cycles_39, _loginfo_cycles_T_79 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_39) : printf_83 node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "[fhdr_writer] tags_for_issue_Q add back tag %d\n", tags_for_issue_Q.io.enq.bits) : printf_84 node _response_latency_injection_q_io_deq_ready_T = and(selectQready, tags_for_issue_Q.io.enq.ready) connect response_latency_injection_q.io.deq.ready, _response_latency_injection_q_io_deq_ready_T node _T_383 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_384 = eq(response_latency_injection_q.io.deq.bits.source, UInt<1>(0h0)) node _T_385 = and(_T_383, _T_384) connect Queue4_L2RespInternal.io.enq.valid, _T_385 connect Queue4_L2RespInternal.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_386 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_387 = eq(response_latency_injection_q.io.deq.bits.source, UInt<1>(0h1)) node _T_388 = and(_T_386, _T_387) connect Queue4_L2RespInternal_1.io.enq.valid, _T_388 connect Queue4_L2RespInternal_1.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_389 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_390 = eq(response_latency_injection_q.io.deq.bits.source, UInt<2>(0h2)) node _T_391 = and(_T_389, _T_390) connect Queue4_L2RespInternal_2.io.enq.valid, _T_391 connect Queue4_L2RespInternal_2.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_392 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_393 = eq(response_latency_injection_q.io.deq.bits.source, UInt<2>(0h3)) node _T_394 = and(_T_392, _T_393) connect Queue4_L2RespInternal_3.io.enq.valid, _T_394 connect Queue4_L2RespInternal_3.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _queueValid_T = eq(UInt<1>(0h0), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_1 = and(Queue4_L2RespInternal.io.deq.valid, _queueValid_T) node _queueValid_T_2 = eq(UInt<1>(0h1), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_3 = and(Queue4_L2RespInternal_1.io.deq.valid, _queueValid_T_2) node _queueValid_T_4 = eq(UInt<2>(0h2), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_5 = and(Queue4_L2RespInternal_2.io.deq.valid, _queueValid_T_4) node _queueValid_T_6 = eq(UInt<2>(0h3), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_7 = and(Queue4_L2RespInternal_3.io.deq.valid, _queueValid_T_6) node _queueValid_T_8 = or(_queueValid_T_1, _queueValid_T_3) node _queueValid_T_9 = or(_queueValid_T_8, _queueValid_T_5) node queueValid = or(_queueValid_T_9, _queueValid_T_7) node resultdata_is_current_q = eq(UInt<1>(0h0), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data : UInt<256> when resultdata_is_current_q : node _resultdata_data_T = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_1 = dshr(Queue4_L2RespInternal.io.deq.bits.data, _resultdata_data_T) connect resultdata_data, _resultdata_data_T_1 else : connect resultdata_data, UInt<1>(0h0) node resultdata_is_current_q_1 = eq(UInt<1>(0h1), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_1 : UInt<256> when resultdata_is_current_q_1 : node _resultdata_data_T_2 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_3 = dshr(Queue4_L2RespInternal_1.io.deq.bits.data, _resultdata_data_T_2) connect resultdata_data_1, _resultdata_data_T_3 else : connect resultdata_data_1, UInt<1>(0h0) node resultdata_is_current_q_2 = eq(UInt<2>(0h2), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_2 : UInt<256> when resultdata_is_current_q_2 : node _resultdata_data_T_4 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_5 = dshr(Queue4_L2RespInternal_2.io.deq.bits.data, _resultdata_data_T_4) connect resultdata_data_2, _resultdata_data_T_5 else : connect resultdata_data_2, UInt<1>(0h0) node resultdata_is_current_q_3 = eq(UInt<2>(0h3), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_3 : UInt<256> when resultdata_is_current_q_3 : node _resultdata_data_T_6 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_7 = dshr(Queue4_L2RespInternal_3.io.deq.bits.data, _resultdata_data_T_6) connect resultdata_data_3, _resultdata_data_T_7 else : connect resultdata_data_3, UInt<1>(0h0) node _resultdata_T = or(resultdata_data, resultdata_data_1) node _resultdata_T_1 = or(_resultdata_T, resultdata_data_2) node resultdata = or(_resultdata_T_1, resultdata_data_3) connect response_output.bits.data, resultdata node _response_output_valid_T = and(queueValid, outstanding_req_addr.io.deq.valid) connect response_output.valid, _response_output_valid_T node _outstanding_req_addr_io_deq_ready_T = and(queueValid, response_output.ready) connect outstanding_req_addr.io.deq.ready, _outstanding_req_addr_io_deq_ready_T node _T_395 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_396 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<1>(0h0)) node _T_397 = and(_T_395, _T_396) connect Queue4_L2RespInternal.io.deq.ready, _T_397 node _T_398 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_399 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<1>(0h1)) node _T_400 = and(_T_398, _T_399) connect Queue4_L2RespInternal_1.io.deq.ready, _T_400 node _T_401 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_402 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<2>(0h2)) node _T_403 = and(_T_401, _T_402) connect Queue4_L2RespInternal_2.io.deq.ready, _T_403 node _T_404 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_405 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<2>(0h3)) node _T_406 = and(_T_404, _T_405) connect Queue4_L2RespInternal_3.io.deq.ready, _T_406 node _T_407 = and(masterNodeOut.d.ready, masterNodeOut.d.valid) when _T_407 : node opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) when opdata : regreset loginfo_cycles_40 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_80 = add(loginfo_cycles_40, UInt<1>(0h1)) node _loginfo_cycles_T_81 = tail(_loginfo_cycles_T_80, 1) connect loginfo_cycles_40, _loginfo_cycles_T_81 node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_40) : printf_85 node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "[fhdr_writer] L2IF: resp(read) data: 0x%x, opnum: %d, gettag: %d\n", masterNodeOut.d.bits.data, global_memop_ackd, masterNodeOut.d.bits.source) : printf_86 else : regreset loginfo_cycles_41 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_82 = add(loginfo_cycles_41, UInt<1>(0h1)) node _loginfo_cycles_T_83 = tail(_loginfo_cycles_T_82, 1) connect loginfo_cycles_41, _loginfo_cycles_T_83 node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_41) : printf_87 node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "[fhdr_writer] L2IF: resp(write) opnum: %d, gettag: %d\n", global_memop_ackd, masterNodeOut.d.bits.source) : printf_88 node _T_416 = and(response_output.ready, response_output.valid) when _T_416 : regreset loginfo_cycles_42 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_84 = add(loginfo_cycles_42, UInt<1>(0h1)) node _loginfo_cycles_T_85 = tail(_loginfo_cycles_T_84, 1) connect loginfo_cycles_42, _loginfo_cycles_T_85 node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_42) : printf_89 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "[fhdr_writer] L2IF: realresp() data: 0x%x, opnum: %d, gettag: %d\n", resultdata, global_memop_resp_to_user, outstanding_req_addr.io.deq.bits.tag) : printf_90 node _T_421 = and(response_latency_injection_q.io.deq.ready, response_latency_injection_q.io.deq.valid) when _T_421 : node _global_memop_ackd_T = add(global_memop_ackd, UInt<1>(0h1)) node _global_memop_ackd_T_1 = tail(_global_memop_ackd_T, 1) connect global_memop_ackd, _global_memop_ackd_T_1 node _T_422 = and(response_output.ready, response_output.valid) when _T_422 : node _global_memop_resp_to_user_T = add(global_memop_resp_to_user, UInt<1>(0h1)) node _global_memop_resp_to_user_T_1 = tail(_global_memop_resp_to_user_T, 1) connect global_memop_resp_to_user, _global_memop_resp_to_user_T_1 extmodule plusarg_reader_116 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_117 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module L2MemHelperLatencyInjection( // @[L2MemHelperLatencyInjection.scala:29:7] input clock, // @[L2MemHelperLatencyInjection.scala:29:7] input reset, // @[L2MemHelperLatencyInjection.scala:29:7] input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_master_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_master_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [255:0] auto_master_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_master_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [255:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_userif_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_userif_req_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [2:0] io_userif_req_bits_size, // @[L2MemHelperLatencyInjection.scala:33:14] input [255:0] io_userif_req_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [255:0] io_userif_resp_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_no_memops_inflight, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_latency_inject_cycles, // @[L2MemHelperLatencyInjection.scala:33:14] input io_sfence, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [26:0] io_ptw_req_bits_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_bits_bits_need_gpa, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_ptw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_final, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hx, // @[L2MemHelperLatencyInjection.scala:33:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_d, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_g, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_u, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_r, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_level, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_homogeneous, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_is_pte, // @[L2MemHelperLatencyInjection.scala:33:14] input [3:0] io_ptw_ptbr_mode, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_ptbr_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_status_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spvp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_gstatus_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_ptw_gstatus_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_ptw_gstatus_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_uie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_0_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_0_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_1_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_1_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_2_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_2_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_3_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_3_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_4_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_4_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_5_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_5_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_6_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_6_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_7_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_7_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_status_bits_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_status_bits_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_uxl, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd_rv32, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_status_bits_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_xs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_uie // @[L2MemHelperLatencyInjection.scala:33:14] ); wire _response_latency_injection_q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:245:44] wire [1:0] _response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44] wire [255:0] _response_latency_injection_q_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:245:44] wire _Queue4_L2RespInternal_3_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_3_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_2_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_1_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _request_latency_injection_q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:151:43] wire _tags_for_issue_Q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:94:32] wire _tags_for_issue_Q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:94:32] wire [1:0] _tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32] wire _outstanding_req_addr_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:91:36] wire _outstanding_req_addr_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_addrindex; // @[L2MemHelperLatencyInjection.scala:91:36] wire [1:0] _outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36] wire _tlb_io_req_ready; // @[L2MemHelperLatencyInjection.scala:68:19] wire _tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19] wire [31:0] _tlb_io_resp_paddr; // @[L2MemHelperLatencyInjection.scala:68:19] wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_d_bits_source_0 = auto_master_out_d_bits_source; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_valid_0 = io_userif_req_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_userif_req_bits_addr_0 = io_userif_req_bits_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] io_userif_req_bits_size_0 = io_userif_req_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_req_bits_data_0 = io_userif_req_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_latency_inject_cycles_0 = io_latency_inject_cycles; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_sfence_0 = io_sfence; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[L2MemHelperLatencyInjection.scala:29:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_valid_0 = io_status_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_debug_0 = io_status_bits_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_cease_0 = io_status_bits_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_wfi_0 = io_status_bits_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_status_bits_isa_0 = io_status_bits_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_dprv_0 = io_status_bits_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_dv_0 = io_status_bits_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_prv_0 = io_status_bits_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_v_0 = io_status_bits_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_0 = io_status_bits_sd; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_status_bits_zero2_0 = io_status_bits_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpv_0 = io_status_bits_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_gva_0 = io_status_bits_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mbe_0 = io_status_bits_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sbe_0 = io_status_bits_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_sxl_0 = io_status_bits_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_uxl_0 = io_status_bits_uxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_rv32_0 = io_status_bits_sd_rv32; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_status_bits_zero1_0 = io_status_bits_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tsr_0 = io_status_bits_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tw_0 = io_status_bits_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tvm_0 = io_status_bits_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mxr_0 = io_status_bits_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sum_0 = io_status_bits_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mprv_0 = io_status_bits_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_xs_0 = io_status_bits_xs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_fs_0 = io_status_bits_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_mpp_0 = io_status_bits_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_vs_0 = io_status_bits_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spp_0 = io_status_bits_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpie_0 = io_status_bits_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_ube_0 = io_status_bits_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spie_0 = io_status_bits_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_upie_0 = io_status_bits_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mie_0 = io_status_bits_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_hie_0 = io_status_bits_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sie_0 = io_status_bits_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_uie_0 = io_status_bits_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire _printf_T = reset; // @[annotations.scala:102:49] wire _printf_T_2 = reset; // @[annotations.scala:102:49] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_ube = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_upie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_hie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_uie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtw = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_hu = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire bundle_corrupt = 1'h0; // @[Edges.scala:460:17] wire _legal_T_125 = 1'h0; // @[Parameters.scala:684:29] wire _legal_T_131 = 1'h0; // @[Parameters.scala:684:54] wire bundle_1_corrupt = 1'h0; // @[Edges.scala:480:17] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_bits_cmd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_ready = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_valid = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire request_input_bits_cmd = 1'h1; // @[L2MemHelperLatencyInjection.scala:44:27] wire response_output_ready = 1'h1; // @[L2MemHelperLatencyInjection.scala:53:29] wire _legal_T = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_63 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_64 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_65 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_66 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_73 = 1'h1; // @[Parameters.scala:92:28] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] bundle_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] bundle_1_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] bundle_1_param = 3'h0; // @[Edges.scala:480:17] wire [255:0] bundle_data = 256'h0; // @[Edges.scala:460:17] wire [2:0] bundle_opcode = 3'h4; // @[Edges.scala:460:17] wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_source = auto_master_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire request_input_ready; // @[L2MemHelperLatencyInjection.scala:44:27] wire request_input_valid = io_userif_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [63:0] request_input_bits_addr = io_userif_req_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [2:0] request_input_bits_size = io_userif_req_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [255:0] request_input_bits_data = io_userif_req_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire response_output_valid; // @[L2MemHelperLatencyInjection.scala:53:29] wire [255:0] response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:53:29] wire _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:128:57] wire [2:0] auto_master_out_a_bits_opcode_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_a_bits_param_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_a_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_a_bits_source_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_address_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_mask_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_a_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_bits_corrupt_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_resp_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_no_memops_inflight_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_opcode_0 = masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_param_0 = masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_size_0 = masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_source_0 = masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_mask_0 = masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_data_0 = masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_corrupt_0 = masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_master_out_d_ready_0 = masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire _request_input_ready_T_4; // @[Misc.scala:26:53] assign io_userif_req_ready_0 = request_input_ready; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire _response_output_valid_T; // @[Misc.scala:26:53] assign io_userif_resp_valid_0 = response_output_valid; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire [255:0] resultdata; // @[L2MemHelperLatencyInjection.scala:307:15] assign io_userif_resp_bits_data_0 = response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] reg status_debug; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_cease; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_wfi; // @[L2MemHelperLatencyInjection.scala:62:19] reg [31:0] status_isa; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_dprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_dv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_prv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_v; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd; // @[L2MemHelperLatencyInjection.scala:62:19] reg [22:0] status_zero2; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_gva; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_sxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_uxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd_rv32; // @[L2MemHelperLatencyInjection.scala:62:19] reg [7:0] status_zero1; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tsr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tw; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tvm; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mxr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sum; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_xs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_fs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_mpp; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_vs; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spp; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_ube; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_upie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_hie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_uie; // @[L2MemHelperLatencyInjection.scala:62:19] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] wire _tlb_ready_T = ~_tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19, :74:39] wire tlb_ready = _tlb_io_req_ready & _tlb_ready_T; // @[L2MemHelperLatencyInjection.scala:68:19, :74:{36,39}] reg [2:0] tags_init_reg; // @[L2MemHelperLatencyInjection.scala:98:30] wire _T_4 = tags_init_reg != 3'h4; // @[L2MemHelperLatencyInjection.scala:98:30, :99:23] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] wire [3:0] _tags_init_reg_T = {1'h0, tags_init_reg} + 4'h1; // @[L2MemHelperLatencyInjection.scala:98:30, :104:38] wire [2:0] _tags_init_reg_T_1 = _tags_init_reg_T[2:0]; // @[L2MemHelperLatencyInjection.scala:104:38] wire [70:0] _addr_mask_check_T = 71'h1 << request_input_bits_size; // @[L2MemHelperLatencyInjection.scala:44:27, :108:36] wire [71:0] _addr_mask_check_T_1 = {1'h0, _addr_mask_check_T} - 72'h1; // @[L2MemHelperLatencyInjection.scala:108:{36,64}] wire [70:0] addr_mask_check = _addr_mask_check_T_1[70:0]; // @[L2MemHelperLatencyInjection.scala:108:64] wire _assertcheck_T = ~request_input_valid; // @[L2MemHelperLatencyInjection.scala:44:27, :109:30] wire [70:0] _assertcheck_T_1 = {7'h0, addr_mask_check[63:0] & request_input_bits_addr}; // @[L2MemHelperLatencyInjection.scala:44:27, :108:64, :109:81] wire _assertcheck_T_2 = _assertcheck_T_1 == 71'h0; // @[L2MemHelperLatencyInjection.scala:108:64, :109:{81,100}] wire _assertcheck_T_3 = _assertcheck_T \| _assertcheck_T_2; // @[L2MemHelperLatencyInjection.scala:109:{30,52,100}] reg assertcheck; // @[L2MemHelperLatencyInjection.scala:109:28] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] global_memop_accepted; // @[L2MemHelperLatencyInjection.scala:117:38] wire [64:0] _global_memop_accepted_T = {1'h0, global_memop_accepted} + 65'h1; // @[L2MemHelperLatencyInjection.scala:117:38, :119:52] wire [63:0] _global_memop_accepted_T_1 = _global_memop_accepted_T[63:0]; // @[L2MemHelperLatencyInjection.scala:119:52] reg [63:0] global_memop_sent; // @[L2MemHelperLatencyInjection.scala:122:34] reg [63:0] global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:124:34] reg [63:0] global_memop_resp_to_user; // @[L2MemHelperLatencyInjection.scala:126:42] assign _io_userif_no_memops_inflight_T = global_memop_accepted == global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:117:38, :124:34, :128:57] assign io_userif_no_memops_inflight_0 = _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:29:7, :128:57] wire [64:0] _GEN = {1'h0, global_memop_sent}; // @[L2MemHelperLatencyInjection.scala:122:34, :130:54] wire [64:0] _GEN_0 = {1'h0, global_memop_ackd}; // @[L2MemHelperLatencyInjection.scala:124:34, :130:54] wire [64:0] _GEN_1 = _GEN - _GEN_0; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:130:54] assign _free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _assert_free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:131:61] assign _assert_free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54, :131:61] wire [63:0] _free_outstanding_op_slots_T_1 = _free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:130:54] wire free_outstanding_op_slots = _free_outstanding_op_slots_T_1 < 64'h4; // @[L2MemHelperLatencyInjection.scala:130:{54,75}] wire [63:0] _assert_free_outstanding_op_slots_T_1 = _assert_free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:131:61] wire assert_free_outstanding_op_slots = _assert_free_outstanding_op_slots_T_1 < 64'h5; // @[L2MemHelperLatencyInjection.scala:131:{61,82}] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] wire [64:0] _global_memop_sent_T = _GEN + 65'h1; // @[L2MemHelperLatencyInjection.scala:130:54, :140:44] wire [63:0] _global_memop_sent_T_1 = _global_memop_sent_T[63:0]; // @[L2MemHelperLatencyInjection.scala:140:44] reg [63:0] cur_cycle; // @[L2MemHelperLatencyInjection.scala:146:26] wire [64:0] _cur_cycle_T = {1'h0, cur_cycle} + 65'h1; // @[L2MemHelperLatencyInjection.scala:146:26, :147:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[L2MemHelperLatencyInjection.scala:147:26] wire [31:0] _GEN_2 = {_tlb_io_resp_paddr[31:14], _tlb_io_resp_paddr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_4; // @[Parameters.scala:137:31] assign _legal_T_4 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _legal_T_67; // @[Parameters.scala:137:31] assign _legal_T_67 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_6 = _legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46] wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54] wire _legal_T_62 = _legal_T_9; // @[Parameters.scala:684:54, :686:26] wire _GEN_3 = request_input_bits_size != 3'h7; // @[Parameters.scala:92:38] wire _legal_T_11; // @[Parameters.scala:92:38] assign _legal_T_11 = _GEN_3; // @[Parameters.scala:92:38] wire _legal_T_74; // @[Parameters.scala:92:38] assign _legal_T_74 = _GEN_3; // @[Parameters.scala:92:38] wire _legal_T_12 = _legal_T_11; // @[Parameters.scala:92:{33,38}] wire _legal_T_13 = _legal_T_12; // @[Parameters.scala:684:29] wire [31:0] _legal_T_14; // @[Parameters.scala:137:31] wire [32:0] _legal_T_15 = {1'h0, _legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_16 = _legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_17 = _legal_T_16; // @[Parameters.scala:137:46] wire _legal_T_18 = _legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_4 = {_tlb_io_resp_paddr[31:17], _tlb_io_resp_paddr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_19; // @[Parameters.scala:137:31] assign _legal_T_19 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_24; // @[Parameters.scala:137:31] assign _legal_T_24 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_126; // @[Parameters.scala:137:31] assign _legal_T_126 = _GEN_4; // @[Parameters.scala:137:31] wire [32:0] _legal_T_20 = {1'h0, _legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_21 = _legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_22 = _legal_T_21; // @[Parameters.scala:137:46] wire _legal_T_23 = _legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_25 = {1'h0, _legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_26 = _legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_27 = _legal_T_26; // @[Parameters.scala:137:46] wire _legal_T_28 = _legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_5 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_29; // @[Parameters.scala:137:31] assign _legal_T_29 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_87; // @[Parameters.scala:137:31] assign _legal_T_87 = _GEN_5; // @[Parameters.scala:137:31] wire [32:0] _legal_T_30 = {1'h0, _legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_31 = _legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_32 = _legal_T_31; // @[Parameters.scala:137:46] wire _legal_T_33 = _legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_6 = {_tlb_io_resp_paddr[31:28], _tlb_io_resp_paddr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_34; // @[Parameters.scala:137:31] assign _legal_T_34 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_39; // @[Parameters.scala:137:31] assign _legal_T_39 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_97; // @[Parameters.scala:137:31] assign _legal_T_97 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_102; // @[Parameters.scala:137:31] assign _legal_T_102 = _GEN_6; // @[Parameters.scala:137:31] wire [32:0] _legal_T_35 = {1'h0, _legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_36 = _legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_37 = _legal_T_36; // @[Parameters.scala:137:46] wire _legal_T_38 = _legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_40 = {1'h0, _legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_41 = _legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_42 = _legal_T_41; // @[Parameters.scala:137:46] wire _legal_T_43 = _legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_7 = {_tlb_io_resp_paddr[31:29], _tlb_io_resp_paddr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_44; // @[Parameters.scala:137:31] assign _legal_T_44 = _GEN_7; // @[Parameters.scala:137:31] wire [31:0] _legal_T_107; // @[Parameters.scala:137:31] assign _legal_T_107 = _GEN_7; // @[Parameters.scala:137:31] wire [32:0] _legal_T_45 = {1'h0, _legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_46 = _legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_47 = _legal_T_46; // @[Parameters.scala:137:46] wire _legal_T_48 = _legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_8 = _tlb_io_resp_paddr ^ 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _legal_T_49; // @[Parameters.scala:137:31] assign _legal_T_49 = _GEN_8; // @[Parameters.scala:137:31] wire [31:0] _legal_T_112; // @[Parameters.scala:137:31] assign _legal_T_112 = _GEN_8; // @[Parameters.scala:137:31] wire [32:0] _legal_T_50 = {1'h0, _legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_51 = _legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_52 = _legal_T_51; // @[Parameters.scala:137:46] wire _legal_T_53 = _legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_54 = _legal_T_18 \| _legal_T_23; // @[Parameters.scala:685:42] wire _legal_T_55 = _legal_T_54 \| _legal_T_28; // @[Parameters.scala:685:42] wire _legal_T_56 = _legal_T_55 \| _legal_T_33; // @[Parameters.scala:685:42] wire _legal_T_57 = _legal_T_56 \| _legal_T_38; // @[Parameters.scala:685:42] wire _legal_T_58 = _legal_T_57 \| _legal_T_43; // @[Parameters.scala:685:42] wire _legal_T_59 = _legal_T_58 \| _legal_T_48; // @[Parameters.scala:685:42] wire _legal_T_60 = _legal_T_59 \| _legal_T_53; // @[Parameters.scala:685:42] wire _legal_T_61 = _legal_T_13 & _legal_T_60; // @[Parameters.scala:684:{29,54}, :685:42] wire legal = _legal_T_62 \| _legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [31:0] _a_mask_T; // @[Misc.scala:222:10] wire [3:0] bundle_size; // @[Edges.scala:460:17] wire [1:0] bundle_source; // @[Edges.scala:460:17] wire [31:0] bundle_address; // @[Edges.scala:460:17] wire [31:0] bundle_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_9 = {1'h0, request_input_bits_size}; // @[Edges.scala:463:15] assign bundle_size = _GEN_9; // @[Edges.scala:460:17, :463:15] wire [3:0] bundle_1_size; // @[Edges.scala:480:17] assign bundle_1_size = _GEN_9; // @[Edges.scala:463:15, :480:17] wire [4:0] _GEN_10 = {2'h0, request_input_bits_size}; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _a_mask_sizeOH_T = _GEN_10; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _a_mask_sizeOH_T_3 = _GEN_10; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_shiftAmount_T = _a_mask_sizeOH_T; // @[OneHot.scala:64:31] wire [2:0] a_mask_sizeOH_shiftAmount = _a_mask_sizeOH_shiftAmount_T[2:0]; // @[OneHot.scala:64:{31,49}] wire [7:0] _a_mask_sizeOH_T_1 = 8'h1 << a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [4:0] _a_mask_sizeOH_T_2 = _a_mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] a_mask_sizeOH = {_a_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27] wire _GEN_11 = request_input_bits_size > 3'h4; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_sub_0_1; // @[Misc.scala:206:21] assign a_mask_sub_sub_sub_sub_sub_0_1 = _GEN_11; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_sub_0_1_1; // @[Misc.scala:206:21] assign a_mask_sub_sub_sub_sub_sub_0_1_1 = _GEN_11; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_size = a_mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_sub_bit = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_sub_acc_T = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_sub_0_1 \| _a_mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _a_mask_sub_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_sub_0_1 \| _a_mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire a_mask_sub_sub_sub_size = a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_bit = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_0_1 \| _a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_0_1 \| _a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_2_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_2_1 = a_mask_sub_sub_sub_sub_1_1 \| _a_mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_3_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_3_1 = a_mask_sub_sub_sub_sub_1_1 \| _a_mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_size = a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_bit = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_bit_1 = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_nbit = ~a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T = a_mask_sub_sub_size & a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_0_1 = a_mask_sub_sub_sub_0_1 \| _a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_1_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_1 = a_mask_sub_sub_size & a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_1_1 = a_mask_sub_sub_sub_0_1 \| _a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_2_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_2 = a_mask_sub_sub_size & a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_2_1 = a_mask_sub_sub_sub_1_1 \| _a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_3_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_3 = a_mask_sub_sub_size & a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_3_1 = a_mask_sub_sub_sub_1_1 \| _a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_4_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_4 = a_mask_sub_sub_size & a_mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_4_1 = a_mask_sub_sub_sub_2_1 \| _a_mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_5_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_5 = a_mask_sub_sub_size & a_mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_5_1 = a_mask_sub_sub_sub_2_1 \| _a_mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_6_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_6 = a_mask_sub_sub_size & a_mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_6_1 = a_mask_sub_sub_sub_3_1 \| _a_mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_7_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_7 = a_mask_sub_sub_size & a_mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_7_1 = a_mask_sub_sub_sub_3_1 \| _a_mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_size = a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_bit = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_bit_1 = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2 = a_mask_sub_sub_0_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T = a_mask_sub_size & a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_0_1 = a_mask_sub_sub_0_1 \| _a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_1_2 = a_mask_sub_sub_0_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_1 = a_mask_sub_size & a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_1_1 = a_mask_sub_sub_0_1 \| _a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_2_2 = a_mask_sub_sub_1_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_2 = a_mask_sub_size & a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_2_1 = a_mask_sub_sub_1_1 \| _a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_3_2 = a_mask_sub_sub_1_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_3 = a_mask_sub_size & a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_3_1 = a_mask_sub_sub_1_1 \| _a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_4_2 = a_mask_sub_sub_2_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_4 = a_mask_sub_size & a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_4_1 = a_mask_sub_sub_2_1 \| _a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_5_2 = a_mask_sub_sub_2_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_5 = a_mask_sub_size & a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_5_1 = a_mask_sub_sub_2_1 \| _a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_6_2 = a_mask_sub_sub_3_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_6 = a_mask_sub_size & a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_6_1 = a_mask_sub_sub_3_1 \| _a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_7_2 = a_mask_sub_sub_3_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_7 = a_mask_sub_size & a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_7_1 = a_mask_sub_sub_3_1 \| _a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_8_2 = a_mask_sub_sub_4_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_8 = a_mask_sub_size & a_mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_8_1 = a_mask_sub_sub_4_1 \| _a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_sub_9_2 = a_mask_sub_sub_4_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_9 = a_mask_sub_size & a_mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_9_1 = a_mask_sub_sub_4_1 \| _a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_sub_10_2 = a_mask_sub_sub_5_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_10 = a_mask_sub_size & a_mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_10_1 = a_mask_sub_sub_5_1 \| _a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_sub_11_2 = a_mask_sub_sub_5_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_11 = a_mask_sub_size & a_mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_11_1 = a_mask_sub_sub_5_1 \| _a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_sub_12_2 = a_mask_sub_sub_6_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_12 = a_mask_sub_size & a_mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_12_1 = a_mask_sub_sub_6_1 \| _a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_sub_13_2 = a_mask_sub_sub_6_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_13 = a_mask_sub_size & a_mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_13_1 = a_mask_sub_sub_6_1 \| _a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_sub_14_2 = a_mask_sub_sub_7_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_14 = a_mask_sub_size & a_mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_14_1 = a_mask_sub_sub_7_1 \| _a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_sub_15_2 = a_mask_sub_sub_7_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_15 = a_mask_sub_size & a_mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_15_1 = a_mask_sub_sub_7_1 \| _a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_size = a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire a_mask_bit = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_bit_1 = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T = a_mask_size & a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc = a_mask_sub_0_1 \| _a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_1 = a_mask_size & a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_1 = a_mask_sub_0_1 \| _a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_2 = a_mask_size & a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_2 = a_mask_sub_1_1 \| _a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_3 = a_mask_size & a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_3 = a_mask_sub_1_1 \| _a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_eq_4 = a_mask_sub_2_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_4 = a_mask_size & a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_4 = a_mask_sub_2_1 \| _a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_eq_5 = a_mask_sub_2_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_5 = a_mask_size & a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_5 = a_mask_sub_2_1 \| _a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_eq_6 = a_mask_sub_3_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_6 = a_mask_size & a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_6 = a_mask_sub_3_1 \| _a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_eq_7 = a_mask_sub_3_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_7 = a_mask_size & a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_7 = a_mask_sub_3_1 \| _a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_eq_8 = a_mask_sub_4_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_8 = a_mask_size & a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_8 = a_mask_sub_4_1 \| _a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_eq_9 = a_mask_sub_4_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_9 = a_mask_size & a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_9 = a_mask_sub_4_1 \| _a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_eq_10 = a_mask_sub_5_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_10 = a_mask_size & a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_10 = a_mask_sub_5_1 \| _a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_eq_11 = a_mask_sub_5_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_11 = a_mask_size & a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_11 = a_mask_sub_5_1 \| _a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_eq_12 = a_mask_sub_6_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_12 = a_mask_size & a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_12 = a_mask_sub_6_1 \| _a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_eq_13 = a_mask_sub_6_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_13 = a_mask_size & a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_13 = a_mask_sub_6_1 \| _a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_eq_14 = a_mask_sub_7_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_14 = a_mask_size & a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_14 = a_mask_sub_7_1 \| _a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_eq_15 = a_mask_sub_7_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_15 = a_mask_size & a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_15 = a_mask_sub_7_1 \| _a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_eq_16 = a_mask_sub_8_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_16 = a_mask_size & a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_16 = a_mask_sub_8_1 \| _a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire a_mask_eq_17 = a_mask_sub_8_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_17 = a_mask_size & a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_17 = a_mask_sub_8_1 \| _a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire a_mask_eq_18 = a_mask_sub_9_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_18 = a_mask_size & a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_18 = a_mask_sub_9_1 \| _a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire a_mask_eq_19 = a_mask_sub_9_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_19 = a_mask_size & a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_19 = a_mask_sub_9_1 \| _a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire a_mask_eq_20 = a_mask_sub_10_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_20 = a_mask_size & a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_20 = a_mask_sub_10_1 \| _a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire a_mask_eq_21 = a_mask_sub_10_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_21 = a_mask_size & a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_21 = a_mask_sub_10_1 \| _a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire a_mask_eq_22 = a_mask_sub_11_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_22 = a_mask_size & a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_22 = a_mask_sub_11_1 \| _a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire a_mask_eq_23 = a_mask_sub_11_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_23 = a_mask_size & a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_23 = a_mask_sub_11_1 \| _a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire a_mask_eq_24 = a_mask_sub_12_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_24 = a_mask_size & a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_24 = a_mask_sub_12_1 \| _a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire a_mask_eq_25 = a_mask_sub_12_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_25 = a_mask_size & a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_25 = a_mask_sub_12_1 \| _a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire a_mask_eq_26 = a_mask_sub_13_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_26 = a_mask_size & a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_26 = a_mask_sub_13_1 \| _a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire a_mask_eq_27 = a_mask_sub_13_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_27 = a_mask_size & a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_27 = a_mask_sub_13_1 \| _a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire a_mask_eq_28 = a_mask_sub_14_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_28 = a_mask_size & a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_28 = a_mask_sub_14_1 \| _a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire a_mask_eq_29 = a_mask_sub_14_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_29 = a_mask_size & a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_29 = a_mask_sub_14_1 \| _a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire a_mask_eq_30 = a_mask_sub_15_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_30 = a_mask_size & a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_30 = a_mask_sub_15_1 \| _a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire a_mask_eq_31 = a_mask_sub_15_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_31 = a_mask_size & a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_31 = a_mask_sub_15_1 \| _a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] a_mask_lo_lo_lo_lo = {a_mask_acc_1, a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_lo_hi = {a_mask_acc_3, a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_lo = {a_mask_lo_lo_lo_hi, a_mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo = {a_mask_acc_5, a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_hi_hi = {a_mask_acc_7, a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_hi = {a_mask_lo_lo_hi_hi, a_mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo = {a_mask_lo_lo_hi, a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo = {a_mask_acc_9, a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_lo_hi = {a_mask_acc_11, a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_lo = {a_mask_lo_hi_lo_hi, a_mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo = {a_mask_acc_13, a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_hi_hi = {a_mask_acc_15, a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_hi = {a_mask_lo_hi_hi_hi, a_mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi = {a_mask_lo_hi_hi, a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] a_mask_lo = {a_mask_lo_hi, a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo = {a_mask_acc_17, a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_lo_hi = {a_mask_acc_19, a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_lo = {a_mask_hi_lo_lo_hi, a_mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo = {a_mask_acc_21, a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_hi_hi = {a_mask_acc_23, a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_hi = {a_mask_hi_lo_hi_hi, a_mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo = {a_mask_hi_lo_hi, a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo = {a_mask_acc_25, a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_lo_hi = {a_mask_acc_27, a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_lo = {a_mask_hi_hi_lo_hi, a_mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo = {a_mask_acc_29, a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_hi_hi = {a_mask_acc_31, a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_hi = {a_mask_hi_hi_hi_hi, a_mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi = {a_mask_hi_hi_hi, a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] a_mask_hi = {a_mask_hi_hi, a_mask_hi_lo}; // @[Misc.scala:222:10] assign _a_mask_T = {a_mask_hi, a_mask_lo}; // @[Misc.scala:222:10] assign bundle_mask = _a_mask_T; // @[Misc.scala:222:10] wire [510:0] _T_31 = {255'h0, request_input_bits_data} << {503'h0, request_input_bits_addr[4:0], 3'h0}; // @[L2MemHelperLatencyInjection.scala:44:27, :172:{58,86}] wire [32:0] _legal_T_68 = {1'h0, _legal_T_67}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_69 = _legal_T_68 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_70 = _legal_T_69; // @[Parameters.scala:137:46] wire _legal_T_71 = _legal_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_72 = _legal_T_71; // @[Parameters.scala:684:54] wire _legal_T_132 = _legal_T_72; // @[Parameters.scala:684:54, :686:26] wire _legal_T_75 = _legal_T_74; // @[Parameters.scala:92:{33,38}] wire _legal_T_76 = _legal_T_75; // @[Parameters.scala:684:29] wire [31:0] _legal_T_77; // @[Parameters.scala:137:31] wire [32:0] _legal_T_78 = {1'h0, _legal_T_77}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_79 = _legal_T_78 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_80 = _legal_T_79; // @[Parameters.scala:137:46] wire _legal_T_81 = _legal_T_80 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_82 = {_tlb_io_resp_paddr[31:21], _tlb_io_resp_paddr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_83 = {1'h0, _legal_T_82}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_84 = _legal_T_83 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_85 = _legal_T_84; // @[Parameters.scala:137:46] wire _legal_T_86 = _legal_T_85 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_88 = {1'h0, _legal_T_87}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_89 = _legal_T_88 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_90 = _legal_T_89; // @[Parameters.scala:137:46] wire _legal_T_91 = _legal_T_90 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_92 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_93 = {1'h0, _legal_T_92}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_94 = _legal_T_93 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_95 = _legal_T_94; // @[Parameters.scala:137:46] wire _legal_T_96 = _legal_T_95 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_98 = {1'h0, _legal_T_97}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_99 = _legal_T_98 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_100 = _legal_T_99; // @[Parameters.scala:137:46] wire _legal_T_101 = _legal_T_100 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_103 = {1'h0, _legal_T_102}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_104 = _legal_T_103 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_105 = _legal_T_104; // @[Parameters.scala:137:46] wire _legal_T_106 = _legal_T_105 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_108 = {1'h0, _legal_T_107}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_109 = _legal_T_108 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_110 = _legal_T_109; // @[Parameters.scala:137:46] wire _legal_T_111 = _legal_T_110 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_113 = {1'h0, _legal_T_112}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_114 = _legal_T_113 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_115 = _legal_T_114; // @[Parameters.scala:137:46] wire _legal_T_116 = _legal_T_115 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_117 = _legal_T_81 \| _legal_T_86; // @[Parameters.scala:685:42] wire _legal_T_118 = _legal_T_117 \| _legal_T_91; // @[Parameters.scala:685:42] wire _legal_T_119 = _legal_T_118 \| _legal_T_96; // @[Parameters.scala:685:42] wire _legal_T_120 = _legal_T_119 \| _legal_T_101; // @[Parameters.scala:685:42] wire _legal_T_121 = _legal_T_120 \| _legal_T_106; // @[Parameters.scala:685:42] wire _legal_T_122 = _legal_T_121 \| _legal_T_111; // @[Parameters.scala:685:42] wire _legal_T_123 = _legal_T_122 \| _legal_T_116; // @[Parameters.scala:685:42] wire _legal_T_124 = _legal_T_76 & _legal_T_123; // @[Parameters.scala:684:{29,54}, :685:42] wire [32:0] _legal_T_127 = {1'h0, _legal_T_126}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_128 = _legal_T_127 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_129 = _legal_T_128; // @[Parameters.scala:137:46] wire _legal_T_130 = _legal_T_129 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_133 = _legal_T_132 \| _legal_T_124; // @[Parameters.scala:684:54, :686:26] wire legal_1 = _legal_T_133; // @[Parameters.scala:686:26] wire [31:0] _a_mask_T_1; // @[Misc.scala:222:10] wire [1:0] bundle_1_source; // @[Edges.scala:480:17] wire [31:0] bundle_1_address; // @[Edges.scala:480:17] wire [31:0] bundle_1_mask; // @[Edges.scala:480:17] wire [255:0] bundle_1_data; // @[Edges.scala:480:17] wire [4:0] _a_mask_sizeOH_shiftAmount_T_1 = _a_mask_sizeOH_T_3; // @[OneHot.scala:64:31] wire [2:0] a_mask_sizeOH_shiftAmount_1 = _a_mask_sizeOH_shiftAmount_T_1[2:0]; // @[OneHot.scala:64:{31,49}] wire [7:0] _a_mask_sizeOH_T_4 = 8'h1 << a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [4:0] _a_mask_sizeOH_T_5 = _a_mask_sizeOH_T_4[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] a_mask_sizeOH_1 = {_a_mask_sizeOH_T_5[4:1], 1'h1}; // @[OneHot.scala:65:27] wire a_mask_sub_sub_sub_sub_size_1 = a_mask_sizeOH_1[4]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _a_mask_sub_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire a_mask_sub_sub_sub_size_1 = a_mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_4 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_5 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_2_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_6 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_2_1_1 = a_mask_sub_sub_sub_sub_1_1_1 \| _a_mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_3_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_7 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_3_1_1 = a_mask_sub_sub_sub_sub_1_1_1 \| _a_mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_size_1 = a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_nbit_1 = ~a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_8 = a_mask_sub_sub_size_1 & a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_0_1_1 = a_mask_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_1_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_9 = a_mask_sub_sub_size_1 & a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_1_1_1 = a_mask_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_2_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_10 = a_mask_sub_sub_size_1 & a_mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_2_1_1 = a_mask_sub_sub_sub_1_1_1 \| _a_mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_3_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_11 = a_mask_sub_sub_size_1 & a_mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_3_1_1 = a_mask_sub_sub_sub_1_1_1 \| _a_mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_4_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_12 = a_mask_sub_sub_size_1 & a_mask_sub_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_4_1_1 = a_mask_sub_sub_sub_2_1_1 \| _a_mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_5_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_13 = a_mask_sub_sub_size_1 & a_mask_sub_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_5_1_1 = a_mask_sub_sub_sub_2_1_1 \| _a_mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_6_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_14 = a_mask_sub_sub_size_1 & a_mask_sub_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_6_1_1 = a_mask_sub_sub_sub_3_1_1 \| _a_mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_7_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_15 = a_mask_sub_sub_size_1 & a_mask_sub_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_7_1_1 = a_mask_sub_sub_sub_3_1_1 \| _a_mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_sub_size_1 = a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_nbit_1 = ~a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_16 = a_mask_sub_size_1 & a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_0_1_1 = a_mask_sub_sub_0_1_1 \| _a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire a_mask_sub_1_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_17 = a_mask_sub_size_1 & a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_1_1_1 = a_mask_sub_sub_0_1_1 \| _a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire a_mask_sub_2_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_18 = a_mask_sub_size_1 & a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_2_1_1 = a_mask_sub_sub_1_1_1 \| _a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire a_mask_sub_3_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_19 = a_mask_sub_size_1 & a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_3_1_1 = a_mask_sub_sub_1_1_1 \| _a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire a_mask_sub_4_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_20 = a_mask_sub_size_1 & a_mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_4_1_1 = a_mask_sub_sub_2_1_1 \| _a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire a_mask_sub_5_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_21 = a_mask_sub_size_1 & a_mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_5_1_1 = a_mask_sub_sub_2_1_1 \| _a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire a_mask_sub_6_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_22 = a_mask_sub_size_1 & a_mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_6_1_1 = a_mask_sub_sub_3_1_1 \| _a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire a_mask_sub_7_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_23 = a_mask_sub_size_1 & a_mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_7_1_1 = a_mask_sub_sub_3_1_1 \| _a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire a_mask_sub_8_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_24 = a_mask_sub_size_1 & a_mask_sub_8_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_8_1_1 = a_mask_sub_sub_4_1_1 \| _a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire a_mask_sub_9_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_25 = a_mask_sub_size_1 & a_mask_sub_9_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_9_1_1 = a_mask_sub_sub_4_1_1 \| _a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire a_mask_sub_10_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_26 = a_mask_sub_size_1 & a_mask_sub_10_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_10_1_1 = a_mask_sub_sub_5_1_1 \| _a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire a_mask_sub_11_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_27 = a_mask_sub_size_1 & a_mask_sub_11_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_11_1_1 = a_mask_sub_sub_5_1_1 \| _a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire a_mask_sub_12_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_28 = a_mask_sub_size_1 & a_mask_sub_12_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_12_1_1 = a_mask_sub_sub_6_1_1 \| _a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire a_mask_sub_13_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_29 = a_mask_sub_size_1 & a_mask_sub_13_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_13_1_1 = a_mask_sub_sub_6_1_1 \| _a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire a_mask_sub_14_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_30 = a_mask_sub_size_1 & a_mask_sub_14_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_14_1_1 = a_mask_sub_sub_7_1_1 \| _a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire a_mask_sub_15_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_31 = a_mask_sub_size_1 & a_mask_sub_15_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_15_1_1 = a_mask_sub_sub_7_1_1 \| _a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire a_mask_size_1 = a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_eq_32 = a_mask_sub_0_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_32 = a_mask_size_1 & a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_32 = a_mask_sub_0_1_1 \| _a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire a_mask_eq_33 = a_mask_sub_0_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_33 = a_mask_size_1 & a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_33 = a_mask_sub_0_1_1 \| _a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire a_mask_eq_34 = a_mask_sub_1_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_34 = a_mask_size_1 & a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_34 = a_mask_sub_1_1_1 \| _a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire a_mask_eq_35 = a_mask_sub_1_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_35 = a_mask_size_1 & a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_35 = a_mask_sub_1_1_1 \| _a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire a_mask_eq_36 = a_mask_sub_2_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_36 = a_mask_size_1 & a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_36 = a_mask_sub_2_1_1 \| _a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire a_mask_eq_37 = a_mask_sub_2_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_37 = a_mask_size_1 & a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_37 = a_mask_sub_2_1_1 \| _a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire a_mask_eq_38 = a_mask_sub_3_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_38 = a_mask_size_1 & a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_38 = a_mask_sub_3_1_1 \| _a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire a_mask_eq_39 = a_mask_sub_3_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_39 = a_mask_size_1 & a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_39 = a_mask_sub_3_1_1 \| _a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire a_mask_eq_40 = a_mask_sub_4_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_40 = a_mask_size_1 & a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_40 = a_mask_sub_4_1_1 \| _a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire a_mask_eq_41 = a_mask_sub_4_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_41 = a_mask_size_1 & a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_41 = a_mask_sub_4_1_1 \| _a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire a_mask_eq_42 = a_mask_sub_5_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_42 = a_mask_size_1 & a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_42 = a_mask_sub_5_1_1 \| _a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire a_mask_eq_43 = a_mask_sub_5_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_43 = a_mask_size_1 & a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_43 = a_mask_sub_5_1_1 \| _a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire a_mask_eq_44 = a_mask_sub_6_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_44 = a_mask_size_1 & a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_44 = a_mask_sub_6_1_1 \| _a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire a_mask_eq_45 = a_mask_sub_6_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_45 = a_mask_size_1 & a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_45 = a_mask_sub_6_1_1 \| _a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire a_mask_eq_46 = a_mask_sub_7_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_46 = a_mask_size_1 & a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_46 = a_mask_sub_7_1_1 \| _a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire a_mask_eq_47 = a_mask_sub_7_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_47 = a_mask_size_1 & a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_47 = a_mask_sub_7_1_1 \| _a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire a_mask_eq_48 = a_mask_sub_8_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_48 = a_mask_size_1 & a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_48 = a_mask_sub_8_1_1 \| _a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire a_mask_eq_49 = a_mask_sub_8_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_49 = a_mask_size_1 & a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_49 = a_mask_sub_8_1_1 \| _a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire a_mask_eq_50 = a_mask_sub_9_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_50 = a_mask_size_1 & a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_50 = a_mask_sub_9_1_1 \| _a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire a_mask_eq_51 = a_mask_sub_9_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_51 = a_mask_size_1 & a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_51 = a_mask_sub_9_1_1 \| _a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire a_mask_eq_52 = a_mask_sub_10_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_52 = a_mask_size_1 & a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_52 = a_mask_sub_10_1_1 \| _a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire a_mask_eq_53 = a_mask_sub_10_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_53 = a_mask_size_1 & a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_53 = a_mask_sub_10_1_1 \| _a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire a_mask_eq_54 = a_mask_sub_11_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_54 = a_mask_size_1 & a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_54 = a_mask_sub_11_1_1 \| _a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire a_mask_eq_55 = a_mask_sub_11_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_55 = a_mask_size_1 & a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_55 = a_mask_sub_11_1_1 \| _a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire a_mask_eq_56 = a_mask_sub_12_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_56 = a_mask_size_1 & a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_56 = a_mask_sub_12_1_1 \| _a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire a_mask_eq_57 = a_mask_sub_12_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_57 = a_mask_size_1 & a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_57 = a_mask_sub_12_1_1 \| _a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire a_mask_eq_58 = a_mask_sub_13_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_58 = a_mask_size_1 & a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_58 = a_mask_sub_13_1_1 \| _a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire a_mask_eq_59 = a_mask_sub_13_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_59 = a_mask_size_1 & a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_59 = a_mask_sub_13_1_1 \| _a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire a_mask_eq_60 = a_mask_sub_14_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_60 = a_mask_size_1 & a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_60 = a_mask_sub_14_1_1 \| _a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire a_mask_eq_61 = a_mask_sub_14_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_61 = a_mask_size_1 & a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_61 = a_mask_sub_14_1_1 \| _a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire a_mask_eq_62 = a_mask_sub_15_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_62 = a_mask_size_1 & a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_62 = a_mask_sub_15_1_1 \| _a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire a_mask_eq_63 = a_mask_sub_15_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_63 = a_mask_size_1 & a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_63 = a_mask_sub_15_1_1 \| _a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] a_mask_lo_lo_lo_lo_1 = {a_mask_acc_33, a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_lo_hi_1 = {a_mask_acc_35, a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_lo_1 = {a_mask_lo_lo_lo_hi_1, a_mask_lo_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo_1 = {a_mask_acc_37, a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_hi_hi_1 = {a_mask_acc_39, a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_hi_1 = {a_mask_lo_lo_hi_hi_1, a_mask_lo_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo_1 = {a_mask_lo_lo_hi_1, a_mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo_1 = {a_mask_acc_41, a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_lo_hi_1 = {a_mask_acc_43, a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_lo_1 = {a_mask_lo_hi_lo_hi_1, a_mask_lo_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo_1 = {a_mask_acc_45, a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_hi_hi_1 = {a_mask_acc_47, a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_hi_1 = {a_mask_lo_hi_hi_hi_1, a_mask_lo_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi_1 = {a_mask_lo_hi_hi_1, a_mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] a_mask_lo_1 = {a_mask_lo_hi_1, a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo_1 = {a_mask_acc_49, a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_lo_hi_1 = {a_mask_acc_51, a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_lo_1 = {a_mask_hi_lo_lo_hi_1, a_mask_hi_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo_1 = {a_mask_acc_53, a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_hi_hi_1 = {a_mask_acc_55, a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_hi_1 = {a_mask_hi_lo_hi_hi_1, a_mask_hi_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo_1 = {a_mask_hi_lo_hi_1, a_mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo_1 = {a_mask_acc_57, a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_lo_hi_1 = {a_mask_acc_59, a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_lo_1 = {a_mask_hi_hi_lo_hi_1, a_mask_hi_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo_1 = {a_mask_acc_61, a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_hi_hi_1 = {a_mask_acc_63, a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_hi_1 = {a_mask_hi_hi_hi_hi_1, a_mask_hi_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi_1 = {a_mask_hi_hi_hi_1, a_mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] a_mask_hi_1 = {a_mask_hi_hi_1, a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _a_mask_T_1 = {a_mask_hi_1, a_mask_lo_1}; // @[Misc.scala:222:10] assign bundle_1_mask = _a_mask_T_1; // @[Misc.scala:222:10] assign bundle_1_data = _T_31[255:0]; // @[Edges.scala:480:17, :489:15] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] wire _current_request_tag_has_response_space_T = _tags_for_issue_Q_io_deq_bits == 2'h0; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_1 = _Queue4_L2RespInternal_io_enq_ready & _current_request_tag_has_response_space_T; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_2 = _tags_for_issue_Q_io_deq_bits == 2'h1; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _current_request_tag_has_response_space_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_4 = _tags_for_issue_Q_io_deq_bits == 2'h2; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _current_request_tag_has_response_space_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_6 = &_tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _current_request_tag_has_response_space_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_8 = _current_request_tag_has_response_space_T_1 \| _current_request_tag_has_response_space_T_3; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_9 = _current_request_tag_has_response_space_T_8 \| _current_request_tag_has_response_space_T_5; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire current_request_tag_has_response_space = _current_request_tag_has_response_space_T_9 \| _current_request_tag_has_response_space_T_7; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire [63:0] _outstanding_req_addr_io_enq_bits_addrindex_T = {59'h0, request_input_bits_addr[4:0]}; // @[L2MemHelperLatencyInjection.scala:44:27, :200:73] wire _request_latency_injection_q_io_enq_valid_T = request_input_valid & tlb_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_1 = _request_latency_injection_q_io_enq_valid_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_2 = _request_latency_injection_q_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_3 = _request_latency_injection_q_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_4 = _request_latency_injection_q_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _request_input_ready_T = _request_latency_injection_q_io_enq_ready & tlb_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_1 = _request_input_ready_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_2 = _request_input_ready_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_input_ready_T_3 = _request_input_ready_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] assign _request_input_ready_T_4 = _request_input_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] assign request_input_ready = _request_input_ready_T_4; // @[Misc.scala:26:53] wire _T_45 = request_input_valid & _request_latency_injection_q_io_enq_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T; // @[Misc.scala:26:53] assign _outstanding_req_addr_io_enq_valid_T = _T_45; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T; // @[Misc.scala:26:53] assign _tags_for_issue_Q_io_deq_ready_T = _T_45; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_1 = _outstanding_req_addr_io_enq_valid_T & tlb_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_2 = _outstanding_req_addr_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_3 = _outstanding_req_addr_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_4 = _outstanding_req_addr_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_1 = _tags_for_issue_Q_io_deq_ready_T & tlb_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_2 = _tags_for_issue_Q_io_deq_ready_T_1 & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_3 = _tags_for_issue_Q_io_deq_ready_T_2 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_4 = _tags_for_issue_Q_io_deq_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:26:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:26:33, :27:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:27:38] wire _printf_T_1 = ~_printf_T; // @[annotations.scala:102:49] wire _printf_T_3 = ~_printf_T_2; // @[annotations.scala:102:49] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38] wire _selectQready_T = _response_latency_injection_q_io_deq_bits_source == 2'h0; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_1 = _Queue4_L2RespInternal_io_enq_ready & _selectQready_T; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_2 = _response_latency_injection_q_io_deq_bits_source == 2'h1; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _selectQready_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_4 = _response_latency_injection_q_io_deq_bits_source == 2'h2; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _selectQready_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_6 = &_response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _selectQready_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_8 = _selectQready_T_1 \| _selectQready_T_3; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_9 = _selectQready_T_8 \| _selectQready_T_5; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire selectQready = _selectQready_T_9 \| _selectQready_T_7; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _T_377 = selectQready & _response_latency_injection_q_io_deq_valid; // @[Misc.scala:26:53] wire tags_for_issue_Q_io_enq_valid = _T_377 \| _T_4; // @[Misc.scala:26:53] wire [1:0] tags_for_issue_Q_io_enq_bits = _T_377 ? _response_latency_injection_q_io_deq_bits_source : tags_init_reg[1:0]; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38] wire _response_latency_injection_q_io_deq_ready_T = selectQready & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_392 = _response_latency_injection_q_io_deq_valid & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_396 = _outstanding_req_addr_io_deq_bits_tag == 2'h0; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T = _T_396; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q = _T_396; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_1 = _Queue4_L2RespInternal_io_deq_valid & _queueValid_T; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_399 = _outstanding_req_addr_io_deq_bits_tag == 2'h1; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_2 = _T_399; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_1; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_1 = _T_399; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_3 = _Queue4_L2RespInternal_1_io_deq_valid & _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_402 = _outstanding_req_addr_io_deq_bits_tag == 2'h2; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_4 = _T_402; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_2; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_2 = _T_402; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_5 = _Queue4_L2RespInternal_2_io_deq_valid & _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_6 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_7 = _Queue4_L2RespInternal_3_io_deq_valid & _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_8 = _queueValid_T_1 \| _queueValid_T_3; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_9 = _queueValid_T_8 \| _queueValid_T_5; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire queueValid = _queueValid_T_9 \| _queueValid_T_7; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _outstanding_req_addr_io_deq_ready_T = queueValid; // @[Misc.scala:26:53] wire [255:0] resultdata_data; // @[L2MemHelperLatencyInjection.scala:300:20] wire [7:0] _GEN_12 = {_outstanding_req_addr_io_deq_bits_addrindex, 3'h0}; // @[L2MemHelperLatencyInjection.scala:91:36, :302:78] wire [7:0] _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_2 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_4 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_6 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [255:0] _resultdata_data_T_1 = _Queue4_L2RespInternal_io_deq_bits_data >> _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data = resultdata_is_current_q ? _resultdata_data_T_1 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_3 = _Queue4_L2RespInternal_1_io_deq_bits_data >> _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_1 = resultdata_is_current_q_1 ? _resultdata_data_T_3 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_5 = _Queue4_L2RespInternal_2_io_deq_bits_data >> _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_2 = resultdata_is_current_q_2 ? _resultdata_data_T_5 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire resultdata_is_current_q_3 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27, :299:31] wire [255:0] resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_7 = _Queue4_L2RespInternal_3_io_deq_bits_data >> _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_3 = resultdata_is_current_q_3 ? _resultdata_data_T_7 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] _resultdata_T = resultdata_data \| resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_1 = _resultdata_T \| resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign resultdata = _resultdata_T_1 \| resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign response_output_bits_data = resultdata; // @[L2MemHelperLatencyInjection.scala:53:29, :307:15] assign _response_output_valid_T = queueValid & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] assign response_output_valid = _response_output_valid_T; // @[Misc.scala:26:53] wire opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_38 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[5], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], chosen_oh : UInt<5>[1]} regreset lock_0 : UInt<5>, clock, reset, UInt<5>(0h0) node unassigned_lo = cat(io.in[1].valid, io.in[0].valid) node unassigned_hi_hi = cat(io.in[4].valid, io.in[3].valid) node unassigned_hi = cat(unassigned_hi_hi, io.in[2].valid) node _unassigned_T = cat(unassigned_hi, unassigned_lo) node _unassigned_T_1 = not(lock_0) node unassigned = and(_unassigned_T, _unassigned_T_1) regreset mask : UInt<5>, clock, reset, UInt<5>(0h0) wire choices : UInt<5>[1] node _sel_T = not(mask) node _sel_T_1 = and(unassigned, _sel_T) node _sel_T_2 = cat(unassigned, _sel_T_1) node _sel_T_3 = bits(_sel_T_2, 0, 0) node _sel_T_4 = bits(_sel_T_2, 1, 1) node _sel_T_5 = bits(_sel_T_2, 2, 2) node _sel_T_6 = bits(_sel_T_2, 3, 3) node _sel_T_7 = bits(_sel_T_2, 4, 4) node _sel_T_8 = bits(_sel_T_2, 5, 5) node _sel_T_9 = bits(_sel_T_2, 6, 6) node _sel_T_10 = bits(_sel_T_2, 7, 7) node _sel_T_11 = bits(_sel_T_2, 8, 8) node _sel_T_12 = bits(_sel_T_2, 9, 9) node _sel_T_13 = mux(_sel_T_12, UInt<10>(0h200), UInt<10>(0h0)) node _sel_T_14 = mux(_sel_T_11, UInt<10>(0h100), _sel_T_13) node _sel_T_15 = mux(_sel_T_10, UInt<10>(0h80), _sel_T_14) node _sel_T_16 = mux(_sel_T_9, UInt<10>(0h40), _sel_T_15) node _sel_T_17 = mux(_sel_T_8, UInt<10>(0h20), _sel_T_16) node _sel_T_18 = mux(_sel_T_7, UInt<10>(0h10), _sel_T_17) node _sel_T_19 = mux(_sel_T_6, UInt<10>(0h8), _sel_T_18) node _sel_T_20 = mux(_sel_T_5, UInt<10>(0h4), _sel_T_19) node _sel_T_21 = mux(_sel_T_4, UInt<10>(0h2), _sel_T_20) node sel = mux(_sel_T_3, UInt<10>(0h1), _sel_T_21) node _choices_0_T = shr(sel, 5) node _choices_0_T_1 = or(sel, _choices_0_T) connect choices[0], _choices_0_T_1 node _T = not(choices[0]) node _T_1 = and(unassigned, _T) node _T_2 = bits(_T_1, 0, 0) node _T_3 = bits(_T_1, 1, 1) node _T_4 = bits(_T_1, 2, 2) node _T_5 = bits(_T_1, 3, 3) node _T_6 = bits(_T_1, 4, 4) node _T_7 = mux(_T_6, UInt<5>(0h10), UInt<5>(0h0)) node _T_8 = mux(_T_5, UInt<5>(0h8), _T_7) node _T_9 = mux(_T_4, UInt<5>(0h4), _T_8) node _T_10 = mux(_T_3, UInt<5>(0h2), _T_9) node _T_11 = mux(_T_2, UInt<5>(0h1), _T_10) connect io.in[0].ready, UInt<1>(0h0) connect io.in[1].ready, UInt<1>(0h0) connect io.in[2].ready, UInt<1>(0h0) connect io.in[3].ready, UInt<1>(0h0) connect io.in[4].ready, UInt<1>(0h0) node in_tails_lo = cat(io.in[1].bits.tail, io.in[0].bits.tail) node in_tails_hi_hi = cat(io.in[4].bits.tail, io.in[3].bits.tail) node in_tails_hi = cat(in_tails_hi_hi, io.in[2].bits.tail) node in_tails = cat(in_tails_hi, in_tails_lo) node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T) node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2) node _in_valids_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_5 = and(io.in[2].valid, _in_valids_T_4) node _in_valids_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_7 = and(io.in[3].valid, _in_valids_T_6) node _in_valids_T_8 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_9 = and(io.in[4].valid, _in_valids_T_8) node in_valids_lo = cat(_in_valids_T_3, _in_valids_T_1) node in_valids_hi_hi = cat(_in_valids_T_9, _in_valids_T_7) node in_valids_hi = cat(in_valids_hi_hi, _in_valids_T_5) node in_valids = cat(in_valids_hi, in_valids_lo) node _chosen_T = and(in_valids, lock_0) node _chosen_T_1 = not(UInt<5>(0h0)) node _chosen_T_2 = and(_chosen_T, _chosen_T_1) node _chosen_T_3 = orr(_chosen_T_2) node chosen = mux(_chosen_T_3, lock_0, choices[0]) connect io.chosen_oh[0], chosen node _io_out_0_valid_T = and(in_valids, chosen) node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T) connect io.out[0].valid, _io_out_0_valid_T_1 node _io_out_0_bits_T = bits(chosen, 0, 0) node _io_out_0_bits_T_1 = bits(chosen, 1, 1) node _io_out_0_bits_T_2 = bits(chosen, 2, 2) node _io_out_0_bits_T_3 = bits(chosen, 3, 3) node _io_out_0_bits_T_4 = bits(chosen, 4, 4) wire _io_out_0_bits_WIRE : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>} node _io_out_0_bits_T_5 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_6 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_7 = mux(_io_out_0_bits_T_2, io.in[2].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_8 = mux(_io_out_0_bits_T_3, io.in[3].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_9 = mux(_io_out_0_bits_T_4, io.in[4].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_10 = or(_io_out_0_bits_T_5, _io_out_0_bits_T_6) node _io_out_0_bits_T_11 = or(_io_out_0_bits_T_10, _io_out_0_bits_T_7) node _io_out_0_bits_T_12 = or(_io_out_0_bits_T_11, _io_out_0_bits_T_8) node _io_out_0_bits_T_13 = or(_io_out_0_bits_T_12, _io_out_0_bits_T_9) wire _io_out_0_bits_WIRE_1 : UInt<1> connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_13 connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1 wire _io_out_0_bits_WIRE_2 : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _io_out_0_bits_WIRE_3 : UInt<1>[3] node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_15 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_16 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_17 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_19 = or(_io_out_0_bits_T_14, _io_out_0_bits_T_15) node _io_out_0_bits_T_20 = or(_io_out_0_bits_T_19, _io_out_0_bits_T_16) node _io_out_0_bits_T_21 = or(_io_out_0_bits_T_20, _io_out_0_bits_T_17) node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_21, _io_out_0_bits_T_18) wire _io_out_0_bits_WIRE_4 : UInt<1> connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_22 connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4 node _io_out_0_bits_T_23 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_24 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_25 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_26 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_27 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_28 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_24) node _io_out_0_bits_T_29 = or(_io_out_0_bits_T_28, _io_out_0_bits_T_25) node _io_out_0_bits_T_30 = or(_io_out_0_bits_T_29, _io_out_0_bits_T_26) node _io_out_0_bits_T_31 = or(_io_out_0_bits_T_30, _io_out_0_bits_T_27) wire _io_out_0_bits_WIRE_5 : UInt<1> connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_31 connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5 node _io_out_0_bits_T_32 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_33 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_34 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_35 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_36 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_37 = or(_io_out_0_bits_T_32, _io_out_0_bits_T_33) node _io_out_0_bits_T_38 = or(_io_out_0_bits_T_37, _io_out_0_bits_T_34) node _io_out_0_bits_T_39 = or(_io_out_0_bits_T_38, _io_out_0_bits_T_35) node _io_out_0_bits_T_40 = or(_io_out_0_bits_T_39, _io_out_0_bits_T_36) wire _io_out_0_bits_WIRE_6 : UInt<1> connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_40 connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6 connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3 wire _io_out_0_bits_WIRE_7 : UInt<1>[3] node _io_out_0_bits_T_41 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_42 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_43 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_44 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_45 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_46 = or(_io_out_0_bits_T_41, _io_out_0_bits_T_42) node _io_out_0_bits_T_47 = or(_io_out_0_bits_T_46, _io_out_0_bits_T_43) node _io_out_0_bits_T_48 = or(_io_out_0_bits_T_47, _io_out_0_bits_T_44) node _io_out_0_bits_T_49 = or(_io_out_0_bits_T_48, _io_out_0_bits_T_45) wire _io_out_0_bits_WIRE_8 : UInt<1> connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_49 connect _io_out_0_bits_WIRE_7[0], _io_out_0_bits_WIRE_8 node _io_out_0_bits_T_50 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_51 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_52 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_53 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_54 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_55 = or(_io_out_0_bits_T_50, _io_out_0_bits_T_51) node _io_out_0_bits_T_56 = or(_io_out_0_bits_T_55, _io_out_0_bits_T_52) node _io_out_0_bits_T_57 = or(_io_out_0_bits_T_56, _io_out_0_bits_T_53) node _io_out_0_bits_T_58 = or(_io_out_0_bits_T_57, _io_out_0_bits_T_54) wire _io_out_0_bits_WIRE_9 : UInt<1> connect _io_out_0_bits_WIRE_9, _io_out_0_bits_T_58 connect _io_out_0_bits_WIRE_7[1], _io_out_0_bits_WIRE_9 node _io_out_0_bits_T_59 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_60 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_61 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_62 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_63 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_64 = or(_io_out_0_bits_T_59, _io_out_0_bits_T_60) node _io_out_0_bits_T_65 = or(_io_out_0_bits_T_64, _io_out_0_bits_T_61) node _io_out_0_bits_T_66 = or(_io_out_0_bits_T_65, _io_out_0_bits_T_62) node _io_out_0_bits_T_67 = or(_io_out_0_bits_T_66, _io_out_0_bits_T_63) wire _io_out_0_bits_WIRE_10 : UInt<1> connect _io_out_0_bits_WIRE_10, _io_out_0_bits_T_67 connect _io_out_0_bits_WIRE_7[2], _io_out_0_bits_WIRE_10 connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_7 wire _io_out_0_bits_WIRE_11 : UInt<1>[3] node _io_out_0_bits_T_68 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_69 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_70 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_71 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_72 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_73 = or(_io_out_0_bits_T_68, _io_out_0_bits_T_69) node _io_out_0_bits_T_74 = or(_io_out_0_bits_T_73, _io_out_0_bits_T_70) node _io_out_0_bits_T_75 = or(_io_out_0_bits_T_74, _io_out_0_bits_T_71) node _io_out_0_bits_T_76 = or(_io_out_0_bits_T_75, _io_out_0_bits_T_72) wire _io_out_0_bits_WIRE_12 : UInt<1> connect _io_out_0_bits_WIRE_12, _io_out_0_bits_T_76 connect _io_out_0_bits_WIRE_11[0], _io_out_0_bits_WIRE_12 node _io_out_0_bits_T_77 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_78 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_79 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_80 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_81 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_82 = or(_io_out_0_bits_T_77, _io_out_0_bits_T_78) node _io_out_0_bits_T_83 = or(_io_out_0_bits_T_82, _io_out_0_bits_T_79) node _io_out_0_bits_T_84 = or(_io_out_0_bits_T_83, _io_out_0_bits_T_80) node _io_out_0_bits_T_85 = or(_io_out_0_bits_T_84, _io_out_0_bits_T_81) wire _io_out_0_bits_WIRE_13 : UInt<1> connect _io_out_0_bits_WIRE_13, _io_out_0_bits_T_85 connect _io_out_0_bits_WIRE_11[1], _io_out_0_bits_WIRE_13 node _io_out_0_bits_T_86 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_87 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_88 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_89 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_90 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_91 = or(_io_out_0_bits_T_86, _io_out_0_bits_T_87) node _io_out_0_bits_T_92 = or(_io_out_0_bits_T_91, _io_out_0_bits_T_88) node _io_out_0_bits_T_93 = or(_io_out_0_bits_T_92, _io_out_0_bits_T_89) node _io_out_0_bits_T_94 = or(_io_out_0_bits_T_93, _io_out_0_bits_T_90) wire _io_out_0_bits_WIRE_14 : UInt<1> connect _io_out_0_bits_WIRE_14, _io_out_0_bits_T_94 connect _io_out_0_bits_WIRE_11[2], _io_out_0_bits_WIRE_14 connect _io_out_0_bits_WIRE_2.`2`, _io_out_0_bits_WIRE_11 wire _io_out_0_bits_WIRE_15 : UInt<1>[3] node _io_out_0_bits_T_95 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_96 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_97 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_98 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_99 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_100 = or(_io_out_0_bits_T_95, _io_out_0_bits_T_96) node _io_out_0_bits_T_101 = or(_io_out_0_bits_T_100, _io_out_0_bits_T_97) node _io_out_0_bits_T_102 = or(_io_out_0_bits_T_101, _io_out_0_bits_T_98) node _io_out_0_bits_T_103 = or(_io_out_0_bits_T_102, _io_out_0_bits_T_99) wire _io_out_0_bits_WIRE_16 : UInt<1> connect _io_out_0_bits_WIRE_16, _io_out_0_bits_T_103 connect _io_out_0_bits_WIRE_15[0], _io_out_0_bits_WIRE_16 node _io_out_0_bits_T_104 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[1], UInt<1>(0h0)) node _io_out_0_bits_T_105 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[1], UInt<1>(0h0)) node _io_out_0_bits_T_106 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[1], UInt<1>(0h0)) node _io_out_0_bits_T_107 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[1], UInt<1>(0h0)) node _io_out_0_bits_T_108 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`3`[1], UInt<1>(0h0)) node _io_out_0_bits_T_109 = or(_io_out_0_bits_T_104, _io_out_0_bits_T_105) node _io_out_0_bits_T_110 = or(_io_out_0_bits_T_109, _io_out_0_bits_T_106) node _io_out_0_bits_T_111 = or(_io_out_0_bits_T_110, _io_out_0_bits_T_107) node _io_out_0_bits_T_112 = or(_io_out_0_bits_T_111, _io_out_0_bits_T_108) wire _io_out_0_bits_WIRE_17 : UInt<1> connect _io_out_0_bits_WIRE_17, _io_out_0_bits_T_112 connect _io_out_0_bits_WIRE_15[1], _io_out_0_bits_WIRE_17 node _io_out_0_bits_T_113 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[2], UInt<1>(0h0)) node _io_out_0_bits_T_114 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[2], UInt<1>(0h0)) node _io_out_0_bits_T_115 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[2], UInt<1>(0h0)) node _io_out_0_bits_T_116 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[2], UInt<1>(0h0)) node _io_out_0_bits_T_117 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`3`[2], UInt<1>(0h0)) node _io_out_0_bits_T_118 = or(_io_out_0_bits_T_113, _io_out_0_bits_T_114) node _io_out_0_bits_T_119 = or(_io_out_0_bits_T_118, _io_out_0_bits_T_115) node _io_out_0_bits_T_120 = or(_io_out_0_bits_T_119, _io_out_0_bits_T_116) node _io_out_0_bits_T_121 = or(_io_out_0_bits_T_120, _io_out_0_bits_T_117) wire _io_out_0_bits_WIRE_18 : UInt<1> connect _io_out_0_bits_WIRE_18, _io_out_0_bits_T_121 connect _io_out_0_bits_WIRE_15[2], _io_out_0_bits_WIRE_18 connect _io_out_0_bits_WIRE_2.`3`, _io_out_0_bits_WIRE_15 wire _io_out_0_bits_WIRE_19 : UInt<1>[1] node _io_out_0_bits_T_122 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_123 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_124 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_125 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_126 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_127 = or(_io_out_0_bits_T_122, _io_out_0_bits_T_123) node _io_out_0_bits_T_128 = or(_io_out_0_bits_T_127, _io_out_0_bits_T_124) node _io_out_0_bits_T_129 = or(_io_out_0_bits_T_128, _io_out_0_bits_T_125) node _io_out_0_bits_T_130 = or(_io_out_0_bits_T_129, _io_out_0_bits_T_126) wire _io_out_0_bits_WIRE_20 : UInt<1> connect _io_out_0_bits_WIRE_20, _io_out_0_bits_T_130 connect _io_out_0_bits_WIRE_19[0], _io_out_0_bits_WIRE_20 connect _io_out_0_bits_WIRE_2.`4`, _io_out_0_bits_WIRE_19 wire _io_out_0_bits_WIRE_21 : UInt<1>[1] node _io_out_0_bits_T_131 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_132 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_133 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_134 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_135 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_136 = or(_io_out_0_bits_T_131, _io_out_0_bits_T_132) node _io_out_0_bits_T_137 = or(_io_out_0_bits_T_136, _io_out_0_bits_T_133) node _io_out_0_bits_T_138 = or(_io_out_0_bits_T_137, _io_out_0_bits_T_134) node _io_out_0_bits_T_139 = or(_io_out_0_bits_T_138, _io_out_0_bits_T_135) wire _io_out_0_bits_WIRE_22 : UInt<1> connect _io_out_0_bits_WIRE_22, _io_out_0_bits_T_139 connect _io_out_0_bits_WIRE_21[0], _io_out_0_bits_WIRE_22 connect _io_out_0_bits_WIRE_2.`5`, _io_out_0_bits_WIRE_21 connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2 connect io.out[0].bits, _io_out_0_bits_WIRE node _T_12 = bits(chosen, 0, 0) node _T_13 = and(_T_12, io.out[0].ready) when _T_13 : connect io.in[0].ready, UInt<1>(0h1) node _T_14 = bits(chosen, 1, 1) node _T_15 = and(_T_14, io.out[0].ready) when _T_15 : connect io.in[1].ready, UInt<1>(0h1) node _T_16 = bits(chosen, 2, 2) node _T_17 = and(_T_16, io.out[0].ready) when _T_17 : connect io.in[2].ready, UInt<1>(0h1) node _T_18 = bits(chosen, 3, 3) node _T_19 = and(_T_18, io.out[0].ready) when _T_19 : connect io.in[3].ready, UInt<1>(0h1) node _T_20 = bits(chosen, 4, 4) node _T_21 = and(_T_20, io.out[0].ready) when _T_21 : connect io.in[4].ready, UInt<1>(0h1) node _T_22 = or(UInt<5>(0h0), chosen) node _T_23 = and(io.out[0].ready, io.out[0].valid) when _T_23 : node _lock_0_T = not(in_tails) node _lock_0_T_1 = and(chosen, _lock_0_T) connect lock_0, _lock_0_T_1 node _T_24 = and(io.out[0].ready, io.out[0].valid) when _T_24 : node _mask_T = shr(io.chosen_oh[0], 0) node _mask_T_1 = shr(io.chosen_oh[0], 1) node _mask_T_2 = shr(io.chosen_oh[0], 2) node _mask_T_3 = shr(io.chosen_oh[0], 3) node _mask_T_4 = shr(io.chosen_oh[0], 4) node _mask_T_5 = or(_mask_T, _mask_T_1) node _mask_T_6 = or(_mask_T_5, _mask_T_2) node _mask_T_7 = or(_mask_T_6, _mask_T_3) node _mask_T_8 = or(_mask_T_7, _mask_T_4) connect mask, _mask_T_8 else : node _mask_T_9 = not(mask) node _mask_T_10 = eq(_mask_T_9, UInt<1>(0h0)) node _mask_T_11 = shl(mask, 1) node _mask_T_12 = or(_mask_T_11, UInt<1>(0h1)) node _mask_T_13 = mux(_mask_T_10, UInt<1>(0h0), _mask_T_12) connect mask, _mask_T_13	module SwitchArbiter_38( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_3_ready, // @[SwitchAllocator.scala:18:14] input io_in_3_valid, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_4_ready, // @[SwitchAllocator.scala:18:14] input io_in_4_valid, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_tail, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [4:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [4:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [4:0] unassigned = {io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [4:0] mask; // @[SwitchAllocator.scala:27:21] wire [4:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [9:0] sel = _sel_T_1[0] ? 10'h1 : _sel_T_1[1] ? 10'h2 : _sel_T_1[2] ? 10'h4 : _sel_T_1[3] ? 10'h8 : _sel_T_1[4] ? 10'h10 : unassigned[0] ? 10'h20 : unassigned[1] ? 10'h40 : unassigned[2] ? 10'h80 : unassigned[3] ? 10'h100 : {unassigned[4], 9'h0}; // @[OneHot.scala:85:71] wire [4:0] in_valids = {io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [4:0] chosen = (\|(in_valids & lock_0)) ? lock_0 : sel[4:0] \| sel[9:5]; // @[Mux.scala:50:70] wire [4:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire [3:0] _GEN = chosen[3:0] \| chosen[4:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [2:0] _GEN_0 = _GEN[2:0] \| chosen[4:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [1:0] _GEN_1 = _GEN_0[1:0] \| chosen[4:3]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 5'h0; // @[SwitchAllocator.scala:24:38] mask <= 5'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (\|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}] lock_0 <= chosen & ~{io_in_4_bits_tail, io_in_3_bits_tail, io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= (\|_io_out_0_valid_T) ? {chosen[4], _GEN[3], _GEN_0[2], _GEN_1[1], _GEN_1[0] \| chosen[4]} : (&mask) ? 5'h0 : {mask[3:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,55,71}, :60:{10,16,23,49}] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module SourceE_3 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} wire e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} inst io_e_q of Queue2_TLBundleE_a32d64s4k3z3c_3 connect io_e_q.clock, clock connect io_e_q.reset, reset connect io_e_q.io.enq.valid, e.valid connect io_e_q.io.enq.bits.sink, e.bits.sink connect e.ready, io_e_q.io.enq.ready connect io.e.bits, io_e_q.io.deq.bits connect io.e.valid, io_e_q.io.deq.valid connect io_e_q.io.deq.ready, io.e.ready connect io.req.ready, e.ready connect e.valid, io.req.valid connect e.bits.sink, io.req.bits.sink	module SourceE_3( // @[SourceE.scala:29:7] input clock, // @[SourceE.scala:29:7] input reset, // @[SourceE.scala:29:7] output io_req_ready, // @[SourceE.scala:31:14] input io_req_valid, // @[SourceE.scala:31:14] input [2:0] io_req_bits_sink, // @[SourceE.scala:31:14] output io_e_valid, // @[SourceE.scala:31:14] output [2:0] io_e_bits_sink // @[SourceE.scala:31:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceE.scala:29:7] wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceE.scala:29:7] wire io_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire e_ready; // @[SourceE.scala:39:15] wire e_valid = io_req_valid_0; // @[SourceE.scala:29:7, :39:15] wire [2:0] e_bits_sink = io_req_bits_sink_0; // @[SourceE.scala:29:7, :39:15] wire io_req_ready_0; // @[SourceE.scala:29:7] wire [2:0] io_e_bits_sink_0; // @[SourceE.scala:29:7] wire io_e_valid_0; // @[SourceE.scala:29:7] assign io_req_ready_0 = e_ready; // @[SourceE.scala:29:7, :39:15] Queue2_TLBundleE_a32d64s4k3z3c_3 io_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (e_ready), .io_enq_valid (e_valid), // @[SourceE.scala:39:15] .io_enq_bits_sink (e_bits_sink), // @[SourceE.scala:39:15] .io_deq_valid (io_e_valid_0), .io_deq_bits_sink (io_e_bits_sink_0) ); // @[Decoupled.scala:362:21] assign io_req_ready = io_req_ready_0; // @[SourceE.scala:29:7] assign io_e_valid = io_e_valid_0; // @[SourceE.scala:29:7] assign io_e_bits_sink = io_e_bits_sink_0; // @[SourceE.scala:29:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_7 : input clock : Clock input reset : Reset output auto : { } skip	module TLBuffer_7( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset // @[Buffer.scala:40:9] ); endmodule
Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_11 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[5], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], chosen_oh : UInt<5>[1]} regreset lock_0 : UInt<5>, clock, reset, UInt<5>(0h0) node unassigned_lo = cat(io.in[1].valid, io.in[0].valid) node unassigned_hi_hi = cat(io.in[4].valid, io.in[3].valid) node unassigned_hi = cat(unassigned_hi_hi, io.in[2].valid) node _unassigned_T = cat(unassigned_hi, unassigned_lo) node _unassigned_T_1 = not(lock_0) node unassigned = and(_unassigned_T, _unassigned_T_1) regreset mask : UInt<5>, clock, reset, UInt<5>(0h0) wire choices : UInt<5>[1] node _sel_T = not(mask) node _sel_T_1 = and(unassigned, _sel_T) node _sel_T_2 = cat(unassigned, _sel_T_1) node _sel_T_3 = bits(_sel_T_2, 0, 0) node _sel_T_4 = bits(_sel_T_2, 1, 1) node _sel_T_5 = bits(_sel_T_2, 2, 2) node _sel_T_6 = bits(_sel_T_2, 3, 3) node _sel_T_7 = bits(_sel_T_2, 4, 4) node _sel_T_8 = bits(_sel_T_2, 5, 5) node _sel_T_9 = bits(_sel_T_2, 6, 6) node _sel_T_10 = bits(_sel_T_2, 7, 7) node _sel_T_11 = bits(_sel_T_2, 8, 8) node _sel_T_12 = bits(_sel_T_2, 9, 9) node _sel_T_13 = mux(_sel_T_12, UInt<10>(0h200), UInt<10>(0h0)) node _sel_T_14 = mux(_sel_T_11, UInt<10>(0h100), _sel_T_13) node _sel_T_15 = mux(_sel_T_10, UInt<10>(0h80), _sel_T_14) node _sel_T_16 = mux(_sel_T_9, UInt<10>(0h40), _sel_T_15) node _sel_T_17 = mux(_sel_T_8, UInt<10>(0h20), _sel_T_16) node _sel_T_18 = mux(_sel_T_7, UInt<10>(0h10), _sel_T_17) node _sel_T_19 = mux(_sel_T_6, UInt<10>(0h8), _sel_T_18) node _sel_T_20 = mux(_sel_T_5, UInt<10>(0h4), _sel_T_19) node _sel_T_21 = mux(_sel_T_4, UInt<10>(0h2), _sel_T_20) node sel = mux(_sel_T_3, UInt<10>(0h1), _sel_T_21) node _choices_0_T = shr(sel, 5) node _choices_0_T_1 = or(sel, _choices_0_T) connect choices[0], _choices_0_T_1 node _T = not(choices[0]) node _T_1 = and(unassigned, _T) node _T_2 = bits(_T_1, 0, 0) node _T_3 = bits(_T_1, 1, 1) node _T_4 = bits(_T_1, 2, 2) node _T_5 = bits(_T_1, 3, 3) node _T_6 = bits(_T_1, 4, 4) node _T_7 = mux(_T_6, UInt<5>(0h10), UInt<5>(0h0)) node _T_8 = mux(_T_5, UInt<5>(0h8), _T_7) node _T_9 = mux(_T_4, UInt<5>(0h4), _T_8) node _T_10 = mux(_T_3, UInt<5>(0h2), _T_9) node _T_11 = mux(_T_2, UInt<5>(0h1), _T_10) connect io.in[0].ready, UInt<1>(0h0) connect io.in[1].ready, UInt<1>(0h0) connect io.in[2].ready, UInt<1>(0h0) connect io.in[3].ready, UInt<1>(0h0) connect io.in[4].ready, UInt<1>(0h0) node in_tails_lo = cat(io.in[1].bits.tail, io.in[0].bits.tail) node in_tails_hi_hi = cat(io.in[4].bits.tail, io.in[3].bits.tail) node in_tails_hi = cat(in_tails_hi_hi, io.in[2].bits.tail) node in_tails = cat(in_tails_hi, in_tails_lo) node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T) node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2) node _in_valids_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_5 = and(io.in[2].valid, _in_valids_T_4) node _in_valids_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_7 = and(io.in[3].valid, _in_valids_T_6) node _in_valids_T_8 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_9 = and(io.in[4].valid, _in_valids_T_8) node in_valids_lo = cat(_in_valids_T_3, _in_valids_T_1) node in_valids_hi_hi = cat(_in_valids_T_9, _in_valids_T_7) node in_valids_hi = cat(in_valids_hi_hi, _in_valids_T_5) node in_valids = cat(in_valids_hi, in_valids_lo) node _chosen_T = and(in_valids, lock_0) node _chosen_T_1 = not(UInt<5>(0h0)) node _chosen_T_2 = and(_chosen_T, _chosen_T_1) node _chosen_T_3 = orr(_chosen_T_2) node chosen = mux(_chosen_T_3, lock_0, choices[0]) connect io.chosen_oh[0], chosen node _io_out_0_valid_T = and(in_valids, chosen) node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T) connect io.out[0].valid, _io_out_0_valid_T_1 node _io_out_0_bits_T = bits(chosen, 0, 0) node _io_out_0_bits_T_1 = bits(chosen, 1, 1) node _io_out_0_bits_T_2 = bits(chosen, 2, 2) node _io_out_0_bits_T_3 = bits(chosen, 3, 3) node _io_out_0_bits_T_4 = bits(chosen, 4, 4) wire _io_out_0_bits_WIRE : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>} node _io_out_0_bits_T_5 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_6 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_7 = mux(_io_out_0_bits_T_2, io.in[2].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_8 = mux(_io_out_0_bits_T_3, io.in[3].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_9 = mux(_io_out_0_bits_T_4, io.in[4].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_10 = or(_io_out_0_bits_T_5, _io_out_0_bits_T_6) node _io_out_0_bits_T_11 = or(_io_out_0_bits_T_10, _io_out_0_bits_T_7) node _io_out_0_bits_T_12 = or(_io_out_0_bits_T_11, _io_out_0_bits_T_8) node _io_out_0_bits_T_13 = or(_io_out_0_bits_T_12, _io_out_0_bits_T_9) wire _io_out_0_bits_WIRE_1 : UInt<1> connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_13 connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1 wire _io_out_0_bits_WIRE_2 : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _io_out_0_bits_WIRE_3 : UInt<1>[3] node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_15 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_16 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_17 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_19 = or(_io_out_0_bits_T_14, _io_out_0_bits_T_15) node _io_out_0_bits_T_20 = or(_io_out_0_bits_T_19, _io_out_0_bits_T_16) node _io_out_0_bits_T_21 = or(_io_out_0_bits_T_20, _io_out_0_bits_T_17) node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_21, _io_out_0_bits_T_18) wire _io_out_0_bits_WIRE_4 : UInt<1> connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_22 connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4 node _io_out_0_bits_T_23 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_24 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_25 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_26 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_27 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_28 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_24) node _io_out_0_bits_T_29 = or(_io_out_0_bits_T_28, _io_out_0_bits_T_25) node _io_out_0_bits_T_30 = or(_io_out_0_bits_T_29, _io_out_0_bits_T_26) node _io_out_0_bits_T_31 = or(_io_out_0_bits_T_30, _io_out_0_bits_T_27) wire _io_out_0_bits_WIRE_5 : UInt<1> connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_31 connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5 node _io_out_0_bits_T_32 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_33 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_34 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_35 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_36 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_37 = or(_io_out_0_bits_T_32, _io_out_0_bits_T_33) node _io_out_0_bits_T_38 = or(_io_out_0_bits_T_37, _io_out_0_bits_T_34) node _io_out_0_bits_T_39 = or(_io_out_0_bits_T_38, _io_out_0_bits_T_35) node _io_out_0_bits_T_40 = or(_io_out_0_bits_T_39, _io_out_0_bits_T_36) wire _io_out_0_bits_WIRE_6 : UInt<1> connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_40 connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6 connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3 wire _io_out_0_bits_WIRE_7 : UInt<1>[3] node _io_out_0_bits_T_41 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_42 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_43 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_44 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_45 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_46 = or(_io_out_0_bits_T_41, _io_out_0_bits_T_42) node _io_out_0_bits_T_47 = or(_io_out_0_bits_T_46, _io_out_0_bits_T_43) node _io_out_0_bits_T_48 = or(_io_out_0_bits_T_47, _io_out_0_bits_T_44) node _io_out_0_bits_T_49 = or(_io_out_0_bits_T_48, _io_out_0_bits_T_45) wire _io_out_0_bits_WIRE_8 : UInt<1> connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_49 connect _io_out_0_bits_WIRE_7[0], _io_out_0_bits_WIRE_8 node _io_out_0_bits_T_50 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_51 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_52 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_53 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_54 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_55 = or(_io_out_0_bits_T_50, _io_out_0_bits_T_51) node _io_out_0_bits_T_56 = or(_io_out_0_bits_T_55, _io_out_0_bits_T_52) node _io_out_0_bits_T_57 = or(_io_out_0_bits_T_56, _io_out_0_bits_T_53) node _io_out_0_bits_T_58 = or(_io_out_0_bits_T_57, _io_out_0_bits_T_54) wire _io_out_0_bits_WIRE_9 : UInt<1> connect _io_out_0_bits_WIRE_9, _io_out_0_bits_T_58 connect _io_out_0_bits_WIRE_7[1], _io_out_0_bits_WIRE_9 node _io_out_0_bits_T_59 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_60 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_61 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_62 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_63 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_64 = or(_io_out_0_bits_T_59, _io_out_0_bits_T_60) node _io_out_0_bits_T_65 = or(_io_out_0_bits_T_64, _io_out_0_bits_T_61) node _io_out_0_bits_T_66 = or(_io_out_0_bits_T_65, _io_out_0_bits_T_62) node _io_out_0_bits_T_67 = or(_io_out_0_bits_T_66, _io_out_0_bits_T_63) wire _io_out_0_bits_WIRE_10 : UInt<1> connect _io_out_0_bits_WIRE_10, _io_out_0_bits_T_67 connect _io_out_0_bits_WIRE_7[2], _io_out_0_bits_WIRE_10 connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_7 wire _io_out_0_bits_WIRE_11 : UInt<1>[3] node _io_out_0_bits_T_68 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_69 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_70 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_71 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_72 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_73 = or(_io_out_0_bits_T_68, _io_out_0_bits_T_69) node _io_out_0_bits_T_74 = or(_io_out_0_bits_T_73, _io_out_0_bits_T_70) node _io_out_0_bits_T_75 = or(_io_out_0_bits_T_74, _io_out_0_bits_T_71) node _io_out_0_bits_T_76 = or(_io_out_0_bits_T_75, _io_out_0_bits_T_72) wire _io_out_0_bits_WIRE_12 : UInt<1> connect _io_out_0_bits_WIRE_12, _io_out_0_bits_T_76 connect _io_out_0_bits_WIRE_11[0], _io_out_0_bits_WIRE_12 node _io_out_0_bits_T_77 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_78 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_79 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_80 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_81 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_82 = or(_io_out_0_bits_T_77, _io_out_0_bits_T_78) node _io_out_0_bits_T_83 = or(_io_out_0_bits_T_82, _io_out_0_bits_T_79) node _io_out_0_bits_T_84 = or(_io_out_0_bits_T_83, _io_out_0_bits_T_80) node _io_out_0_bits_T_85 = or(_io_out_0_bits_T_84, _io_out_0_bits_T_81) wire _io_out_0_bits_WIRE_13 : UInt<1> connect _io_out_0_bits_WIRE_13, _io_out_0_bits_T_85 connect _io_out_0_bits_WIRE_11[1], _io_out_0_bits_WIRE_13 node _io_out_0_bits_T_86 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_87 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_88 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_89 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_90 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_91 = or(_io_out_0_bits_T_86, _io_out_0_bits_T_87) node _io_out_0_bits_T_92 = or(_io_out_0_bits_T_91, _io_out_0_bits_T_88) node _io_out_0_bits_T_93 = or(_io_out_0_bits_T_92, _io_out_0_bits_T_89) node _io_out_0_bits_T_94 = or(_io_out_0_bits_T_93, _io_out_0_bits_T_90) wire _io_out_0_bits_WIRE_14 : UInt<1> connect _io_out_0_bits_WIRE_14, _io_out_0_bits_T_94 connect _io_out_0_bits_WIRE_11[2], _io_out_0_bits_WIRE_14 connect _io_out_0_bits_WIRE_2.`2`, _io_out_0_bits_WIRE_11 wire _io_out_0_bits_WIRE_15 : UInt<1>[1] node _io_out_0_bits_T_95 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_96 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_97 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_98 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_99 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_100 = or(_io_out_0_bits_T_95, _io_out_0_bits_T_96) node _io_out_0_bits_T_101 = or(_io_out_0_bits_T_100, _io_out_0_bits_T_97) node _io_out_0_bits_T_102 = or(_io_out_0_bits_T_101, _io_out_0_bits_T_98) node _io_out_0_bits_T_103 = or(_io_out_0_bits_T_102, _io_out_0_bits_T_99) wire _io_out_0_bits_WIRE_16 : UInt<1> connect _io_out_0_bits_WIRE_16, _io_out_0_bits_T_103 connect _io_out_0_bits_WIRE_15[0], _io_out_0_bits_WIRE_16 connect _io_out_0_bits_WIRE_2.`3`, _io_out_0_bits_WIRE_15 connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2 connect io.out[0].bits, _io_out_0_bits_WIRE node _T_12 = bits(chosen, 0, 0) node _T_13 = and(_T_12, io.out[0].ready) when _T_13 : connect io.in[0].ready, UInt<1>(0h1) node _T_14 = bits(chosen, 1, 1) node _T_15 = and(_T_14, io.out[0].ready) when _T_15 : connect io.in[1].ready, UInt<1>(0h1) node _T_16 = bits(chosen, 2, 2) node _T_17 = and(_T_16, io.out[0].ready) when _T_17 : connect io.in[2].ready, UInt<1>(0h1) node _T_18 = bits(chosen, 3, 3) node _T_19 = and(_T_18, io.out[0].ready) when _T_19 : connect io.in[3].ready, UInt<1>(0h1) node _T_20 = bits(chosen, 4, 4) node _T_21 = and(_T_20, io.out[0].ready) when _T_21 : connect io.in[4].ready, UInt<1>(0h1) node _T_22 = or(UInt<5>(0h0), chosen) node _T_23 = and(io.out[0].ready, io.out[0].valid) when _T_23 : node _lock_0_T = not(in_tails) node _lock_0_T_1 = and(chosen, _lock_0_T) connect lock_0, _lock_0_T_1 node _T_24 = and(io.out[0].ready, io.out[0].valid) when _T_24 : node _mask_T = shr(io.chosen_oh[0], 0) node _mask_T_1 = shr(io.chosen_oh[0], 1) node _mask_T_2 = shr(io.chosen_oh[0], 2) node _mask_T_3 = shr(io.chosen_oh[0], 3) node _mask_T_4 = shr(io.chosen_oh[0], 4) node _mask_T_5 = or(_mask_T, _mask_T_1) node _mask_T_6 = or(_mask_T_5, _mask_T_2) node _mask_T_7 = or(_mask_T_6, _mask_T_3) node _mask_T_8 = or(_mask_T_7, _mask_T_4) connect mask, _mask_T_8 else : node _mask_T_9 = not(mask) node _mask_T_10 = eq(_mask_T_9, UInt<1>(0h0)) node _mask_T_11 = shl(mask, 1) node _mask_T_12 = or(_mask_T_11, UInt<1>(0h1)) node _mask_T_13 = mux(_mask_T_10, UInt<1>(0h0), _mask_T_12) connect mask, _mask_T_13	module SwitchArbiter_11( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_3_ready, // @[SwitchAllocator.scala:18:14] input io_in_3_valid, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_4_ready, // @[SwitchAllocator.scala:18:14] input io_in_4_valid, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_tail, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [4:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [4:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [4:0] unassigned = {io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [4:0] mask; // @[SwitchAllocator.scala:27:21] wire [4:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [9:0] sel = _sel_T_1[0] ? 10'h1 : _sel_T_1[1] ? 10'h2 : _sel_T_1[2] ? 10'h4 : _sel_T_1[3] ? 10'h8 : _sel_T_1[4] ? 10'h10 : unassigned[0] ? 10'h20 : unassigned[1] ? 10'h40 : unassigned[2] ? 10'h80 : unassigned[3] ? 10'h100 : {unassigned[4], 9'h0}; // @[OneHot.scala:85:71] wire [4:0] in_valids = {io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [4:0] chosen = (\|(in_valids & lock_0)) ? lock_0 : sel[4:0] \| sel[9:5]; // @[Mux.scala:50:70] wire [4:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire [3:0] _GEN = chosen[3:0] \| chosen[4:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [2:0] _GEN_0 = _GEN[2:0] \| chosen[4:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [1:0] _GEN_1 = _GEN_0[1:0] \| chosen[4:3]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 5'h0; // @[SwitchAllocator.scala:24:38] mask <= 5'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (\|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}] lock_0 <= chosen & ~{io_in_4_bits_tail, io_in_3_bits_tail, io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= (\|_io_out_0_valid_T) ? {chosen[4], _GEN[3], _GEN_0[2], _GEN_1[1], _GEN_1[0] \| chosen[4]} : (&mask) ? 5'h0 : {mask[3:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,55,71}, :60:{10,16,23,49}] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module Tile_218 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_474 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_218( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_474 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module StreamReaderCore : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, spaddr : UInt<14>, is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, len : UInt<16>, repeats : UInt<16>, pixel_repeats : UInt<8>, block_stride : UInt<16>, cmd_id : UInt<8>}}, reserve : { valid : UInt<1>, flip ready : UInt<1>, flip xactid : UInt<6>, entry : { shift : UInt<6>, addr : UInt<14>, is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<8>, len : UInt<16>, block_stride : UInt<16>, spad_row_offset : UInt<9>, lg_len_req : UInt<3>, bytes_to_read : UInt<7>, cmd_id : UInt<3>}}, beatData : { flip ready : UInt<1>, valid : UInt<1>, bits : { xactid : UInt<6>, data : UInt<128>, lg_len_req : UInt<3>, last : UInt<1>}}, tlb : { req : { valid : UInt<1>, bits : { tlb_req : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, flip resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}}, flip flush : UInt<1>, counter : { event_signal : UInt<1>[45], external_values : UInt<32>[8], flip external_reset : UInt<1>}} wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut regreset state : UInt<1>, clock, reset, UInt<1>(0h0) reg req : { vaddr : UInt<40>, spaddr : UInt<14>, is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, len : UInt<16>, repeats : UInt<16>, pixel_repeats : UInt<8>, block_stride : UInt<16>, cmd_id : UInt<8>}, clock reg bytesRequested : UInt<6>, clock node _bytesLeft_T = mul(req.len, UInt<3>(0h4)) node _bytesLeft_T_1 = mul(req.len, UInt<1>(0h1)) node _bytesLeft_T_2 = mux(req.has_acc_bitwidth, _bytesLeft_T, _bytesLeft_T_1) node _bytesLeft_T_3 = sub(_bytesLeft_T_2, bytesRequested) node bytesLeft = tail(_bytesLeft_T_3, 1) node _state_machine_ready_for_req_T = eq(state, UInt<1>(0h0)) wire state_machine_ready_for_req : UInt<1> connect state_machine_ready_for_req, _state_machine_ready_for_req_T connect io.req.ready, state_machine_ready_for_req node _read_packets_vaddr_aligned_to_size_T = bits(req.vaddr, 38, 4) node read_packets_vaddr_aligned_to_size = cat(_read_packets_vaddr_aligned_to_size_T, UInt<4>(0h0)) node read_packets_vaddr_offset = bits(req.vaddr, 3, 0) wire read_packets_0 : { size : UInt<7>, lg_size : UInt<3>, bytes_read : UInt<7>, shift : UInt<6>, vaddr : UInt<39>} connect read_packets_0.size, UInt<5>(0h10) connect read_packets_0.lg_size, UInt<3>(0h4) node _read_packets_packet_bytes_read_T = sub(UInt<5>(0h10), read_packets_vaddr_offset) node _read_packets_packet_bytes_read_T_1 = tail(_read_packets_packet_bytes_read_T, 1) node _read_packets_packet_bytes_read_T_2 = lt(_read_packets_packet_bytes_read_T_1, bytesLeft) node _read_packets_packet_bytes_read_T_3 = mux(_read_packets_packet_bytes_read_T_2, _read_packets_packet_bytes_read_T_1, bytesLeft) connect read_packets_0.bytes_read, _read_packets_packet_bytes_read_T_3 connect read_packets_0.shift, read_packets_vaddr_offset connect read_packets_0.vaddr, read_packets_vaddr_aligned_to_size node _read_packets_vaddr_aligned_to_size_T_1 = bits(req.vaddr, 38, 5) node read_packets_vaddr_aligned_to_size_1 = cat(_read_packets_vaddr_aligned_to_size_T_1, UInt<5>(0h0)) node read_packets_vaddr_offset_1 = bits(req.vaddr, 4, 0) wire read_packets_1 : { size : UInt<7>, lg_size : UInt<3>, bytes_read : UInt<7>, shift : UInt<6>, vaddr : UInt<39>} connect read_packets_1.size, UInt<6>(0h20) connect read_packets_1.lg_size, UInt<3>(0h5) node _read_packets_packet_bytes_read_T_4 = sub(UInt<6>(0h20), read_packets_vaddr_offset_1) node _read_packets_packet_bytes_read_T_5 = tail(_read_packets_packet_bytes_read_T_4, 1) node _read_packets_packet_bytes_read_T_6 = lt(_read_packets_packet_bytes_read_T_5, bytesLeft) node _read_packets_packet_bytes_read_T_7 = mux(_read_packets_packet_bytes_read_T_6, _read_packets_packet_bytes_read_T_5, bytesLeft) connect read_packets_1.bytes_read, _read_packets_packet_bytes_read_T_7 connect read_packets_1.shift, read_packets_vaddr_offset_1 connect read_packets_1.vaddr, read_packets_vaddr_aligned_to_size_1 node _read_packets_vaddr_aligned_to_size_T_2 = bits(req.vaddr, 38, 6) node read_packets_vaddr_aligned_to_size_2 = cat(_read_packets_vaddr_aligned_to_size_T_2, UInt<6>(0h0)) node read_packets_vaddr_offset_2 = bits(req.vaddr, 5, 0) wire read_packets_2 : { size : UInt<7>, lg_size : UInt<3>, bytes_read : UInt<7>, shift : UInt<6>, vaddr : UInt<39>} connect read_packets_2.size, UInt<7>(0h40) connect read_packets_2.lg_size, UInt<3>(0h6) node _read_packets_packet_bytes_read_T_8 = sub(UInt<7>(0h40), read_packets_vaddr_offset_2) node _read_packets_packet_bytes_read_T_9 = tail(_read_packets_packet_bytes_read_T_8, 1) node _read_packets_packet_bytes_read_T_10 = lt(_read_packets_packet_bytes_read_T_9, bytesLeft) node _read_packets_packet_bytes_read_T_11 = mux(_read_packets_packet_bytes_read_T_10, _read_packets_packet_bytes_read_T_9, bytesLeft) connect read_packets_2.bytes_read, _read_packets_packet_bytes_read_T_11 connect read_packets_2.shift, read_packets_vaddr_offset_2 connect read_packets_2.vaddr, read_packets_vaddr_aligned_to_size_2 node _read_packet_T = gt(read_packets_1.bytes_read, read_packets_0.bytes_read) node _read_packet_T_1 = mux(_read_packet_T, read_packets_1, read_packets_0) node _read_packet_T_2 = gt(read_packets_2.bytes_read, _read_packet_T_1.bytes_read) node read_packet = mux(_read_packet_T_2, read_packets_2, _read_packet_T_1) node _get_legal_T = leq(UInt<1>(0h0), read_packet.lg_size) node _get_legal_T_1 = leq(read_packet.lg_size, UInt<4>(0hc)) node _get_legal_T_2 = and(_get_legal_T, _get_legal_T_1) node _get_legal_T_3 = or(UInt<1>(0h0), _get_legal_T_2) node _get_legal_T_4 = xor(UInt<1>(0h0), UInt<14>(0h3000)) node _get_legal_T_5 = cvt(_get_legal_T_4) node _get_legal_T_6 = and(_get_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _get_legal_T_7 = asSInt(_get_legal_T_6) node _get_legal_T_8 = eq(_get_legal_T_7, asSInt(UInt<1>(0h0))) node _get_legal_T_9 = and(_get_legal_T_3, _get_legal_T_8) node _get_legal_T_10 = leq(UInt<1>(0h0), read_packet.lg_size) node _get_legal_T_11 = leq(read_packet.lg_size, UInt<3>(0h6)) node _get_legal_T_12 = and(_get_legal_T_10, _get_legal_T_11) node _get_legal_T_13 = or(UInt<1>(0h0), _get_legal_T_12) node _get_legal_T_14 = xor(UInt<1>(0h0), UInt<1>(0h0)) node _get_legal_T_15 = cvt(_get_legal_T_14) node _get_legal_T_16 = and(_get_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _get_legal_T_17 = asSInt(_get_legal_T_16) node _get_legal_T_18 = eq(_get_legal_T_17, asSInt(UInt<1>(0h0))) node _get_legal_T_19 = xor(UInt<1>(0h0), UInt<17>(0h10000)) node _get_legal_T_20 = cvt(_get_legal_T_19) node _get_legal_T_21 = and(_get_legal_T_20, asSInt(UInt<33>(0h98013000))) node _get_legal_T_22 = asSInt(_get_legal_T_21) node _get_legal_T_23 = eq(_get_legal_T_22, asSInt(UInt<1>(0h0))) node _get_legal_T_24 = xor(UInt<1>(0h0), UInt<17>(0h10000)) node _get_legal_T_25 = cvt(_get_legal_T_24) node _get_legal_T_26 = and(_get_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _get_legal_T_27 = asSInt(_get_legal_T_26) node _get_legal_T_28 = eq(_get_legal_T_27, asSInt(UInt<1>(0h0))) node _get_legal_T_29 = xor(UInt<1>(0h0), UInt<26>(0h2000000)) node _get_legal_T_30 = cvt(_get_legal_T_29) node _get_legal_T_31 = and(_get_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _get_legal_T_32 = asSInt(_get_legal_T_31) node _get_legal_T_33 = eq(_get_legal_T_32, asSInt(UInt<1>(0h0))) node _get_legal_T_34 = xor(UInt<1>(0h0), UInt<28>(0h8000000)) node _get_legal_T_35 = cvt(_get_legal_T_34) node _get_legal_T_36 = and(_get_legal_T_35, asSInt(UInt<33>(0h98000000))) node _get_legal_T_37 = asSInt(_get_legal_T_36) node _get_legal_T_38 = eq(_get_legal_T_37, asSInt(UInt<1>(0h0))) node _get_legal_T_39 = xor(UInt<1>(0h0), UInt<28>(0h8000000)) node _get_legal_T_40 = cvt(_get_legal_T_39) node _get_legal_T_41 = and(_get_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _get_legal_T_42 = asSInt(_get_legal_T_41) node _get_legal_T_43 = eq(_get_legal_T_42, asSInt(UInt<1>(0h0))) node _get_legal_T_44 = xor(UInt<1>(0h0), UInt<29>(0h10000000)) node _get_legal_T_45 = cvt(_get_legal_T_44) node _get_legal_T_46 = and(_get_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _get_legal_T_47 = asSInt(_get_legal_T_46) node _get_legal_T_48 = eq(_get_legal_T_47, asSInt(UInt<1>(0h0))) node _get_legal_T_49 = xor(UInt<1>(0h0), UInt<32>(0h80000000)) node _get_legal_T_50 = cvt(_get_legal_T_49) node _get_legal_T_51 = and(_get_legal_T_50, asSInt(UInt<33>(0h90000000))) node _get_legal_T_52 = asSInt(_get_legal_T_51) node _get_legal_T_53 = eq(_get_legal_T_52, asSInt(UInt<1>(0h0))) node _get_legal_T_54 = or(_get_legal_T_18, _get_legal_T_23) node _get_legal_T_55 = or(_get_legal_T_54, _get_legal_T_28) node _get_legal_T_56 = or(_get_legal_T_55, _get_legal_T_33) node _get_legal_T_57 = or(_get_legal_T_56, _get_legal_T_38) node _get_legal_T_58 = or(_get_legal_T_57, _get_legal_T_43) node _get_legal_T_59 = or(_get_legal_T_58, _get_legal_T_48) node _get_legal_T_60 = or(_get_legal_T_59, _get_legal_T_53) node _get_legal_T_61 = and(_get_legal_T_13, _get_legal_T_60) node _get_legal_T_62 = or(UInt<1>(0h0), _get_legal_T_9) node get_legal = or(_get_legal_T_62, _get_legal_T_61) wire get : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect get.opcode, UInt<3>(0h4) connect get.param, UInt<1>(0h0) connect get.size, read_packet.lg_size connect get.source, io.reserve.xactid connect get.address, UInt<1>(0h0) node _get_a_mask_sizeOH_T = or(read_packet.lg_size, UInt<4>(0h0)) node get_a_mask_sizeOH_shiftAmount = bits(_get_a_mask_sizeOH_T, 1, 0) node _get_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), get_a_mask_sizeOH_shiftAmount) node _get_a_mask_sizeOH_T_2 = bits(_get_a_mask_sizeOH_T_1, 3, 0) node get_a_mask_sizeOH = or(_get_a_mask_sizeOH_T_2, UInt<1>(0h1)) node get_a_mask_sub_sub_sub_sub_0_1 = geq(read_packet.lg_size, UInt<3>(0h4)) node get_a_mask_sub_sub_sub_size = bits(get_a_mask_sizeOH, 3, 3) node get_a_mask_sub_sub_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) node get_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_sub_nbit) node _get_a_mask_sub_sub_sub_acc_T = and(get_a_mask_sub_sub_sub_size, get_a_mask_sub_sub_sub_0_2) node get_a_mask_sub_sub_sub_0_1 = or(get_a_mask_sub_sub_sub_sub_0_1, _get_a_mask_sub_sub_sub_acc_T) node get_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node _get_a_mask_sub_sub_sub_acc_T_1 = and(get_a_mask_sub_sub_sub_size, get_a_mask_sub_sub_sub_1_2) node get_a_mask_sub_sub_sub_1_1 = or(get_a_mask_sub_sub_sub_sub_0_1, _get_a_mask_sub_sub_sub_acc_T_1) node get_a_mask_sub_sub_size = bits(get_a_mask_sizeOH, 2, 2) node get_a_mask_sub_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) node get_a_mask_sub_sub_0_2 = and(get_a_mask_sub_sub_sub_0_2, get_a_mask_sub_sub_nbit) node _get_a_mask_sub_sub_acc_T = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_0_2) node get_a_mask_sub_sub_0_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T) node get_a_mask_sub_sub_1_2 = and(get_a_mask_sub_sub_sub_0_2, UInt<1>(0h0)) node _get_a_mask_sub_sub_acc_T_1 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_1_2) node get_a_mask_sub_sub_1_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T_1) node get_a_mask_sub_sub_2_2 = and(get_a_mask_sub_sub_sub_1_2, get_a_mask_sub_sub_nbit) node _get_a_mask_sub_sub_acc_T_2 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_2_2) node get_a_mask_sub_sub_2_1 = or(get_a_mask_sub_sub_sub_1_1, _get_a_mask_sub_sub_acc_T_2) node get_a_mask_sub_sub_3_2 = and(get_a_mask_sub_sub_sub_1_2, UInt<1>(0h0)) node _get_a_mask_sub_sub_acc_T_3 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_3_2) node get_a_mask_sub_sub_3_1 = or(get_a_mask_sub_sub_sub_1_1, _get_a_mask_sub_sub_acc_T_3) node get_a_mask_sub_size = bits(get_a_mask_sizeOH, 1, 1) node get_a_mask_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) node get_a_mask_sub_0_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_nbit) node _get_a_mask_sub_acc_T = and(get_a_mask_sub_size, get_a_mask_sub_0_2) node get_a_mask_sub_0_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T) node get_a_mask_sub_1_2 = and(get_a_mask_sub_sub_0_2, UInt<1>(0h0)) node _get_a_mask_sub_acc_T_1 = and(get_a_mask_sub_size, get_a_mask_sub_1_2) node get_a_mask_sub_1_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T_1) node get_a_mask_sub_2_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_nbit) node _get_a_mask_sub_acc_T_2 = and(get_a_mask_sub_size, get_a_mask_sub_2_2) node get_a_mask_sub_2_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_2) node get_a_mask_sub_3_2 = and(get_a_mask_sub_sub_1_2, UInt<1>(0h0)) node _get_a_mask_sub_acc_T_3 = and(get_a_mask_sub_size, get_a_mask_sub_3_2) node get_a_mask_sub_3_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_3) node get_a_mask_sub_4_2 = and(get_a_mask_sub_sub_2_2, get_a_mask_sub_nbit) node _get_a_mask_sub_acc_T_4 = and(get_a_mask_sub_size, get_a_mask_sub_4_2) node get_a_mask_sub_4_1 = or(get_a_mask_sub_sub_2_1, _get_a_mask_sub_acc_T_4) node get_a_mask_sub_5_2 = and(get_a_mask_sub_sub_2_2, UInt<1>(0h0)) node _get_a_mask_sub_acc_T_5 = and(get_a_mask_sub_size, get_a_mask_sub_5_2) node get_a_mask_sub_5_1 = or(get_a_mask_sub_sub_2_1, _get_a_mask_sub_acc_T_5) node get_a_mask_sub_6_2 = and(get_a_mask_sub_sub_3_2, get_a_mask_sub_nbit) node _get_a_mask_sub_acc_T_6 = and(get_a_mask_sub_size, get_a_mask_sub_6_2) node get_a_mask_sub_6_1 = or(get_a_mask_sub_sub_3_1, _get_a_mask_sub_acc_T_6) node get_a_mask_sub_7_2 = and(get_a_mask_sub_sub_3_2, UInt<1>(0h0)) node _get_a_mask_sub_acc_T_7 = and(get_a_mask_sub_size, get_a_mask_sub_7_2) node get_a_mask_sub_7_1 = or(get_a_mask_sub_sub_3_1, _get_a_mask_sub_acc_T_7) node get_a_mask_size = bits(get_a_mask_sizeOH, 0, 0) node get_a_mask_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) node get_a_mask_eq = and(get_a_mask_sub_0_2, get_a_mask_nbit) node _get_a_mask_acc_T = and(get_a_mask_size, get_a_mask_eq) node get_a_mask_acc = or(get_a_mask_sub_0_1, _get_a_mask_acc_T) node get_a_mask_eq_1 = and(get_a_mask_sub_0_2, UInt<1>(0h0)) node _get_a_mask_acc_T_1 = and(get_a_mask_size, get_a_mask_eq_1) node get_a_mask_acc_1 = or(get_a_mask_sub_0_1, _get_a_mask_acc_T_1) node get_a_mask_eq_2 = and(get_a_mask_sub_1_2, get_a_mask_nbit) node _get_a_mask_acc_T_2 = and(get_a_mask_size, get_a_mask_eq_2) node get_a_mask_acc_2 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_2) node get_a_mask_eq_3 = and(get_a_mask_sub_1_2, UInt<1>(0h0)) node _get_a_mask_acc_T_3 = and(get_a_mask_size, get_a_mask_eq_3) node get_a_mask_acc_3 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_3) node get_a_mask_eq_4 = and(get_a_mask_sub_2_2, get_a_mask_nbit) node _get_a_mask_acc_T_4 = and(get_a_mask_size, get_a_mask_eq_4) node get_a_mask_acc_4 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_4) node get_a_mask_eq_5 = and(get_a_mask_sub_2_2, UInt<1>(0h0)) node _get_a_mask_acc_T_5 = and(get_a_mask_size, get_a_mask_eq_5) node get_a_mask_acc_5 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_5) node get_a_mask_eq_6 = and(get_a_mask_sub_3_2, get_a_mask_nbit) node _get_a_mask_acc_T_6 = and(get_a_mask_size, get_a_mask_eq_6) node get_a_mask_acc_6 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_6) node get_a_mask_eq_7 = and(get_a_mask_sub_3_2, UInt<1>(0h0)) node _get_a_mask_acc_T_7 = and(get_a_mask_size, get_a_mask_eq_7) node get_a_mask_acc_7 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_7) node get_a_mask_eq_8 = and(get_a_mask_sub_4_2, get_a_mask_nbit) node _get_a_mask_acc_T_8 = and(get_a_mask_size, get_a_mask_eq_8) node get_a_mask_acc_8 = or(get_a_mask_sub_4_1, _get_a_mask_acc_T_8) node get_a_mask_eq_9 = and(get_a_mask_sub_4_2, UInt<1>(0h0)) node _get_a_mask_acc_T_9 = and(get_a_mask_size, get_a_mask_eq_9) node get_a_mask_acc_9 = or(get_a_mask_sub_4_1, _get_a_mask_acc_T_9) node get_a_mask_eq_10 = and(get_a_mask_sub_5_2, get_a_mask_nbit) node _get_a_mask_acc_T_10 = and(get_a_mask_size, get_a_mask_eq_10) node get_a_mask_acc_10 = or(get_a_mask_sub_5_1, _get_a_mask_acc_T_10) node get_a_mask_eq_11 = and(get_a_mask_sub_5_2, UInt<1>(0h0)) node _get_a_mask_acc_T_11 = and(get_a_mask_size, get_a_mask_eq_11) node get_a_mask_acc_11 = or(get_a_mask_sub_5_1, _get_a_mask_acc_T_11) node get_a_mask_eq_12 = and(get_a_mask_sub_6_2, get_a_mask_nbit) node _get_a_mask_acc_T_12 = and(get_a_mask_size, get_a_mask_eq_12) node get_a_mask_acc_12 = or(get_a_mask_sub_6_1, _get_a_mask_acc_T_12) node get_a_mask_eq_13 = and(get_a_mask_sub_6_2, UInt<1>(0h0)) node _get_a_mask_acc_T_13 = and(get_a_mask_size, get_a_mask_eq_13) node get_a_mask_acc_13 = or(get_a_mask_sub_6_1, _get_a_mask_acc_T_13) node get_a_mask_eq_14 = and(get_a_mask_sub_7_2, get_a_mask_nbit) node _get_a_mask_acc_T_14 = and(get_a_mask_size, get_a_mask_eq_14) node get_a_mask_acc_14 = or(get_a_mask_sub_7_1, _get_a_mask_acc_T_14) node get_a_mask_eq_15 = and(get_a_mask_sub_7_2, UInt<1>(0h0)) node _get_a_mask_acc_T_15 = and(get_a_mask_size, get_a_mask_eq_15) node get_a_mask_acc_15 = or(get_a_mask_sub_7_1, _get_a_mask_acc_T_15) node get_a_mask_lo_lo_lo = cat(get_a_mask_acc_1, get_a_mask_acc) node get_a_mask_lo_lo_hi = cat(get_a_mask_acc_3, get_a_mask_acc_2) node get_a_mask_lo_lo = cat(get_a_mask_lo_lo_hi, get_a_mask_lo_lo_lo) node get_a_mask_lo_hi_lo = cat(get_a_mask_acc_5, get_a_mask_acc_4) node get_a_mask_lo_hi_hi = cat(get_a_mask_acc_7, get_a_mask_acc_6) node get_a_mask_lo_hi = cat(get_a_mask_lo_hi_hi, get_a_mask_lo_hi_lo) node get_a_mask_lo = cat(get_a_mask_lo_hi, get_a_mask_lo_lo) node get_a_mask_hi_lo_lo = cat(get_a_mask_acc_9, get_a_mask_acc_8) node get_a_mask_hi_lo_hi = cat(get_a_mask_acc_11, get_a_mask_acc_10) node get_a_mask_hi_lo = cat(get_a_mask_hi_lo_hi, get_a_mask_hi_lo_lo) node get_a_mask_hi_hi_lo = cat(get_a_mask_acc_13, get_a_mask_acc_12) node get_a_mask_hi_hi_hi = cat(get_a_mask_acc_15, get_a_mask_acc_14) node get_a_mask_hi_hi = cat(get_a_mask_hi_hi_hi, get_a_mask_hi_hi_lo) node get_a_mask_hi = cat(get_a_mask_hi_hi, get_a_mask_hi_lo) node _get_a_mask_T = cat(get_a_mask_hi, get_a_mask_lo) connect get.mask, _get_a_mask_T invalidate get.data connect get.corrupt, UInt<1>(0h0) wire untranslated_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { tl_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}, vaddr : UInt<39>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} node _untranslated_a_valid_T = eq(state, UInt<1>(0h1)) node _untranslated_a_valid_T_1 = and(_untranslated_a_valid_T, io.reserve.ready) connect untranslated_a.valid, _untranslated_a_valid_T_1 connect untranslated_a.bits.tl_a, get connect untranslated_a.bits.vaddr, read_packet.vaddr connect untranslated_a.bits.status, req.status wire retry_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { tl_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}, vaddr : UInt<39>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} inst tlb_arb of Arbiter2_TLBundleAWithInfo connect tlb_arb.clock, clock connect tlb_arb.reset, reset connect tlb_arb.io.in[0], retry_a connect tlb_arb.io.in[1], untranslated_a inst tlb_q of Queue1_TLBundleAWithInfo connect tlb_q.clock, clock connect tlb_q.reset, reset connect tlb_q.io.enq, tlb_arb.io.out connect io.tlb.req.valid, tlb_q.io.deq.valid invalidate io.tlb.req.bits.status.uie invalidate io.tlb.req.bits.status.sie invalidate io.tlb.req.bits.status.hie invalidate io.tlb.req.bits.status.mie invalidate io.tlb.req.bits.status.upie invalidate io.tlb.req.bits.status.spie invalidate io.tlb.req.bits.status.ube invalidate io.tlb.req.bits.status.mpie invalidate io.tlb.req.bits.status.spp invalidate io.tlb.req.bits.status.vs invalidate io.tlb.req.bits.status.mpp invalidate io.tlb.req.bits.status.fs invalidate io.tlb.req.bits.status.xs invalidate io.tlb.req.bits.status.mprv invalidate io.tlb.req.bits.status.sum invalidate io.tlb.req.bits.status.mxr invalidate io.tlb.req.bits.status.tvm invalidate io.tlb.req.bits.status.tw invalidate io.tlb.req.bits.status.tsr invalidate io.tlb.req.bits.status.zero1 invalidate io.tlb.req.bits.status.sd_rv32 invalidate io.tlb.req.bits.status.uxl invalidate io.tlb.req.bits.status.sxl invalidate io.tlb.req.bits.status.sbe invalidate io.tlb.req.bits.status.mbe invalidate io.tlb.req.bits.status.gva invalidate io.tlb.req.bits.status.mpv invalidate io.tlb.req.bits.status.zero2 invalidate io.tlb.req.bits.status.sd invalidate io.tlb.req.bits.status.v invalidate io.tlb.req.bits.status.prv invalidate io.tlb.req.bits.status.dv invalidate io.tlb.req.bits.status.dprv invalidate io.tlb.req.bits.status.isa invalidate io.tlb.req.bits.status.wfi invalidate io.tlb.req.bits.status.cease invalidate io.tlb.req.bits.status.debug invalidate io.tlb.req.bits.tlb_req.v invalidate io.tlb.req.bits.tlb_req.prv invalidate io.tlb.req.bits.tlb_req.cmd invalidate io.tlb.req.bits.tlb_req.size invalidate io.tlb.req.bits.tlb_req.passthrough invalidate io.tlb.req.bits.tlb_req.vaddr connect io.tlb.req.bits.tlb_req.vaddr, tlb_q.io.deq.bits.vaddr connect io.tlb.req.bits.tlb_req.passthrough, UInt<1>(0h0) connect io.tlb.req.bits.tlb_req.size, UInt<1>(0h0) connect io.tlb.req.bits.tlb_req.cmd, UInt<1>(0h0) connect io.tlb.req.bits.status, tlb_q.io.deq.bits.status inst translate_q of Queue1_TLBundleAWithInfo_1 connect translate_q.clock, clock connect translate_q.reset, reset connect translate_q.io.enq, tlb_q.io.deq connect translate_q.io.deq.ready, UInt<1>(0h1) node _retry_a_valid_T = eq(nodeOut.a.ready, UInt<1>(0h0)) node _retry_a_valid_T_1 = or(io.tlb.resp.miss, _retry_a_valid_T) node _retry_a_valid_T_2 = and(translate_q.io.deq.valid, _retry_a_valid_T_1) connect retry_a.valid, _retry_a_valid_T_2 connect retry_a.bits, translate_q.io.deq.bits node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : node _T_2 = eq(retry_a.ready, UInt<1>(0h0)) when _T_2 : printf(clock, UInt<1>(0h1), "Assertion failed\n at DMA.scala:247 assert(retry_a.ready)\n") : printf assert(clock, retry_a.ready, UInt<1>(0h1), "") : assert node _nodeOut_a_valid_T = eq(io.tlb.resp.miss, UInt<1>(0h0)) node _nodeOut_a_valid_T_1 = and(translate_q.io.deq.valid, _nodeOut_a_valid_T) connect nodeOut.a.valid, _nodeOut_a_valid_T_1 connect nodeOut.a.bits, translate_q.io.deq.bits.tl_a connect nodeOut.a.bits.address, io.tlb.resp.paddr node _io_reserve_valid_T = eq(state, UInt<1>(0h1)) node _io_reserve_valid_T_1 = and(_io_reserve_valid_T, untranslated_a.ready) connect io.reserve.valid, _io_reserve_valid_T_1 connect io.reserve.entry.shift, read_packet.shift connect io.reserve.entry.is_acc, req.is_acc connect io.reserve.entry.accumulate, req.accumulate connect io.reserve.entry.has_acc_bitwidth, req.has_acc_bitwidth connect io.reserve.entry.scale, req.scale connect io.reserve.entry.repeats, req.repeats connect io.reserve.entry.pixel_repeats, req.pixel_repeats connect io.reserve.entry.len, req.len connect io.reserve.entry.block_stride, req.block_stride invalidate io.reserve.entry.lg_len_req connect io.reserve.entry.bytes_to_read, read_packet.bytes_read connect io.reserve.entry.cmd_id, req.cmd_id node _io_reserve_entry_addr_T = div(bytesRequested, UInt<6>(0h10)) node _io_reserve_entry_addr_T_1 = mux(req.has_acc_bitwidth, UInt<1>(0h0), _io_reserve_entry_addr_T) node _io_reserve_entry_addr_T_2 = mul(req.block_stride, _io_reserve_entry_addr_T_1) node _io_reserve_entry_addr_T_3 = add(req.spaddr, _io_reserve_entry_addr_T_2) node _io_reserve_entry_addr_T_4 = tail(_io_reserve_entry_addr_T_3, 1) connect io.reserve.entry.addr, _io_reserve_entry_addr_T_4 node _io_reserve_entry_spad_row_offset_T = rem(bytesRequested, UInt<7>(0h40)) node _io_reserve_entry_spad_row_offset_T_1 = rem(bytesRequested, UInt<5>(0h10)) node _io_reserve_entry_spad_row_offset_T_2 = mux(req.has_acc_bitwidth, _io_reserve_entry_spad_row_offset_T, _io_reserve_entry_spad_row_offset_T_1) connect io.reserve.entry.spad_row_offset, _io_reserve_entry_spad_row_offset_T_2 node _T_3 = and(untranslated_a.ready, untranslated_a.valid) when _T_3 : node _next_vaddr_T = add(req.vaddr, read_packet.bytes_read) node next_vaddr = tail(_next_vaddr_T, 1) node _new_page_T = bits(next_vaddr, 11, 0) node new_page = eq(_new_page_T, UInt<1>(0h0)) connect req.vaddr, next_vaddr node _bytesRequested_T = add(bytesRequested, read_packet.bytes_read) node _bytesRequested_T_1 = tail(_bytesRequested_T, 1) connect bytesRequested, _bytesRequested_T_1 node _T_4 = geq(read_packet.bytes_read, bytesLeft) when _T_4 : connect state_machine_ready_for_req, UInt<1>(0h1) connect state, UInt<1>(0h0) connect nodeOut.d.ready, io.beatData.ready connect io.beatData.valid, nodeOut.d.valid connect io.beatData.bits.xactid, nodeOut.d.bits.source connect io.beatData.bits.data, nodeOut.d.bits.data connect io.beatData.bits.lg_len_req, nodeOut.d.bits.size node _io_beatData_bits_last_T = and(nodeOut.d.ready, nodeOut.d.valid) node _io_beatData_bits_last_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.d.bits.size) node _io_beatData_bits_last_beats1_decode_T_1 = bits(_io_beatData_bits_last_beats1_decode_T, 11, 0) node _io_beatData_bits_last_beats1_decode_T_2 = not(_io_beatData_bits_last_beats1_decode_T_1) node io_beatData_bits_last_beats1_decode = shr(_io_beatData_bits_last_beats1_decode_T_2, 4) node io_beatData_bits_last_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0) node io_beatData_bits_last_beats1 = mux(io_beatData_bits_last_beats1_opdata, io_beatData_bits_last_beats1_decode, UInt<1>(0h0)) regreset io_beatData_bits_last_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _io_beatData_bits_last_counter1_T = sub(io_beatData_bits_last_counter, UInt<1>(0h1)) node io_beatData_bits_last_counter1 = tail(_io_beatData_bits_last_counter1_T, 1) node io_beatData_bits_last_first = eq(io_beatData_bits_last_counter, UInt<1>(0h0)) node _io_beatData_bits_last_last_T = eq(io_beatData_bits_last_counter, UInt<1>(0h1)) node _io_beatData_bits_last_last_T_1 = eq(io_beatData_bits_last_beats1, UInt<1>(0h0)) node io_beatData_bits_last_last = or(_io_beatData_bits_last_last_T, _io_beatData_bits_last_last_T_1) node io_beatData_bits_last_done = and(io_beatData_bits_last_last, _io_beatData_bits_last_T) node _io_beatData_bits_last_count_T = not(io_beatData_bits_last_counter1) node io_beatData_bits_last_count = and(io_beatData_bits_last_beats1, _io_beatData_bits_last_count_T) when _io_beatData_bits_last_T : node _io_beatData_bits_last_counter_T = mux(io_beatData_bits_last_first, io_beatData_bits_last_beats1, io_beatData_bits_last_counter1) connect io_beatData_bits_last_counter, _io_beatData_bits_last_counter_T connect io.beatData.bits.last, io_beatData_bits_last_last node _T_5 = and(io.req.ready, io.req.valid) when _T_5 : connect req, io.req.bits connect bytesRequested, UInt<1>(0h0) connect state, UInt<1>(0h1) invalidate io.counter.external_reset invalidate io.counter.external_values[0] invalidate io.counter.external_values[1] invalidate io.counter.external_values[2] invalidate io.counter.external_values[3] invalidate io.counter.external_values[4] invalidate io.counter.external_values[5] invalidate io.counter.external_values[6] invalidate io.counter.external_values[7] invalidate io.counter.event_signal[0] invalidate io.counter.event_signal[1] invalidate io.counter.event_signal[2] invalidate io.counter.event_signal[3] invalidate io.counter.event_signal[4] invalidate io.counter.event_signal[5] invalidate io.counter.event_signal[6] invalidate io.counter.event_signal[7] invalidate io.counter.event_signal[8] invalidate io.counter.event_signal[9] invalidate io.counter.event_signal[10] invalidate io.counter.event_signal[11] invalidate io.counter.event_signal[12] invalidate io.counter.event_signal[13] invalidate io.counter.event_signal[14] invalidate io.counter.event_signal[15] invalidate io.counter.event_signal[16] invalidate io.counter.event_signal[17] invalidate io.counter.event_signal[18] invalidate io.counter.event_signal[19] invalidate io.counter.event_signal[20] invalidate io.counter.event_signal[21] invalidate io.counter.event_signal[22] invalidate io.counter.event_signal[23] invalidate io.counter.event_signal[24] invalidate io.counter.event_signal[25] invalidate io.counter.event_signal[26] invalidate io.counter.event_signal[27] invalidate io.counter.event_signal[28] invalidate io.counter.event_signal[29] invalidate io.counter.event_signal[30] invalidate io.counter.event_signal[31] invalidate io.counter.event_signal[32] invalidate io.counter.event_signal[33] invalidate io.counter.event_signal[34] invalidate io.counter.event_signal[35] invalidate io.counter.event_signal[36] invalidate io.counter.event_signal[37] invalidate io.counter.event_signal[38] invalidate io.counter.event_signal[39] invalidate io.counter.event_signal[40] invalidate io.counter.event_signal[41] invalidate io.counter.event_signal[42] invalidate io.counter.event_signal[43] invalidate io.counter.event_signal[44] wire _WIRE : UInt<1>[45] connect _WIRE[0], UInt<1>(0h0) connect _WIRE[1], UInt<1>(0h0) connect _WIRE[2], UInt<1>(0h0) connect _WIRE[3], UInt<1>(0h0) connect _WIRE[4], UInt<1>(0h0) connect _WIRE[5], UInt<1>(0h0) connect _WIRE[6], UInt<1>(0h0) connect _WIRE[7], UInt<1>(0h0) connect _WIRE[8], UInt<1>(0h0) connect _WIRE[9], UInt<1>(0h0) connect _WIRE[10], UInt<1>(0h0) connect _WIRE[11], UInt<1>(0h0) connect _WIRE[12], UInt<1>(0h0) connect _WIRE[13], UInt<1>(0h0) connect _WIRE[14], UInt<1>(0h0) connect _WIRE[15], UInt<1>(0h0) connect _WIRE[16], UInt<1>(0h0) connect _WIRE[17], UInt<1>(0h0) connect _WIRE[18], UInt<1>(0h0) connect _WIRE[19], UInt<1>(0h0) connect _WIRE[20], UInt<1>(0h0) connect _WIRE[21], UInt<1>(0h0) connect _WIRE[22], UInt<1>(0h0) connect _WIRE[23], UInt<1>(0h0) connect _WIRE[24], UInt<1>(0h0) connect _WIRE[25], UInt<1>(0h0) connect _WIRE[26], UInt<1>(0h0) connect _WIRE[27], UInt<1>(0h0) connect _WIRE[28], UInt<1>(0h0) connect _WIRE[29], UInt<1>(0h0) connect _WIRE[30], UInt<1>(0h0) connect _WIRE[31], UInt<1>(0h0) connect _WIRE[32], UInt<1>(0h0) connect _WIRE[33], UInt<1>(0h0) connect _WIRE[34], UInt<1>(0h0) connect _WIRE[35], UInt<1>(0h0) connect _WIRE[36], UInt<1>(0h0) connect _WIRE[37], UInt<1>(0h0) connect _WIRE[38], UInt<1>(0h0) connect _WIRE[39], UInt<1>(0h0) connect _WIRE[40], UInt<1>(0h0) connect _WIRE[41], UInt<1>(0h0) connect _WIRE[42], UInt<1>(0h0) connect _WIRE[43], UInt<1>(0h0) connect _WIRE[44], UInt<1>(0h0) connect io.counter.event_signal, _WIRE wire _WIRE_1 : UInt<32>[8] connect _WIRE_1[0], UInt<32>(0h0) connect _WIRE_1[1], UInt<32>(0h0) connect _WIRE_1[2], UInt<32>(0h0) connect _WIRE_1[3], UInt<32>(0h0) connect _WIRE_1[4], UInt<32>(0h0) connect _WIRE_1[5], UInt<32>(0h0) connect _WIRE_1[6], UInt<32>(0h0) connect _WIRE_1[7], UInt<32>(0h0) connect io.counter.external_values, _WIRE_1 node _T_6 = neq(state, UInt<1>(0h0)) connect io.counter.event_signal[18], _T_6 connect io.counter.event_signal[19], io.tlb.resp.miss node _T_7 = eq(nodeOut.a.ready, UInt<1>(0h0)) node _T_8 = and(nodeOut.a.valid, _T_7) connect io.counter.event_signal[20], _T_8 regreset total_bytes_read : UInt<32>, clock, reset, UInt<32>(0h0) when io.counter.external_reset : connect total_bytes_read, UInt<1>(0h0) else : node _T_9 = and(nodeOut.d.ready, nodeOut.d.valid) when _T_9 : node _total_bytes_read_T = dshl(UInt<1>(0h1), nodeOut.d.bits.size) node _total_bytes_read_T_1 = add(total_bytes_read, _total_bytes_read_T) node _total_bytes_read_T_2 = tail(_total_bytes_read_T_1, 1) connect total_bytes_read, _total_bytes_read_T_2 connect io.counter.external_values[4], total_bytes_read node _T_10 = neq(state, UInt<1>(0h0)) node _T_11 = and(nodeOut.a.ready, translate_q.io.deq.valid) node _T_12 = and(_T_11, io.tlb.resp.miss) node _T_13 = eq(nodeOut.a.ready, UInt<1>(0h0)) node _T_14 = and(nodeOut.a.valid, _T_13) regreset cntr_value : UInt<19>, clock, reset, UInt<19>(0h0) node wrap = eq(cntr_value, UInt<19>(0h7a11f)) node _value_T = add(cntr_value, UInt<1>(0h1)) node _value_T_1 = tail(_value_T, 1) connect cntr_value, _value_T_1 when wrap : connect cntr_value, UInt<1>(0h0) when wrap : node _printf_T = asUInt(reset) node _printf_T_1 = eq(_printf_T, UInt<1>(0h0)) when _printf_T_1 : printf(clock, UInt<1>(0h1), "RDMA bytes rec: %d\n", total_bytes_read) : printf_1 node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "") : printf_2	module StreamReaderCore( // @[DMA.scala:138:9] input clock, // @[DMA.scala:138:9] input reset, // @[DMA.scala:138:9] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_req_ready, // @[DMA.scala:147:16] input io_req_valid, // @[DMA.scala:147:16] input [39:0] io_req_bits_vaddr, // @[DMA.scala:147:16] input [13:0] io_req_bits_spaddr, // @[DMA.scala:147:16] input io_req_bits_is_acc, // @[DMA.scala:147:16] input io_req_bits_accumulate, // @[DMA.scala:147:16] input io_req_bits_has_acc_bitwidth, // @[DMA.scala:147:16] input [31:0] io_req_bits_scale, // @[DMA.scala:147:16] input io_req_bits_status_debug, // @[DMA.scala:147:16] input io_req_bits_status_cease, // @[DMA.scala:147:16] input io_req_bits_status_wfi, // @[DMA.scala:147:16] input [31:0] io_req_bits_status_isa, // @[DMA.scala:147:16] input [1:0] io_req_bits_status_dprv, // @[DMA.scala:147:16] input io_req_bits_status_dv, // @[DMA.scala:147:16] input [1:0] io_req_bits_status_prv, // @[DMA.scala:147:16] input io_req_bits_status_v, // @[DMA.scala:147:16] input io_req_bits_status_sd, // @[DMA.scala:147:16] input [22:0] io_req_bits_status_zero2, // @[DMA.scala:147:16] input io_req_bits_status_mpv, // @[DMA.scala:147:16] input io_req_bits_status_gva, // @[DMA.scala:147:16] input io_req_bits_status_mbe, // @[DMA.scala:147:16] input io_req_bits_status_sbe, // @[DMA.scala:147:16] input [1:0] io_req_bits_status_sxl, // @[DMA.scala:147:16] input [1:0] io_req_bits_status_uxl, // @[DMA.scala:147:16] input io_req_bits_status_sd_rv32, // @[DMA.scala:147:16] input [7:0] io_req_bits_status_zero1, // @[DMA.scala:147:16] input io_req_bits_status_tsr, // @[DMA.scala:147:16] input io_req_bits_status_tw, // @[DMA.scala:147:16] input io_req_bits_status_tvm, // @[DMA.scala:147:16] input io_req_bits_status_mxr, // @[DMA.scala:147:16] input io_req_bits_status_sum, // @[DMA.scala:147:16] input io_req_bits_status_mprv, // @[DMA.scala:147:16] input [1:0] io_req_bits_status_xs, // @[DMA.scala:147:16] input [1:0] io_req_bits_status_fs, // @[DMA.scala:147:16] input [1:0] io_req_bits_status_mpp, // @[DMA.scala:147:16] input [1:0] io_req_bits_status_vs, // @[DMA.scala:147:16] input io_req_bits_status_spp, // @[DMA.scala:147:16] input io_req_bits_status_mpie, // @[DMA.scala:147:16] input io_req_bits_status_ube, // @[DMA.scala:147:16] input io_req_bits_status_spie, // @[DMA.scala:147:16] input io_req_bits_status_upie, // @[DMA.scala:147:16] input io_req_bits_status_mie, // @[DMA.scala:147:16] input io_req_bits_status_hie, // @[DMA.scala:147:16] input io_req_bits_status_sie, // @[DMA.scala:147:16] input io_req_bits_status_uie, // @[DMA.scala:147:16] input [15:0] io_req_bits_len, // @[DMA.scala:147:16] input [15:0] io_req_bits_repeats, // @[DMA.scala:147:16] input [7:0] io_req_bits_pixel_repeats, // @[DMA.scala:147:16] input [15:0] io_req_bits_block_stride, // @[DMA.scala:147:16] input [7:0] io_req_bits_cmd_id, // @[DMA.scala:147:16] output io_reserve_valid, // @[DMA.scala:147:16] input io_reserve_ready, // @[DMA.scala:147:16] input [5:0] io_reserve_xactid, // @[DMA.scala:147:16] output [5:0] io_reserve_entry_shift, // @[DMA.scala:147:16] output [13:0] io_reserve_entry_addr, // @[DMA.scala:147:16] output io_reserve_entry_is_acc, // @[DMA.scala:147:16] output io_reserve_entry_accumulate, // @[DMA.scala:147:16] output io_reserve_entry_has_acc_bitwidth, // @[DMA.scala:147:16] output [31:0] io_reserve_entry_scale, // @[DMA.scala:147:16] output [15:0] io_reserve_entry_repeats, // @[DMA.scala:147:16] output [7:0] io_reserve_entry_pixel_repeats, // @[DMA.scala:147:16] output [15:0] io_reserve_entry_len, // @[DMA.scala:147:16] output [15:0] io_reserve_entry_block_stride, // @[DMA.scala:147:16] output [8:0] io_reserve_entry_spad_row_offset, // @[DMA.scala:147:16] output [6:0] io_reserve_entry_bytes_to_read, // @[DMA.scala:147:16] output [2:0] io_reserve_entry_cmd_id, // @[DMA.scala:147:16] input io_beatData_ready, // @[DMA.scala:147:16] output io_beatData_valid, // @[DMA.scala:147:16] output [5:0] io_beatData_bits_xactid, // @[DMA.scala:147:16] output [127:0] io_beatData_bits_data, // @[DMA.scala:147:16] output [2:0] io_beatData_bits_lg_len_req, // @[DMA.scala:147:16] output io_beatData_bits_last, // @[DMA.scala:147:16] output io_tlb_req_valid, // @[DMA.scala:147:16] output [39:0] io_tlb_req_bits_tlb_req_vaddr, // @[DMA.scala:147:16] output io_tlb_req_bits_status_debug, // @[DMA.scala:147:16] output io_tlb_req_bits_status_cease, // @[DMA.scala:147:16] output io_tlb_req_bits_status_wfi, // @[DMA.scala:147:16] output [31:0] io_tlb_req_bits_status_isa, // @[DMA.scala:147:16] output [1:0] io_tlb_req_bits_status_dprv, // @[DMA.scala:147:16] output io_tlb_req_bits_status_dv, // @[DMA.scala:147:16] output [1:0] io_tlb_req_bits_status_prv, // @[DMA.scala:147:16] output io_tlb_req_bits_status_v, // @[DMA.scala:147:16] output io_tlb_req_bits_status_sd, // @[DMA.scala:147:16] output [22:0] io_tlb_req_bits_status_zero2, // @[DMA.scala:147:16] output io_tlb_req_bits_status_mpv, // @[DMA.scala:147:16] output io_tlb_req_bits_status_gva, // @[DMA.scala:147:16] output io_tlb_req_bits_status_mbe, // @[DMA.scala:147:16] output io_tlb_req_bits_status_sbe, // @[DMA.scala:147:16] output [1:0] io_tlb_req_bits_status_sxl, // @[DMA.scala:147:16] output [1:0] io_tlb_req_bits_status_uxl, // @[DMA.scala:147:16] output io_tlb_req_bits_status_sd_rv32, // @[DMA.scala:147:16] output [7:0] io_tlb_req_bits_status_zero1, // @[DMA.scala:147:16] output io_tlb_req_bits_status_tsr, // @[DMA.scala:147:16] output io_tlb_req_bits_status_tw, // @[DMA.scala:147:16] output io_tlb_req_bits_status_tvm, // @[DMA.scala:147:16] output io_tlb_req_bits_status_mxr, // @[DMA.scala:147:16] output io_tlb_req_bits_status_sum, // @[DMA.scala:147:16] output io_tlb_req_bits_status_mprv, // @[DMA.scala:147:16] output [1:0] io_tlb_req_bits_status_xs, // @[DMA.scala:147:16] output [1:0] io_tlb_req_bits_status_fs, // @[DMA.scala:147:16] output [1:0] io_tlb_req_bits_status_mpp, // @[DMA.scala:147:16] output [1:0] io_tlb_req_bits_status_vs, // @[DMA.scala:147:16] output io_tlb_req_bits_status_spp, // @[DMA.scala:147:16] output io_tlb_req_bits_status_mpie, // @[DMA.scala:147:16] output io_tlb_req_bits_status_ube, // @[DMA.scala:147:16] output io_tlb_req_bits_status_spie, // @[DMA.scala:147:16] output io_tlb_req_bits_status_upie, // @[DMA.scala:147:16] output io_tlb_req_bits_status_mie, // @[DMA.scala:147:16] output io_tlb_req_bits_status_hie, // @[DMA.scala:147:16] output io_tlb_req_bits_status_sie, // @[DMA.scala:147:16] output io_tlb_req_bits_status_uie, // @[DMA.scala:147:16] input io_tlb_resp_miss, // @[DMA.scala:147:16] input [31:0] io_tlb_resp_paddr, // @[DMA.scala:147:16] input [39:0] io_tlb_resp_gpa, // @[DMA.scala:147:16] input io_tlb_resp_pf_ld, // @[DMA.scala:147:16] input io_tlb_resp_pf_st, // @[DMA.scala:147:16] input io_tlb_resp_pf_inst, // @[DMA.scala:147:16] input io_tlb_resp_ae_ld, // @[DMA.scala:147:16] input io_tlb_resp_ae_st, // @[DMA.scala:147:16] input io_tlb_resp_ae_inst, // @[DMA.scala:147:16] input io_tlb_resp_cacheable, // @[DMA.scala:147:16] input io_tlb_resp_must_alloc, // @[DMA.scala:147:16] input io_tlb_resp_prefetchable, // @[DMA.scala:147:16] input [4:0] io_tlb_resp_cmd, // @[DMA.scala:147:16] input io_flush, // @[DMA.scala:147:16] output io_counter_event_signal_18, // @[DMA.scala:147:16] output io_counter_event_signal_19, // @[DMA.scala:147:16] output io_counter_event_signal_20, // @[DMA.scala:147:16] output [31:0] io_counter_external_values_4, // @[DMA.scala:147:16] input io_counter_external_reset // @[DMA.scala:147:16] ); wire [15:0] get_mask; // @[Edges.scala:460:17] wire [3:0] get_size; // @[Edges.scala:460:17] wire _translate_q_io_deq_valid; // @[DMA.scala:241:29] wire [2:0] _translate_q_io_deq_bits_tl_a_opcode; // @[DMA.scala:241:29] wire [2:0] _translate_q_io_deq_bits_tl_a_param; // @[DMA.scala:241:29] wire [3:0] _translate_q_io_deq_bits_tl_a_size; // @[DMA.scala:241:29] wire [5:0] _translate_q_io_deq_bits_tl_a_source; // @[DMA.scala:241:29] wire [15:0] _translate_q_io_deq_bits_tl_a_mask; // @[DMA.scala:241:29] wire [127:0] _translate_q_io_deq_bits_tl_a_data; // @[DMA.scala:241:29] wire _translate_q_io_deq_bits_tl_a_corrupt; // @[DMA.scala:241:29] wire _tlb_q_io_deq_valid; // @[DMA.scala:230:23] wire [2:0] _tlb_q_io_deq_bits_tl_a_opcode; // @[DMA.scala:230:23] wire [2:0] _tlb_q_io_deq_bits_tl_a_param; // @[DMA.scala:230:23] wire [3:0] _tlb_q_io_deq_bits_tl_a_size; // @[DMA.scala:230:23] wire [5:0] _tlb_q_io_deq_bits_tl_a_source; // @[DMA.scala:230:23] wire [31:0] _tlb_q_io_deq_bits_tl_a_address; // @[DMA.scala:230:23] wire [15:0] _tlb_q_io_deq_bits_tl_a_mask; // @[DMA.scala:230:23] wire [127:0] _tlb_q_io_deq_bits_tl_a_data; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_tl_a_corrupt; // @[DMA.scala:230:23] wire [38:0] _tlb_q_io_deq_bits_vaddr; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_debug; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_cease; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_wfi; // @[DMA.scala:230:23] wire [31:0] _tlb_q_io_deq_bits_status_isa; // @[DMA.scala:230:23] wire [1:0] _tlb_q_io_deq_bits_status_dprv; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_dv; // @[DMA.scala:230:23] wire [1:0] _tlb_q_io_deq_bits_status_prv; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_v; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_sd; // @[DMA.scala:230:23] wire [22:0] _tlb_q_io_deq_bits_status_zero2; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_mpv; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_gva; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_mbe; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_sbe; // @[DMA.scala:230:23] wire [1:0] _tlb_q_io_deq_bits_status_sxl; // @[DMA.scala:230:23] wire [1:0] _tlb_q_io_deq_bits_status_uxl; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_sd_rv32; // @[DMA.scala:230:23] wire [7:0] _tlb_q_io_deq_bits_status_zero1; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_tsr; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_tw; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_tvm; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_mxr; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_sum; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_mprv; // @[DMA.scala:230:23] wire [1:0] _tlb_q_io_deq_bits_status_xs; // @[DMA.scala:230:23] wire [1:0] _tlb_q_io_deq_bits_status_fs; // @[DMA.scala:230:23] wire [1:0] _tlb_q_io_deq_bits_status_mpp; // @[DMA.scala:230:23] wire [1:0] _tlb_q_io_deq_bits_status_vs; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_spp; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_mpie; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_ube; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_spie; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_upie; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_mie; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_hie; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_sie; // @[DMA.scala:230:23] wire _tlb_q_io_deq_bits_status_uie; // @[DMA.scala:230:23] wire _tlb_arb_io_out_valid; // @[DMA.scala:226:25] wire [2:0] _tlb_arb_io_out_bits_tl_a_opcode; // @[DMA.scala:226:25] wire [2:0] _tlb_arb_io_out_bits_tl_a_param; // @[DMA.scala:226:25] wire [3:0] _tlb_arb_io_out_bits_tl_a_size; // @[DMA.scala:226:25] wire [5:0] _tlb_arb_io_out_bits_tl_a_source; // @[DMA.scala:226:25] wire [31:0] _tlb_arb_io_out_bits_tl_a_address; // @[DMA.scala:226:25] wire [15:0] _tlb_arb_io_out_bits_tl_a_mask; // @[DMA.scala:226:25] wire [127:0] _tlb_arb_io_out_bits_tl_a_data; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_tl_a_corrupt; // @[DMA.scala:226:25] wire [38:0] _tlb_arb_io_out_bits_vaddr; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_debug; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_cease; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_wfi; // @[DMA.scala:226:25] wire [31:0] _tlb_arb_io_out_bits_status_isa; // @[DMA.scala:226:25] wire [1:0] _tlb_arb_io_out_bits_status_dprv; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_dv; // @[DMA.scala:226:25] wire [1:0] _tlb_arb_io_out_bits_status_prv; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_v; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_sd; // @[DMA.scala:226:25] wire [22:0] _tlb_arb_io_out_bits_status_zero2; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_mpv; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_gva; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_mbe; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_sbe; // @[DMA.scala:226:25] wire [1:0] _tlb_arb_io_out_bits_status_sxl; // @[DMA.scala:226:25] wire [1:0] _tlb_arb_io_out_bits_status_uxl; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_sd_rv32; // @[DMA.scala:226:25] wire [7:0] _tlb_arb_io_out_bits_status_zero1; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_tsr; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_tw; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_tvm; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_mxr; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_sum; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_mprv; // @[DMA.scala:226:25] wire [1:0] _tlb_arb_io_out_bits_status_xs; // @[DMA.scala:226:25] wire [1:0] _tlb_arb_io_out_bits_status_fs; // @[DMA.scala:226:25] wire [1:0] _tlb_arb_io_out_bits_status_mpp; // @[DMA.scala:226:25] wire [1:0] _tlb_arb_io_out_bits_status_vs; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_spp; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_mpie; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_ube; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_spie; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_upie; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_mie; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_hie; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_sie; // @[DMA.scala:226:25] wire _tlb_arb_io_out_bits_status_uie; // @[DMA.scala:226:25] wire auto_out_a_ready_0 = auto_out_a_ready; // @[DMA.scala:138:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[DMA.scala:138:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DMA.scala:138:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DMA.scala:138:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DMA.scala:138:9] wire [5:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[DMA.scala:138:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DMA.scala:138:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DMA.scala:138:9] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DMA.scala:138:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DMA.scala:138:9] wire io_req_valid_0 = io_req_valid; // @[DMA.scala:138:9] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[DMA.scala:138:9] wire [13:0] io_req_bits_spaddr_0 = io_req_bits_spaddr; // @[DMA.scala:138:9] wire io_req_bits_is_acc_0 = io_req_bits_is_acc; // @[DMA.scala:138:9] wire io_req_bits_accumulate_0 = io_req_bits_accumulate; // @[DMA.scala:138:9] wire io_req_bits_has_acc_bitwidth_0 = io_req_bits_has_acc_bitwidth; // @[DMA.scala:138:9] wire [31:0] io_req_bits_scale_0 = io_req_bits_scale; // @[DMA.scala:138:9] wire io_req_bits_status_debug_0 = io_req_bits_status_debug; // @[DMA.scala:138:9] wire io_req_bits_status_cease_0 = io_req_bits_status_cease; // @[DMA.scala:138:9] wire io_req_bits_status_wfi_0 = io_req_bits_status_wfi; // @[DMA.scala:138:9] wire [31:0] io_req_bits_status_isa_0 = io_req_bits_status_isa; // @[DMA.scala:138:9] wire [1:0] io_req_bits_status_dprv_0 = io_req_bits_status_dprv; // @[DMA.scala:138:9] wire io_req_bits_status_dv_0 = io_req_bits_status_dv; // @[DMA.scala:138:9] wire [1:0] io_req_bits_status_prv_0 = io_req_bits_status_prv; // @[DMA.scala:138:9] wire io_req_bits_status_v_0 = io_req_bits_status_v; // @[DMA.scala:138:9] wire io_req_bits_status_sd_0 = io_req_bits_status_sd; // @[DMA.scala:138:9] wire [22:0] io_req_bits_status_zero2_0 = io_req_bits_status_zero2; // @[DMA.scala:138:9] wire io_req_bits_status_mpv_0 = io_req_bits_status_mpv; // @[DMA.scala:138:9] wire io_req_bits_status_gva_0 = io_req_bits_status_gva; // @[DMA.scala:138:9] wire io_req_bits_status_mbe_0 = io_req_bits_status_mbe; // @[DMA.scala:138:9] wire io_req_bits_status_sbe_0 = io_req_bits_status_sbe; // @[DMA.scala:138:9] wire [1:0] io_req_bits_status_sxl_0 = io_req_bits_status_sxl; // @[DMA.scala:138:9] wire [1:0] io_req_bits_status_uxl_0 = io_req_bits_status_uxl; // @[DMA.scala:138:9] wire io_req_bits_status_sd_rv32_0 = io_req_bits_status_sd_rv32; // @[DMA.scala:138:9] wire [7:0] io_req_bits_status_zero1_0 = io_req_bits_status_zero1; // @[DMA.scala:138:9] wire io_req_bits_status_tsr_0 = io_req_bits_status_tsr; // @[DMA.scala:138:9] wire io_req_bits_status_tw_0 = io_req_bits_status_tw; // @[DMA.scala:138:9] wire io_req_bits_status_tvm_0 = io_req_bits_status_tvm; // @[DMA.scala:138:9] wire io_req_bits_status_mxr_0 = io_req_bits_status_mxr; // @[DMA.scala:138:9] wire io_req_bits_status_sum_0 = io_req_bits_status_sum; // @[DMA.scala:138:9] wire io_req_bits_status_mprv_0 = io_req_bits_status_mprv; // @[DMA.scala:138:9] wire [1:0] io_req_bits_status_xs_0 = io_req_bits_status_xs; // @[DMA.scala:138:9] wire [1:0] io_req_bits_status_fs_0 = io_req_bits_status_fs; // @[DMA.scala:138:9] wire [1:0] io_req_bits_status_mpp_0 = io_req_bits_status_mpp; // @[DMA.scala:138:9] wire [1:0] io_req_bits_status_vs_0 = io_req_bits_status_vs; // @[DMA.scala:138:9] wire io_req_bits_status_spp_0 = io_req_bits_status_spp; // @[DMA.scala:138:9] wire io_req_bits_status_mpie_0 = io_req_bits_status_mpie; // @[DMA.scala:138:9] wire io_req_bits_status_ube_0 = io_req_bits_status_ube; // @[DMA.scala:138:9] wire io_req_bits_status_spie_0 = io_req_bits_status_spie; // @[DMA.scala:138:9] wire io_req_bits_status_upie_0 = io_req_bits_status_upie; // @[DMA.scala:138:9] wire io_req_bits_status_mie_0 = io_req_bits_status_mie; // @[DMA.scala:138:9] wire io_req_bits_status_hie_0 = io_req_bits_status_hie; // @[DMA.scala:138:9] wire io_req_bits_status_sie_0 = io_req_bits_status_sie; // @[DMA.scala:138:9] wire io_req_bits_status_uie_0 = io_req_bits_status_uie; // @[DMA.scala:138:9] wire [15:0] io_req_bits_len_0 = io_req_bits_len; // @[DMA.scala:138:9] wire [15:0] io_req_bits_repeats_0 = io_req_bits_repeats; // @[DMA.scala:138:9] wire [7:0] io_req_bits_pixel_repeats_0 = io_req_bits_pixel_repeats; // @[DMA.scala:138:9] wire [15:0] io_req_bits_block_stride_0 = io_req_bits_block_stride; // @[DMA.scala:138:9] wire [7:0] io_req_bits_cmd_id_0 = io_req_bits_cmd_id; // @[DMA.scala:138:9] wire io_reserve_ready_0 = io_reserve_ready; // @[DMA.scala:138:9] wire [5:0] io_reserve_xactid_0 = io_reserve_xactid; // @[DMA.scala:138:9] wire io_beatData_ready_0 = io_beatData_ready; // @[DMA.scala:138:9] wire io_tlb_resp_miss_0 = io_tlb_resp_miss; // @[DMA.scala:138:9] wire [31:0] io_tlb_resp_paddr_0 = io_tlb_resp_paddr; // @[DMA.scala:138:9] wire [39:0] io_tlb_resp_gpa_0 = io_tlb_resp_gpa; // @[DMA.scala:138:9] wire io_tlb_resp_pf_ld_0 = io_tlb_resp_pf_ld; // @[DMA.scala:138:9] wire io_tlb_resp_pf_st_0 = io_tlb_resp_pf_st; // @[DMA.scala:138:9] wire io_tlb_resp_pf_inst_0 = io_tlb_resp_pf_inst; // @[DMA.scala:138:9] wire io_tlb_resp_ae_ld_0 = io_tlb_resp_ae_ld; // @[DMA.scala:138:9] wire io_tlb_resp_ae_st_0 = io_tlb_resp_ae_st; // @[DMA.scala:138:9] wire io_tlb_resp_ae_inst_0 = io_tlb_resp_ae_inst; // @[DMA.scala:138:9] wire io_tlb_resp_cacheable_0 = io_tlb_resp_cacheable; // @[DMA.scala:138:9] wire io_tlb_resp_must_alloc_0 = io_tlb_resp_must_alloc; // @[DMA.scala:138:9] wire io_tlb_resp_prefetchable_0 = io_tlb_resp_prefetchable; // @[DMA.scala:138:9] wire [4:0] io_tlb_resp_cmd_0 = io_tlb_resp_cmd; // @[DMA.scala:138:9] wire io_flush_0 = io_flush; // @[DMA.scala:138:9] wire io_counter_external_reset_0 = io_counter_external_reset; // @[DMA.scala:138:9] wire _printf_T = reset; // @[annotations.scala:102:49] wire io_tlb_req_bits_tlb_req_passthrough = 1'h0; // @[DMA.scala:138:9] wire io_tlb_req_bits_tlb_req_v = 1'h0; // @[DMA.scala:138:9] wire io_tlb_resp_gpa_is_pte = 1'h0; // @[DMA.scala:138:9] wire io_tlb_resp_gf_ld = 1'h0; // @[DMA.scala:138:9] wire io_tlb_resp_gf_st = 1'h0; // @[DMA.scala:138:9] wire io_tlb_resp_gf_inst = 1'h0; // @[DMA.scala:138:9] wire io_tlb_resp_ma_ld = 1'h0; // @[DMA.scala:138:9] wire io_tlb_resp_ma_st = 1'h0; // @[DMA.scala:138:9] wire io_tlb_resp_ma_inst = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_0 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_1 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_2 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_3 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_4 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_5 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_6 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_7 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_8 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_9 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_10 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_11 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_12 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_13 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_14 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_15 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_16 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_17 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_21 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_22 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_23 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_24 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_25 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_26 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_27 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_28 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_29 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_30 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_31 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_32 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_33 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_34 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_35 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_36 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_37 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_38 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_39 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_40 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_41 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_42 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_43 = 1'h0; // @[DMA.scala:138:9] wire io_counter_event_signal_44 = 1'h0; // @[DMA.scala:138:9] wire _get_legal_T_8 = 1'h0; // @[Parameters.scala:137:59] wire _get_legal_T_9 = 1'h0; // @[Parameters.scala:684:54] wire _get_legal_T_14 = 1'h0; // @[Parameters.scala:137:31] wire _get_legal_T_23 = 1'h0; // @[Parameters.scala:137:59] wire _get_legal_T_28 = 1'h0; // @[Parameters.scala:137:59] wire _get_legal_T_33 = 1'h0; // @[Parameters.scala:137:59] wire _get_legal_T_38 = 1'h0; // @[Parameters.scala:137:59] wire _get_legal_T_43 = 1'h0; // @[Parameters.scala:137:59] wire _get_legal_T_48 = 1'h0; // @[Parameters.scala:137:59] wire _get_legal_T_53 = 1'h0; // @[Parameters.scala:137:59] wire _get_legal_T_62 = 1'h0; // @[Parameters.scala:686:26] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire get_a_mask_sub_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_sub_sub_2_2 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_sub_sub_3_2 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_sub_2_2 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_sub_3_2 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_sub_4_2 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_sub_5_2 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_sub_6_2 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_sub_7_2 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_eq_1 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_eq_2 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_eq_3 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_eq_4 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_eq_5 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_eq_6 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_eq_7 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_eq_8 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_eq_9 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_eq_10 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_eq_11 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_eq_12 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_eq_13 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_eq_14 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire get_a_mask_eq_15 = 1'h0; // @[Misc.scala:214:27] wire _get_a_mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire untranslated_a_bits_tl_a_corrupt = 1'h0; // @[DMA.scala:218:30] wire [1:0] io_tlb_req_bits_tlb_req_size = 2'h0; // @[DMA.scala:138:9] wire [1:0] io_tlb_req_bits_tlb_req_prv = 2'h0; // @[DMA.scala:138:9] wire [1:0] io_tlb_resp_size = 2'h0; // @[DMA.scala:138:9] wire [1:0] _get_legal_T_15 = 2'h0; // @[Parameters.scala:137:41] wire [2:0] io_reserve_entry_lg_len_req = 3'h0; // @[DMA.scala:138:9] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] untranslated_a_bits_tl_a_param = 3'h0; // @[DMA.scala:218:30] wire [4:0] io_tlb_req_bits_tlb_req_cmd = 5'h0; // @[DMA.scala:138:9] wire [31:0] io_counter_external_values_0 = 32'h0; // @[DMA.scala:138:9] wire [31:0] io_counter_external_values_1 = 32'h0; // @[DMA.scala:138:9] wire [31:0] io_counter_external_values_2 = 32'h0; // @[DMA.scala:138:9] wire [31:0] io_counter_external_values_3 = 32'h0; // @[DMA.scala:138:9] wire [31:0] io_counter_external_values_5 = 32'h0; // @[DMA.scala:138:9] wire [31:0] io_counter_external_values_6 = 32'h0; // @[DMA.scala:138:9] wire [31:0] io_counter_external_values_7 = 32'h0; // @[DMA.scala:138:9] wire [31:0] get_address = 32'h0; // @[Edges.scala:460:17] wire [31:0] untranslated_a_bits_tl_a_address = 32'h0; // @[DMA.scala:218:30] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_18 = 1'h1; // @[Parameters.scala:137:59] wire _get_legal_T_54 = 1'h1; // @[Parameters.scala:685:42] wire _get_legal_T_55 = 1'h1; // @[Parameters.scala:685:42] wire _get_legal_T_56 = 1'h1; // @[Parameters.scala:685:42] wire _get_legal_T_57 = 1'h1; // @[Parameters.scala:685:42] wire _get_legal_T_58 = 1'h1; // @[Parameters.scala:685:42] wire _get_legal_T_59 = 1'h1; // @[Parameters.scala:685:42] wire _get_legal_T_60 = 1'h1; // @[Parameters.scala:685:42] wire get_a_mask_sub_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire get_a_mask_sub_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire get_a_mask_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire get_a_mask_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire get_a_mask_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire get_a_mask_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire get_a_mask_nbit = 1'h1; // @[Misc.scala:211:20] wire get_a_mask_eq = 1'h1; // @[Misc.scala:214:27] wire retry_a_ready = 1'h1; // @[DMA.scala:225:23] wire [127:0] get_data = 128'h0; // @[Edges.scala:460:17] wire [127:0] untranslated_a_bits_tl_a_data = 128'h0; // @[DMA.scala:218:30] wire [2:0] read_packets_0_lg_size = 3'h4; // @[DMA.scala:188:24] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] untranslated_a_bits_tl_a_opcode = 3'h4; // @[DMA.scala:218:30] wire [32:0] _get_legal_T_50 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _get_legal_T_51 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _get_legal_T_52 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _get_legal_T_46 = 33'h10000000; // @[Parameters.scala:137:46] wire [32:0] _get_legal_T_47 = 33'h10000000; // @[Parameters.scala:137:46] wire [29:0] _get_legal_T_45 = 30'h10000000; // @[Parameters.scala:137:41] wire [32:0] _get_legal_T_36 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _get_legal_T_37 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _get_legal_T_41 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _get_legal_T_42 = 33'h8000000; // @[Parameters.scala:137:46] wire [28:0] _get_legal_T_35 = 29'h8000000; // @[Parameters.scala:137:41] wire [28:0] _get_legal_T_40 = 29'h8000000; // @[Parameters.scala:137:41] wire [32:0] _get_legal_T_31 = 33'h2000000; // @[Parameters.scala:137:46] wire [32:0] _get_legal_T_32 = 33'h2000000; // @[Parameters.scala:137:46] wire [26:0] _get_legal_T_30 = 27'h2000000; // @[Parameters.scala:137:41] wire [32:0] _get_legal_T_21 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _get_legal_T_22 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _get_legal_T_26 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _get_legal_T_27 = 33'h10000; // @[Parameters.scala:137:46] wire [17:0] _get_legal_T_20 = 18'h10000; // @[Parameters.scala:137:41] wire [17:0] _get_legal_T_25 = 18'h10000; // @[Parameters.scala:137:41] wire [32:0] _get_legal_T_16 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _get_legal_T_17 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _get_legal_T_6 = 33'h3000; // @[Parameters.scala:137:46] wire [32:0] _get_legal_T_7 = 33'h3000; // @[Parameters.scala:137:46] wire [14:0] _get_legal_T_5 = 15'h3000; // @[Parameters.scala:137:41] wire [2:0] read_packets_2_lg_size = 3'h6; // @[DMA.scala:188:24] wire [6:0] read_packets_2_size = 7'h40; // @[DMA.scala:188:24] wire [2:0] read_packets_1_lg_size = 3'h5; // @[DMA.scala:188:24] wire [6:0] read_packets_1_size = 7'h20; // @[DMA.scala:188:24] wire [6:0] read_packets_0_size = 7'h10; // @[DMA.scala:188:24] wire [31:0] _get_legal_T_49 = 32'h80000000; // @[Parameters.scala:137:31] wire [28:0] _get_legal_T_44 = 29'h10000000; // @[Parameters.scala:137:31] wire [27:0] _get_legal_T_34 = 28'h8000000; // @[Parameters.scala:137:31] wire [27:0] _get_legal_T_39 = 28'h8000000; // @[Parameters.scala:137:31] wire [25:0] _get_legal_T_29 = 26'h2000000; // @[Parameters.scala:137:31] wire [16:0] _get_legal_T_19 = 17'h10000; // @[Parameters.scala:137:31] wire [16:0] _get_legal_T_24 = 17'h10000; // @[Parameters.scala:137:31] wire [13:0] _get_legal_T_4 = 14'h3000; // @[Parameters.scala:137:31] wire nodeOut_a_ready = auto_out_a_ready_0; // @[DMA.scala:138:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[DMA.scala:138:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DMA.scala:138:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DMA.scala:138:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DMA.scala:138:9] wire [5:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[DMA.scala:138:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DMA.scala:138:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DMA.scala:138:9] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DMA.scala:138:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DMA.scala:138:9] wire state_machine_ready_for_req; // @[DMA.scala:165:47] wire _io_reserve_valid_T_1; // @[DMA.scala:253:51] wire [5:0] read_packet_shift; // @[DMA.scala:198:10] wire [5:0] get_source = io_reserve_xactid_0; // @[Edges.scala:460:17] wire [6:0] read_packet_bytes_read; // @[DMA.scala:198:10] assign nodeOut_d_ready = io_beatData_ready_0; // @[DMA.scala:138:9] wire io_beatData_bits_last_last; // @[Edges.scala:232:33] wire io_counter_event_signal_19_0 = io_tlb_resp_miss_0; // @[DMA.scala:138:9] assign nodeOut_a_bits_address = io_tlb_resp_paddr_0; // @[DMA.scala:138:9] wire [2:0] auto_out_a_bits_opcode_0; // @[DMA.scala:138:9] wire [2:0] auto_out_a_bits_param_0; // @[DMA.scala:138:9] wire [3:0] auto_out_a_bits_size_0; // @[DMA.scala:138:9] wire [5:0] auto_out_a_bits_source_0; // @[DMA.scala:138:9] wire [31:0] auto_out_a_bits_address_0; // @[DMA.scala:138:9] wire [15:0] auto_out_a_bits_mask_0; // @[DMA.scala:138:9] wire [127:0] auto_out_a_bits_data_0; // @[DMA.scala:138:9] wire auto_out_a_bits_corrupt_0; // @[DMA.scala:138:9] wire auto_out_a_valid_0; // @[DMA.scala:138:9] wire auto_out_d_ready_0; // @[DMA.scala:138:9] wire io_req_ready_0; // @[DMA.scala:138:9] wire [5:0] io_reserve_entry_shift_0; // @[DMA.scala:138:9] wire [13:0] io_reserve_entry_addr_0; // @[DMA.scala:138:9] wire io_reserve_entry_is_acc_0; // @[DMA.scala:138:9] wire io_reserve_entry_accumulate_0; // @[DMA.scala:138:9] wire io_reserve_entry_has_acc_bitwidth_0; // @[DMA.scala:138:9] wire [31:0] io_reserve_entry_scale_0; // @[DMA.scala:138:9] wire [15:0] io_reserve_entry_repeats_0; // @[DMA.scala:138:9] wire [7:0] io_reserve_entry_pixel_repeats_0; // @[DMA.scala:138:9] wire [15:0] io_reserve_entry_len_0; // @[DMA.scala:138:9] wire [15:0] io_reserve_entry_block_stride_0; // @[DMA.scala:138:9] wire [8:0] io_reserve_entry_spad_row_offset_0; // @[DMA.scala:138:9] wire [6:0] io_reserve_entry_bytes_to_read_0; // @[DMA.scala:138:9] wire [2:0] io_reserve_entry_cmd_id_0; // @[DMA.scala:138:9] wire io_reserve_valid_0; // @[DMA.scala:138:9] wire [5:0] io_beatData_bits_xactid_0; // @[DMA.scala:138:9] wire [127:0] io_beatData_bits_data_0; // @[DMA.scala:138:9] wire [2:0] io_beatData_bits_lg_len_req_0; // @[DMA.scala:138:9] wire io_beatData_bits_last_0; // @[DMA.scala:138:9] wire io_beatData_valid_0; // @[DMA.scala:138:9] wire [39:0] io_tlb_req_bits_tlb_req_vaddr_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_debug_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_cease_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_wfi_0; // @[DMA.scala:138:9] wire [31:0] io_tlb_req_bits_status_isa_0; // @[DMA.scala:138:9] wire [1:0] io_tlb_req_bits_status_dprv_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_dv_0; // @[DMA.scala:138:9] wire [1:0] io_tlb_req_bits_status_prv_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_v_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_sd_0; // @[DMA.scala:138:9] wire [22:0] io_tlb_req_bits_status_zero2_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_mpv_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_gva_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_mbe_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_sbe_0; // @[DMA.scala:138:9] wire [1:0] io_tlb_req_bits_status_sxl_0; // @[DMA.scala:138:9] wire [1:0] io_tlb_req_bits_status_uxl_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_sd_rv32_0; // @[DMA.scala:138:9] wire [7:0] io_tlb_req_bits_status_zero1_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_tsr_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_tw_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_tvm_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_mxr_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_sum_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_mprv_0; // @[DMA.scala:138:9] wire [1:0] io_tlb_req_bits_status_xs_0; // @[DMA.scala:138:9] wire [1:0] io_tlb_req_bits_status_fs_0; // @[DMA.scala:138:9] wire [1:0] io_tlb_req_bits_status_mpp_0; // @[DMA.scala:138:9] wire [1:0] io_tlb_req_bits_status_vs_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_spp_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_mpie_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_ube_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_spie_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_upie_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_mie_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_hie_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_sie_0; // @[DMA.scala:138:9] wire io_tlb_req_bits_status_uie_0; // @[DMA.scala:138:9] wire io_tlb_req_valid_0; // @[DMA.scala:138:9] wire io_counter_event_signal_18_0; // @[DMA.scala:138:9] wire io_counter_event_signal_20_0; // @[DMA.scala:138:9] wire [31:0] io_counter_external_values_4_0; // @[DMA.scala:138:9] wire _nodeOut_a_valid_T_1; // @[DMA.scala:249:44] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DMA.scala:138:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DMA.scala:138:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[DMA.scala:138:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DMA.scala:138:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[DMA.scala:138:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DMA.scala:138:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DMA.scala:138:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DMA.scala:138:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[DMA.scala:138:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DMA.scala:138:9] assign io_beatData_valid_0 = nodeOut_d_valid; // @[DMA.scala:138:9] assign io_beatData_bits_xactid_0 = nodeOut_d_bits_source; // @[DMA.scala:138:9] assign io_beatData_bits_data_0 = nodeOut_d_bits_data; // @[DMA.scala:138:9] reg state; // @[DMA.scala:157:24] assign io_counter_event_signal_18_0 = state; // @[DMA.scala:138:9, :157:24] wire _untranslated_a_valid_T = state; // @[DMA.scala:157:24, :219:35] wire _io_reserve_valid_T = state; // @[DMA.scala:157:24, :253:31] reg [39:0] req_vaddr; // @[DMA.scala:159:18] reg [13:0] req_spaddr; // @[DMA.scala:159:18] reg req_is_acc; // @[DMA.scala:159:18] assign io_reserve_entry_is_acc_0 = req_is_acc; // @[DMA.scala:138:9, :159:18] reg req_accumulate; // @[DMA.scala:159:18] assign io_reserve_entry_accumulate_0 = req_accumulate; // @[DMA.scala:138:9, :159:18] reg req_has_acc_bitwidth; // @[DMA.scala:159:18] assign io_reserve_entry_has_acc_bitwidth_0 = req_has_acc_bitwidth; // @[DMA.scala:138:9, :159:18] reg [31:0] req_scale; // @[DMA.scala:159:18] assign io_reserve_entry_scale_0 = req_scale; // @[DMA.scala:138:9, :159:18] reg req_status_debug; // @[DMA.scala:159:18] wire untranslated_a_bits_status_debug = req_status_debug; // @[DMA.scala:159:18, :218:30] reg req_status_cease; // @[DMA.scala:159:18] wire untranslated_a_bits_status_cease = req_status_cease; // @[DMA.scala:159:18, :218:30] reg req_status_wfi; // @[DMA.scala:159:18] wire untranslated_a_bits_status_wfi = req_status_wfi; // @[DMA.scala:159:18, :218:30] reg [31:0] req_status_isa; // @[DMA.scala:159:18] wire [31:0] untranslated_a_bits_status_isa = req_status_isa; // @[DMA.scala:159:18, :218:30] reg [1:0] req_status_dprv; // @[DMA.scala:159:18] wire [1:0] untranslated_a_bits_status_dprv = req_status_dprv; // @[DMA.scala:159:18, :218:30] reg req_status_dv; // @[DMA.scala:159:18] wire untranslated_a_bits_status_dv = req_status_dv; // @[DMA.scala:159:18, :218:30] reg [1:0] req_status_prv; // @[DMA.scala:159:18] wire [1:0] untranslated_a_bits_status_prv = req_status_prv; // @[DMA.scala:159:18, :218:30] reg req_status_v; // @[DMA.scala:159:18] wire untranslated_a_bits_status_v = req_status_v; // @[DMA.scala:159:18, :218:30] reg req_status_sd; // @[DMA.scala:159:18] wire untranslated_a_bits_status_sd = req_status_sd; // @[DMA.scala:159:18, :218:30] reg [22:0] req_status_zero2; // @[DMA.scala:159:18] wire [22:0] untranslated_a_bits_status_zero2 = req_status_zero2; // @[DMA.scala:159:18, :218:30] reg req_status_mpv; // @[DMA.scala:159:18] wire untranslated_a_bits_status_mpv = req_status_mpv; // @[DMA.scala:159:18, :218:30] reg req_status_gva; // @[DMA.scala:159:18] wire untranslated_a_bits_status_gva = req_status_gva; // @[DMA.scala:159:18, :218:30] reg req_status_mbe; // @[DMA.scala:159:18] wire untranslated_a_bits_status_mbe = req_status_mbe; // @[DMA.scala:159:18, :218:30] reg req_status_sbe; // @[DMA.scala:159:18] wire untranslated_a_bits_status_sbe = req_status_sbe; // @[DMA.scala:159:18, :218:30] reg [1:0] req_status_sxl; // @[DMA.scala:159:18] wire [1:0] untranslated_a_bits_status_sxl = req_status_sxl; // @[DMA.scala:159:18, :218:30] reg [1:0] req_status_uxl; // @[DMA.scala:159:18] wire [1:0] untranslated_a_bits_status_uxl = req_status_uxl; // @[DMA.scala:159:18, :218:30] reg req_status_sd_rv32; // @[DMA.scala:159:18] wire untranslated_a_bits_status_sd_rv32 = req_status_sd_rv32; // @[DMA.scala:159:18, :218:30] reg [7:0] req_status_zero1; // @[DMA.scala:159:18] wire [7:0] untranslated_a_bits_status_zero1 = req_status_zero1; // @[DMA.scala:159:18, :218:30] reg req_status_tsr; // @[DMA.scala:159:18] wire untranslated_a_bits_status_tsr = req_status_tsr; // @[DMA.scala:159:18, :218:30] reg req_status_tw; // @[DMA.scala:159:18] wire untranslated_a_bits_status_tw = req_status_tw; // @[DMA.scala:159:18, :218:30] reg req_status_tvm; // @[DMA.scala:159:18] wire untranslated_a_bits_status_tvm = req_status_tvm; // @[DMA.scala:159:18, :218:30] reg req_status_mxr; // @[DMA.scala:159:18] wire untranslated_a_bits_status_mxr = req_status_mxr; // @[DMA.scala:159:18, :218:30] reg req_status_sum; // @[DMA.scala:159:18] wire untranslated_a_bits_status_sum = req_status_sum; // @[DMA.scala:159:18, :218:30] reg req_status_mprv; // @[DMA.scala:159:18] wire untranslated_a_bits_status_mprv = req_status_mprv; // @[DMA.scala:159:18, :218:30] reg [1:0] req_status_xs; // @[DMA.scala:159:18] wire [1:0] untranslated_a_bits_status_xs = req_status_xs; // @[DMA.scala:159:18, :218:30] reg [1:0] req_status_fs; // @[DMA.scala:159:18] wire [1:0] untranslated_a_bits_status_fs = req_status_fs; // @[DMA.scala:159:18, :218:30] reg [1:0] req_status_mpp; // @[DMA.scala:159:18] wire [1:0] untranslated_a_bits_status_mpp = req_status_mpp; // @[DMA.scala:159:18, :218:30] reg [1:0] req_status_vs; // @[DMA.scala:159:18] wire [1:0] untranslated_a_bits_status_vs = req_status_vs; // @[DMA.scala:159:18, :218:30] reg req_status_spp; // @[DMA.scala:159:18] wire untranslated_a_bits_status_spp = req_status_spp; // @[DMA.scala:159:18, :218:30] reg req_status_mpie; // @[DMA.scala:159:18] wire untranslated_a_bits_status_mpie = req_status_mpie; // @[DMA.scala:159:18, :218:30] reg req_status_ube; // @[DMA.scala:159:18] wire untranslated_a_bits_status_ube = req_status_ube; // @[DMA.scala:159:18, :218:30] reg req_status_spie; // @[DMA.scala:159:18] wire untranslated_a_bits_status_spie = req_status_spie; // @[DMA.scala:159:18, :218:30] reg req_status_upie; // @[DMA.scala:159:18] wire untranslated_a_bits_status_upie = req_status_upie; // @[DMA.scala:159:18, :218:30] reg req_status_mie; // @[DMA.scala:159:18] wire untranslated_a_bits_status_mie = req_status_mie; // @[DMA.scala:159:18, :218:30] reg req_status_hie; // @[DMA.scala:159:18] wire untranslated_a_bits_status_hie = req_status_hie; // @[DMA.scala:159:18, :218:30] reg req_status_sie; // @[DMA.scala:159:18] wire untranslated_a_bits_status_sie = req_status_sie; // @[DMA.scala:159:18, :218:30] reg req_status_uie; // @[DMA.scala:159:18] wire untranslated_a_bits_status_uie = req_status_uie; // @[DMA.scala:159:18, :218:30] reg [15:0] req_len; // @[DMA.scala:159:18] assign io_reserve_entry_len_0 = req_len; // @[DMA.scala:138:9, :159:18] reg [15:0] req_repeats; // @[DMA.scala:159:18] assign io_reserve_entry_repeats_0 = req_repeats; // @[DMA.scala:138:9, :159:18] reg [7:0] req_pixel_repeats; // @[DMA.scala:159:18] assign io_reserve_entry_pixel_repeats_0 = req_pixel_repeats; // @[DMA.scala:138:9, :159:18] reg [15:0] req_block_stride; // @[DMA.scala:159:18] assign io_reserve_entry_block_stride_0 = req_block_stride; // @[DMA.scala:138:9, :159:18] reg [7:0] req_cmd_id; // @[DMA.scala:159:18] reg [5:0] bytesRequested; // @[DMA.scala:162:29] wire [18:0] _bytesLeft_T = {1'h0, req_len, 2'h0}; // @[DMA.scala:159:18, :163:55] wire [16:0] _bytesLeft_T_1 = {1'h0, req_len}; // @[DMA.scala:159:18, :163:98] wire [18:0] _bytesLeft_T_2 = req_has_acc_bitwidth ? _bytesLeft_T : {2'h0, _bytesLeft_T_1}; // @[DMA.scala:159:18, :163:{24,55,98}] wire [19:0] _bytesLeft_T_3 = {1'h0, _bytesLeft_T_2} - {14'h0, bytesRequested}; // @[DMA.scala:162:29, :163:{24,135}] wire [18:0] bytesLeft = _bytesLeft_T_3[18:0]; // @[DMA.scala:163:135] wire _state_machine_ready_for_req_T = ~state; // @[DMA.scala:157:24, :165:54] assign io_req_ready_0 = state_machine_ready_for_req; // @[DMA.scala:138:9, :165:47] wire [34:0] _read_packets_vaddr_aligned_to_size_T = req_vaddr[38:4]; // @[DMA.scala:159:18, :185:67] wire [38:0] read_packets_vaddr_aligned_to_size = {_read_packets_vaddr_aligned_to_size_T, 4'h0}; // @[DMA.scala:185:{61,67}] wire [38:0] read_packets_0_vaddr = read_packets_vaddr_aligned_to_size; // @[DMA.scala:185:61, :188:24] wire [3:0] read_packets_vaddr_offset = req_vaddr[3:0]; // @[DMA.scala:159:18, :186:42] wire [6:0] read_packets_0_bytes_read; // @[DMA.scala:188:24] wire [5:0] read_packets_0_shift; // @[DMA.scala:188:24] assign read_packets_0_shift = {2'h0, read_packets_vaddr_offset}; // @[DMA.scala:186:42, :188:24, :191:38] wire [5:0] _read_packets_packet_bytes_read_T = 6'h10 - read_packets_0_shift; // @[DMA.scala:188:24, :191:38] wire [4:0] _read_packets_packet_bytes_read_T_1 = _read_packets_packet_bytes_read_T[4:0]; // @[DMA.scala:191:38] wire [18:0] _GEN = {14'h0, _read_packets_packet_bytes_read_T_1}; // @[Util.scala:109:12] wire _read_packets_packet_bytes_read_T_2 = _GEN < bytesLeft; // @[Util.scala:109:12] wire [18:0] _read_packets_packet_bytes_read_T_3 = _read_packets_packet_bytes_read_T_2 ? _GEN : bytesLeft; // @[Util.scala:109:{8,12}] assign read_packets_0_bytes_read = _read_packets_packet_bytes_read_T_3[6:0]; // @[Util.scala:109:8] wire [33:0] _read_packets_vaddr_aligned_to_size_T_1 = req_vaddr[38:5]; // @[DMA.scala:159:18, :185:67] wire [38:0] read_packets_vaddr_aligned_to_size_1 = {_read_packets_vaddr_aligned_to_size_T_1, 5'h0}; // @[DMA.scala:185:{61,67}] wire [38:0] read_packets_1_vaddr = read_packets_vaddr_aligned_to_size_1; // @[DMA.scala:185:61, :188:24] wire [4:0] read_packets_vaddr_offset_1 = req_vaddr[4:0]; // @[DMA.scala:159:18, :186:42] wire [6:0] read_packets_1_bytes_read; // @[DMA.scala:188:24] wire [5:0] read_packets_1_shift; // @[DMA.scala:188:24] wire [6:0] _read_packets_packet_bytes_read_T_4 = 7'h20 - {2'h0, read_packets_vaddr_offset_1}; // @[DMA.scala:186:42, :191:38] wire [5:0] _read_packets_packet_bytes_read_T_5 = _read_packets_packet_bytes_read_T_4[5:0]; // @[DMA.scala:191:38] wire [18:0] _GEN_0 = {13'h0, _read_packets_packet_bytes_read_T_5}; // @[Util.scala:109:12] wire _read_packets_packet_bytes_read_T_6 = _GEN_0 < bytesLeft; // @[Util.scala:109:12] wire [18:0] _read_packets_packet_bytes_read_T_7 = _read_packets_packet_bytes_read_T_6 ? _GEN_0 : bytesLeft; // @[Util.scala:109:{8,12}] assign read_packets_1_bytes_read = _read_packets_packet_bytes_read_T_7[6:0]; // @[Util.scala:109:8] assign read_packets_1_shift = {1'h0, read_packets_vaddr_offset_1}; // @[DMA.scala:186:42, :188:24, :192:20] wire [32:0] _read_packets_vaddr_aligned_to_size_T_2 = req_vaddr[38:6]; // @[DMA.scala:159:18, :185:67] wire [38:0] read_packets_vaddr_aligned_to_size_2 = {_read_packets_vaddr_aligned_to_size_T_2, 6'h0}; // @[DMA.scala:185:{61,67}] wire [38:0] read_packets_2_vaddr = read_packets_vaddr_aligned_to_size_2; // @[DMA.scala:185:61, :188:24] wire [5:0] read_packets_vaddr_offset_2 = req_vaddr[5:0]; // @[DMA.scala:159:18, :186:42] wire [5:0] read_packets_2_shift = read_packets_vaddr_offset_2; // @[DMA.scala:186:42, :188:24] wire [6:0] read_packets_2_bytes_read; // @[DMA.scala:188:24] wire [7:0] _read_packets_packet_bytes_read_T_8 = 8'h40 - {2'h0, read_packets_vaddr_offset_2}; // @[DMA.scala:186:42, :191:38] wire [6:0] _read_packets_packet_bytes_read_T_9 = _read_packets_packet_bytes_read_T_8[6:0]; // @[DMA.scala:191:38] wire [18:0] _GEN_1 = {12'h0, _read_packets_packet_bytes_read_T_9}; // @[Util.scala:109:12] wire _read_packets_packet_bytes_read_T_10 = _GEN_1 < bytesLeft; // @[Util.scala:109:12] wire [18:0] _read_packets_packet_bytes_read_T_11 = _read_packets_packet_bytes_read_T_10 ? _GEN_1 : bytesLeft; // @[Util.scala:109:{8,12}] assign read_packets_2_bytes_read = _read_packets_packet_bytes_read_T_11[6:0]; // @[Util.scala:109:8] wire _read_packet_T = read_packets_1_bytes_read > read_packets_0_bytes_read; // @[DMA.scala:188:24, :198:24] wire [6:0] _read_packet_T_1_size = _read_packet_T ? 7'h20 : 7'h10; // @[DMA.scala:198:{10,24}] wire [2:0] _read_packet_T_1_lg_size = {2'h2, _read_packet_T}; // @[DMA.scala:198:{10,24}] wire [6:0] _read_packet_T_1_bytes_read = _read_packet_T ? read_packets_1_bytes_read : read_packets_0_bytes_read; // @[DMA.scala:188:24, :198:{10,24}] wire [5:0] _read_packet_T_1_shift = _read_packet_T ? read_packets_1_shift : read_packets_0_shift; // @[DMA.scala:188:24, :198:{10,24}] wire [38:0] _read_packet_T_1_vaddr = _read_packet_T ? read_packets_1_vaddr : read_packets_0_vaddr; // @[DMA.scala:188:24, :198:{10,24}] wire _read_packet_T_2 = read_packets_2_bytes_read > _read_packet_T_1_bytes_read; // @[DMA.scala:188:24, :198:{10,24}] wire [6:0] read_packet_size = _read_packet_T_2 ? 7'h40 : _read_packet_T_1_size; // @[DMA.scala:198:{10,24}] wire [2:0] read_packet_lg_size = _read_packet_T_2 ? 3'h6 : _read_packet_T_1_lg_size; // @[DMA.scala:198:{10,24}] assign read_packet_bytes_read = _read_packet_T_2 ? read_packets_2_bytes_read : _read_packet_T_1_bytes_read; // @[DMA.scala:188:24, :198:{10,24}] assign read_packet_shift = _read_packet_T_2 ? read_packets_2_shift : _read_packet_T_1_shift; // @[DMA.scala:188:24, :198:{10,24}] wire [38:0] read_packet_vaddr = _read_packet_T_2 ? read_packets_2_vaddr : _read_packet_T_1_vaddr; // @[DMA.scala:188:24, :198:{10,24}] assign io_reserve_entry_bytes_to_read_0 = read_packet_bytes_read; // @[DMA.scala:138:9, :198:10] assign io_reserve_entry_shift_0 = read_packet_shift; // @[DMA.scala:138:9, :198:10] wire [38:0] untranslated_a_bits_vaddr = read_packet_vaddr; // @[DMA.scala:198:10, :218:30] wire _get_legal_T_11 = read_packet_lg_size != 3'h7; // @[Parameters.scala:92:38] wire _get_legal_T_12 = _get_legal_T_11; // @[Parameters.scala:92:{33,38}] wire _get_legal_T_13 = _get_legal_T_12; // @[Parameters.scala:684:29] wire _get_legal_T_61 = _get_legal_T_13; // @[Parameters.scala:684:{29,54}] wire get_legal = _get_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [3:0] untranslated_a_bits_tl_a_size = get_size; // @[Edges.scala:460:17] wire [5:0] untranslated_a_bits_tl_a_source = get_source; // @[Edges.scala:460:17] wire [15:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [15:0] untranslated_a_bits_tl_a_mask = get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_2 = {1'h0, read_packet_lg_size}; // @[Edges.scala:463:15] assign get_size = _GEN_2; // @[Edges.scala:460:17, :463:15] wire [3:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_2; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_sub_0_1 = read_packet_lg_size[2]; // @[Misc.scala:206:21] wire get_a_mask_sub_sub_sub_1_1 = get_a_mask_sub_sub_sub_sub_0_1; // @[Misc.scala:206:21, :215:29] wire get_a_mask_sub_sub_sub_size = get_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire _get_a_mask_sub_sub_sub_acc_T = get_a_mask_sub_sub_sub_size; // @[Misc.scala:209:26, :215:38] wire get_a_mask_sub_sub_sub_0_1 = get_a_mask_sub_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1; // @[Misc.scala:215:29] wire get_a_mask_sub_sub_2_1 = get_a_mask_sub_sub_sub_1_1; // @[Misc.scala:215:29] wire get_a_mask_sub_sub_3_1 = get_a_mask_sub_sub_sub_1_1; // @[Misc.scala:215:29] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size; // @[Misc.scala:209:26, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1; // @[Misc.scala:215:29] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1; // @[Misc.scala:215:29] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1; // @[Misc.scala:215:29] wire get_a_mask_sub_4_1 = get_a_mask_sub_sub_2_1; // @[Misc.scala:215:29] wire get_a_mask_sub_5_1 = get_a_mask_sub_sub_2_1; // @[Misc.scala:215:29] wire get_a_mask_sub_6_1 = get_a_mask_sub_sub_3_1; // @[Misc.scala:215:29] wire get_a_mask_sub_7_1 = get_a_mask_sub_sub_3_1; // @[Misc.scala:215:29] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size; // @[Misc.scala:209:26, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_acc_1 = get_a_mask_sub_0_1; // @[Misc.scala:215:29] wire get_a_mask_acc_2 = get_a_mask_sub_1_1; // @[Misc.scala:215:29] wire get_a_mask_acc_3 = get_a_mask_sub_1_1; // @[Misc.scala:215:29] wire get_a_mask_acc_4 = get_a_mask_sub_2_1; // @[Misc.scala:215:29] wire get_a_mask_acc_5 = get_a_mask_sub_2_1; // @[Misc.scala:215:29] wire get_a_mask_acc_6 = get_a_mask_sub_3_1; // @[Misc.scala:215:29] wire get_a_mask_acc_7 = get_a_mask_sub_3_1; // @[Misc.scala:215:29] wire get_a_mask_acc_8 = get_a_mask_sub_4_1; // @[Misc.scala:215:29] wire get_a_mask_acc_9 = get_a_mask_sub_4_1; // @[Misc.scala:215:29] wire get_a_mask_acc_10 = get_a_mask_sub_5_1; // @[Misc.scala:215:29] wire get_a_mask_acc_11 = get_a_mask_sub_5_1; // @[Misc.scala:215:29] wire get_a_mask_acc_12 = get_a_mask_sub_6_1; // @[Misc.scala:215:29] wire get_a_mask_acc_13 = get_a_mask_sub_6_1; // @[Misc.scala:215:29] wire get_a_mask_acc_14 = get_a_mask_sub_7_1; // @[Misc.scala:215:29] wire get_a_mask_acc_15 = get_a_mask_sub_7_1; // @[Misc.scala:215:29] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire _get_a_mask_acc_T = get_a_mask_size; // @[Misc.scala:209:26, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 \| _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_lo = {get_a_mask_lo_lo_hi, get_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_lo_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo_hi = {get_a_mask_lo_hi_hi, get_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo_lo = {get_a_mask_acc_9, get_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_lo_hi = {get_a_mask_acc_11, get_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_lo = {get_a_mask_hi_lo_hi, get_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_hi_lo = {get_a_mask_acc_13, get_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi_hi = {get_a_mask_acc_15, get_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi_hi = {get_a_mask_hi_hi_hi, get_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire _untranslated_a_valid_T_1; // @[DMA.scala:219:55] wire untranslated_a_ready; // @[DMA.scala:218:30] wire untranslated_a_valid; // @[DMA.scala:218:30] assign _untranslated_a_valid_T_1 = _untranslated_a_valid_T & io_reserve_ready_0; // @[DMA.scala:138:9, :219:{35,55}] assign untranslated_a_valid = _untranslated_a_valid_T_1; // @[DMA.scala:218:30, :219:55] wire _retry_a_valid_T_2; // @[DMA.scala:245:47] wire [2:0] retry_a_bits_tl_a_opcode; // @[DMA.scala:225:23] wire [2:0] retry_a_bits_tl_a_param; // @[DMA.scala:225:23] wire [3:0] retry_a_bits_tl_a_size; // @[DMA.scala:225:23] wire [5:0] retry_a_bits_tl_a_source; // @[DMA.scala:225:23] wire [31:0] retry_a_bits_tl_a_address; // @[DMA.scala:225:23] wire [15:0] retry_a_bits_tl_a_mask; // @[DMA.scala:225:23] wire [127:0] retry_a_bits_tl_a_data; // @[DMA.scala:225:23] wire retry_a_bits_tl_a_corrupt; // @[DMA.scala:225:23] wire retry_a_bits_status_debug; // @[DMA.scala:225:23] wire retry_a_bits_status_cease; // @[DMA.scala:225:23] wire retry_a_bits_status_wfi; // @[DMA.scala:225:23] wire [31:0] retry_a_bits_status_isa; // @[DMA.scala:225:23] wire [1:0] retry_a_bits_status_dprv; // @[DMA.scala:225:23] wire retry_a_bits_status_dv; // @[DMA.scala:225:23] wire [1:0] retry_a_bits_status_prv; // @[DMA.scala:225:23] wire retry_a_bits_status_v; // @[DMA.scala:225:23] wire retry_a_bits_status_sd; // @[DMA.scala:225:23] wire [22:0] retry_a_bits_status_zero2; // @[DMA.scala:225:23] wire retry_a_bits_status_mpv; // @[DMA.scala:225:23] wire retry_a_bits_status_gva; // @[DMA.scala:225:23] wire retry_a_bits_status_mbe; // @[DMA.scala:225:23] wire retry_a_bits_status_sbe; // @[DMA.scala:225:23] wire [1:0] retry_a_bits_status_sxl; // @[DMA.scala:225:23] wire [1:0] retry_a_bits_status_uxl; // @[DMA.scala:225:23] wire retry_a_bits_status_sd_rv32; // @[DMA.scala:225:23] wire [7:0] retry_a_bits_status_zero1; // @[DMA.scala:225:23] wire retry_a_bits_status_tsr; // @[DMA.scala:225:23] wire retry_a_bits_status_tw; // @[DMA.scala:225:23] wire retry_a_bits_status_tvm; // @[DMA.scala:225:23] wire retry_a_bits_status_mxr; // @[DMA.scala:225:23] wire retry_a_bits_status_sum; // @[DMA.scala:225:23] wire retry_a_bits_status_mprv; // @[DMA.scala:225:23] wire [1:0] retry_a_bits_status_xs; // @[DMA.scala:225:23] wire [1:0] retry_a_bits_status_fs; // @[DMA.scala:225:23] wire [1:0] retry_a_bits_status_mpp; // @[DMA.scala:225:23] wire [1:0] retry_a_bits_status_vs; // @[DMA.scala:225:23] wire retry_a_bits_status_spp; // @[DMA.scala:225:23] wire retry_a_bits_status_mpie; // @[DMA.scala:225:23] wire retry_a_bits_status_ube; // @[DMA.scala:225:23] wire retry_a_bits_status_spie; // @[DMA.scala:225:23] wire retry_a_bits_status_upie; // @[DMA.scala:225:23] wire retry_a_bits_status_mie; // @[DMA.scala:225:23] wire retry_a_bits_status_hie; // @[DMA.scala:225:23] wire retry_a_bits_status_sie; // @[DMA.scala:225:23] wire retry_a_bits_status_uie; // @[DMA.scala:225:23] wire [38:0] retry_a_bits_vaddr; // @[DMA.scala:225:23] wire retry_a_valid; // @[DMA.scala:225:23] assign io_tlb_req_bits_tlb_req_vaddr_0 = {1'h0, _tlb_q_io_deq_bits_vaddr}; // @[DMA.scala:138:9, :230:23, :235:35] wire _retry_a_valid_T = ~nodeOut_a_ready; // @[DMA.scala:245:71] wire _retry_a_valid_T_1 = io_tlb_resp_miss_0 \| _retry_a_valid_T; // @[DMA.scala:138:9, :245:{68,71}] assign _retry_a_valid_T_2 = _translate_q_io_deq_valid & _retry_a_valid_T_1; // @[DMA.scala:241:29, :245:{47,68}] assign retry_a_valid = _retry_a_valid_T_2; // @[DMA.scala:225:23, :245:47] wire _nodeOut_a_valid_T = ~io_tlb_resp_miss_0; // @[DMA.scala:138:9, :249:47] assign _nodeOut_a_valid_T_1 = _translate_q_io_deq_valid & _nodeOut_a_valid_T; // @[DMA.scala:241:29, :249:{44,47}] assign nodeOut_a_valid = _nodeOut_a_valid_T_1; // @[DMA.scala:249:44] assign _io_reserve_valid_T_1 = _io_reserve_valid_T & untranslated_a_ready; // @[DMA.scala:218:30, :253:{31,51}] assign io_reserve_valid_0 = _io_reserve_valid_T_1; // @[DMA.scala:138:9, :253:51] assign io_reserve_entry_cmd_id_0 = req_cmd_id[2:0]; // @[DMA.scala:138:9, :159:18, :265:29] wire [5:0] _io_reserve_entry_addr_T = bytesRequested / 6'h10; // @[DMA.scala:162:29, :273:81] wire [5:0] _io_reserve_entry_addr_T_1 = req_has_acc_bitwidth ? 6'h0 : _io_reserve_entry_addr_T; // @[DMA.scala:159:18, :268:10, :273:81] wire [21:0] _io_reserve_entry_addr_T_2 = {6'h0, req_block_stride} * {16'h0, _io_reserve_entry_addr_T_1}; // @[DMA.scala:159:18, :267:60, :268:10] wire [22:0] _io_reserve_entry_addr_T_3 = {9'h0, req_spaddr} + {1'h0, _io_reserve_entry_addr_T_2}; // @[DMA.scala:159:18, :267:{41,60}] wire [21:0] _io_reserve_entry_addr_T_4 = _io_reserve_entry_addr_T_3[21:0]; // @[DMA.scala:267:41] assign io_reserve_entry_addr_0 = _io_reserve_entry_addr_T_4[13:0]; // @[DMA.scala:138:9, :267:{27,41}] wire [6:0] _GEN_3 = {1'h0, bytesRequested} % 7'h40; // @[DMA.scala:162:29, :274:82] wire [5:0] _io_reserve_entry_spad_row_offset_T = _GEN_3[5:0]; // @[DMA.scala:274:82] wire [5:0] _GEN_4 = bytesRequested % 6'h10; // @[DMA.scala:162:29, :274:116] wire [4:0] _io_reserve_entry_spad_row_offset_T_1 = _GEN_4[4:0]; // @[DMA.scala:274:116] wire [5:0] _io_reserve_entry_spad_row_offset_T_2 = req_has_acc_bitwidth ? _io_reserve_entry_spad_row_offset_T : {1'h0, _io_reserve_entry_spad_row_offset_T_1}; // @[DMA.scala:159:18, :274:{44,82,116}] assign io_reserve_entry_spad_row_offset_0 = {3'h0, _io_reserve_entry_spad_row_offset_T_2}; // @[DMA.scala:138:9, :274:{38,44}] wire _T_3 = untranslated_a_ready & untranslated_a_valid; // @[Decoupled.scala:51:35] wire [40:0] _next_vaddr_T = {1'h0, req_vaddr} + {34'h0, read_packet_bytes_read}; // @[DMA.scala:159:18, :198:10, :277:34] wire [39:0] next_vaddr = _next_vaddr_T[39:0]; // @[DMA.scala:277:34] wire [11:0] _new_page_T = next_vaddr[11:0]; // @[DMA.scala:277:34, :278:32] wire new_page = _new_page_T == 12'h0; // @[DMA.scala:278:{32,49}] wire [7:0] _bytesRequested_T = {2'h0, bytesRequested} + {1'h0, read_packet_bytes_read}; // @[DMA.scala:162:29, :198:10, :281:40] wire [6:0] _bytesRequested_T_1 = _bytesRequested_T[6:0]; // @[DMA.scala:281:40] wire _GEN_5 = _T_3 & {12'h0, read_packet_bytes_read} >= bytesLeft; // @[Decoupled.scala:51:35] assign state_machine_ready_for_req = _GEN_5 \| _state_machine_ready_for_req_T; // @[DMA.scala:165:{47,54}, :276:32, :284:43, :286:37] assign io_beatData_bits_lg_len_req_0 = nodeOut_d_bits_size[2:0]; // @[DMA.scala:138:9, :296:33] wire _io_beatData_bits_last_T = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35] wire [26:0] _io_beatData_bits_last_beats1_decode_T = 27'hFFF << nodeOut_d_bits_size; // @[package.scala:243:71] wire [11:0] _io_beatData_bits_last_beats1_decode_T_1 = _io_beatData_bits_last_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _io_beatData_bits_last_beats1_decode_T_2 = ~_io_beatData_bits_last_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] io_beatData_bits_last_beats1_decode = _io_beatData_bits_last_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire io_beatData_bits_last_beats1_opdata = nodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [7:0] io_beatData_bits_last_beats1 = io_beatData_bits_last_beats1_opdata ? io_beatData_bits_last_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] io_beatData_bits_last_counter; // @[Edges.scala:229:27] wire [8:0] _io_beatData_bits_last_counter1_T = {1'h0, io_beatData_bits_last_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] io_beatData_bits_last_counter1 = _io_beatData_bits_last_counter1_T[7:0]; // @[Edges.scala:230:28] wire io_beatData_bits_last_first = io_beatData_bits_last_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _io_beatData_bits_last_last_T = io_beatData_bits_last_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _io_beatData_bits_last_last_T_1 = io_beatData_bits_last_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] assign io_beatData_bits_last_last = _io_beatData_bits_last_last_T \| _io_beatData_bits_last_last_T_1; // @[Edges.scala:232:{25,33,43}] assign io_beatData_bits_last_0 = io_beatData_bits_last_last; // @[Edges.scala:232:33] wire io_beatData_bits_last_done = io_beatData_bits_last_last & _io_beatData_bits_last_T; // @[Decoupled.scala:51:35] wire [7:0] _io_beatData_bits_last_count_T = ~io_beatData_bits_last_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] io_beatData_bits_last_count = io_beatData_bits_last_beats1 & _io_beatData_bits_last_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _io_beatData_bits_last_counter_T = io_beatData_bits_last_first ? io_beatData_bits_last_beats1 : io_beatData_bits_last_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] assign io_counter_event_signal_20_0 = nodeOut_a_valid & ~nodeOut_a_ready; // @[DMA.scala:138:9, :245:71, :313:80] reg [31:0] total_bytes_read; // @[DMA.scala:316:35] assign io_counter_external_values_4_0 = total_bytes_read; // @[DMA.scala:138:9, :316:35] wire [15:0] _total_bytes_read_T = 16'h1 << nodeOut_d_bits_size; // @[DMA.scala:320:51] wire [32:0] _total_bytes_read_T_1 = {1'h0, total_bytes_read} + {17'h0, _total_bytes_read_T}; // @[DMA.scala:316:35, :320:{44,51}] wire [31:0] _total_bytes_read_T_2 = _total_bytes_read_T_1[31:0]; // @[DMA.scala:320:44] reg [18:0] cntr_value; // @[Counter.scala:61:40] wire wrap = cntr_value == 19'h7A11F; // @[Counter.scala:61:40, :73:24] wire [19:0] _value_T = {1'h0, cntr_value} + 20'h1; // @[Counter.scala:61:40, :77:24] wire [18:0] _value_T_1 = _value_T[18:0]; // @[Counter.scala:77:24] wire _printf_T_1 = ~_printf_T; // @[annotations.scala:102:49]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_43 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0hf)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0hf)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0hf)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_197 = shr(io.in.a.bits.source, 4) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<4>(0hf)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_374 = shr(io.in.a.bits.source, 4) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<4>(0hf)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_480 = shr(io.in.a.bits.source, 4) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<4>(0hf)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_582 = shr(io.in.a.bits.source, 4) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<4>(0hf)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_686 = shr(io.in.a.bits.source, 4) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<4>(0hf)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<27>(0h4000000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = or(_T_702, _T_707) node _T_734 = or(_T_733, _T_712) node _T_735 = or(_T_734, _T_717) node _T_736 = or(_T_735, _T_722) node _T_737 = or(_T_736, _T_727) node _T_738 = or(_T_737, _T_732) node _T_739 = and(_T_697, _T_738) node _T_740 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_741 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<17>(0h10000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = and(_T_740, _T_745) node _T_747 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_748 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<17>(0h10000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_757 = cvt(_T_756) node _T_758 = and(_T_757, asSInt(UInt<29>(0h10000000))) node _T_759 = asSInt(_T_758) node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0))) node _T_761 = or(_T_755, _T_760) node _T_762 = and(_T_750, _T_761) node _T_763 = or(UInt<1>(0h0), _T_739) node _T_764 = or(_T_763, _T_746) node _T_765 = or(_T_764, _T_762) node _T_766 = and(_T_693, _T_765) node _T_767 = asUInt(reset) node _T_768 = eq(_T_767, UInt<1>(0h0)) when _T_768 : node _T_769 = eq(_T_766, UInt<1>(0h0)) when _T_769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_766, UInt<1>(0h1), "") : assert_36 node _T_770 = asUInt(reset) node _T_771 = eq(_T_770, UInt<1>(0h0)) when _T_771 : node _T_772 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_773 = asUInt(reset) node _T_774 = eq(_T_773, UInt<1>(0h0)) when _T_774 : node _T_775 = eq(is_aligned, UInt<1>(0h0)) when _T_775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_776 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_777 = asUInt(reset) node _T_778 = eq(_T_777, UInt<1>(0h0)) when _T_778 : node _T_779 = eq(_T_776, UInt<1>(0h0)) when _T_779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_776, UInt<1>(0h1), "") : assert_39 node _T_780 = eq(io.in.a.bits.mask, mask) node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(_T_780, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_780, UInt<1>(0h1), "") : assert_40 node _T_784 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_784 : node _T_785 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_786 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_787 = and(_T_785, _T_786) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_788 = shr(io.in.a.bits.source, 4) node _T_789 = eq(_T_788, UInt<1>(0h0)) node _T_790 = leq(UInt<1>(0h0), uncommonBits_7) node _T_791 = and(_T_789, _T_790) node _T_792 = leq(uncommonBits_7, UInt<4>(0hf)) node _T_793 = and(_T_791, _T_792) node _T_794 = and(_T_787, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_797 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_798 = and(_T_796, _T_797) node _T_799 = or(UInt<1>(0h0), _T_798) node _T_800 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<14>(0h2000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<13>(0h1000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<18>(0h2f000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<17>(0h10000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<13>(0h1000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = or(_T_804, _T_809) node _T_836 = or(_T_835, _T_814) node _T_837 = or(_T_836, _T_819) node _T_838 = or(_T_837, _T_824) node _T_839 = or(_T_838, _T_829) node _T_840 = or(_T_839, _T_834) node _T_841 = and(_T_799, _T_840) node _T_842 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_843 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_844 = cvt(_T_843) node _T_845 = and(_T_844, asSInt(UInt<17>(0h10000))) node _T_846 = asSInt(_T_845) node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0))) node _T_848 = and(_T_842, _T_847) node _T_849 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_850 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_854 = cvt(_T_853) node _T_855 = and(_T_854, asSInt(UInt<17>(0h10000))) node _T_856 = asSInt(_T_855) node _T_857 = eq(_T_856, asSInt(UInt<1>(0h0))) node _T_858 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_859 = cvt(_T_858) node _T_860 = and(_T_859, asSInt(UInt<29>(0h10000000))) node _T_861 = asSInt(_T_860) node _T_862 = eq(_T_861, asSInt(UInt<1>(0h0))) node _T_863 = or(_T_857, _T_862) node _T_864 = and(_T_852, _T_863) node _T_865 = or(UInt<1>(0h0), _T_841) node _T_866 = or(_T_865, _T_848) node _T_867 = or(_T_866, _T_864) node _T_868 = and(_T_795, _T_867) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_868, UInt<1>(0h1), "") : assert_41 node _T_872 = asUInt(reset) node _T_873 = eq(_T_872, UInt<1>(0h0)) when _T_873 : node _T_874 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(is_aligned, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_878 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_878, UInt<1>(0h1), "") : assert_44 node _T_882 = eq(io.in.a.bits.mask, mask) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_882, UInt<1>(0h1), "") : assert_45 node _T_886 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_886 : node _T_887 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_888 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_889 = and(_T_887, _T_888) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_890 = shr(io.in.a.bits.source, 4) node _T_891 = eq(_T_890, UInt<1>(0h0)) node _T_892 = leq(UInt<1>(0h0), uncommonBits_8) node _T_893 = and(_T_891, _T_892) node _T_894 = leq(uncommonBits_8, UInt<4>(0hf)) node _T_895 = and(_T_893, _T_894) node _T_896 = and(_T_889, _T_895) node _T_897 = or(UInt<1>(0h0), _T_896) node _T_898 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_899 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_900 = and(_T_898, _T_899) node _T_901 = or(UInt<1>(0h0), _T_900) node _T_902 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_903 = cvt(_T_902) node _T_904 = and(_T_903, asSInt(UInt<13>(0h1000))) node _T_905 = asSInt(_T_904) node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0))) node _T_907 = and(_T_901, _T_906) node _T_908 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_909 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<14>(0h2000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<18>(0h2f000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<17>(0h10000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_935 = cvt(_T_934) node _T_936 = and(_T_935, asSInt(UInt<27>(0h4000000))) node _T_937 = asSInt(_T_936) node _T_938 = eq(_T_937, asSInt(UInt<1>(0h0))) node _T_939 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_940 = cvt(_T_939) node _T_941 = and(_T_940, asSInt(UInt<13>(0h1000))) node _T_942 = asSInt(_T_941) node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0))) node _T_944 = or(_T_913, _T_918) node _T_945 = or(_T_944, _T_923) node _T_946 = or(_T_945, _T_928) node _T_947 = or(_T_946, _T_933) node _T_948 = or(_T_947, _T_938) node _T_949 = or(_T_948, _T_943) node _T_950 = and(_T_908, _T_949) node _T_951 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_952 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_953 = and(_T_951, _T_952) node _T_954 = or(UInt<1>(0h0), _T_953) node _T_955 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_956 = cvt(_T_955) node _T_957 = and(_T_956, asSInt(UInt<17>(0h10000))) node _T_958 = asSInt(_T_957) node _T_959 = eq(_T_958, asSInt(UInt<1>(0h0))) node _T_960 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_961 = cvt(_T_960) node _T_962 = and(_T_961, asSInt(UInt<29>(0h10000000))) node _T_963 = asSInt(_T_962) node _T_964 = eq(_T_963, asSInt(UInt<1>(0h0))) node _T_965 = or(_T_959, _T_964) node _T_966 = and(_T_954, _T_965) node _T_967 = or(UInt<1>(0h0), _T_907) node _T_968 = or(_T_967, _T_950) node _T_969 = or(_T_968, _T_966) node _T_970 = and(_T_897, _T_969) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_970, UInt<1>(0h1), "") : assert_46 node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(is_aligned, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_980 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_980, UInt<1>(0h1), "") : assert_49 node _T_984 = eq(io.in.a.bits.mask, mask) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_984, UInt<1>(0h1), "") : assert_50 node _T_988 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_988, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_992 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(_T_992, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_992, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0hf)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_996 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_996 : node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_1000 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_54 node _T_1004 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_55 node _T_1008 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(_T_1008, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1008, UInt<1>(0h1), "") : assert_56 node _T_1012 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(_T_1012, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1012, UInt<1>(0h1), "") : assert_57 node _T_1016 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1016 : node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(sink_ok, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1023 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_60 node _T_1027 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_61 node _T_1031 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_62 node _T_1035 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_63 node _T_1039 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1040 = or(UInt<1>(0h1), _T_1039) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_64 node _T_1044 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1044 : node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(sink_ok, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1051 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(_T_1051, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1051, UInt<1>(0h1), "") : assert_67 node _T_1055 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_68 node _T_1059 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_69 node _T_1063 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1064 = or(_T_1063, io.in.d.bits.corrupt) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_70 node _T_1068 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1069 = or(UInt<1>(0h1), _T_1068) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_71 node _T_1073 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1073 : node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1077 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_73 node _T_1081 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_74 node _T_1085 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1086 = or(UInt<1>(0h1), _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_75 node _T_1090 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1090 : node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1094 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_77 node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1099 = or(_T_1098, io.in.d.bits.corrupt) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_78 node _T_1103 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1104 = or(UInt<1>(0h1), _T_1103) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_79 node _T_1108 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1108 : node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1112 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_81 node _T_1116 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_82 node _T_1120 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1121 = or(UInt<1>(0h1), _T_1120) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1125 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1129 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1133 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1137 = eq(a_first, UInt<1>(0h0)) node _T_1138 = and(io.in.a.valid, _T_1137) when _T_1138 : node _T_1139 = eq(io.in.a.bits.opcode, opcode) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_87 node _T_1143 = eq(io.in.a.bits.param, param) node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(_T_1143, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1143, UInt<1>(0h1), "") : assert_88 node _T_1147 = eq(io.in.a.bits.size, size) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_89 node _T_1151 = eq(io.in.a.bits.source, source) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_90 node _T_1155 = eq(io.in.a.bits.address, address) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_91 node _T_1159 = and(io.in.a.ready, io.in.a.valid) node _T_1160 = and(_T_1159, a_first) when _T_1160 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1161 = eq(d_first, UInt<1>(0h0)) node _T_1162 = and(io.in.d.valid, _T_1161) when _T_1162 : node _T_1163 = eq(io.in.d.bits.opcode, opcode_1) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_92 node _T_1167 = eq(io.in.d.bits.param, param_1) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_93 node _T_1171 = eq(io.in.d.bits.size, size_1) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_94 node _T_1175 = eq(io.in.d.bits.source, source_1) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_95 node _T_1179 = eq(io.in.d.bits.sink, sink) node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(_T_1179, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1179, UInt<1>(0h1), "") : assert_96 node _T_1183 = eq(io.in.d.bits.denied, denied) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_97 node _T_1187 = and(io.in.d.ready, io.in.d.valid) node _T_1188 = and(_T_1187, d_first) when _T_1188 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0) regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<16> connect a_set, UInt<16>(0h0) wire a_set_wo_ready : UInt<16> connect a_set_wo_ready, UInt<16>(0h0) wire a_opcodes_set : UInt<64> connect a_opcodes_set, UInt<64>(0h0) wire a_sizes_set : UInt<128> connect a_sizes_set, UInt<128>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1189 = and(io.in.a.valid, a_first_1) node _T_1190 = and(_T_1189, UInt<1>(0h1)) when _T_1190 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1191 = and(io.in.a.ready, io.in.a.valid) node _T_1192 = and(_T_1191, a_first_1) node _T_1193 = and(_T_1192, UInt<1>(0h1)) when _T_1193 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1194 = dshr(inflight, io.in.a.bits.source) node _T_1195 = bits(_T_1194, 0, 0) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(_T_1196, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1196, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<16> connect d_clr, UInt<16>(0h0) wire d_clr_wo_ready : UInt<16> connect d_clr_wo_ready, UInt<16>(0h0) wire d_opcodes_clr : UInt<64> connect d_opcodes_clr, UInt<64>(0h0) wire d_sizes_clr : UInt<128> connect d_sizes_clr, UInt<128>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1200 = and(io.in.d.valid, d_first_1) node _T_1201 = and(_T_1200, UInt<1>(0h1)) node _T_1202 = eq(d_release_ack, UInt<1>(0h0)) node _T_1203 = and(_T_1201, _T_1202) when _T_1203 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1204 = and(io.in.d.ready, io.in.d.valid) node _T_1205 = and(_T_1204, d_first_1) node _T_1206 = and(_T_1205, UInt<1>(0h1)) node _T_1207 = eq(d_release_ack, UInt<1>(0h0)) node _T_1208 = and(_T_1206, _T_1207) when _T_1208 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1209 = and(io.in.d.valid, d_first_1) node _T_1210 = and(_T_1209, UInt<1>(0h1)) node _T_1211 = eq(d_release_ack, UInt<1>(0h0)) node _T_1212 = and(_T_1210, _T_1211) when _T_1212 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1213 = dshr(inflight, io.in.d.bits.source) node _T_1214 = bits(_T_1213, 0, 0) node _T_1215 = or(_T_1214, same_cycle_resp) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_100 node _T_1225 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_101 else : node _T_1229 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1230 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1231 = or(_T_1229, _T_1230) node _T_1232 = asUInt(reset) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) when _T_1233 : node _T_1234 = eq(_T_1231, UInt<1>(0h0)) when _T_1234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1231, UInt<1>(0h1), "") : assert_102 node _T_1235 = eq(io.in.d.bits.size, a_size_lookup) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_103 node _T_1239 = and(io.in.d.valid, d_first_1) node _T_1240 = and(_T_1239, a_first_1) node _T_1241 = and(_T_1240, io.in.a.valid) node _T_1242 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1243 = and(_T_1241, _T_1242) node _T_1244 = eq(d_release_ack, UInt<1>(0h0)) node _T_1245 = and(_T_1243, _T_1244) when _T_1245 : node _T_1246 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1247 = or(_T_1246, io.in.a.ready) node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(_T_1247, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1247, UInt<1>(0h1), "") : assert_104 node _T_1251 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1252 = orr(a_set_wo_ready) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) node _T_1254 = or(_T_1251, _T_1253) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_86 node _T_1258 = orr(inflight) node _T_1259 = eq(_T_1258, UInt<1>(0h0)) node _T_1260 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1261 = or(_T_1259, _T_1260) node _T_1262 = lt(watchdog, plusarg_reader.out) node _T_1263 = or(_T_1261, _T_1262) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1267 = and(io.in.a.ready, io.in.a.valid) node _T_1268 = and(io.in.d.ready, io.in.d.valid) node _T_1269 = or(_T_1267, _T_1268) when _T_1269 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<16> connect c_set, UInt<16>(0h0) wire c_set_wo_ready : UInt<16> connect c_set_wo_ready, UInt<16>(0h0) wire c_opcodes_set : UInt<64> connect c_opcodes_set, UInt<64>(0h0) wire c_sizes_set : UInt<128> connect c_sizes_set, UInt<128>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1270 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<128>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1271 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1272 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1273 = and(_T_1271, _T_1272) node _T_1274 = and(_T_1270, _T_1273) when _T_1274 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1275 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1276 = and(_T_1275, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1277 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1278 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1279 = and(_T_1277, _T_1278) node _T_1280 = and(_T_1276, _T_1279) when _T_1280 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1281 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1282 = bits(_T_1281, 0, 0) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(_T_1283, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1283, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<16> connect d_clr_1, UInt<16>(0h0) wire d_clr_wo_ready_1 : UInt<16> connect d_clr_wo_ready_1, UInt<16>(0h0) wire d_opcodes_clr_1 : UInt<64> connect d_opcodes_clr_1, UInt<64>(0h0) wire d_sizes_clr_1 : UInt<128> connect d_sizes_clr_1, UInt<128>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1287 = and(io.in.d.valid, d_first_2) node _T_1288 = and(_T_1287, UInt<1>(0h1)) node _T_1289 = and(_T_1288, d_release_ack_1) when _T_1289 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1290 = and(io.in.d.ready, io.in.d.valid) node _T_1291 = and(_T_1290, d_first_2) node _T_1292 = and(_T_1291, UInt<1>(0h1)) node _T_1293 = and(_T_1292, d_release_ack_1) when _T_1293 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1294 = and(io.in.d.valid, d_first_2) node _T_1295 = and(_T_1294, UInt<1>(0h1)) node _T_1296 = and(_T_1295, d_release_ack_1) when _T_1296 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1297 = dshr(inflight_1, io.in.d.bits.source) node _T_1298 = bits(_T_1297, 0, 0) node _T_1299 = or(_T_1298, same_cycle_resp_1) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1303 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_109 else : node _T_1307 = eq(io.in.d.bits.size, c_size_lookup) node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(_T_1307, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1307, UInt<1>(0h1), "") : assert_110 node _T_1311 = and(io.in.d.valid, d_first_2) node _T_1312 = and(_T_1311, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1313 = and(_T_1312, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1314 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1315 = and(_T_1313, _T_1314) node _T_1316 = and(_T_1315, d_release_ack_1) node _T_1317 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1318 = and(_T_1316, _T_1317) when _T_1318 : node _T_1319 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1320 = or(_T_1319, _WIRE_23.ready) node _T_1321 = asUInt(reset) node _T_1322 = eq(_T_1321, UInt<1>(0h0)) when _T_1322 : node _T_1323 = eq(_T_1320, UInt<1>(0h0)) when _T_1323 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1320, UInt<1>(0h1), "") : assert_111 node _T_1324 = orr(c_set_wo_ready) when _T_1324 : node _T_1325 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1326 = asUInt(reset) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) when _T_1327 : node _T_1328 = eq(_T_1325, UInt<1>(0h0)) when _T_1328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1325, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_87 node _T_1329 = orr(inflight_1) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) node _T_1331 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1332 = or(_T_1330, _T_1331) node _T_1333 = lt(watchdog_1, plusarg_reader_1.out) node _T_1334 = or(_T_1332, _T_1333) node _T_1335 = asUInt(reset) node _T_1336 = eq(_T_1335, UInt<1>(0h0)) when _T_1336 : node _T_1337 = eq(_T_1334, UInt<1>(0h0)) when _T_1337 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:200:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1334, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1338 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1339 = and(io.in.d.ready, io.in.d.valid) node _T_1340 = or(_T_1338, _T_1339) when _T_1340 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_88 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_89 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_43( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34] wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34] wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1267 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1267; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1267; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1340 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1340; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1340; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1340; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [15:0] inflight; // @[Monitor.scala:614:27] reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [127:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] a_set; // @[Monitor.scala:626:34] wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [127:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1193 = _T_1267 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1193 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1193 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1193 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1193 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1193 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [15:0] d_clr; // @[Monitor.scala:664:34] wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1239 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1239 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1208 = _T_1340 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1208 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1208 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1208 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [15:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [63:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [127:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [15:0] inflight_1; // @[Monitor.scala:726:35] wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [15:0] d_clr_1; // @[Monitor.scala:774:34] wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1311 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1311 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35] wire _T_1293 = _T_1340 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1293 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1293 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1293 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RotatingSingleVCAllocator_21 : input clock : Clock input reset : Reset output io : { req : { flip `4` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}}, resp : { `4` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `3` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `2` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `1` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `0` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, channel_status : { flip `4` : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip `3` : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2], flip `2` : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2], flip `1` : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2], flip `0` : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2]}, out_allocs : { `4` : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], `3` : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2], `2` : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2], `1` : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2], `0` : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[2]}} regreset mask : UInt<5>, clock, reset, UInt<5>(0h0) wire in_arb_reqs : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}[5] wire in_arb_vals : UInt<1>[5] node in_arb_filter_lo = cat(in_arb_vals[1], in_arb_vals[0]) node in_arb_filter_hi_hi = cat(in_arb_vals[4], in_arb_vals[3]) node in_arb_filter_hi = cat(in_arb_filter_hi_hi, in_arb_vals[2]) node _in_arb_filter_T = cat(in_arb_filter_hi, in_arb_filter_lo) node in_arb_filter_lo_1 = cat(in_arb_vals[1], in_arb_vals[0]) node in_arb_filter_hi_hi_1 = cat(in_arb_vals[4], in_arb_vals[3]) node in_arb_filter_hi_1 = cat(in_arb_filter_hi_hi_1, in_arb_vals[2]) node _in_arb_filter_T_1 = cat(in_arb_filter_hi_1, in_arb_filter_lo_1) node _in_arb_filter_T_2 = not(mask) node _in_arb_filter_T_3 = and(_in_arb_filter_T_1, _in_arb_filter_T_2) node _in_arb_filter_T_4 = cat(_in_arb_filter_T, _in_arb_filter_T_3) node _in_arb_filter_T_5 = bits(_in_arb_filter_T_4, 0, 0) node _in_arb_filter_T_6 = bits(_in_arb_filter_T_4, 1, 1) node _in_arb_filter_T_7 = bits(_in_arb_filter_T_4, 2, 2) node _in_arb_filter_T_8 = bits(_in_arb_filter_T_4, 3, 3) node _in_arb_filter_T_9 = bits(_in_arb_filter_T_4, 4, 4) node _in_arb_filter_T_10 = bits(_in_arb_filter_T_4, 5, 5) node _in_arb_filter_T_11 = bits(_in_arb_filter_T_4, 6, 6) node _in_arb_filter_T_12 = bits(_in_arb_filter_T_4, 7, 7) node _in_arb_filter_T_13 = bits(_in_arb_filter_T_4, 8, 8) node _in_arb_filter_T_14 = bits(_in_arb_filter_T_4, 9, 9) node _in_arb_filter_T_15 = mux(_in_arb_filter_T_14, UInt<10>(0h200), UInt<10>(0h0)) node _in_arb_filter_T_16 = mux(_in_arb_filter_T_13, UInt<10>(0h100), _in_arb_filter_T_15) node _in_arb_filter_T_17 = mux(_in_arb_filter_T_12, UInt<10>(0h80), _in_arb_filter_T_16) node _in_arb_filter_T_18 = mux(_in_arb_filter_T_11, UInt<10>(0h40), _in_arb_filter_T_17) node _in_arb_filter_T_19 = mux(_in_arb_filter_T_10, UInt<10>(0h20), _in_arb_filter_T_18) node _in_arb_filter_T_20 = mux(_in_arb_filter_T_9, UInt<10>(0h10), _in_arb_filter_T_19) node _in_arb_filter_T_21 = mux(_in_arb_filter_T_8, UInt<10>(0h8), _in_arb_filter_T_20) node _in_arb_filter_T_22 = mux(_in_arb_filter_T_7, UInt<10>(0h4), _in_arb_filter_T_21) node _in_arb_filter_T_23 = mux(_in_arb_filter_T_6, UInt<10>(0h2), _in_arb_filter_T_22) node in_arb_filter = mux(_in_arb_filter_T_5, UInt<10>(0h1), _in_arb_filter_T_23) node _in_arb_sel_T = bits(in_arb_filter, 4, 0) node _in_arb_sel_T_1 = shr(in_arb_filter, 5) node in_arb_sel = or(_in_arb_sel_T, _in_arb_sel_T_1) node _T = or(in_arb_vals[0], in_arb_vals[1]) node _T_1 = or(_T, in_arb_vals[2]) node _T_2 = or(_T_1, in_arb_vals[3]) node _T_3 = or(_T_2, in_arb_vals[4]) when _T_3 : node _mask_T = not(UInt<1>(0h0)) node _mask_T_1 = not(UInt<2>(0h0)) node _mask_T_2 = not(UInt<3>(0h0)) node _mask_T_3 = not(UInt<4>(0h0)) node _mask_T_4 = not(UInt<5>(0h0)) node _mask_T_5 = bits(in_arb_sel, 0, 0) node _mask_T_6 = bits(in_arb_sel, 1, 1) node _mask_T_7 = bits(in_arb_sel, 2, 2) node _mask_T_8 = bits(in_arb_sel, 3, 3) node _mask_T_9 = bits(in_arb_sel, 4, 4) node _mask_T_10 = mux(_mask_T_5, _mask_T, UInt<1>(0h0)) node _mask_T_11 = mux(_mask_T_6, _mask_T_1, UInt<1>(0h0)) node _mask_T_12 = mux(_mask_T_7, _mask_T_2, UInt<1>(0h0)) node _mask_T_13 = mux(_mask_T_8, _mask_T_3, UInt<1>(0h0)) node _mask_T_14 = mux(_mask_T_9, _mask_T_4, UInt<1>(0h0)) node _mask_T_15 = or(_mask_T_10, _mask_T_11) node _mask_T_16 = or(_mask_T_15, _mask_T_12) node _mask_T_17 = or(_mask_T_16, _mask_T_13) node _mask_T_18 = or(_mask_T_17, _mask_T_14) wire _mask_WIRE : UInt<5> connect _mask_WIRE, _mask_T_18 connect mask, _mask_WIRE node _in_arb_reqs_0_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_0_T_1 = and(io.req.`0`.bits.vc_sel.`0`[0], _in_arb_reqs_0_0_0_T) connect in_arb_reqs[0].`0`[0], _in_arb_reqs_0_0_0_T_1 node _in_arb_reqs_0_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_1_T_1 = and(io.req.`0`.bits.vc_sel.`0`[1], _in_arb_reqs_0_0_1_T) connect in_arb_reqs[0].`0`[1], _in_arb_reqs_0_0_1_T_1 node _in_arb_reqs_0_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_0_T_1 = and(io.req.`0`.bits.vc_sel.`1`[0], _in_arb_reqs_0_1_0_T) connect in_arb_reqs[0].`1`[0], _in_arb_reqs_0_1_0_T_1 node _in_arb_reqs_0_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_1_T_1 = and(io.req.`0`.bits.vc_sel.`1`[1], _in_arb_reqs_0_1_1_T) connect in_arb_reqs[0].`1`[1], _in_arb_reqs_0_1_1_T_1 node _in_arb_reqs_0_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_0_T_1 = and(io.req.`0`.bits.vc_sel.`2`[0], _in_arb_reqs_0_2_0_T) connect in_arb_reqs[0].`2`[0], _in_arb_reqs_0_2_0_T_1 node _in_arb_reqs_0_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_1_T_1 = and(io.req.`0`.bits.vc_sel.`2`[1], _in_arb_reqs_0_2_1_T) connect in_arb_reqs[0].`2`[1], _in_arb_reqs_0_2_1_T_1 node _in_arb_reqs_0_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_3_0_T_1 = and(io.req.`0`.bits.vc_sel.`3`[0], _in_arb_reqs_0_3_0_T) connect in_arb_reqs[0].`3`[0], _in_arb_reqs_0_3_0_T_1 node _in_arb_reqs_0_3_1_T = eq(io.channel_status.`3`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_3_1_T_1 = and(io.req.`0`.bits.vc_sel.`3`[1], _in_arb_reqs_0_3_1_T) connect in_arb_reqs[0].`3`[1], _in_arb_reqs_0_3_1_T_1 node _in_arb_reqs_0_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_4_0_T_1 = and(io.req.`0`.bits.vc_sel.`4`[0], _in_arb_reqs_0_4_0_T) connect in_arb_reqs[0].`4`[0], _in_arb_reqs_0_4_0_T_1 node _in_arb_vals_0_T = or(in_arb_reqs[0].`0`[0], in_arb_reqs[0].`0`[1]) node _in_arb_vals_0_T_1 = or(in_arb_reqs[0].`1`[0], in_arb_reqs[0].`1`[1]) node _in_arb_vals_0_T_2 = or(in_arb_reqs[0].`2`[0], in_arb_reqs[0].`2`[1]) node _in_arb_vals_0_T_3 = or(in_arb_reqs[0].`3`[0], in_arb_reqs[0].`3`[1]) node _in_arb_vals_0_T_4 = or(_in_arb_vals_0_T, _in_arb_vals_0_T_1) node _in_arb_vals_0_T_5 = or(_in_arb_vals_0_T_4, _in_arb_vals_0_T_2) node _in_arb_vals_0_T_6 = or(_in_arb_vals_0_T_5, _in_arb_vals_0_T_3) node _in_arb_vals_0_T_7 = or(_in_arb_vals_0_T_6, in_arb_reqs[0].`4`[0]) node _in_arb_vals_0_T_8 = and(io.req.`0`.valid, _in_arb_vals_0_T_7) connect in_arb_vals[0], _in_arb_vals_0_T_8 node _in_arb_reqs_1_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_0_T_1 = and(io.req.`1`.bits.vc_sel.`0`[0], _in_arb_reqs_1_0_0_T) connect in_arb_reqs[1].`0`[0], _in_arb_reqs_1_0_0_T_1 node _in_arb_reqs_1_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_1_T_1 = and(io.req.`1`.bits.vc_sel.`0`[1], _in_arb_reqs_1_0_1_T) connect in_arb_reqs[1].`0`[1], _in_arb_reqs_1_0_1_T_1 node _in_arb_reqs_1_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_0_T_1 = and(io.req.`1`.bits.vc_sel.`1`[0], _in_arb_reqs_1_1_0_T) connect in_arb_reqs[1].`1`[0], _in_arb_reqs_1_1_0_T_1 node _in_arb_reqs_1_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_1_T_1 = and(io.req.`1`.bits.vc_sel.`1`[1], _in_arb_reqs_1_1_1_T) connect in_arb_reqs[1].`1`[1], _in_arb_reqs_1_1_1_T_1 node _in_arb_reqs_1_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_0_T_1 = and(io.req.`1`.bits.vc_sel.`2`[0], _in_arb_reqs_1_2_0_T) connect in_arb_reqs[1].`2`[0], _in_arb_reqs_1_2_0_T_1 node _in_arb_reqs_1_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_1_T_1 = and(io.req.`1`.bits.vc_sel.`2`[1], _in_arb_reqs_1_2_1_T) connect in_arb_reqs[1].`2`[1], _in_arb_reqs_1_2_1_T_1 node _in_arb_reqs_1_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_3_0_T_1 = and(io.req.`1`.bits.vc_sel.`3`[0], _in_arb_reqs_1_3_0_T) connect in_arb_reqs[1].`3`[0], _in_arb_reqs_1_3_0_T_1 node _in_arb_reqs_1_3_1_T = eq(io.channel_status.`3`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_3_1_T_1 = and(io.req.`1`.bits.vc_sel.`3`[1], _in_arb_reqs_1_3_1_T) connect in_arb_reqs[1].`3`[1], _in_arb_reqs_1_3_1_T_1 node _in_arb_reqs_1_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_4_0_T_1 = and(io.req.`1`.bits.vc_sel.`4`[0], _in_arb_reqs_1_4_0_T) connect in_arb_reqs[1].`4`[0], _in_arb_reqs_1_4_0_T_1 node _in_arb_vals_1_T = or(in_arb_reqs[1].`0`[0], in_arb_reqs[1].`0`[1]) node _in_arb_vals_1_T_1 = or(in_arb_reqs[1].`1`[0], in_arb_reqs[1].`1`[1]) node _in_arb_vals_1_T_2 = or(in_arb_reqs[1].`2`[0], in_arb_reqs[1].`2`[1]) node _in_arb_vals_1_T_3 = or(in_arb_reqs[1].`3`[0], in_arb_reqs[1].`3`[1]) node _in_arb_vals_1_T_4 = or(_in_arb_vals_1_T, _in_arb_vals_1_T_1) node _in_arb_vals_1_T_5 = or(_in_arb_vals_1_T_4, _in_arb_vals_1_T_2) node _in_arb_vals_1_T_6 = or(_in_arb_vals_1_T_5, _in_arb_vals_1_T_3) node _in_arb_vals_1_T_7 = or(_in_arb_vals_1_T_6, in_arb_reqs[1].`4`[0]) node _in_arb_vals_1_T_8 = and(io.req.`1`.valid, _in_arb_vals_1_T_7) connect in_arb_vals[1], _in_arb_vals_1_T_8 node _in_arb_reqs_2_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_0_T_1 = and(io.req.`2`.bits.vc_sel.`0`[0], _in_arb_reqs_2_0_0_T) connect in_arb_reqs[2].`0`[0], _in_arb_reqs_2_0_0_T_1 node _in_arb_reqs_2_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_1_T_1 = and(io.req.`2`.bits.vc_sel.`0`[1], _in_arb_reqs_2_0_1_T) connect in_arb_reqs[2].`0`[1], _in_arb_reqs_2_0_1_T_1 node _in_arb_reqs_2_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_0_T_1 = and(io.req.`2`.bits.vc_sel.`1`[0], _in_arb_reqs_2_1_0_T) connect in_arb_reqs[2].`1`[0], _in_arb_reqs_2_1_0_T_1 node _in_arb_reqs_2_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_1_T_1 = and(io.req.`2`.bits.vc_sel.`1`[1], _in_arb_reqs_2_1_1_T) connect in_arb_reqs[2].`1`[1], _in_arb_reqs_2_1_1_T_1 node _in_arb_reqs_2_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_0_T_1 = and(io.req.`2`.bits.vc_sel.`2`[0], _in_arb_reqs_2_2_0_T) connect in_arb_reqs[2].`2`[0], _in_arb_reqs_2_2_0_T_1 node _in_arb_reqs_2_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_1_T_1 = and(io.req.`2`.bits.vc_sel.`2`[1], _in_arb_reqs_2_2_1_T) connect in_arb_reqs[2].`2`[1], _in_arb_reqs_2_2_1_T_1 node _in_arb_reqs_2_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_3_0_T_1 = and(io.req.`2`.bits.vc_sel.`3`[0], _in_arb_reqs_2_3_0_T) connect in_arb_reqs[2].`3`[0], _in_arb_reqs_2_3_0_T_1 node _in_arb_reqs_2_3_1_T = eq(io.channel_status.`3`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_3_1_T_1 = and(io.req.`2`.bits.vc_sel.`3`[1], _in_arb_reqs_2_3_1_T) connect in_arb_reqs[2].`3`[1], _in_arb_reqs_2_3_1_T_1 node _in_arb_reqs_2_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_4_0_T_1 = and(io.req.`2`.bits.vc_sel.`4`[0], _in_arb_reqs_2_4_0_T) connect in_arb_reqs[2].`4`[0], _in_arb_reqs_2_4_0_T_1 node _in_arb_vals_2_T = or(in_arb_reqs[2].`0`[0], in_arb_reqs[2].`0`[1]) node _in_arb_vals_2_T_1 = or(in_arb_reqs[2].`1`[0], in_arb_reqs[2].`1`[1]) node _in_arb_vals_2_T_2 = or(in_arb_reqs[2].`2`[0], in_arb_reqs[2].`2`[1]) node _in_arb_vals_2_T_3 = or(in_arb_reqs[2].`3`[0], in_arb_reqs[2].`3`[1]) node _in_arb_vals_2_T_4 = or(_in_arb_vals_2_T, _in_arb_vals_2_T_1) node _in_arb_vals_2_T_5 = or(_in_arb_vals_2_T_4, _in_arb_vals_2_T_2) node _in_arb_vals_2_T_6 = or(_in_arb_vals_2_T_5, _in_arb_vals_2_T_3) node _in_arb_vals_2_T_7 = or(_in_arb_vals_2_T_6, in_arb_reqs[2].`4`[0]) node _in_arb_vals_2_T_8 = and(io.req.`2`.valid, _in_arb_vals_2_T_7) connect in_arb_vals[2], _in_arb_vals_2_T_8 node _in_arb_reqs_3_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_0_T_1 = and(io.req.`3`.bits.vc_sel.`0`[0], _in_arb_reqs_3_0_0_T) connect in_arb_reqs[3].`0`[0], _in_arb_reqs_3_0_0_T_1 node _in_arb_reqs_3_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_1_T_1 = and(io.req.`3`.bits.vc_sel.`0`[1], _in_arb_reqs_3_0_1_T) connect in_arb_reqs[3].`0`[1], _in_arb_reqs_3_0_1_T_1 node _in_arb_reqs_3_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_1_0_T_1 = and(io.req.`3`.bits.vc_sel.`1`[0], _in_arb_reqs_3_1_0_T) connect in_arb_reqs[3].`1`[0], _in_arb_reqs_3_1_0_T_1 node _in_arb_reqs_3_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_1_1_T_1 = and(io.req.`3`.bits.vc_sel.`1`[1], _in_arb_reqs_3_1_1_T) connect in_arb_reqs[3].`1`[1], _in_arb_reqs_3_1_1_T_1 node _in_arb_reqs_3_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_2_0_T_1 = and(io.req.`3`.bits.vc_sel.`2`[0], _in_arb_reqs_3_2_0_T) connect in_arb_reqs[3].`2`[0], _in_arb_reqs_3_2_0_T_1 node _in_arb_reqs_3_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_2_1_T_1 = and(io.req.`3`.bits.vc_sel.`2`[1], _in_arb_reqs_3_2_1_T) connect in_arb_reqs[3].`2`[1], _in_arb_reqs_3_2_1_T_1 node _in_arb_reqs_3_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_3_0_T_1 = and(io.req.`3`.bits.vc_sel.`3`[0], _in_arb_reqs_3_3_0_T) connect in_arb_reqs[3].`3`[0], _in_arb_reqs_3_3_0_T_1 node _in_arb_reqs_3_3_1_T = eq(io.channel_status.`3`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_3_1_T_1 = and(io.req.`3`.bits.vc_sel.`3`[1], _in_arb_reqs_3_3_1_T) connect in_arb_reqs[3].`3`[1], _in_arb_reqs_3_3_1_T_1 node _in_arb_reqs_3_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_4_0_T_1 = and(io.req.`3`.bits.vc_sel.`4`[0], _in_arb_reqs_3_4_0_T) connect in_arb_reqs[3].`4`[0], _in_arb_reqs_3_4_0_T_1 node _in_arb_vals_3_T = or(in_arb_reqs[3].`0`[0], in_arb_reqs[3].`0`[1]) node _in_arb_vals_3_T_1 = or(in_arb_reqs[3].`1`[0], in_arb_reqs[3].`1`[1]) node _in_arb_vals_3_T_2 = or(in_arb_reqs[3].`2`[0], in_arb_reqs[3].`2`[1]) node _in_arb_vals_3_T_3 = or(in_arb_reqs[3].`3`[0], in_arb_reqs[3].`3`[1]) node _in_arb_vals_3_T_4 = or(_in_arb_vals_3_T, _in_arb_vals_3_T_1) node _in_arb_vals_3_T_5 = or(_in_arb_vals_3_T_4, _in_arb_vals_3_T_2) node _in_arb_vals_3_T_6 = or(_in_arb_vals_3_T_5, _in_arb_vals_3_T_3) node _in_arb_vals_3_T_7 = or(_in_arb_vals_3_T_6, in_arb_reqs[3].`4`[0]) node _in_arb_vals_3_T_8 = and(io.req.`3`.valid, _in_arb_vals_3_T_7) connect in_arb_vals[3], _in_arb_vals_3_T_8 node _in_arb_reqs_4_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_4_0_0_T_1 = and(io.req.`4`.bits.vc_sel.`0`[0], _in_arb_reqs_4_0_0_T) connect in_arb_reqs[4].`0`[0], _in_arb_reqs_4_0_0_T_1 node _in_arb_reqs_4_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_4_0_1_T_1 = and(io.req.`4`.bits.vc_sel.`0`[1], _in_arb_reqs_4_0_1_T) connect in_arb_reqs[4].`0`[1], _in_arb_reqs_4_0_1_T_1 node _in_arb_reqs_4_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_4_1_0_T_1 = and(io.req.`4`.bits.vc_sel.`1`[0], _in_arb_reqs_4_1_0_T) connect in_arb_reqs[4].`1`[0], _in_arb_reqs_4_1_0_T_1 node _in_arb_reqs_4_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_4_1_1_T_1 = and(io.req.`4`.bits.vc_sel.`1`[1], _in_arb_reqs_4_1_1_T) connect in_arb_reqs[4].`1`[1], _in_arb_reqs_4_1_1_T_1 node _in_arb_reqs_4_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_4_2_0_T_1 = and(io.req.`4`.bits.vc_sel.`2`[0], _in_arb_reqs_4_2_0_T) connect in_arb_reqs[4].`2`[0], _in_arb_reqs_4_2_0_T_1 node _in_arb_reqs_4_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_4_2_1_T_1 = and(io.req.`4`.bits.vc_sel.`2`[1], _in_arb_reqs_4_2_1_T) connect in_arb_reqs[4].`2`[1], _in_arb_reqs_4_2_1_T_1 node _in_arb_reqs_4_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_4_3_0_T_1 = and(io.req.`4`.bits.vc_sel.`3`[0], _in_arb_reqs_4_3_0_T) connect in_arb_reqs[4].`3`[0], _in_arb_reqs_4_3_0_T_1 node _in_arb_reqs_4_3_1_T = eq(io.channel_status.`3`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_4_3_1_T_1 = and(io.req.`4`.bits.vc_sel.`3`[1], _in_arb_reqs_4_3_1_T) connect in_arb_reqs[4].`3`[1], _in_arb_reqs_4_3_1_T_1 node _in_arb_reqs_4_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_4_4_0_T_1 = and(io.req.`4`.bits.vc_sel.`4`[0], _in_arb_reqs_4_4_0_T) connect in_arb_reqs[4].`4`[0], _in_arb_reqs_4_4_0_T_1 node _in_arb_vals_4_T = or(in_arb_reqs[4].`0`[0], in_arb_reqs[4].`0`[1]) node _in_arb_vals_4_T_1 = or(in_arb_reqs[4].`1`[0], in_arb_reqs[4].`1`[1]) node _in_arb_vals_4_T_2 = or(in_arb_reqs[4].`2`[0], in_arb_reqs[4].`2`[1]) node _in_arb_vals_4_T_3 = or(in_arb_reqs[4].`3`[0], in_arb_reqs[4].`3`[1]) node _in_arb_vals_4_T_4 = or(_in_arb_vals_4_T, _in_arb_vals_4_T_1) node _in_arb_vals_4_T_5 = or(_in_arb_vals_4_T_4, _in_arb_vals_4_T_2) node _in_arb_vals_4_T_6 = or(_in_arb_vals_4_T_5, _in_arb_vals_4_T_3) node _in_arb_vals_4_T_7 = or(_in_arb_vals_4_T_6, in_arb_reqs[4].`4`[0]) node _in_arb_vals_4_T_8 = and(io.req.`4`.valid, _in_arb_vals_4_T_7) connect in_arb_vals[4], _in_arb_vals_4_T_8 connect io.req.`0`.ready, UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h0) connect io.req.`3`.ready, UInt<1>(0h0) connect io.req.`4`.ready, UInt<1>(0h0) wire in_alloc : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]} node _in_flow_T = bits(in_arb_sel, 0, 0) node _in_flow_T_1 = bits(in_arb_sel, 1, 1) node _in_flow_T_2 = bits(in_arb_sel, 2, 2) node _in_flow_T_3 = bits(in_arb_sel, 3, 3) node _in_flow_T_4 = bits(in_arb_sel, 4, 4) wire in_flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _in_flow_T_5 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_6 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_7 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_8 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_9 = mux(_in_flow_T_4, io.req.`4`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_10 = or(_in_flow_T_5, _in_flow_T_6) node _in_flow_T_11 = or(_in_flow_T_10, _in_flow_T_7) node _in_flow_T_12 = or(_in_flow_T_11, _in_flow_T_8) node _in_flow_T_13 = or(_in_flow_T_12, _in_flow_T_9) wire _in_flow_WIRE : UInt<2> connect _in_flow_WIRE, _in_flow_T_13 connect in_flow.egress_node_id, _in_flow_WIRE node _in_flow_T_14 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_15 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_16 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_17 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_18 = mux(_in_flow_T_4, io.req.`4`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_19 = or(_in_flow_T_14, _in_flow_T_15) node _in_flow_T_20 = or(_in_flow_T_19, _in_flow_T_16) node _in_flow_T_21 = or(_in_flow_T_20, _in_flow_T_17) node _in_flow_T_22 = or(_in_flow_T_21, _in_flow_T_18) wire _in_flow_WIRE_1 : UInt<4> connect _in_flow_WIRE_1, _in_flow_T_22 connect in_flow.egress_node, _in_flow_WIRE_1 node _in_flow_T_23 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_24 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_25 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_26 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_27 = mux(_in_flow_T_4, io.req.`4`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_28 = or(_in_flow_T_23, _in_flow_T_24) node _in_flow_T_29 = or(_in_flow_T_28, _in_flow_T_25) node _in_flow_T_30 = or(_in_flow_T_29, _in_flow_T_26) node _in_flow_T_31 = or(_in_flow_T_30, _in_flow_T_27) wire _in_flow_WIRE_2 : UInt<2> connect _in_flow_WIRE_2, _in_flow_T_31 connect in_flow.ingress_node_id, _in_flow_WIRE_2 node _in_flow_T_32 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_33 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_34 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_35 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_36 = mux(_in_flow_T_4, io.req.`4`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_37 = or(_in_flow_T_32, _in_flow_T_33) node _in_flow_T_38 = or(_in_flow_T_37, _in_flow_T_34) node _in_flow_T_39 = or(_in_flow_T_38, _in_flow_T_35) node _in_flow_T_40 = or(_in_flow_T_39, _in_flow_T_36) wire _in_flow_WIRE_3 : UInt<4> connect _in_flow_WIRE_3, _in_flow_T_40 connect in_flow.ingress_node, _in_flow_WIRE_3 node _in_flow_T_41 = mux(_in_flow_T, io.req.`0`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_42 = mux(_in_flow_T_1, io.req.`1`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_43 = mux(_in_flow_T_2, io.req.`2`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_44 = mux(_in_flow_T_3, io.req.`3`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_45 = mux(_in_flow_T_4, io.req.`4`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_46 = or(_in_flow_T_41, _in_flow_T_42) node _in_flow_T_47 = or(_in_flow_T_46, _in_flow_T_43) node _in_flow_T_48 = or(_in_flow_T_47, _in_flow_T_44) node _in_flow_T_49 = or(_in_flow_T_48, _in_flow_T_45) wire _in_flow_WIRE_4 : UInt<1> connect _in_flow_WIRE_4, _in_flow_T_49 connect in_flow.vnet_id, _in_flow_WIRE_4 node _in_vc_T = bits(in_arb_sel, 0, 0) node _in_vc_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_T_2 = bits(in_arb_sel, 2, 2) node _in_vc_T_3 = bits(in_arb_sel, 3, 3) node _in_vc_T_4 = bits(in_arb_sel, 4, 4) node _in_vc_T_5 = mux(_in_vc_T, io.req.`0`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_6 = mux(_in_vc_T_1, io.req.`1`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_7 = mux(_in_vc_T_2, io.req.`2`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_8 = mux(_in_vc_T_3, io.req.`3`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_9 = mux(_in_vc_T_4, io.req.`4`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_10 = or(_in_vc_T_5, _in_vc_T_6) node _in_vc_T_11 = or(_in_vc_T_10, _in_vc_T_7) node _in_vc_T_12 = or(_in_vc_T_11, _in_vc_T_8) node _in_vc_T_13 = or(_in_vc_T_12, _in_vc_T_9) wire in_vc : UInt<1> connect in_vc, _in_vc_T_13 node _in_vc_sel_T = bits(in_arb_sel, 0, 0) node _in_vc_sel_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_sel_T_2 = bits(in_arb_sel, 2, 2) node _in_vc_sel_T_3 = bits(in_arb_sel, 3, 3) node _in_vc_sel_T_4 = bits(in_arb_sel, 4, 4) wire in_vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _in_vc_sel_WIRE : UInt<1>[2] node _in_vc_sel_T_5 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_6 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_7 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_8 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_9 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_10 = or(_in_vc_sel_T_5, _in_vc_sel_T_6) node _in_vc_sel_T_11 = or(_in_vc_sel_T_10, _in_vc_sel_T_7) node _in_vc_sel_T_12 = or(_in_vc_sel_T_11, _in_vc_sel_T_8) node _in_vc_sel_T_13 = or(_in_vc_sel_T_12, _in_vc_sel_T_9) wire _in_vc_sel_WIRE_1 : UInt<1> connect _in_vc_sel_WIRE_1, _in_vc_sel_T_13 connect _in_vc_sel_WIRE[0], _in_vc_sel_WIRE_1 node _in_vc_sel_T_14 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_15 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_16 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_17 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_18 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_19 = or(_in_vc_sel_T_14, _in_vc_sel_T_15) node _in_vc_sel_T_20 = or(_in_vc_sel_T_19, _in_vc_sel_T_16) node _in_vc_sel_T_21 = or(_in_vc_sel_T_20, _in_vc_sel_T_17) node _in_vc_sel_T_22 = or(_in_vc_sel_T_21, _in_vc_sel_T_18) wire _in_vc_sel_WIRE_2 : UInt<1> connect _in_vc_sel_WIRE_2, _in_vc_sel_T_22 connect _in_vc_sel_WIRE[1], _in_vc_sel_WIRE_2 connect in_vc_sel.`0`, _in_vc_sel_WIRE wire _in_vc_sel_WIRE_3 : UInt<1>[2] node _in_vc_sel_T_23 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_24 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_25 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_26 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_27 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_28 = or(_in_vc_sel_T_23, _in_vc_sel_T_24) node _in_vc_sel_T_29 = or(_in_vc_sel_T_28, _in_vc_sel_T_25) node _in_vc_sel_T_30 = or(_in_vc_sel_T_29, _in_vc_sel_T_26) node _in_vc_sel_T_31 = or(_in_vc_sel_T_30, _in_vc_sel_T_27) wire _in_vc_sel_WIRE_4 : UInt<1> connect _in_vc_sel_WIRE_4, _in_vc_sel_T_31 connect _in_vc_sel_WIRE_3[0], _in_vc_sel_WIRE_4 node _in_vc_sel_T_32 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_33 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_34 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_35 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_36 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`1`[1], UInt<1>(0h0)) node _in_vc_sel_T_37 = or(_in_vc_sel_T_32, _in_vc_sel_T_33) node _in_vc_sel_T_38 = or(_in_vc_sel_T_37, _in_vc_sel_T_34) node _in_vc_sel_T_39 = or(_in_vc_sel_T_38, _in_vc_sel_T_35) node _in_vc_sel_T_40 = or(_in_vc_sel_T_39, _in_vc_sel_T_36) wire _in_vc_sel_WIRE_5 : UInt<1> connect _in_vc_sel_WIRE_5, _in_vc_sel_T_40 connect _in_vc_sel_WIRE_3[1], _in_vc_sel_WIRE_5 connect in_vc_sel.`1`, _in_vc_sel_WIRE_3 wire _in_vc_sel_WIRE_6 : UInt<1>[2] node _in_vc_sel_T_41 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_42 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_43 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_44 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_45 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_46 = or(_in_vc_sel_T_41, _in_vc_sel_T_42) node _in_vc_sel_T_47 = or(_in_vc_sel_T_46, _in_vc_sel_T_43) node _in_vc_sel_T_48 = or(_in_vc_sel_T_47, _in_vc_sel_T_44) node _in_vc_sel_T_49 = or(_in_vc_sel_T_48, _in_vc_sel_T_45) wire _in_vc_sel_WIRE_7 : UInt<1> connect _in_vc_sel_WIRE_7, _in_vc_sel_T_49 connect _in_vc_sel_WIRE_6[0], _in_vc_sel_WIRE_7 node _in_vc_sel_T_50 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[1], UInt<1>(0h0)) node _in_vc_sel_T_51 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[1], UInt<1>(0h0)) node _in_vc_sel_T_52 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[1], UInt<1>(0h0)) node _in_vc_sel_T_53 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`2`[1], UInt<1>(0h0)) node _in_vc_sel_T_54 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`2`[1], UInt<1>(0h0)) node _in_vc_sel_T_55 = or(_in_vc_sel_T_50, _in_vc_sel_T_51) node _in_vc_sel_T_56 = or(_in_vc_sel_T_55, _in_vc_sel_T_52) node _in_vc_sel_T_57 = or(_in_vc_sel_T_56, _in_vc_sel_T_53) node _in_vc_sel_T_58 = or(_in_vc_sel_T_57, _in_vc_sel_T_54) wire _in_vc_sel_WIRE_8 : UInt<1> connect _in_vc_sel_WIRE_8, _in_vc_sel_T_58 connect _in_vc_sel_WIRE_6[1], _in_vc_sel_WIRE_8 connect in_vc_sel.`2`, _in_vc_sel_WIRE_6 wire _in_vc_sel_WIRE_9 : UInt<1>[2] node _in_vc_sel_T_59 = mux(_in_vc_sel_T, in_arb_reqs[0].`3`[0], UInt<1>(0h0)) node _in_vc_sel_T_60 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`3`[0], UInt<1>(0h0)) node _in_vc_sel_T_61 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`3`[0], UInt<1>(0h0)) node _in_vc_sel_T_62 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`3`[0], UInt<1>(0h0)) node _in_vc_sel_T_63 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`3`[0], UInt<1>(0h0)) node _in_vc_sel_T_64 = or(_in_vc_sel_T_59, _in_vc_sel_T_60) node _in_vc_sel_T_65 = or(_in_vc_sel_T_64, _in_vc_sel_T_61) node _in_vc_sel_T_66 = or(_in_vc_sel_T_65, _in_vc_sel_T_62) node _in_vc_sel_T_67 = or(_in_vc_sel_T_66, _in_vc_sel_T_63) wire _in_vc_sel_WIRE_10 : UInt<1> connect _in_vc_sel_WIRE_10, _in_vc_sel_T_67 connect _in_vc_sel_WIRE_9[0], _in_vc_sel_WIRE_10 node _in_vc_sel_T_68 = mux(_in_vc_sel_T, in_arb_reqs[0].`3`[1], UInt<1>(0h0)) node _in_vc_sel_T_69 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`3`[1], UInt<1>(0h0)) node _in_vc_sel_T_70 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`3`[1], UInt<1>(0h0)) node _in_vc_sel_T_71 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`3`[1], UInt<1>(0h0)) node _in_vc_sel_T_72 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`3`[1], UInt<1>(0h0)) node _in_vc_sel_T_73 = or(_in_vc_sel_T_68, _in_vc_sel_T_69) node _in_vc_sel_T_74 = or(_in_vc_sel_T_73, _in_vc_sel_T_70) node _in_vc_sel_T_75 = or(_in_vc_sel_T_74, _in_vc_sel_T_71) node _in_vc_sel_T_76 = or(_in_vc_sel_T_75, _in_vc_sel_T_72) wire _in_vc_sel_WIRE_11 : UInt<1> connect _in_vc_sel_WIRE_11, _in_vc_sel_T_76 connect _in_vc_sel_WIRE_9[1], _in_vc_sel_WIRE_11 connect in_vc_sel.`3`, _in_vc_sel_WIRE_9 wire _in_vc_sel_WIRE_12 : UInt<1>[1] node _in_vc_sel_T_77 = mux(_in_vc_sel_T, in_arb_reqs[0].`4`[0], UInt<1>(0h0)) node _in_vc_sel_T_78 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`4`[0], UInt<1>(0h0)) node _in_vc_sel_T_79 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`4`[0], UInt<1>(0h0)) node _in_vc_sel_T_80 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`4`[0], UInt<1>(0h0)) node _in_vc_sel_T_81 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`4`[0], UInt<1>(0h0)) node _in_vc_sel_T_82 = or(_in_vc_sel_T_77, _in_vc_sel_T_78) node _in_vc_sel_T_83 = or(_in_vc_sel_T_82, _in_vc_sel_T_79) node _in_vc_sel_T_84 = or(_in_vc_sel_T_83, _in_vc_sel_T_80) node _in_vc_sel_T_85 = or(_in_vc_sel_T_84, _in_vc_sel_T_81) wire _in_vc_sel_WIRE_13 : UInt<1> connect _in_vc_sel_WIRE_13, _in_vc_sel_T_85 connect _in_vc_sel_WIRE_12[0], _in_vc_sel_WIRE_13 connect in_vc_sel.`4`, _in_vc_sel_WIRE_12 node _T_4 = or(in_arb_vals[0], in_arb_vals[1]) node _T_5 = or(_T_4, in_arb_vals[2]) node _T_6 = or(_T_5, in_arb_vals[3]) node _T_7 = or(_T_6, in_arb_vals[4]) node hi = bits(in_arb_sel, 4, 4) node lo = bits(in_arb_sel, 3, 0) node _T_8 = orr(hi) node _T_9 = or(hi, lo) node hi_1 = bits(_T_9, 3, 2) node lo_1 = bits(_T_9, 1, 0) node _T_10 = orr(hi_1) node _T_11 = or(hi_1, lo_1) node _T_12 = bits(_T_11, 1, 1) node _T_13 = cat(_T_10, _T_12) node _T_14 = cat(_T_8, _T_13) node _T_15 = and(io.req.`0`.ready, io.req.`0`.valid) node _T_16 = and(io.req.`1`.ready, io.req.`1`.valid) node _T_17 = and(io.req.`2`.ready, io.req.`2`.valid) node _T_18 = and(io.req.`3`.ready, io.req.`3`.valid) node _T_19 = and(io.req.`4`.ready, io.req.`4`.valid) node _T_20 = or(_T_15, _T_16) node _T_21 = or(_T_20, _T_17) node _T_22 = or(_T_21, _T_18) node _T_23 = or(_T_22, _T_19) node _T_24 = cat(in_vc_sel.`0`[1], in_vc_sel.`0`[0]) node _T_25 = cat(in_vc_sel.`1`[1], in_vc_sel.`1`[0]) node _T_26 = cat(in_vc_sel.`2`[1], in_vc_sel.`2`[0]) node _T_27 = cat(in_vc_sel.`3`[1], in_vc_sel.`3`[0]) node lo_2 = cat(_T_25, _T_24) node hi_hi = cat(in_vc_sel.`4`[0], _T_27) node hi_2 = cat(hi_hi, _T_26) node _T_28 = cat(hi_2, lo_2) regreset mask_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _full_T = not(mask_1) node _full_T_1 = and(_T_28, _full_T) node full = cat(_T_28, _full_T_1) node _oh_T = bits(full, 0, 0) node _oh_T_1 = bits(full, 1, 1) node _oh_T_2 = bits(full, 2, 2) node _oh_T_3 = bits(full, 3, 3) node _oh_T_4 = bits(full, 4, 4) node _oh_T_5 = bits(full, 5, 5) node _oh_T_6 = bits(full, 6, 6) node _oh_T_7 = bits(full, 7, 7) node _oh_T_8 = bits(full, 8, 8) node _oh_T_9 = bits(full, 9, 9) node _oh_T_10 = bits(full, 10, 10) node _oh_T_11 = bits(full, 11, 11) node _oh_T_12 = bits(full, 12, 12) node _oh_T_13 = bits(full, 13, 13) node _oh_T_14 = bits(full, 14, 14) node _oh_T_15 = bits(full, 15, 15) node _oh_T_16 = bits(full, 16, 16) node _oh_T_17 = bits(full, 17, 17) node _oh_T_18 = mux(_oh_T_17, UInt<18>(0h20000), UInt<18>(0h0)) node _oh_T_19 = mux(_oh_T_16, UInt<18>(0h10000), _oh_T_18) node _oh_T_20 = mux(_oh_T_15, UInt<18>(0h8000), _oh_T_19) node _oh_T_21 = mux(_oh_T_14, UInt<18>(0h4000), _oh_T_20) node _oh_T_22 = mux(_oh_T_13, UInt<18>(0h2000), _oh_T_21) node _oh_T_23 = mux(_oh_T_12, UInt<18>(0h1000), _oh_T_22) node _oh_T_24 = mux(_oh_T_11, UInt<18>(0h800), _oh_T_23) node _oh_T_25 = mux(_oh_T_10, UInt<18>(0h400), _oh_T_24) node _oh_T_26 = mux(_oh_T_9, UInt<18>(0h200), _oh_T_25) node _oh_T_27 = mux(_oh_T_8, UInt<18>(0h100), _oh_T_26) node _oh_T_28 = mux(_oh_T_7, UInt<18>(0h80), _oh_T_27) node _oh_T_29 = mux(_oh_T_6, UInt<18>(0h40), _oh_T_28) node _oh_T_30 = mux(_oh_T_5, UInt<18>(0h20), _oh_T_29) node _oh_T_31 = mux(_oh_T_4, UInt<18>(0h10), _oh_T_30) node _oh_T_32 = mux(_oh_T_3, UInt<18>(0h8), _oh_T_31) node _oh_T_33 = mux(_oh_T_2, UInt<18>(0h4), _oh_T_32) node _oh_T_34 = mux(_oh_T_1, UInt<18>(0h2), _oh_T_33) node oh = mux(_oh_T, UInt<18>(0h1), _oh_T_34) node _sel_T = bits(oh, 8, 0) node _sel_T_1 = shr(oh, 9) node sel = or(_sel_T, _sel_T_1) when _T_23 : node _mask_T_19 = bits(sel, 0, 0) node _mask_T_20 = not(UInt<1>(0h0)) node _mask_T_21 = bits(sel, 1, 1) node _mask_T_22 = not(UInt<2>(0h0)) node _mask_T_23 = bits(sel, 2, 2) node _mask_T_24 = not(UInt<3>(0h0)) node _mask_T_25 = bits(sel, 3, 3) node _mask_T_26 = not(UInt<4>(0h0)) node _mask_T_27 = bits(sel, 4, 4) node _mask_T_28 = not(UInt<5>(0h0)) node _mask_T_29 = bits(sel, 5, 5) node _mask_T_30 = not(UInt<6>(0h0)) node _mask_T_31 = bits(sel, 6, 6) node _mask_T_32 = not(UInt<7>(0h0)) node _mask_T_33 = bits(sel, 7, 7) node _mask_T_34 = not(UInt<8>(0h0)) node _mask_T_35 = bits(sel, 8, 8) node _mask_T_36 = not(UInt<9>(0h0)) node _mask_T_37 = mux(_mask_T_35, _mask_T_36, UInt<1>(0h0)) node _mask_T_38 = mux(_mask_T_33, _mask_T_34, _mask_T_37) node _mask_T_39 = mux(_mask_T_31, _mask_T_32, _mask_T_38) node _mask_T_40 = mux(_mask_T_29, _mask_T_30, _mask_T_39) node _mask_T_41 = mux(_mask_T_27, _mask_T_28, _mask_T_40) node _mask_T_42 = mux(_mask_T_25, _mask_T_26, _mask_T_41) node _mask_T_43 = mux(_mask_T_23, _mask_T_24, _mask_T_42) node _mask_T_44 = mux(_mask_T_21, _mask_T_22, _mask_T_43) node _mask_T_45 = mux(_mask_T_19, _mask_T_20, _mask_T_44) connect mask_1, _mask_T_45 wire _WIRE : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]} wire _WIRE_1 : UInt<9> connect _WIRE_1, sel node _T_29 = bits(_WIRE_1, 0, 0) connect _WIRE.`0`[0], _T_29 node _T_30 = bits(_WIRE_1, 1, 1) connect _WIRE.`0`[1], _T_30 node _T_31 = bits(_WIRE_1, 2, 2) connect _WIRE.`1`[0], _T_31 node _T_32 = bits(_WIRE_1, 3, 3) connect _WIRE.`1`[1], _T_32 node _T_33 = bits(_WIRE_1, 4, 4) connect _WIRE.`2`[0], _T_33 node _T_34 = bits(_WIRE_1, 5, 5) connect _WIRE.`2`[1], _T_34 node _T_35 = bits(_WIRE_1, 6, 6) connect _WIRE.`3`[0], _T_35 node _T_36 = bits(_WIRE_1, 7, 7) connect _WIRE.`3`[1], _T_36 node _T_37 = bits(_WIRE_1, 8, 8) connect _WIRE.`4`[0], _T_37 wire _WIRE_2 : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]} connect _WIRE_2.`0`[0], UInt<1>(0h0) connect _WIRE_2.`0`[1], UInt<1>(0h0) connect _WIRE_2.`1`[0], UInt<1>(0h0) connect _WIRE_2.`1`[1], UInt<1>(0h0) connect _WIRE_2.`2`[0], UInt<1>(0h0) connect _WIRE_2.`2`[1], UInt<1>(0h0) connect _WIRE_2.`3`[0], UInt<1>(0h0) connect _WIRE_2.`3`[1], UInt<1>(0h0) connect _WIRE_2.`4`[0], UInt<1>(0h0) node _T_38 = mux(_T_7, _WIRE, _WIRE_2) connect in_alloc.`0`, _T_38.`0` connect in_alloc.`1`, _T_38.`1` connect in_alloc.`2`, _T_38.`2` connect in_alloc.`3`, _T_38.`3` connect in_alloc.`4`, _T_38.`4` node _io_req_0_ready_T = bits(in_arb_sel, 0, 0) connect io.req.`0`.ready, _io_req_0_ready_T connect io.resp.`0`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`0`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`0`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`0`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`0`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`0`.vc_sel.`2`[1], in_alloc.`2`[1] connect io.resp.`0`.vc_sel.`3`[0], in_alloc.`3`[0] connect io.resp.`0`.vc_sel.`3`[1], in_alloc.`3`[1] connect io.resp.`0`.vc_sel.`4`[0], in_alloc.`4`[0] node _T_39 = cat(io.resp.`0`.vc_sel.`0`[1], io.resp.`0`.vc_sel.`0`[0]) node _T_40 = cat(io.resp.`0`.vc_sel.`1`[1], io.resp.`0`.vc_sel.`1`[0]) node _T_41 = cat(io.resp.`0`.vc_sel.`2`[1], io.resp.`0`.vc_sel.`2`[0]) node _T_42 = cat(io.resp.`0`.vc_sel.`3`[1], io.resp.`0`.vc_sel.`3`[0]) node lo_3 = cat(_T_40, _T_39) node hi_hi_1 = cat(io.resp.`0`.vc_sel.`4`[0], _T_42) node hi_3 = cat(hi_hi_1, _T_41) node _T_43 = cat(hi_3, lo_3) node _T_44 = bits(_T_43, 0, 0) node _T_45 = bits(_T_43, 1, 1) node _T_46 = bits(_T_43, 2, 2) node _T_47 = bits(_T_43, 3, 3) node _T_48 = bits(_T_43, 4, 4) node _T_49 = bits(_T_43, 5, 5) node _T_50 = bits(_T_43, 6, 6) node _T_51 = bits(_T_43, 7, 7) node _T_52 = bits(_T_43, 8, 8) node _T_53 = add(_T_44, _T_45) node _T_54 = bits(_T_53, 1, 0) node _T_55 = add(_T_46, _T_47) node _T_56 = bits(_T_55, 1, 0) node _T_57 = add(_T_54, _T_56) node _T_58 = bits(_T_57, 2, 0) node _T_59 = add(_T_48, _T_49) node _T_60 = bits(_T_59, 1, 0) node _T_61 = add(_T_51, _T_52) node _T_62 = bits(_T_61, 1, 0) node _T_63 = add(_T_50, _T_62) node _T_64 = bits(_T_63, 1, 0) node _T_65 = add(_T_60, _T_64) node _T_66 = bits(_T_65, 2, 0) node _T_67 = add(_T_58, _T_66) node _T_68 = bits(_T_67, 3, 0) node _T_69 = leq(_T_68, UInt<1>(0h1)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf assert(clock, _T_69, UInt<1>(0h1), "") : assert node _io_req_1_ready_T = bits(in_arb_sel, 1, 1) connect io.req.`1`.ready, _io_req_1_ready_T connect io.resp.`1`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`1`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`1`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`1`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`1`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`1`.vc_sel.`2`[1], in_alloc.`2`[1] connect io.resp.`1`.vc_sel.`3`[0], in_alloc.`3`[0] connect io.resp.`1`.vc_sel.`3`[1], in_alloc.`3`[1] connect io.resp.`1`.vc_sel.`4`[0], in_alloc.`4`[0] node _T_73 = cat(io.resp.`1`.vc_sel.`0`[1], io.resp.`1`.vc_sel.`0`[0]) node _T_74 = cat(io.resp.`1`.vc_sel.`1`[1], io.resp.`1`.vc_sel.`1`[0]) node _T_75 = cat(io.resp.`1`.vc_sel.`2`[1], io.resp.`1`.vc_sel.`2`[0]) node _T_76 = cat(io.resp.`1`.vc_sel.`3`[1], io.resp.`1`.vc_sel.`3`[0]) node lo_4 = cat(_T_74, _T_73) node hi_hi_2 = cat(io.resp.`1`.vc_sel.`4`[0], _T_76) node hi_4 = cat(hi_hi_2, _T_75) node _T_77 = cat(hi_4, lo_4) node _T_78 = bits(_T_77, 0, 0) node _T_79 = bits(_T_77, 1, 1) node _T_80 = bits(_T_77, 2, 2) node _T_81 = bits(_T_77, 3, 3) node _T_82 = bits(_T_77, 4, 4) node _T_83 = bits(_T_77, 5, 5) node _T_84 = bits(_T_77, 6, 6) node _T_85 = bits(_T_77, 7, 7) node _T_86 = bits(_T_77, 8, 8) node _T_87 = add(_T_78, _T_79) node _T_88 = bits(_T_87, 1, 0) node _T_89 = add(_T_80, _T_81) node _T_90 = bits(_T_89, 1, 0) node _T_91 = add(_T_88, _T_90) node _T_92 = bits(_T_91, 2, 0) node _T_93 = add(_T_82, _T_83) node _T_94 = bits(_T_93, 1, 0) node _T_95 = add(_T_85, _T_86) node _T_96 = bits(_T_95, 1, 0) node _T_97 = add(_T_84, _T_96) node _T_98 = bits(_T_97, 1, 0) node _T_99 = add(_T_94, _T_98) node _T_100 = bits(_T_99, 2, 0) node _T_101 = add(_T_92, _T_100) node _T_102 = bits(_T_101, 3, 0) node _T_103 = leq(_T_102, UInt<1>(0h1)) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _io_req_2_ready_T = bits(in_arb_sel, 2, 2) connect io.req.`2`.ready, _io_req_2_ready_T connect io.resp.`2`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`2`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`2`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`2`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`2`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`2`.vc_sel.`2`[1], in_alloc.`2`[1] connect io.resp.`2`.vc_sel.`3`[0], in_alloc.`3`[0] connect io.resp.`2`.vc_sel.`3`[1], in_alloc.`3`[1] connect io.resp.`2`.vc_sel.`4`[0], in_alloc.`4`[0] node _T_107 = cat(io.resp.`2`.vc_sel.`0`[1], io.resp.`2`.vc_sel.`0`[0]) node _T_108 = cat(io.resp.`2`.vc_sel.`1`[1], io.resp.`2`.vc_sel.`1`[0]) node _T_109 = cat(io.resp.`2`.vc_sel.`2`[1], io.resp.`2`.vc_sel.`2`[0]) node _T_110 = cat(io.resp.`2`.vc_sel.`3`[1], io.resp.`2`.vc_sel.`3`[0]) node lo_5 = cat(_T_108, _T_107) node hi_hi_3 = cat(io.resp.`2`.vc_sel.`4`[0], _T_110) node hi_5 = cat(hi_hi_3, _T_109) node _T_111 = cat(hi_5, lo_5) node _T_112 = bits(_T_111, 0, 0) node _T_113 = bits(_T_111, 1, 1) node _T_114 = bits(_T_111, 2, 2) node _T_115 = bits(_T_111, 3, 3) node _T_116 = bits(_T_111, 4, 4) node _T_117 = bits(_T_111, 5, 5) node _T_118 = bits(_T_111, 6, 6) node _T_119 = bits(_T_111, 7, 7) node _T_120 = bits(_T_111, 8, 8) node _T_121 = add(_T_112, _T_113) node _T_122 = bits(_T_121, 1, 0) node _T_123 = add(_T_114, _T_115) node _T_124 = bits(_T_123, 1, 0) node _T_125 = add(_T_122, _T_124) node _T_126 = bits(_T_125, 2, 0) node _T_127 = add(_T_116, _T_117) node _T_128 = bits(_T_127, 1, 0) node _T_129 = add(_T_119, _T_120) node _T_130 = bits(_T_129, 1, 0) node _T_131 = add(_T_118, _T_130) node _T_132 = bits(_T_131, 1, 0) node _T_133 = add(_T_128, _T_132) node _T_134 = bits(_T_133, 2, 0) node _T_135 = add(_T_126, _T_134) node _T_136 = bits(_T_135, 3, 0) node _T_137 = leq(_T_136, UInt<1>(0h1)) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_2 assert(clock, _T_137, UInt<1>(0h1), "") : assert_2 node _io_req_3_ready_T = bits(in_arb_sel, 3, 3) connect io.req.`3`.ready, _io_req_3_ready_T connect io.resp.`3`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`3`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`3`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`3`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`3`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`3`.vc_sel.`2`[1], in_alloc.`2`[1] connect io.resp.`3`.vc_sel.`3`[0], in_alloc.`3`[0] connect io.resp.`3`.vc_sel.`3`[1], in_alloc.`3`[1] connect io.resp.`3`.vc_sel.`4`[0], in_alloc.`4`[0] node _T_141 = cat(io.resp.`3`.vc_sel.`0`[1], io.resp.`3`.vc_sel.`0`[0]) node _T_142 = cat(io.resp.`3`.vc_sel.`1`[1], io.resp.`3`.vc_sel.`1`[0]) node _T_143 = cat(io.resp.`3`.vc_sel.`2`[1], io.resp.`3`.vc_sel.`2`[0]) node _T_144 = cat(io.resp.`3`.vc_sel.`3`[1], io.resp.`3`.vc_sel.`3`[0]) node lo_6 = cat(_T_142, _T_141) node hi_hi_4 = cat(io.resp.`3`.vc_sel.`4`[0], _T_144) node hi_6 = cat(hi_hi_4, _T_143) node _T_145 = cat(hi_6, lo_6) node _T_146 = bits(_T_145, 0, 0) node _T_147 = bits(_T_145, 1, 1) node _T_148 = bits(_T_145, 2, 2) node _T_149 = bits(_T_145, 3, 3) node _T_150 = bits(_T_145, 4, 4) node _T_151 = bits(_T_145, 5, 5) node _T_152 = bits(_T_145, 6, 6) node _T_153 = bits(_T_145, 7, 7) node _T_154 = bits(_T_145, 8, 8) node _T_155 = add(_T_146, _T_147) node _T_156 = bits(_T_155, 1, 0) node _T_157 = add(_T_148, _T_149) node _T_158 = bits(_T_157, 1, 0) node _T_159 = add(_T_156, _T_158) node _T_160 = bits(_T_159, 2, 0) node _T_161 = add(_T_150, _T_151) node _T_162 = bits(_T_161, 1, 0) node _T_163 = add(_T_153, _T_154) node _T_164 = bits(_T_163, 1, 0) node _T_165 = add(_T_152, _T_164) node _T_166 = bits(_T_165, 1, 0) node _T_167 = add(_T_162, _T_166) node _T_168 = bits(_T_167, 2, 0) node _T_169 = add(_T_160, _T_168) node _T_170 = bits(_T_169, 3, 0) node _T_171 = leq(_T_170, UInt<1>(0h1)) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_3 assert(clock, _T_171, UInt<1>(0h1), "") : assert_3 node _io_req_4_ready_T = bits(in_arb_sel, 4, 4) connect io.req.`4`.ready, _io_req_4_ready_T connect io.resp.`4`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`4`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`4`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`4`.vc_sel.`1`[1], in_alloc.`1`[1] connect io.resp.`4`.vc_sel.`2`[0], in_alloc.`2`[0] connect io.resp.`4`.vc_sel.`2`[1], in_alloc.`2`[1] connect io.resp.`4`.vc_sel.`3`[0], in_alloc.`3`[0] connect io.resp.`4`.vc_sel.`3`[1], in_alloc.`3`[1] connect io.resp.`4`.vc_sel.`4`[0], in_alloc.`4`[0] node _T_175 = cat(io.resp.`4`.vc_sel.`0`[1], io.resp.`4`.vc_sel.`0`[0]) node _T_176 = cat(io.resp.`4`.vc_sel.`1`[1], io.resp.`4`.vc_sel.`1`[0]) node _T_177 = cat(io.resp.`4`.vc_sel.`2`[1], io.resp.`4`.vc_sel.`2`[0]) node _T_178 = cat(io.resp.`4`.vc_sel.`3`[1], io.resp.`4`.vc_sel.`3`[0]) node lo_7 = cat(_T_176, _T_175) node hi_hi_5 = cat(io.resp.`4`.vc_sel.`4`[0], _T_178) node hi_7 = cat(hi_hi_5, _T_177) node _T_179 = cat(hi_7, lo_7) node _T_180 = bits(_T_179, 0, 0) node _T_181 = bits(_T_179, 1, 1) node _T_182 = bits(_T_179, 2, 2) node _T_183 = bits(_T_179, 3, 3) node _T_184 = bits(_T_179, 4, 4) node _T_185 = bits(_T_179, 5, 5) node _T_186 = bits(_T_179, 6, 6) node _T_187 = bits(_T_179, 7, 7) node _T_188 = bits(_T_179, 8, 8) node _T_189 = add(_T_180, _T_181) node _T_190 = bits(_T_189, 1, 0) node _T_191 = add(_T_182, _T_183) node _T_192 = bits(_T_191, 1, 0) node _T_193 = add(_T_190, _T_192) node _T_194 = bits(_T_193, 2, 0) node _T_195 = add(_T_184, _T_185) node _T_196 = bits(_T_195, 1, 0) node _T_197 = add(_T_187, _T_188) node _T_198 = bits(_T_197, 1, 0) node _T_199 = add(_T_186, _T_198) node _T_200 = bits(_T_199, 1, 0) node _T_201 = add(_T_196, _T_200) node _T_202 = bits(_T_201, 2, 0) node _T_203 = add(_T_194, _T_202) node _T_204 = bits(_T_203, 3, 0) node _T_205 = leq(_T_204, UInt<1>(0h1)) node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(_T_205, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_4 assert(clock, _T_205, UInt<1>(0h1), "") : assert_4 connect io.out_allocs.`0`[0].alloc, in_alloc.`0`[0] connect io.out_allocs.`0`[0].flow, in_flow connect io.out_allocs.`0`[1].alloc, in_alloc.`0`[1] connect io.out_allocs.`0`[1].flow, in_flow connect io.out_allocs.`1`[0].alloc, in_alloc.`1`[0] connect io.out_allocs.`1`[0].flow, in_flow connect io.out_allocs.`1`[1].alloc, in_alloc.`1`[1] connect io.out_allocs.`1`[1].flow, in_flow connect io.out_allocs.`2`[0].alloc, in_alloc.`2`[0] connect io.out_allocs.`2`[0].flow, in_flow connect io.out_allocs.`2`[1].alloc, in_alloc.`2`[1] connect io.out_allocs.`2`[1].flow, in_flow connect io.out_allocs.`3`[0].alloc, in_alloc.`3`[0] connect io.out_allocs.`3`[0].flow, in_flow connect io.out_allocs.`3`[1].alloc, in_alloc.`3`[1] connect io.out_allocs.`3`[1].flow, in_flow connect io.out_allocs.`4`[0].alloc, in_alloc.`4`[0] connect io.out_allocs.`4`[0].flow, in_flow	module RotatingSingleVCAllocator_21( // @[ISLIP.scala:43:7] input clock, // @[ISLIP.scala:43:7] input reset, // @[ISLIP.scala:43:7] output io_req_4_ready, // @[VCAllocator.scala:49:14] input io_req_4_valid, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_3_1, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_req_3_ready, // @[VCAllocator.scala:49:14] input io_req_3_valid, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_3_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_req_2_ready, // @[VCAllocator.scala:49:14] input io_req_2_valid, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_3_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_req_1_ready, // @[VCAllocator.scala:49:14] input io_req_1_valid, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_3_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_req_0_ready, // @[VCAllocator.scala:49:14] input io_req_0_valid, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_3_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_4_0, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_3_1, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_4_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_4_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_3_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_4_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_3_1, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_4_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_3_1, // @[VCAllocator.scala:49:14] input io_channel_status_4_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_3_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_3_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14] output io_out_allocs_4_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_3_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_3_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_1_alloc // @[VCAllocator.scala:49:14] ); wire in_arb_vals_4; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_3; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39] reg [4:0] mask; // @[SingleVCAllocator.scala:16:21] wire [4:0] _in_arb_filter_T_3 = {in_arb_vals_4, in_arb_vals_3, in_arb_vals_2, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39] wire [9:0] in_arb_filter = _in_arb_filter_T_3[0] ? 10'h1 : _in_arb_filter_T_3[1] ? 10'h2 : _in_arb_filter_T_3[2] ? 10'h4 : _in_arb_filter_T_3[3] ? 10'h8 : _in_arb_filter_T_3[4] ? 10'h10 : in_arb_vals_0 ? 10'h20 : in_arb_vals_1 ? 10'h40 : in_arb_vals_2 ? 10'h80 : in_arb_vals_3 ? 10'h100 : {in_arb_vals_4, 9'h0}; // @[OneHot.scala:85:71] wire [4:0] in_arb_sel = in_arb_filter[4:0] \| in_arb_filter[9:5]; // @[Mux.scala:50:70] wire _GEN = in_arb_vals_0 \| in_arb_vals_1 \| in_arb_vals_2 \| in_arb_vals_3 \| in_arb_vals_4; // @[package.scala:81:59] wire in_arb_reqs_0_0_0 = io_req_0_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_0_1 = io_req_0_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_1 = io_req_0_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_1 = io_req_0_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_3_0 = io_req_0_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_3_1 = io_req_0_bits_vc_sel_3_1 & ~io_channel_status_3_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_4_0 = io_req_0_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_0_0 \| in_arb_reqs_0_0_1 \| in_arb_reqs_0_1_0 \| in_arb_reqs_0_1_1 \| in_arb_reqs_0_2_0 \| in_arb_reqs_0_2_1 \| in_arb_reqs_0_3_0 \| in_arb_reqs_0_3_1 \| in_arb_reqs_0_4_0); // @[package.scala:81:59] wire in_arb_reqs_1_0_0 = io_req_1_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_1 = io_req_1_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_0 = io_req_1_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_1 = io_req_1_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_1 = io_req_1_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_3_0 = io_req_1_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_3_1 = io_req_1_bits_vc_sel_3_1 & ~io_channel_status_3_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_4_0 = io_req_1_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_0_0 \| in_arb_reqs_1_0_1 \| in_arb_reqs_1_1_0 \| in_arb_reqs_1_1_1 \| in_arb_reqs_1_2_0 \| in_arb_reqs_1_2_1 \| in_arb_reqs_1_3_0 \| in_arb_reqs_1_3_1 \| in_arb_reqs_1_4_0); // @[package.scala:81:59] wire in_arb_reqs_2_0_0 = io_req_2_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_1 = io_req_2_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_0 = io_req_2_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_1 = io_req_2_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_2_0 = io_req_2_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_2_1 = io_req_2_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_3_0 = io_req_2_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_3_1 = io_req_2_bits_vc_sel_3_1 & ~io_channel_status_3_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_4_0 = io_req_2_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_2 = io_req_2_valid & (in_arb_reqs_2_0_0 \| in_arb_reqs_2_0_1 \| in_arb_reqs_2_1_0 \| in_arb_reqs_2_1_1 \| in_arb_reqs_2_2_0 \| in_arb_reqs_2_2_1 \| in_arb_reqs_2_3_0 \| in_arb_reqs_2_3_1 \| in_arb_reqs_2_4_0); // @[package.scala:81:59] wire in_arb_reqs_3_0_0 = io_req_3_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_0_1 = io_req_3_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_0 = io_req_3_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_1 = io_req_3_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_2_0 = io_req_3_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_2_1 = io_req_3_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_3_0 = io_req_3_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_3_1 = io_req_3_bits_vc_sel_3_1 & ~io_channel_status_3_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_4_0 = io_req_3_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_3 = io_req_3_valid & (in_arb_reqs_3_0_0 \| in_arb_reqs_3_0_1 \| in_arb_reqs_3_1_0 \| in_arb_reqs_3_1_1 \| in_arb_reqs_3_2_0 \| in_arb_reqs_3_2_1 \| in_arb_reqs_3_3_0 \| in_arb_reqs_3_3_1 \| in_arb_reqs_3_4_0); // @[package.scala:81:59] wire in_arb_reqs_4_0_0 = io_req_4_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_0_1 = io_req_4_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_1_0 = io_req_4_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_1_1 = io_req_4_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_2_0 = io_req_4_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_2_1 = io_req_4_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_3_0 = io_req_4_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_3_1 = io_req_4_bits_vc_sel_3_1 & ~io_channel_status_3_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_4_0 = io_req_4_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_4 = io_req_4_valid & (in_arb_reqs_4_0_0 \| in_arb_reqs_4_0_1 \| in_arb_reqs_4_1_0 \| in_arb_reqs_4_1_1 \| in_arb_reqs_4_2_0 \| in_arb_reqs_4_2_1 \| in_arb_reqs_4_3_0 \| in_arb_reqs_4_3_1 \| in_arb_reqs_4_4_0); // @[package.scala:81:59] wire _in_vc_sel_T_13 = in_arb_sel[0] & in_arb_reqs_0_0_0 \| in_arb_sel[1] & in_arb_reqs_1_0_0 \| in_arb_sel[2] & in_arb_reqs_2_0_0 \| in_arb_sel[3] & in_arb_reqs_3_0_0 \| in_arb_sel[4] & in_arb_reqs_4_0_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_22 = in_arb_sel[0] & in_arb_reqs_0_0_1 \| in_arb_sel[1] & in_arb_reqs_1_0_1 \| in_arb_sel[2] & in_arb_reqs_2_0_1 \| in_arb_sel[3] & in_arb_reqs_3_0_1 \| in_arb_sel[4] & in_arb_reqs_4_0_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_31 = in_arb_sel[0] & in_arb_reqs_0_1_0 \| in_arb_sel[1] & in_arb_reqs_1_1_0 \| in_arb_sel[2] & in_arb_reqs_2_1_0 \| in_arb_sel[3] & in_arb_reqs_3_1_0 \| in_arb_sel[4] & in_arb_reqs_4_1_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_40 = in_arb_sel[0] & in_arb_reqs_0_1_1 \| in_arb_sel[1] & in_arb_reqs_1_1_1 \| in_arb_sel[2] & in_arb_reqs_2_1_1 \| in_arb_sel[3] & in_arb_reqs_3_1_1 \| in_arb_sel[4] & in_arb_reqs_4_1_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_49 = in_arb_sel[0] & in_arb_reqs_0_2_0 \| in_arb_sel[1] & in_arb_reqs_1_2_0 \| in_arb_sel[2] & in_arb_reqs_2_2_0 \| in_arb_sel[3] & in_arb_reqs_3_2_0 \| in_arb_sel[4] & in_arb_reqs_4_2_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_58 = in_arb_sel[0] & in_arb_reqs_0_2_1 \| in_arb_sel[1] & in_arb_reqs_1_2_1 \| in_arb_sel[2] & in_arb_reqs_2_2_1 \| in_arb_sel[3] & in_arb_reqs_3_2_1 \| in_arb_sel[4] & in_arb_reqs_4_2_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_67 = in_arb_sel[0] & in_arb_reqs_0_3_0 \| in_arb_sel[1] & in_arb_reqs_1_3_0 \| in_arb_sel[2] & in_arb_reqs_2_3_0 \| in_arb_sel[3] & in_arb_reqs_3_3_0 \| in_arb_sel[4] & in_arb_reqs_4_3_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_76 = in_arb_sel[0] & in_arb_reqs_0_3_1 \| in_arb_sel[1] & in_arb_reqs_1_3_1 \| in_arb_sel[2] & in_arb_reqs_2_3_1 \| in_arb_sel[3] & in_arb_reqs_3_3_1 \| in_arb_sel[4] & in_arb_reqs_4_3_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_85 = in_arb_sel[0] & in_arb_reqs_0_4_0 \| in_arb_sel[1] & in_arb_reqs_1_4_0 \| in_arb_sel[2] & in_arb_reqs_2_4_0 \| in_arb_sel[3] & in_arb_reqs_3_4_0 \| in_arb_sel[4] & in_arb_reqs_4_4_0; // @[Mux.scala:30:73, :32:36] reg [8:0] mask_1; // @[ISLIP.scala:17:25] wire [8:0] _full_T_1 = {_in_vc_sel_T_85, _in_vc_sel_T_76, _in_vc_sel_T_67, _in_vc_sel_T_58, _in_vc_sel_T_49, _in_vc_sel_T_40, _in_vc_sel_T_31, _in_vc_sel_T_22, _in_vc_sel_T_13} & ~mask_1; // @[Mux.scala:30:73] wire [17:0] oh = _full_T_1[0] ? 18'h1 : _full_T_1[1] ? 18'h2 : _full_T_1[2] ? 18'h4 : _full_T_1[3] ? 18'h8 : _full_T_1[4] ? 18'h10 : _full_T_1[5] ? 18'h20 : _full_T_1[6] ? 18'h40 : _full_T_1[7] ? 18'h80 : _full_T_1[8] ? 18'h100 : _in_vc_sel_T_13 ? 18'h200 : _in_vc_sel_T_22 ? 18'h400 : _in_vc_sel_T_31 ? 18'h800 : _in_vc_sel_T_40 ? 18'h1000 : _in_vc_sel_T_49 ? 18'h2000 : _in_vc_sel_T_58 ? 18'h4000 : _in_vc_sel_T_67 ? 18'h8000 : _in_vc_sel_T_76 ? 18'h10000 : {_in_vc_sel_T_85, 17'h0}; // @[OneHot.scala:85:71] wire [8:0] sel = oh[8:0] \| oh[17:9]; // @[Mux.scala:50:70] wire in_alloc_4_0 = _GEN & sel[8]; // @[package.scala:81:59] wire in_alloc_3_0 = _GEN & sel[6]; // @[package.scala:81:59] wire in_alloc_3_1 = _GEN & sel[7]; // @[package.scala:81:59] wire in_alloc_2_0 = _GEN & sel[4]; // @[package.scala:81:59] wire in_alloc_2_1 = _GEN & sel[5]; // @[package.scala:81:59] wire in_alloc_1_0 = _GEN & sel[2]; // @[package.scala:81:59] wire in_alloc_1_1 = _GEN & sel[3]; // @[package.scala:81:59] wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59] wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_469 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_469( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module OFSeqToCode_1 : input clock : Clock input reset : Reset output io : { flip ofbase : UInt<32>, ofcode : UInt<8>} node _io_ofcode_highBit_T = shl(UInt<16>(0hffff), 16) node _io_ofcode_highBit_T_1 = xor(UInt<32>(0hffffffff), _io_ofcode_highBit_T) node _io_ofcode_highBit_T_2 = shr(io.ofbase, 16) node _io_ofcode_highBit_T_3 = and(_io_ofcode_highBit_T_2, _io_ofcode_highBit_T_1) node _io_ofcode_highBit_T_4 = bits(io.ofbase, 15, 0) node _io_ofcode_highBit_T_5 = shl(_io_ofcode_highBit_T_4, 16) node _io_ofcode_highBit_T_6 = not(_io_ofcode_highBit_T_1) node _io_ofcode_highBit_T_7 = and(_io_ofcode_highBit_T_5, _io_ofcode_highBit_T_6) node _io_ofcode_highBit_T_8 = or(_io_ofcode_highBit_T_3, _io_ofcode_highBit_T_7) node _io_ofcode_highBit_T_9 = bits(_io_ofcode_highBit_T_1, 23, 0) node _io_ofcode_highBit_T_10 = shl(_io_ofcode_highBit_T_9, 8) node _io_ofcode_highBit_T_11 = xor(_io_ofcode_highBit_T_1, _io_ofcode_highBit_T_10) node _io_ofcode_highBit_T_12 = shr(_io_ofcode_highBit_T_8, 8) node _io_ofcode_highBit_T_13 = and(_io_ofcode_highBit_T_12, _io_ofcode_highBit_T_11) node _io_ofcode_highBit_T_14 = bits(_io_ofcode_highBit_T_8, 23, 0) node _io_ofcode_highBit_T_15 = shl(_io_ofcode_highBit_T_14, 8) node _io_ofcode_highBit_T_16 = not(_io_ofcode_highBit_T_11) node _io_ofcode_highBit_T_17 = and(_io_ofcode_highBit_T_15, _io_ofcode_highBit_T_16) node _io_ofcode_highBit_T_18 = or(_io_ofcode_highBit_T_13, _io_ofcode_highBit_T_17) node _io_ofcode_highBit_T_19 = bits(_io_ofcode_highBit_T_11, 27, 0) node _io_ofcode_highBit_T_20 = shl(_io_ofcode_highBit_T_19, 4) node _io_ofcode_highBit_T_21 = xor(_io_ofcode_highBit_T_11, _io_ofcode_highBit_T_20) node _io_ofcode_highBit_T_22 = shr(_io_ofcode_highBit_T_18, 4) node _io_ofcode_highBit_T_23 = and(_io_ofcode_highBit_T_22, _io_ofcode_highBit_T_21) node _io_ofcode_highBit_T_24 = bits(_io_ofcode_highBit_T_18, 27, 0) node _io_ofcode_highBit_T_25 = shl(_io_ofcode_highBit_T_24, 4) node _io_ofcode_highBit_T_26 = not(_io_ofcode_highBit_T_21) node _io_ofcode_highBit_T_27 = and(_io_ofcode_highBit_T_25, _io_ofcode_highBit_T_26) node _io_ofcode_highBit_T_28 = or(_io_ofcode_highBit_T_23, _io_ofcode_highBit_T_27) node _io_ofcode_highBit_T_29 = bits(_io_ofcode_highBit_T_21, 29, 0) node _io_ofcode_highBit_T_30 = shl(_io_ofcode_highBit_T_29, 2) node _io_ofcode_highBit_T_31 = xor(_io_ofcode_highBit_T_21, _io_ofcode_highBit_T_30) node _io_ofcode_highBit_T_32 = shr(_io_ofcode_highBit_T_28, 2) node _io_ofcode_highBit_T_33 = and(_io_ofcode_highBit_T_32, _io_ofcode_highBit_T_31) node _io_ofcode_highBit_T_34 = bits(_io_ofcode_highBit_T_28, 29, 0) node _io_ofcode_highBit_T_35 = shl(_io_ofcode_highBit_T_34, 2) node _io_ofcode_highBit_T_36 = not(_io_ofcode_highBit_T_31) node _io_ofcode_highBit_T_37 = and(_io_ofcode_highBit_T_35, _io_ofcode_highBit_T_36) node _io_ofcode_highBit_T_38 = or(_io_ofcode_highBit_T_33, _io_ofcode_highBit_T_37) node _io_ofcode_highBit_T_39 = bits(_io_ofcode_highBit_T_31, 30, 0) node _io_ofcode_highBit_T_40 = shl(_io_ofcode_highBit_T_39, 1) node _io_ofcode_highBit_T_41 = xor(_io_ofcode_highBit_T_31, _io_ofcode_highBit_T_40) node _io_ofcode_highBit_T_42 = shr(_io_ofcode_highBit_T_38, 1) node _io_ofcode_highBit_T_43 = and(_io_ofcode_highBit_T_42, _io_ofcode_highBit_T_41) node _io_ofcode_highBit_T_44 = bits(_io_ofcode_highBit_T_38, 30, 0) node _io_ofcode_highBit_T_45 = shl(_io_ofcode_highBit_T_44, 1) node _io_ofcode_highBit_T_46 = not(_io_ofcode_highBit_T_41) node _io_ofcode_highBit_T_47 = and(_io_ofcode_highBit_T_45, _io_ofcode_highBit_T_46) node _io_ofcode_highBit_T_48 = or(_io_ofcode_highBit_T_43, _io_ofcode_highBit_T_47) node _io_ofcode_highBit_T_49 = bits(_io_ofcode_highBit_T_48, 0, 0) node _io_ofcode_highBit_T_50 = bits(_io_ofcode_highBit_T_48, 1, 1) node _io_ofcode_highBit_T_51 = bits(_io_ofcode_highBit_T_48, 2, 2) node _io_ofcode_highBit_T_52 = bits(_io_ofcode_highBit_T_48, 3, 3) node _io_ofcode_highBit_T_53 = bits(_io_ofcode_highBit_T_48, 4, 4) node _io_ofcode_highBit_T_54 = bits(_io_ofcode_highBit_T_48, 5, 5) node _io_ofcode_highBit_T_55 = bits(_io_ofcode_highBit_T_48, 6, 6) node _io_ofcode_highBit_T_56 = bits(_io_ofcode_highBit_T_48, 7, 7) node _io_ofcode_highBit_T_57 = bits(_io_ofcode_highBit_T_48, 8, 8) node _io_ofcode_highBit_T_58 = bits(_io_ofcode_highBit_T_48, 9, 9) node _io_ofcode_highBit_T_59 = bits(_io_ofcode_highBit_T_48, 10, 10) node _io_ofcode_highBit_T_60 = bits(_io_ofcode_highBit_T_48, 11, 11) node _io_ofcode_highBit_T_61 = bits(_io_ofcode_highBit_T_48, 12, 12) node _io_ofcode_highBit_T_62 = bits(_io_ofcode_highBit_T_48, 13, 13) node _io_ofcode_highBit_T_63 = bits(_io_ofcode_highBit_T_48, 14, 14) node _io_ofcode_highBit_T_64 = bits(_io_ofcode_highBit_T_48, 15, 15) node _io_ofcode_highBit_T_65 = bits(_io_ofcode_highBit_T_48, 16, 16) node _io_ofcode_highBit_T_66 = bits(_io_ofcode_highBit_T_48, 17, 17) node _io_ofcode_highBit_T_67 = bits(_io_ofcode_highBit_T_48, 18, 18) node _io_ofcode_highBit_T_68 = bits(_io_ofcode_highBit_T_48, 19, 19) node _io_ofcode_highBit_T_69 = bits(_io_ofcode_highBit_T_48, 20, 20) node _io_ofcode_highBit_T_70 = bits(_io_ofcode_highBit_T_48, 21, 21) node _io_ofcode_highBit_T_71 = bits(_io_ofcode_highBit_T_48, 22, 22) node _io_ofcode_highBit_T_72 = bits(_io_ofcode_highBit_T_48, 23, 23) node _io_ofcode_highBit_T_73 = bits(_io_ofcode_highBit_T_48, 24, 24) node _io_ofcode_highBit_T_74 = bits(_io_ofcode_highBit_T_48, 25, 25) node _io_ofcode_highBit_T_75 = bits(_io_ofcode_highBit_T_48, 26, 26) node _io_ofcode_highBit_T_76 = bits(_io_ofcode_highBit_T_48, 27, 27) node _io_ofcode_highBit_T_77 = bits(_io_ofcode_highBit_T_48, 28, 28) node _io_ofcode_highBit_T_78 = bits(_io_ofcode_highBit_T_48, 29, 29) node _io_ofcode_highBit_T_79 = bits(_io_ofcode_highBit_T_48, 30, 30) node _io_ofcode_highBit_T_80 = bits(_io_ofcode_highBit_T_48, 31, 31) node _io_ofcode_highBit_T_81 = mux(_io_ofcode_highBit_T_79, UInt<5>(0h1e), UInt<5>(0h1f)) node _io_ofcode_highBit_T_82 = mux(_io_ofcode_highBit_T_78, UInt<5>(0h1d), _io_ofcode_highBit_T_81) node _io_ofcode_highBit_T_83 = mux(_io_ofcode_highBit_T_77, UInt<5>(0h1c), _io_ofcode_highBit_T_82) node _io_ofcode_highBit_T_84 = mux(_io_ofcode_highBit_T_76, UInt<5>(0h1b), _io_ofcode_highBit_T_83) node _io_ofcode_highBit_T_85 = mux(_io_ofcode_highBit_T_75, UInt<5>(0h1a), _io_ofcode_highBit_T_84) node _io_ofcode_highBit_T_86 = mux(_io_ofcode_highBit_T_74, UInt<5>(0h19), _io_ofcode_highBit_T_85) node _io_ofcode_highBit_T_87 = mux(_io_ofcode_highBit_T_73, UInt<5>(0h18), _io_ofcode_highBit_T_86) node _io_ofcode_highBit_T_88 = mux(_io_ofcode_highBit_T_72, UInt<5>(0h17), _io_ofcode_highBit_T_87) node _io_ofcode_highBit_T_89 = mux(_io_ofcode_highBit_T_71, UInt<5>(0h16), _io_ofcode_highBit_T_88) node _io_ofcode_highBit_T_90 = mux(_io_ofcode_highBit_T_70, UInt<5>(0h15), _io_ofcode_highBit_T_89) node _io_ofcode_highBit_T_91 = mux(_io_ofcode_highBit_T_69, UInt<5>(0h14), _io_ofcode_highBit_T_90) node _io_ofcode_highBit_T_92 = mux(_io_ofcode_highBit_T_68, UInt<5>(0h13), _io_ofcode_highBit_T_91) node _io_ofcode_highBit_T_93 = mux(_io_ofcode_highBit_T_67, UInt<5>(0h12), _io_ofcode_highBit_T_92) node _io_ofcode_highBit_T_94 = mux(_io_ofcode_highBit_T_66, UInt<5>(0h11), _io_ofcode_highBit_T_93) node _io_ofcode_highBit_T_95 = mux(_io_ofcode_highBit_T_65, UInt<5>(0h10), _io_ofcode_highBit_T_94) node _io_ofcode_highBit_T_96 = mux(_io_ofcode_highBit_T_64, UInt<4>(0hf), _io_ofcode_highBit_T_95) node _io_ofcode_highBit_T_97 = mux(_io_ofcode_highBit_T_63, UInt<4>(0he), _io_ofcode_highBit_T_96) node _io_ofcode_highBit_T_98 = mux(_io_ofcode_highBit_T_62, UInt<4>(0hd), _io_ofcode_highBit_T_97) node _io_ofcode_highBit_T_99 = mux(_io_ofcode_highBit_T_61, UInt<4>(0hc), _io_ofcode_highBit_T_98) node _io_ofcode_highBit_T_100 = mux(_io_ofcode_highBit_T_60, UInt<4>(0hb), _io_ofcode_highBit_T_99) node _io_ofcode_highBit_T_101 = mux(_io_ofcode_highBit_T_59, UInt<4>(0ha), _io_ofcode_highBit_T_100) node _io_ofcode_highBit_T_102 = mux(_io_ofcode_highBit_T_58, UInt<4>(0h9), _io_ofcode_highBit_T_101) node _io_ofcode_highBit_T_103 = mux(_io_ofcode_highBit_T_57, UInt<4>(0h8), _io_ofcode_highBit_T_102) node _io_ofcode_highBit_T_104 = mux(_io_ofcode_highBit_T_56, UInt<3>(0h7), _io_ofcode_highBit_T_103) node _io_ofcode_highBit_T_105 = mux(_io_ofcode_highBit_T_55, UInt<3>(0h6), _io_ofcode_highBit_T_104) node _io_ofcode_highBit_T_106 = mux(_io_ofcode_highBit_T_54, UInt<3>(0h5), _io_ofcode_highBit_T_105) node _io_ofcode_highBit_T_107 = mux(_io_ofcode_highBit_T_53, UInt<3>(0h4), _io_ofcode_highBit_T_106) node _io_ofcode_highBit_T_108 = mux(_io_ofcode_highBit_T_52, UInt<2>(0h3), _io_ofcode_highBit_T_107) node _io_ofcode_highBit_T_109 = mux(_io_ofcode_highBit_T_51, UInt<2>(0h2), _io_ofcode_highBit_T_108) node _io_ofcode_highBit_T_110 = mux(_io_ofcode_highBit_T_50, UInt<1>(0h1), _io_ofcode_highBit_T_109) node _io_ofcode_highBit_T_111 = mux(_io_ofcode_highBit_T_49, UInt<1>(0h0), _io_ofcode_highBit_T_110) node _io_ofcode_highBit_T_112 = sub(UInt<5>(0h1f), _io_ofcode_highBit_T_111) node io_ofcode_highBit = tail(_io_ofcode_highBit_T_112, 1) connect io.ofcode, io_ofcode_highBit	module OFSeqToCode_1( // @[FSESequenceToCodeConverter.scala:192:7] input clock, // @[FSESequenceToCodeConverter.scala:192:7] input reset, // @[FSESequenceToCodeConverter.scala:192:7] input [31:0] io_ofbase, // @[FSESequenceToCodeConverter.scala:193:14] output [7:0] io_ofcode // @[FSESequenceToCodeConverter.scala:193:14] ); wire [31:0] io_ofbase_0 = io_ofbase; // @[FSESequenceToCodeConverter.scala:192:7] wire [31:0] _io_ofcode_highBit_T_1 = 32'hFFFF; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T = 32'hFFFF0000; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_6 = 32'hFFFF0000; // @[Common.scala:66:49] wire [23:0] _io_ofcode_highBit_T_9 = 24'hFFFF; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_10 = 32'hFFFF00; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_11 = 32'hFF00FF; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_16 = 32'hFF00FF00; // @[Common.scala:66:49] wire [27:0] _io_ofcode_highBit_T_19 = 28'hFF00FF; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_20 = 32'hFF00FF0; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_21 = 32'hF0F0F0F; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_26 = 32'hF0F0F0F0; // @[Common.scala:66:49] wire [29:0] _io_ofcode_highBit_T_29 = 30'hF0F0F0F; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_30 = 32'h3C3C3C3C; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_31 = 32'h33333333; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_36 = 32'hCCCCCCCC; // @[Common.scala:66:49] wire [30:0] _io_ofcode_highBit_T_39 = 31'h33333333; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_40 = 32'h66666666; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_41 = 32'h55555555; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_46 = 32'hAAAAAAAA; // @[Common.scala:66:49] wire [7:0] io_ofcode_0; // @[FSESequenceToCodeConverter.scala:192:7] wire [15:0] _io_ofcode_highBit_T_2 = io_ofbase_0[31:16]; // @[FSESequenceToCodeConverter.scala:192:7] wire [31:0] _io_ofcode_highBit_T_3 = {16'h0, _io_ofcode_highBit_T_2}; // @[Common.scala:66:49] wire [15:0] _io_ofcode_highBit_T_4 = io_ofbase_0[15:0]; // @[FSESequenceToCodeConverter.scala:192:7] wire [31:0] _io_ofcode_highBit_T_5 = {_io_ofcode_highBit_T_4, 16'h0}; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_7 = _io_ofcode_highBit_T_5 & 32'hFFFF0000; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_8 = _io_ofcode_highBit_T_3 \| _io_ofcode_highBit_T_7; // @[Common.scala:66:49] wire [23:0] _io_ofcode_highBit_T_12 = _io_ofcode_highBit_T_8[31:8]; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_13 = {8'h0, _io_ofcode_highBit_T_12 & 24'hFF00FF}; // @[Common.scala:66:49] wire [23:0] _io_ofcode_highBit_T_14 = _io_ofcode_highBit_T_8[23:0]; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_15 = {_io_ofcode_highBit_T_14, 8'h0}; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_17 = _io_ofcode_highBit_T_15 & 32'hFF00FF00; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_18 = _io_ofcode_highBit_T_13 \| _io_ofcode_highBit_T_17; // @[Common.scala:66:49] wire [27:0] _io_ofcode_highBit_T_22 = _io_ofcode_highBit_T_18[31:4]; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_23 = {4'h0, _io_ofcode_highBit_T_22 & 28'hF0F0F0F}; // @[Common.scala:66:49] wire [27:0] _io_ofcode_highBit_T_24 = _io_ofcode_highBit_T_18[27:0]; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_25 = {_io_ofcode_highBit_T_24, 4'h0}; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_27 = _io_ofcode_highBit_T_25 & 32'hF0F0F0F0; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_28 = _io_ofcode_highBit_T_23 \| _io_ofcode_highBit_T_27; // @[Common.scala:66:49] wire [29:0] _io_ofcode_highBit_T_32 = _io_ofcode_highBit_T_28[31:2]; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_33 = {2'h0, _io_ofcode_highBit_T_32 & 30'h33333333}; // @[Common.scala:66:49] wire [29:0] _io_ofcode_highBit_T_34 = _io_ofcode_highBit_T_28[29:0]; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_35 = {_io_ofcode_highBit_T_34, 2'h0}; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_37 = _io_ofcode_highBit_T_35 & 32'hCCCCCCCC; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_38 = _io_ofcode_highBit_T_33 \| _io_ofcode_highBit_T_37; // @[Common.scala:66:49] wire [30:0] _io_ofcode_highBit_T_42 = _io_ofcode_highBit_T_38[31:1]; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_43 = {1'h0, _io_ofcode_highBit_T_42 & 31'h55555555}; // @[Common.scala:66:49] wire [30:0] _io_ofcode_highBit_T_44 = _io_ofcode_highBit_T_38[30:0]; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_45 = {_io_ofcode_highBit_T_44, 1'h0}; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_47 = _io_ofcode_highBit_T_45 & 32'hAAAAAAAA; // @[Common.scala:66:49] wire [31:0] _io_ofcode_highBit_T_48 = _io_ofcode_highBit_T_43 \| _io_ofcode_highBit_T_47; // @[Common.scala:66:49] wire _io_ofcode_highBit_T_49 = _io_ofcode_highBit_T_48[0]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_50 = _io_ofcode_highBit_T_48[1]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_51 = _io_ofcode_highBit_T_48[2]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_52 = _io_ofcode_highBit_T_48[3]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_53 = _io_ofcode_highBit_T_48[4]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_54 = _io_ofcode_highBit_T_48[5]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_55 = _io_ofcode_highBit_T_48[6]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_56 = _io_ofcode_highBit_T_48[7]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_57 = _io_ofcode_highBit_T_48[8]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_58 = _io_ofcode_highBit_T_48[9]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_59 = _io_ofcode_highBit_T_48[10]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_60 = _io_ofcode_highBit_T_48[11]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_61 = _io_ofcode_highBit_T_48[12]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_62 = _io_ofcode_highBit_T_48[13]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_63 = _io_ofcode_highBit_T_48[14]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_64 = _io_ofcode_highBit_T_48[15]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_65 = _io_ofcode_highBit_T_48[16]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_66 = _io_ofcode_highBit_T_48[17]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_67 = _io_ofcode_highBit_T_48[18]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_68 = _io_ofcode_highBit_T_48[19]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_69 = _io_ofcode_highBit_T_48[20]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_70 = _io_ofcode_highBit_T_48[21]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_71 = _io_ofcode_highBit_T_48[22]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_72 = _io_ofcode_highBit_T_48[23]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_73 = _io_ofcode_highBit_T_48[24]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_74 = _io_ofcode_highBit_T_48[25]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_75 = _io_ofcode_highBit_T_48[26]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_76 = _io_ofcode_highBit_T_48[27]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_77 = _io_ofcode_highBit_T_48[28]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_78 = _io_ofcode_highBit_T_48[29]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_79 = _io_ofcode_highBit_T_48[30]; // @[OneHot.scala:48:45] wire _io_ofcode_highBit_T_80 = _io_ofcode_highBit_T_48[31]; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_81 = {4'hF, ~_io_ofcode_highBit_T_79}; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_82 = _io_ofcode_highBit_T_78 ? 5'h1D : _io_ofcode_highBit_T_81; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_83 = _io_ofcode_highBit_T_77 ? 5'h1C : _io_ofcode_highBit_T_82; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_84 = _io_ofcode_highBit_T_76 ? 5'h1B : _io_ofcode_highBit_T_83; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_85 = _io_ofcode_highBit_T_75 ? 5'h1A : _io_ofcode_highBit_T_84; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_86 = _io_ofcode_highBit_T_74 ? 5'h19 : _io_ofcode_highBit_T_85; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_87 = _io_ofcode_highBit_T_73 ? 5'h18 : _io_ofcode_highBit_T_86; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_88 = _io_ofcode_highBit_T_72 ? 5'h17 : _io_ofcode_highBit_T_87; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_89 = _io_ofcode_highBit_T_71 ? 5'h16 : _io_ofcode_highBit_T_88; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_90 = _io_ofcode_highBit_T_70 ? 5'h15 : _io_ofcode_highBit_T_89; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_91 = _io_ofcode_highBit_T_69 ? 5'h14 : _io_ofcode_highBit_T_90; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_92 = _io_ofcode_highBit_T_68 ? 5'h13 : _io_ofcode_highBit_T_91; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_93 = _io_ofcode_highBit_T_67 ? 5'h12 : _io_ofcode_highBit_T_92; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_94 = _io_ofcode_highBit_T_66 ? 5'h11 : _io_ofcode_highBit_T_93; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_95 = _io_ofcode_highBit_T_65 ? 5'h10 : _io_ofcode_highBit_T_94; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_96 = _io_ofcode_highBit_T_64 ? 5'hF : _io_ofcode_highBit_T_95; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_97 = _io_ofcode_highBit_T_63 ? 5'hE : _io_ofcode_highBit_T_96; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_98 = _io_ofcode_highBit_T_62 ? 5'hD : _io_ofcode_highBit_T_97; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_99 = _io_ofcode_highBit_T_61 ? 5'hC : _io_ofcode_highBit_T_98; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_100 = _io_ofcode_highBit_T_60 ? 5'hB : _io_ofcode_highBit_T_99; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_101 = _io_ofcode_highBit_T_59 ? 5'hA : _io_ofcode_highBit_T_100; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_102 = _io_ofcode_highBit_T_58 ? 5'h9 : _io_ofcode_highBit_T_101; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_103 = _io_ofcode_highBit_T_57 ? 5'h8 : _io_ofcode_highBit_T_102; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_104 = _io_ofcode_highBit_T_56 ? 5'h7 : _io_ofcode_highBit_T_103; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_105 = _io_ofcode_highBit_T_55 ? 5'h6 : _io_ofcode_highBit_T_104; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_106 = _io_ofcode_highBit_T_54 ? 5'h5 : _io_ofcode_highBit_T_105; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_107 = _io_ofcode_highBit_T_53 ? 5'h4 : _io_ofcode_highBit_T_106; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_108 = _io_ofcode_highBit_T_52 ? 5'h3 : _io_ofcode_highBit_T_107; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_109 = _io_ofcode_highBit_T_51 ? 5'h2 : _io_ofcode_highBit_T_108; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_110 = _io_ofcode_highBit_T_50 ? 5'h1 : _io_ofcode_highBit_T_109; // @[OneHot.scala:48:45] wire [4:0] _io_ofcode_highBit_T_111 = _io_ofcode_highBit_T_49 ? 5'h0 : _io_ofcode_highBit_T_110; // @[OneHot.scala:48:45] wire [5:0] _io_ofcode_highBit_T_112 = 6'h1F - {1'h0, _io_ofcode_highBit_T_111}; // @[Mux.scala:50:70] wire [4:0] io_ofcode_highBit = _io_ofcode_highBit_T_112[4:0]; // @[Common.scala:66:24] assign io_ofcode_0 = {3'h0, io_ofcode_highBit}; // @[FSESequenceToCodeConverter.scala:192:7, :198:13] assign io_ofcode = io_ofcode_0; // @[FSESequenceToCodeConverter.scala:192:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_110 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_110( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module DigitalTop : output auto : { flip chipyard_prcictrl_domain_reset_setter_clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, mbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}, cbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}} output psd : { } output resetctrl : { flip hartIsInReset : UInt<1>[1]} output debug : { flip clock : Clock, flip reset : Reset, systemjtag : { flip jtag : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}}, flip reset : Reset, flip mfr_id : UInt<11>, flip part_number : UInt<16>, flip version : UInt<4>}, ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>} output mem_tl : { } output mem_axi4 : { `0` : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}} output mmio_axi4 : { } input l2_frontend_bus_axi4 : { } input custom_boot : UInt<1> output serial_tl_0 : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip clock_in : Clock} output serial_tl_0_debug : { ser_busy : UInt<1>, des_busy : UInt<1>} output uart_0 : { txd : UInt<1>, flip rxd : UInt<1>} output clock_tap : Clock input interrupts : UInt<0> wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst ibus of ClockSinkDomain inst sbus of SystemBus inst pbus of PeripheryBus_pbus inst fbus of FrontBus inst cbus of PeripheryBus_cbus inst mbus of MemoryBus inst coh_wrapper of CoherenceManagerWrapper inst tile_prci_domain of TilePRCIDomain inst xbar of IntXbar_i1_o1_1 inst xbar_1 of IntXbar_i1_o1_2 inst xbar_2 of IntXbar_i1_o1_3 inst tileHartIdNexusNode of BundleBridgeNexus_UInt1_1 inst broadcast of BundleBridgeNexus_UInt32_1 inst clint_domain of CLINTClockSinkDomain inst plic_domain of PLICClockSinkDomain inst tlDM of TLDebugModule inst debugCustomXbarOpt of DebugCustomXbar inst nexus of BundleBridgeNexus_TraceBundle inst nexus_1 of BundleBridgeNexus_TraceCoreInterface inst bootrom_domain of BootROMClockSinkDomain inst bank of ScratchpadBank_4 inst serial_tl_domain of SerialTL0ClockSinkDomain inst uartClockDomainWrapper of TLUARTClockSinkDomain inst intsink of IntSyncSyncCrossingSink_n1x1_5 inst chipyard_prcictrl_domain of ChipyardPRCICtrlClockSinkDomain inst aggregator of ClockGroupAggregator_allClocks inst clockNamePrefixer of ClockGroupParameterModifier inst frequencySpecifier of ClockGroupParameterModifier_1 inst clockGroupCombiner of ClockGroupCombiner inst clockTapNode of ClockGroup_6 inst globalNoCDomain of ClockSinkDomain_1 inst reRoCCManagerIdNexusNode of BundleBridgeNexus_NoOutput_8 wire allClockGroupsNodeOut : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeOut.member.sbus_0.reset invalidate allClockGroupsNodeOut.member.sbus_0.clock invalidate allClockGroupsNodeOut.member.sbus_1.reset invalidate allClockGroupsNodeOut.member.sbus_1.clock wire x1_allClockGroupsNodeOut : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut.member.pbus_0.reset invalidate x1_allClockGroupsNodeOut.member.pbus_0.clock wire x1_allClockGroupsNodeOut_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.clock wire x1_allClockGroupsNodeOut_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.clock wire x1_allClockGroupsNodeOut_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.clock wire x1_allClockGroupsNodeOut_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.clock wire allClockGroupsNodeIn : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeIn.member.sbus_0.reset invalidate allClockGroupsNodeIn.member.sbus_0.clock invalidate allClockGroupsNodeIn.member.sbus_1.reset invalidate allClockGroupsNodeIn.member.sbus_1.clock wire x1_allClockGroupsNodeIn : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn.member.pbus_0.reset invalidate x1_allClockGroupsNodeIn.member.pbus_0.clock wire x1_allClockGroupsNodeIn_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.clock wire x1_allClockGroupsNodeIn_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.clock wire x1_allClockGroupsNodeIn_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.clock wire x1_allClockGroupsNodeIn_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.clock connect allClockGroupsNodeOut, allClockGroupsNodeIn connect x1_allClockGroupsNodeOut, x1_allClockGroupsNodeIn connect x1_allClockGroupsNodeOut_1, x1_allClockGroupsNodeIn_1 connect x1_allClockGroupsNodeOut_2, x1_allClockGroupsNodeIn_2 connect x1_allClockGroupsNodeOut_3, x1_allClockGroupsNodeIn_3 connect x1_allClockGroupsNodeOut_4, x1_allClockGroupsNodeIn_4 wire tileHaltSinkNodeIn : UInt<1>[1] invalidate tileHaltSinkNodeIn[0] wire tileWFISinkNodeIn : UInt<1>[1] invalidate tileWFISinkNodeIn[0] wire tileCeaseSinkNodeIn : UInt<1>[1] invalidate tileCeaseSinkNodeIn[0] wire domainIn : { clock : Clock, reset : Reset} invalidate domainIn.reset invalidate domainIn.clock wire debugNodesOut : { sync : UInt<1>[1]} invalidate debugNodesOut.sync[0] wire debugNodesIn : { sync : UInt<1>[1]} invalidate debugNodesIn.sync[0] connect debugNodesOut, debugNodesIn wire traceCoreNodesIn : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn.cause invalidate traceCoreNodesIn.tval invalidate traceCoreNodesIn.priv invalidate traceCoreNodesIn.group[0].ilastsize invalidate traceCoreNodesIn.group[0].itype invalidate traceCoreNodesIn.group[0].iaddr invalidate traceCoreNodesIn.group[0].iretire wire traceNodesIn : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceNodesIn.time invalidate traceNodesIn.insns[0].tval invalidate traceNodesIn.insns[0].cause invalidate traceNodesIn.insns[0].interrupt invalidate traceNodesIn.insns[0].exception invalidate traceNodesIn.insns[0].priv invalidate traceNodesIn.insns[0].insn invalidate traceNodesIn.insns[0].iaddr invalidate traceNodesIn.insns[0].valid wire memAXI4NodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}} invalidate memAXI4NodeIn.r.bits.last invalidate memAXI4NodeIn.r.bits.resp invalidate memAXI4NodeIn.r.bits.data invalidate memAXI4NodeIn.r.bits.id invalidate memAXI4NodeIn.r.valid invalidate memAXI4NodeIn.r.ready invalidate memAXI4NodeIn.ar.bits.qos invalidate memAXI4NodeIn.ar.bits.prot invalidate memAXI4NodeIn.ar.bits.cache invalidate memAXI4NodeIn.ar.bits.lock invalidate memAXI4NodeIn.ar.bits.burst invalidate memAXI4NodeIn.ar.bits.size invalidate memAXI4NodeIn.ar.bits.len invalidate memAXI4NodeIn.ar.bits.addr invalidate memAXI4NodeIn.ar.bits.id invalidate memAXI4NodeIn.ar.valid invalidate memAXI4NodeIn.ar.ready invalidate memAXI4NodeIn.b.bits.resp invalidate memAXI4NodeIn.b.bits.id invalidate memAXI4NodeIn.b.valid invalidate memAXI4NodeIn.b.ready invalidate memAXI4NodeIn.w.bits.last invalidate memAXI4NodeIn.w.bits.strb invalidate memAXI4NodeIn.w.bits.data invalidate memAXI4NodeIn.w.valid invalidate memAXI4NodeIn.w.ready invalidate memAXI4NodeIn.aw.bits.qos invalidate memAXI4NodeIn.aw.bits.prot invalidate memAXI4NodeIn.aw.bits.cache invalidate memAXI4NodeIn.aw.bits.lock invalidate memAXI4NodeIn.aw.bits.burst invalidate memAXI4NodeIn.aw.bits.size invalidate memAXI4NodeIn.aw.bits.len invalidate memAXI4NodeIn.aw.bits.addr invalidate memAXI4NodeIn.aw.bits.id invalidate memAXI4NodeIn.aw.valid invalidate memAXI4NodeIn.aw.ready wire bootROMResetVectorSourceNodeOut : UInt<32> invalidate bootROMResetVectorSourceNodeOut wire intXingOut : { sync : UInt<1>[1]} invalidate intXingOut.sync[0] wire intXingIn : { sync : UInt<1>[1]} invalidate intXingIn.sync[0] connect intXingOut, intXingIn wire ioNodeIn : { txd : UInt<1>, flip rxd : UInt<1>} invalidate ioNodeIn.rxd invalidate ioNodeIn.txd wire clockTapIn : { clock : Clock, reset : Reset} invalidate clockTapIn.reset invalidate clockTapIn.clock connect plic_domain.auto.plic_int_in[0], ibus.auto.int_bus_anon_out[0] connect sbus.auto.sbus_clock_groups_in, allClockGroupsNodeOut connect pbus.auto.pbus_clock_groups_in, x1_allClockGroupsNodeOut connect fbus.auto.fbus_clock_groups_in, x1_allClockGroupsNodeOut_1 connect mbus.auto.mbus_clock_groups_in, x1_allClockGroupsNodeOut_2 connect cbus.auto.cbus_clock_groups_in, x1_allClockGroupsNodeOut_3 connect clockTapNode.auto.in, x1_allClockGroupsNodeOut_4 connect coh_wrapper.auto.coh_clock_groups_in, sbus.auto.sbus_clock_groups_out connect ibus.auto.clock_in, sbus.auto.fixedClockNode_anon_out_0 connect tile_prci_domain.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_1 connect globalNoCDomain.auto.clock_in, sbus.auto.fixedClockNode_anon_out_2 connect uartClockDomainWrapper.auto.clock_in, pbus.auto.fixedClockNode_anon_out connect serial_tl_domain.auto.clock_in, fbus.auto.fixedClockNode_anon_out connect clint_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_0 connect plic_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_1 connect domainIn, cbus.auto.fixedClockNode_anon_out_2 connect bootrom_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_3 connect chipyard_prcictrl_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_4 connect bank.auto.clock_in, mbus.auto.fixedClockNode_anon_out_0 connect coh_wrapper.auto.l2_ctrls_ctrl_in, cbus.auto.coupler_to_l2_ctrl_buffer_out connect cbus.auto.bus_xing_in, sbus.auto.coupler_to_bus_named_cbus_bus_xing_out connect pbus.auto.bus_xing_in, cbus.auto.coupler_to_bus_named_pbus_bus_xing_out connect sbus.auto.coupler_from_bus_named_fbus_bus_xing_in, fbus.auto.bus_xing_out connect coh_wrapper.auto.coherent_jbar_anon_in, sbus.auto.coupler_to_bus_named_coh_widget_anon_out connect mbus.auto.bus_xing_in, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out connect nexus.auto.in, tile_prci_domain.auto.element_reset_domain_rockettile_trace_source_out connect nexus_1.auto.in, tile_prci_domain.auto.element_reset_domain_rockettile_trace_core_source_out connect tileHaltSinkNodeIn, xbar.auto.anon_out connect tileWFISinkNodeIn, xbar_1.auto.anon_out connect tileCeaseSinkNodeIn, xbar_2.auto.anon_out connect tile_prci_domain.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out connect tile_prci_domain.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out connect clint_domain.auto.clint_in, cbus.auto.coupler_to_clint_fragmenter_anon_out connect plic_domain.auto.plic_in, cbus.auto.coupler_to_plic_fragmenter_anon_out connect debugNodesIn, tlDM.auto.dmOuter_int_out connect fbus.auto.coupler_from_debug_sb_widget_anon_in, tlDM.auto.dmInner_dmInner_sb2tlOpt_out connect tlDM.auto.dmInner_dmInner_tl_in, cbus.auto.coupler_to_debug_fragmenter_anon_out connect tlDM.auto.dmInner_dmInner_custom_in, debugCustomXbarOpt.auto.out connect tile_prci_domain.auto.intsink_in.sync[0], debugNodesOut.sync[0] connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_0, tile_prci_domain.auto.tl_master_clock_xing_out_0 connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in_1, tile_prci_domain.auto.tl_master_clock_xing_out_1 connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out.sync[1] connect tile_prci_domain.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_0.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_1.sync[0] connect xbar.auto.anon_in[0], tile_prci_domain.auto.intsink_out_0[0] connect xbar_1.auto.anon_in[0], tile_prci_domain.auto.intsink_out_1[0] connect xbar_2.auto.anon_in[0], tile_prci_domain.auto.intsink_out_2[0] connect traceNodesIn, nexus.auto.out connect traceCoreNodesIn, nexus_1.auto.out connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.r, memAXI4NodeIn.r connect memAXI4NodeIn.ar.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.bits connect memAXI4NodeIn.ar.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.ready, memAXI4NodeIn.ar.ready connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.b, memAXI4NodeIn.b connect memAXI4NodeIn.w.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.bits connect memAXI4NodeIn.w.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.ready, memAXI4NodeIn.w.ready connect memAXI4NodeIn.aw.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.bits connect memAXI4NodeIn.aw.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.ready, memAXI4NodeIn.aw.ready connect broadcast.auto.in, bootROMResetVectorSourceNodeOut connect bootrom_domain.auto.bootrom_in, cbus.auto.coupler_to_bootrom_fragmenter_anon_out connect bank.auto.xbar_anon_in, mbus.auto.buffer_out connect fbus.auto.coupler_from_port_named_serial_tl_0_in_buffer_in, serial_tl_domain.auto.serdesser_client_out connect uartClockDomainWrapper.auto.uart_0_io_out.rxd, ioNodeIn.rxd connect ioNodeIn.txd, uartClockDomainWrapper.auto.uart_0_io_out.txd connect uartClockDomainWrapper.auto.uart_0_control_xing_in, pbus.auto.coupler_to_device_named_uart_0_control_xing_out connect ibus.auto.int_bus_anon_in[0], intsink.auto.out[0] connect intsink.auto.in.sync[0], intXingOut.sync[0] connect intXingIn, uartClockDomainWrapper.auto.uart_0_int_xing_out connect chipyard_prcictrl_domain.auto.xbar_anon_in, cbus.auto.coupler_to_prci_ctrl_fixer_anon_out connect clockNamePrefixer.auto.clock_name_prefixer_in_0, aggregator.auto.out_0 connect clockNamePrefixer.auto.clock_name_prefixer_in_1, aggregator.auto.out_1 connect clockNamePrefixer.auto.clock_name_prefixer_in_2, aggregator.auto.out_2 connect clockNamePrefixer.auto.clock_name_prefixer_in_3, aggregator.auto.out_3 connect clockNamePrefixer.auto.clock_name_prefixer_in_4, aggregator.auto.out_4 connect clockNamePrefixer.auto.clock_name_prefixer_in_5, aggregator.auto.out_5 connect allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_0 connect x1_allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_1 connect x1_allClockGroupsNodeIn_1, clockNamePrefixer.auto.clock_name_prefixer_out_2 connect x1_allClockGroupsNodeIn_2, clockNamePrefixer.auto.clock_name_prefixer_out_3 connect x1_allClockGroupsNodeIn_3, clockNamePrefixer.auto.clock_name_prefixer_out_4 connect x1_allClockGroupsNodeIn_4, clockNamePrefixer.auto.clock_name_prefixer_out_5 connect aggregator.auto.in, frequencySpecifier.auto.frequency_specifier_out connect frequencySpecifier.auto.frequency_specifier_in, clockGroupCombiner.auto.clock_group_combiner_out connect clockGroupCombiner.auto.clock_group_combiner_in, chipyard_prcictrl_domain.auto.resetSynchronizer_out connect clockTapIn, clockTapNode.auto.out connect auto.cbus_fixedClockNode_anon_out, cbus.auto.fixedClockNode_anon_out_5 connect auto.mbus_fixedClockNode_anon_out, mbus.auto.fixedClockNode_anon_out_1 connect chipyard_prcictrl_domain.auto.reset_setter_clock_in, auto.chipyard_prcictrl_domain_reset_setter_clock_in connect tlDM.io.tl_reset, domainIn.reset connect tlDM.io.tl_clock, domainIn.clock connect tlDM.io.hartIsInReset[0], resetctrl.hartIsInReset[0] connect tlDM.io.debug_reset, debug.reset connect tlDM.io.debug_clock, debug.clock connect debug.ndreset, tlDM.io.ctrl.ndreset connect debug.dmactive, tlDM.io.ctrl.dmactive connect tlDM.io.ctrl.dmactiveAck, debug.dmactiveAck connect tlDM.io.ctrl.debugUnavail[0], UInt<1>(0h0) inst dtm of DebugTransportModuleJTAG connect dtm.io.jtag, debug.systemjtag.jtag connect dtm.io.jtag_clock, debug.systemjtag.jtag.TCK connect dtm.io.jtag_reset, debug.systemjtag.reset connect dtm.io.jtag_mfr_id, debug.systemjtag.mfr_id connect dtm.io.jtag_part_number, debug.systemjtag.part_number connect dtm.io.jtag_version, debug.systemjtag.version connect dtm.rf_reset, debug.systemjtag.reset connect tlDM.io.dmi.dmi, dtm.io.dmi connect tlDM.io.dmi.dmiClock, debug.systemjtag.jtag.TCK connect tlDM.io.dmi.dmiReset, debug.systemjtag.reset connect mem_axi4.`0`, memAXI4NodeIn connect bootROMResetVectorSourceNodeOut, UInt<17>(0h10000) connect cbus.custom_boot, custom_boot connect serial_tl_domain.serial_tl_0.clock_in, serial_tl_0.clock_in connect serial_tl_0.out.bits, serial_tl_domain.serial_tl_0.out.bits connect serial_tl_0.out.valid, serial_tl_domain.serial_tl_0.out.valid connect serial_tl_domain.serial_tl_0.out.ready, serial_tl_0.out.ready connect serial_tl_domain.serial_tl_0.in, serial_tl_0.in connect serial_tl_0_debug, serial_tl_domain.serial_tl_0_debug connect uart_0, ioNodeIn connect clock_tap, clockTapIn.clock regreset int_rtc_tick_c_value : UInt<10>, clint_domain.clock, clint_domain.reset, UInt<10>(0h0) wire int_rtc_tick : UInt<1> connect int_rtc_tick, UInt<1>(0h0) when UInt<1>(0h1) : node int_rtc_tick_wrap_wrap = eq(int_rtc_tick_c_value, UInt<10>(0h3e7)) node _int_rtc_tick_wrap_value_T = add(int_rtc_tick_c_value, UInt<1>(0h1)) node _int_rtc_tick_wrap_value_T_1 = tail(_int_rtc_tick_wrap_value_T, 1) connect int_rtc_tick_c_value, _int_rtc_tick_wrap_value_T_1 when int_rtc_tick_wrap_wrap : connect int_rtc_tick_c_value, UInt<1>(0h0) connect int_rtc_tick, int_rtc_tick_wrap_wrap connect clint_domain.tick, int_rtc_tick extmodule GenericDigitalInIOCell : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell extmodule GenericDigitalOutIOCell : output pad : UInt<1> input o : UInt<1> input oe : UInt<1> defname = GenericDigitalOutIOCell extmodule GenericDigitalInIOCell_1 : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell	module DigitalTop( // @[DigitalTop.scala:47:7] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25] input debug_clock, // @[Periphery.scala:125:19] input debug_reset, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19] output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19] input debug_systemjtag_reset, // @[Periphery.scala:125:19] output debug_dmactive, // @[Periphery.scala:125:19] input debug_dmactiveAck, // @[Periphery.scala:125:19] input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21] input custom_boot, // @[CustomBootPin.scala:73:27] output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24] input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24] output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24] output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24] output uart_0_txd, // @[BundleBridgeSink.scala:25:19] input uart_0_rxd, // @[BundleBridgeSink.scala:25:19] output clock_tap // @[CanHaveClockTap.scala:23:23] ); wire clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire [63:0] nexus_auto_out_time; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_0_tval; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_out_insns_0_cause; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_interrupt; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_exception; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_out_insns_0_priv; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_out_insns_0_insn; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_0_iaddr; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_valid; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_in_time; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_0_tval; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_in_insns_0_cause; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_0_interrupt; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_0_exception; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_in_insns_0_priv; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_in_insns_0_insn; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_0_iaddr; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_0_valid; // @[BundleBridgeNexus.scala:20:9] wire ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21] wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21] wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21] wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21] wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [8:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44] wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44] wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44] wire [12:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44] wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44] wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38] wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38] wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38] wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_serial_tl_0_debug_ser_busy; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_serial_tl_0_debug_des_busy; // @[PeripheryTLSerial.scala:116:38] wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28] wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28] wire [4:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28] wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28] wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28] wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28] wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [12:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26] wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26] wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26] wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26] wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26] wire [12:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26] wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26] wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26] wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26] wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [12:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [12:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_clock; // @[BusWrapper.scala:89:28] wire _clint_domain_reset; // @[BusWrapper.scala:89:28] wire _tileHartIdNexusNode_auto_out; // @[HasTiles.scala:75:39] wire _tile_prci_domain_auto_intsink_out_1_0; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_1_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_1_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_1_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_1_e_valid; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_1_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_size; // @[HasTiles.scala:163:38] wire [6:0] _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_0_d_ready; // @[HasTiles.scala:163:38] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [4:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [127:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [12:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _mbus_auto_buffer_out_a_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_buffer_out_a_bits_source; // @[MemoryBus.scala:30:26] wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[MemoryBus.scala:30:26] wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_a_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_d_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_bus_xing_in_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [8:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [12:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [12:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [12:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [12:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [8:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [12:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26] wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26] wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [12:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_clock; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_reset; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [8:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address; // @[SystemBus.scala:31:26] wire [15:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala:31:26] wire [28:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_2_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_2_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_reset; // @[SystemBus.scala:31:26] wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock; // @[DigitalTop.scala:47:7] wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset; // @[DigitalTop.scala:47:7] wire resetctrl_hartIsInReset_0_0 = resetctrl_hartIsInReset_0; // @[DigitalTop.scala:47:7] wire debug_clock_0 = debug_clock; // @[DigitalTop.scala:47:7] wire debug_reset_0 = debug_reset; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TCK_0 = debug_systemjtag_jtag_TCK; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TMS_0 = debug_systemjtag_jtag_TMS; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDI_0 = debug_systemjtag_jtag_TDI; // @[DigitalTop.scala:47:7] wire debug_systemjtag_reset_0 = debug_systemjtag_reset; // @[DigitalTop.scala:47:7] wire debug_dmactiveAck_0 = debug_dmactiveAck; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_ready_0 = mem_axi4_0_aw_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_ready_0 = mem_axi4_0_w_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_b_valid_0 = mem_axi4_0_b_valid; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_b_bits_id_0 = mem_axi4_0_b_bits_id; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_b_bits_resp_0 = mem_axi4_0_b_bits_resp; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_ready_0 = mem_axi4_0_ar_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_valid_0 = mem_axi4_0_r_valid; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_r_bits_id_0 = mem_axi4_0_r_bits_id; // @[DigitalTop.scala:47:7] wire [63:0] mem_axi4_0_r_bits_data_0 = mem_axi4_0_r_bits_data; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_r_bits_resp_0 = mem_axi4_0_r_bits_resp; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_bits_last_0 = mem_axi4_0_r_bits_last; // @[DigitalTop.scala:47:7] wire serial_tl_0_in_valid_0 = serial_tl_0_in_valid; // @[DigitalTop.scala:47:7] wire [31:0] serial_tl_0_in_bits_phit_0 = serial_tl_0_in_bits_phit; // @[DigitalTop.scala:47:7] wire serial_tl_0_out_ready_0 = serial_tl_0_out_ready; // @[DigitalTop.scala:47:7] wire serial_tl_0_clock_in_0 = serial_tl_0_clock_in; // @[DigitalTop.scala:47:7] wire uart_0_rxd_0 = uart_0_rxd; // @[DigitalTop.scala:47:7] wire [10:0] debug_systemjtag_mfr_id = 11'h0; // @[DigitalTop.scala:47:7] wire [15:0] debug_systemjtag_part_number = 16'h0; // @[DigitalTop.scala:47:7] wire [3:0] debug_systemjtag_version = 4'h0; // @[DigitalTop.scala:47:7] wire [3:0] nexus_1_auto_in_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_in_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_out_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_out_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_nodeIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] nexus_1_nodeIn_priv = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] nexus_1_nodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] nexus_1_nodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreNodesIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] traceCoreNodesIn_priv = 4'h0; // @[MixedNode.scala:551:17] wire [31:0] broadcast_auto_in = 32'h10000; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_auto_out = 32'h10000; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_nodeIn = 32'h10000; // @[MixedNode.scala:551:17] wire [31:0] broadcast_nodeOut = 32'h10000; // @[MixedNode.scala:542:17] wire [31:0] bootROMResetVectorSourceNodeOut = 32'h10000; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_auto_in_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_in_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_in_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_nodeIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeIn_tval = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeIn_cause = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_nodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_nodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreNodesIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceCoreNodesIn_tval = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceCoreNodesIn_cause = 32'h0; // @[MixedNode.scala:551:17] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire ibus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_auto_in_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_in_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_out_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_out_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_nodeIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17] wire nexus_1_nodeIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17] wire nexus_1_nodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire clockNamePrefixer_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockNamePrefixer_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockNamePrefixer__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire frequencySpecifier_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire frequencySpecifier_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire frequencySpecifier__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockTapNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockTapNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockTapNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire tileHaltSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire tileCeaseSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreNodesIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreNodesIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_ready = mem_axi4_0_aw_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17] wire [31:0] memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_ready = mem_axi4_0_w_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17] wire [63:0] memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_b_valid = mem_axi4_0_b_valid_0; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_b_bits_id = mem_axi4_0_b_bits_id_0; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_b_bits_resp = mem_axi4_0_b_bits_resp_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_ready = mem_axi4_0_ar_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17] wire [31:0] memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_valid = mem_axi4_0_r_valid_0; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_r_bits_id = mem_axi4_0_r_bits_id_0; // @[MixedNode.scala:551:17] wire [63:0] memAXI4NodeIn_r_bits_data = mem_axi4_0_r_bits_data_0; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_r_bits_resp = mem_axi4_0_r_bits_resp_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_bits_last = mem_axi4_0_r_bits_last_0; // @[MixedNode.scala:551:17] wire ioNodeIn_txd; // @[MixedNode.scala:551:17] wire ioNodeIn_rxd = uart_0_rxd_0; // @[MixedNode.scala:551:17] wire auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] wire auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] wire auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] wire auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDO_driven; // @[DigitalTop.scala:47:7] wire debug_ndreset; // @[DigitalTop.scala:47:7] wire debug_dmactive_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7] wire [31:0] mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7] wire [63:0] mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7] wire [31:0] mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7] wire serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7] wire [31:0] serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7] wire serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7] wire uart_0_txd_0; // @[DigitalTop.scala:47:7] wire clockTapIn_clock; // @[MixedNode.scala:551:17] wire ibus_clockNodeIn_clock = ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_in_0; // @[ClockDomain.scala:14:9] wire ibus_clockNodeIn_reset = ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_out_0; // @[ClockDomain.scala:14:9] wire ibus_childClock; // @[LazyModuleImp.scala:155:31] wire ibus_childReset; // @[LazyModuleImp.scala:158:31] assign ibus_childClock = ibus_clockNodeIn_clock; // @[MixedNode.scala:551:17] assign ibus_childReset = ibus_clockNodeIn_reset; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_0_valid = nexus_auto_in_insns_0_valid; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_0_iaddr = nexus_auto_in_insns_0_iaddr; // @[MixedNode.scala:551:17] wire [31:0] nexus_nodeIn_insns_0_insn = nexus_auto_in_insns_0_insn; // @[MixedNode.scala:551:17] wire [2:0] nexus_nodeIn_insns_0_priv = nexus_auto_in_insns_0_priv; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_0_exception = nexus_auto_in_insns_0_exception; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_0_interrupt = nexus_auto_in_insns_0_interrupt; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeIn_insns_0_cause = nexus_auto_in_insns_0_cause; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_0_tval = nexus_auto_in_insns_0_tval; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeIn_time = nexus_auto_in_time; // @[MixedNode.scala:551:17] wire nexus_nodeOut_insns_0_valid; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17] wire traceNodesIn_insns_0_valid = nexus_auto_out_insns_0_valid; // @[MixedNode.scala:551:17] wire [31:0] nexus_nodeOut_insns_0_insn; // @[MixedNode.scala:542:17] wire [39:0] traceNodesIn_insns_0_iaddr = nexus_auto_out_insns_0_iaddr; // @[MixedNode.scala:551:17] wire [2:0] nexus_nodeOut_insns_0_priv; // @[MixedNode.scala:542:17] wire [31:0] traceNodesIn_insns_0_insn = nexus_auto_out_insns_0_insn; // @[MixedNode.scala:551:17] wire nexus_nodeOut_insns_0_exception; // @[MixedNode.scala:542:17] wire [2:0] traceNodesIn_insns_0_priv = nexus_auto_out_insns_0_priv; // @[MixedNode.scala:551:17] wire nexus_nodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17] wire traceNodesIn_insns_0_exception = nexus_auto_out_insns_0_exception; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeOut_insns_0_cause; // @[MixedNode.scala:542:17] wire traceNodesIn_insns_0_interrupt = nexus_auto_out_insns_0_interrupt; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeOut_insns_0_tval; // @[MixedNode.scala:542:17] wire [63:0] traceNodesIn_insns_0_cause = nexus_auto_out_insns_0_cause; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeOut_time; // @[MixedNode.scala:542:17] wire [39:0] traceNodesIn_insns_0_tval = nexus_auto_out_insns_0_tval; // @[MixedNode.scala:551:17] wire [63:0] traceNodesIn_time = nexus_auto_out_time; // @[MixedNode.scala:551:17] assign nexus_nodeOut_insns_0_valid = nexus_nodeIn_insns_0_valid; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_iaddr = nexus_nodeIn_insns_0_iaddr; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_insn = nexus_nodeIn_insns_0_insn; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_priv = nexus_nodeIn_insns_0_priv; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_exception = nexus_nodeIn_insns_0_exception; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_interrupt = nexus_nodeIn_insns_0_interrupt; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_cause = nexus_nodeIn_insns_0_cause; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_insns_0_tval = nexus_nodeIn_insns_0_tval; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_time = nexus_nodeIn_time; // @[MixedNode.scala:542:17, :551:17] assign nexus_auto_out_insns_0_valid = nexus_nodeOut_insns_0_valid; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_iaddr = nexus_nodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_insn = nexus_nodeOut_insns_0_insn; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_priv = nexus_nodeOut_insns_0_priv; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_exception = nexus_nodeOut_insns_0_exception; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_interrupt = nexus_nodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_cause = nexus_nodeOut_insns_0_cause; // @[MixedNode.scala:542:17] assign nexus_auto_out_insns_0_tval = nexus_nodeOut_insns_0_tval; // @[MixedNode.scala:542:17] assign nexus_auto_out_time = nexus_nodeOut_time; // @[MixedNode.scala:542:17] wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_3_member_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_3_member_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_2_member_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_2_member_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_1_member_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_1_member_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_member_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_member_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[MixedNode.scala:551:17] wire allClockGroupsNodeIn_member_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[MixedNode.scala:551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock = clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire clockTapNode_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset = clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_nodeOut_reset; // @[MixedNode.scala:542:17] assign clockTapIn_clock = clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockTapIn_reset = clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_out_clock = clockTapNode_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_out_reset = clockTapNode_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockTapNode_nodeOut_clock = clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign clockTapNode_nodeOut_reset = clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] wire allClockGroupsNodeOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] assign clockTapNode_auto_in_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_in_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] assign allClockGroupsNodeOut_member_sbus_1_clock = allClockGroupsNodeIn_member_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_1_reset = allClockGroupsNodeIn_member_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_0_clock = allClockGroupsNodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_0_reset = allClockGroupsNodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_member_pbus_0_clock = x1_allClockGroupsNodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_member_pbus_0_reset = x1_allClockGroupsNodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_1_member_fbus_0_clock = x1_allClockGroupsNodeIn_1_member_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_1_member_fbus_0_reset = x1_allClockGroupsNodeIn_1_member_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_2_member_mbus_0_clock = x1_allClockGroupsNodeIn_2_member_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_2_member_mbus_0_reset = x1_allClockGroupsNodeIn_2_member_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_3_member_cbus_0_clock = x1_allClockGroupsNodeIn_3_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_3_member_cbus_0_reset = x1_allClockGroupsNodeIn_3_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] wire tileWFISinkNodeIn_0; // @[MixedNode.scala:551:17] wire domainIn_clock; // @[MixedNode.scala:551:17] wire domainIn_reset; // @[MixedNode.scala:551:17] wire debugNodesIn_sync_0; // @[MixedNode.scala:551:17] wire debugNodesOut_sync_0; // @[MixedNode.scala:542:17] assign debugNodesOut_sync_0 = debugNodesIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign mem_axi4_0_aw_valid_0 = memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_id_0 = memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_addr_0 = memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_len_0 = memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_size_0 = memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_burst_0 = memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_lock_0 = memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_cache_0 = memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_prot_0 = memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_qos_0 = memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_valid_0 = memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_data_0 = memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_strb_0 = memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_last_0 = memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17] assign mem_axi4_0_b_ready_0 = memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_valid_0 = memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_id_0 = memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_addr_0 = memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_len_0 = memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_size_0 = memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_burst_0 = memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_lock_0 = memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_cache_0 = memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_prot_0 = memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_qos_0 = memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17] assign mem_axi4_0_r_ready_0 = memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17] wire intXingIn_sync_0; // @[MixedNode.scala:551:17] wire intXingOut_sync_0; // @[MixedNode.scala:542:17] assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign uart_0_txd_0 = ioNodeIn_txd; // @[MixedNode.scala:551:17] reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40] wire int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24] wire int_rtc_tick; // @[Counter.scala:117:24] assign int_rtc_tick_wrap_wrap = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24] assign int_rtc_tick = int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24, :117:24] wire [10:0] _int_rtc_tick_wrap_value_T = {1'h0, int_rtc_tick_c_value} + 11'h1; // @[Counter.scala:61:40, :77:24] wire [9:0] _int_rtc_tick_wrap_value_T_1 = _int_rtc_tick_wrap_value_T[9:0]; // @[Counter.scala:77:24] always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28] if (_clint_domain_reset) // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40] else // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= int_rtc_tick_wrap_wrap ? 10'h0 : _int_rtc_tick_wrap_value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] always @(posedge) IntXbar_i1_o1 ibus_int_bus ( // @[InterruptBus.scala:19:27] .auto_anon_in_0 (ibus_auto_int_bus_anon_in_0), // @[ClockDomain.scala:14:9] .auto_anon_out_0 (ibus_auto_int_bus_anon_out_0) ); // @[InterruptBus.scala:19:27] SystemBus sbus ( // @[SystemBus.scala:31:26] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_1_b_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_1_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt), .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_1_e_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_1_e_bits_sink), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_0_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data), .auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt), .auto_coupler_to_bus_named_coh_widget_anon_out_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), .auto_coupler_to_bus_named_coh_widget_anon_out_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), .auto_coupler_to_bus_named_coh_widget_anon_out_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), .auto_coupler_to_bus_named_coh_widget_anon_out_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), .auto_coupler_to_bus_named_coh_widget_anon_out_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), .auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), .auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid (_fbus_auto_bus_xing_out_a_valid), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready (_fbus_auto_bus_xing_out_d_ready), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready (_cbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid (_cbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_fixedClockNode_anon_out_2_clock (_sbus_auto_fixedClockNode_anon_out_2_clock), .auto_fixedClockNode_anon_out_2_reset (_sbus_auto_fixedClockNode_anon_out_2_reset), .auto_fixedClockNode_anon_out_1_clock (_sbus_auto_fixedClockNode_anon_out_1_clock), .auto_fixedClockNode_anon_out_1_reset (_sbus_auto_fixedClockNode_anon_out_1_reset), .auto_fixedClockNode_anon_out_0_clock (ibus_auto_clock_in_clock), .auto_fixedClockNode_anon_out_0_reset (ibus_auto_clock_in_reset), .auto_sbus_clock_groups_in_member_sbus_1_clock (allClockGroupsNodeOut_member_sbus_1_clock), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_1_reset (allClockGroupsNodeOut_member_sbus_1_reset), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_0_clock (allClockGroupsNodeOut_member_sbus_0_clock), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_0_reset (allClockGroupsNodeOut_member_sbus_0_reset), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_out_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock), .auto_sbus_clock_groups_out_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset) ); // @[SystemBus.scala:31:26] PeripheryBus_pbus pbus ( // @[PeripheryBus.scala:37:26] .auto_coupler_to_device_named_uart_0_control_xing_out_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt), .auto_coupler_to_device_named_uart_0_control_xing_out_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready), .auto_coupler_to_device_named_uart_0_control_xing_out_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data), // @[UART.scala:270:44] .auto_fixedClockNode_anon_out_clock (_pbus_auto_fixedClockNode_anon_out_clock), .auto_fixedClockNode_anon_out_reset (_pbus_auto_fixedClockNode_anon_out_reset), .auto_pbus_clock_groups_in_member_pbus_0_clock (x1_allClockGroupsNodeOut_member_pbus_0_clock), // @[MixedNode.scala:542:17] .auto_pbus_clock_groups_in_member_pbus_0_reset (x1_allClockGroupsNodeOut_member_pbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_pbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_d_valid (_pbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt) ); // @[PeripheryBus.scala:37:26] FrontBus fbus ( // @[FrontBus.scala:23:26] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), .auto_coupler_from_debug_sb_widget_anon_in_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready), .auto_coupler_from_debug_sb_widget_anon_in_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), .auto_fixedClockNode_anon_out_clock (_fbus_auto_fixedClockNode_anon_out_clock), .auto_fixedClockNode_anon_out_reset (_fbus_auto_fixedClockNode_anon_out_reset), .auto_fbus_clock_groups_in_member_fbus_0_clock (x1_allClockGroupsNodeOut_1_member_fbus_0_clock), // @[MixedNode.scala:542:17] .auto_fbus_clock_groups_in_member_fbus_0_reset (x1_allClockGroupsNodeOut_1_member_fbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_out_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), // @[SystemBus.scala:31:26] .auto_bus_xing_out_a_valid (_fbus_auto_bus_xing_out_a_valid), .auto_bus_xing_out_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode), .auto_bus_xing_out_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param), .auto_bus_xing_out_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size), .auto_bus_xing_out_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source), .auto_bus_xing_out_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address), .auto_bus_xing_out_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask), .auto_bus_xing_out_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data), .auto_bus_xing_out_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt), .auto_bus_xing_out_d_ready (_fbus_auto_bus_xing_out_d_ready), .auto_bus_xing_out_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt) // @[SystemBus.scala:31:26] ); // @[FrontBus.scala:23:26] PeripheryBus_cbus cbus ( // @[PeripheryBus.scala:37:26] .auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt), .auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready), .auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_a_ready (_bootrom_domain_auto_bootrom_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_bootrom_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready), .auto_coupler_to_bootrom_fragmenter_anon_out_d_valid (_bootrom_domain_auto_bootrom_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_debug_fragmenter_anon_out_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_debug_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready), .auto_coupler_to_debug_fragmenter_anon_out_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data), // @[Periphery.scala:88:26] .auto_coupler_to_plic_fragmenter_anon_out_a_ready (_plic_domain_auto_plic_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_plic_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready), .auto_coupler_to_plic_fragmenter_anon_out_d_valid (_plic_domain_auto_plic_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_size (_plic_domain_auto_plic_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_source (_plic_domain_auto_plic_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_data (_plic_domain_auto_plic_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_a_ready (_clint_domain_auto_clint_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_clint_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready), .auto_coupler_to_clint_fragmenter_anon_out_d_valid (_clint_domain_auto_clint_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_size (_clint_domain_auto_clint_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_source (_clint_domain_auto_clint_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_data (_clint_domain_auto_clint_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready (_pbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid (_pbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_coupler_to_l2_ctrl_buffer_out_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt), .auto_coupler_to_l2_ctrl_buffer_out_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready), .auto_coupler_to_l2_ctrl_buffer_out_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_fixedClockNode_anon_out_5_clock (auto_cbus_fixedClockNode_anon_out_clock_0), .auto_fixedClockNode_anon_out_5_reset (auto_cbus_fixedClockNode_anon_out_reset_0), .auto_fixedClockNode_anon_out_4_clock (_cbus_auto_fixedClockNode_anon_out_4_clock), .auto_fixedClockNode_anon_out_4_reset (_cbus_auto_fixedClockNode_anon_out_4_reset), .auto_fixedClockNode_anon_out_3_clock (_cbus_auto_fixedClockNode_anon_out_3_clock), .auto_fixedClockNode_anon_out_3_reset (_cbus_auto_fixedClockNode_anon_out_3_reset), .auto_fixedClockNode_anon_out_2_clock (domainIn_clock), .auto_fixedClockNode_anon_out_2_reset (domainIn_reset), .auto_fixedClockNode_anon_out_1_clock (_cbus_auto_fixedClockNode_anon_out_1_clock), .auto_fixedClockNode_anon_out_1_reset (_cbus_auto_fixedClockNode_anon_out_1_reset), .auto_fixedClockNode_anon_out_0_clock (_cbus_auto_fixedClockNode_anon_out_0_clock), .auto_fixedClockNode_anon_out_0_reset (_cbus_auto_fixedClockNode_anon_out_0_reset), .auto_cbus_clock_groups_in_member_cbus_0_clock (x1_allClockGroupsNodeOut_3_member_cbus_0_clock), // @[MixedNode.scala:542:17] .auto_cbus_clock_groups_in_member_cbus_0_reset (x1_allClockGroupsNodeOut_3_member_cbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_cbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), // @[SystemBus.scala:31:26] .auto_bus_xing_in_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), // @[SystemBus.scala:31:26] .auto_bus_xing_in_d_valid (_cbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt), .custom_boot (custom_boot) ); // @[PeripheryBus.scala:37:26] MemoryBus mbus ( // @[MemoryBus.scala:30:26] .auto_buffer_out_a_ready (_bank_auto_xbar_anon_in_a_ready), // @[Scratchpad.scala:65:28] .auto_buffer_out_a_valid (_mbus_auto_buffer_out_a_valid), .auto_buffer_out_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode), .auto_buffer_out_a_bits_param (_mbus_auto_buffer_out_a_bits_param), .auto_buffer_out_a_bits_size (_mbus_auto_buffer_out_a_bits_size), .auto_buffer_out_a_bits_source (_mbus_auto_buffer_out_a_bits_source), .auto_buffer_out_a_bits_address (_mbus_auto_buffer_out_a_bits_address), .auto_buffer_out_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask), .auto_buffer_out_a_bits_data (_mbus_auto_buffer_out_a_bits_data), .auto_buffer_out_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt), .auto_buffer_out_d_ready (_mbus_auto_buffer_out_d_ready), .auto_buffer_out_d_valid (_bank_auto_xbar_anon_in_d_valid), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt), // @[Scratchpad.scala:65:28] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready (memAXI4NodeIn_aw_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid (memAXI4NodeIn_aw_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id (memAXI4NodeIn_aw_bits_id), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr (memAXI4NodeIn_aw_bits_addr), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len (memAXI4NodeIn_aw_bits_len), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size (memAXI4NodeIn_aw_bits_size), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst (memAXI4NodeIn_aw_bits_burst), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock (memAXI4NodeIn_aw_bits_lock), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache (memAXI4NodeIn_aw_bits_cache), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot (memAXI4NodeIn_aw_bits_prot), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos (memAXI4NodeIn_aw_bits_qos), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready (memAXI4NodeIn_w_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid (memAXI4NodeIn_w_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data (memAXI4NodeIn_w_bits_data), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb (memAXI4NodeIn_w_bits_strb), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last (memAXI4NodeIn_w_bits_last), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready (memAXI4NodeIn_b_ready), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid (memAXI4NodeIn_b_valid), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id (memAXI4NodeIn_b_bits_id), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp (memAXI4NodeIn_b_bits_resp), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready (memAXI4NodeIn_ar_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid (memAXI4NodeIn_ar_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id (memAXI4NodeIn_ar_bits_id), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr (memAXI4NodeIn_ar_bits_addr), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len (memAXI4NodeIn_ar_bits_len), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size (memAXI4NodeIn_ar_bits_size), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst (memAXI4NodeIn_ar_bits_burst), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock (memAXI4NodeIn_ar_bits_lock), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache (memAXI4NodeIn_ar_bits_cache), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot (memAXI4NodeIn_ar_bits_prot), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos (memAXI4NodeIn_ar_bits_qos), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready (memAXI4NodeIn_r_ready), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid (memAXI4NodeIn_r_valid), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id (memAXI4NodeIn_r_bits_id), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data (memAXI4NodeIn_r_bits_data), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp (memAXI4NodeIn_r_bits_resp), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last (memAXI4NodeIn_r_bits_last), // @[MixedNode.scala:551:17] .auto_fixedClockNode_anon_out_1_clock (auto_mbus_fixedClockNode_anon_out_clock_0), .auto_fixedClockNode_anon_out_1_reset (auto_mbus_fixedClockNode_anon_out_reset_0), .auto_fixedClockNode_anon_out_0_clock (_mbus_auto_fixedClockNode_anon_out_0_clock), .auto_fixedClockNode_anon_out_0_reset (_mbus_auto_fixedClockNode_anon_out_0_reset), .auto_mbus_clock_groups_in_member_mbus_0_clock (x1_allClockGroupsNodeOut_2_member_mbus_0_clock), // @[MixedNode.scala:542:17] .auto_mbus_clock_groups_in_member_mbus_0_reset (x1_allClockGroupsNodeOut_2_member_mbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_mbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_d_valid (_mbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt) ); // @[MemoryBus.scala:30:26] CoherenceManagerWrapper coh_wrapper ( // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready (_mbus_auto_bus_xing_in_a_ready), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid (_mbus_auto_bus_xing_in_d_valid), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt), // @[MemoryBus.scala:30:26] .auto_coherent_jbar_anon_in_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready), .auto_coherent_jbar_anon_in_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid), .auto_coherent_jbar_anon_in_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param), .auto_coherent_jbar_anon_in_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address), .auto_coherent_jbar_anon_in_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready), .auto_coherent_jbar_anon_in_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid), .auto_coherent_jbar_anon_in_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode), .auto_coherent_jbar_anon_in_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param), .auto_coherent_jbar_anon_in_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size), .auto_coherent_jbar_anon_in_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source), .auto_coherent_jbar_anon_in_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink), .auto_coherent_jbar_anon_in_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied), .auto_coherent_jbar_anon_in_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data), .auto_coherent_jbar_anon_in_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt), .auto_coherent_jbar_anon_in_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), // @[SystemBus.scala:31:26] .auto_l2_ctrls_ctrl_in_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready), .auto_l2_ctrls_ctrl_in_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid), .auto_l2_ctrls_ctrl_in_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode), .auto_l2_ctrls_ctrl_in_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size), .auto_l2_ctrls_ctrl_in_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source), .auto_l2_ctrls_ctrl_in_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data), .auto_coh_clock_groups_in_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock), // @[SystemBus.scala:31:26] .auto_coh_clock_groups_in_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset) // @[SystemBus.scala:31:26] ); // @[BankedCoherenceParams.scala:56:31] TilePRCIDomain tile_prci_domain ( // @[HasTiles.scala:163:38] .auto_intsink_out_1_0 (_tile_prci_domain_auto_intsink_out_1_0), .auto_intsink_in_sync_0 (debugNodesOut_sync_0), // @[MixedNode.scala:542:17] .auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid (nexus_auto_in_insns_0_valid), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr (nexus_auto_in_insns_0_iaddr), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn (nexus_auto_in_insns_0_insn), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv (nexus_auto_in_insns_0_priv), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception (nexus_auto_in_insns_0_exception), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt (nexus_auto_in_insns_0_interrupt), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause (nexus_auto_in_insns_0_cause), .auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval (nexus_auto_in_insns_0_tval), .auto_element_reset_domain_rockettile_trace_source_out_time (nexus_auto_in_time), .auto_element_reset_domain_rockettile_hartid_in (_tileHartIdNexusNode_auto_out), // @[HasTiles.scala:75:39] .auto_int_in_clock_xing_in_2_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_0_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_0_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1), // @[BusWrapper.scala:89:28] .auto_tl_master_clock_xing_out_1_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_valid), .auto_tl_master_clock_xing_out_1_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_opcode), .auto_tl_master_clock_xing_out_1_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_param), .auto_tl_master_clock_xing_out_1_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_size), .auto_tl_master_clock_xing_out_1_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_source), .auto_tl_master_clock_xing_out_1_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_address), .auto_tl_master_clock_xing_out_1_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_mask), .auto_tl_master_clock_xing_out_1_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_data), .auto_tl_master_clock_xing_out_1_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_1_a_bits_corrupt), .auto_tl_master_clock_xing_out_1_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_1_b_ready), .auto_tl_master_clock_xing_out_1_b_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_b_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_b_bits_address (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_c_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_valid), .auto_tl_master_clock_xing_out_1_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_opcode), .auto_tl_master_clock_xing_out_1_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_param), .auto_tl_master_clock_xing_out_1_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_size), .auto_tl_master_clock_xing_out_1_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_source), .auto_tl_master_clock_xing_out_1_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_address), .auto_tl_master_clock_xing_out_1_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_data), .auto_tl_master_clock_xing_out_1_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_1_c_bits_corrupt), .auto_tl_master_clock_xing_out_1_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_1_d_ready), .auto_tl_master_clock_xing_out_1_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_1_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_1_e_valid), .auto_tl_master_clock_xing_out_1_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_1_e_bits_sink), .auto_tl_master_clock_xing_out_0_a_ready (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_valid), .auto_tl_master_clock_xing_out_0_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_opcode), .auto_tl_master_clock_xing_out_0_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_param), .auto_tl_master_clock_xing_out_0_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_size), .auto_tl_master_clock_xing_out_0_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_source), .auto_tl_master_clock_xing_out_0_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_address), .auto_tl_master_clock_xing_out_0_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_mask), .auto_tl_master_clock_xing_out_0_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_data), .auto_tl_master_clock_xing_out_0_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_0_a_bits_corrupt), .auto_tl_master_clock_xing_out_0_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_0_d_ready), .auto_tl_master_clock_xing_out_0_d_valid (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_opcode (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_param (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_size (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_source (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_sink (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_denied (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_data (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_0_d_bits_corrupt (_sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tap_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_1_clock), // @[SystemBus.scala:31:26] .auto_tap_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_1_reset) // @[SystemBus.scala:31:26] ); // @[HasTiles.scala:163:38] IntXbar_i1_o1_1 xbar (); // @[Xbar.scala:52:26] IntXbar_i1_o1_2 xbar_1 ( // @[Xbar.scala:52:26] .auto_anon_in_0 (_tile_prci_domain_auto_intsink_out_1_0), // @[HasTiles.scala:163:38] .auto_anon_out_0 (tileWFISinkNodeIn_0) ); // @[Xbar.scala:52:26] IntXbar_i1_o1_3 xbar_2 (); // @[Xbar.scala:52:26] BundleBridgeNexus_UInt1_1 tileHartIdNexusNode ( // @[HasTiles.scala:75:39] .auto_out (_tileHartIdNexusNode_auto_out) ); // @[HasTiles.scala:75:39] CLINTClockSinkDomain clint_domain ( // @[BusWrapper.scala:89:28] .auto_clint_in_a_ready (_clint_domain_auto_clint_in_a_ready), .auto_clint_in_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_clint_in_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_clint_in_d_valid (_clint_domain_auto_clint_in_d_valid), .auto_clint_in_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode), .auto_clint_in_d_bits_size (_clint_domain_auto_clint_in_d_bits_size), .auto_clint_in_d_bits_source (_clint_domain_auto_clint_in_d_bits_source), .auto_clint_in_d_bits_data (_clint_domain_auto_clint_in_d_bits_data), .auto_int_in_clock_xing_out_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0), .auto_int_in_clock_xing_out_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_0_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_0_reset), // @[PeripheryBus.scala:37:26] .tick (int_rtc_tick), // @[Counter.scala:117:24] .clock (_clint_domain_clock), .reset (_clint_domain_reset) ); // @[BusWrapper.scala:89:28] PLICClockSinkDomain plic_domain ( // @[BusWrapper.scala:89:28] .auto_plic_int_in_0 (ibus_auto_int_bus_anon_out_0), // @[ClockDomain.scala:14:9] .auto_plic_in_a_ready (_plic_domain_auto_plic_in_a_ready), .auto_plic_in_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_plic_in_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_plic_in_d_valid (_plic_domain_auto_plic_in_d_valid), .auto_plic_in_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode), .auto_plic_in_d_bits_size (_plic_domain_auto_plic_in_d_bits_size), .auto_plic_in_d_bits_source (_plic_domain_auto_plic_in_d_bits_source), .auto_plic_in_d_bits_data (_plic_domain_auto_plic_in_d_bits_data), .auto_int_in_clock_xing_out_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0), .auto_int_in_clock_xing_out_0_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_1_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_1_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] TLDebugModule tlDM ( // @[Periphery.scala:88:26] .auto_dmInner_dmInner_sb2tlOpt_out_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data), .auto_dmInner_dmInner_sb2tlOpt_out_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready), .auto_dmInner_dmInner_sb2tlOpt_out_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_tl_in_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready), .auto_dmInner_dmInner_tl_in_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid), .auto_dmInner_dmInner_tl_in_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode), .auto_dmInner_dmInner_tl_in_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size), .auto_dmInner_dmInner_tl_in_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source), .auto_dmInner_dmInner_tl_in_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data), .auto_dmOuter_int_out_sync_0 (debugNodesIn_sync_0), .io_debug_clock (debug_clock_0), // @[DigitalTop.scala:47:7] .io_debug_reset (debug_reset_0), // @[DigitalTop.scala:47:7] .io_tl_clock (domainIn_clock), // @[MixedNode.scala:551:17] .io_tl_reset (domainIn_reset), // @[MixedNode.scala:551:17] .io_ctrl_ndreset (debug_ndreset), .io_ctrl_dmactive (debug_dmactive_0), .io_ctrl_dmactiveAck (debug_dmactiveAck_0), // @[DigitalTop.scala:47:7] .io_dmi_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready), .io_dmi_dmi_req_valid (_dtm_io_dmi_req_valid), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_data (_dtm_io_dmi_req_bits_data), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_op (_dtm_io_dmi_req_bits_op), // @[Periphery.scala:166:21] .io_dmi_dmi_resp_ready (_dtm_io_dmi_resp_ready), // @[Periphery.scala:166:21] .io_dmi_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid), .io_dmi_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data), .io_dmi_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp), .io_dmi_dmiClock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_dmi_dmiReset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7] .io_hartIsInReset_0 (resetctrl_hartIsInReset_0_0) // @[DigitalTop.scala:47:7] ); // @[Periphery.scala:88:26] DebugCustomXbar debugCustomXbarOpt (); // @[Periphery.scala:80:75] BootROMClockSinkDomain bootrom_domain ( // @[BusWrapper.scala:89:28] .auto_bootrom_in_a_ready (_bootrom_domain_auto_bootrom_in_a_ready), .auto_bootrom_in_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_d_valid (_bootrom_domain_auto_bootrom_in_d_valid), .auto_bootrom_in_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size), .auto_bootrom_in_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source), .auto_bootrom_in_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_3_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_3_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] ScratchpadBank_4 bank ( // @[Scratchpad.scala:65:28] .auto_xbar_anon_in_a_ready (_bank_auto_xbar_anon_in_a_ready), .auto_xbar_anon_in_a_valid (_mbus_auto_buffer_out_a_valid), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_param (_mbus_auto_buffer_out_a_bits_param), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_size (_mbus_auto_buffer_out_a_bits_size), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_source (_mbus_auto_buffer_out_a_bits_source), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_address (_mbus_auto_buffer_out_a_bits_address), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_data (_mbus_auto_buffer_out_a_bits_data), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_d_ready (_mbus_auto_buffer_out_d_ready), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_d_valid (_bank_auto_xbar_anon_in_d_valid), .auto_xbar_anon_in_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode), .auto_xbar_anon_in_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param), .auto_xbar_anon_in_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size), .auto_xbar_anon_in_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source), .auto_xbar_anon_in_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink), .auto_xbar_anon_in_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied), .auto_xbar_anon_in_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data), .auto_xbar_anon_in_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt), .auto_clock_in_clock (_mbus_auto_fixedClockNode_anon_out_0_clock), // @[MemoryBus.scala:30:26] .auto_clock_in_reset (_mbus_auto_fixedClockNode_anon_out_0_reset) // @[MemoryBus.scala:30:26] ); // @[Scratchpad.scala:65:28] SerialTL0ClockSinkDomain serial_tl_domain ( // @[PeripheryTLSerial.scala:116:38] .auto_serdesser_client_out_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid), .auto_serdesser_client_out_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode), .auto_serdesser_client_out_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param), .auto_serdesser_client_out_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size), .auto_serdesser_client_out_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source), .auto_serdesser_client_out_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address), .auto_serdesser_client_out_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask), .auto_serdesser_client_out_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data), .auto_serdesser_client_out_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt), .auto_serdesser_client_out_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready), .auto_serdesser_client_out_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), // @[FrontBus.scala:23:26] .auto_clock_in_clock (_fbus_auto_fixedClockNode_anon_out_clock), // @[FrontBus.scala:23:26] .auto_clock_in_reset (_fbus_auto_fixedClockNode_anon_out_reset), // @[FrontBus.scala:23:26] .serial_tl_0_in_ready (serial_tl_0_in_ready_0), .serial_tl_0_in_valid (serial_tl_0_in_valid_0), // @[DigitalTop.scala:47:7] .serial_tl_0_in_bits_phit (serial_tl_0_in_bits_phit_0), // @[DigitalTop.scala:47:7] .serial_tl_0_out_ready (serial_tl_0_out_ready_0), // @[DigitalTop.scala:47:7] .serial_tl_0_out_valid (serial_tl_0_out_valid_0), .serial_tl_0_out_bits_phit (serial_tl_0_out_bits_phit_0), .serial_tl_0_clock_in (serial_tl_0_clock_in_0), // @[DigitalTop.scala:47:7] .serial_tl_0_debug_ser_busy (_serial_tl_domain_serial_tl_0_debug_ser_busy), .serial_tl_0_debug_des_busy (_serial_tl_domain_serial_tl_0_debug_des_busy) ); // @[PeripheryTLSerial.scala:116:38] TLUARTClockSinkDomain uartClockDomainWrapper ( // @[UART.scala:270:44] .auto_uart_0_int_xing_out_sync_0 (intXingIn_sync_0), .auto_uart_0_control_xing_in_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready), .auto_uart_0_control_xing_in_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid), .auto_uart_0_control_xing_in_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode), .auto_uart_0_control_xing_in_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size), .auto_uart_0_control_xing_in_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source), .auto_uart_0_control_xing_in_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data), .auto_uart_0_io_out_txd (ioNodeIn_txd), .auto_uart_0_io_out_rxd (ioNodeIn_rxd), // @[MixedNode.scala:551:17] .auto_clock_in_clock (_pbus_auto_fixedClockNode_anon_out_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_pbus_auto_fixedClockNode_anon_out_reset) // @[PeripheryBus.scala:37:26] ); // @[UART.scala:270:44] IntSyncSyncCrossingSink_n1x1_5 intsink ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intXingOut_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (ibus_auto_int_bus_anon_in_0) ); // @[Crossing.scala:109:29] ChipyardPRCICtrlClockSinkDomain chipyard_prcictrl_domain ( // @[BusWrapper.scala:89:28] .auto_reset_setter_clock_in_member_allClocks_uncore_clock (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0), // @[DigitalTop.scala:47:7] .auto_reset_setter_clock_in_member_allClocks_uncore_reset (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0), // @[DigitalTop.scala:47:7] .auto_resetSynchronizer_out_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock), .auto_resetSynchronizer_out_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset), .auto_xbar_anon_in_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready), .auto_xbar_anon_in_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid), .auto_xbar_anon_in_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode), .auto_xbar_anon_in_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size), .auto_xbar_anon_in_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source), .auto_xbar_anon_in_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_4_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_4_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] ClockGroupAggregator_allClocks aggregator ( // @[HasChipyardPRCI.scala:51:30] .auto_in_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_out_5_member_clockTapNode_clockTapNode_clock_tap_clock (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock), .auto_out_5_member_clockTapNode_clockTapNode_clock_tap_reset (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset), .auto_out_4_member_cbus_cbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock), .auto_out_4_member_cbus_cbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset), .auto_out_3_member_mbus_mbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock), .auto_out_3_member_mbus_mbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset), .auto_out_2_member_fbus_fbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock), .auto_out_2_member_fbus_fbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset), .auto_out_1_member_pbus_pbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock), .auto_out_1_member_pbus_pbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset), .auto_out_0_member_sbus_sbus_1_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock), .auto_out_0_member_sbus_sbus_1_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset), .auto_out_0_member_sbus_sbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock), .auto_out_0_member_sbus_sbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset) ); // @[HasChipyardPRCI.scala:51:30] ClockGroupCombiner clockGroupCombiner ( // @[ClockGroupCombiner.scala:19:15] .auto_clock_group_combiner_in_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock), // @[BusWrapper.scala:89:28] .auto_clock_group_combiner_in_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset), // @[BusWrapper.scala:89:28] .auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock), .auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset), .auto_clock_group_combiner_out_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock), .auto_clock_group_combiner_out_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset), .auto_clock_group_combiner_out_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset) ); // @[ClockGroupCombiner.scala:19:15] ClockSinkDomain_1 globalNoCDomain ( // @[GlobalNoC.scala:45:40] .auto_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_2_clock), // @[SystemBus.scala:31:26] .auto_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_2_reset) // @[SystemBus.scala:31:26] ); // @[GlobalNoC.scala:45:40] BundleBridgeNexus_NoOutput_8 reRoCCManagerIdNexusNode (); // @[Integration.scala:34:44] DebugTransportModuleJTAG dtm ( // @[Periphery.scala:166:21] .io_jtag_clock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_jtag_reset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7] .io_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready), // @[Periphery.scala:88:26] .io_dmi_req_valid (_dtm_io_dmi_req_valid), .io_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr), .io_dmi_req_bits_data (_dtm_io_dmi_req_bits_data), .io_dmi_req_bits_op (_dtm_io_dmi_req_bits_op), .io_dmi_resp_ready (_dtm_io_dmi_resp_ready), .io_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid), // @[Periphery.scala:88:26] .io_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data), // @[Periphery.scala:88:26] .io_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp), // @[Periphery.scala:88:26] .io_jtag_TCK (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_jtag_TMS (debug_systemjtag_jtag_TMS_0), // @[DigitalTop.scala:47:7] .io_jtag_TDI (debug_systemjtag_jtag_TDI_0), // @[DigitalTop.scala:47:7] .io_jtag_TDO_data (debug_systemjtag_jtag_TDO_data_0), .io_jtag_TDO_driven (debug_systemjtag_jtag_TDO_driven), .rf_reset (debug_systemjtag_reset_0) // @[DigitalTop.scala:47:7] ); // @[Periphery.scala:166:21] assign auto_mbus_fixedClockNode_anon_out_clock = auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] assign auto_mbus_fixedClockNode_anon_out_reset = auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] assign auto_cbus_fixedClockNode_anon_out_clock = auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] assign auto_cbus_fixedClockNode_anon_out_reset = auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] assign debug_systemjtag_jtag_TDO_data = debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7] assign debug_dmactive = debug_dmactive_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_valid = mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_id = mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_addr = mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_len = mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_size = mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_burst = mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_lock = mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_cache = mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_prot = mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_qos = mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_valid = mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_data = mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_strb = mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_last = mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_b_ready = mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_valid = mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_id = mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_addr = mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_len = mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_size = mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_burst = mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_lock = mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_cache = mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_prot = mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_qos = mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_r_ready = mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_in_ready = serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_out_valid = serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_out_bits_phit = serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7] assign uart_0_txd = uart_0_txd_0; // @[DigitalTop.scala:47:7] assign clock_tap = clockTapIn_clock; // @[MixedNode.scala:551:17] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_82 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}, flip out_credit_available : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}} inst input_buffer of InputBuffer_82 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) inst route_arbiter of Arbiter5_RouteComputerReq_10 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<5>}[5], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_9 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_9 : connect states[1].g, UInt<3>(0h2) connect route_arbiter.io.in[2].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[2].bits.flow.egress_node_id invalidate route_arbiter.io.in[2].bits.flow.egress_node invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id invalidate route_arbiter.io.in[2].bits.flow.ingress_node invalidate route_arbiter.io.in[2].bits.flow.vnet_id invalidate route_arbiter.io.in[2].bits.src_virt_id connect route_arbiter.io.in[3].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[3].bits.flow.egress_node_id invalidate route_arbiter.io.in[3].bits.flow.egress_node invalidate route_arbiter.io.in[3].bits.flow.ingress_node_id invalidate route_arbiter.io.in[3].bits.flow.ingress_node invalidate route_arbiter.io.in[3].bits.flow.vnet_id invalidate route_arbiter.io.in[3].bits.src_virt_id connect route_arbiter.io.in[4].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[4].bits.flow.egress_node_id invalidate route_arbiter.io.in[4].bits.flow.egress_node invalidate route_arbiter.io.in[4].bits.flow.ingress_node_id invalidate route_arbiter.io.in[4].bits.flow.ingress_node invalidate route_arbiter.io.in[4].bits.flow.vnet_id invalidate route_arbiter.io.in[4].bits.src_virt_id node _T_10 = and(io.router_req.ready, io.router_req.valid) when _T_10 : node _T_11 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_15 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_15 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_16 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_16 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_17 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_17 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_18 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_18 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` node _T_19 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_19 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` regreset mask : UInt<5>, clock, reset, UInt<5>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}}[5] wire vcalloc_vals : UInt<1>[5] node vcalloc_filter_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_vals[2]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_vals[2]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_14, UInt<10>(0h200), UInt<10>(0h0)) node _vcalloc_filter_T_16 = mux(_vcalloc_filter_T_13, UInt<10>(0h100), _vcalloc_filter_T_15) node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_12, UInt<10>(0h80), _vcalloc_filter_T_16) node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_11, UInt<10>(0h40), _vcalloc_filter_T_17) node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_10, UInt<10>(0h20), _vcalloc_filter_T_18) node _vcalloc_filter_T_20 = mux(_vcalloc_filter_T_9, UInt<10>(0h10), _vcalloc_filter_T_19) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_8, UInt<10>(0h8), _vcalloc_filter_T_20) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_7, UInt<10>(0h4), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_6, UInt<10>(0h2), _vcalloc_filter_T_22) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<10>(0h1), _vcalloc_filter_T_23) node _vcalloc_sel_T = bits(vcalloc_filter, 4, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 5) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_20 = and(io.router_req.ready, io.router_req.valid) when _T_20 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_21 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_22 = or(_T_21, vcalloc_vals[2]) node _T_23 = or(_T_22, vcalloc_vals[3]) node _T_24 = or(_T_23, vcalloc_vals[4]) when _T_24 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = bits(vcalloc_sel, 0, 0) node _mask_T_9 = bits(vcalloc_sel, 1, 1) node _mask_T_10 = bits(vcalloc_sel, 2, 2) node _mask_T_11 = bits(vcalloc_sel, 3, 3) node _mask_T_12 = bits(vcalloc_sel, 4, 4) node _mask_T_13 = mux(_mask_T_8, _mask_T_3, UInt<1>(0h0)) node _mask_T_14 = mux(_mask_T_9, _mask_T_4, UInt<1>(0h0)) node _mask_T_15 = mux(_mask_T_10, _mask_T_5, UInt<1>(0h0)) node _mask_T_16 = mux(_mask_T_11, _mask_T_6, UInt<1>(0h0)) node _mask_T_17 = mux(_mask_T_12, _mask_T_7, UInt<1>(0h0)) node _mask_T_18 = or(_mask_T_13, _mask_T_14) node _mask_T_19 = or(_mask_T_18, _mask_T_15) node _mask_T_20 = or(_mask_T_19, _mask_T_16) node _mask_T_21 = or(_mask_T_20, _mask_T_17) wire _mask_WIRE : UInt<5> connect _mask_WIRE, _mask_T_21 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]}} wire _io_vcalloc_req_bits_WIRE_1 : { `1` : UInt<1>[5], `0` : UInt<1>[5]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[5] node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6) node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_7) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_8) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_12, _io_vcalloc_req_bits_T_9) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_13 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_16) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_17) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_18) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_29 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_30 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_30, _io_vcalloc_req_bits_T_27) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_31 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33) node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_35) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_36) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_40 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_49 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[5] node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_55, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_54) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_58 connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_60) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_61) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_62) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_63) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_8[1], _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_74 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_75 = or(_io_vcalloc_req_bits_T_74, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_75, _io_vcalloc_req_bits_T_72) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_76 connect _io_vcalloc_req_bits_WIRE_8[2], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_81 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_78) node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_79) node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_80) node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_81) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_85 connect _io_vcalloc_req_bits_WIRE_8[3], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_94 connect _io_vcalloc_req_bits_WIRE_8[4], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_8 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_97 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_96) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_97) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_98) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_99) wire _io_vcalloc_req_bits_WIRE_14 : UInt<3> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_103 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_14 wire _io_vcalloc_req_bits_WIRE_15 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_104, _io_vcalloc_req_bits_T_105) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_108) wire _io_vcalloc_req_bits_WIRE_16 : UInt<2> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_15.egress_node_id, _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_117) wire _io_vcalloc_req_bits_WIRE_17 : UInt<5> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_121 connect _io_vcalloc_req_bits_WIRE_15.egress_node, _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_122 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_123 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_123) node _io_vcalloc_req_bits_T_128 = or(_io_vcalloc_req_bits_T_127, _io_vcalloc_req_bits_T_124) node _io_vcalloc_req_bits_T_129 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_125) node _io_vcalloc_req_bits_T_130 = or(_io_vcalloc_req_bits_T_129, _io_vcalloc_req_bits_T_126) wire _io_vcalloc_req_bits_WIRE_18 : UInt<2> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_130 connect _io_vcalloc_req_bits_WIRE_15.ingress_node_id, _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_131, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_19 : UInt<5> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_139 connect _io_vcalloc_req_bits_WIRE_15.ingress_node, _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_140 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_141 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_142 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_141) node _io_vcalloc_req_bits_T_146 = or(_io_vcalloc_req_bits_T_145, _io_vcalloc_req_bits_T_142) node _io_vcalloc_req_bits_T_147 = or(_io_vcalloc_req_bits_T_146, _io_vcalloc_req_bits_T_143) node _io_vcalloc_req_bits_T_148 = or(_io_vcalloc_req_bits_T_147, _io_vcalloc_req_bits_T_144) wire _io_vcalloc_req_bits_WIRE_20 : UInt<3> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_148 connect _io_vcalloc_req_bits_WIRE_15.vnet_id, _io_vcalloc_req_bits_WIRE_20 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_15 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].flow, states[1].flow node _T_25 = bits(vcalloc_sel, 1, 1) node _T_26 = and(vcalloc_vals[1], _T_25) node _T_27 = and(_T_26, io.vcalloc_req.ready) when _T_27 : connect states[1].g, UInt<3>(0h3) connect vcalloc_vals[2], UInt<1>(0h0) invalidate vcalloc_reqs[2].vc_sel.`0`[0] invalidate vcalloc_reqs[2].vc_sel.`0`[1] invalidate vcalloc_reqs[2].vc_sel.`0`[2] invalidate vcalloc_reqs[2].vc_sel.`0`[3] invalidate vcalloc_reqs[2].vc_sel.`0`[4] invalidate vcalloc_reqs[2].vc_sel.`1`[0] invalidate vcalloc_reqs[2].vc_sel.`1`[1] invalidate vcalloc_reqs[2].vc_sel.`1`[2] invalidate vcalloc_reqs[2].vc_sel.`1`[3] invalidate vcalloc_reqs[2].vc_sel.`1`[4] invalidate vcalloc_reqs[2].in_vc invalidate vcalloc_reqs[2].flow.egress_node_id invalidate vcalloc_reqs[2].flow.egress_node invalidate vcalloc_reqs[2].flow.ingress_node_id invalidate vcalloc_reqs[2].flow.ingress_node invalidate vcalloc_reqs[2].flow.vnet_id connect vcalloc_vals[3], UInt<1>(0h0) invalidate vcalloc_reqs[3].vc_sel.`0`[0] invalidate vcalloc_reqs[3].vc_sel.`0`[1] invalidate vcalloc_reqs[3].vc_sel.`0`[2] invalidate vcalloc_reqs[3].vc_sel.`0`[3] invalidate vcalloc_reqs[3].vc_sel.`0`[4] invalidate vcalloc_reqs[3].vc_sel.`1`[0] invalidate vcalloc_reqs[3].vc_sel.`1`[1] invalidate vcalloc_reqs[3].vc_sel.`1`[2] invalidate vcalloc_reqs[3].vc_sel.`1`[3] invalidate vcalloc_reqs[3].vc_sel.`1`[4] invalidate vcalloc_reqs[3].in_vc invalidate vcalloc_reqs[3].flow.egress_node_id invalidate vcalloc_reqs[3].flow.egress_node invalidate vcalloc_reqs[3].flow.ingress_node_id invalidate vcalloc_reqs[3].flow.ingress_node invalidate vcalloc_reqs[3].flow.vnet_id connect vcalloc_vals[4], UInt<1>(0h0) invalidate vcalloc_reqs[4].vc_sel.`0`[0] invalidate vcalloc_reqs[4].vc_sel.`0`[1] invalidate vcalloc_reqs[4].vc_sel.`0`[2] invalidate vcalloc_reqs[4].vc_sel.`0`[3] invalidate vcalloc_reqs[4].vc_sel.`0`[4] invalidate vcalloc_reqs[4].vc_sel.`1`[0] invalidate vcalloc_reqs[4].vc_sel.`1`[1] invalidate vcalloc_reqs[4].vc_sel.`1`[2] invalidate vcalloc_reqs[4].vc_sel.`1`[3] invalidate vcalloc_reqs[4].vc_sel.`1`[4] invalidate vcalloc_reqs[4].in_vc invalidate vcalloc_reqs[4].flow.egress_node_id invalidate vcalloc_reqs[4].flow.egress_node invalidate vcalloc_reqs[4].flow.ingress_node_id invalidate vcalloc_reqs[4].flow.ingress_node invalidate vcalloc_reqs[4].flow.vnet_id node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0) node _io_debug_va_stall_T_8 = sub(_io_debug_va_stall_T_7, io.vcalloc_req.ready) node _io_debug_va_stall_T_9 = tail(_io_debug_va_stall_T_8, 1) connect io.debug.va_stall, _io_debug_va_stall_T_9 node _T_28 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_28 : node _T_29 = bits(vcalloc_sel, 0, 0) when _T_29 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].g, UInt<3>(0h3) node _T_30 = eq(states[0].g, UInt<3>(0h2)) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_30, UInt<1>(0h1), "") : assert_3 node _T_34 = bits(vcalloc_sel, 1, 1) when _T_34 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].g, UInt<3>(0h3) node _T_35 = eq(states[1].g, UInt<3>(0h2)) node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(_T_35, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_35, UInt<1>(0h1), "") : assert_4 node _T_39 = bits(vcalloc_sel, 2, 2) when _T_39 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].g, UInt<3>(0h3) node _T_40 = eq(states[2].g, UInt<3>(0h2)) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_40, UInt<1>(0h1), "") : assert_5 node _T_44 = bits(vcalloc_sel, 3, 3) when _T_44 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].g, UInt<3>(0h3) node _T_45 = eq(states[3].g, UInt<3>(0h2)) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_45, UInt<1>(0h1), "") : assert_6 node _T_49 = bits(vcalloc_sel, 4, 4) when _T_49 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].g, UInt<3>(0h3) node _T_50 = eq(states[4].g, UInt<3>(0h2)) node _T_51 = asUInt(reset) node _T_52 = eq(_T_51, UInt<1>(0h0)) when _T_52 : node _T_53 = eq(_T_50, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_50, UInt<1>(0h1), "") : assert_7 inst salloc_arb of SwitchArbiter_222 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] node credit_available_lo = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_hi_hi = cat(states[1].vc_sel.`0`[4], states[1].vc_sel.`0`[3]) node credit_available_hi = cat(credit_available_hi_hi, states[1].vc_sel.`0`[2]) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node credit_available_hi_hi_1 = cat(states[1].vc_sel.`1`[4], states[1].vc_sel.`1`[3]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, states[1].vc_sel.`1`[2]) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node _credit_available_T_2 = cat(_credit_available_T_1, _credit_available_T) node credit_available_lo_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_hi_hi_2 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, io.out_credit_available.`0`[2]) node _credit_available_T_3 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_3 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_hi_hi_3 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, io.out_credit_available.`1`[2]) node _credit_available_T_4 = cat(credit_available_hi_3, credit_available_lo_3) node _credit_available_T_5 = cat(_credit_available_T_4, _credit_available_T_3) node _credit_available_T_6 = and(_credit_available_T_2, _credit_available_T_5) node credit_available = neq(_credit_available_T_6, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3] connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_54 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_55 = and(_T_54, input_buffer.io.deq[1].bits.tail) when _T_55 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready connect salloc_arb.io.in[2].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[2].bits.tail invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[4] connect salloc_arb.io.in[3].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[3].bits.tail invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[4] connect salloc_arb.io.in[4].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[4].bits.tail invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[4] node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_11 = bits(_io_debug_sa_stall_T_10, 1, 0) node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9) node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 1, 0) node _io_debug_sa_stall_T_14 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_15 = bits(_io_debug_sa_stall_T_14, 1, 0) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 2, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_17 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = or(_io_in_vc_free_T_6, _io_in_vc_free_T_7) node _io_in_vc_free_T_12 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_8) node _io_in_vc_free_T_13 = or(_io_in_vc_free_T_12, _io_in_vc_free_T_9) node _io_in_vc_free_T_14 = or(_io_in_vc_free_T_13, _io_in_vc_free_T_10) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_14 node _io_in_vc_free_T_15 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_15, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_16 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 4, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) wire vc_sel : { `1` : UInt<1>[5], `0` : UInt<1>[5]} wire _vc_sel_WIRE : UInt<1>[5] node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_7 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_8 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = or(_vc_sel_T_5, _vc_sel_T_6) node _vc_sel_T_11 = or(_vc_sel_T_10, _vc_sel_T_7) node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_8) node _vc_sel_T_13 = or(_vc_sel_T_12, _vc_sel_T_9) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_13 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_16 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_17 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_19 = or(_vc_sel_T_14, _vc_sel_T_15) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_16) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_17) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_18) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_22 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_28 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_29 = or(_vc_sel_T_28, _vc_sel_T_25) node _vc_sel_T_30 = or(_vc_sel_T_29, _vc_sel_T_26) node _vc_sel_T_31 = or(_vc_sel_T_30, _vc_sel_T_27) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_31 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_32 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_36 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_37 = or(_vc_sel_T_32, _vc_sel_T_33) node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_34) node _vc_sel_T_39 = or(_vc_sel_T_38, _vc_sel_T_35) node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_36) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_40 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_41 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_41, _vc_sel_T_42) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_43) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_44) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_45) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_49 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_6 : UInt<1>[5] node _vc_sel_T_50 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_55 = or(_vc_sel_T_50, _vc_sel_T_51) node _vc_sel_T_56 = or(_vc_sel_T_55, _vc_sel_T_52) node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_53) node _vc_sel_T_58 = or(_vc_sel_T_57, _vc_sel_T_54) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_58 connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7 node _vc_sel_T_59 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_61 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_62 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_63 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_64 = or(_vc_sel_T_59, _vc_sel_T_60) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_61) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_62) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_63) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_67 connect _vc_sel_WIRE_6[1], _vc_sel_WIRE_8 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_73 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_74 = or(_vc_sel_T_73, _vc_sel_T_70) node _vc_sel_T_75 = or(_vc_sel_T_74, _vc_sel_T_71) node _vc_sel_T_76 = or(_vc_sel_T_75, _vc_sel_T_72) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_76 connect _vc_sel_WIRE_6[2], _vc_sel_WIRE_9 node _vc_sel_T_77 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_78 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_79 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_80 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_81 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_82 = or(_vc_sel_T_77, _vc_sel_T_78) node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_79) node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_80) node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_81) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_85 connect _vc_sel_WIRE_6[3], _vc_sel_WIRE_10 node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_86, _vc_sel_T_87) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_88) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_89) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_90) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_94 connect _vc_sel_WIRE_6[4], _vc_sel_WIRE_11 connect vc_sel.`1`, _vc_sel_WIRE_6 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node channel_oh_0 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_3 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`1`[2]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`1`[3]) node channel_oh_1 = or(_channel_oh_T_5, vc_sel.`1`[4]) node virt_channel_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3]) node virt_channel_hi = cat(virt_channel_hi_hi, vc_sel.`0`[2]) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 4, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_3 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[4], vc_sel.`1`[3]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, vc_sel.`1`[2]) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 4, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node _virt_channel_T_16 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_17 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_18 = or(_virt_channel_T_16, _virt_channel_T_17) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_18 node _T_56 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_56 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = or(_salloc_outs_0_flit_payload_T_5, _salloc_outs_0_flit_payload_T_6) node _salloc_outs_0_flit_payload_T_11 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_7) node _salloc_outs_0_flit_payload_T_12 = or(_salloc_outs_0_flit_payload_T_11, _salloc_outs_0_flit_payload_T_8) node _salloc_outs_0_flit_payload_T_13 = or(_salloc_outs_0_flit_payload_T_12, _salloc_outs_0_flit_payload_T_9) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_13 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = or(_salloc_outs_0_flit_head_T_5, _salloc_outs_0_flit_head_T_6) node _salloc_outs_0_flit_head_T_11 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_7) node _salloc_outs_0_flit_head_T_12 = or(_salloc_outs_0_flit_head_T_11, _salloc_outs_0_flit_head_T_8) node _salloc_outs_0_flit_head_T_13 = or(_salloc_outs_0_flit_head_T_12, _salloc_outs_0_flit_head_T_9) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_13 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = or(_salloc_outs_0_flit_tail_T_5, _salloc_outs_0_flit_tail_T_6) node _salloc_outs_0_flit_tail_T_11 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_7) node _salloc_outs_0_flit_tail_T_12 = or(_salloc_outs_0_flit_tail_T_11, _salloc_outs_0_flit_tail_T_8) node _salloc_outs_0_flit_tail_T_13 = or(_salloc_outs_0_flit_tail_T_12, _salloc_outs_0_flit_tail_T_9) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_13 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6) node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_7) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_8) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_12, _salloc_outs_0_flit_flow_T_9) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_13 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_16) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_17) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_18) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_29 = or(_salloc_outs_0_flit_flow_T_28, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_30 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_30, _salloc_outs_0_flit_flow_T_27) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_31 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_33) node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_34) node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_35) node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_36) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_40 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_49 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`0`[3], UInt<1>(0h0) connect states[1].vc_sel.`0`[4], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[1], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[3], UInt<1>(0h0) connect states[1].vc_sel.`1`[4], UInt<1>(0h0) invalidate states[2].fifo_deps invalidate states[2].flow.egress_node_id invalidate states[2].flow.egress_node invalidate states[2].flow.ingress_node_id invalidate states[2].flow.ingress_node invalidate states[2].flow.vnet_id invalidate states[2].vc_sel.`0`[0] invalidate states[2].vc_sel.`0`[1] invalidate states[2].vc_sel.`0`[2] invalidate states[2].vc_sel.`0`[3] invalidate states[2].vc_sel.`0`[4] invalidate states[2].vc_sel.`1`[0] invalidate states[2].vc_sel.`1`[1] invalidate states[2].vc_sel.`1`[2] invalidate states[2].vc_sel.`1`[3] invalidate states[2].vc_sel.`1`[4] invalidate states[2].g invalidate states[3].fifo_deps invalidate states[3].flow.egress_node_id invalidate states[3].flow.egress_node invalidate states[3].flow.ingress_node_id invalidate states[3].flow.ingress_node invalidate states[3].flow.vnet_id invalidate states[3].vc_sel.`0`[0] invalidate states[3].vc_sel.`0`[1] invalidate states[3].vc_sel.`0`[2] invalidate states[3].vc_sel.`0`[3] invalidate states[3].vc_sel.`0`[4] invalidate states[3].vc_sel.`1`[0] invalidate states[3].vc_sel.`1`[1] invalidate states[3].vc_sel.`1`[2] invalidate states[3].vc_sel.`1`[3] invalidate states[3].vc_sel.`1`[4] invalidate states[3].g invalidate states[4].fifo_deps invalidate states[4].flow.egress_node_id invalidate states[4].flow.egress_node invalidate states[4].flow.ingress_node_id invalidate states[4].flow.ingress_node invalidate states[4].flow.vnet_id invalidate states[4].vc_sel.`0`[0] invalidate states[4].vc_sel.`0`[1] invalidate states[4].vc_sel.`0`[2] invalidate states[4].vc_sel.`0`[3] invalidate states[4].vc_sel.`0`[4] invalidate states[4].vc_sel.`1`[0] invalidate states[4].vc_sel.`1`[1] invalidate states[4].vc_sel.`1`[2] invalidate states[4].vc_sel.`1`[3] invalidate states[4].vc_sel.`1`[4] invalidate states[4].g node _T_57 = asUInt(reset) when _T_57 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0)	module InputUnit_82( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [4:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [4:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [4:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [4:0] mask; // @[InputUnit.scala:250:21] wire [4:0] _vcalloc_filter_T_3 = {3'h0, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [9:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 10'h1 : _vcalloc_filter_T_3[1] ? 10'h2 : _vcalloc_filter_T_3[2] ? 10'h4 : _vcalloc_filter_T_3[3] ? 10'h8 : _vcalloc_filter_T_3[4] ? 10'h10 : {3'h0, vcalloc_vals_1, 6'h0}; // @[OneHot.scala:85:71] wire [4:0] vcalloc_sel = vcalloc_filter[4:0] \| vcalloc_filter[9:5]; // @[Mux.scala:50:70] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_1; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module TSIToTileLink : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { tsi : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}}, state : UInt} wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut reg cmd : UInt<32>, clock reg addr : UInt<64>, clock reg len : UInt<64>, clock reg body : UInt<32>[2], clock reg bodyValid : UInt<2>, clock reg idx : UInt<1>, clock regreset state : UInt<4>, clock, reset, UInt<4>(0h0) connect io.state, state node _io_tsi_in_ready_T = eq(state, UInt<4>(0h0)) node _io_tsi_in_ready_T_1 = eq(state, UInt<4>(0h1)) node _io_tsi_in_ready_T_2 = eq(state, UInt<4>(0h2)) node _io_tsi_in_ready_T_3 = eq(state, UInt<4>(0h6)) node _io_tsi_in_ready_T_4 = or(_io_tsi_in_ready_T, _io_tsi_in_ready_T_1) node _io_tsi_in_ready_T_5 = or(_io_tsi_in_ready_T_4, _io_tsi_in_ready_T_2) node _io_tsi_in_ready_T_6 = or(_io_tsi_in_ready_T_5, _io_tsi_in_ready_T_3) connect io.tsi.in.ready, _io_tsi_in_ready_T_6 node _io_tsi_out_valid_T = eq(state, UInt<4>(0h5)) connect io.tsi.out.valid, _io_tsi_out_valid_T connect io.tsi.out.bits, body[idx] node beatAddr = bits(addr, 31, 3) node _nextAddr_T = add(beatAddr, UInt<1>(0h1)) node _nextAddr_T_1 = tail(_nextAddr_T, 1) node nextAddr = cat(_nextAddr_T_1, UInt<3>(0h0)) node _wmask_T = bits(bodyValid, 0, 0) node _wmask_T_1 = bits(bodyValid, 1, 1) node _wmask_T_2 = mux(_wmask_T, UInt<4>(0hf), UInt<4>(0h0)) node _wmask_T_3 = mux(_wmask_T_1, UInt<4>(0hf), UInt<4>(0h0)) node wmask = cat(_wmask_T_3, _wmask_T_2) node _addr_size_T = sub(nextAddr, addr) node addr_size = tail(_addr_size_T, 1) node _len_size_T = add(len, UInt<1>(0h1)) node _len_size_T_1 = tail(_len_size_T, 1) node len_size = cat(_len_size_T_1, UInt<2>(0h0)) node _raw_size_T = lt(len_size, addr_size) node raw_size = mux(_raw_size_T, len_size, addr_size) node _rsize_T = eq(UInt<1>(0h1), raw_size) node _rsize_T_1 = mux(_rsize_T, UInt<1>(0h0), UInt<2>(0h3)) node _rsize_T_2 = eq(UInt<2>(0h2), raw_size) node _rsize_T_3 = mux(_rsize_T_2, UInt<1>(0h1), _rsize_T_1) node _rsize_T_4 = eq(UInt<3>(0h4), raw_size) node rsize = mux(_rsize_T_4, UInt<2>(0h2), _rsize_T_3) node _pow2size_T = bits(raw_size, 0, 0) node _pow2size_T_1 = bits(raw_size, 1, 1) node _pow2size_T_2 = bits(raw_size, 2, 2) node _pow2size_T_3 = bits(raw_size, 3, 3) node _pow2size_T_4 = bits(raw_size, 4, 4) node _pow2size_T_5 = bits(raw_size, 5, 5) node _pow2size_T_6 = bits(raw_size, 6, 6) node _pow2size_T_7 = bits(raw_size, 7, 7) node _pow2size_T_8 = bits(raw_size, 8, 8) node _pow2size_T_9 = bits(raw_size, 9, 9) node _pow2size_T_10 = bits(raw_size, 10, 10) node _pow2size_T_11 = bits(raw_size, 11, 11) node _pow2size_T_12 = bits(raw_size, 12, 12) node _pow2size_T_13 = bits(raw_size, 13, 13) node _pow2size_T_14 = bits(raw_size, 14, 14) node _pow2size_T_15 = bits(raw_size, 15, 15) node _pow2size_T_16 = bits(raw_size, 16, 16) node _pow2size_T_17 = bits(raw_size, 17, 17) node _pow2size_T_18 = bits(raw_size, 18, 18) node _pow2size_T_19 = bits(raw_size, 19, 19) node _pow2size_T_20 = bits(raw_size, 20, 20) node _pow2size_T_21 = bits(raw_size, 21, 21) node _pow2size_T_22 = bits(raw_size, 22, 22) node _pow2size_T_23 = bits(raw_size, 23, 23) node _pow2size_T_24 = bits(raw_size, 24, 24) node _pow2size_T_25 = bits(raw_size, 25, 25) node _pow2size_T_26 = bits(raw_size, 26, 26) node _pow2size_T_27 = bits(raw_size, 27, 27) node _pow2size_T_28 = bits(raw_size, 28, 28) node _pow2size_T_29 = bits(raw_size, 29, 29) node _pow2size_T_30 = bits(raw_size, 30, 30) node _pow2size_T_31 = bits(raw_size, 31, 31) node _pow2size_T_32 = bits(raw_size, 32, 32) node _pow2size_T_33 = bits(raw_size, 33, 33) node _pow2size_T_34 = bits(raw_size, 34, 34) node _pow2size_T_35 = bits(raw_size, 35, 35) node _pow2size_T_36 = bits(raw_size, 36, 36) node _pow2size_T_37 = bits(raw_size, 37, 37) node _pow2size_T_38 = bits(raw_size, 38, 38) node _pow2size_T_39 = bits(raw_size, 39, 39) node _pow2size_T_40 = bits(raw_size, 40, 40) node _pow2size_T_41 = bits(raw_size, 41, 41) node _pow2size_T_42 = bits(raw_size, 42, 42) node _pow2size_T_43 = bits(raw_size, 43, 43) node _pow2size_T_44 = bits(raw_size, 44, 44) node _pow2size_T_45 = bits(raw_size, 45, 45) node _pow2size_T_46 = bits(raw_size, 46, 46) node _pow2size_T_47 = bits(raw_size, 47, 47) node _pow2size_T_48 = bits(raw_size, 48, 48) node _pow2size_T_49 = bits(raw_size, 49, 49) node _pow2size_T_50 = bits(raw_size, 50, 50) node _pow2size_T_51 = bits(raw_size, 51, 51) node _pow2size_T_52 = bits(raw_size, 52, 52) node _pow2size_T_53 = bits(raw_size, 53, 53) node _pow2size_T_54 = bits(raw_size, 54, 54) node _pow2size_T_55 = bits(raw_size, 55, 55) node _pow2size_T_56 = bits(raw_size, 56, 56) node _pow2size_T_57 = bits(raw_size, 57, 57) node _pow2size_T_58 = bits(raw_size, 58, 58) node _pow2size_T_59 = bits(raw_size, 59, 59) node _pow2size_T_60 = bits(raw_size, 60, 60) node _pow2size_T_61 = bits(raw_size, 61, 61) node _pow2size_T_62 = bits(raw_size, 62, 62) node _pow2size_T_63 = bits(raw_size, 63, 63) node _pow2size_T_64 = bits(raw_size, 64, 64) node _pow2size_T_65 = bits(raw_size, 65, 65) node _pow2size_T_66 = add(_pow2size_T, _pow2size_T_1) node _pow2size_T_67 = bits(_pow2size_T_66, 1, 0) node _pow2size_T_68 = add(_pow2size_T_2, _pow2size_T_3) node _pow2size_T_69 = bits(_pow2size_T_68, 1, 0) node _pow2size_T_70 = add(_pow2size_T_67, _pow2size_T_69) node _pow2size_T_71 = bits(_pow2size_T_70, 2, 0) node _pow2size_T_72 = add(_pow2size_T_4, _pow2size_T_5) node _pow2size_T_73 = bits(_pow2size_T_72, 1, 0) node _pow2size_T_74 = add(_pow2size_T_6, _pow2size_T_7) node _pow2size_T_75 = bits(_pow2size_T_74, 1, 0) node _pow2size_T_76 = add(_pow2size_T_73, _pow2size_T_75) node _pow2size_T_77 = bits(_pow2size_T_76, 2, 0) node _pow2size_T_78 = add(_pow2size_T_71, _pow2size_T_77) node _pow2size_T_79 = bits(_pow2size_T_78, 3, 0) node _pow2size_T_80 = add(_pow2size_T_8, _pow2size_T_9) node _pow2size_T_81 = bits(_pow2size_T_80, 1, 0) node _pow2size_T_82 = add(_pow2size_T_10, _pow2size_T_11) node _pow2size_T_83 = bits(_pow2size_T_82, 1, 0) node _pow2size_T_84 = add(_pow2size_T_81, _pow2size_T_83) node _pow2size_T_85 = bits(_pow2size_T_84, 2, 0) node _pow2size_T_86 = add(_pow2size_T_12, _pow2size_T_13) node _pow2size_T_87 = bits(_pow2size_T_86, 1, 0) node _pow2size_T_88 = add(_pow2size_T_14, _pow2size_T_15) node _pow2size_T_89 = bits(_pow2size_T_88, 1, 0) node _pow2size_T_90 = add(_pow2size_T_87, _pow2size_T_89) node _pow2size_T_91 = bits(_pow2size_T_90, 2, 0) node _pow2size_T_92 = add(_pow2size_T_85, _pow2size_T_91) node _pow2size_T_93 = bits(_pow2size_T_92, 3, 0) node _pow2size_T_94 = add(_pow2size_T_79, _pow2size_T_93) node _pow2size_T_95 = bits(_pow2size_T_94, 4, 0) node _pow2size_T_96 = add(_pow2size_T_16, _pow2size_T_17) node _pow2size_T_97 = bits(_pow2size_T_96, 1, 0) node _pow2size_T_98 = add(_pow2size_T_18, _pow2size_T_19) node _pow2size_T_99 = bits(_pow2size_T_98, 1, 0) node _pow2size_T_100 = add(_pow2size_T_97, _pow2size_T_99) node _pow2size_T_101 = bits(_pow2size_T_100, 2, 0) node _pow2size_T_102 = add(_pow2size_T_20, _pow2size_T_21) node _pow2size_T_103 = bits(_pow2size_T_102, 1, 0) node _pow2size_T_104 = add(_pow2size_T_22, _pow2size_T_23) node _pow2size_T_105 = bits(_pow2size_T_104, 1, 0) node _pow2size_T_106 = add(_pow2size_T_103, _pow2size_T_105) node _pow2size_T_107 = bits(_pow2size_T_106, 2, 0) node _pow2size_T_108 = add(_pow2size_T_101, _pow2size_T_107) node _pow2size_T_109 = bits(_pow2size_T_108, 3, 0) node _pow2size_T_110 = add(_pow2size_T_24, _pow2size_T_25) node _pow2size_T_111 = bits(_pow2size_T_110, 1, 0) node _pow2size_T_112 = add(_pow2size_T_26, _pow2size_T_27) node _pow2size_T_113 = bits(_pow2size_T_112, 1, 0) node _pow2size_T_114 = add(_pow2size_T_111, _pow2size_T_113) node _pow2size_T_115 = bits(_pow2size_T_114, 2, 0) node _pow2size_T_116 = add(_pow2size_T_28, _pow2size_T_29) node _pow2size_T_117 = bits(_pow2size_T_116, 1, 0) node _pow2size_T_118 = add(_pow2size_T_31, _pow2size_T_32) node _pow2size_T_119 = bits(_pow2size_T_118, 1, 0) node _pow2size_T_120 = add(_pow2size_T_30, _pow2size_T_119) node _pow2size_T_121 = bits(_pow2size_T_120, 1, 0) node _pow2size_T_122 = add(_pow2size_T_117, _pow2size_T_121) node _pow2size_T_123 = bits(_pow2size_T_122, 2, 0) node _pow2size_T_124 = add(_pow2size_T_115, _pow2size_T_123) node _pow2size_T_125 = bits(_pow2size_T_124, 3, 0) node _pow2size_T_126 = add(_pow2size_T_109, _pow2size_T_125) node _pow2size_T_127 = bits(_pow2size_T_126, 4, 0) node _pow2size_T_128 = add(_pow2size_T_95, _pow2size_T_127) node _pow2size_T_129 = bits(_pow2size_T_128, 5, 0) node _pow2size_T_130 = add(_pow2size_T_33, _pow2size_T_34) node _pow2size_T_131 = bits(_pow2size_T_130, 1, 0) node _pow2size_T_132 = add(_pow2size_T_35, _pow2size_T_36) node _pow2size_T_133 = bits(_pow2size_T_132, 1, 0) node _pow2size_T_134 = add(_pow2size_T_131, _pow2size_T_133) node _pow2size_T_135 = bits(_pow2size_T_134, 2, 0) node _pow2size_T_136 = add(_pow2size_T_37, _pow2size_T_38) node _pow2size_T_137 = bits(_pow2size_T_136, 1, 0) node _pow2size_T_138 = add(_pow2size_T_39, _pow2size_T_40) node _pow2size_T_139 = bits(_pow2size_T_138, 1, 0) node _pow2size_T_140 = add(_pow2size_T_137, _pow2size_T_139) node _pow2size_T_141 = bits(_pow2size_T_140, 2, 0) node _pow2size_T_142 = add(_pow2size_T_135, _pow2size_T_141) node _pow2size_T_143 = bits(_pow2size_T_142, 3, 0) node _pow2size_T_144 = add(_pow2size_T_41, _pow2size_T_42) node _pow2size_T_145 = bits(_pow2size_T_144, 1, 0) node _pow2size_T_146 = add(_pow2size_T_43, _pow2size_T_44) node _pow2size_T_147 = bits(_pow2size_T_146, 1, 0) node _pow2size_T_148 = add(_pow2size_T_145, _pow2size_T_147) node _pow2size_T_149 = bits(_pow2size_T_148, 2, 0) node _pow2size_T_150 = add(_pow2size_T_45, _pow2size_T_46) node _pow2size_T_151 = bits(_pow2size_T_150, 1, 0) node _pow2size_T_152 = add(_pow2size_T_47, _pow2size_T_48) node _pow2size_T_153 = bits(_pow2size_T_152, 1, 0) node _pow2size_T_154 = add(_pow2size_T_151, _pow2size_T_153) node _pow2size_T_155 = bits(_pow2size_T_154, 2, 0) node _pow2size_T_156 = add(_pow2size_T_149, _pow2size_T_155) node _pow2size_T_157 = bits(_pow2size_T_156, 3, 0) node _pow2size_T_158 = add(_pow2size_T_143, _pow2size_T_157) node _pow2size_T_159 = bits(_pow2size_T_158, 4, 0) node _pow2size_T_160 = add(_pow2size_T_49, _pow2size_T_50) node _pow2size_T_161 = bits(_pow2size_T_160, 1, 0) node _pow2size_T_162 = add(_pow2size_T_51, _pow2size_T_52) node _pow2size_T_163 = bits(_pow2size_T_162, 1, 0) node _pow2size_T_164 = add(_pow2size_T_161, _pow2size_T_163) node _pow2size_T_165 = bits(_pow2size_T_164, 2, 0) node _pow2size_T_166 = add(_pow2size_T_53, _pow2size_T_54) node _pow2size_T_167 = bits(_pow2size_T_166, 1, 0) node _pow2size_T_168 = add(_pow2size_T_55, _pow2size_T_56) node _pow2size_T_169 = bits(_pow2size_T_168, 1, 0) node _pow2size_T_170 = add(_pow2size_T_167, _pow2size_T_169) node _pow2size_T_171 = bits(_pow2size_T_170, 2, 0) node _pow2size_T_172 = add(_pow2size_T_165, _pow2size_T_171) node _pow2size_T_173 = bits(_pow2size_T_172, 3, 0) node _pow2size_T_174 = add(_pow2size_T_57, _pow2size_T_58) node _pow2size_T_175 = bits(_pow2size_T_174, 1, 0) node _pow2size_T_176 = add(_pow2size_T_59, _pow2size_T_60) node _pow2size_T_177 = bits(_pow2size_T_176, 1, 0) node _pow2size_T_178 = add(_pow2size_T_175, _pow2size_T_177) node _pow2size_T_179 = bits(_pow2size_T_178, 2, 0) node _pow2size_T_180 = add(_pow2size_T_61, _pow2size_T_62) node _pow2size_T_181 = bits(_pow2size_T_180, 1, 0) node _pow2size_T_182 = add(_pow2size_T_64, _pow2size_T_65) node _pow2size_T_183 = bits(_pow2size_T_182, 1, 0) node _pow2size_T_184 = add(_pow2size_T_63, _pow2size_T_183) node _pow2size_T_185 = bits(_pow2size_T_184, 1, 0) node _pow2size_T_186 = add(_pow2size_T_181, _pow2size_T_185) node _pow2size_T_187 = bits(_pow2size_T_186, 2, 0) node _pow2size_T_188 = add(_pow2size_T_179, _pow2size_T_187) node _pow2size_T_189 = bits(_pow2size_T_188, 3, 0) node _pow2size_T_190 = add(_pow2size_T_173, _pow2size_T_189) node _pow2size_T_191 = bits(_pow2size_T_190, 4, 0) node _pow2size_T_192 = add(_pow2size_T_159, _pow2size_T_191) node _pow2size_T_193 = bits(_pow2size_T_192, 5, 0) node _pow2size_T_194 = add(_pow2size_T_129, _pow2size_T_193) node _pow2size_T_195 = bits(_pow2size_T_194, 6, 0) node pow2size = eq(_pow2size_T_195, UInt<1>(0h1)) node _byteAddr_T = bits(addr, 2, 0) node byteAddr = mux(pow2size, _byteAddr_T, UInt<1>(0h0)) node _put_acquire_T = dshl(beatAddr, UInt<2>(0h3)) node _put_acquire_T_1 = cat(body[1], body[0]) node _put_acquire_legal_T = leq(UInt<1>(0h0), UInt<2>(0h3)) node _put_acquire_legal_T_1 = leq(UInt<2>(0h3), UInt<4>(0hc)) node _put_acquire_legal_T_2 = and(_put_acquire_legal_T, _put_acquire_legal_T_1) node _put_acquire_legal_T_3 = or(UInt<1>(0h0), _put_acquire_legal_T_2) node _put_acquire_legal_T_4 = xor(_put_acquire_T, UInt<14>(0h3000)) node _put_acquire_legal_T_5 = cvt(_put_acquire_legal_T_4) node _put_acquire_legal_T_6 = and(_put_acquire_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _put_acquire_legal_T_7 = asSInt(_put_acquire_legal_T_6) node _put_acquire_legal_T_8 = eq(_put_acquire_legal_T_7, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_9 = and(_put_acquire_legal_T_3, _put_acquire_legal_T_8) node _put_acquire_legal_T_10 = leq(UInt<1>(0h0), UInt<2>(0h3)) node _put_acquire_legal_T_11 = leq(UInt<2>(0h3), UInt<3>(0h6)) node _put_acquire_legal_T_12 = and(_put_acquire_legal_T_10, _put_acquire_legal_T_11) node _put_acquire_legal_T_13 = or(UInt<1>(0h0), _put_acquire_legal_T_12) node _put_acquire_legal_T_14 = xor(_put_acquire_T, UInt<1>(0h0)) node _put_acquire_legal_T_15 = cvt(_put_acquire_legal_T_14) node _put_acquire_legal_T_16 = and(_put_acquire_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _put_acquire_legal_T_17 = asSInt(_put_acquire_legal_T_16) node _put_acquire_legal_T_18 = eq(_put_acquire_legal_T_17, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_19 = xor(_put_acquire_T, UInt<21>(0h100000)) node _put_acquire_legal_T_20 = cvt(_put_acquire_legal_T_19) node _put_acquire_legal_T_21 = and(_put_acquire_legal_T_20, asSInt(UInt<33>(0h9a103000))) node _put_acquire_legal_T_22 = asSInt(_put_acquire_legal_T_21) node _put_acquire_legal_T_23 = eq(_put_acquire_legal_T_22, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_24 = xor(_put_acquire_T, UInt<26>(0h2000000)) node _put_acquire_legal_T_25 = cvt(_put_acquire_legal_T_24) node _put_acquire_legal_T_26 = and(_put_acquire_legal_T_25, asSInt(UInt<33>(0h9a110000))) node _put_acquire_legal_T_27 = asSInt(_put_acquire_legal_T_26) node _put_acquire_legal_T_28 = eq(_put_acquire_legal_T_27, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_29 = xor(_put_acquire_T, UInt<26>(0h2010000)) node _put_acquire_legal_T_30 = cvt(_put_acquire_legal_T_29) node _put_acquire_legal_T_31 = and(_put_acquire_legal_T_30, asSInt(UInt<33>(0h9a113000))) node _put_acquire_legal_T_32 = asSInt(_put_acquire_legal_T_31) node _put_acquire_legal_T_33 = eq(_put_acquire_legal_T_32, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_34 = xor(_put_acquire_T, UInt<28>(0h8000000)) node _put_acquire_legal_T_35 = cvt(_put_acquire_legal_T_34) node _put_acquire_legal_T_36 = and(_put_acquire_legal_T_35, asSInt(UInt<33>(0h98000000))) node _put_acquire_legal_T_37 = asSInt(_put_acquire_legal_T_36) node _put_acquire_legal_T_38 = eq(_put_acquire_legal_T_37, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_39 = xor(_put_acquire_T, UInt<28>(0h8000000)) node _put_acquire_legal_T_40 = cvt(_put_acquire_legal_T_39) node _put_acquire_legal_T_41 = and(_put_acquire_legal_T_40, asSInt(UInt<33>(0h9a110000))) node _put_acquire_legal_T_42 = asSInt(_put_acquire_legal_T_41) node _put_acquire_legal_T_43 = eq(_put_acquire_legal_T_42, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_44 = xor(_put_acquire_T, UInt<29>(0h10000000)) node _put_acquire_legal_T_45 = cvt(_put_acquire_legal_T_44) node _put_acquire_legal_T_46 = and(_put_acquire_legal_T_45, asSInt(UInt<33>(0h9a113000))) node _put_acquire_legal_T_47 = asSInt(_put_acquire_legal_T_46) node _put_acquire_legal_T_48 = eq(_put_acquire_legal_T_47, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_49 = xor(_put_acquire_T, UInt<32>(0h80000000)) node _put_acquire_legal_T_50 = cvt(_put_acquire_legal_T_49) node _put_acquire_legal_T_51 = and(_put_acquire_legal_T_50, asSInt(UInt<33>(0h90000000))) node _put_acquire_legal_T_52 = asSInt(_put_acquire_legal_T_51) node _put_acquire_legal_T_53 = eq(_put_acquire_legal_T_52, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_54 = or(_put_acquire_legal_T_18, _put_acquire_legal_T_23) node _put_acquire_legal_T_55 = or(_put_acquire_legal_T_54, _put_acquire_legal_T_28) node _put_acquire_legal_T_56 = or(_put_acquire_legal_T_55, _put_acquire_legal_T_33) node _put_acquire_legal_T_57 = or(_put_acquire_legal_T_56, _put_acquire_legal_T_38) node _put_acquire_legal_T_58 = or(_put_acquire_legal_T_57, _put_acquire_legal_T_43) node _put_acquire_legal_T_59 = or(_put_acquire_legal_T_58, _put_acquire_legal_T_48) node _put_acquire_legal_T_60 = or(_put_acquire_legal_T_59, _put_acquire_legal_T_53) node _put_acquire_legal_T_61 = and(_put_acquire_legal_T_13, _put_acquire_legal_T_60) node _put_acquire_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) node _put_acquire_legal_T_63 = xor(_put_acquire_T, UInt<17>(0h10000)) node _put_acquire_legal_T_64 = cvt(_put_acquire_legal_T_63) node _put_acquire_legal_T_65 = and(_put_acquire_legal_T_64, asSInt(UInt<33>(0h9a110000))) node _put_acquire_legal_T_66 = asSInt(_put_acquire_legal_T_65) node _put_acquire_legal_T_67 = eq(_put_acquire_legal_T_66, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_68 = and(_put_acquire_legal_T_62, _put_acquire_legal_T_67) node _put_acquire_legal_T_69 = or(UInt<1>(0h0), _put_acquire_legal_T_9) node _put_acquire_legal_T_70 = or(_put_acquire_legal_T_69, _put_acquire_legal_T_61) node put_acquire_legal = or(_put_acquire_legal_T_70, _put_acquire_legal_T_68) wire put_acquire : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect put_acquire.opcode, UInt<1>(0h1) connect put_acquire.param, UInt<1>(0h0) connect put_acquire.size, UInt<2>(0h3) connect put_acquire.source, UInt<1>(0h0) connect put_acquire.address, _put_acquire_T connect put_acquire.mask, wmask connect put_acquire.data, _put_acquire_T_1 connect put_acquire.corrupt, UInt<1>(0h0) node _get_acquire_T = cat(beatAddr, byteAddr) node _get_acquire_legal_T = leq(UInt<1>(0h0), rsize) node _get_acquire_legal_T_1 = leq(rsize, UInt<4>(0hc)) node _get_acquire_legal_T_2 = and(_get_acquire_legal_T, _get_acquire_legal_T_1) node _get_acquire_legal_T_3 = or(UInt<1>(0h0), _get_acquire_legal_T_2) node _get_acquire_legal_T_4 = xor(_get_acquire_T, UInt<14>(0h3000)) node _get_acquire_legal_T_5 = cvt(_get_acquire_legal_T_4) node _get_acquire_legal_T_6 = and(_get_acquire_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _get_acquire_legal_T_7 = asSInt(_get_acquire_legal_T_6) node _get_acquire_legal_T_8 = eq(_get_acquire_legal_T_7, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_9 = and(_get_acquire_legal_T_3, _get_acquire_legal_T_8) node _get_acquire_legal_T_10 = leq(UInt<1>(0h0), rsize) node _get_acquire_legal_T_11 = leq(rsize, UInt<3>(0h6)) node _get_acquire_legal_T_12 = and(_get_acquire_legal_T_10, _get_acquire_legal_T_11) node _get_acquire_legal_T_13 = or(UInt<1>(0h0), _get_acquire_legal_T_12) node _get_acquire_legal_T_14 = xor(_get_acquire_T, UInt<1>(0h0)) node _get_acquire_legal_T_15 = cvt(_get_acquire_legal_T_14) node _get_acquire_legal_T_16 = and(_get_acquire_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _get_acquire_legal_T_17 = asSInt(_get_acquire_legal_T_16) node _get_acquire_legal_T_18 = eq(_get_acquire_legal_T_17, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_19 = xor(_get_acquire_T, UInt<17>(0h10000)) node _get_acquire_legal_T_20 = cvt(_get_acquire_legal_T_19) node _get_acquire_legal_T_21 = and(_get_acquire_legal_T_20, asSInt(UInt<33>(0h98013000))) node _get_acquire_legal_T_22 = asSInt(_get_acquire_legal_T_21) node _get_acquire_legal_T_23 = eq(_get_acquire_legal_T_22, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_24 = xor(_get_acquire_T, UInt<17>(0h10000)) node _get_acquire_legal_T_25 = cvt(_get_acquire_legal_T_24) node _get_acquire_legal_T_26 = and(_get_acquire_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _get_acquire_legal_T_27 = asSInt(_get_acquire_legal_T_26) node _get_acquire_legal_T_28 = eq(_get_acquire_legal_T_27, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_29 = xor(_get_acquire_T, UInt<26>(0h2000000)) node _get_acquire_legal_T_30 = cvt(_get_acquire_legal_T_29) node _get_acquire_legal_T_31 = and(_get_acquire_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _get_acquire_legal_T_32 = asSInt(_get_acquire_legal_T_31) node _get_acquire_legal_T_33 = eq(_get_acquire_legal_T_32, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_34 = xor(_get_acquire_T, UInt<28>(0h8000000)) node _get_acquire_legal_T_35 = cvt(_get_acquire_legal_T_34) node _get_acquire_legal_T_36 = and(_get_acquire_legal_T_35, asSInt(UInt<33>(0h98000000))) node _get_acquire_legal_T_37 = asSInt(_get_acquire_legal_T_36) node _get_acquire_legal_T_38 = eq(_get_acquire_legal_T_37, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_39 = xor(_get_acquire_T, UInt<28>(0h8000000)) node _get_acquire_legal_T_40 = cvt(_get_acquire_legal_T_39) node _get_acquire_legal_T_41 = and(_get_acquire_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _get_acquire_legal_T_42 = asSInt(_get_acquire_legal_T_41) node _get_acquire_legal_T_43 = eq(_get_acquire_legal_T_42, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_44 = xor(_get_acquire_T, UInt<29>(0h10000000)) node _get_acquire_legal_T_45 = cvt(_get_acquire_legal_T_44) node _get_acquire_legal_T_46 = and(_get_acquire_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _get_acquire_legal_T_47 = asSInt(_get_acquire_legal_T_46) node _get_acquire_legal_T_48 = eq(_get_acquire_legal_T_47, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_49 = xor(_get_acquire_T, UInt<32>(0h80000000)) node _get_acquire_legal_T_50 = cvt(_get_acquire_legal_T_49) node _get_acquire_legal_T_51 = and(_get_acquire_legal_T_50, asSInt(UInt<33>(0h90000000))) node _get_acquire_legal_T_52 = asSInt(_get_acquire_legal_T_51) node _get_acquire_legal_T_53 = eq(_get_acquire_legal_T_52, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_54 = or(_get_acquire_legal_T_18, _get_acquire_legal_T_23) node _get_acquire_legal_T_55 = or(_get_acquire_legal_T_54, _get_acquire_legal_T_28) node _get_acquire_legal_T_56 = or(_get_acquire_legal_T_55, _get_acquire_legal_T_33) node _get_acquire_legal_T_57 = or(_get_acquire_legal_T_56, _get_acquire_legal_T_38) node _get_acquire_legal_T_58 = or(_get_acquire_legal_T_57, _get_acquire_legal_T_43) node _get_acquire_legal_T_59 = or(_get_acquire_legal_T_58, _get_acquire_legal_T_48) node _get_acquire_legal_T_60 = or(_get_acquire_legal_T_59, _get_acquire_legal_T_53) node _get_acquire_legal_T_61 = and(_get_acquire_legal_T_13, _get_acquire_legal_T_60) node _get_acquire_legal_T_62 = or(UInt<1>(0h0), _get_acquire_legal_T_9) node get_acquire_legal = or(_get_acquire_legal_T_62, _get_acquire_legal_T_61) wire get_acquire : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect get_acquire.opcode, UInt<3>(0h4) connect get_acquire.param, UInt<1>(0h0) connect get_acquire.size, rsize connect get_acquire.source, UInt<1>(0h0) connect get_acquire.address, _get_acquire_T node _get_acquire_a_mask_sizeOH_T = or(rsize, UInt<3>(0h0)) node get_acquire_a_mask_sizeOH_shiftAmount = bits(_get_acquire_a_mask_sizeOH_T, 1, 0) node _get_acquire_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), get_acquire_a_mask_sizeOH_shiftAmount) node _get_acquire_a_mask_sizeOH_T_2 = bits(_get_acquire_a_mask_sizeOH_T_1, 2, 0) node get_acquire_a_mask_sizeOH = or(_get_acquire_a_mask_sizeOH_T_2, UInt<1>(0h1)) node get_acquire_a_mask_sub_sub_sub_0_1 = geq(rsize, UInt<2>(0h3)) node get_acquire_a_mask_sub_sub_size = bits(get_acquire_a_mask_sizeOH, 2, 2) node get_acquire_a_mask_sub_sub_bit = bits(_get_acquire_T, 2, 2) node get_acquire_a_mask_sub_sub_nbit = eq(get_acquire_a_mask_sub_sub_bit, UInt<1>(0h0)) node get_acquire_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), get_acquire_a_mask_sub_sub_nbit) node _get_acquire_a_mask_sub_sub_acc_T = and(get_acquire_a_mask_sub_sub_size, get_acquire_a_mask_sub_sub_0_2) node get_acquire_a_mask_sub_sub_0_1 = or(get_acquire_a_mask_sub_sub_sub_0_1, _get_acquire_a_mask_sub_sub_acc_T) node get_acquire_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), get_acquire_a_mask_sub_sub_bit) node _get_acquire_a_mask_sub_sub_acc_T_1 = and(get_acquire_a_mask_sub_sub_size, get_acquire_a_mask_sub_sub_1_2) node get_acquire_a_mask_sub_sub_1_1 = or(get_acquire_a_mask_sub_sub_sub_0_1, _get_acquire_a_mask_sub_sub_acc_T_1) node get_acquire_a_mask_sub_size = bits(get_acquire_a_mask_sizeOH, 1, 1) node get_acquire_a_mask_sub_bit = bits(_get_acquire_T, 1, 1) node get_acquire_a_mask_sub_nbit = eq(get_acquire_a_mask_sub_bit, UInt<1>(0h0)) node get_acquire_a_mask_sub_0_2 = and(get_acquire_a_mask_sub_sub_0_2, get_acquire_a_mask_sub_nbit) node _get_acquire_a_mask_sub_acc_T = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_0_2) node get_acquire_a_mask_sub_0_1 = or(get_acquire_a_mask_sub_sub_0_1, _get_acquire_a_mask_sub_acc_T) node get_acquire_a_mask_sub_1_2 = and(get_acquire_a_mask_sub_sub_0_2, get_acquire_a_mask_sub_bit) node _get_acquire_a_mask_sub_acc_T_1 = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_1_2) node get_acquire_a_mask_sub_1_1 = or(get_acquire_a_mask_sub_sub_0_1, _get_acquire_a_mask_sub_acc_T_1) node get_acquire_a_mask_sub_2_2 = and(get_acquire_a_mask_sub_sub_1_2, get_acquire_a_mask_sub_nbit) node _get_acquire_a_mask_sub_acc_T_2 = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_2_2) node get_acquire_a_mask_sub_2_1 = or(get_acquire_a_mask_sub_sub_1_1, _get_acquire_a_mask_sub_acc_T_2) node get_acquire_a_mask_sub_3_2 = and(get_acquire_a_mask_sub_sub_1_2, get_acquire_a_mask_sub_bit) node _get_acquire_a_mask_sub_acc_T_3 = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_3_2) node get_acquire_a_mask_sub_3_1 = or(get_acquire_a_mask_sub_sub_1_1, _get_acquire_a_mask_sub_acc_T_3) node get_acquire_a_mask_size = bits(get_acquire_a_mask_sizeOH, 0, 0) node get_acquire_a_mask_bit = bits(_get_acquire_T, 0, 0) node get_acquire_a_mask_nbit = eq(get_acquire_a_mask_bit, UInt<1>(0h0)) node get_acquire_a_mask_eq = and(get_acquire_a_mask_sub_0_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T = and(get_acquire_a_mask_size, get_acquire_a_mask_eq) node get_acquire_a_mask_acc = or(get_acquire_a_mask_sub_0_1, _get_acquire_a_mask_acc_T) node get_acquire_a_mask_eq_1 = and(get_acquire_a_mask_sub_0_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_1 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_1) node get_acquire_a_mask_acc_1 = or(get_acquire_a_mask_sub_0_1, _get_acquire_a_mask_acc_T_1) node get_acquire_a_mask_eq_2 = and(get_acquire_a_mask_sub_1_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T_2 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_2) node get_acquire_a_mask_acc_2 = or(get_acquire_a_mask_sub_1_1, _get_acquire_a_mask_acc_T_2) node get_acquire_a_mask_eq_3 = and(get_acquire_a_mask_sub_1_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_3 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_3) node get_acquire_a_mask_acc_3 = or(get_acquire_a_mask_sub_1_1, _get_acquire_a_mask_acc_T_3) node get_acquire_a_mask_eq_4 = and(get_acquire_a_mask_sub_2_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T_4 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_4) node get_acquire_a_mask_acc_4 = or(get_acquire_a_mask_sub_2_1, _get_acquire_a_mask_acc_T_4) node get_acquire_a_mask_eq_5 = and(get_acquire_a_mask_sub_2_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_5 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_5) node get_acquire_a_mask_acc_5 = or(get_acquire_a_mask_sub_2_1, _get_acquire_a_mask_acc_T_5) node get_acquire_a_mask_eq_6 = and(get_acquire_a_mask_sub_3_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T_6 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_6) node get_acquire_a_mask_acc_6 = or(get_acquire_a_mask_sub_3_1, _get_acquire_a_mask_acc_T_6) node get_acquire_a_mask_eq_7 = and(get_acquire_a_mask_sub_3_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_7 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_7) node get_acquire_a_mask_acc_7 = or(get_acquire_a_mask_sub_3_1, _get_acquire_a_mask_acc_T_7) node get_acquire_a_mask_lo_lo = cat(get_acquire_a_mask_acc_1, get_acquire_a_mask_acc) node get_acquire_a_mask_lo_hi = cat(get_acquire_a_mask_acc_3, get_acquire_a_mask_acc_2) node get_acquire_a_mask_lo = cat(get_acquire_a_mask_lo_hi, get_acquire_a_mask_lo_lo) node get_acquire_a_mask_hi_lo = cat(get_acquire_a_mask_acc_5, get_acquire_a_mask_acc_4) node get_acquire_a_mask_hi_hi = cat(get_acquire_a_mask_acc_7, get_acquire_a_mask_acc_6) node get_acquire_a_mask_hi = cat(get_acquire_a_mask_hi_hi, get_acquire_a_mask_hi_lo) node _get_acquire_a_mask_T = cat(get_acquire_a_mask_hi, get_acquire_a_mask_lo) connect get_acquire.mask, _get_acquire_a_mask_T invalidate get_acquire.data connect get_acquire.corrupt, UInt<1>(0h0) node _nodeOut_a_valid_T = eq(state, UInt<4>(0h7)) node _nodeOut_a_valid_T_1 = eq(state, UInt<4>(0h3)) node _nodeOut_a_valid_T_2 = or(_nodeOut_a_valid_T, _nodeOut_a_valid_T_1) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 node _nodeOut_a_bits_T = eq(state, UInt<4>(0h7)) node _nodeOut_a_bits_T_1 = mux(_nodeOut_a_bits_T, put_acquire, get_acquire) connect nodeOut.a.bits, _nodeOut_a_bits_T_1 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.ready, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) node _nodeOut_d_ready_T = eq(state, UInt<4>(0h8)) node _nodeOut_d_ready_T_1 = eq(state, UInt<4>(0h4)) node _nodeOut_d_ready_T_2 = or(_nodeOut_d_ready_T, _nodeOut_d_ready_T_1) connect nodeOut.d.ready, _nodeOut_d_ready_T_2 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.valid, UInt<1>(0h0) node _T = eq(state, UInt<4>(0h0)) node _T_1 = and(_T, io.tsi.in.valid) when _T_1 : connect cmd, io.tsi.in.bits connect idx, UInt<1>(0h0) connect addr, UInt<1>(0h0) connect len, UInt<1>(0h0) connect state, UInt<4>(0h1) node _T_2 = eq(state, UInt<4>(0h1)) node _T_3 = and(_T_2, io.tsi.in.valid) when _T_3 : node _addr_T = bits(idx, 0, 0) node _addr_T_1 = cat(_addr_T, UInt<5>(0h0)) node _addr_T_2 = dshl(io.tsi.in.bits, _addr_T_1) node _addr_T_3 = or(addr, _addr_T_2) connect addr, _addr_T_3 node _idx_T = add(idx, UInt<1>(0h1)) node _idx_T_1 = tail(_idx_T, 1) connect idx, _idx_T_1 node _T_4 = eq(idx, UInt<1>(0h1)) when _T_4 : connect idx, UInt<1>(0h0) connect state, UInt<4>(0h2) node _T_5 = eq(state, UInt<4>(0h2)) node _T_6 = and(_T_5, io.tsi.in.valid) when _T_6 : node _len_T = bits(idx, 0, 0) node _len_T_1 = cat(_len_T, UInt<5>(0h0)) node _len_T_2 = dshl(io.tsi.in.bits, _len_T_1) node _len_T_3 = or(len, _len_T_2) connect len, _len_T_3 node _idx_T_2 = add(idx, UInt<1>(0h1)) node _idx_T_3 = tail(_idx_T_2, 1) connect idx, _idx_T_3 node _T_7 = eq(idx, UInt<1>(0h1)) when _T_7 : node _idx_T_4 = bits(addr, 2, 2) connect idx, _idx_T_4 node _T_8 = eq(cmd, UInt<1>(0h1)) when _T_8 : connect bodyValid, UInt<1>(0h0) connect state, UInt<4>(0h6) else : node _T_9 = eq(cmd, UInt<1>(0h0)) when _T_9 : connect state, UInt<4>(0h3) else : node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed: Bad TSI command\n at TSIToTileLink.scala:137 assert(false.B, \"Bad TSI command\")\n") : printf assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert node _T_13 = eq(state, UInt<4>(0h3)) node _T_14 = and(_T_13, nodeOut.a.ready) when _T_14 : connect state, UInt<4>(0h4) node _T_15 = eq(state, UInt<4>(0h4)) node _T_16 = and(_T_15, nodeOut.d.valid) when _T_16 : wire _WIRE_6 : UInt<32>[2] wire _WIRE_7 : UInt<64> connect _WIRE_7, nodeOut.d.bits.data node _T_17 = bits(_WIRE_7, 31, 0) connect _WIRE_6[0], _T_17 node _T_18 = bits(_WIRE_7, 63, 32) connect _WIRE_6[1], _T_18 connect body, _WIRE_6 node _idx_T_5 = bits(addr, 2, 2) connect idx, _idx_T_5 connect addr, nextAddr connect state, UInt<4>(0h5) node _T_19 = eq(state, UInt<4>(0h5)) node _T_20 = and(_T_19, io.tsi.out.ready) when _T_20 : node _idx_T_6 = add(idx, UInt<1>(0h1)) node _idx_T_7 = tail(_idx_T_6, 1) connect idx, _idx_T_7 node _len_T_4 = sub(len, UInt<1>(0h1)) node _len_T_5 = tail(_len_T_4, 1) connect len, _len_T_5 node _T_21 = eq(len, UInt<1>(0h0)) when _T_21 : connect state, UInt<4>(0h0) else : node _T_22 = eq(idx, UInt<1>(0h1)) when _T_22 : connect state, UInt<4>(0h3) node _T_23 = eq(state, UInt<4>(0h6)) node _T_24 = and(_T_23, io.tsi.in.valid) when _T_24 : connect body[idx], io.tsi.in.bits node _bodyValid_T = dshl(UInt<1>(0h1), idx) node _bodyValid_T_1 = or(bodyValid, _bodyValid_T) connect bodyValid, _bodyValid_T_1 node _T_25 = eq(idx, UInt<1>(0h1)) node _T_26 = eq(len, UInt<1>(0h0)) node _T_27 = or(_T_25, _T_26) when _T_27 : connect state, UInt<4>(0h7) else : node _idx_T_8 = add(idx, UInt<1>(0h1)) node _idx_T_9 = tail(_idx_T_8, 1) connect idx, _idx_T_9 node _len_T_6 = sub(len, UInt<1>(0h1)) node _len_T_7 = tail(_len_T_6, 1) connect len, _len_T_7 node _T_28 = eq(state, UInt<4>(0h7)) node _T_29 = and(_T_28, nodeOut.a.ready) when _T_29 : connect state, UInt<4>(0h8) node _T_30 = eq(state, UInt<4>(0h8)) node _T_31 = and(_T_30, nodeOut.d.valid) when _T_31 : node _T_32 = eq(len, UInt<1>(0h0)) when _T_32 : connect state, UInt<4>(0h0) else : connect addr, nextAddr node _len_T_8 = sub(len, UInt<1>(0h1)) node _len_T_9 = tail(_len_T_8, 1) connect len, _len_T_9 connect idx, UInt<1>(0h0) connect bodyValid, UInt<1>(0h0) connect state, UInt<4>(0h6) extmodule plusarg_reader_139 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_140 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TSIToTileLink( // @[TSIToTileLink.scala:36:7] input clock, // @[TSIToTileLink.scala:36:7] input reset, // @[TSIToTileLink.scala:36:7] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_tsi_in_ready, // @[TSIToTileLink.scala:37:14] input io_tsi_in_valid, // @[TSIToTileLink.scala:37:14] input [31:0] io_tsi_in_bits, // @[TSIToTileLink.scala:37:14] input io_tsi_out_ready, // @[TSIToTileLink.scala:37:14] output io_tsi_out_valid, // @[TSIToTileLink.scala:37:14] output [31:0] io_tsi_out_bits, // @[TSIToTileLink.scala:37:14] output [3:0] io_state // @[TSIToTileLink.scala:37:14] ); wire auto_out_a_ready_0 = auto_out_a_ready; // @[TSIToTileLink.scala:36:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[TSIToTileLink.scala:36:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[TSIToTileLink.scala:36:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[TSIToTileLink.scala:36:7] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[TSIToTileLink.scala:36:7] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[TSIToTileLink.scala:36:7] wire io_tsi_in_valid_0 = io_tsi_in_valid; // @[TSIToTileLink.scala:36:7] wire [31:0] io_tsi_in_bits_0 = io_tsi_in_bits; // @[TSIToTileLink.scala:36:7] wire io_tsi_out_ready_0 = io_tsi_out_ready; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_a_bits_param = 3'h0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] put_acquire_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] get_acquire_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] _nodeOut_a_bits_T_1_param = 3'h0; // @[TSIToTileLink.scala:95:20] wire auto_out_a_bits_source = 1'h0; // @[TSIToTileLink.scala:36:7] wire auto_out_a_bits_corrupt = 1'h0; // @[TSIToTileLink.scala:36:7] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire _put_acquire_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _put_acquire_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire put_acquire_source = 1'h0; // @[Edges.scala:500:17] wire put_acquire_corrupt = 1'h0; // @[Edges.scala:500:17] wire get_acquire_source = 1'h0; // @[Edges.scala:460:17] wire get_acquire_corrupt = 1'h0; // @[Edges.scala:460:17] wire _nodeOut_a_bits_T_1_source = 1'h0; // @[TSIToTileLink.scala:95:20] wire _nodeOut_a_bits_T_1_corrupt = 1'h0; // @[TSIToTileLink.scala:95:20] wire [63:0] get_acquire_data = 64'h0; // @[Edges.scala:460:17] wire [2:0] get_acquire_opcode = 3'h4; // @[Edges.scala:460:17] wire _put_acquire_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_acquire_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_acquire_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_acquire_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_acquire_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_acquire_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_acquire_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_acquire_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _get_acquire_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_acquire_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_acquire_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_acquire_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_acquire_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_acquire_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_acquire_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_acquire_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire [3:0] put_acquire_size = 4'h3; // @[Edges.scala:500:17] wire [2:0] put_acquire_opcode = 3'h1; // @[Edges.scala:500:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[TSIToTileLink.scala:36:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[TSIToTileLink.scala:36:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[TSIToTileLink.scala:36:7] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[TSIToTileLink.scala:36:7] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[TSIToTileLink.scala:36:7] wire _io_tsi_in_ready_T_6; // @[package.scala:81:59] wire _io_tsi_out_valid_T; // @[TSIToTileLink.scala:71:29] wire [2:0] auto_out_a_bits_opcode_0; // @[TSIToTileLink.scala:36:7] wire [3:0] auto_out_a_bits_size_0; // @[TSIToTileLink.scala:36:7] wire [31:0] auto_out_a_bits_address_0; // @[TSIToTileLink.scala:36:7] wire [7:0] auto_out_a_bits_mask_0; // @[TSIToTileLink.scala:36:7] wire [63:0] auto_out_a_bits_data_0; // @[TSIToTileLink.scala:36:7] wire auto_out_a_valid_0; // @[TSIToTileLink.scala:36:7] wire auto_out_d_ready_0; // @[TSIToTileLink.scala:36:7] wire io_tsi_in_ready_0; // @[TSIToTileLink.scala:36:7] wire io_tsi_out_valid_0; // @[TSIToTileLink.scala:36:7] wire [31:0] io_tsi_out_bits_0; // @[TSIToTileLink.scala:36:7] wire [3:0] io_state_0; // @[TSIToTileLink.scala:36:7] wire _nodeOut_a_valid_T_2; // @[package.scala:81:59] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[TSIToTileLink.scala:36:7] wire [2:0] _nodeOut_a_bits_T_1_opcode; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[TSIToTileLink.scala:36:7] wire [3:0] _nodeOut_a_bits_T_1_size; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[TSIToTileLink.scala:36:7] wire [31:0] _nodeOut_a_bits_T_1_address; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[TSIToTileLink.scala:36:7] wire [7:0] _nodeOut_a_bits_T_1_mask; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[TSIToTileLink.scala:36:7] wire [63:0] _nodeOut_a_bits_T_1_data; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[TSIToTileLink.scala:36:7] wire _nodeOut_d_ready_T_2; // @[package.scala:81:59] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[TSIToTileLink.scala:36:7] reg [31:0] cmd; // @[TSIToTileLink.scala:56:16] reg [63:0] addr; // @[TSIToTileLink.scala:57:17] reg [63:0] len; // @[TSIToTileLink.scala:58:16] reg [31:0] body_0; // @[TSIToTileLink.scala:59:17] reg [31:0] body_1; // @[TSIToTileLink.scala:59:17] reg [1:0] bodyValid; // @[TSIToTileLink.scala:60:22] reg idx; // @[TSIToTileLink.scala:61:16] wire _addr_T = idx; // @[TSIToTileLink.scala:61:16, :103:22] wire _len_T = idx; // @[TSIToTileLink.scala:61:16, :103:22] reg [3:0] state; // @[TSIToTileLink.scala:67:22] assign io_state_0 = state; // @[TSIToTileLink.scala:36:7, :67:22] wire _io_tsi_in_ready_T = state == 4'h0; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_1 = state == 4'h1; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_2 = state == 4'h2; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_3 = state == 4'h6; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_4 = _io_tsi_in_ready_T \| _io_tsi_in_ready_T_1; // @[package.scala:16:47, :81:59] wire _io_tsi_in_ready_T_5 = _io_tsi_in_ready_T_4 \| _io_tsi_in_ready_T_2; // @[package.scala:16:47, :81:59] assign _io_tsi_in_ready_T_6 = _io_tsi_in_ready_T_5 \| _io_tsi_in_ready_T_3; // @[package.scala:16:47, :81:59] assign io_tsi_in_ready_0 = _io_tsi_in_ready_T_6; // @[TSIToTileLink.scala:36:7] assign _io_tsi_out_valid_T = state == 4'h5; // @[TSIToTileLink.scala:67:22, :71:29] assign io_tsi_out_valid_0 = _io_tsi_out_valid_T; // @[TSIToTileLink.scala:36:7, :71:29] assign io_tsi_out_bits_0 = idx ? body_1 : body_0; // @[TSIToTileLink.scala:36:7, :59:17, :61:16, :72:19] wire [28:0] beatAddr = addr[31:3]; // @[TSIToTileLink.scala:57:17, :74:22] wire [29:0] _nextAddr_T = {1'h0, beatAddr} + 30'h1; // @[TSIToTileLink.scala:74:22, :75:31] wire [28:0] _nextAddr_T_1 = _nextAddr_T[28:0]; // @[TSIToTileLink.scala:75:31] wire [31:0] nextAddr = {_nextAddr_T_1, 3'h0}; // @[TSIToTileLink.scala:75:{21,31}] wire _wmask_T = bodyValid[0]; // @[TSIToTileLink.scala:60:22, :77:30] wire _wmask_T_1 = bodyValid[1]; // @[TSIToTileLink.scala:60:22, :77:30] wire [3:0] _wmask_T_2 = {4{_wmask_T}}; // @[TSIToTileLink.scala:77:30] wire [3:0] _wmask_T_3 = {4{_wmask_T_1}}; // @[TSIToTileLink.scala:77:30] wire [7:0] wmask = {_wmask_T_3, _wmask_T_2}; // @[TSIToTileLink.scala:77:30] wire [7:0] put_acquire_mask = wmask; // @[TSIToTileLink.scala:77:30] wire [64:0] _addr_size_T = {33'h0, nextAddr} - {1'h0, addr}; // @[TSIToTileLink.scala:57:17, :75:21, :78:28] wire [63:0] addr_size = _addr_size_T[63:0]; // @[TSIToTileLink.scala:78:28] wire [64:0] _GEN = {1'h0, len}; // @[TSIToTileLink.scala:58:16, :79:26] wire [64:0] _len_size_T = _GEN + 65'h1; // @[TSIToTileLink.scala:79:26] wire [63:0] _len_size_T_1 = _len_size_T[63:0]; // @[TSIToTileLink.scala:79:26] wire [65:0] len_size = {_len_size_T_1, 2'h0}; // @[TSIToTileLink.scala:79:{21,26}] wire [65:0] _GEN_0 = {2'h0, addr_size}; // @[TSIToTileLink.scala:78:28, :80:31] wire _raw_size_T = len_size < _GEN_0; // @[TSIToTileLink.scala:79:21, :80:31] wire [65:0] raw_size = _raw_size_T ? len_size : _GEN_0; // @[TSIToTileLink.scala:79:21, :80:{21,31}] wire _rsize_T = raw_size == 66'h1; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] _rsize_T_1 = _rsize_T ? 2'h0 : 2'h3; // @[TSIToTileLink.scala:81:50] wire _rsize_T_2 = raw_size == 66'h2; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] _rsize_T_3 = _rsize_T_2 ? 2'h1 : _rsize_T_1; // @[TSIToTileLink.scala:81:50] wire _rsize_T_4 = raw_size == 66'h4; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] rsize = _rsize_T_4 ? 2'h2 : _rsize_T_3; // @[TSIToTileLink.scala:81:50] wire _pow2size_T = raw_size[0]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_1 = raw_size[1]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_2 = raw_size[2]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_3 = raw_size[3]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_4 = raw_size[4]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_5 = raw_size[5]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_6 = raw_size[6]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_7 = raw_size[7]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_8 = raw_size[8]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_9 = raw_size[9]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_10 = raw_size[10]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_11 = raw_size[11]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_12 = raw_size[12]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_13 = raw_size[13]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_14 = raw_size[14]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_15 = raw_size[15]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_16 = raw_size[16]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_17 = raw_size[17]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_18 = raw_size[18]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_19 = raw_size[19]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_20 = raw_size[20]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_21 = raw_size[21]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_22 = raw_size[22]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_23 = raw_size[23]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_24 = raw_size[24]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_25 = raw_size[25]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_26 = raw_size[26]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_27 = raw_size[27]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_28 = raw_size[28]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_29 = raw_size[29]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_30 = raw_size[30]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_31 = raw_size[31]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_32 = raw_size[32]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_33 = raw_size[33]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_34 = raw_size[34]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_35 = raw_size[35]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_36 = raw_size[36]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_37 = raw_size[37]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_38 = raw_size[38]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_39 = raw_size[39]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_40 = raw_size[40]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_41 = raw_size[41]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_42 = raw_size[42]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_43 = raw_size[43]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_44 = raw_size[44]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_45 = raw_size[45]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_46 = raw_size[46]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_47 = raw_size[47]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_48 = raw_size[48]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_49 = raw_size[49]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_50 = raw_size[50]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_51 = raw_size[51]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_52 = raw_size[52]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_53 = raw_size[53]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_54 = raw_size[54]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_55 = raw_size[55]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_56 = raw_size[56]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_57 = raw_size[57]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_58 = raw_size[58]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_59 = raw_size[59]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_60 = raw_size[60]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_61 = raw_size[61]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_62 = raw_size[62]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_63 = raw_size[63]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_64 = raw_size[64]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_65 = raw_size[65]; // @[TSIToTileLink.scala:80:21, :84:26] wire [1:0] _pow2size_T_66 = {1'h0, _pow2size_T} + {1'h0, _pow2size_T_1}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_67 = _pow2size_T_66; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_68 = {1'h0, _pow2size_T_2} + {1'h0, _pow2size_T_3}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_69 = _pow2size_T_68; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_70 = {1'h0, _pow2size_T_67} + {1'h0, _pow2size_T_69}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_71 = _pow2size_T_70; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_72 = {1'h0, _pow2size_T_4} + {1'h0, _pow2size_T_5}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_73 = _pow2size_T_72; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_74 = {1'h0, _pow2size_T_6} + {1'h0, _pow2size_T_7}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_75 = _pow2size_T_74; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_76 = {1'h0, _pow2size_T_73} + {1'h0, _pow2size_T_75}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_77 = _pow2size_T_76; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_78 = {1'h0, _pow2size_T_71} + {1'h0, _pow2size_T_77}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_79 = _pow2size_T_78; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_80 = {1'h0, _pow2size_T_8} + {1'h0, _pow2size_T_9}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_81 = _pow2size_T_80; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_82 = {1'h0, _pow2size_T_10} + {1'h0, _pow2size_T_11}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_83 = _pow2size_T_82; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_84 = {1'h0, _pow2size_T_81} + {1'h0, _pow2size_T_83}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_85 = _pow2size_T_84; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_86 = {1'h0, _pow2size_T_12} + {1'h0, _pow2size_T_13}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_87 = _pow2size_T_86; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_88 = {1'h0, _pow2size_T_14} + {1'h0, _pow2size_T_15}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_89 = _pow2size_T_88; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_90 = {1'h0, _pow2size_T_87} + {1'h0, _pow2size_T_89}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_91 = _pow2size_T_90; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_92 = {1'h0, _pow2size_T_85} + {1'h0, _pow2size_T_91}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_93 = _pow2size_T_92; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_94 = {1'h0, _pow2size_T_79} + {1'h0, _pow2size_T_93}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_95 = _pow2size_T_94; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_96 = {1'h0, _pow2size_T_16} + {1'h0, _pow2size_T_17}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_97 = _pow2size_T_96; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_98 = {1'h0, _pow2size_T_18} + {1'h0, _pow2size_T_19}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_99 = _pow2size_T_98; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_100 = {1'h0, _pow2size_T_97} + {1'h0, _pow2size_T_99}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_101 = _pow2size_T_100; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_102 = {1'h0, _pow2size_T_20} + {1'h0, _pow2size_T_21}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_103 = _pow2size_T_102; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_104 = {1'h0, _pow2size_T_22} + {1'h0, _pow2size_T_23}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_105 = _pow2size_T_104; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_106 = {1'h0, _pow2size_T_103} + {1'h0, _pow2size_T_105}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_107 = _pow2size_T_106; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_108 = {1'h0, _pow2size_T_101} + {1'h0, _pow2size_T_107}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_109 = _pow2size_T_108; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_110 = {1'h0, _pow2size_T_24} + {1'h0, _pow2size_T_25}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_111 = _pow2size_T_110; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_112 = {1'h0, _pow2size_T_26} + {1'h0, _pow2size_T_27}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_113 = _pow2size_T_112; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_114 = {1'h0, _pow2size_T_111} + {1'h0, _pow2size_T_113}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_115 = _pow2size_T_114; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_116 = {1'h0, _pow2size_T_28} + {1'h0, _pow2size_T_29}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_117 = _pow2size_T_116; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_118 = {1'h0, _pow2size_T_31} + {1'h0, _pow2size_T_32}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_119 = _pow2size_T_118; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_120 = {2'h0, _pow2size_T_30} + {1'h0, _pow2size_T_119}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_121 = _pow2size_T_120[1:0]; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_122 = {1'h0, _pow2size_T_117} + {1'h0, _pow2size_T_121}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_123 = _pow2size_T_122; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_124 = {1'h0, _pow2size_T_115} + {1'h0, _pow2size_T_123}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_125 = _pow2size_T_124; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_126 = {1'h0, _pow2size_T_109} + {1'h0, _pow2size_T_125}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_127 = _pow2size_T_126; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_128 = {1'h0, _pow2size_T_95} + {1'h0, _pow2size_T_127}; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_129 = _pow2size_T_128; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_130 = {1'h0, _pow2size_T_33} + {1'h0, _pow2size_T_34}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_131 = _pow2size_T_130; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_132 = {1'h0, _pow2size_T_35} + {1'h0, _pow2size_T_36}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_133 = _pow2size_T_132; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_134 = {1'h0, _pow2size_T_131} + {1'h0, _pow2size_T_133}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_135 = _pow2size_T_134; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_136 = {1'h0, _pow2size_T_37} + {1'h0, _pow2size_T_38}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_137 = _pow2size_T_136; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_138 = {1'h0, _pow2size_T_39} + {1'h0, _pow2size_T_40}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_139 = _pow2size_T_138; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_140 = {1'h0, _pow2size_T_137} + {1'h0, _pow2size_T_139}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_141 = _pow2size_T_140; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_142 = {1'h0, _pow2size_T_135} + {1'h0, _pow2size_T_141}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_143 = _pow2size_T_142; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_144 = {1'h0, _pow2size_T_41} + {1'h0, _pow2size_T_42}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_145 = _pow2size_T_144; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_146 = {1'h0, _pow2size_T_43} + {1'h0, _pow2size_T_44}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_147 = _pow2size_T_146; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_148 = {1'h0, _pow2size_T_145} + {1'h0, _pow2size_T_147}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_149 = _pow2size_T_148; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_150 = {1'h0, _pow2size_T_45} + {1'h0, _pow2size_T_46}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_151 = _pow2size_T_150; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_152 = {1'h0, _pow2size_T_47} + {1'h0, _pow2size_T_48}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_153 = _pow2size_T_152; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_154 = {1'h0, _pow2size_T_151} + {1'h0, _pow2size_T_153}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_155 = _pow2size_T_154; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_156 = {1'h0, _pow2size_T_149} + {1'h0, _pow2size_T_155}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_157 = _pow2size_T_156; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_158 = {1'h0, _pow2size_T_143} + {1'h0, _pow2size_T_157}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_159 = _pow2size_T_158; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_160 = {1'h0, _pow2size_T_49} + {1'h0, _pow2size_T_50}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_161 = _pow2size_T_160; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_162 = {1'h0, _pow2size_T_51} + {1'h0, _pow2size_T_52}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_163 = _pow2size_T_162; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_164 = {1'h0, _pow2size_T_161} + {1'h0, _pow2size_T_163}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_165 = _pow2size_T_164; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_166 = {1'h0, _pow2size_T_53} + {1'h0, _pow2size_T_54}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_167 = _pow2size_T_166; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_168 = {1'h0, _pow2size_T_55} + {1'h0, _pow2size_T_56}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_169 = _pow2size_T_168; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_170 = {1'h0, _pow2size_T_167} + {1'h0, _pow2size_T_169}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_171 = _pow2size_T_170; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_172 = {1'h0, _pow2size_T_165} + {1'h0, _pow2size_T_171}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_173 = _pow2size_T_172; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_174 = {1'h0, _pow2size_T_57} + {1'h0, _pow2size_T_58}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_175 = _pow2size_T_174; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_176 = {1'h0, _pow2size_T_59} + {1'h0, _pow2size_T_60}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_177 = _pow2size_T_176; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_178 = {1'h0, _pow2size_T_175} + {1'h0, _pow2size_T_177}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_179 = _pow2size_T_178; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_180 = {1'h0, _pow2size_T_61} + {1'h0, _pow2size_T_62}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_181 = _pow2size_T_180; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_182 = {1'h0, _pow2size_T_64} + {1'h0, _pow2size_T_65}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_183 = _pow2size_T_182; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_184 = {2'h0, _pow2size_T_63} + {1'h0, _pow2size_T_183}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_185 = _pow2size_T_184[1:0]; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_186 = {1'h0, _pow2size_T_181} + {1'h0, _pow2size_T_185}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_187 = _pow2size_T_186; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_188 = {1'h0, _pow2size_T_179} + {1'h0, _pow2size_T_187}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_189 = _pow2size_T_188; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_190 = {1'h0, _pow2size_T_173} + {1'h0, _pow2size_T_189}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_191 = _pow2size_T_190; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_192 = {1'h0, _pow2size_T_159} + {1'h0, _pow2size_T_191}; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_193 = _pow2size_T_192; // @[TSIToTileLink.scala:84:26] wire [6:0] _pow2size_T_194 = {1'h0, _pow2size_T_129} + {1'h0, _pow2size_T_193}; // @[TSIToTileLink.scala:84:26] wire [6:0] _pow2size_T_195 = _pow2size_T_194; // @[TSIToTileLink.scala:84:26] wire pow2size = _pow2size_T_195 == 7'h1; // @[TSIToTileLink.scala:84:{26,37}] wire [2:0] _byteAddr_T = addr[2:0]; // @[TSIToTileLink.scala:57:17, :85:36] wire [2:0] byteAddr = pow2size ? _byteAddr_T : 3'h0; // @[TSIToTileLink.scala:84:37, :85:{21,36}] wire [31:0] _put_acquire_T = {beatAddr, 3'h0}; // @[TSIToTileLink.scala:74:22, :88:19] wire [31:0] _put_acquire_legal_T_14 = _put_acquire_T; // @[TSIToTileLink.scala:88:19] wire [31:0] put_acquire_address = _put_acquire_T; // @[TSIToTileLink.scala:88:19] wire [63:0] _put_acquire_T_1 = {body_1, body_0}; // @[TSIToTileLink.scala:59:17, :89:10] wire [63:0] put_acquire_data = _put_acquire_T_1; // @[TSIToTileLink.scala:89:10] wire [31:0] _put_acquire_legal_T_4 = {_put_acquire_T[31:14], _put_acquire_T[13:0] ^ 14'h3000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_5 = {1'h0, _put_acquire_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_6 = _put_acquire_legal_T_5 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_7 = _put_acquire_legal_T_6; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_8 = _put_acquire_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_9 = _put_acquire_legal_T_8; // @[Parameters.scala:684:54] wire _put_acquire_legal_T_69 = _put_acquire_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _put_acquire_legal_T_15 = {1'h0, _put_acquire_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_16 = _put_acquire_legal_T_15 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_17 = _put_acquire_legal_T_16; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_18 = _put_acquire_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_19 = {_put_acquire_T[31:21], _put_acquire_T[20:0] ^ 21'h100000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_20 = {1'h0, _put_acquire_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_21 = _put_acquire_legal_T_20 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_22 = _put_acquire_legal_T_21; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_23 = _put_acquire_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_24 = {_put_acquire_T[31:26], _put_acquire_T[25:0] ^ 26'h2000000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_25 = {1'h0, _put_acquire_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_26 = _put_acquire_legal_T_25 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_27 = _put_acquire_legal_T_26; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_28 = _put_acquire_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_29 = {_put_acquire_T[31:26], _put_acquire_T[25:0] ^ 26'h2010000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_30 = {1'h0, _put_acquire_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_31 = _put_acquire_legal_T_30 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_32 = _put_acquire_legal_T_31; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_33 = _put_acquire_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_1 = {_put_acquire_T[31:28], _put_acquire_T[27:0] ^ 28'h8000000}; // @[TSIToTileLink.scala:88:19] wire [31:0] _put_acquire_legal_T_34; // @[Parameters.scala:137:31] assign _put_acquire_legal_T_34 = _GEN_1; // @[Parameters.scala:137:31] wire [31:0] _put_acquire_legal_T_39; // @[Parameters.scala:137:31] assign _put_acquire_legal_T_39 = _GEN_1; // @[Parameters.scala:137:31] wire [32:0] _put_acquire_legal_T_35 = {1'h0, _put_acquire_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_36 = _put_acquire_legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_37 = _put_acquire_legal_T_36; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_38 = _put_acquire_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _put_acquire_legal_T_40 = {1'h0, _put_acquire_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_41 = _put_acquire_legal_T_40 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_42 = _put_acquire_legal_T_41; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_43 = _put_acquire_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_44 = {_put_acquire_T[31:29], _put_acquire_T[28:0] ^ 29'h10000000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_45 = {1'h0, _put_acquire_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_46 = _put_acquire_legal_T_45 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_47 = _put_acquire_legal_T_46; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_48 = _put_acquire_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_49 = _put_acquire_T ^ 32'h80000000; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_50 = {1'h0, _put_acquire_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_51 = _put_acquire_legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_52 = _put_acquire_legal_T_51; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_53 = _put_acquire_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_54 = _put_acquire_legal_T_18 \| _put_acquire_legal_T_23; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_55 = _put_acquire_legal_T_54 \| _put_acquire_legal_T_28; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_56 = _put_acquire_legal_T_55 \| _put_acquire_legal_T_33; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_57 = _put_acquire_legal_T_56 \| _put_acquire_legal_T_38; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_58 = _put_acquire_legal_T_57 \| _put_acquire_legal_T_43; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_59 = _put_acquire_legal_T_58 \| _put_acquire_legal_T_48; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_60 = _put_acquire_legal_T_59 \| _put_acquire_legal_T_53; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_61 = _put_acquire_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [31:0] _put_acquire_legal_T_63 = {_put_acquire_T[31:17], _put_acquire_T[16:0] ^ 17'h10000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_64 = {1'h0, _put_acquire_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_65 = _put_acquire_legal_T_64 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_66 = _put_acquire_legal_T_65; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_67 = _put_acquire_legal_T_66 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_70 = _put_acquire_legal_T_69 \| _put_acquire_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire put_acquire_legal = _put_acquire_legal_T_70; // @[Parameters.scala:686:26] wire [31:0] _get_acquire_T = {beatAddr, byteAddr}; // @[TSIToTileLink.scala:74:22, :85:21, :92:13] wire [31:0] _get_acquire_legal_T_14 = _get_acquire_T; // @[TSIToTileLink.scala:92:13] wire [31:0] get_acquire_address = _get_acquire_T; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_4 = {_get_acquire_T[31:14], _get_acquire_T[13:0] ^ 14'h3000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_5 = {1'h0, _get_acquire_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_6 = _get_acquire_legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_7 = _get_acquire_legal_T_6; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_8 = _get_acquire_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _get_acquire_legal_T_9 = _get_acquire_legal_T_8; // @[Parameters.scala:684:54] wire _get_acquire_legal_T_62 = _get_acquire_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _get_acquire_legal_T_15 = {1'h0, _get_acquire_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_16 = _get_acquire_legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_17 = _get_acquire_legal_T_16; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_18 = _get_acquire_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_2 = {_get_acquire_T[31:17], _get_acquire_T[16:0] ^ 17'h10000}; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_19; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_19 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _get_acquire_legal_T_24; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _get_acquire_legal_T_20 = {1'h0, _get_acquire_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_21 = _get_acquire_legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_22 = _get_acquire_legal_T_21; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_23 = _get_acquire_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _get_acquire_legal_T_25 = {1'h0, _get_acquire_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_26 = _get_acquire_legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_27 = _get_acquire_legal_T_26; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_28 = _get_acquire_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_29 = {_get_acquire_T[31:26], _get_acquire_T[25:0] ^ 26'h2000000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_30 = {1'h0, _get_acquire_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_31 = _get_acquire_legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_32 = _get_acquire_legal_T_31; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_33 = _get_acquire_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_3 = {_get_acquire_T[31:28], _get_acquire_T[27:0] ^ 28'h8000000}; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_34; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_34 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _get_acquire_legal_T_39; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [32:0] _get_acquire_legal_T_35 = {1'h0, _get_acquire_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_36 = _get_acquire_legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_37 = _get_acquire_legal_T_36; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_38 = _get_acquire_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _get_acquire_legal_T_40 = {1'h0, _get_acquire_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_41 = _get_acquire_legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_42 = _get_acquire_legal_T_41; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_43 = _get_acquire_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_44 = {_get_acquire_T[31:29], _get_acquire_T[28:0] ^ 29'h10000000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_45 = {1'h0, _get_acquire_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_46 = _get_acquire_legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_47 = _get_acquire_legal_T_46; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_48 = _get_acquire_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_49 = _get_acquire_T ^ 32'h80000000; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_50 = {1'h0, _get_acquire_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_51 = _get_acquire_legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_52 = _get_acquire_legal_T_51; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_53 = _get_acquire_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _get_acquire_legal_T_54 = _get_acquire_legal_T_18 \| _get_acquire_legal_T_23; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_55 = _get_acquire_legal_T_54 \| _get_acquire_legal_T_28; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_56 = _get_acquire_legal_T_55 \| _get_acquire_legal_T_33; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_57 = _get_acquire_legal_T_56 \| _get_acquire_legal_T_38; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_58 = _get_acquire_legal_T_57 \| _get_acquire_legal_T_43; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_59 = _get_acquire_legal_T_58 \| _get_acquire_legal_T_48; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_60 = _get_acquire_legal_T_59 \| _get_acquire_legal_T_53; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_61 = _get_acquire_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire get_acquire_legal = _get_acquire_legal_T_62 \| _get_acquire_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_acquire_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_acquire_size; // @[Edges.scala:460:17] wire [7:0] get_acquire_mask; // @[Edges.scala:460:17] assign get_acquire_size = {2'h0, rsize}; // @[TSIToTileLink.scala:81:50] wire [2:0] _get_acquire_a_mask_sizeOH_T = {1'h0, rsize}; // @[TSIToTileLink.scala:81:50] wire [1:0] get_acquire_a_mask_sizeOH_shiftAmount = _get_acquire_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_acquire_a_mask_sizeOH_T_1 = 4'h1 << get_acquire_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_acquire_a_mask_sizeOH_T_2 = _get_acquire_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_acquire_a_mask_sizeOH = {_get_acquire_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_acquire_a_mask_sub_sub_sub_0_1 = &rsize; // @[TSIToTileLink.scala:81:50] wire get_acquire_a_mask_sub_sub_size = get_acquire_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_sub_sub_bit = _get_acquire_T[2]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_sub_sub_1_2 = get_acquire_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_acquire_a_mask_sub_sub_nbit = ~get_acquire_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_sub_sub_0_2 = get_acquire_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_sub_acc_T = get_acquire_a_mask_sub_sub_size & get_acquire_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_sub_0_1 = get_acquire_a_mask_sub_sub_sub_0_1 \| _get_acquire_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_acquire_a_mask_sub_sub_acc_T_1 = get_acquire_a_mask_sub_sub_size & get_acquire_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_sub_1_1 = get_acquire_a_mask_sub_sub_sub_0_1 \| _get_acquire_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_acquire_a_mask_sub_size = get_acquire_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_sub_bit = _get_acquire_T[1]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_sub_nbit = ~get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_sub_0_2 = get_acquire_a_mask_sub_sub_0_2 & get_acquire_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_acc_T = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_0_1 = get_acquire_a_mask_sub_sub_0_1 \| _get_acquire_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_1_2 = get_acquire_a_mask_sub_sub_0_2 & get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_sub_acc_T_1 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_1_1 = get_acquire_a_mask_sub_sub_0_1 \| _get_acquire_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_2_2 = get_acquire_a_mask_sub_sub_1_2 & get_acquire_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_acc_T_2 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_2_1 = get_acquire_a_mask_sub_sub_1_1 \| _get_acquire_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_3_2 = get_acquire_a_mask_sub_sub_1_2 & get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_sub_acc_T_3 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_3_1 = get_acquire_a_mask_sub_sub_1_1 \| _get_acquire_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_size = get_acquire_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_bit = _get_acquire_T[0]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_nbit = ~get_acquire_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_eq = get_acquire_a_mask_sub_0_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T = get_acquire_a_mask_size & get_acquire_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc = get_acquire_a_mask_sub_0_1 \| _get_acquire_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_1 = get_acquire_a_mask_sub_0_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_1 = get_acquire_a_mask_size & get_acquire_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_1 = get_acquire_a_mask_sub_0_1 \| _get_acquire_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_2 = get_acquire_a_mask_sub_1_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_2 = get_acquire_a_mask_size & get_acquire_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_2 = get_acquire_a_mask_sub_1_1 \| _get_acquire_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_3 = get_acquire_a_mask_sub_1_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_3 = get_acquire_a_mask_size & get_acquire_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_3 = get_acquire_a_mask_sub_1_1 \| _get_acquire_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_4 = get_acquire_a_mask_sub_2_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_4 = get_acquire_a_mask_size & get_acquire_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_4 = get_acquire_a_mask_sub_2_1 \| _get_acquire_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_5 = get_acquire_a_mask_sub_2_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_5 = get_acquire_a_mask_size & get_acquire_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_5 = get_acquire_a_mask_sub_2_1 \| _get_acquire_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_6 = get_acquire_a_mask_sub_3_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_6 = get_acquire_a_mask_size & get_acquire_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_6 = get_acquire_a_mask_sub_3_1 \| _get_acquire_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_7 = get_acquire_a_mask_sub_3_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_7 = get_acquire_a_mask_size & get_acquire_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_7 = get_acquire_a_mask_sub_3_1 \| _get_acquire_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_acquire_a_mask_lo_lo = {get_acquire_a_mask_acc_1, get_acquire_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_acquire_a_mask_lo_hi = {get_acquire_a_mask_acc_3, get_acquire_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_acquire_a_mask_lo = {get_acquire_a_mask_lo_hi, get_acquire_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_acquire_a_mask_hi_lo = {get_acquire_a_mask_acc_5, get_acquire_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_acquire_a_mask_hi_hi = {get_acquire_a_mask_acc_7, get_acquire_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_acquire_a_mask_hi = {get_acquire_a_mask_hi_hi, get_acquire_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_acquire_a_mask_T = {get_acquire_a_mask_hi, get_acquire_a_mask_lo}; // @[Misc.scala:222:10] assign get_acquire_mask = _get_acquire_a_mask_T; // @[Misc.scala:222:10] wire _T_28 = state == 4'h7; // @[TSIToTileLink.scala:67:22] wire _nodeOut_a_valid_T; // @[package.scala:16:47] assign _nodeOut_a_valid_T = _T_28; // @[package.scala:16:47] wire _nodeOut_a_bits_T; // @[TSIToTileLink.scala:95:27] assign _nodeOut_a_bits_T = _T_28; // @[TSIToTileLink.scala:95:27] wire _nodeOut_a_valid_T_1 = state == 4'h3; // @[TSIToTileLink.scala:67:22] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T \| _nodeOut_a_valid_T_1; // @[package.scala:16:47, :81:59] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[package.scala:81:59] assign _nodeOut_a_bits_T_1_opcode = _nodeOut_a_bits_T ? 3'h1 : 3'h4; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_size = _nodeOut_a_bits_T ? 4'h3 : get_acquire_size; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_address = _nodeOut_a_bits_T ? put_acquire_address : get_acquire_address; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_mask = _nodeOut_a_bits_T ? put_acquire_mask : get_acquire_mask; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_data = _nodeOut_a_bits_T ? put_acquire_data : 64'h0; // @[TSIToTileLink.scala:95:{20,27}] assign nodeOut_a_bits_opcode = _nodeOut_a_bits_T_1_opcode; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_size = _nodeOut_a_bits_T_1_size; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_address = _nodeOut_a_bits_T_1_address; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_mask = _nodeOut_a_bits_T_1_mask; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_data = _nodeOut_a_bits_T_1_data; // @[TSIToTileLink.scala:95:20] wire _nodeOut_d_ready_T = state == 4'h8; // @[TSIToTileLink.scala:67:22] wire _nodeOut_d_ready_T_1 = state == 4'h4; // @[TSIToTileLink.scala:67:22] assign _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T \| _nodeOut_d_ready_T_1; // @[package.scala:16:47, :81:59] assign nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[package.scala:81:59] wire [5:0] _addr_T_1 = {_addr_T, 5'h0}; // @[TSIToTileLink.scala:103:{18,22}] wire [94:0] _GEN_4 = {63'h0, io_tsi_in_bits_0}; // @[TSIToTileLink.scala:36:7, :103:12] wire [94:0] _addr_T_2 = _GEN_4 << _addr_T_1; // @[TSIToTileLink.scala:103:{12,18}] wire [94:0] _addr_T_3 = {31'h0, addr} \| _addr_T_2; // @[TSIToTileLink.scala:57:17, :103:12, :118:18] wire [1:0] _GEN_5 = {1'h0, idx}; // @[TSIToTileLink.scala:61:16, :119:16] wire [1:0] _GEN_6 = _GEN_5 + 2'h1; // @[TSIToTileLink.scala:119:16] wire [1:0] _idx_T; // @[TSIToTileLink.scala:119:16] assign _idx_T = _GEN_6; // @[TSIToTileLink.scala:119:16] wire [1:0] _idx_T_2; // @[TSIToTileLink.scala:128:16] assign _idx_T_2 = _GEN_6; // @[TSIToTileLink.scala:119:16, :128:16] wire [1:0] _idx_T_6; // @[TSIToTileLink.scala:154:16] assign _idx_T_6 = _GEN_6; // @[TSIToTileLink.scala:119:16, :154:16] wire [1:0] _idx_T_8; // @[TSIToTileLink.scala:166:18] assign _idx_T_8 = _GEN_6; // @[TSIToTileLink.scala:119:16, :166:18] wire _idx_T_1 = _idx_T[0]; // @[TSIToTileLink.scala:119:16] wire _T_6 = _io_tsi_in_ready_T_2 & io_tsi_in_valid_0; // @[TSIToTileLink.scala:36:7, :126:25] wire [5:0] _len_T_1 = {_len_T, 5'h0}; // @[TSIToTileLink.scala:103:{18,22}] wire [94:0] _len_T_2 = _GEN_4 << _len_T_1; // @[TSIToTileLink.scala:103:{12,18}] wire [94:0] _len_T_3 = {31'h0, len} \| _len_T_2; // @[TSIToTileLink.scala:58:16, :103:12, :127:16] wire _idx_T_3 = _idx_T_2[0]; // @[TSIToTileLink.scala:128:16] wire _GEN_7 = _T_6 & idx; // @[TSIToTileLink.scala:61:16, :126:25, :129:43] wire _idx_T_4 = addr[2]; // @[TSIToTileLink.scala:57:17, :107:33] wire _idx_T_5 = addr[2]; // @[TSIToTileLink.scala:57:17, :107:33]
Generate the Verilog code corresponding to this FIRRTL code module TSIToTileLink : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { tsi : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}}, state : UInt} wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut reg cmd : UInt<32>, clock reg addr : UInt<64>, clock reg len : UInt<64>, clock reg body : UInt<32>[2], clock reg bodyValid : UInt<2>, clock reg idx : UInt<1>, clock regreset state : UInt<4>, clock, reset, UInt<4>(0h0) connect io.state, state node _io_tsi_in_ready_T = eq(state, UInt<4>(0h0)) node _io_tsi_in_ready_T_1 = eq(state, UInt<4>(0h1)) node _io_tsi_in_ready_T_2 = eq(state, UInt<4>(0h2)) node _io_tsi_in_ready_T_3 = eq(state, UInt<4>(0h6)) node _io_tsi_in_ready_T_4 = or(_io_tsi_in_ready_T, _io_tsi_in_ready_T_1) node _io_tsi_in_ready_T_5 = or(_io_tsi_in_ready_T_4, _io_tsi_in_ready_T_2) node _io_tsi_in_ready_T_6 = or(_io_tsi_in_ready_T_5, _io_tsi_in_ready_T_3) connect io.tsi.in.ready, _io_tsi_in_ready_T_6 node _io_tsi_out_valid_T = eq(state, UInt<4>(0h5)) connect io.tsi.out.valid, _io_tsi_out_valid_T connect io.tsi.out.bits, body[idx] node beatAddr = bits(addr, 31, 3) node _nextAddr_T = add(beatAddr, UInt<1>(0h1)) node _nextAddr_T_1 = tail(_nextAddr_T, 1) node nextAddr = cat(_nextAddr_T_1, UInt<3>(0h0)) node _wmask_T = bits(bodyValid, 0, 0) node _wmask_T_1 = bits(bodyValid, 1, 1) node _wmask_T_2 = mux(_wmask_T, UInt<4>(0hf), UInt<4>(0h0)) node _wmask_T_3 = mux(_wmask_T_1, UInt<4>(0hf), UInt<4>(0h0)) node wmask = cat(_wmask_T_3, _wmask_T_2) node _addr_size_T = sub(nextAddr, addr) node addr_size = tail(_addr_size_T, 1) node _len_size_T = add(len, UInt<1>(0h1)) node _len_size_T_1 = tail(_len_size_T, 1) node len_size = cat(_len_size_T_1, UInt<2>(0h0)) node _raw_size_T = lt(len_size, addr_size) node raw_size = mux(_raw_size_T, len_size, addr_size) node _rsize_T = eq(UInt<1>(0h1), raw_size) node _rsize_T_1 = mux(_rsize_T, UInt<1>(0h0), UInt<2>(0h3)) node _rsize_T_2 = eq(UInt<2>(0h2), raw_size) node _rsize_T_3 = mux(_rsize_T_2, UInt<1>(0h1), _rsize_T_1) node _rsize_T_4 = eq(UInt<3>(0h4), raw_size) node rsize = mux(_rsize_T_4, UInt<2>(0h2), _rsize_T_3) node _pow2size_T = bits(raw_size, 0, 0) node _pow2size_T_1 = bits(raw_size, 1, 1) node _pow2size_T_2 = bits(raw_size, 2, 2) node _pow2size_T_3 = bits(raw_size, 3, 3) node _pow2size_T_4 = bits(raw_size, 4, 4) node _pow2size_T_5 = bits(raw_size, 5, 5) node _pow2size_T_6 = bits(raw_size, 6, 6) node _pow2size_T_7 = bits(raw_size, 7, 7) node _pow2size_T_8 = bits(raw_size, 8, 8) node _pow2size_T_9 = bits(raw_size, 9, 9) node _pow2size_T_10 = bits(raw_size, 10, 10) node _pow2size_T_11 = bits(raw_size, 11, 11) node _pow2size_T_12 = bits(raw_size, 12, 12) node _pow2size_T_13 = bits(raw_size, 13, 13) node _pow2size_T_14 = bits(raw_size, 14, 14) node _pow2size_T_15 = bits(raw_size, 15, 15) node _pow2size_T_16 = bits(raw_size, 16, 16) node _pow2size_T_17 = bits(raw_size, 17, 17) node _pow2size_T_18 = bits(raw_size, 18, 18) node _pow2size_T_19 = bits(raw_size, 19, 19) node _pow2size_T_20 = bits(raw_size, 20, 20) node _pow2size_T_21 = bits(raw_size, 21, 21) node _pow2size_T_22 = bits(raw_size, 22, 22) node _pow2size_T_23 = bits(raw_size, 23, 23) node _pow2size_T_24 = bits(raw_size, 24, 24) node _pow2size_T_25 = bits(raw_size, 25, 25) node _pow2size_T_26 = bits(raw_size, 26, 26) node _pow2size_T_27 = bits(raw_size, 27, 27) node _pow2size_T_28 = bits(raw_size, 28, 28) node _pow2size_T_29 = bits(raw_size, 29, 29) node _pow2size_T_30 = bits(raw_size, 30, 30) node _pow2size_T_31 = bits(raw_size, 31, 31) node _pow2size_T_32 = bits(raw_size, 32, 32) node _pow2size_T_33 = bits(raw_size, 33, 33) node _pow2size_T_34 = bits(raw_size, 34, 34) node _pow2size_T_35 = bits(raw_size, 35, 35) node _pow2size_T_36 = bits(raw_size, 36, 36) node _pow2size_T_37 = bits(raw_size, 37, 37) node _pow2size_T_38 = bits(raw_size, 38, 38) node _pow2size_T_39 = bits(raw_size, 39, 39) node _pow2size_T_40 = bits(raw_size, 40, 40) node _pow2size_T_41 = bits(raw_size, 41, 41) node _pow2size_T_42 = bits(raw_size, 42, 42) node _pow2size_T_43 = bits(raw_size, 43, 43) node _pow2size_T_44 = bits(raw_size, 44, 44) node _pow2size_T_45 = bits(raw_size, 45, 45) node _pow2size_T_46 = bits(raw_size, 46, 46) node _pow2size_T_47 = bits(raw_size, 47, 47) node _pow2size_T_48 = bits(raw_size, 48, 48) node _pow2size_T_49 = bits(raw_size, 49, 49) node _pow2size_T_50 = bits(raw_size, 50, 50) node _pow2size_T_51 = bits(raw_size, 51, 51) node _pow2size_T_52 = bits(raw_size, 52, 52) node _pow2size_T_53 = bits(raw_size, 53, 53) node _pow2size_T_54 = bits(raw_size, 54, 54) node _pow2size_T_55 = bits(raw_size, 55, 55) node _pow2size_T_56 = bits(raw_size, 56, 56) node _pow2size_T_57 = bits(raw_size, 57, 57) node _pow2size_T_58 = bits(raw_size, 58, 58) node _pow2size_T_59 = bits(raw_size, 59, 59) node _pow2size_T_60 = bits(raw_size, 60, 60) node _pow2size_T_61 = bits(raw_size, 61, 61) node _pow2size_T_62 = bits(raw_size, 62, 62) node _pow2size_T_63 = bits(raw_size, 63, 63) node _pow2size_T_64 = bits(raw_size, 64, 64) node _pow2size_T_65 = bits(raw_size, 65, 65) node _pow2size_T_66 = add(_pow2size_T, _pow2size_T_1) node _pow2size_T_67 = bits(_pow2size_T_66, 1, 0) node _pow2size_T_68 = add(_pow2size_T_2, _pow2size_T_3) node _pow2size_T_69 = bits(_pow2size_T_68, 1, 0) node _pow2size_T_70 = add(_pow2size_T_67, _pow2size_T_69) node _pow2size_T_71 = bits(_pow2size_T_70, 2, 0) node _pow2size_T_72 = add(_pow2size_T_4, _pow2size_T_5) node _pow2size_T_73 = bits(_pow2size_T_72, 1, 0) node _pow2size_T_74 = add(_pow2size_T_6, _pow2size_T_7) node _pow2size_T_75 = bits(_pow2size_T_74, 1, 0) node _pow2size_T_76 = add(_pow2size_T_73, _pow2size_T_75) node _pow2size_T_77 = bits(_pow2size_T_76, 2, 0) node _pow2size_T_78 = add(_pow2size_T_71, _pow2size_T_77) node _pow2size_T_79 = bits(_pow2size_T_78, 3, 0) node _pow2size_T_80 = add(_pow2size_T_8, _pow2size_T_9) node _pow2size_T_81 = bits(_pow2size_T_80, 1, 0) node _pow2size_T_82 = add(_pow2size_T_10, _pow2size_T_11) node _pow2size_T_83 = bits(_pow2size_T_82, 1, 0) node _pow2size_T_84 = add(_pow2size_T_81, _pow2size_T_83) node _pow2size_T_85 = bits(_pow2size_T_84, 2, 0) node _pow2size_T_86 = add(_pow2size_T_12, _pow2size_T_13) node _pow2size_T_87 = bits(_pow2size_T_86, 1, 0) node _pow2size_T_88 = add(_pow2size_T_14, _pow2size_T_15) node _pow2size_T_89 = bits(_pow2size_T_88, 1, 0) node _pow2size_T_90 = add(_pow2size_T_87, _pow2size_T_89) node _pow2size_T_91 = bits(_pow2size_T_90, 2, 0) node _pow2size_T_92 = add(_pow2size_T_85, _pow2size_T_91) node _pow2size_T_93 = bits(_pow2size_T_92, 3, 0) node _pow2size_T_94 = add(_pow2size_T_79, _pow2size_T_93) node _pow2size_T_95 = bits(_pow2size_T_94, 4, 0) node _pow2size_T_96 = add(_pow2size_T_16, _pow2size_T_17) node _pow2size_T_97 = bits(_pow2size_T_96, 1, 0) node _pow2size_T_98 = add(_pow2size_T_18, _pow2size_T_19) node _pow2size_T_99 = bits(_pow2size_T_98, 1, 0) node _pow2size_T_100 = add(_pow2size_T_97, _pow2size_T_99) node _pow2size_T_101 = bits(_pow2size_T_100, 2, 0) node _pow2size_T_102 = add(_pow2size_T_20, _pow2size_T_21) node _pow2size_T_103 = bits(_pow2size_T_102, 1, 0) node _pow2size_T_104 = add(_pow2size_T_22, _pow2size_T_23) node _pow2size_T_105 = bits(_pow2size_T_104, 1, 0) node _pow2size_T_106 = add(_pow2size_T_103, _pow2size_T_105) node _pow2size_T_107 = bits(_pow2size_T_106, 2, 0) node _pow2size_T_108 = add(_pow2size_T_101, _pow2size_T_107) node _pow2size_T_109 = bits(_pow2size_T_108, 3, 0) node _pow2size_T_110 = add(_pow2size_T_24, _pow2size_T_25) node _pow2size_T_111 = bits(_pow2size_T_110, 1, 0) node _pow2size_T_112 = add(_pow2size_T_26, _pow2size_T_27) node _pow2size_T_113 = bits(_pow2size_T_112, 1, 0) node _pow2size_T_114 = add(_pow2size_T_111, _pow2size_T_113) node _pow2size_T_115 = bits(_pow2size_T_114, 2, 0) node _pow2size_T_116 = add(_pow2size_T_28, _pow2size_T_29) node _pow2size_T_117 = bits(_pow2size_T_116, 1, 0) node _pow2size_T_118 = add(_pow2size_T_31, _pow2size_T_32) node _pow2size_T_119 = bits(_pow2size_T_118, 1, 0) node _pow2size_T_120 = add(_pow2size_T_30, _pow2size_T_119) node _pow2size_T_121 = bits(_pow2size_T_120, 1, 0) node _pow2size_T_122 = add(_pow2size_T_117, _pow2size_T_121) node _pow2size_T_123 = bits(_pow2size_T_122, 2, 0) node _pow2size_T_124 = add(_pow2size_T_115, _pow2size_T_123) node _pow2size_T_125 = bits(_pow2size_T_124, 3, 0) node _pow2size_T_126 = add(_pow2size_T_109, _pow2size_T_125) node _pow2size_T_127 = bits(_pow2size_T_126, 4, 0) node _pow2size_T_128 = add(_pow2size_T_95, _pow2size_T_127) node _pow2size_T_129 = bits(_pow2size_T_128, 5, 0) node _pow2size_T_130 = add(_pow2size_T_33, _pow2size_T_34) node _pow2size_T_131 = bits(_pow2size_T_130, 1, 0) node _pow2size_T_132 = add(_pow2size_T_35, _pow2size_T_36) node _pow2size_T_133 = bits(_pow2size_T_132, 1, 0) node _pow2size_T_134 = add(_pow2size_T_131, _pow2size_T_133) node _pow2size_T_135 = bits(_pow2size_T_134, 2, 0) node _pow2size_T_136 = add(_pow2size_T_37, _pow2size_T_38) node _pow2size_T_137 = bits(_pow2size_T_136, 1, 0) node _pow2size_T_138 = add(_pow2size_T_39, _pow2size_T_40) node _pow2size_T_139 = bits(_pow2size_T_138, 1, 0) node _pow2size_T_140 = add(_pow2size_T_137, _pow2size_T_139) node _pow2size_T_141 = bits(_pow2size_T_140, 2, 0) node _pow2size_T_142 = add(_pow2size_T_135, _pow2size_T_141) node _pow2size_T_143 = bits(_pow2size_T_142, 3, 0) node _pow2size_T_144 = add(_pow2size_T_41, _pow2size_T_42) node _pow2size_T_145 = bits(_pow2size_T_144, 1, 0) node _pow2size_T_146 = add(_pow2size_T_43, _pow2size_T_44) node _pow2size_T_147 = bits(_pow2size_T_146, 1, 0) node _pow2size_T_148 = add(_pow2size_T_145, _pow2size_T_147) node _pow2size_T_149 = bits(_pow2size_T_148, 2, 0) node _pow2size_T_150 = add(_pow2size_T_45, _pow2size_T_46) node _pow2size_T_151 = bits(_pow2size_T_150, 1, 0) node _pow2size_T_152 = add(_pow2size_T_47, _pow2size_T_48) node _pow2size_T_153 = bits(_pow2size_T_152, 1, 0) node _pow2size_T_154 = add(_pow2size_T_151, _pow2size_T_153) node _pow2size_T_155 = bits(_pow2size_T_154, 2, 0) node _pow2size_T_156 = add(_pow2size_T_149, _pow2size_T_155) node _pow2size_T_157 = bits(_pow2size_T_156, 3, 0) node _pow2size_T_158 = add(_pow2size_T_143, _pow2size_T_157) node _pow2size_T_159 = bits(_pow2size_T_158, 4, 0) node _pow2size_T_160 = add(_pow2size_T_49, _pow2size_T_50) node _pow2size_T_161 = bits(_pow2size_T_160, 1, 0) node _pow2size_T_162 = add(_pow2size_T_51, _pow2size_T_52) node _pow2size_T_163 = bits(_pow2size_T_162, 1, 0) node _pow2size_T_164 = add(_pow2size_T_161, _pow2size_T_163) node _pow2size_T_165 = bits(_pow2size_T_164, 2, 0) node _pow2size_T_166 = add(_pow2size_T_53, _pow2size_T_54) node _pow2size_T_167 = bits(_pow2size_T_166, 1, 0) node _pow2size_T_168 = add(_pow2size_T_55, _pow2size_T_56) node _pow2size_T_169 = bits(_pow2size_T_168, 1, 0) node _pow2size_T_170 = add(_pow2size_T_167, _pow2size_T_169) node _pow2size_T_171 = bits(_pow2size_T_170, 2, 0) node _pow2size_T_172 = add(_pow2size_T_165, _pow2size_T_171) node _pow2size_T_173 = bits(_pow2size_T_172, 3, 0) node _pow2size_T_174 = add(_pow2size_T_57, _pow2size_T_58) node _pow2size_T_175 = bits(_pow2size_T_174, 1, 0) node _pow2size_T_176 = add(_pow2size_T_59, _pow2size_T_60) node _pow2size_T_177 = bits(_pow2size_T_176, 1, 0) node _pow2size_T_178 = add(_pow2size_T_175, _pow2size_T_177) node _pow2size_T_179 = bits(_pow2size_T_178, 2, 0) node _pow2size_T_180 = add(_pow2size_T_61, _pow2size_T_62) node _pow2size_T_181 = bits(_pow2size_T_180, 1, 0) node _pow2size_T_182 = add(_pow2size_T_64, _pow2size_T_65) node _pow2size_T_183 = bits(_pow2size_T_182, 1, 0) node _pow2size_T_184 = add(_pow2size_T_63, _pow2size_T_183) node _pow2size_T_185 = bits(_pow2size_T_184, 1, 0) node _pow2size_T_186 = add(_pow2size_T_181, _pow2size_T_185) node _pow2size_T_187 = bits(_pow2size_T_186, 2, 0) node _pow2size_T_188 = add(_pow2size_T_179, _pow2size_T_187) node _pow2size_T_189 = bits(_pow2size_T_188, 3, 0) node _pow2size_T_190 = add(_pow2size_T_173, _pow2size_T_189) node _pow2size_T_191 = bits(_pow2size_T_190, 4, 0) node _pow2size_T_192 = add(_pow2size_T_159, _pow2size_T_191) node _pow2size_T_193 = bits(_pow2size_T_192, 5, 0) node _pow2size_T_194 = add(_pow2size_T_129, _pow2size_T_193) node _pow2size_T_195 = bits(_pow2size_T_194, 6, 0) node pow2size = eq(_pow2size_T_195, UInt<1>(0h1)) node _byteAddr_T = bits(addr, 2, 0) node byteAddr = mux(pow2size, _byteAddr_T, UInt<1>(0h0)) node _put_acquire_T = dshl(beatAddr, UInt<2>(0h3)) node _put_acquire_T_1 = cat(body[1], body[0]) node _put_acquire_legal_T = leq(UInt<1>(0h0), UInt<2>(0h3)) node _put_acquire_legal_T_1 = leq(UInt<2>(0h3), UInt<4>(0hc)) node _put_acquire_legal_T_2 = and(_put_acquire_legal_T, _put_acquire_legal_T_1) node _put_acquire_legal_T_3 = or(UInt<1>(0h0), _put_acquire_legal_T_2) node _put_acquire_legal_T_4 = xor(_put_acquire_T, UInt<14>(0h3000)) node _put_acquire_legal_T_5 = cvt(_put_acquire_legal_T_4) node _put_acquire_legal_T_6 = and(_put_acquire_legal_T_5, asSInt(UInt<33>(0hffffb000))) node _put_acquire_legal_T_7 = asSInt(_put_acquire_legal_T_6) node _put_acquire_legal_T_8 = eq(_put_acquire_legal_T_7, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_9 = and(_put_acquire_legal_T_3, _put_acquire_legal_T_8) node _put_acquire_legal_T_10 = leq(UInt<1>(0h0), UInt<2>(0h3)) node _put_acquire_legal_T_11 = leq(UInt<2>(0h3), UInt<3>(0h6)) node _put_acquire_legal_T_12 = and(_put_acquire_legal_T_10, _put_acquire_legal_T_11) node _put_acquire_legal_T_13 = or(UInt<1>(0h0), _put_acquire_legal_T_12) node _put_acquire_legal_T_14 = xor(_put_acquire_T, UInt<1>(0h0)) node _put_acquire_legal_T_15 = cvt(_put_acquire_legal_T_14) node _put_acquire_legal_T_16 = and(_put_acquire_legal_T_15, asSInt(UInt<33>(0hffffa000))) node _put_acquire_legal_T_17 = asSInt(_put_acquire_legal_T_16) node _put_acquire_legal_T_18 = eq(_put_acquire_legal_T_17, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_19 = xor(_put_acquire_T, UInt<21>(0h100000)) node _put_acquire_legal_T_20 = cvt(_put_acquire_legal_T_19) node _put_acquire_legal_T_21 = and(_put_acquire_legal_T_20, asSInt(UInt<33>(0hfffeb000))) node _put_acquire_legal_T_22 = asSInt(_put_acquire_legal_T_21) node _put_acquire_legal_T_23 = eq(_put_acquire_legal_T_22, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_24 = xor(_put_acquire_T, UInt<26>(0h2000000)) node _put_acquire_legal_T_25 = cvt(_put_acquire_legal_T_24) node _put_acquire_legal_T_26 = and(_put_acquire_legal_T_25, asSInt(UInt<33>(0hffff0000))) node _put_acquire_legal_T_27 = asSInt(_put_acquire_legal_T_26) node _put_acquire_legal_T_28 = eq(_put_acquire_legal_T_27, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_29 = xor(_put_acquire_T, UInt<26>(0h2010000)) node _put_acquire_legal_T_30 = cvt(_put_acquire_legal_T_29) node _put_acquire_legal_T_31 = and(_put_acquire_legal_T_30, asSInt(UInt<33>(0hffffb000))) node _put_acquire_legal_T_32 = asSInt(_put_acquire_legal_T_31) node _put_acquire_legal_T_33 = eq(_put_acquire_legal_T_32, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_34 = xor(_put_acquire_T, UInt<28>(0h8000000)) node _put_acquire_legal_T_35 = cvt(_put_acquire_legal_T_34) node _put_acquire_legal_T_36 = and(_put_acquire_legal_T_35, asSInt(UInt<33>(0hffff0000))) node _put_acquire_legal_T_37 = asSInt(_put_acquire_legal_T_36) node _put_acquire_legal_T_38 = eq(_put_acquire_legal_T_37, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_39 = xor(_put_acquire_T, UInt<28>(0hc000000)) node _put_acquire_legal_T_40 = cvt(_put_acquire_legal_T_39) node _put_acquire_legal_T_41 = and(_put_acquire_legal_T_40, asSInt(UInt<33>(0hfc000000))) node _put_acquire_legal_T_42 = asSInt(_put_acquire_legal_T_41) node _put_acquire_legal_T_43 = eq(_put_acquire_legal_T_42, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_44 = xor(_put_acquire_T, UInt<29>(0h10020000)) node _put_acquire_legal_T_45 = cvt(_put_acquire_legal_T_44) node _put_acquire_legal_T_46 = and(_put_acquire_legal_T_45, asSInt(UInt<33>(0hffffb000))) node _put_acquire_legal_T_47 = asSInt(_put_acquire_legal_T_46) node _put_acquire_legal_T_48 = eq(_put_acquire_legal_T_47, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_49 = xor(_put_acquire_T, UInt<32>(0h80000000)) node _put_acquire_legal_T_50 = cvt(_put_acquire_legal_T_49) node _put_acquire_legal_T_51 = and(_put_acquire_legal_T_50, asSInt(UInt<33>(0hf0000000))) node _put_acquire_legal_T_52 = asSInt(_put_acquire_legal_T_51) node _put_acquire_legal_T_53 = eq(_put_acquire_legal_T_52, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_54 = or(_put_acquire_legal_T_18, _put_acquire_legal_T_23) node _put_acquire_legal_T_55 = or(_put_acquire_legal_T_54, _put_acquire_legal_T_28) node _put_acquire_legal_T_56 = or(_put_acquire_legal_T_55, _put_acquire_legal_T_33) node _put_acquire_legal_T_57 = or(_put_acquire_legal_T_56, _put_acquire_legal_T_38) node _put_acquire_legal_T_58 = or(_put_acquire_legal_T_57, _put_acquire_legal_T_43) node _put_acquire_legal_T_59 = or(_put_acquire_legal_T_58, _put_acquire_legal_T_48) node _put_acquire_legal_T_60 = or(_put_acquire_legal_T_59, _put_acquire_legal_T_53) node _put_acquire_legal_T_61 = and(_put_acquire_legal_T_13, _put_acquire_legal_T_60) node _put_acquire_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) node _put_acquire_legal_T_63 = xor(_put_acquire_T, UInt<17>(0h10000)) node _put_acquire_legal_T_64 = cvt(_put_acquire_legal_T_63) node _put_acquire_legal_T_65 = and(_put_acquire_legal_T_64, asSInt(UInt<33>(0hffff0000))) node _put_acquire_legal_T_66 = asSInt(_put_acquire_legal_T_65) node _put_acquire_legal_T_67 = eq(_put_acquire_legal_T_66, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_68 = and(_put_acquire_legal_T_62, _put_acquire_legal_T_67) node _put_acquire_legal_T_69 = leq(UInt<1>(0h0), UInt<2>(0h3)) node _put_acquire_legal_T_70 = leq(UInt<2>(0h3), UInt<2>(0h3)) node _put_acquire_legal_T_71 = and(_put_acquire_legal_T_69, _put_acquire_legal_T_70) node _put_acquire_legal_T_72 = or(UInt<1>(0h0), _put_acquire_legal_T_71) node _put_acquire_legal_T_73 = xor(_put_acquire_T, UInt<18>(0h20000)) node _put_acquire_legal_T_74 = cvt(_put_acquire_legal_T_73) node _put_acquire_legal_T_75 = and(_put_acquire_legal_T_74, asSInt(UInt<33>(0hffff8000))) node _put_acquire_legal_T_76 = asSInt(_put_acquire_legal_T_75) node _put_acquire_legal_T_77 = eq(_put_acquire_legal_T_76, asSInt(UInt<1>(0h0))) node _put_acquire_legal_T_78 = and(_put_acquire_legal_T_72, _put_acquire_legal_T_77) node _put_acquire_legal_T_79 = or(UInt<1>(0h0), _put_acquire_legal_T_9) node _put_acquire_legal_T_80 = or(_put_acquire_legal_T_79, _put_acquire_legal_T_61) node _put_acquire_legal_T_81 = or(_put_acquire_legal_T_80, _put_acquire_legal_T_68) node put_acquire_legal = or(_put_acquire_legal_T_81, _put_acquire_legal_T_78) wire put_acquire : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect put_acquire.opcode, UInt<1>(0h1) connect put_acquire.param, UInt<1>(0h0) connect put_acquire.size, UInt<2>(0h3) connect put_acquire.source, UInt<1>(0h0) connect put_acquire.address, _put_acquire_T connect put_acquire.mask, wmask connect put_acquire.data, _put_acquire_T_1 connect put_acquire.corrupt, UInt<1>(0h0) node _get_acquire_T = cat(beatAddr, byteAddr) node _get_acquire_legal_T = leq(UInt<1>(0h0), rsize) node _get_acquire_legal_T_1 = leq(rsize, UInt<4>(0hc)) node _get_acquire_legal_T_2 = and(_get_acquire_legal_T, _get_acquire_legal_T_1) node _get_acquire_legal_T_3 = or(UInt<1>(0h0), _get_acquire_legal_T_2) node _get_acquire_legal_T_4 = xor(_get_acquire_T, UInt<14>(0h3000)) node _get_acquire_legal_T_5 = cvt(_get_acquire_legal_T_4) node _get_acquire_legal_T_6 = and(_get_acquire_legal_T_5, asSInt(UInt<33>(0hffefb000))) node _get_acquire_legal_T_7 = asSInt(_get_acquire_legal_T_6) node _get_acquire_legal_T_8 = eq(_get_acquire_legal_T_7, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_9 = and(_get_acquire_legal_T_3, _get_acquire_legal_T_8) node _get_acquire_legal_T_10 = leq(UInt<1>(0h0), rsize) node _get_acquire_legal_T_11 = leq(rsize, UInt<3>(0h6)) node _get_acquire_legal_T_12 = and(_get_acquire_legal_T_10, _get_acquire_legal_T_11) node _get_acquire_legal_T_13 = or(UInt<1>(0h0), _get_acquire_legal_T_12) node _get_acquire_legal_T_14 = xor(_get_acquire_T, UInt<1>(0h0)) node _get_acquire_legal_T_15 = cvt(_get_acquire_legal_T_14) node _get_acquire_legal_T_16 = and(_get_acquire_legal_T_15, asSInt(UInt<33>(0hffefa000))) node _get_acquire_legal_T_17 = asSInt(_get_acquire_legal_T_16) node _get_acquire_legal_T_18 = eq(_get_acquire_legal_T_17, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_19 = xor(_get_acquire_T, UInt<17>(0h10000)) node _get_acquire_legal_T_20 = cvt(_get_acquire_legal_T_19) node _get_acquire_legal_T_21 = and(_get_acquire_legal_T_20, asSInt(UInt<33>(0hfdefb000))) node _get_acquire_legal_T_22 = asSInt(_get_acquire_legal_T_21) node _get_acquire_legal_T_23 = eq(_get_acquire_legal_T_22, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_24 = xor(_get_acquire_T, UInt<17>(0h10000)) node _get_acquire_legal_T_25 = cvt(_get_acquire_legal_T_24) node _get_acquire_legal_T_26 = and(_get_acquire_legal_T_25, asSInt(UInt<33>(0hffef0000))) node _get_acquire_legal_T_27 = asSInt(_get_acquire_legal_T_26) node _get_acquire_legal_T_28 = eq(_get_acquire_legal_T_27, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_29 = xor(_get_acquire_T, UInt<26>(0h2000000)) node _get_acquire_legal_T_30 = cvt(_get_acquire_legal_T_29) node _get_acquire_legal_T_31 = and(_get_acquire_legal_T_30, asSInt(UInt<33>(0hffef0000))) node _get_acquire_legal_T_32 = asSInt(_get_acquire_legal_T_31) node _get_acquire_legal_T_33 = eq(_get_acquire_legal_T_32, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_34 = xor(_get_acquire_T, UInt<28>(0h8000000)) node _get_acquire_legal_T_35 = cvt(_get_acquire_legal_T_34) node _get_acquire_legal_T_36 = and(_get_acquire_legal_T_35, asSInt(UInt<33>(0hffef0000))) node _get_acquire_legal_T_37 = asSInt(_get_acquire_legal_T_36) node _get_acquire_legal_T_38 = eq(_get_acquire_legal_T_37, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_39 = xor(_get_acquire_T, UInt<28>(0hc000000)) node _get_acquire_legal_T_40 = cvt(_get_acquire_legal_T_39) node _get_acquire_legal_T_41 = and(_get_acquire_legal_T_40, asSInt(UInt<33>(0hfc000000))) node _get_acquire_legal_T_42 = asSInt(_get_acquire_legal_T_41) node _get_acquire_legal_T_43 = eq(_get_acquire_legal_T_42, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_44 = xor(_get_acquire_T, UInt<29>(0h10020000)) node _get_acquire_legal_T_45 = cvt(_get_acquire_legal_T_44) node _get_acquire_legal_T_46 = and(_get_acquire_legal_T_45, asSInt(UInt<33>(0hffefb000))) node _get_acquire_legal_T_47 = asSInt(_get_acquire_legal_T_46) node _get_acquire_legal_T_48 = eq(_get_acquire_legal_T_47, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_49 = xor(_get_acquire_T, UInt<32>(0h80000000)) node _get_acquire_legal_T_50 = cvt(_get_acquire_legal_T_49) node _get_acquire_legal_T_51 = and(_get_acquire_legal_T_50, asSInt(UInt<33>(0hf0000000))) node _get_acquire_legal_T_52 = asSInt(_get_acquire_legal_T_51) node _get_acquire_legal_T_53 = eq(_get_acquire_legal_T_52, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_54 = or(_get_acquire_legal_T_18, _get_acquire_legal_T_23) node _get_acquire_legal_T_55 = or(_get_acquire_legal_T_54, _get_acquire_legal_T_28) node _get_acquire_legal_T_56 = or(_get_acquire_legal_T_55, _get_acquire_legal_T_33) node _get_acquire_legal_T_57 = or(_get_acquire_legal_T_56, _get_acquire_legal_T_38) node _get_acquire_legal_T_58 = or(_get_acquire_legal_T_57, _get_acquire_legal_T_43) node _get_acquire_legal_T_59 = or(_get_acquire_legal_T_58, _get_acquire_legal_T_48) node _get_acquire_legal_T_60 = or(_get_acquire_legal_T_59, _get_acquire_legal_T_53) node _get_acquire_legal_T_61 = and(_get_acquire_legal_T_13, _get_acquire_legal_T_60) node _get_acquire_legal_T_62 = leq(UInt<1>(0h0), rsize) node _get_acquire_legal_T_63 = leq(rsize, UInt<2>(0h3)) node _get_acquire_legal_T_64 = and(_get_acquire_legal_T_62, _get_acquire_legal_T_63) node _get_acquire_legal_T_65 = or(UInt<1>(0h0), _get_acquire_legal_T_64) node _get_acquire_legal_T_66 = xor(_get_acquire_T, UInt<18>(0h20000)) node _get_acquire_legal_T_67 = cvt(_get_acquire_legal_T_66) node _get_acquire_legal_T_68 = and(_get_acquire_legal_T_67, asSInt(UInt<33>(0hffef8000))) node _get_acquire_legal_T_69 = asSInt(_get_acquire_legal_T_68) node _get_acquire_legal_T_70 = eq(_get_acquire_legal_T_69, asSInt(UInt<1>(0h0))) node _get_acquire_legal_T_71 = and(_get_acquire_legal_T_65, _get_acquire_legal_T_70) node _get_acquire_legal_T_72 = or(UInt<1>(0h0), _get_acquire_legal_T_9) node _get_acquire_legal_T_73 = or(_get_acquire_legal_T_72, _get_acquire_legal_T_61) node get_acquire_legal = or(_get_acquire_legal_T_73, _get_acquire_legal_T_71) wire get_acquire : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect get_acquire.opcode, UInt<3>(0h4) connect get_acquire.param, UInt<1>(0h0) connect get_acquire.size, rsize connect get_acquire.source, UInt<1>(0h0) connect get_acquire.address, _get_acquire_T node _get_acquire_a_mask_sizeOH_T = or(rsize, UInt<3>(0h0)) node get_acquire_a_mask_sizeOH_shiftAmount = bits(_get_acquire_a_mask_sizeOH_T, 1, 0) node _get_acquire_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), get_acquire_a_mask_sizeOH_shiftAmount) node _get_acquire_a_mask_sizeOH_T_2 = bits(_get_acquire_a_mask_sizeOH_T_1, 2, 0) node get_acquire_a_mask_sizeOH = or(_get_acquire_a_mask_sizeOH_T_2, UInt<1>(0h1)) node get_acquire_a_mask_sub_sub_sub_0_1 = geq(rsize, UInt<2>(0h3)) node get_acquire_a_mask_sub_sub_size = bits(get_acquire_a_mask_sizeOH, 2, 2) node get_acquire_a_mask_sub_sub_bit = bits(_get_acquire_T, 2, 2) node get_acquire_a_mask_sub_sub_nbit = eq(get_acquire_a_mask_sub_sub_bit, UInt<1>(0h0)) node get_acquire_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), get_acquire_a_mask_sub_sub_nbit) node _get_acquire_a_mask_sub_sub_acc_T = and(get_acquire_a_mask_sub_sub_size, get_acquire_a_mask_sub_sub_0_2) node get_acquire_a_mask_sub_sub_0_1 = or(get_acquire_a_mask_sub_sub_sub_0_1, _get_acquire_a_mask_sub_sub_acc_T) node get_acquire_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), get_acquire_a_mask_sub_sub_bit) node _get_acquire_a_mask_sub_sub_acc_T_1 = and(get_acquire_a_mask_sub_sub_size, get_acquire_a_mask_sub_sub_1_2) node get_acquire_a_mask_sub_sub_1_1 = or(get_acquire_a_mask_sub_sub_sub_0_1, _get_acquire_a_mask_sub_sub_acc_T_1) node get_acquire_a_mask_sub_size = bits(get_acquire_a_mask_sizeOH, 1, 1) node get_acquire_a_mask_sub_bit = bits(_get_acquire_T, 1, 1) node get_acquire_a_mask_sub_nbit = eq(get_acquire_a_mask_sub_bit, UInt<1>(0h0)) node get_acquire_a_mask_sub_0_2 = and(get_acquire_a_mask_sub_sub_0_2, get_acquire_a_mask_sub_nbit) node _get_acquire_a_mask_sub_acc_T = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_0_2) node get_acquire_a_mask_sub_0_1 = or(get_acquire_a_mask_sub_sub_0_1, _get_acquire_a_mask_sub_acc_T) node get_acquire_a_mask_sub_1_2 = and(get_acquire_a_mask_sub_sub_0_2, get_acquire_a_mask_sub_bit) node _get_acquire_a_mask_sub_acc_T_1 = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_1_2) node get_acquire_a_mask_sub_1_1 = or(get_acquire_a_mask_sub_sub_0_1, _get_acquire_a_mask_sub_acc_T_1) node get_acquire_a_mask_sub_2_2 = and(get_acquire_a_mask_sub_sub_1_2, get_acquire_a_mask_sub_nbit) node _get_acquire_a_mask_sub_acc_T_2 = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_2_2) node get_acquire_a_mask_sub_2_1 = or(get_acquire_a_mask_sub_sub_1_1, _get_acquire_a_mask_sub_acc_T_2) node get_acquire_a_mask_sub_3_2 = and(get_acquire_a_mask_sub_sub_1_2, get_acquire_a_mask_sub_bit) node _get_acquire_a_mask_sub_acc_T_3 = and(get_acquire_a_mask_sub_size, get_acquire_a_mask_sub_3_2) node get_acquire_a_mask_sub_3_1 = or(get_acquire_a_mask_sub_sub_1_1, _get_acquire_a_mask_sub_acc_T_3) node get_acquire_a_mask_size = bits(get_acquire_a_mask_sizeOH, 0, 0) node get_acquire_a_mask_bit = bits(_get_acquire_T, 0, 0) node get_acquire_a_mask_nbit = eq(get_acquire_a_mask_bit, UInt<1>(0h0)) node get_acquire_a_mask_eq = and(get_acquire_a_mask_sub_0_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T = and(get_acquire_a_mask_size, get_acquire_a_mask_eq) node get_acquire_a_mask_acc = or(get_acquire_a_mask_sub_0_1, _get_acquire_a_mask_acc_T) node get_acquire_a_mask_eq_1 = and(get_acquire_a_mask_sub_0_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_1 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_1) node get_acquire_a_mask_acc_1 = or(get_acquire_a_mask_sub_0_1, _get_acquire_a_mask_acc_T_1) node get_acquire_a_mask_eq_2 = and(get_acquire_a_mask_sub_1_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T_2 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_2) node get_acquire_a_mask_acc_2 = or(get_acquire_a_mask_sub_1_1, _get_acquire_a_mask_acc_T_2) node get_acquire_a_mask_eq_3 = and(get_acquire_a_mask_sub_1_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_3 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_3) node get_acquire_a_mask_acc_3 = or(get_acquire_a_mask_sub_1_1, _get_acquire_a_mask_acc_T_3) node get_acquire_a_mask_eq_4 = and(get_acquire_a_mask_sub_2_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T_4 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_4) node get_acquire_a_mask_acc_4 = or(get_acquire_a_mask_sub_2_1, _get_acquire_a_mask_acc_T_4) node get_acquire_a_mask_eq_5 = and(get_acquire_a_mask_sub_2_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_5 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_5) node get_acquire_a_mask_acc_5 = or(get_acquire_a_mask_sub_2_1, _get_acquire_a_mask_acc_T_5) node get_acquire_a_mask_eq_6 = and(get_acquire_a_mask_sub_3_2, get_acquire_a_mask_nbit) node _get_acquire_a_mask_acc_T_6 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_6) node get_acquire_a_mask_acc_6 = or(get_acquire_a_mask_sub_3_1, _get_acquire_a_mask_acc_T_6) node get_acquire_a_mask_eq_7 = and(get_acquire_a_mask_sub_3_2, get_acquire_a_mask_bit) node _get_acquire_a_mask_acc_T_7 = and(get_acquire_a_mask_size, get_acquire_a_mask_eq_7) node get_acquire_a_mask_acc_7 = or(get_acquire_a_mask_sub_3_1, _get_acquire_a_mask_acc_T_7) node get_acquire_a_mask_lo_lo = cat(get_acquire_a_mask_acc_1, get_acquire_a_mask_acc) node get_acquire_a_mask_lo_hi = cat(get_acquire_a_mask_acc_3, get_acquire_a_mask_acc_2) node get_acquire_a_mask_lo = cat(get_acquire_a_mask_lo_hi, get_acquire_a_mask_lo_lo) node get_acquire_a_mask_hi_lo = cat(get_acquire_a_mask_acc_5, get_acquire_a_mask_acc_4) node get_acquire_a_mask_hi_hi = cat(get_acquire_a_mask_acc_7, get_acquire_a_mask_acc_6) node get_acquire_a_mask_hi = cat(get_acquire_a_mask_hi_hi, get_acquire_a_mask_hi_lo) node _get_acquire_a_mask_T = cat(get_acquire_a_mask_hi, get_acquire_a_mask_lo) connect get_acquire.mask, _get_acquire_a_mask_T invalidate get_acquire.data connect get_acquire.corrupt, UInt<1>(0h0) node _nodeOut_a_valid_T = eq(state, UInt<4>(0h7)) node _nodeOut_a_valid_T_1 = eq(state, UInt<4>(0h3)) node _nodeOut_a_valid_T_2 = or(_nodeOut_a_valid_T, _nodeOut_a_valid_T_1) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 node _nodeOut_a_bits_T = eq(state, UInt<4>(0h7)) node _nodeOut_a_bits_T_1 = mux(_nodeOut_a_bits_T, put_acquire, get_acquire) connect nodeOut.a.bits, _nodeOut_a_bits_T_1 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.ready, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) node _nodeOut_d_ready_T = eq(state, UInt<4>(0h8)) node _nodeOut_d_ready_T_1 = eq(state, UInt<4>(0h4)) node _nodeOut_d_ready_T_2 = or(_nodeOut_d_ready_T, _nodeOut_d_ready_T_1) connect nodeOut.d.ready, _nodeOut_d_ready_T_2 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.valid, UInt<1>(0h0) node _T = eq(state, UInt<4>(0h0)) node _T_1 = and(_T, io.tsi.in.valid) when _T_1 : connect cmd, io.tsi.in.bits connect idx, UInt<1>(0h0) connect addr, UInt<1>(0h0) connect len, UInt<1>(0h0) connect state, UInt<4>(0h1) node _T_2 = eq(state, UInt<4>(0h1)) node _T_3 = and(_T_2, io.tsi.in.valid) when _T_3 : node _addr_T = bits(idx, 0, 0) node _addr_T_1 = cat(_addr_T, UInt<5>(0h0)) node _addr_T_2 = dshl(io.tsi.in.bits, _addr_T_1) node _addr_T_3 = or(addr, _addr_T_2) connect addr, _addr_T_3 node _idx_T = add(idx, UInt<1>(0h1)) node _idx_T_1 = tail(_idx_T, 1) connect idx, _idx_T_1 node _T_4 = eq(idx, UInt<1>(0h1)) when _T_4 : connect idx, UInt<1>(0h0) connect state, UInt<4>(0h2) node _T_5 = eq(state, UInt<4>(0h2)) node _T_6 = and(_T_5, io.tsi.in.valid) when _T_6 : node _len_T = bits(idx, 0, 0) node _len_T_1 = cat(_len_T, UInt<5>(0h0)) node _len_T_2 = dshl(io.tsi.in.bits, _len_T_1) node _len_T_3 = or(len, _len_T_2) connect len, _len_T_3 node _idx_T_2 = add(idx, UInt<1>(0h1)) node _idx_T_3 = tail(_idx_T_2, 1) connect idx, _idx_T_3 node _T_7 = eq(idx, UInt<1>(0h1)) when _T_7 : node _idx_T_4 = bits(addr, 2, 2) connect idx, _idx_T_4 node _T_8 = eq(cmd, UInt<1>(0h1)) when _T_8 : connect bodyValid, UInt<1>(0h0) connect state, UInt<4>(0h6) else : node _T_9 = eq(cmd, UInt<1>(0h0)) when _T_9 : connect state, UInt<4>(0h3) else : node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed: Bad TSI command\n at TSIToTileLink.scala:137 assert(false.B, \"Bad TSI command\")\n") : printf assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert node _T_13 = eq(state, UInt<4>(0h3)) node _T_14 = and(_T_13, nodeOut.a.ready) when _T_14 : connect state, UInt<4>(0h4) node _T_15 = eq(state, UInt<4>(0h4)) node _T_16 = and(_T_15, nodeOut.d.valid) when _T_16 : wire _WIRE_6 : UInt<32>[2] wire _WIRE_7 : UInt<64> connect _WIRE_7, nodeOut.d.bits.data node _T_17 = bits(_WIRE_7, 31, 0) connect _WIRE_6[0], _T_17 node _T_18 = bits(_WIRE_7, 63, 32) connect _WIRE_6[1], _T_18 connect body, _WIRE_6 node _idx_T_5 = bits(addr, 2, 2) connect idx, _idx_T_5 connect addr, nextAddr connect state, UInt<4>(0h5) node _T_19 = eq(state, UInt<4>(0h5)) node _T_20 = and(_T_19, io.tsi.out.ready) when _T_20 : node _idx_T_6 = add(idx, UInt<1>(0h1)) node _idx_T_7 = tail(_idx_T_6, 1) connect idx, _idx_T_7 node _len_T_4 = sub(len, UInt<1>(0h1)) node _len_T_5 = tail(_len_T_4, 1) connect len, _len_T_5 node _T_21 = eq(len, UInt<1>(0h0)) when _T_21 : connect state, UInt<4>(0h0) else : node _T_22 = eq(idx, UInt<1>(0h1)) when _T_22 : connect state, UInt<4>(0h3) node _T_23 = eq(state, UInt<4>(0h6)) node _T_24 = and(_T_23, io.tsi.in.valid) when _T_24 : connect body[idx], io.tsi.in.bits node _bodyValid_T = dshl(UInt<1>(0h1), idx) node _bodyValid_T_1 = or(bodyValid, _bodyValid_T) connect bodyValid, _bodyValid_T_1 node _T_25 = eq(idx, UInt<1>(0h1)) node _T_26 = eq(len, UInt<1>(0h0)) node _T_27 = or(_T_25, _T_26) when _T_27 : connect state, UInt<4>(0h7) else : node _idx_T_8 = add(idx, UInt<1>(0h1)) node _idx_T_9 = tail(_idx_T_8, 1) connect idx, _idx_T_9 node _len_T_6 = sub(len, UInt<1>(0h1)) node _len_T_7 = tail(_len_T_6, 1) connect len, _len_T_7 node _T_28 = eq(state, UInt<4>(0h7)) node _T_29 = and(_T_28, nodeOut.a.ready) when _T_29 : connect state, UInt<4>(0h8) node _T_30 = eq(state, UInt<4>(0h8)) node _T_31 = and(_T_30, nodeOut.d.valid) when _T_31 : node _T_32 = eq(len, UInt<1>(0h0)) when _T_32 : connect state, UInt<4>(0h0) else : connect addr, nextAddr node _len_T_8 = sub(len, UInt<1>(0h1)) node _len_T_9 = tail(_len_T_8, 1) connect len, _len_T_9 connect idx, UInt<1>(0h0) connect bodyValid, UInt<1>(0h0) connect state, UInt<4>(0h6) extmodule plusarg_reader_183 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_184 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TSIToTileLink( // @[TSIToTileLink.scala:36:7] input clock, // @[TSIToTileLink.scala:36:7] input reset, // @[TSIToTileLink.scala:36:7] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_tsi_in_ready, // @[TSIToTileLink.scala:37:14] input io_tsi_in_valid, // @[TSIToTileLink.scala:37:14] input [31:0] io_tsi_in_bits, // @[TSIToTileLink.scala:37:14] input io_tsi_out_ready, // @[TSIToTileLink.scala:37:14] output io_tsi_out_valid, // @[TSIToTileLink.scala:37:14] output [31:0] io_tsi_out_bits, // @[TSIToTileLink.scala:37:14] output [3:0] io_state // @[TSIToTileLink.scala:37:14] ); wire auto_out_a_ready_0 = auto_out_a_ready; // @[TSIToTileLink.scala:36:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[TSIToTileLink.scala:36:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[TSIToTileLink.scala:36:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[TSIToTileLink.scala:36:7] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[TSIToTileLink.scala:36:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[TSIToTileLink.scala:36:7] wire io_tsi_in_valid_0 = io_tsi_in_valid; // @[TSIToTileLink.scala:36:7] wire [31:0] io_tsi_in_bits_0 = io_tsi_in_bits; // @[TSIToTileLink.scala:36:7] wire io_tsi_out_ready_0 = io_tsi_out_ready; // @[TSIToTileLink.scala:36:7] wire [2:0] auto_out_a_bits_param = 3'h0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] put_acquire_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] get_acquire_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] _nodeOut_a_bits_T_1_param = 3'h0; // @[TSIToTileLink.scala:95:20] wire auto_out_a_bits_source = 1'h0; // @[TSIToTileLink.scala:36:7] wire auto_out_a_bits_corrupt = 1'h0; // @[TSIToTileLink.scala:36:7] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire _put_acquire_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _put_acquire_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire put_acquire_source = 1'h0; // @[Edges.scala:500:17] wire put_acquire_corrupt = 1'h0; // @[Edges.scala:500:17] wire get_acquire_source = 1'h0; // @[Edges.scala:460:17] wire get_acquire_corrupt = 1'h0; // @[Edges.scala:460:17] wire _nodeOut_a_bits_T_1_source = 1'h0; // @[TSIToTileLink.scala:95:20] wire _nodeOut_a_bits_T_1_corrupt = 1'h0; // @[TSIToTileLink.scala:95:20] wire [63:0] get_acquire_data = 64'h0; // @[Edges.scala:460:17] wire [2:0] get_acquire_opcode = 3'h4; // @[Edges.scala:460:17] wire _put_acquire_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_acquire_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_acquire_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_acquire_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_acquire_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_acquire_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_acquire_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_acquire_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_acquire_legal_T_69 = 1'h1; // @[Parameters.scala:92:28] wire _put_acquire_legal_T_70 = 1'h1; // @[Parameters.scala:92:38] wire _put_acquire_legal_T_71 = 1'h1; // @[Parameters.scala:92:33] wire _put_acquire_legal_T_72 = 1'h1; // @[Parameters.scala:684:29] wire _get_acquire_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_acquire_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_acquire_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_acquire_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_acquire_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_acquire_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_acquire_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_acquire_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _get_acquire_legal_T_62 = 1'h1; // @[Parameters.scala:92:28] wire _get_acquire_legal_T_63 = 1'h1; // @[Parameters.scala:92:38] wire _get_acquire_legal_T_64 = 1'h1; // @[Parameters.scala:92:33] wire _get_acquire_legal_T_65 = 1'h1; // @[Parameters.scala:684:29] wire [3:0] put_acquire_size = 4'h3; // @[Edges.scala:500:17] wire [2:0] put_acquire_opcode = 3'h1; // @[Edges.scala:500:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[TSIToTileLink.scala:36:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[TSIToTileLink.scala:36:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[TSIToTileLink.scala:36:7] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[TSIToTileLink.scala:36:7] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[TSIToTileLink.scala:36:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[TSIToTileLink.scala:36:7] wire _io_tsi_in_ready_T_6; // @[package.scala:81:59] wire _io_tsi_out_valid_T; // @[TSIToTileLink.scala:71:29] wire [2:0] auto_out_a_bits_opcode_0; // @[TSIToTileLink.scala:36:7] wire [3:0] auto_out_a_bits_size_0; // @[TSIToTileLink.scala:36:7] wire [31:0] auto_out_a_bits_address_0; // @[TSIToTileLink.scala:36:7] wire [7:0] auto_out_a_bits_mask_0; // @[TSIToTileLink.scala:36:7] wire [63:0] auto_out_a_bits_data_0; // @[TSIToTileLink.scala:36:7] wire auto_out_a_valid_0; // @[TSIToTileLink.scala:36:7] wire auto_out_d_ready_0; // @[TSIToTileLink.scala:36:7] wire io_tsi_in_ready_0; // @[TSIToTileLink.scala:36:7] wire io_tsi_out_valid_0; // @[TSIToTileLink.scala:36:7] wire [31:0] io_tsi_out_bits_0; // @[TSIToTileLink.scala:36:7] wire [3:0] io_state_0; // @[TSIToTileLink.scala:36:7] wire _nodeOut_a_valid_T_2; // @[package.scala:81:59] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[TSIToTileLink.scala:36:7] wire [2:0] _nodeOut_a_bits_T_1_opcode; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[TSIToTileLink.scala:36:7] wire [3:0] _nodeOut_a_bits_T_1_size; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[TSIToTileLink.scala:36:7] wire [31:0] _nodeOut_a_bits_T_1_address; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[TSIToTileLink.scala:36:7] wire [7:0] _nodeOut_a_bits_T_1_mask; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[TSIToTileLink.scala:36:7] wire [63:0] _nodeOut_a_bits_T_1_data; // @[TSIToTileLink.scala:95:20] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[TSIToTileLink.scala:36:7] wire _nodeOut_d_ready_T_2; // @[package.scala:81:59] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[TSIToTileLink.scala:36:7] reg [31:0] cmd; // @[TSIToTileLink.scala:56:16] reg [63:0] addr; // @[TSIToTileLink.scala:57:17] reg [63:0] len; // @[TSIToTileLink.scala:58:16] reg [31:0] body_0; // @[TSIToTileLink.scala:59:17] reg [31:0] body_1; // @[TSIToTileLink.scala:59:17] reg [1:0] bodyValid; // @[TSIToTileLink.scala:60:22] reg idx; // @[TSIToTileLink.scala:61:16] wire _addr_T = idx; // @[TSIToTileLink.scala:61:16, :103:22] wire _len_T = idx; // @[TSIToTileLink.scala:61:16, :103:22] reg [3:0] state; // @[TSIToTileLink.scala:67:22] assign io_state_0 = state; // @[TSIToTileLink.scala:36:7, :67:22] wire _io_tsi_in_ready_T = state == 4'h0; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_1 = state == 4'h1; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_2 = state == 4'h2; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_3 = state == 4'h6; // @[TSIToTileLink.scala:67:22] wire _io_tsi_in_ready_T_4 = _io_tsi_in_ready_T \| _io_tsi_in_ready_T_1; // @[package.scala:16:47, :81:59] wire _io_tsi_in_ready_T_5 = _io_tsi_in_ready_T_4 \| _io_tsi_in_ready_T_2; // @[package.scala:16:47, :81:59] assign _io_tsi_in_ready_T_6 = _io_tsi_in_ready_T_5 \| _io_tsi_in_ready_T_3; // @[package.scala:16:47, :81:59] assign io_tsi_in_ready_0 = _io_tsi_in_ready_T_6; // @[TSIToTileLink.scala:36:7] assign _io_tsi_out_valid_T = state == 4'h5; // @[TSIToTileLink.scala:67:22, :71:29] assign io_tsi_out_valid_0 = _io_tsi_out_valid_T; // @[TSIToTileLink.scala:36:7, :71:29] assign io_tsi_out_bits_0 = idx ? body_1 : body_0; // @[TSIToTileLink.scala:36:7, :59:17, :61:16, :72:19] wire [28:0] beatAddr = addr[31:3]; // @[TSIToTileLink.scala:57:17, :74:22] wire [29:0] _nextAddr_T = {1'h0, beatAddr} + 30'h1; // @[TSIToTileLink.scala:74:22, :75:31] wire [28:0] _nextAddr_T_1 = _nextAddr_T[28:0]; // @[TSIToTileLink.scala:75:31] wire [31:0] nextAddr = {_nextAddr_T_1, 3'h0}; // @[TSIToTileLink.scala:75:{21,31}] wire _wmask_T = bodyValid[0]; // @[TSIToTileLink.scala:60:22, :77:30] wire _wmask_T_1 = bodyValid[1]; // @[TSIToTileLink.scala:60:22, :77:30] wire [3:0] _wmask_T_2 = {4{_wmask_T}}; // @[TSIToTileLink.scala:77:30] wire [3:0] _wmask_T_3 = {4{_wmask_T_1}}; // @[TSIToTileLink.scala:77:30] wire [7:0] wmask = {_wmask_T_3, _wmask_T_2}; // @[TSIToTileLink.scala:77:30] wire [7:0] put_acquire_mask = wmask; // @[TSIToTileLink.scala:77:30] wire [64:0] _addr_size_T = {33'h0, nextAddr} - {1'h0, addr}; // @[TSIToTileLink.scala:57:17, :75:21, :78:28] wire [63:0] addr_size = _addr_size_T[63:0]; // @[TSIToTileLink.scala:78:28] wire [64:0] _GEN = {1'h0, len}; // @[TSIToTileLink.scala:58:16, :79:26] wire [64:0] _len_size_T = _GEN + 65'h1; // @[TSIToTileLink.scala:79:26] wire [63:0] _len_size_T_1 = _len_size_T[63:0]; // @[TSIToTileLink.scala:79:26] wire [65:0] len_size = {_len_size_T_1, 2'h0}; // @[TSIToTileLink.scala:79:{21,26}] wire [65:0] _GEN_0 = {2'h0, addr_size}; // @[TSIToTileLink.scala:78:28, :80:31] wire _raw_size_T = len_size < _GEN_0; // @[TSIToTileLink.scala:79:21, :80:31] wire [65:0] raw_size = _raw_size_T ? len_size : _GEN_0; // @[TSIToTileLink.scala:79:21, :80:{21,31}] wire _rsize_T = raw_size == 66'h1; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] _rsize_T_1 = _rsize_T ? 2'h0 : 2'h3; // @[TSIToTileLink.scala:81:50] wire _rsize_T_2 = raw_size == 66'h2; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] _rsize_T_3 = _rsize_T_2 ? 2'h1 : _rsize_T_1; // @[TSIToTileLink.scala:81:50] wire _rsize_T_4 = raw_size == 66'h4; // @[TSIToTileLink.scala:80:21, :81:50] wire [1:0] rsize = _rsize_T_4 ? 2'h2 : _rsize_T_3; // @[TSIToTileLink.scala:81:50] wire _pow2size_T = raw_size[0]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_1 = raw_size[1]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_2 = raw_size[2]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_3 = raw_size[3]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_4 = raw_size[4]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_5 = raw_size[5]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_6 = raw_size[6]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_7 = raw_size[7]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_8 = raw_size[8]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_9 = raw_size[9]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_10 = raw_size[10]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_11 = raw_size[11]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_12 = raw_size[12]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_13 = raw_size[13]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_14 = raw_size[14]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_15 = raw_size[15]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_16 = raw_size[16]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_17 = raw_size[17]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_18 = raw_size[18]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_19 = raw_size[19]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_20 = raw_size[20]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_21 = raw_size[21]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_22 = raw_size[22]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_23 = raw_size[23]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_24 = raw_size[24]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_25 = raw_size[25]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_26 = raw_size[26]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_27 = raw_size[27]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_28 = raw_size[28]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_29 = raw_size[29]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_30 = raw_size[30]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_31 = raw_size[31]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_32 = raw_size[32]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_33 = raw_size[33]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_34 = raw_size[34]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_35 = raw_size[35]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_36 = raw_size[36]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_37 = raw_size[37]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_38 = raw_size[38]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_39 = raw_size[39]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_40 = raw_size[40]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_41 = raw_size[41]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_42 = raw_size[42]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_43 = raw_size[43]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_44 = raw_size[44]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_45 = raw_size[45]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_46 = raw_size[46]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_47 = raw_size[47]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_48 = raw_size[48]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_49 = raw_size[49]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_50 = raw_size[50]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_51 = raw_size[51]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_52 = raw_size[52]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_53 = raw_size[53]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_54 = raw_size[54]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_55 = raw_size[55]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_56 = raw_size[56]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_57 = raw_size[57]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_58 = raw_size[58]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_59 = raw_size[59]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_60 = raw_size[60]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_61 = raw_size[61]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_62 = raw_size[62]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_63 = raw_size[63]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_64 = raw_size[64]; // @[TSIToTileLink.scala:80:21, :84:26] wire _pow2size_T_65 = raw_size[65]; // @[TSIToTileLink.scala:80:21, :84:26] wire [1:0] _pow2size_T_66 = {1'h0, _pow2size_T} + {1'h0, _pow2size_T_1}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_67 = _pow2size_T_66; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_68 = {1'h0, _pow2size_T_2} + {1'h0, _pow2size_T_3}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_69 = _pow2size_T_68; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_70 = {1'h0, _pow2size_T_67} + {1'h0, _pow2size_T_69}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_71 = _pow2size_T_70; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_72 = {1'h0, _pow2size_T_4} + {1'h0, _pow2size_T_5}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_73 = _pow2size_T_72; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_74 = {1'h0, _pow2size_T_6} + {1'h0, _pow2size_T_7}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_75 = _pow2size_T_74; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_76 = {1'h0, _pow2size_T_73} + {1'h0, _pow2size_T_75}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_77 = _pow2size_T_76; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_78 = {1'h0, _pow2size_T_71} + {1'h0, _pow2size_T_77}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_79 = _pow2size_T_78; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_80 = {1'h0, _pow2size_T_8} + {1'h0, _pow2size_T_9}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_81 = _pow2size_T_80; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_82 = {1'h0, _pow2size_T_10} + {1'h0, _pow2size_T_11}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_83 = _pow2size_T_82; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_84 = {1'h0, _pow2size_T_81} + {1'h0, _pow2size_T_83}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_85 = _pow2size_T_84; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_86 = {1'h0, _pow2size_T_12} + {1'h0, _pow2size_T_13}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_87 = _pow2size_T_86; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_88 = {1'h0, _pow2size_T_14} + {1'h0, _pow2size_T_15}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_89 = _pow2size_T_88; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_90 = {1'h0, _pow2size_T_87} + {1'h0, _pow2size_T_89}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_91 = _pow2size_T_90; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_92 = {1'h0, _pow2size_T_85} + {1'h0, _pow2size_T_91}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_93 = _pow2size_T_92; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_94 = {1'h0, _pow2size_T_79} + {1'h0, _pow2size_T_93}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_95 = _pow2size_T_94; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_96 = {1'h0, _pow2size_T_16} + {1'h0, _pow2size_T_17}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_97 = _pow2size_T_96; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_98 = {1'h0, _pow2size_T_18} + {1'h0, _pow2size_T_19}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_99 = _pow2size_T_98; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_100 = {1'h0, _pow2size_T_97} + {1'h0, _pow2size_T_99}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_101 = _pow2size_T_100; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_102 = {1'h0, _pow2size_T_20} + {1'h0, _pow2size_T_21}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_103 = _pow2size_T_102; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_104 = {1'h0, _pow2size_T_22} + {1'h0, _pow2size_T_23}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_105 = _pow2size_T_104; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_106 = {1'h0, _pow2size_T_103} + {1'h0, _pow2size_T_105}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_107 = _pow2size_T_106; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_108 = {1'h0, _pow2size_T_101} + {1'h0, _pow2size_T_107}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_109 = _pow2size_T_108; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_110 = {1'h0, _pow2size_T_24} + {1'h0, _pow2size_T_25}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_111 = _pow2size_T_110; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_112 = {1'h0, _pow2size_T_26} + {1'h0, _pow2size_T_27}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_113 = _pow2size_T_112; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_114 = {1'h0, _pow2size_T_111} + {1'h0, _pow2size_T_113}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_115 = _pow2size_T_114; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_116 = {1'h0, _pow2size_T_28} + {1'h0, _pow2size_T_29}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_117 = _pow2size_T_116; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_118 = {1'h0, _pow2size_T_31} + {1'h0, _pow2size_T_32}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_119 = _pow2size_T_118; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_120 = {2'h0, _pow2size_T_30} + {1'h0, _pow2size_T_119}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_121 = _pow2size_T_120[1:0]; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_122 = {1'h0, _pow2size_T_117} + {1'h0, _pow2size_T_121}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_123 = _pow2size_T_122; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_124 = {1'h0, _pow2size_T_115} + {1'h0, _pow2size_T_123}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_125 = _pow2size_T_124; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_126 = {1'h0, _pow2size_T_109} + {1'h0, _pow2size_T_125}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_127 = _pow2size_T_126; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_128 = {1'h0, _pow2size_T_95} + {1'h0, _pow2size_T_127}; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_129 = _pow2size_T_128; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_130 = {1'h0, _pow2size_T_33} + {1'h0, _pow2size_T_34}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_131 = _pow2size_T_130; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_132 = {1'h0, _pow2size_T_35} + {1'h0, _pow2size_T_36}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_133 = _pow2size_T_132; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_134 = {1'h0, _pow2size_T_131} + {1'h0, _pow2size_T_133}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_135 = _pow2size_T_134; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_136 = {1'h0, _pow2size_T_37} + {1'h0, _pow2size_T_38}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_137 = _pow2size_T_136; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_138 = {1'h0, _pow2size_T_39} + {1'h0, _pow2size_T_40}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_139 = _pow2size_T_138; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_140 = {1'h0, _pow2size_T_137} + {1'h0, _pow2size_T_139}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_141 = _pow2size_T_140; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_142 = {1'h0, _pow2size_T_135} + {1'h0, _pow2size_T_141}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_143 = _pow2size_T_142; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_144 = {1'h0, _pow2size_T_41} + {1'h0, _pow2size_T_42}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_145 = _pow2size_T_144; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_146 = {1'h0, _pow2size_T_43} + {1'h0, _pow2size_T_44}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_147 = _pow2size_T_146; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_148 = {1'h0, _pow2size_T_145} + {1'h0, _pow2size_T_147}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_149 = _pow2size_T_148; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_150 = {1'h0, _pow2size_T_45} + {1'h0, _pow2size_T_46}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_151 = _pow2size_T_150; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_152 = {1'h0, _pow2size_T_47} + {1'h0, _pow2size_T_48}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_153 = _pow2size_T_152; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_154 = {1'h0, _pow2size_T_151} + {1'h0, _pow2size_T_153}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_155 = _pow2size_T_154; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_156 = {1'h0, _pow2size_T_149} + {1'h0, _pow2size_T_155}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_157 = _pow2size_T_156; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_158 = {1'h0, _pow2size_T_143} + {1'h0, _pow2size_T_157}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_159 = _pow2size_T_158; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_160 = {1'h0, _pow2size_T_49} + {1'h0, _pow2size_T_50}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_161 = _pow2size_T_160; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_162 = {1'h0, _pow2size_T_51} + {1'h0, _pow2size_T_52}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_163 = _pow2size_T_162; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_164 = {1'h0, _pow2size_T_161} + {1'h0, _pow2size_T_163}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_165 = _pow2size_T_164; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_166 = {1'h0, _pow2size_T_53} + {1'h0, _pow2size_T_54}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_167 = _pow2size_T_166; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_168 = {1'h0, _pow2size_T_55} + {1'h0, _pow2size_T_56}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_169 = _pow2size_T_168; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_170 = {1'h0, _pow2size_T_167} + {1'h0, _pow2size_T_169}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_171 = _pow2size_T_170; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_172 = {1'h0, _pow2size_T_165} + {1'h0, _pow2size_T_171}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_173 = _pow2size_T_172; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_174 = {1'h0, _pow2size_T_57} + {1'h0, _pow2size_T_58}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_175 = _pow2size_T_174; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_176 = {1'h0, _pow2size_T_59} + {1'h0, _pow2size_T_60}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_177 = _pow2size_T_176; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_178 = {1'h0, _pow2size_T_175} + {1'h0, _pow2size_T_177}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_179 = _pow2size_T_178; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_180 = {1'h0, _pow2size_T_61} + {1'h0, _pow2size_T_62}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_181 = _pow2size_T_180; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_182 = {1'h0, _pow2size_T_64} + {1'h0, _pow2size_T_65}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_183 = _pow2size_T_182; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_184 = {2'h0, _pow2size_T_63} + {1'h0, _pow2size_T_183}; // @[TSIToTileLink.scala:84:26] wire [1:0] _pow2size_T_185 = _pow2size_T_184[1:0]; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_186 = {1'h0, _pow2size_T_181} + {1'h0, _pow2size_T_185}; // @[TSIToTileLink.scala:84:26] wire [2:0] _pow2size_T_187 = _pow2size_T_186; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_188 = {1'h0, _pow2size_T_179} + {1'h0, _pow2size_T_187}; // @[TSIToTileLink.scala:84:26] wire [3:0] _pow2size_T_189 = _pow2size_T_188; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_190 = {1'h0, _pow2size_T_173} + {1'h0, _pow2size_T_189}; // @[TSIToTileLink.scala:84:26] wire [4:0] _pow2size_T_191 = _pow2size_T_190; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_192 = {1'h0, _pow2size_T_159} + {1'h0, _pow2size_T_191}; // @[TSIToTileLink.scala:84:26] wire [5:0] _pow2size_T_193 = _pow2size_T_192; // @[TSIToTileLink.scala:84:26] wire [6:0] _pow2size_T_194 = {1'h0, _pow2size_T_129} + {1'h0, _pow2size_T_193}; // @[TSIToTileLink.scala:84:26] wire [6:0] _pow2size_T_195 = _pow2size_T_194; // @[TSIToTileLink.scala:84:26] wire pow2size = _pow2size_T_195 == 7'h1; // @[TSIToTileLink.scala:84:{26,37}] wire [2:0] _byteAddr_T = addr[2:0]; // @[TSIToTileLink.scala:57:17, :85:36] wire [2:0] byteAddr = pow2size ? _byteAddr_T : 3'h0; // @[TSIToTileLink.scala:84:37, :85:{21,36}] wire [31:0] _put_acquire_T = {beatAddr, 3'h0}; // @[TSIToTileLink.scala:74:22, :88:19] wire [31:0] _put_acquire_legal_T_14 = _put_acquire_T; // @[TSIToTileLink.scala:88:19] wire [31:0] put_acquire_address = _put_acquire_T; // @[TSIToTileLink.scala:88:19] wire [63:0] _put_acquire_T_1 = {body_1, body_0}; // @[TSIToTileLink.scala:59:17, :89:10] wire [63:0] put_acquire_data = _put_acquire_T_1; // @[TSIToTileLink.scala:89:10] wire [31:0] _put_acquire_legal_T_4 = {_put_acquire_T[31:14], _put_acquire_T[13:0] ^ 14'h3000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_5 = {1'h0, _put_acquire_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_6 = _put_acquire_legal_T_5 & 33'hFFFFB000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_7 = _put_acquire_legal_T_6; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_8 = _put_acquire_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_9 = _put_acquire_legal_T_8; // @[Parameters.scala:684:54] wire _put_acquire_legal_T_79 = _put_acquire_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _put_acquire_legal_T_15 = {1'h0, _put_acquire_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_16 = _put_acquire_legal_T_15 & 33'hFFFFA000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_17 = _put_acquire_legal_T_16; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_18 = _put_acquire_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_19 = {_put_acquire_T[31:21], _put_acquire_T[20:0] ^ 21'h100000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_20 = {1'h0, _put_acquire_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_21 = _put_acquire_legal_T_20 & 33'hFFFEB000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_22 = _put_acquire_legal_T_21; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_23 = _put_acquire_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_24 = {_put_acquire_T[31:26], _put_acquire_T[25:0] ^ 26'h2000000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_25 = {1'h0, _put_acquire_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_26 = _put_acquire_legal_T_25 & 33'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_27 = _put_acquire_legal_T_26; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_28 = _put_acquire_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_29 = {_put_acquire_T[31:26], _put_acquire_T[25:0] ^ 26'h2010000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_30 = {1'h0, _put_acquire_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_31 = _put_acquire_legal_T_30 & 33'hFFFFB000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_32 = _put_acquire_legal_T_31; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_33 = _put_acquire_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_34 = {_put_acquire_T[31:28], _put_acquire_T[27:0] ^ 28'h8000000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_35 = {1'h0, _put_acquire_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_36 = _put_acquire_legal_T_35 & 33'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_37 = _put_acquire_legal_T_36; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_38 = _put_acquire_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_39 = {_put_acquire_T[31:28], _put_acquire_T[27:0] ^ 28'hC000000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_40 = {1'h0, _put_acquire_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_41 = _put_acquire_legal_T_40 & 33'hFC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_42 = _put_acquire_legal_T_41; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_43 = _put_acquire_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_44 = {_put_acquire_T[31:29], _put_acquire_T[28:0] ^ 29'h10020000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_45 = {1'h0, _put_acquire_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_46 = _put_acquire_legal_T_45 & 33'hFFFFB000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_47 = _put_acquire_legal_T_46; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_48 = _put_acquire_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_49 = _put_acquire_T ^ 32'h80000000; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_50 = {1'h0, _put_acquire_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_51 = _put_acquire_legal_T_50 & 33'hF0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_52 = _put_acquire_legal_T_51; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_53 = _put_acquire_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_54 = _put_acquire_legal_T_18 \| _put_acquire_legal_T_23; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_55 = _put_acquire_legal_T_54 \| _put_acquire_legal_T_28; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_56 = _put_acquire_legal_T_55 \| _put_acquire_legal_T_33; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_57 = _put_acquire_legal_T_56 \| _put_acquire_legal_T_38; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_58 = _put_acquire_legal_T_57 \| _put_acquire_legal_T_43; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_59 = _put_acquire_legal_T_58 \| _put_acquire_legal_T_48; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_60 = _put_acquire_legal_T_59 \| _put_acquire_legal_T_53; // @[Parameters.scala:685:42] wire _put_acquire_legal_T_61 = _put_acquire_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [31:0] _put_acquire_legal_T_63 = {_put_acquire_T[31:17], _put_acquire_T[16:0] ^ 17'h10000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_64 = {1'h0, _put_acquire_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_65 = _put_acquire_legal_T_64 & 33'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_66 = _put_acquire_legal_T_65; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_67 = _put_acquire_legal_T_66 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _put_acquire_legal_T_73 = {_put_acquire_T[31:18], _put_acquire_T[17:0] ^ 18'h20000}; // @[TSIToTileLink.scala:88:19] wire [32:0] _put_acquire_legal_T_74 = {1'h0, _put_acquire_legal_T_73}; // @[Parameters.scala:137:{31,41}] wire [32:0] _put_acquire_legal_T_75 = _put_acquire_legal_T_74 & 33'hFFFF8000; // @[Parameters.scala:137:{41,46}] wire [32:0] _put_acquire_legal_T_76 = _put_acquire_legal_T_75; // @[Parameters.scala:137:46] wire _put_acquire_legal_T_77 = _put_acquire_legal_T_76 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _put_acquire_legal_T_78 = _put_acquire_legal_T_77; // @[Parameters.scala:684:54] wire _put_acquire_legal_T_80 = _put_acquire_legal_T_79 \| _put_acquire_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire _put_acquire_legal_T_81 = _put_acquire_legal_T_80; // @[Parameters.scala:686:26] wire put_acquire_legal = _put_acquire_legal_T_81 \| _put_acquire_legal_T_78; // @[Parameters.scala:684:54, :686:26] wire [31:0] _get_acquire_T = {beatAddr, byteAddr}; // @[TSIToTileLink.scala:74:22, :85:21, :92:13] wire [31:0] _get_acquire_legal_T_14 = _get_acquire_T; // @[TSIToTileLink.scala:92:13] wire [31:0] get_acquire_address = _get_acquire_T; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_4 = {_get_acquire_T[31:14], _get_acquire_T[13:0] ^ 14'h3000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_5 = {1'h0, _get_acquire_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_6 = _get_acquire_legal_T_5 & 33'hFFEFB000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_7 = _get_acquire_legal_T_6; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_8 = _get_acquire_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _get_acquire_legal_T_9 = _get_acquire_legal_T_8; // @[Parameters.scala:684:54] wire _get_acquire_legal_T_72 = _get_acquire_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _get_acquire_legal_T_15 = {1'h0, _get_acquire_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_16 = _get_acquire_legal_T_15 & 33'hFFEFA000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_17 = _get_acquire_legal_T_16; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_18 = _get_acquire_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_1 = {_get_acquire_T[31:17], _get_acquire_T[16:0] ^ 17'h10000}; // @[TSIToTileLink.scala:92:13] wire [31:0] _get_acquire_legal_T_19; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_19 = _GEN_1; // @[Parameters.scala:137:31] wire [31:0] _get_acquire_legal_T_24; // @[Parameters.scala:137:31] assign _get_acquire_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31] wire [32:0] _get_acquire_legal_T_20 = {1'h0, _get_acquire_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_21 = _get_acquire_legal_T_20 & 33'hFDEFB000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_22 = _get_acquire_legal_T_21; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_23 = _get_acquire_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _get_acquire_legal_T_25 = {1'h0, _get_acquire_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_26 = _get_acquire_legal_T_25 & 33'hFFEF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_27 = _get_acquire_legal_T_26; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_28 = _get_acquire_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_29 = {_get_acquire_T[31:26], _get_acquire_T[25:0] ^ 26'h2000000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_30 = {1'h0, _get_acquire_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_31 = _get_acquire_legal_T_30 & 33'hFFEF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_32 = _get_acquire_legal_T_31; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_33 = _get_acquire_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_34 = {_get_acquire_T[31:28], _get_acquire_T[27:0] ^ 28'h8000000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_35 = {1'h0, _get_acquire_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_36 = _get_acquire_legal_T_35 & 33'hFFEF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_37 = _get_acquire_legal_T_36; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_38 = _get_acquire_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_39 = {_get_acquire_T[31:28], _get_acquire_T[27:0] ^ 28'hC000000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_40 = {1'h0, _get_acquire_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_41 = _get_acquire_legal_T_40 & 33'hFC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_42 = _get_acquire_legal_T_41; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_43 = _get_acquire_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_44 = {_get_acquire_T[31:29], _get_acquire_T[28:0] ^ 29'h10020000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_45 = {1'h0, _get_acquire_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_46 = _get_acquire_legal_T_45 & 33'hFFEFB000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_47 = _get_acquire_legal_T_46; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_48 = _get_acquire_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _get_acquire_legal_T_49 = _get_acquire_T ^ 32'h80000000; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_50 = {1'h0, _get_acquire_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_51 = _get_acquire_legal_T_50 & 33'hF0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_52 = _get_acquire_legal_T_51; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_53 = _get_acquire_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _get_acquire_legal_T_54 = _get_acquire_legal_T_18 \| _get_acquire_legal_T_23; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_55 = _get_acquire_legal_T_54 \| _get_acquire_legal_T_28; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_56 = _get_acquire_legal_T_55 \| _get_acquire_legal_T_33; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_57 = _get_acquire_legal_T_56 \| _get_acquire_legal_T_38; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_58 = _get_acquire_legal_T_57 \| _get_acquire_legal_T_43; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_59 = _get_acquire_legal_T_58 \| _get_acquire_legal_T_48; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_60 = _get_acquire_legal_T_59 \| _get_acquire_legal_T_53; // @[Parameters.scala:685:42] wire _get_acquire_legal_T_61 = _get_acquire_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [31:0] _get_acquire_legal_T_66 = {_get_acquire_T[31:18], _get_acquire_T[17:0] ^ 18'h20000}; // @[TSIToTileLink.scala:92:13] wire [32:0] _get_acquire_legal_T_67 = {1'h0, _get_acquire_legal_T_66}; // @[Parameters.scala:137:{31,41}] wire [32:0] _get_acquire_legal_T_68 = _get_acquire_legal_T_67 & 33'hFFEF8000; // @[Parameters.scala:137:{41,46}] wire [32:0] _get_acquire_legal_T_69 = _get_acquire_legal_T_68; // @[Parameters.scala:137:46] wire _get_acquire_legal_T_70 = _get_acquire_legal_T_69 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _get_acquire_legal_T_71 = _get_acquire_legal_T_70; // @[Parameters.scala:684:54] wire _get_acquire_legal_T_73 = _get_acquire_legal_T_72 \| _get_acquire_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire get_acquire_legal = _get_acquire_legal_T_73 \| _get_acquire_legal_T_71; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_acquire_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_acquire_size; // @[Edges.scala:460:17] wire [7:0] get_acquire_mask; // @[Edges.scala:460:17] assign get_acquire_size = {2'h0, rsize}; // @[TSIToTileLink.scala:81:50] wire [2:0] _get_acquire_a_mask_sizeOH_T = {1'h0, rsize}; // @[TSIToTileLink.scala:81:50] wire [1:0] get_acquire_a_mask_sizeOH_shiftAmount = _get_acquire_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_acquire_a_mask_sizeOH_T_1 = 4'h1 << get_acquire_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_acquire_a_mask_sizeOH_T_2 = _get_acquire_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_acquire_a_mask_sizeOH = {_get_acquire_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_acquire_a_mask_sub_sub_sub_0_1 = &rsize; // @[TSIToTileLink.scala:81:50] wire get_acquire_a_mask_sub_sub_size = get_acquire_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_sub_sub_bit = _get_acquire_T[2]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_sub_sub_1_2 = get_acquire_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_acquire_a_mask_sub_sub_nbit = ~get_acquire_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_sub_sub_0_2 = get_acquire_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_sub_acc_T = get_acquire_a_mask_sub_sub_size & get_acquire_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_sub_0_1 = get_acquire_a_mask_sub_sub_sub_0_1 \| _get_acquire_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_acquire_a_mask_sub_sub_acc_T_1 = get_acquire_a_mask_sub_sub_size & get_acquire_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_sub_1_1 = get_acquire_a_mask_sub_sub_sub_0_1 \| _get_acquire_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_acquire_a_mask_sub_size = get_acquire_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_sub_bit = _get_acquire_T[1]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_sub_nbit = ~get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_sub_0_2 = get_acquire_a_mask_sub_sub_0_2 & get_acquire_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_acc_T = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_0_1 = get_acquire_a_mask_sub_sub_0_1 \| _get_acquire_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_1_2 = get_acquire_a_mask_sub_sub_0_2 & get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_sub_acc_T_1 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_1_1 = get_acquire_a_mask_sub_sub_0_1 \| _get_acquire_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_2_2 = get_acquire_a_mask_sub_sub_1_2 & get_acquire_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_sub_acc_T_2 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_2_1 = get_acquire_a_mask_sub_sub_1_1 \| _get_acquire_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_sub_3_2 = get_acquire_a_mask_sub_sub_1_2 & get_acquire_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_sub_acc_T_3 = get_acquire_a_mask_sub_size & get_acquire_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_sub_3_1 = get_acquire_a_mask_sub_sub_1_1 \| _get_acquire_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_size = get_acquire_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_acquire_a_mask_bit = _get_acquire_T[0]; // @[TSIToTileLink.scala:92:13] wire get_acquire_a_mask_nbit = ~get_acquire_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_acquire_a_mask_eq = get_acquire_a_mask_sub_0_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T = get_acquire_a_mask_size & get_acquire_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc = get_acquire_a_mask_sub_0_1 \| _get_acquire_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_1 = get_acquire_a_mask_sub_0_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_1 = get_acquire_a_mask_size & get_acquire_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_1 = get_acquire_a_mask_sub_0_1 \| _get_acquire_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_2 = get_acquire_a_mask_sub_1_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_2 = get_acquire_a_mask_size & get_acquire_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_2 = get_acquire_a_mask_sub_1_1 \| _get_acquire_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_3 = get_acquire_a_mask_sub_1_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_3 = get_acquire_a_mask_size & get_acquire_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_3 = get_acquire_a_mask_sub_1_1 \| _get_acquire_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_4 = get_acquire_a_mask_sub_2_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_4 = get_acquire_a_mask_size & get_acquire_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_4 = get_acquire_a_mask_sub_2_1 \| _get_acquire_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_5 = get_acquire_a_mask_sub_2_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_5 = get_acquire_a_mask_size & get_acquire_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_5 = get_acquire_a_mask_sub_2_1 \| _get_acquire_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_6 = get_acquire_a_mask_sub_3_2 & get_acquire_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_acquire_a_mask_acc_T_6 = get_acquire_a_mask_size & get_acquire_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_6 = get_acquire_a_mask_sub_3_1 \| _get_acquire_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_acquire_a_mask_eq_7 = get_acquire_a_mask_sub_3_2 & get_acquire_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_acquire_a_mask_acc_T_7 = get_acquire_a_mask_size & get_acquire_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_acquire_a_mask_acc_7 = get_acquire_a_mask_sub_3_1 \| _get_acquire_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_acquire_a_mask_lo_lo = {get_acquire_a_mask_acc_1, get_acquire_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_acquire_a_mask_lo_hi = {get_acquire_a_mask_acc_3, get_acquire_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_acquire_a_mask_lo = {get_acquire_a_mask_lo_hi, get_acquire_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_acquire_a_mask_hi_lo = {get_acquire_a_mask_acc_5, get_acquire_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_acquire_a_mask_hi_hi = {get_acquire_a_mask_acc_7, get_acquire_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_acquire_a_mask_hi = {get_acquire_a_mask_hi_hi, get_acquire_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_acquire_a_mask_T = {get_acquire_a_mask_hi, get_acquire_a_mask_lo}; // @[Misc.scala:222:10] assign get_acquire_mask = _get_acquire_a_mask_T; // @[Misc.scala:222:10] wire _T_28 = state == 4'h7; // @[TSIToTileLink.scala:67:22] wire _nodeOut_a_valid_T; // @[package.scala:16:47] assign _nodeOut_a_valid_T = _T_28; // @[package.scala:16:47] wire _nodeOut_a_bits_T; // @[TSIToTileLink.scala:95:27] assign _nodeOut_a_bits_T = _T_28; // @[TSIToTileLink.scala:95:27] wire _nodeOut_a_valid_T_1 = state == 4'h3; // @[TSIToTileLink.scala:67:22] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T \| _nodeOut_a_valid_T_1; // @[package.scala:16:47, :81:59] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[package.scala:81:59] assign _nodeOut_a_bits_T_1_opcode = _nodeOut_a_bits_T ? 3'h1 : 3'h4; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_size = _nodeOut_a_bits_T ? 4'h3 : get_acquire_size; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_address = _nodeOut_a_bits_T ? put_acquire_address : get_acquire_address; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_mask = _nodeOut_a_bits_T ? put_acquire_mask : get_acquire_mask; // @[TSIToTileLink.scala:95:{20,27}] assign _nodeOut_a_bits_T_1_data = _nodeOut_a_bits_T ? put_acquire_data : 64'h0; // @[TSIToTileLink.scala:95:{20,27}] assign nodeOut_a_bits_opcode = _nodeOut_a_bits_T_1_opcode; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_size = _nodeOut_a_bits_T_1_size; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_address = _nodeOut_a_bits_T_1_address; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_mask = _nodeOut_a_bits_T_1_mask; // @[TSIToTileLink.scala:95:20] assign nodeOut_a_bits_data = _nodeOut_a_bits_T_1_data; // @[TSIToTileLink.scala:95:20] wire _nodeOut_d_ready_T = state == 4'h8; // @[TSIToTileLink.scala:67:22] wire _nodeOut_d_ready_T_1 = state == 4'h4; // @[TSIToTileLink.scala:67:22] assign _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T \| _nodeOut_d_ready_T_1; // @[package.scala:16:47, :81:59] assign nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[package.scala:81:59] wire [5:0] _addr_T_1 = {_addr_T, 5'h0}; // @[TSIToTileLink.scala:103:{18,22}] wire [94:0] _GEN_2 = {63'h0, io_tsi_in_bits_0}; // @[TSIToTileLink.scala:36:7, :103:12] wire [94:0] _addr_T_2 = _GEN_2 << _addr_T_1; // @[TSIToTileLink.scala:103:{12,18}] wire [94:0] _addr_T_3 = {31'h0, addr} \| _addr_T_2; // @[TSIToTileLink.scala:57:17, :103:12, :118:18] wire [1:0] _GEN_3 = {1'h0, idx}; // @[TSIToTileLink.scala:61:16, :119:16] wire [1:0] _GEN_4 = _GEN_3 + 2'h1; // @[TSIToTileLink.scala:119:16] wire [1:0] _idx_T; // @[TSIToTileLink.scala:119:16] assign _idx_T = _GEN_4; // @[TSIToTileLink.scala:119:16] wire [1:0] _idx_T_2; // @[TSIToTileLink.scala:128:16] assign _idx_T_2 = _GEN_4; // @[TSIToTileLink.scala:119:16, :128:16] wire [1:0] _idx_T_6; // @[TSIToTileLink.scala:154:16] assign _idx_T_6 = _GEN_4; // @[TSIToTileLink.scala:119:16, :154:16] wire [1:0] _idx_T_8; // @[TSIToTileLink.scala:166:18] assign _idx_T_8 = _GEN_4; // @[TSIToTileLink.scala:119:16, :166:18] wire _idx_T_1 = _idx_T[0]; // @[TSIToTileLink.scala:119:16] wire _T_6 = _io_tsi_in_ready_T_2 & io_tsi_in_valid_0; // @[TSIToTileLink.scala:36:7, :126:25] wire [5:0] _len_T_1 = {_len_T, 5'h0}; // @[TSIToTileLink.scala:103:{18,22}] wire [94:0] _len_T_2 = _GEN_2 << _len_T_1; // @[TSIToTileLink.scala:103:{12,18}] wire [94:0] _len_T_3 = {31'h0, len} \| _len_T_2; // @[TSIToTileLink.scala:58:16, :103:12, :127:16] wire _idx_T_3 = _idx_T_2[0]; // @[TSIToTileLink.scala:128:16] wire _GEN_5 = _T_6 & idx; // @[TSIToTileLink.scala:61:16, :126:25, :129:43] wire _idx_T_4 = addr[2]; // @[TSIToTileLink.scala:57:17, :107:33] wire _idx_T_5 = addr[2]; // @[TSIToTileLink.scala:57:17, :107:33]
Generate the Verilog code corresponding to this FIRRTL code module PE_366 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_110 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_366( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_110 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_41 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = or(_T_667, _T_672) node _T_699 = or(_T_698, _T_677) node _T_700 = or(_T_699, _T_682) node _T_701 = or(_T_700, _T_687) node _T_702 = or(_T_701, _T_692) node _T_703 = or(_T_702, _T_697) node _T_704 = and(_T_662, _T_703) node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = and(_T_705, _T_710) node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_714 = and(_T_712, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = or(_T_720, _T_725) node _T_727 = and(_T_715, _T_726) node _T_728 = or(UInt<1>(0h0), _T_704) node _T_729 = or(_T_728, _T_711) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_731, UInt<1>(0h1), "") : assert_36 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_741, UInt<1>(0h1), "") : assert_39 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_745, UInt<1>(0h1), "") : assert_40 node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = or(_T_764, _T_769) node _T_796 = or(_T_795, _T_774) node _T_797 = or(_T_796, _T_779) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_789) node _T_800 = or(_T_799, _T_794) node _T_801 = and(_T_759, _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = or(_T_817, _T_822) node _T_824 = and(_T_812, _T_823) node _T_825 = or(UInt<1>(0h0), _T_801) node _T_826 = or(_T_825, _T_808) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_828, UInt<1>(0h1), "") : assert_41 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_838, UInt<1>(0h1), "") : assert_44 node _T_842 = eq(io.in.a.bits.mask, mask) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_842, UInt<1>(0h1), "") : assert_45 node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_846 : node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_849 = and(_T_847, _T_848) node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = or(_T_868, _T_873) node _T_900 = or(_T_899, _T_878) node _T_901 = or(_T_900, _T_883) node _T_902 = or(_T_901, _T_888) node _T_903 = or(_T_902, _T_893) node _T_904 = or(_T_903, _T_898) node _T_905 = and(_T_863, _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_862) node _T_923 = or(_T_922, _T_905) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_852, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_925, UInt<1>(0h1), "") : assert_46 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_935, UInt<1>(0h1), "") : assert_49 node _T_939 = eq(io.in.a.bits.mask, mask) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_939, UInt<1>(0h1), "") : assert_50 node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_943, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_947, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_955 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_955, UInt<1>(0h1), "") : assert_54 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_959, UInt<1>(0h1), "") : assert_55 node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_963, UInt<1>(0h1), "") : assert_56 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_967, UInt<1>(0h1), "") : assert_57 node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(sink_ok, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_978 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_978, UInt<1>(0h1), "") : assert_60 node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_982, UInt<1>(0h1), "") : assert_61 node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_986, UInt<1>(0h1), "") : assert_62 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_990, UInt<1>(0h1), "") : assert_63 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_995, UInt<1>(0h1), "") : assert_64 node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(sink_ok, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1006 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67 node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68 node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h1), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71 node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h1), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75 node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1045 : node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79 node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1092 = eq(a_first, UInt<1>(0h0)) node _T_1093 = and(io.in.a.valid, _T_1092) when _T_1093 : node _T_1094 = eq(io.in.a.bits.opcode, opcode) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87 node _T_1098 = eq(io.in.a.bits.param, param) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88 node _T_1102 = eq(io.in.a.bits.size, size) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89 node _T_1106 = eq(io.in.a.bits.source, source) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90 node _T_1110 = eq(io.in.a.bits.address, address) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91 node _T_1114 = and(io.in.a.ready, io.in.a.valid) node _T_1115 = and(_T_1114, a_first) when _T_1115 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1116 = eq(d_first, UInt<1>(0h0)) node _T_1117 = and(io.in.d.valid, _T_1116) when _T_1117 : node _T_1118 = eq(io.in.d.bits.opcode, opcode_1) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92 node _T_1122 = eq(io.in.d.bits.param, param_1) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93 node _T_1126 = eq(io.in.d.bits.size, size_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94 node _T_1130 = eq(io.in.d.bits.source, source_1) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95 node _T_1134 = eq(io.in.d.bits.sink, sink) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96 node _T_1138 = eq(io.in.d.bits.denied, denied) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97 node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = and(_T_1142, d_first) when _T_1143 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1144 = and(io.in.a.valid, a_first_1) node _T_1145 = and(_T_1144, UInt<1>(0h1)) when _T_1145 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1146 = and(io.in.a.ready, io.in.a.valid) node _T_1147 = and(_T_1146, a_first_1) node _T_1148 = and(_T_1147, UInt<1>(0h1)) when _T_1148 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1149 = dshr(inflight, io.in.a.bits.source) node _T_1150 = bits(_T_1149, 0, 0) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1155 = and(io.in.d.valid, d_first_1) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = eq(d_release_ack, UInt<1>(0h0)) node _T_1158 = and(_T_1156, _T_1157) when _T_1158 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1159 = and(io.in.d.ready, io.in.d.valid) node _T_1160 = and(_T_1159, d_first_1) node _T_1161 = and(_T_1160, UInt<1>(0h1)) node _T_1162 = eq(d_release_ack, UInt<1>(0h0)) node _T_1163 = and(_T_1161, _T_1162) when _T_1163 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1164 = and(io.in.d.valid, d_first_1) node _T_1165 = and(_T_1164, UInt<1>(0h1)) node _T_1166 = eq(d_release_ack, UInt<1>(0h0)) node _T_1167 = and(_T_1165, _T_1166) when _T_1167 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1168 = dshr(inflight, io.in.d.bits.source) node _T_1169 = bits(_T_1168, 0, 0) node _T_1170 = or(_T_1169, same_cycle_resp) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100 node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101 else : node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1186 = or(_T_1184, _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102 node _T_1190 = eq(io.in.d.bits.size, a_size_lookup) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103 node _T_1194 = and(io.in.d.valid, d_first_1) node _T_1195 = and(_T_1194, a_first_1) node _T_1196 = and(_T_1195, io.in.a.valid) node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = eq(d_release_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.a.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104 node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1207 = orr(a_set_wo_ready) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = or(_T_1206, _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_82 node _T_1213 = orr(inflight) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog, plusarg_reader.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1222 = and(io.in.a.ready, io.in.a.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1225 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<128>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1231 = and(_T_1230, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = and(_T_1231, _T_1234) when _T_1235 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1237 = bits(_T_1236, 0, 0) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1242 = and(io.in.d.valid, d_first_2) node _T_1243 = and(_T_1242, UInt<1>(0h1)) node _T_1244 = and(_T_1243, d_release_ack_1) when _T_1244 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1245 = and(io.in.d.ready, io.in.d.valid) node _T_1246 = and(_T_1245, d_first_2) node _T_1247 = and(_T_1246, UInt<1>(0h1)) node _T_1248 = and(_T_1247, d_release_ack_1) when _T_1248 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1249 = and(io.in.d.valid, d_first_2) node _T_1250 = and(_T_1249, UInt<1>(0h1)) node _T_1251 = and(_T_1250, d_release_ack_1) when _T_1251 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1252 = dshr(inflight_1, io.in.d.bits.source) node _T_1253 = bits(_T_1252, 0, 0) node _T_1254 = or(_T_1253, same_cycle_resp_1) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109 else : node _T_1262 = eq(io.in.d.bits.size, c_size_lookup) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _T_1266 = and(io.in.d.valid, d_first_2) node _T_1267 = and(_T_1266, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1268 = and(_T_1267, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = and(_T_1270, d_release_ack_1) node _T_1272 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1275 = or(_T_1274, _WIRE_23.ready) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111 node _T_1279 = orr(c_set_wo_ready) when _T_1279 : node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_83 node _T_1284 = orr(inflight_1) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1287 = or(_T_1285, _T_1286) node _T_1288 = lt(watchdog_1, plusarg_reader_1.out) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1294 = and(io.in.d.ready, io.in.d.valid) node _T_1295 = or(_T_1293, _T_1294) when _T_1295 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_41( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_1 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_2 = 2'h1 << _GEN_1; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1148 = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1148 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1148 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1148 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1148 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1148 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1194 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_82 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_95 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_82( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_95 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_22 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_32 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_22( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_32 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_52 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}} node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero) node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf) node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1) node notNaN_isInfOut = or(io.a.isInf, io.b.isInf) node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero) node notNaN_signOut = xor(io.a.sign, io.b.sign) node _common_sExpOut_T = add(io.a.sExp, io.b.sExp) node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1) node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1) node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100))) node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1) node common_sExpOut = asSInt(_common_sExpOut_T_4) node _common_sigOut_T = mul(io.a.sig, io.b.sig) node common_sigOut = bits(_common_sigOut_T, 47, 0) node _io_invalidExc_T = bits(io.a.sig, 22, 22) node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0)) node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1) node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22) node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0)) node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4) node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5) node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc) connect io.invalidExc, _io_invalidExc_T_7 connect io.rawOut.isInf, notNaN_isInfOut connect io.rawOut.isZero, notNaN_isZeroOut connect io.rawOut.sExp, common_sExpOut node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.sign, notNaN_signOut connect io.rawOut.sig, common_sigOut	module MulFullRawFN_52( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T \| _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 \| io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 \| io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 \| _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 \| notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 \| io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLPLIC : input clock : Clock input reset : Reset output auto : { flip int_in : UInt<1>[2], int_out_1 : UInt<1>[1], int_out_0 : UInt<1>[1], flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_51 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire intnodeIn : UInt<1>[2] invalidate intnodeIn[0] invalidate intnodeIn[1] wire intnodeOut : UInt<1>[1] invalidate intnodeOut[0] wire x1_intnodeOut : UInt<1>[1] invalidate x1_intnodeOut[0] connect nodeIn, auto.in connect auto.int_out_0, intnodeOut connect auto.int_out_1, x1_intnodeOut connect intnodeIn, auto.int_in inst gateways_gateway of LevelGateway connect gateways_gateway.clock, clock connect gateways_gateway.reset, reset connect gateways_gateway.io.interrupt, intnodeIn[0] inst gateways_gateway_1 of LevelGateway_1 connect gateways_gateway_1.clock, clock connect gateways_gateway_1.reset, reset connect gateways_gateway_1.io.interrupt, intnodeIn[1] reg priority : UInt<2>[2], clock reg threshold : UInt<2>[2], clock wire _pending_WIRE : UInt<1>[2] connect _pending_WIRE[0], UInt<1>(0h0) connect _pending_WIRE[1], UInt<1>(0h0) regreset pending : UInt<1>[2], clock, reset, _pending_WIRE reg enables_0_0 : UInt<2>, clock reg enables_1_0 : UInt<2>, clock wire enableVec : UInt<2>[2] connect enableVec[0], enables_0_0 connect enableVec[1], enables_1_0 node _enableVec0_T = cat(enableVec[0], UInt<1>(0h0)) node _enableVec0_T_1 = cat(enableVec[1], UInt<1>(0h0)) wire enableVec0 : UInt<3>[2] connect enableVec0[0], _enableVec0_T connect enableVec0[1], _enableVec0_T_1 reg maxDevs : UInt<2>[2], clock node pendingUInt = cat(pending[1], pending[0]) inst fanin of PLICFanIn connect fanin.clock, clock connect fanin.reset, reset connect fanin.io.prio[0], priority[0] connect fanin.io.prio[1], priority[1] node _fanin_io_ip_T = and(enableVec[0], pendingUInt) connect fanin.io.ip, _fanin_io_ip_T connect maxDevs[0], fanin.io.dev reg intnodeOut_0_REG : UInt, clock connect intnodeOut_0_REG, fanin.io.max node _intnodeOut_0_T = gt(intnodeOut_0_REG, threshold[0]) connect intnodeOut[0], _intnodeOut_0_T inst fanin_1 of PLICFanIn_1 connect fanin_1.clock, clock connect fanin_1.reset, reset connect fanin_1.io.prio[0], priority[0] connect fanin_1.io.prio[1], priority[1] node _fanin_io_ip_T_1 = and(enableVec[1], pendingUInt) connect fanin_1.io.ip, _fanin_io_ip_T_1 connect maxDevs[1], fanin_1.io.dev reg intnodeOut_0_REG_1 : UInt, clock connect intnodeOut_0_REG_1, fanin_1.io.max node _intnodeOut_0_T_1 = gt(intnodeOut_0_REG_1, threshold[1]) connect x1_intnodeOut[0], _intnodeOut_0_T_1 wire claimer : UInt<1>[2] node _T = cat(claimer[1], claimer[0]) node _T_1 = cat(claimer[1], claimer[0]) node _T_2 = sub(_T_1, UInt<1>(0h1)) node _T_3 = tail(_T_2, 1) node _T_4 = and(_T, _T_3) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Plic.scala:251 assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot\n") : printf assert(clock, _T_5, UInt<1>(0h1), "") : assert node _claiming_T = mux(claimer[0], maxDevs[0], UInt<1>(0h0)) node _claiming_T_1 = mux(claimer[1], maxDevs[1], UInt<1>(0h0)) node claiming = or(_claiming_T, _claiming_T_1) node claimedDevs_shiftAmount = bits(claiming, 1, 0) node _claimedDevs_T = dshl(UInt<1>(0h1), claimedDevs_shiftAmount) node _claimedDevs_T_1 = bits(_claimedDevs_T, 2, 0) node _claimedDevs_T_2 = bits(_claimedDevs_T_1, 0, 0) node _claimedDevs_T_3 = bits(_claimedDevs_T_1, 1, 1) node _claimedDevs_T_4 = bits(_claimedDevs_T_1, 2, 2) wire claimedDevs : UInt<1>[3] connect claimedDevs[0], _claimedDevs_T_2 connect claimedDevs[1], _claimedDevs_T_3 connect claimedDevs[2], _claimedDevs_T_4 node _gateway_io_plic_ready_T = eq(pending[0], UInt<1>(0h0)) connect gateways_gateway.io.plic.ready, _gateway_io_plic_ready_T node _T_9 = or(claimedDevs[1], gateways_gateway.io.plic.valid) when _T_9 : node _pending_0_T = eq(claimedDevs[1], UInt<1>(0h0)) connect pending[0], _pending_0_T node _gateway_io_plic_ready_T_1 = eq(pending[1], UInt<1>(0h0)) connect gateways_gateway_1.io.plic.ready, _gateway_io_plic_ready_T_1 node _T_10 = or(claimedDevs[2], gateways_gateway_1.io.plic.valid) when _T_10 : node _pending_1_T = eq(claimedDevs[2], UInt<1>(0h0)) connect pending[1], _pending_1_T wire completer : UInt<1>[2] node _T_11 = cat(completer[1], completer[0]) node _T_12 = cat(completer[1], completer[0]) node _T_13 = sub(_T_12, UInt<1>(0h1)) node _T_14 = tail(_T_13, 1) node _T_15 = and(_T_11, _T_14) node _T_16 = eq(_T_15, UInt<1>(0h0)) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Plic.scala:268 assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 wire completerDev : UInt<2> node _completedDevs_T = or(completer[0], completer[1]) node completedDevs_shiftAmount = bits(completerDev, 1, 0) node _completedDevs_T_1 = dshl(UInt<1>(0h1), completedDevs_shiftAmount) node _completedDevs_T_2 = bits(_completedDevs_T_1, 2, 0) node completedDevs = mux(_completedDevs_T, _completedDevs_T_2, UInt<1>(0h0)) node _T_20 = bits(completedDevs, 0, 0) node _T_21 = bits(completedDevs, 1, 1) node _T_22 = bits(completedDevs, 2, 2) connect gateways_gateway.io.plic.complete, _T_21 connect gateways_gateway_1.io.plic.complete, _T_22 wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}} connect out_front.bits, in.bits inst out_back_front_q of Queue1_RegMapperInput_i23_m8 connect out_back_front_q.clock, clock connect out_back_front_q.reset, reset connect out_back_front_q.io.enq, out_front node out_maskMatch = not(UInt<23>(0h40611)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<23>(0h0)) node _out_T_1 = eq(out_bindex, UInt<23>(0h0)) node _out_T_2 = eq(out_findex, UInt<23>(0h0)) node _out_T_3 = eq(out_bindex, UInt<23>(0h0)) node _out_T_4 = eq(out_findex, UInt<23>(0h0)) node _out_T_5 = eq(out_bindex, UInt<23>(0h0)) node _out_T_6 = eq(out_findex, UInt<23>(0h0)) node _out_T_7 = eq(out_bindex, UInt<23>(0h0)) node _out_T_8 = eq(out_findex, UInt<23>(0h0)) node _out_T_9 = eq(out_bindex, UInt<23>(0h0)) node _out_T_10 = eq(out_findex, UInt<23>(0h0)) node _out_T_11 = eq(out_bindex, UInt<23>(0h0)) node _out_T_12 = eq(out_findex, UInt<23>(0h0)) node _out_T_13 = eq(out_bindex, UInt<23>(0h0)) wire out_rivalid : UInt<1>[15] wire out_wivalid : UInt<1>[15] wire out_roready : UInt<1>[15] wire out_woready : UInt<1>[15] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_14 = bits(out_back_front_q.io.deq.bits.data, 0, 0) node _out_T_15 = and(out_f_rivalid, UInt<1>(0h1)) node _out_T_16 = and(UInt<1>(0h1), out_f_roready) node _out_T_17 = eq(out_rimask, UInt<1>(0h0)) node _out_T_18 = eq(out_wimask, UInt<1>(0h0)) node _out_T_19 = eq(out_romask, UInt<1>(0h0)) node _out_T_20 = eq(out_womask, UInt<1>(0h0)) node _out_T_21 = or(UInt<1>(0h0), UInt<1>(0h0)) node _out_T_22 = bits(_out_T_21, 0, 0) node _out_rimask_T_1 = bits(out_frontMask, 2, 1) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 2, 1) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 2, 1) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 2, 1) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_23 = bits(out_back_front_q.io.deq.bits.data, 2, 1) when out_f_woready_1 : connect enables_1_0, _out_T_23 node _out_T_24 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_25 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_26 = and(out_f_wivalid_1, UInt<1>(0h1)) node _out_T_27 = and(UInt<1>(0h1), out_f_woready_1) node _out_T_28 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_29 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_30 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_31 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_22, UInt<1>(0h0)) node out_prepend = cat(enables_1_0, _out_prepend_T) node _out_T_32 = or(out_prepend, UInt<3>(0h0)) node _out_T_33 = bits(_out_T_32, 2, 0) node _out_rimask_T_2 = bits(out_frontMask, 1, 0) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 1, 0) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 1, 0) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 1, 0) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_34 = bits(out_back_front_q.io.deq.bits.data, 1, 0) when out_f_woready_2 : connect priority[1], _out_T_34 node _out_T_35 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_36 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_37 = and(out_f_wivalid_2, UInt<1>(0h1)) node _out_T_38 = and(UInt<1>(0h1), out_f_woready_2) node _out_T_39 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_40 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_41 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_42 = eq(out_womask_2, UInt<1>(0h0)) node _out_T_43 = or(priority[1], UInt<2>(0h0)) node _out_T_44 = bits(_out_T_43, 1, 0) node _out_rimask_T_3 = bits(out_frontMask, 0, 0) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 0, 0) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 0, 0) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 0, 0) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_45 = bits(out_back_front_q.io.deq.bits.data, 0, 0) node _out_T_46 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_47 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_48 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_49 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_50 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_51 = eq(out_womask_3, UInt<1>(0h0)) node _out_T_52 = or(UInt<1>(0h0), UInt<1>(0h0)) node _out_T_53 = bits(_out_T_52, 0, 0) node _out_rimask_T_4 = bits(out_frontMask, 1, 1) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 1, 1) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 1, 1) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 1, 1) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_54 = bits(out_back_front_q.io.deq.bits.data, 1, 1) node _out_T_55 = and(out_f_rivalid_4, UInt<1>(0h1)) node _out_T_56 = and(UInt<1>(0h1), out_f_roready_4) node _out_T_57 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_58 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_59 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_60 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_53, UInt<1>(0h0)) node out_prepend_1 = cat(pending[0], _out_prepend_T_1) node _out_T_61 = or(out_prepend_1, UInt<2>(0h0)) node _out_T_62 = bits(_out_T_61, 1, 0) node _out_rimask_T_5 = bits(out_frontMask, 2, 2) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 2, 2) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 2, 2) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 2, 2) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_63 = bits(out_back_front_q.io.deq.bits.data, 2, 2) node _out_T_64 = and(out_f_rivalid_5, UInt<1>(0h1)) node _out_T_65 = and(UInt<1>(0h1), out_f_roready_5) node _out_T_66 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_67 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_68 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_69 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_62, UInt<2>(0h0)) node out_prepend_2 = cat(pending[1], _out_prepend_T_2) node _out_T_70 = or(out_prepend_2, UInt<3>(0h0)) node _out_T_71 = bits(_out_T_70, 2, 0) node _out_rimask_T_6 = bits(out_frontMask, 1, 0) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 1, 0) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 1, 0) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 1, 0) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_72 = bits(out_back_front_q.io.deq.bits.data, 1, 0) when out_f_woready_6 : connect threshold[1], _out_T_72 node _out_T_73 = and(out_f_rivalid_6, UInt<1>(0h1)) node _out_T_74 = and(UInt<1>(0h1), out_f_roready_6) node _out_T_75 = and(out_f_wivalid_6, UInt<1>(0h1)) node _out_T_76 = and(UInt<1>(0h1), out_f_woready_6) node _out_T_77 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_78 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_79 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_80 = eq(out_womask_6, UInt<1>(0h0)) node _out_T_81 = or(threshold[1], UInt<2>(0h0)) node _out_T_82 = bits(_out_T_81, 1, 0) node _out_rimask_T_7 = bits(out_frontMask, 31, 2) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 31, 2) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 31, 2) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 31, 2) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_83 = bits(out_back_front_q.io.deq.bits.data, 31, 2) node _out_T_84 = and(out_f_rivalid_7, UInt<1>(0h1)) node _out_T_85 = and(UInt<1>(0h1), out_f_roready_7) node _out_T_86 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_87 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_88 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_89 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_82, UInt<2>(0h0)) node out_prepend_3 = cat(UInt<1>(0h0), _out_prepend_T_3) node _out_T_90 = or(out_prepend_3, UInt<32>(0h0)) node _out_T_91 = bits(_out_T_90, 31, 0) node _out_rimask_T_8 = bits(out_frontMask, 63, 32) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 63, 32) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 63, 32) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 63, 32) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) connect claimer[1], out_f_roready_8 node _out_T_92 = bits(out_back_front_q.io.deq.bits.data, 63, 32) node _out_T_93 = bits(_out_T_92, 1, 0) node _out_T_94 = eq(completerDev, _out_T_93) node _out_T_95 = asUInt(reset) node _out_T_96 = eq(_out_T_95, UInt<1>(0h0)) when _out_T_96 : node _out_T_97 = eq(_out_T_94, UInt<1>(0h0)) when _out_T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:298 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n") : out_printf assert(clock, _out_T_94, UInt<1>(0h1), "") : out_assert node _out_completerDev_T = bits(_out_T_92, 1, 0) connect completerDev, _out_completerDev_T node _out_completer_1_T = dshr(enableVec0[1], completerDev) node _out_completer_1_T_1 = bits(_out_completer_1_T, 0, 0) node _out_completer_1_T_2 = and(out_f_woready_8, _out_completer_1_T_1) connect completer[1], _out_completer_1_T_2 node _out_T_98 = and(out_f_rivalid_8, UInt<1>(0h1)) node _out_T_99 = and(UInt<1>(0h1), out_f_roready_8) node _out_T_100 = and(out_f_wivalid_8, UInt<1>(0h1)) node _out_T_101 = and(UInt<1>(0h1), out_f_woready_8) node _out_T_102 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_103 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_104 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_105 = eq(out_womask_8, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_91, UInt<32>(0h0)) node out_prepend_4 = cat(maxDevs[1], _out_prepend_T_4) node _out_T_106 = or(out_prepend_4, UInt<64>(0h0)) node _out_T_107 = bits(_out_T_106, 63, 0) node _out_rimask_T_9 = bits(out_frontMask, 1, 0) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 1, 0) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 1, 0) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 1, 0) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) node _out_T_108 = bits(out_back_front_q.io.deq.bits.data, 1, 0) when out_f_woready_9 : connect threshold[0], _out_T_108 node _out_T_109 = and(out_f_rivalid_9, UInt<1>(0h1)) node _out_T_110 = and(UInt<1>(0h1), out_f_roready_9) node _out_T_111 = and(out_f_wivalid_9, UInt<1>(0h1)) node _out_T_112 = and(UInt<1>(0h1), out_f_woready_9) node _out_T_113 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_114 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_115 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_116 = eq(out_womask_9, UInt<1>(0h0)) node _out_T_117 = or(threshold[0], UInt<2>(0h0)) node _out_T_118 = bits(_out_T_117, 1, 0) node _out_rimask_T_10 = bits(out_frontMask, 31, 2) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 31, 2) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 31, 2) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 31, 2) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) node _out_T_119 = bits(out_back_front_q.io.deq.bits.data, 31, 2) node _out_T_120 = and(out_f_rivalid_10, UInt<1>(0h1)) node _out_T_121 = and(UInt<1>(0h1), out_f_roready_10) node _out_T_122 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_123 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_124 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_125 = eq(out_womask_10, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_118, UInt<2>(0h0)) node out_prepend_5 = cat(UInt<1>(0h0), _out_prepend_T_5) node _out_T_126 = or(out_prepend_5, UInt<32>(0h0)) node _out_T_127 = bits(_out_T_126, 31, 0) node _out_rimask_T_11 = bits(out_frontMask, 63, 32) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 63, 32) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 63, 32) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 63, 32) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) connect claimer[0], out_f_roready_11 node _out_T_128 = bits(out_back_front_q.io.deq.bits.data, 63, 32) node _out_T_129 = bits(_out_T_128, 1, 0) node _out_T_130 = eq(completerDev, _out_T_129) node _out_T_131 = asUInt(reset) node _out_T_132 = eq(_out_T_131, UInt<1>(0h0)) when _out_T_132 : node _out_T_133 = eq(_out_T_130, UInt<1>(0h0)) when _out_T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:298 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n") : out_printf_1 assert(clock, _out_T_130, UInt<1>(0h1), "") : out_assert_1 node _out_completerDev_T_1 = bits(_out_T_128, 1, 0) connect completerDev, _out_completerDev_T_1 node _out_completer_0_T = dshr(enableVec0[0], completerDev) node _out_completer_0_T_1 = bits(_out_completer_0_T, 0, 0) node _out_completer_0_T_2 = and(out_f_woready_11, _out_completer_0_T_1) connect completer[0], _out_completer_0_T_2 node _out_T_134 = and(out_f_rivalid_11, UInt<1>(0h1)) node _out_T_135 = and(UInt<1>(0h1), out_f_roready_11) node _out_T_136 = and(out_f_wivalid_11, UInt<1>(0h1)) node _out_T_137 = and(UInt<1>(0h1), out_f_woready_11) node _out_T_138 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_139 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_140 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_141 = eq(out_womask_11, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_127, UInt<32>(0h0)) node out_prepend_6 = cat(maxDevs[0], _out_prepend_T_6) node _out_T_142 = or(out_prepend_6, UInt<64>(0h0)) node _out_T_143 = bits(_out_T_142, 63, 0) node _out_rimask_T_12 = bits(out_frontMask, 0, 0) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 0, 0) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 0, 0) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 0, 0) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_144 = bits(out_back_front_q.io.deq.bits.data, 0, 0) node _out_T_145 = and(out_f_rivalid_12, UInt<1>(0h1)) node _out_T_146 = and(UInt<1>(0h1), out_f_roready_12) node _out_T_147 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_148 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_149 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_150 = eq(out_womask_12, UInt<1>(0h0)) node _out_T_151 = or(UInt<1>(0h0), UInt<1>(0h0)) node _out_T_152 = bits(_out_T_151, 0, 0) node _out_rimask_T_13 = bits(out_frontMask, 2, 1) node out_rimask_13 = orr(_out_rimask_T_13) node _out_wimask_T_13 = bits(out_frontMask, 2, 1) node out_wimask_13 = andr(_out_wimask_T_13) node _out_romask_T_13 = bits(out_backMask, 2, 1) node out_romask_13 = orr(_out_romask_T_13) node _out_womask_T_13 = bits(out_backMask, 2, 1) node out_womask_13 = andr(_out_womask_T_13) node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) node out_f_roready_13 = and(out_roready[13], out_romask_13) node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) node out_f_woready_13 = and(out_woready[13], out_womask_13) node _out_T_153 = bits(out_back_front_q.io.deq.bits.data, 2, 1) when out_f_woready_13 : connect enables_0_0, _out_T_153 node _out_T_154 = and(out_f_rivalid_13, UInt<1>(0h1)) node _out_T_155 = and(UInt<1>(0h1), out_f_roready_13) node _out_T_156 = and(out_f_wivalid_13, UInt<1>(0h1)) node _out_T_157 = and(UInt<1>(0h1), out_f_woready_13) node _out_T_158 = eq(out_rimask_13, UInt<1>(0h0)) node _out_T_159 = eq(out_wimask_13, UInt<1>(0h0)) node _out_T_160 = eq(out_romask_13, UInt<1>(0h0)) node _out_T_161 = eq(out_womask_13, UInt<1>(0h0)) node _out_prepend_T_7 = or(_out_T_152, UInt<1>(0h0)) node out_prepend_7 = cat(enables_0_0, _out_prepend_T_7) node _out_T_162 = or(out_prepend_7, UInt<3>(0h0)) node _out_T_163 = bits(_out_T_162, 2, 0) node _out_rimask_T_14 = bits(out_frontMask, 33, 32) node out_rimask_14 = orr(_out_rimask_T_14) node _out_wimask_T_14 = bits(out_frontMask, 33, 32) node out_wimask_14 = andr(_out_wimask_T_14) node _out_romask_T_14 = bits(out_backMask, 33, 32) node out_romask_14 = orr(_out_romask_T_14) node _out_womask_T_14 = bits(out_backMask, 33, 32) node out_womask_14 = andr(_out_womask_T_14) node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) node out_f_roready_14 = and(out_roready[14], out_romask_14) node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) node out_f_woready_14 = and(out_woready[14], out_womask_14) node _out_T_164 = bits(out_back_front_q.io.deq.bits.data, 33, 32) when out_f_woready_14 : connect priority[0], _out_T_164 node _out_T_165 = and(out_f_rivalid_14, UInt<1>(0h1)) node _out_T_166 = and(UInt<1>(0h1), out_f_roready_14) node _out_T_167 = and(out_f_wivalid_14, UInt<1>(0h1)) node _out_T_168 = and(UInt<1>(0h1), out_f_woready_14) node _out_T_169 = eq(out_rimask_14, UInt<1>(0h0)) node _out_T_170 = eq(out_wimask_14, UInt<1>(0h0)) node _out_T_171 = eq(out_romask_14, UInt<1>(0h0)) node _out_T_172 = eq(out_womask_14, UInt<1>(0h0)) node _out_prepend_T_8 = or(UInt<1>(0h0), UInt<32>(0h0)) node out_prepend_8 = cat(priority[0], _out_prepend_T_8) node _out_T_173 = or(out_prepend_8, UInt<34>(0h0)) node _out_T_174 = bits(_out_T_173, 33, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node _out_iindex_T_9 = bits(out_front.bits.index, 9, 9) node _out_iindex_T_10 = bits(out_front.bits.index, 10, 10) node _out_iindex_T_11 = bits(out_front.bits.index, 11, 11) node _out_iindex_T_12 = bits(out_front.bits.index, 12, 12) node _out_iindex_T_13 = bits(out_front.bits.index, 13, 13) node _out_iindex_T_14 = bits(out_front.bits.index, 14, 14) node _out_iindex_T_15 = bits(out_front.bits.index, 15, 15) node _out_iindex_T_16 = bits(out_front.bits.index, 16, 16) node _out_iindex_T_17 = bits(out_front.bits.index, 17, 17) node _out_iindex_T_18 = bits(out_front.bits.index, 18, 18) node _out_iindex_T_19 = bits(out_front.bits.index, 19, 19) node _out_iindex_T_20 = bits(out_front.bits.index, 20, 20) node _out_iindex_T_21 = bits(out_front.bits.index, 21, 21) node _out_iindex_T_22 = bits(out_front.bits.index, 22, 22) node out_iindex_lo = cat(_out_iindex_T_4, _out_iindex_T) node out_iindex_hi_hi = cat(_out_iindex_T_18, _out_iindex_T_10) node out_iindex_hi = cat(out_iindex_hi_hi, _out_iindex_T_9) node out_iindex = cat(out_iindex_hi, out_iindex_lo) node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_back_front_q.io.deq.bits.index, 8, 8) node _out_oindex_T_9 = bits(out_back_front_q.io.deq.bits.index, 9, 9) node _out_oindex_T_10 = bits(out_back_front_q.io.deq.bits.index, 10, 10) node _out_oindex_T_11 = bits(out_back_front_q.io.deq.bits.index, 11, 11) node _out_oindex_T_12 = bits(out_back_front_q.io.deq.bits.index, 12, 12) node _out_oindex_T_13 = bits(out_back_front_q.io.deq.bits.index, 13, 13) node _out_oindex_T_14 = bits(out_back_front_q.io.deq.bits.index, 14, 14) node _out_oindex_T_15 = bits(out_back_front_q.io.deq.bits.index, 15, 15) node _out_oindex_T_16 = bits(out_back_front_q.io.deq.bits.index, 16, 16) node _out_oindex_T_17 = bits(out_back_front_q.io.deq.bits.index, 17, 17) node _out_oindex_T_18 = bits(out_back_front_q.io.deq.bits.index, 18, 18) node _out_oindex_T_19 = bits(out_back_front_q.io.deq.bits.index, 19, 19) node _out_oindex_T_20 = bits(out_back_front_q.io.deq.bits.index, 20, 20) node _out_oindex_T_21 = bits(out_back_front_q.io.deq.bits.index, 21, 21) node _out_oindex_T_22 = bits(out_back_front_q.io.deq.bits.index, 22, 22) node out_oindex_lo = cat(_out_oindex_T_4, _out_oindex_T) node out_oindex_hi_hi = cat(_out_oindex_T_18, _out_oindex_T_10) node out_oindex_hi = cat(out_oindex_hi_hi, _out_oindex_T_9) node out_oindex = cat(out_oindex_hi, out_oindex_lo) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node out_frontSel_4 = bits(_out_frontSel_T, 4, 4) node out_frontSel_5 = bits(_out_frontSel_T, 5, 5) node out_frontSel_6 = bits(_out_frontSel_T, 6, 6) node out_frontSel_7 = bits(_out_frontSel_T, 7, 7) node out_frontSel_8 = bits(_out_frontSel_T, 8, 8) node out_frontSel_9 = bits(_out_frontSel_T, 9, 9) node out_frontSel_10 = bits(_out_frontSel_T, 10, 10) node out_frontSel_11 = bits(_out_frontSel_T, 11, 11) node out_frontSel_12 = bits(_out_frontSel_T, 12, 12) node out_frontSel_13 = bits(_out_frontSel_T, 13, 13) node out_frontSel_14 = bits(_out_frontSel_T, 14, 14) node out_frontSel_15 = bits(_out_frontSel_T, 15, 15) node out_frontSel_16 = bits(_out_frontSel_T, 16, 16) node out_frontSel_17 = bits(_out_frontSel_T, 17, 17) node out_frontSel_18 = bits(_out_frontSel_T, 18, 18) node out_frontSel_19 = bits(_out_frontSel_T, 19, 19) node out_frontSel_20 = bits(_out_frontSel_T, 20, 20) node out_frontSel_21 = bits(_out_frontSel_T, 21, 21) node out_frontSel_22 = bits(_out_frontSel_T, 22, 22) node out_frontSel_23 = bits(_out_frontSel_T, 23, 23) node out_frontSel_24 = bits(_out_frontSel_T, 24, 24) node out_frontSel_25 = bits(_out_frontSel_T, 25, 25) node out_frontSel_26 = bits(_out_frontSel_T, 26, 26) node out_frontSel_27 = bits(_out_frontSel_T, 27, 27) node out_frontSel_28 = bits(_out_frontSel_T, 28, 28) node out_frontSel_29 = bits(_out_frontSel_T, 29, 29) node out_frontSel_30 = bits(_out_frontSel_T, 30, 30) node out_frontSel_31 = bits(_out_frontSel_T, 31, 31) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node out_backSel_4 = bits(_out_backSel_T, 4, 4) node out_backSel_5 = bits(_out_backSel_T, 5, 5) node out_backSel_6 = bits(_out_backSel_T, 6, 6) node out_backSel_7 = bits(_out_backSel_T, 7, 7) node out_backSel_8 = bits(_out_backSel_T, 8, 8) node out_backSel_9 = bits(_out_backSel_T, 9, 9) node out_backSel_10 = bits(_out_backSel_T, 10, 10) node out_backSel_11 = bits(_out_backSel_T, 11, 11) node out_backSel_12 = bits(_out_backSel_T, 12, 12) node out_backSel_13 = bits(_out_backSel_T, 13, 13) node out_backSel_14 = bits(_out_backSel_T, 14, 14) node out_backSel_15 = bits(_out_backSel_T, 15, 15) node out_backSel_16 = bits(_out_backSel_T, 16, 16) node out_backSel_17 = bits(_out_backSel_T, 17, 17) node out_backSel_18 = bits(_out_backSel_T, 18, 18) node out_backSel_19 = bits(_out_backSel_T, 19, 19) node out_backSel_20 = bits(_out_backSel_T, 20, 20) node out_backSel_21 = bits(_out_backSel_T, 21, 21) node out_backSel_22 = bits(_out_backSel_T, 22, 22) node out_backSel_23 = bits(_out_backSel_T, 23, 23) node out_backSel_24 = bits(_out_backSel_T, 24, 24) node out_backSel_25 = bits(_out_backSel_T, 25, 25) node out_backSel_26 = bits(_out_backSel_T, 26, 26) node out_backSel_27 = bits(_out_backSel_T, 27, 27) node out_backSel_28 = bits(_out_backSel_T, 28, 28) node out_backSel_29 = bits(_out_backSel_T, 29, 29) node out_backSel_30 = bits(_out_backSel_T, 30, 30) node out_backSel_31 = bits(_out_backSel_T, 31, 31) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T_12) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[14], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T_12, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[2], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, UInt<1>(0h1)) connect out_rifireMux_out_2, UInt<1>(0h1) node _out_rifireMux_T_12 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, UInt<1>(0h1)) connect out_rifireMux_out_3, UInt<1>(0h1) node _out_rifireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) wire out_rifireMux_out_4 : UInt<1> node _out_rifireMux_T_18 = and(_out_rifireMux_T_1, out_frontSel_4) node _out_rifireMux_T_19 = and(_out_rifireMux_T_18, _out_T_4) connect out_rifireMux_out_4, UInt<1>(0h1) connect out_rivalid[5], _out_rifireMux_T_19 connect out_rivalid[4], _out_rifireMux_T_19 connect out_rivalid[3], _out_rifireMux_T_19 node _out_rifireMux_T_20 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_21 = or(out_rifireMux_out_4, _out_rifireMux_T_20) wire out_rifireMux_out_5 : UInt<1> node _out_rifireMux_T_22 = and(_out_rifireMux_T_1, out_frontSel_5) node _out_rifireMux_T_23 = and(_out_rifireMux_T_22, UInt<1>(0h1)) connect out_rifireMux_out_5, UInt<1>(0h1) node _out_rifireMux_T_24 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_25 = or(out_rifireMux_out_5, _out_rifireMux_T_24) wire out_rifireMux_out_6 : UInt<1> node _out_rifireMux_T_26 = and(_out_rifireMux_T_1, out_frontSel_6) node _out_rifireMux_T_27 = and(_out_rifireMux_T_26, UInt<1>(0h1)) connect out_rifireMux_out_6, UInt<1>(0h1) node _out_rifireMux_T_28 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_29 = or(out_rifireMux_out_6, _out_rifireMux_T_28) wire out_rifireMux_out_7 : UInt<1> node _out_rifireMux_T_30 = and(_out_rifireMux_T_1, out_frontSel_7) node _out_rifireMux_T_31 = and(_out_rifireMux_T_30, UInt<1>(0h1)) connect out_rifireMux_out_7, UInt<1>(0h1) node _out_rifireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_33 = or(out_rifireMux_out_7, _out_rifireMux_T_32) wire out_rifireMux_out_8 : UInt<1> node _out_rifireMux_T_34 = and(_out_rifireMux_T_1, out_frontSel_8) node _out_rifireMux_T_35 = and(_out_rifireMux_T_34, _out_T_10) connect out_rifireMux_out_8, UInt<1>(0h1) connect out_rivalid[13], _out_rifireMux_T_35 connect out_rivalid[12], _out_rifireMux_T_35 node _out_rifireMux_T_36 = eq(_out_T_10, UInt<1>(0h0)) node _out_rifireMux_T_37 = or(out_rifireMux_out_8, _out_rifireMux_T_36) wire out_rifireMux_out_9 : UInt<1> node _out_rifireMux_T_38 = and(_out_rifireMux_T_1, out_frontSel_9) node _out_rifireMux_T_39 = and(_out_rifireMux_T_38, UInt<1>(0h1)) connect out_rifireMux_out_9, UInt<1>(0h1) node _out_rifireMux_T_40 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_41 = or(out_rifireMux_out_9, _out_rifireMux_T_40) wire out_rifireMux_out_10 : UInt<1> node _out_rifireMux_T_42 = and(_out_rifireMux_T_1, out_frontSel_10) node _out_rifireMux_T_43 = and(_out_rifireMux_T_42, _out_T) connect out_rifireMux_out_10, UInt<1>(0h1) connect out_rivalid[1], _out_rifireMux_T_43 connect out_rivalid[0], _out_rifireMux_T_43 node _out_rifireMux_T_44 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_45 = or(out_rifireMux_out_10, _out_rifireMux_T_44) wire out_rifireMux_out_11 : UInt<1> node _out_rifireMux_T_46 = and(_out_rifireMux_T_1, out_frontSel_11) node _out_rifireMux_T_47 = and(_out_rifireMux_T_46, UInt<1>(0h1)) connect out_rifireMux_out_11, UInt<1>(0h1) node _out_rifireMux_T_48 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_49 = or(out_rifireMux_out_11, _out_rifireMux_T_48) wire out_rifireMux_out_12 : UInt<1> node _out_rifireMux_T_50 = and(_out_rifireMux_T_1, out_frontSel_12) node _out_rifireMux_T_51 = and(_out_rifireMux_T_50, UInt<1>(0h1)) connect out_rifireMux_out_12, UInt<1>(0h1) node _out_rifireMux_T_52 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_53 = or(out_rifireMux_out_12, _out_rifireMux_T_52) wire out_rifireMux_out_13 : UInt<1> node _out_rifireMux_T_54 = and(_out_rifireMux_T_1, out_frontSel_13) node _out_rifireMux_T_55 = and(_out_rifireMux_T_54, UInt<1>(0h1)) connect out_rifireMux_out_13, UInt<1>(0h1) node _out_rifireMux_T_56 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_57 = or(out_rifireMux_out_13, _out_rifireMux_T_56) wire out_rifireMux_out_14 : UInt<1> node _out_rifireMux_T_58 = and(_out_rifireMux_T_1, out_frontSel_14) node _out_rifireMux_T_59 = and(_out_rifireMux_T_58, UInt<1>(0h1)) connect out_rifireMux_out_14, UInt<1>(0h1) node _out_rifireMux_T_60 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_61 = or(out_rifireMux_out_14, _out_rifireMux_T_60) wire out_rifireMux_out_15 : UInt<1> node _out_rifireMux_T_62 = and(_out_rifireMux_T_1, out_frontSel_15) node _out_rifireMux_T_63 = and(_out_rifireMux_T_62, UInt<1>(0h1)) connect out_rifireMux_out_15, UInt<1>(0h1) node _out_rifireMux_T_64 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_65 = or(out_rifireMux_out_15, _out_rifireMux_T_64) wire out_rifireMux_out_16 : UInt<1> node _out_rifireMux_T_66 = and(_out_rifireMux_T_1, out_frontSel_16) node _out_rifireMux_T_67 = and(_out_rifireMux_T_66, _out_T_8) connect out_rifireMux_out_16, UInt<1>(0h1) connect out_rivalid[11], _out_rifireMux_T_67 connect out_rivalid[10], _out_rifireMux_T_67 connect out_rivalid[9], _out_rifireMux_T_67 node _out_rifireMux_T_68 = eq(_out_T_8, UInt<1>(0h0)) node _out_rifireMux_T_69 = or(out_rifireMux_out_16, _out_rifireMux_T_68) wire out_rifireMux_out_17 : UInt<1> node _out_rifireMux_T_70 = and(_out_rifireMux_T_1, out_frontSel_17) node _out_rifireMux_T_71 = and(_out_rifireMux_T_70, UInt<1>(0h1)) connect out_rifireMux_out_17, UInt<1>(0h1) node _out_rifireMux_T_72 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_73 = or(out_rifireMux_out_17, _out_rifireMux_T_72) wire out_rifireMux_out_18 : UInt<1> node _out_rifireMux_T_74 = and(_out_rifireMux_T_1, out_frontSel_18) node _out_rifireMux_T_75 = and(_out_rifireMux_T_74, UInt<1>(0h1)) connect out_rifireMux_out_18, UInt<1>(0h1) node _out_rifireMux_T_76 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_77 = or(out_rifireMux_out_18, _out_rifireMux_T_76) wire out_rifireMux_out_19 : UInt<1> node _out_rifireMux_T_78 = and(_out_rifireMux_T_1, out_frontSel_19) node _out_rifireMux_T_79 = and(_out_rifireMux_T_78, UInt<1>(0h1)) connect out_rifireMux_out_19, UInt<1>(0h1) node _out_rifireMux_T_80 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_81 = or(out_rifireMux_out_19, _out_rifireMux_T_80) wire out_rifireMux_out_20 : UInt<1> node _out_rifireMux_T_82 = and(_out_rifireMux_T_1, out_frontSel_20) node _out_rifireMux_T_83 = and(_out_rifireMux_T_82, _out_T_6) connect out_rifireMux_out_20, UInt<1>(0h1) connect out_rivalid[8], _out_rifireMux_T_83 connect out_rivalid[7], _out_rifireMux_T_83 connect out_rivalid[6], _out_rifireMux_T_83 node _out_rifireMux_T_84 = eq(_out_T_6, UInt<1>(0h0)) node _out_rifireMux_T_85 = or(out_rifireMux_out_20, _out_rifireMux_T_84) wire out_rifireMux_out_21 : UInt<1> node _out_rifireMux_T_86 = and(_out_rifireMux_T_1, out_frontSel_21) node _out_rifireMux_T_87 = and(_out_rifireMux_T_86, UInt<1>(0h1)) connect out_rifireMux_out_21, UInt<1>(0h1) node _out_rifireMux_T_88 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_89 = or(out_rifireMux_out_21, _out_rifireMux_T_88) wire out_rifireMux_out_22 : UInt<1> node _out_rifireMux_T_90 = and(_out_rifireMux_T_1, out_frontSel_22) node _out_rifireMux_T_91 = and(_out_rifireMux_T_90, UInt<1>(0h1)) connect out_rifireMux_out_22, UInt<1>(0h1) node _out_rifireMux_T_92 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_93 = or(out_rifireMux_out_22, _out_rifireMux_T_92) wire out_rifireMux_out_23 : UInt<1> node _out_rifireMux_T_94 = and(_out_rifireMux_T_1, out_frontSel_23) node _out_rifireMux_T_95 = and(_out_rifireMux_T_94, UInt<1>(0h1)) connect out_rifireMux_out_23, UInt<1>(0h1) node _out_rifireMux_T_96 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_97 = or(out_rifireMux_out_23, _out_rifireMux_T_96) wire out_rifireMux_out_24 : UInt<1> node _out_rifireMux_T_98 = and(_out_rifireMux_T_1, out_frontSel_24) node _out_rifireMux_T_99 = and(_out_rifireMux_T_98, UInt<1>(0h1)) connect out_rifireMux_out_24, UInt<1>(0h1) node _out_rifireMux_T_100 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_101 = or(out_rifireMux_out_24, _out_rifireMux_T_100) wire out_rifireMux_out_25 : UInt<1> node _out_rifireMux_T_102 = and(_out_rifireMux_T_1, out_frontSel_25) node _out_rifireMux_T_103 = and(_out_rifireMux_T_102, UInt<1>(0h1)) connect out_rifireMux_out_25, UInt<1>(0h1) node _out_rifireMux_T_104 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_105 = or(out_rifireMux_out_25, _out_rifireMux_T_104) wire out_rifireMux_out_26 : UInt<1> node _out_rifireMux_T_106 = and(_out_rifireMux_T_1, out_frontSel_26) node _out_rifireMux_T_107 = and(_out_rifireMux_T_106, UInt<1>(0h1)) connect out_rifireMux_out_26, UInt<1>(0h1) node _out_rifireMux_T_108 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_109 = or(out_rifireMux_out_26, _out_rifireMux_T_108) wire out_rifireMux_out_27 : UInt<1> node _out_rifireMux_T_110 = and(_out_rifireMux_T_1, out_frontSel_27) node _out_rifireMux_T_111 = and(_out_rifireMux_T_110, UInt<1>(0h1)) connect out_rifireMux_out_27, UInt<1>(0h1) node _out_rifireMux_T_112 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_113 = or(out_rifireMux_out_27, _out_rifireMux_T_112) wire out_rifireMux_out_28 : UInt<1> node _out_rifireMux_T_114 = and(_out_rifireMux_T_1, out_frontSel_28) node _out_rifireMux_T_115 = and(_out_rifireMux_T_114, UInt<1>(0h1)) connect out_rifireMux_out_28, UInt<1>(0h1) node _out_rifireMux_T_116 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_117 = or(out_rifireMux_out_28, _out_rifireMux_T_116) wire out_rifireMux_out_29 : UInt<1> node _out_rifireMux_T_118 = and(_out_rifireMux_T_1, out_frontSel_29) node _out_rifireMux_T_119 = and(_out_rifireMux_T_118, UInt<1>(0h1)) connect out_rifireMux_out_29, UInt<1>(0h1) node _out_rifireMux_T_120 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_121 = or(out_rifireMux_out_29, _out_rifireMux_T_120) wire out_rifireMux_out_30 : UInt<1> node _out_rifireMux_T_122 = and(_out_rifireMux_T_1, out_frontSel_30) node _out_rifireMux_T_123 = and(_out_rifireMux_T_122, UInt<1>(0h1)) connect out_rifireMux_out_30, UInt<1>(0h1) node _out_rifireMux_T_124 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_125 = or(out_rifireMux_out_30, _out_rifireMux_T_124) wire out_rifireMux_out_31 : UInt<1> node _out_rifireMux_T_126 = and(_out_rifireMux_T_1, out_frontSel_31) node _out_rifireMux_T_127 = and(_out_rifireMux_T_126, UInt<1>(0h1)) connect out_rifireMux_out_31, UInt<1>(0h1) node _out_rifireMux_T_128 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_129 = or(out_rifireMux_out_31, _out_rifireMux_T_128) node _out_rifireMux_T_130 = geq(out_iindex, UInt<6>(0h20)) wire _out_rifireMux_WIRE : UInt<1>[32] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 connect _out_rifireMux_WIRE[4], _out_rifireMux_T_21 connect _out_rifireMux_WIRE[5], _out_rifireMux_T_25 connect _out_rifireMux_WIRE[6], _out_rifireMux_T_29 connect _out_rifireMux_WIRE[7], _out_rifireMux_T_33 connect _out_rifireMux_WIRE[8], _out_rifireMux_T_37 connect _out_rifireMux_WIRE[9], _out_rifireMux_T_41 connect _out_rifireMux_WIRE[10], _out_rifireMux_T_45 connect _out_rifireMux_WIRE[11], _out_rifireMux_T_49 connect _out_rifireMux_WIRE[12], _out_rifireMux_T_53 connect _out_rifireMux_WIRE[13], _out_rifireMux_T_57 connect _out_rifireMux_WIRE[14], _out_rifireMux_T_61 connect _out_rifireMux_WIRE[15], _out_rifireMux_T_65 connect _out_rifireMux_WIRE[16], _out_rifireMux_T_69 connect _out_rifireMux_WIRE[17], _out_rifireMux_T_73 connect _out_rifireMux_WIRE[18], _out_rifireMux_T_77 connect _out_rifireMux_WIRE[19], _out_rifireMux_T_81 connect _out_rifireMux_WIRE[20], _out_rifireMux_T_85 connect _out_rifireMux_WIRE[21], _out_rifireMux_T_89 connect _out_rifireMux_WIRE[22], _out_rifireMux_T_93 connect _out_rifireMux_WIRE[23], _out_rifireMux_T_97 connect _out_rifireMux_WIRE[24], _out_rifireMux_T_101 connect _out_rifireMux_WIRE[25], _out_rifireMux_T_105 connect _out_rifireMux_WIRE[26], _out_rifireMux_T_109 connect _out_rifireMux_WIRE[27], _out_rifireMux_T_113 connect _out_rifireMux_WIRE[28], _out_rifireMux_T_117 connect _out_rifireMux_WIRE[29], _out_rifireMux_T_121 connect _out_rifireMux_WIRE[30], _out_rifireMux_T_125 connect _out_rifireMux_WIRE[31], _out_rifireMux_T_129 node out_rifireMux = mux(_out_rifireMux_T_130, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T_12) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[14], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T_12, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[2], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, UInt<1>(0h1)) connect out_wifireMux_out_2, UInt<1>(0h1) node _out_wifireMux_T_13 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, UInt<1>(0h1)) connect out_wifireMux_out_3, UInt<1>(0h1) node _out_wifireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) wire out_wifireMux_out_4 : UInt<1> node _out_wifireMux_T_19 = and(_out_wifireMux_T_2, out_frontSel_4) node _out_wifireMux_T_20 = and(_out_wifireMux_T_19, _out_T_4) connect out_wifireMux_out_4, UInt<1>(0h1) connect out_wivalid[5], _out_wifireMux_T_20 connect out_wivalid[4], _out_wifireMux_T_20 connect out_wivalid[3], _out_wifireMux_T_20 node _out_wifireMux_T_21 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_22 = or(out_wifireMux_out_4, _out_wifireMux_T_21) wire out_wifireMux_out_5 : UInt<1> node _out_wifireMux_T_23 = and(_out_wifireMux_T_2, out_frontSel_5) node _out_wifireMux_T_24 = and(_out_wifireMux_T_23, UInt<1>(0h1)) connect out_wifireMux_out_5, UInt<1>(0h1) node _out_wifireMux_T_25 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_26 = or(out_wifireMux_out_5, _out_wifireMux_T_25) wire out_wifireMux_out_6 : UInt<1> node _out_wifireMux_T_27 = and(_out_wifireMux_T_2, out_frontSel_6) node _out_wifireMux_T_28 = and(_out_wifireMux_T_27, UInt<1>(0h1)) connect out_wifireMux_out_6, UInt<1>(0h1) node _out_wifireMux_T_29 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_30 = or(out_wifireMux_out_6, _out_wifireMux_T_29) wire out_wifireMux_out_7 : UInt<1> node _out_wifireMux_T_31 = and(_out_wifireMux_T_2, out_frontSel_7) node _out_wifireMux_T_32 = and(_out_wifireMux_T_31, UInt<1>(0h1)) connect out_wifireMux_out_7, UInt<1>(0h1) node _out_wifireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_34 = or(out_wifireMux_out_7, _out_wifireMux_T_33) wire out_wifireMux_out_8 : UInt<1> node _out_wifireMux_T_35 = and(_out_wifireMux_T_2, out_frontSel_8) node _out_wifireMux_T_36 = and(_out_wifireMux_T_35, _out_T_10) connect out_wifireMux_out_8, UInt<1>(0h1) connect out_wivalid[13], _out_wifireMux_T_36 connect out_wivalid[12], _out_wifireMux_T_36 node _out_wifireMux_T_37 = eq(_out_T_10, UInt<1>(0h0)) node _out_wifireMux_T_38 = or(out_wifireMux_out_8, _out_wifireMux_T_37) wire out_wifireMux_out_9 : UInt<1> node _out_wifireMux_T_39 = and(_out_wifireMux_T_2, out_frontSel_9) node _out_wifireMux_T_40 = and(_out_wifireMux_T_39, UInt<1>(0h1)) connect out_wifireMux_out_9, UInt<1>(0h1) node _out_wifireMux_T_41 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_42 = or(out_wifireMux_out_9, _out_wifireMux_T_41) wire out_wifireMux_out_10 : UInt<1> node _out_wifireMux_T_43 = and(_out_wifireMux_T_2, out_frontSel_10) node _out_wifireMux_T_44 = and(_out_wifireMux_T_43, _out_T) connect out_wifireMux_out_10, UInt<1>(0h1) connect out_wivalid[1], _out_wifireMux_T_44 connect out_wivalid[0], _out_wifireMux_T_44 node _out_wifireMux_T_45 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_46 = or(out_wifireMux_out_10, _out_wifireMux_T_45) wire out_wifireMux_out_11 : UInt<1> node _out_wifireMux_T_47 = and(_out_wifireMux_T_2, out_frontSel_11) node _out_wifireMux_T_48 = and(_out_wifireMux_T_47, UInt<1>(0h1)) connect out_wifireMux_out_11, UInt<1>(0h1) node _out_wifireMux_T_49 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_50 = or(out_wifireMux_out_11, _out_wifireMux_T_49) wire out_wifireMux_out_12 : UInt<1> node _out_wifireMux_T_51 = and(_out_wifireMux_T_2, out_frontSel_12) node _out_wifireMux_T_52 = and(_out_wifireMux_T_51, UInt<1>(0h1)) connect out_wifireMux_out_12, UInt<1>(0h1) node _out_wifireMux_T_53 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_54 = or(out_wifireMux_out_12, _out_wifireMux_T_53) wire out_wifireMux_out_13 : UInt<1> node _out_wifireMux_T_55 = and(_out_wifireMux_T_2, out_frontSel_13) node _out_wifireMux_T_56 = and(_out_wifireMux_T_55, UInt<1>(0h1)) connect out_wifireMux_out_13, UInt<1>(0h1) node _out_wifireMux_T_57 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_58 = or(out_wifireMux_out_13, _out_wifireMux_T_57) wire out_wifireMux_out_14 : UInt<1> node _out_wifireMux_T_59 = and(_out_wifireMux_T_2, out_frontSel_14) node _out_wifireMux_T_60 = and(_out_wifireMux_T_59, UInt<1>(0h1)) connect out_wifireMux_out_14, UInt<1>(0h1) node _out_wifireMux_T_61 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_62 = or(out_wifireMux_out_14, _out_wifireMux_T_61) wire out_wifireMux_out_15 : UInt<1> node _out_wifireMux_T_63 = and(_out_wifireMux_T_2, out_frontSel_15) node _out_wifireMux_T_64 = and(_out_wifireMux_T_63, UInt<1>(0h1)) connect out_wifireMux_out_15, UInt<1>(0h1) node _out_wifireMux_T_65 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_66 = or(out_wifireMux_out_15, _out_wifireMux_T_65) wire out_wifireMux_out_16 : UInt<1> node _out_wifireMux_T_67 = and(_out_wifireMux_T_2, out_frontSel_16) node _out_wifireMux_T_68 = and(_out_wifireMux_T_67, _out_T_8) connect out_wifireMux_out_16, UInt<1>(0h1) connect out_wivalid[11], _out_wifireMux_T_68 connect out_wivalid[10], _out_wifireMux_T_68 connect out_wivalid[9], _out_wifireMux_T_68 node _out_wifireMux_T_69 = eq(_out_T_8, UInt<1>(0h0)) node _out_wifireMux_T_70 = or(out_wifireMux_out_16, _out_wifireMux_T_69) wire out_wifireMux_out_17 : UInt<1> node _out_wifireMux_T_71 = and(_out_wifireMux_T_2, out_frontSel_17) node _out_wifireMux_T_72 = and(_out_wifireMux_T_71, UInt<1>(0h1)) connect out_wifireMux_out_17, UInt<1>(0h1) node _out_wifireMux_T_73 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_74 = or(out_wifireMux_out_17, _out_wifireMux_T_73) wire out_wifireMux_out_18 : UInt<1> node _out_wifireMux_T_75 = and(_out_wifireMux_T_2, out_frontSel_18) node _out_wifireMux_T_76 = and(_out_wifireMux_T_75, UInt<1>(0h1)) connect out_wifireMux_out_18, UInt<1>(0h1) node _out_wifireMux_T_77 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_78 = or(out_wifireMux_out_18, _out_wifireMux_T_77) wire out_wifireMux_out_19 : UInt<1> node _out_wifireMux_T_79 = and(_out_wifireMux_T_2, out_frontSel_19) node _out_wifireMux_T_80 = and(_out_wifireMux_T_79, UInt<1>(0h1)) connect out_wifireMux_out_19, UInt<1>(0h1) node _out_wifireMux_T_81 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_82 = or(out_wifireMux_out_19, _out_wifireMux_T_81) wire out_wifireMux_out_20 : UInt<1> node _out_wifireMux_T_83 = and(_out_wifireMux_T_2, out_frontSel_20) node _out_wifireMux_T_84 = and(_out_wifireMux_T_83, _out_T_6) connect out_wifireMux_out_20, UInt<1>(0h1) connect out_wivalid[8], _out_wifireMux_T_84 connect out_wivalid[7], _out_wifireMux_T_84 connect out_wivalid[6], _out_wifireMux_T_84 node _out_wifireMux_T_85 = eq(_out_T_6, UInt<1>(0h0)) node _out_wifireMux_T_86 = or(out_wifireMux_out_20, _out_wifireMux_T_85) wire out_wifireMux_out_21 : UInt<1> node _out_wifireMux_T_87 = and(_out_wifireMux_T_2, out_frontSel_21) node _out_wifireMux_T_88 = and(_out_wifireMux_T_87, UInt<1>(0h1)) connect out_wifireMux_out_21, UInt<1>(0h1) node _out_wifireMux_T_89 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_90 = or(out_wifireMux_out_21, _out_wifireMux_T_89) wire out_wifireMux_out_22 : UInt<1> node _out_wifireMux_T_91 = and(_out_wifireMux_T_2, out_frontSel_22) node _out_wifireMux_T_92 = and(_out_wifireMux_T_91, UInt<1>(0h1)) connect out_wifireMux_out_22, UInt<1>(0h1) node _out_wifireMux_T_93 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_94 = or(out_wifireMux_out_22, _out_wifireMux_T_93) wire out_wifireMux_out_23 : UInt<1> node _out_wifireMux_T_95 = and(_out_wifireMux_T_2, out_frontSel_23) node _out_wifireMux_T_96 = and(_out_wifireMux_T_95, UInt<1>(0h1)) connect out_wifireMux_out_23, UInt<1>(0h1) node _out_wifireMux_T_97 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_98 = or(out_wifireMux_out_23, _out_wifireMux_T_97) wire out_wifireMux_out_24 : UInt<1> node _out_wifireMux_T_99 = and(_out_wifireMux_T_2, out_frontSel_24) node _out_wifireMux_T_100 = and(_out_wifireMux_T_99, UInt<1>(0h1)) connect out_wifireMux_out_24, UInt<1>(0h1) node _out_wifireMux_T_101 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_102 = or(out_wifireMux_out_24, _out_wifireMux_T_101) wire out_wifireMux_out_25 : UInt<1> node _out_wifireMux_T_103 = and(_out_wifireMux_T_2, out_frontSel_25) node _out_wifireMux_T_104 = and(_out_wifireMux_T_103, UInt<1>(0h1)) connect out_wifireMux_out_25, UInt<1>(0h1) node _out_wifireMux_T_105 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_106 = or(out_wifireMux_out_25, _out_wifireMux_T_105) wire out_wifireMux_out_26 : UInt<1> node _out_wifireMux_T_107 = and(_out_wifireMux_T_2, out_frontSel_26) node _out_wifireMux_T_108 = and(_out_wifireMux_T_107, UInt<1>(0h1)) connect out_wifireMux_out_26, UInt<1>(0h1) node _out_wifireMux_T_109 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_110 = or(out_wifireMux_out_26, _out_wifireMux_T_109) wire out_wifireMux_out_27 : UInt<1> node _out_wifireMux_T_111 = and(_out_wifireMux_T_2, out_frontSel_27) node _out_wifireMux_T_112 = and(_out_wifireMux_T_111, UInt<1>(0h1)) connect out_wifireMux_out_27, UInt<1>(0h1) node _out_wifireMux_T_113 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_114 = or(out_wifireMux_out_27, _out_wifireMux_T_113) wire out_wifireMux_out_28 : UInt<1> node _out_wifireMux_T_115 = and(_out_wifireMux_T_2, out_frontSel_28) node _out_wifireMux_T_116 = and(_out_wifireMux_T_115, UInt<1>(0h1)) connect out_wifireMux_out_28, UInt<1>(0h1) node _out_wifireMux_T_117 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_118 = or(out_wifireMux_out_28, _out_wifireMux_T_117) wire out_wifireMux_out_29 : UInt<1> node _out_wifireMux_T_119 = and(_out_wifireMux_T_2, out_frontSel_29) node _out_wifireMux_T_120 = and(_out_wifireMux_T_119, UInt<1>(0h1)) connect out_wifireMux_out_29, UInt<1>(0h1) node _out_wifireMux_T_121 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_122 = or(out_wifireMux_out_29, _out_wifireMux_T_121) wire out_wifireMux_out_30 : UInt<1> node _out_wifireMux_T_123 = and(_out_wifireMux_T_2, out_frontSel_30) node _out_wifireMux_T_124 = and(_out_wifireMux_T_123, UInt<1>(0h1)) connect out_wifireMux_out_30, UInt<1>(0h1) node _out_wifireMux_T_125 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_126 = or(out_wifireMux_out_30, _out_wifireMux_T_125) wire out_wifireMux_out_31 : UInt<1> node _out_wifireMux_T_127 = and(_out_wifireMux_T_2, out_frontSel_31) node _out_wifireMux_T_128 = and(_out_wifireMux_T_127, UInt<1>(0h1)) connect out_wifireMux_out_31, UInt<1>(0h1) node _out_wifireMux_T_129 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_130 = or(out_wifireMux_out_31, _out_wifireMux_T_129) node _out_wifireMux_T_131 = geq(out_iindex, UInt<6>(0h20)) wire _out_wifireMux_WIRE : UInt<1>[32] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 connect _out_wifireMux_WIRE[4], _out_wifireMux_T_22 connect _out_wifireMux_WIRE[5], _out_wifireMux_T_26 connect _out_wifireMux_WIRE[6], _out_wifireMux_T_30 connect _out_wifireMux_WIRE[7], _out_wifireMux_T_34 connect _out_wifireMux_WIRE[8], _out_wifireMux_T_38 connect _out_wifireMux_WIRE[9], _out_wifireMux_T_42 connect _out_wifireMux_WIRE[10], _out_wifireMux_T_46 connect _out_wifireMux_WIRE[11], _out_wifireMux_T_50 connect _out_wifireMux_WIRE[12], _out_wifireMux_T_54 connect _out_wifireMux_WIRE[13], _out_wifireMux_T_58 connect _out_wifireMux_WIRE[14], _out_wifireMux_T_62 connect _out_wifireMux_WIRE[15], _out_wifireMux_T_66 connect _out_wifireMux_WIRE[16], _out_wifireMux_T_70 connect _out_wifireMux_WIRE[17], _out_wifireMux_T_74 connect _out_wifireMux_WIRE[18], _out_wifireMux_T_78 connect _out_wifireMux_WIRE[19], _out_wifireMux_T_82 connect _out_wifireMux_WIRE[20], _out_wifireMux_T_86 connect _out_wifireMux_WIRE[21], _out_wifireMux_T_90 connect _out_wifireMux_WIRE[22], _out_wifireMux_T_94 connect _out_wifireMux_WIRE[23], _out_wifireMux_T_98 connect _out_wifireMux_WIRE[24], _out_wifireMux_T_102 connect _out_wifireMux_WIRE[25], _out_wifireMux_T_106 connect _out_wifireMux_WIRE[26], _out_wifireMux_T_110 connect _out_wifireMux_WIRE[27], _out_wifireMux_T_114 connect _out_wifireMux_WIRE[28], _out_wifireMux_T_118 connect _out_wifireMux_WIRE[29], _out_wifireMux_T_122 connect _out_wifireMux_WIRE[30], _out_wifireMux_T_126 connect _out_wifireMux_WIRE[31], _out_wifireMux_T_130 node out_wifireMux = mux(_out_wifireMux_T_131, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_13) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[14], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_13, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[2], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, UInt<1>(0h1)) connect out_rofireMux_out_2, UInt<1>(0h1) node _out_rofireMux_T_12 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, UInt<1>(0h1)) connect out_rofireMux_out_3, UInt<1>(0h1) node _out_rofireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) wire out_rofireMux_out_4 : UInt<1> node _out_rofireMux_T_18 = and(_out_rofireMux_T_1, out_backSel_4) node _out_rofireMux_T_19 = and(_out_rofireMux_T_18, _out_T_5) connect out_rofireMux_out_4, UInt<1>(0h1) connect out_roready[5], _out_rofireMux_T_19 connect out_roready[4], _out_rofireMux_T_19 connect out_roready[3], _out_rofireMux_T_19 node _out_rofireMux_T_20 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_21 = or(out_rofireMux_out_4, _out_rofireMux_T_20) wire out_rofireMux_out_5 : UInt<1> node _out_rofireMux_T_22 = and(_out_rofireMux_T_1, out_backSel_5) node _out_rofireMux_T_23 = and(_out_rofireMux_T_22, UInt<1>(0h1)) connect out_rofireMux_out_5, UInt<1>(0h1) node _out_rofireMux_T_24 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_25 = or(out_rofireMux_out_5, _out_rofireMux_T_24) wire out_rofireMux_out_6 : UInt<1> node _out_rofireMux_T_26 = and(_out_rofireMux_T_1, out_backSel_6) node _out_rofireMux_T_27 = and(_out_rofireMux_T_26, UInt<1>(0h1)) connect out_rofireMux_out_6, UInt<1>(0h1) node _out_rofireMux_T_28 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_29 = or(out_rofireMux_out_6, _out_rofireMux_T_28) wire out_rofireMux_out_7 : UInt<1> node _out_rofireMux_T_30 = and(_out_rofireMux_T_1, out_backSel_7) node _out_rofireMux_T_31 = and(_out_rofireMux_T_30, UInt<1>(0h1)) connect out_rofireMux_out_7, UInt<1>(0h1) node _out_rofireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_33 = or(out_rofireMux_out_7, _out_rofireMux_T_32) wire out_rofireMux_out_8 : UInt<1> node _out_rofireMux_T_34 = and(_out_rofireMux_T_1, out_backSel_8) node _out_rofireMux_T_35 = and(_out_rofireMux_T_34, _out_T_11) connect out_rofireMux_out_8, UInt<1>(0h1) connect out_roready[13], _out_rofireMux_T_35 connect out_roready[12], _out_rofireMux_T_35 node _out_rofireMux_T_36 = eq(_out_T_11, UInt<1>(0h0)) node _out_rofireMux_T_37 = or(out_rofireMux_out_8, _out_rofireMux_T_36) wire out_rofireMux_out_9 : UInt<1> node _out_rofireMux_T_38 = and(_out_rofireMux_T_1, out_backSel_9) node _out_rofireMux_T_39 = and(_out_rofireMux_T_38, UInt<1>(0h1)) connect out_rofireMux_out_9, UInt<1>(0h1) node _out_rofireMux_T_40 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_41 = or(out_rofireMux_out_9, _out_rofireMux_T_40) wire out_rofireMux_out_10 : UInt<1> node _out_rofireMux_T_42 = and(_out_rofireMux_T_1, out_backSel_10) node _out_rofireMux_T_43 = and(_out_rofireMux_T_42, _out_T_1) connect out_rofireMux_out_10, UInt<1>(0h1) connect out_roready[1], _out_rofireMux_T_43 connect out_roready[0], _out_rofireMux_T_43 node _out_rofireMux_T_44 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_45 = or(out_rofireMux_out_10, _out_rofireMux_T_44) wire out_rofireMux_out_11 : UInt<1> node _out_rofireMux_T_46 = and(_out_rofireMux_T_1, out_backSel_11) node _out_rofireMux_T_47 = and(_out_rofireMux_T_46, UInt<1>(0h1)) connect out_rofireMux_out_11, UInt<1>(0h1) node _out_rofireMux_T_48 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_49 = or(out_rofireMux_out_11, _out_rofireMux_T_48) wire out_rofireMux_out_12 : UInt<1> node _out_rofireMux_T_50 = and(_out_rofireMux_T_1, out_backSel_12) node _out_rofireMux_T_51 = and(_out_rofireMux_T_50, UInt<1>(0h1)) connect out_rofireMux_out_12, UInt<1>(0h1) node _out_rofireMux_T_52 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_53 = or(out_rofireMux_out_12, _out_rofireMux_T_52) wire out_rofireMux_out_13 : UInt<1> node _out_rofireMux_T_54 = and(_out_rofireMux_T_1, out_backSel_13) node _out_rofireMux_T_55 = and(_out_rofireMux_T_54, UInt<1>(0h1)) connect out_rofireMux_out_13, UInt<1>(0h1) node _out_rofireMux_T_56 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_57 = or(out_rofireMux_out_13, _out_rofireMux_T_56) wire out_rofireMux_out_14 : UInt<1> node _out_rofireMux_T_58 = and(_out_rofireMux_T_1, out_backSel_14) node _out_rofireMux_T_59 = and(_out_rofireMux_T_58, UInt<1>(0h1)) connect out_rofireMux_out_14, UInt<1>(0h1) node _out_rofireMux_T_60 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_61 = or(out_rofireMux_out_14, _out_rofireMux_T_60) wire out_rofireMux_out_15 : UInt<1> node _out_rofireMux_T_62 = and(_out_rofireMux_T_1, out_backSel_15) node _out_rofireMux_T_63 = and(_out_rofireMux_T_62, UInt<1>(0h1)) connect out_rofireMux_out_15, UInt<1>(0h1) node _out_rofireMux_T_64 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_65 = or(out_rofireMux_out_15, _out_rofireMux_T_64) wire out_rofireMux_out_16 : UInt<1> node _out_rofireMux_T_66 = and(_out_rofireMux_T_1, out_backSel_16) node _out_rofireMux_T_67 = and(_out_rofireMux_T_66, _out_T_9) connect out_rofireMux_out_16, UInt<1>(0h1) connect out_roready[11], _out_rofireMux_T_67 connect out_roready[10], _out_rofireMux_T_67 connect out_roready[9], _out_rofireMux_T_67 node _out_rofireMux_T_68 = eq(_out_T_9, UInt<1>(0h0)) node _out_rofireMux_T_69 = or(out_rofireMux_out_16, _out_rofireMux_T_68) wire out_rofireMux_out_17 : UInt<1> node _out_rofireMux_T_70 = and(_out_rofireMux_T_1, out_backSel_17) node _out_rofireMux_T_71 = and(_out_rofireMux_T_70, UInt<1>(0h1)) connect out_rofireMux_out_17, UInt<1>(0h1) node _out_rofireMux_T_72 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_73 = or(out_rofireMux_out_17, _out_rofireMux_T_72) wire out_rofireMux_out_18 : UInt<1> node _out_rofireMux_T_74 = and(_out_rofireMux_T_1, out_backSel_18) node _out_rofireMux_T_75 = and(_out_rofireMux_T_74, UInt<1>(0h1)) connect out_rofireMux_out_18, UInt<1>(0h1) node _out_rofireMux_T_76 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_77 = or(out_rofireMux_out_18, _out_rofireMux_T_76) wire out_rofireMux_out_19 : UInt<1> node _out_rofireMux_T_78 = and(_out_rofireMux_T_1, out_backSel_19) node _out_rofireMux_T_79 = and(_out_rofireMux_T_78, UInt<1>(0h1)) connect out_rofireMux_out_19, UInt<1>(0h1) node _out_rofireMux_T_80 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_81 = or(out_rofireMux_out_19, _out_rofireMux_T_80) wire out_rofireMux_out_20 : UInt<1> node _out_rofireMux_T_82 = and(_out_rofireMux_T_1, out_backSel_20) node _out_rofireMux_T_83 = and(_out_rofireMux_T_82, _out_T_7) connect out_rofireMux_out_20, UInt<1>(0h1) connect out_roready[8], _out_rofireMux_T_83 connect out_roready[7], _out_rofireMux_T_83 connect out_roready[6], _out_rofireMux_T_83 node _out_rofireMux_T_84 = eq(_out_T_7, UInt<1>(0h0)) node _out_rofireMux_T_85 = or(out_rofireMux_out_20, _out_rofireMux_T_84) wire out_rofireMux_out_21 : UInt<1> node _out_rofireMux_T_86 = and(_out_rofireMux_T_1, out_backSel_21) node _out_rofireMux_T_87 = and(_out_rofireMux_T_86, UInt<1>(0h1)) connect out_rofireMux_out_21, UInt<1>(0h1) node _out_rofireMux_T_88 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_89 = or(out_rofireMux_out_21, _out_rofireMux_T_88) wire out_rofireMux_out_22 : UInt<1> node _out_rofireMux_T_90 = and(_out_rofireMux_T_1, out_backSel_22) node _out_rofireMux_T_91 = and(_out_rofireMux_T_90, UInt<1>(0h1)) connect out_rofireMux_out_22, UInt<1>(0h1) node _out_rofireMux_T_92 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_93 = or(out_rofireMux_out_22, _out_rofireMux_T_92) wire out_rofireMux_out_23 : UInt<1> node _out_rofireMux_T_94 = and(_out_rofireMux_T_1, out_backSel_23) node _out_rofireMux_T_95 = and(_out_rofireMux_T_94, UInt<1>(0h1)) connect out_rofireMux_out_23, UInt<1>(0h1) node _out_rofireMux_T_96 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_97 = or(out_rofireMux_out_23, _out_rofireMux_T_96) wire out_rofireMux_out_24 : UInt<1> node _out_rofireMux_T_98 = and(_out_rofireMux_T_1, out_backSel_24) node _out_rofireMux_T_99 = and(_out_rofireMux_T_98, UInt<1>(0h1)) connect out_rofireMux_out_24, UInt<1>(0h1) node _out_rofireMux_T_100 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_101 = or(out_rofireMux_out_24, _out_rofireMux_T_100) wire out_rofireMux_out_25 : UInt<1> node _out_rofireMux_T_102 = and(_out_rofireMux_T_1, out_backSel_25) node _out_rofireMux_T_103 = and(_out_rofireMux_T_102, UInt<1>(0h1)) connect out_rofireMux_out_25, UInt<1>(0h1) node _out_rofireMux_T_104 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_105 = or(out_rofireMux_out_25, _out_rofireMux_T_104) wire out_rofireMux_out_26 : UInt<1> node _out_rofireMux_T_106 = and(_out_rofireMux_T_1, out_backSel_26) node _out_rofireMux_T_107 = and(_out_rofireMux_T_106, UInt<1>(0h1)) connect out_rofireMux_out_26, UInt<1>(0h1) node _out_rofireMux_T_108 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_109 = or(out_rofireMux_out_26, _out_rofireMux_T_108) wire out_rofireMux_out_27 : UInt<1> node _out_rofireMux_T_110 = and(_out_rofireMux_T_1, out_backSel_27) node _out_rofireMux_T_111 = and(_out_rofireMux_T_110, UInt<1>(0h1)) connect out_rofireMux_out_27, UInt<1>(0h1) node _out_rofireMux_T_112 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_113 = or(out_rofireMux_out_27, _out_rofireMux_T_112) wire out_rofireMux_out_28 : UInt<1> node _out_rofireMux_T_114 = and(_out_rofireMux_T_1, out_backSel_28) node _out_rofireMux_T_115 = and(_out_rofireMux_T_114, UInt<1>(0h1)) connect out_rofireMux_out_28, UInt<1>(0h1) node _out_rofireMux_T_116 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_117 = or(out_rofireMux_out_28, _out_rofireMux_T_116) wire out_rofireMux_out_29 : UInt<1> node _out_rofireMux_T_118 = and(_out_rofireMux_T_1, out_backSel_29) node _out_rofireMux_T_119 = and(_out_rofireMux_T_118, UInt<1>(0h1)) connect out_rofireMux_out_29, UInt<1>(0h1) node _out_rofireMux_T_120 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_121 = or(out_rofireMux_out_29, _out_rofireMux_T_120) wire out_rofireMux_out_30 : UInt<1> node _out_rofireMux_T_122 = and(_out_rofireMux_T_1, out_backSel_30) node _out_rofireMux_T_123 = and(_out_rofireMux_T_122, UInt<1>(0h1)) connect out_rofireMux_out_30, UInt<1>(0h1) node _out_rofireMux_T_124 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_125 = or(out_rofireMux_out_30, _out_rofireMux_T_124) wire out_rofireMux_out_31 : UInt<1> node _out_rofireMux_T_126 = and(_out_rofireMux_T_1, out_backSel_31) node _out_rofireMux_T_127 = and(_out_rofireMux_T_126, UInt<1>(0h1)) connect out_rofireMux_out_31, UInt<1>(0h1) node _out_rofireMux_T_128 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_129 = or(out_rofireMux_out_31, _out_rofireMux_T_128) node _out_rofireMux_T_130 = geq(out_oindex, UInt<6>(0h20)) wire _out_rofireMux_WIRE : UInt<1>[32] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 connect _out_rofireMux_WIRE[4], _out_rofireMux_T_21 connect _out_rofireMux_WIRE[5], _out_rofireMux_T_25 connect _out_rofireMux_WIRE[6], _out_rofireMux_T_29 connect _out_rofireMux_WIRE[7], _out_rofireMux_T_33 connect _out_rofireMux_WIRE[8], _out_rofireMux_T_37 connect _out_rofireMux_WIRE[9], _out_rofireMux_T_41 connect _out_rofireMux_WIRE[10], _out_rofireMux_T_45 connect _out_rofireMux_WIRE[11], _out_rofireMux_T_49 connect _out_rofireMux_WIRE[12], _out_rofireMux_T_53 connect _out_rofireMux_WIRE[13], _out_rofireMux_T_57 connect _out_rofireMux_WIRE[14], _out_rofireMux_T_61 connect _out_rofireMux_WIRE[15], _out_rofireMux_T_65 connect _out_rofireMux_WIRE[16], _out_rofireMux_T_69 connect _out_rofireMux_WIRE[17], _out_rofireMux_T_73 connect _out_rofireMux_WIRE[18], _out_rofireMux_T_77 connect _out_rofireMux_WIRE[19], _out_rofireMux_T_81 connect _out_rofireMux_WIRE[20], _out_rofireMux_T_85 connect _out_rofireMux_WIRE[21], _out_rofireMux_T_89 connect _out_rofireMux_WIRE[22], _out_rofireMux_T_93 connect _out_rofireMux_WIRE[23], _out_rofireMux_T_97 connect _out_rofireMux_WIRE[24], _out_rofireMux_T_101 connect _out_rofireMux_WIRE[25], _out_rofireMux_T_105 connect _out_rofireMux_WIRE[26], _out_rofireMux_T_109 connect _out_rofireMux_WIRE[27], _out_rofireMux_T_113 connect _out_rofireMux_WIRE[28], _out_rofireMux_T_117 connect _out_rofireMux_WIRE[29], _out_rofireMux_T_121 connect _out_rofireMux_WIRE[30], _out_rofireMux_T_125 connect _out_rofireMux_WIRE[31], _out_rofireMux_T_129 node out_rofireMux = mux(_out_rofireMux_T_130, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_13) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[14], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_13, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[2], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, UInt<1>(0h1)) connect out_wofireMux_out_2, UInt<1>(0h1) node _out_wofireMux_T_13 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, UInt<1>(0h1)) connect out_wofireMux_out_3, UInt<1>(0h1) node _out_wofireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) wire out_wofireMux_out_4 : UInt<1> node _out_wofireMux_T_19 = and(_out_wofireMux_T_2, out_backSel_4) node _out_wofireMux_T_20 = and(_out_wofireMux_T_19, _out_T_5) connect out_wofireMux_out_4, UInt<1>(0h1) connect out_woready[5], _out_wofireMux_T_20 connect out_woready[4], _out_wofireMux_T_20 connect out_woready[3], _out_wofireMux_T_20 node _out_wofireMux_T_21 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_22 = or(out_wofireMux_out_4, _out_wofireMux_T_21) wire out_wofireMux_out_5 : UInt<1> node _out_wofireMux_T_23 = and(_out_wofireMux_T_2, out_backSel_5) node _out_wofireMux_T_24 = and(_out_wofireMux_T_23, UInt<1>(0h1)) connect out_wofireMux_out_5, UInt<1>(0h1) node _out_wofireMux_T_25 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_26 = or(out_wofireMux_out_5, _out_wofireMux_T_25) wire out_wofireMux_out_6 : UInt<1> node _out_wofireMux_T_27 = and(_out_wofireMux_T_2, out_backSel_6) node _out_wofireMux_T_28 = and(_out_wofireMux_T_27, UInt<1>(0h1)) connect out_wofireMux_out_6, UInt<1>(0h1) node _out_wofireMux_T_29 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_30 = or(out_wofireMux_out_6, _out_wofireMux_T_29) wire out_wofireMux_out_7 : UInt<1> node _out_wofireMux_T_31 = and(_out_wofireMux_T_2, out_backSel_7) node _out_wofireMux_T_32 = and(_out_wofireMux_T_31, UInt<1>(0h1)) connect out_wofireMux_out_7, UInt<1>(0h1) node _out_wofireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_34 = or(out_wofireMux_out_7, _out_wofireMux_T_33) wire out_wofireMux_out_8 : UInt<1> node _out_wofireMux_T_35 = and(_out_wofireMux_T_2, out_backSel_8) node _out_wofireMux_T_36 = and(_out_wofireMux_T_35, _out_T_11) connect out_wofireMux_out_8, UInt<1>(0h1) connect out_woready[13], _out_wofireMux_T_36 connect out_woready[12], _out_wofireMux_T_36 node _out_wofireMux_T_37 = eq(_out_T_11, UInt<1>(0h0)) node _out_wofireMux_T_38 = or(out_wofireMux_out_8, _out_wofireMux_T_37) wire out_wofireMux_out_9 : UInt<1> node _out_wofireMux_T_39 = and(_out_wofireMux_T_2, out_backSel_9) node _out_wofireMux_T_40 = and(_out_wofireMux_T_39, UInt<1>(0h1)) connect out_wofireMux_out_9, UInt<1>(0h1) node _out_wofireMux_T_41 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_42 = or(out_wofireMux_out_9, _out_wofireMux_T_41) wire out_wofireMux_out_10 : UInt<1> node _out_wofireMux_T_43 = and(_out_wofireMux_T_2, out_backSel_10) node _out_wofireMux_T_44 = and(_out_wofireMux_T_43, _out_T_1) connect out_wofireMux_out_10, UInt<1>(0h1) connect out_woready[1], _out_wofireMux_T_44 connect out_woready[0], _out_wofireMux_T_44 node _out_wofireMux_T_45 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_46 = or(out_wofireMux_out_10, _out_wofireMux_T_45) wire out_wofireMux_out_11 : UInt<1> node _out_wofireMux_T_47 = and(_out_wofireMux_T_2, out_backSel_11) node _out_wofireMux_T_48 = and(_out_wofireMux_T_47, UInt<1>(0h1)) connect out_wofireMux_out_11, UInt<1>(0h1) node _out_wofireMux_T_49 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_50 = or(out_wofireMux_out_11, _out_wofireMux_T_49) wire out_wofireMux_out_12 : UInt<1> node _out_wofireMux_T_51 = and(_out_wofireMux_T_2, out_backSel_12) node _out_wofireMux_T_52 = and(_out_wofireMux_T_51, UInt<1>(0h1)) connect out_wofireMux_out_12, UInt<1>(0h1) node _out_wofireMux_T_53 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_54 = or(out_wofireMux_out_12, _out_wofireMux_T_53) wire out_wofireMux_out_13 : UInt<1> node _out_wofireMux_T_55 = and(_out_wofireMux_T_2, out_backSel_13) node _out_wofireMux_T_56 = and(_out_wofireMux_T_55, UInt<1>(0h1)) connect out_wofireMux_out_13, UInt<1>(0h1) node _out_wofireMux_T_57 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_58 = or(out_wofireMux_out_13, _out_wofireMux_T_57) wire out_wofireMux_out_14 : UInt<1> node _out_wofireMux_T_59 = and(_out_wofireMux_T_2, out_backSel_14) node _out_wofireMux_T_60 = and(_out_wofireMux_T_59, UInt<1>(0h1)) connect out_wofireMux_out_14, UInt<1>(0h1) node _out_wofireMux_T_61 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_62 = or(out_wofireMux_out_14, _out_wofireMux_T_61) wire out_wofireMux_out_15 : UInt<1> node _out_wofireMux_T_63 = and(_out_wofireMux_T_2, out_backSel_15) node _out_wofireMux_T_64 = and(_out_wofireMux_T_63, UInt<1>(0h1)) connect out_wofireMux_out_15, UInt<1>(0h1) node _out_wofireMux_T_65 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_66 = or(out_wofireMux_out_15, _out_wofireMux_T_65) wire out_wofireMux_out_16 : UInt<1> node _out_wofireMux_T_67 = and(_out_wofireMux_T_2, out_backSel_16) node _out_wofireMux_T_68 = and(_out_wofireMux_T_67, _out_T_9) connect out_wofireMux_out_16, UInt<1>(0h1) connect out_woready[11], _out_wofireMux_T_68 connect out_woready[10], _out_wofireMux_T_68 connect out_woready[9], _out_wofireMux_T_68 node _out_wofireMux_T_69 = eq(_out_T_9, UInt<1>(0h0)) node _out_wofireMux_T_70 = or(out_wofireMux_out_16, _out_wofireMux_T_69) wire out_wofireMux_out_17 : UInt<1> node _out_wofireMux_T_71 = and(_out_wofireMux_T_2, out_backSel_17) node _out_wofireMux_T_72 = and(_out_wofireMux_T_71, UInt<1>(0h1)) connect out_wofireMux_out_17, UInt<1>(0h1) node _out_wofireMux_T_73 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_74 = or(out_wofireMux_out_17, _out_wofireMux_T_73) wire out_wofireMux_out_18 : UInt<1> node _out_wofireMux_T_75 = and(_out_wofireMux_T_2, out_backSel_18) node _out_wofireMux_T_76 = and(_out_wofireMux_T_75, UInt<1>(0h1)) connect out_wofireMux_out_18, UInt<1>(0h1) node _out_wofireMux_T_77 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_78 = or(out_wofireMux_out_18, _out_wofireMux_T_77) wire out_wofireMux_out_19 : UInt<1> node _out_wofireMux_T_79 = and(_out_wofireMux_T_2, out_backSel_19) node _out_wofireMux_T_80 = and(_out_wofireMux_T_79, UInt<1>(0h1)) connect out_wofireMux_out_19, UInt<1>(0h1) node _out_wofireMux_T_81 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_82 = or(out_wofireMux_out_19, _out_wofireMux_T_81) wire out_wofireMux_out_20 : UInt<1> node _out_wofireMux_T_83 = and(_out_wofireMux_T_2, out_backSel_20) node _out_wofireMux_T_84 = and(_out_wofireMux_T_83, _out_T_7) connect out_wofireMux_out_20, UInt<1>(0h1) connect out_woready[8], _out_wofireMux_T_84 connect out_woready[7], _out_wofireMux_T_84 connect out_woready[6], _out_wofireMux_T_84 node _out_wofireMux_T_85 = eq(_out_T_7, UInt<1>(0h0)) node _out_wofireMux_T_86 = or(out_wofireMux_out_20, _out_wofireMux_T_85) wire out_wofireMux_out_21 : UInt<1> node _out_wofireMux_T_87 = and(_out_wofireMux_T_2, out_backSel_21) node _out_wofireMux_T_88 = and(_out_wofireMux_T_87, UInt<1>(0h1)) connect out_wofireMux_out_21, UInt<1>(0h1) node _out_wofireMux_T_89 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_90 = or(out_wofireMux_out_21, _out_wofireMux_T_89) wire out_wofireMux_out_22 : UInt<1> node _out_wofireMux_T_91 = and(_out_wofireMux_T_2, out_backSel_22) node _out_wofireMux_T_92 = and(_out_wofireMux_T_91, UInt<1>(0h1)) connect out_wofireMux_out_22, UInt<1>(0h1) node _out_wofireMux_T_93 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_94 = or(out_wofireMux_out_22, _out_wofireMux_T_93) wire out_wofireMux_out_23 : UInt<1> node _out_wofireMux_T_95 = and(_out_wofireMux_T_2, out_backSel_23) node _out_wofireMux_T_96 = and(_out_wofireMux_T_95, UInt<1>(0h1)) connect out_wofireMux_out_23, UInt<1>(0h1) node _out_wofireMux_T_97 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_98 = or(out_wofireMux_out_23, _out_wofireMux_T_97) wire out_wofireMux_out_24 : UInt<1> node _out_wofireMux_T_99 = and(_out_wofireMux_T_2, out_backSel_24) node _out_wofireMux_T_100 = and(_out_wofireMux_T_99, UInt<1>(0h1)) connect out_wofireMux_out_24, UInt<1>(0h1) node _out_wofireMux_T_101 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_102 = or(out_wofireMux_out_24, _out_wofireMux_T_101) wire out_wofireMux_out_25 : UInt<1> node _out_wofireMux_T_103 = and(_out_wofireMux_T_2, out_backSel_25) node _out_wofireMux_T_104 = and(_out_wofireMux_T_103, UInt<1>(0h1)) connect out_wofireMux_out_25, UInt<1>(0h1) node _out_wofireMux_T_105 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_106 = or(out_wofireMux_out_25, _out_wofireMux_T_105) wire out_wofireMux_out_26 : UInt<1> node _out_wofireMux_T_107 = and(_out_wofireMux_T_2, out_backSel_26) node _out_wofireMux_T_108 = and(_out_wofireMux_T_107, UInt<1>(0h1)) connect out_wofireMux_out_26, UInt<1>(0h1) node _out_wofireMux_T_109 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_110 = or(out_wofireMux_out_26, _out_wofireMux_T_109) wire out_wofireMux_out_27 : UInt<1> node _out_wofireMux_T_111 = and(_out_wofireMux_T_2, out_backSel_27) node _out_wofireMux_T_112 = and(_out_wofireMux_T_111, UInt<1>(0h1)) connect out_wofireMux_out_27, UInt<1>(0h1) node _out_wofireMux_T_113 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_114 = or(out_wofireMux_out_27, _out_wofireMux_T_113) wire out_wofireMux_out_28 : UInt<1> node _out_wofireMux_T_115 = and(_out_wofireMux_T_2, out_backSel_28) node _out_wofireMux_T_116 = and(_out_wofireMux_T_115, UInt<1>(0h1)) connect out_wofireMux_out_28, UInt<1>(0h1) node _out_wofireMux_T_117 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_118 = or(out_wofireMux_out_28, _out_wofireMux_T_117) wire out_wofireMux_out_29 : UInt<1> node _out_wofireMux_T_119 = and(_out_wofireMux_T_2, out_backSel_29) node _out_wofireMux_T_120 = and(_out_wofireMux_T_119, UInt<1>(0h1)) connect out_wofireMux_out_29, UInt<1>(0h1) node _out_wofireMux_T_121 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_122 = or(out_wofireMux_out_29, _out_wofireMux_T_121) wire out_wofireMux_out_30 : UInt<1> node _out_wofireMux_T_123 = and(_out_wofireMux_T_2, out_backSel_30) node _out_wofireMux_T_124 = and(_out_wofireMux_T_123, UInt<1>(0h1)) connect out_wofireMux_out_30, UInt<1>(0h1) node _out_wofireMux_T_125 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_126 = or(out_wofireMux_out_30, _out_wofireMux_T_125) wire out_wofireMux_out_31 : UInt<1> node _out_wofireMux_T_127 = and(_out_wofireMux_T_2, out_backSel_31) node _out_wofireMux_T_128 = and(_out_wofireMux_T_127, UInt<1>(0h1)) connect out_wofireMux_out_31, UInt<1>(0h1) node _out_wofireMux_T_129 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_130 = or(out_wofireMux_out_31, _out_wofireMux_T_129) node _out_wofireMux_T_131 = geq(out_oindex, UInt<6>(0h20)) wire _out_wofireMux_WIRE : UInt<1>[32] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 connect _out_wofireMux_WIRE[4], _out_wofireMux_T_22 connect _out_wofireMux_WIRE[5], _out_wofireMux_T_26 connect _out_wofireMux_WIRE[6], _out_wofireMux_T_30 connect _out_wofireMux_WIRE[7], _out_wofireMux_T_34 connect _out_wofireMux_WIRE[8], _out_wofireMux_T_38 connect _out_wofireMux_WIRE[9], _out_wofireMux_T_42 connect _out_wofireMux_WIRE[10], _out_wofireMux_T_46 connect _out_wofireMux_WIRE[11], _out_wofireMux_T_50 connect _out_wofireMux_WIRE[12], _out_wofireMux_T_54 connect _out_wofireMux_WIRE[13], _out_wofireMux_T_58 connect _out_wofireMux_WIRE[14], _out_wofireMux_T_62 connect _out_wofireMux_WIRE[15], _out_wofireMux_T_66 connect _out_wofireMux_WIRE[16], _out_wofireMux_T_70 connect _out_wofireMux_WIRE[17], _out_wofireMux_T_74 connect _out_wofireMux_WIRE[18], _out_wofireMux_T_78 connect _out_wofireMux_WIRE[19], _out_wofireMux_T_82 connect _out_wofireMux_WIRE[20], _out_wofireMux_T_86 connect _out_wofireMux_WIRE[21], _out_wofireMux_T_90 connect _out_wofireMux_WIRE[22], _out_wofireMux_T_94 connect _out_wofireMux_WIRE[23], _out_wofireMux_T_98 connect _out_wofireMux_WIRE[24], _out_wofireMux_T_102 connect _out_wofireMux_WIRE[25], _out_wofireMux_T_106 connect _out_wofireMux_WIRE[26], _out_wofireMux_T_110 connect _out_wofireMux_WIRE[27], _out_wofireMux_T_114 connect _out_wofireMux_WIRE[28], _out_wofireMux_T_118 connect _out_wofireMux_WIRE[29], _out_wofireMux_T_122 connect _out_wofireMux_WIRE[30], _out_wofireMux_T_126 connect _out_wofireMux_WIRE[31], _out_wofireMux_T_130 node out_wofireMux = mux(_out_wofireMux_T_131, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_q_io_deq_ready_T = and(out.ready, out_oready) connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_back_front_q.io.deq.bits.read wire out_out_bits_data_out : UInt<1> connect out_out_bits_data_out, UInt<1>(0h1) node _out_out_bits_data_T = eq(UInt<1>(0h0), out_oindex) when _out_out_bits_data_T : connect out_out_bits_data_out, _out_T_13 else : node _out_out_bits_data_T_1 = eq(UInt<1>(0h1), out_oindex) when _out_out_bits_data_T_1 : connect out_out_bits_data_out, _out_T_3 else : node _out_out_bits_data_T_2 = eq(UInt<3>(0h4), out_oindex) when _out_out_bits_data_T_2 : connect out_out_bits_data_out, _out_T_5 else : node _out_out_bits_data_T_3 = eq(UInt<4>(0h8), out_oindex) when _out_out_bits_data_T_3 : connect out_out_bits_data_out, _out_T_11 else : node _out_out_bits_data_T_4 = eq(UInt<4>(0ha), out_oindex) when _out_out_bits_data_T_4 : connect out_out_bits_data_out, _out_T_1 else : node _out_out_bits_data_T_5 = eq(UInt<5>(0h10), out_oindex) when _out_out_bits_data_T_5 : connect out_out_bits_data_out, _out_T_9 else : node _out_out_bits_data_T_6 = eq(UInt<5>(0h14), out_oindex) when _out_out_bits_data_T_6 : connect out_out_bits_data_out, _out_T_7 wire out_out_bits_data_out_1 : UInt connect out_out_bits_data_out_1, UInt<1>(0h0) node _out_out_bits_data_T_7 = eq(UInt<1>(0h0), out_oindex) when _out_out_bits_data_T_7 : connect out_out_bits_data_out_1, _out_T_174 else : node _out_out_bits_data_T_8 = eq(UInt<1>(0h1), out_oindex) when _out_out_bits_data_T_8 : connect out_out_bits_data_out_1, _out_T_44 else : node _out_out_bits_data_T_9 = eq(UInt<3>(0h4), out_oindex) when _out_out_bits_data_T_9 : connect out_out_bits_data_out_1, _out_T_71 else : node _out_out_bits_data_T_10 = eq(UInt<4>(0h8), out_oindex) when _out_out_bits_data_T_10 : connect out_out_bits_data_out_1, _out_T_163 else : node _out_out_bits_data_T_11 = eq(UInt<4>(0ha), out_oindex) when _out_out_bits_data_T_11 : connect out_out_bits_data_out_1, _out_T_33 else : node _out_out_bits_data_T_12 = eq(UInt<5>(0h10), out_oindex) when _out_out_bits_data_T_12 : connect out_out_bits_data_out_1, _out_T_143 else : node _out_out_bits_data_T_13 = eq(UInt<5>(0h14), out_oindex) when _out_out_bits_data_T_13 : connect out_out_bits_data_out_1, _out_T_107 node _out_out_bits_data_T_14 = mux(out_out_bits_data_out, out_out_bits_data_out_1, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_14 connect out.bits.extra, out_back_front_q.io.deq.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<14>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<14>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) node _claimed_T = gt(maxDevs[0], UInt<1>(0h0)) node claimed = and(claimer[0], _claimed_T) node _T_23 = or(claimed, completer[0]) regreset r : UInt<1>, clock, reset, UInt<1>(0h0) when _T_23 : connect r, claimed node _T_24 = and(claimed, r) node _T_25 = or(claimed, completer[0]) regreset r_1 : UInt<1>, clock, reset, UInt<1>(0h0) when _T_25 : connect r_1, completer[0] node _T_26 = and(completer[0], r_1) node _ep_T = cat(pending[1], pending[0]) node ep = and(enables_0_0, _ep_T) reg ep2 : UInt, clock connect ep2, ep node _diff_T = not(ep2) node diff = and(ep, _diff_T) node _T_27 = sub(diff, UInt<1>(0h1)) node _T_28 = tail(_T_27, 1) node _T_29 = and(diff, _T_28) node _T_30 = neq(_T_29, UInt<1>(0h0)) node _T_31 = shl(UInt<1>(0h1), 2) node _T_32 = gt(maxDevs[0], _T_31) node _T_33 = cat(UInt<1>(0h1), threshold[0]) node _T_34 = leq(maxDevs[0], _T_33) node _T_35 = and(_T_32, _T_34)	module TLPLIC( // @[Plic.scala:132:9] input clock, // @[Plic.scala:132:9] input reset, // @[Plic.scala:132:9] input auto_int_in_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_1, // @[LazyModuleImp.scala:107:25] output auto_int_out_1_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_0_0, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] wire out_backSel_20; // @[RegisterRouter.scala:87:24] wire out_backSel_16; // @[RegisterRouter.scala:87:24] wire completer_0; // @[RegisterRouter.scala:87:24] wire [1:0] completerDev; // @[package.scala:163:13] wire completer_1; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_enq_ready; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [22:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire [13:0] _out_back_front_q_io_deq_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] _out_back_front_q_io_deq_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [1:0] _fanin_1_io_dev; // @[Plic.scala:189:27] wire [1:0] _fanin_1_io_max; // @[Plic.scala:189:27] wire [1:0] _fanin_io_dev; // @[Plic.scala:189:27] wire [1:0] _fanin_io_max; // @[Plic.scala:189:27] wire _gateways_gateway_1_io_plic_valid; // @[Plic.scala:160:27] wire _gateways_gateway_io_plic_valid; // @[Plic.scala:160:27] reg [1:0] priority_0; // @[Plic.scala:167:31] reg [1:0] priority_1; // @[Plic.scala:167:31] reg [1:0] threshold_0; // @[Plic.scala:170:31] reg [1:0] threshold_1; // @[Plic.scala:170:31] reg pending_0; // @[Plic.scala:172:26] reg pending_1; // @[Plic.scala:172:26] reg [1:0] enables_0_0; // @[Plic.scala:178:26] reg [1:0] enables_1_0; // @[Plic.scala:178:26] reg [1:0] maxDevs_0; // @[Plic.scala:185:22] reg [1:0] maxDevs_1; // @[Plic.scala:185:22] wire [1:0] pendingUInt = {pending_1, pending_0}; // @[Plic.scala:172:26, :186:26] reg [1:0] intnodeOut_0_REG; // @[Plic.scala:193:45] reg [1:0] intnodeOut_0_REG_1; // @[Plic.scala:193:45] wire [3:0] _completedDevs_T_1 = 4'h1 << completerDev; // @[OneHot.scala:65:12] wire [1:0] completedDevs = completer_0 \| completer_1 ? _completedDevs_T_1[2:1] : 2'h0; // @[OneHot.scala:65:{12,27}] wire _out_T_13 = {_out_back_front_q_io_deq_bits_index[22:19], _out_back_front_q_io_deq_bits_index[17:11], _out_back_front_q_io_deq_bits_index[8:5], _out_back_front_q_io_deq_bits_index[3:1]} == 18'h0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_11 = {{8{_out_back_front_q_io_deq_bits_mask[7]}}, {8{_out_back_front_q_io_deq_bits_mask[6]}}, {8{_out_back_front_q_io_deq_bits_mask[5]}}, {8{_out_back_front_q_io_deq_bits_mask[4]}}}; // @[RegisterRouter.scala:87:24] wire claimer_1 = _out_rofireMux_T_1 & out_backSel_20 & _out_T_13 & (\|_out_womask_T_11); // @[RegisterRouter.scala:87:24] wire [2:0] _GEN = {1'h0, completerDev}; // @[package.scala:163:13] wire [2:0] _out_completer_1_T = {enables_1_0, 1'h0} >> _GEN; // @[Plic.scala:132:9, :178:26, :183:52, :301:51] assign completer_1 = out_woready_8 & (&_out_womask_T_11) & _out_completer_1_T[0]; // @[RegisterRouter.scala:87:24] wire claimer_0 = _out_rofireMux_T_1 & out_backSel_16 & _out_T_13 & (\|_out_womask_T_11); // @[RegisterRouter.scala:87:24] assign completerDev = _out_back_front_q_io_deq_bits_data[33:32]; // @[package.scala:163:13]
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_MasterXbar_Cluster_i0_o0_a1d8s1k1z1u : input clock : Clock input reset : Reset output auto : { } wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}[0] wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}[0]	module TLXbar_MasterXbar_Cluster_i0_o0_a1d8s1k1z1u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset // @[Xbar.scala:74:9] ); endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_151 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_168 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_151( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_168 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_23 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_23( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DTLB_2 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<3>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<3>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren node vpn = bits(io.req.bits.vaddr, 38, 12) reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[1][1], clock reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<2>, clock reg r_sectored_repl_addr : UInt<0>, clock reg r_sectored_hit : { valid : UInt<1>, bits : UInt<0>}, clock reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock reg r_vstage1_en : UInt<1>, clock reg r_stage2_en : UInt<1>, clock reg r_need_gpa : UInt<1>, clock reg r_gpa_valid : UInt<1>, clock reg r_gpa : UInt<39>, clock reg r_gpa_vpn : UInt<27>, clock reg r_gpa_is_pte : UInt<1>, clock node priv_v = and(UInt<1>(0h0), io.req.bits.v) node priv_s = bits(io.req.bits.prv, 0, 0) node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) node _stage1_en_T = bits(satp.mode, 3, 3) node stage1_en = and(UInt<1>(0h1), _stage1_en_T) node _vstage1_en_T = and(UInt<1>(0h0), priv_v) node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) node _stage2_en_T = and(UInt<1>(0h0), priv_v) node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) node stage2_en = and(_stage2_en_T, _stage2_en_T_1) node _vm_enabled_T = or(stage1_en, stage2_en) node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_WIRE_1 : UInt<42> connect _mpu_ppn_WIRE_1, special_entry.data[0] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_28 connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0)) node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9) node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0)) node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0) node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30) node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12) node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32) node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33) node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T) node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) inst pmp of PMPChecker_s6 connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr connect pmp.io.size, io.req.bits.size connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l connect pmp.io.prv, mpu_priv inst pma of PMAChecker_2 connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9) node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14) node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19) node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24) node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29) node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34) node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39) node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44) node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49) node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_61 = cvt(_homogeneous_T_60) node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_63 = asSInt(_homogeneous_T_62) node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0))) node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64) node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0)) node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_68 = cvt(_homogeneous_T_67) node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_70 = asSInt(_homogeneous_T_69) node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0))) node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_73 = cvt(_homogeneous_T_72) node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_75 = asSInt(_homogeneous_T_74) node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0))) node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_78 = cvt(_homogeneous_T_77) node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_80 = asSInt(_homogeneous_T_79) node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0))) node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_83 = cvt(_homogeneous_T_82) node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_85 = asSInt(_homogeneous_T_84) node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0))) node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_88 = cvt(_homogeneous_T_87) node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000))) node _homogeneous_T_90 = asSInt(_homogeneous_T_89) node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0))) node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71) node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76) node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81) node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86) node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91) node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_98 = cvt(_homogeneous_T_97) node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000))) node _homogeneous_T_100 = asSInt(_homogeneous_T_99) node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0))) node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_103 = cvt(_homogeneous_T_102) node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_105 = asSInt(_homogeneous_T_104) node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0))) node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101) node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106) node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_110 = cvt(_homogeneous_T_109) node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_112 = asSInt(_homogeneous_T_111) node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0))) node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113) node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0)) node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_117 = cvt(_homogeneous_T_116) node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_119 = asSInt(_homogeneous_T_118) node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0))) node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120) node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0)) node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) node prot_r = and(_prot_r_T_1, pmp.io.r) node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) node prot_w = and(_prot_w_T_1, pmp.io.w) node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) node prot_x = and(_prot_x_T_1, pmp.io.x) node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2]) node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3]) node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn) node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v) node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6) node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7) node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T) node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _superpage_hits_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node superpage_hits_tagMatch_1 = and(superpage_entries[1].valid[0], _superpage_hits_tagMatch_T_1) node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0)) node _superpage_hits_T_14 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_15 = bits(_superpage_hits_T_14, 26, 18) node _superpage_hits_T_16 = eq(_superpage_hits_T_15, UInt<1>(0h0)) node _superpage_hits_T_17 = or(superpage_hits_ignore_3, _superpage_hits_T_16) node _superpage_hits_T_18 = and(superpage_hits_tagMatch_1, _superpage_hits_T_17) node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0)) node _superpage_hits_T_19 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_20 = bits(_superpage_hits_T_19, 17, 9) node _superpage_hits_T_21 = eq(_superpage_hits_T_20, UInt<1>(0h0)) node _superpage_hits_T_22 = or(superpage_hits_ignore_4, _superpage_hits_T_21) node _superpage_hits_T_23 = and(_superpage_hits_T_18, _superpage_hits_T_22) node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1)) node _superpage_hits_T_24 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_25 = bits(_superpage_hits_T_24, 8, 0) node _superpage_hits_T_26 = eq(_superpage_hits_T_25, UInt<1>(0h0)) node _superpage_hits_T_27 = or(superpage_hits_ignore_5, _superpage_hits_T_26) node superpage_hits_1 = and(_superpage_hits_T_23, _superpage_hits_T_27) node _superpage_hits_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node superpage_hits_tagMatch_2 = and(superpage_entries[2].valid[0], _superpage_hits_tagMatch_T_2) node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0)) node _superpage_hits_T_28 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_29 = bits(_superpage_hits_T_28, 26, 18) node _superpage_hits_T_30 = eq(_superpage_hits_T_29, UInt<1>(0h0)) node _superpage_hits_T_31 = or(superpage_hits_ignore_6, _superpage_hits_T_30) node _superpage_hits_T_32 = and(superpage_hits_tagMatch_2, _superpage_hits_T_31) node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0)) node _superpage_hits_T_33 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_34 = bits(_superpage_hits_T_33, 17, 9) node _superpage_hits_T_35 = eq(_superpage_hits_T_34, UInt<1>(0h0)) node _superpage_hits_T_36 = or(superpage_hits_ignore_7, _superpage_hits_T_35) node _superpage_hits_T_37 = and(_superpage_hits_T_32, _superpage_hits_T_36) node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1)) node _superpage_hits_T_38 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_39 = bits(_superpage_hits_T_38, 8, 0) node _superpage_hits_T_40 = eq(_superpage_hits_T_39, UInt<1>(0h0)) node _superpage_hits_T_41 = or(superpage_hits_ignore_8, _superpage_hits_T_40) node superpage_hits_2 = and(_superpage_hits_T_37, _superpage_hits_T_41) node _superpage_hits_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node superpage_hits_tagMatch_3 = and(superpage_entries[3].valid[0], _superpage_hits_tagMatch_T_3) node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0)) node _superpage_hits_T_42 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_43 = bits(_superpage_hits_T_42, 26, 18) node _superpage_hits_T_44 = eq(_superpage_hits_T_43, UInt<1>(0h0)) node _superpage_hits_T_45 = or(superpage_hits_ignore_9, _superpage_hits_T_44) node _superpage_hits_T_46 = and(superpage_hits_tagMatch_3, _superpage_hits_T_45) node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0)) node _superpage_hits_T_47 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_48 = bits(_superpage_hits_T_47, 17, 9) node _superpage_hits_T_49 = eq(_superpage_hits_T_48, UInt<1>(0h0)) node _superpage_hits_T_50 = or(superpage_hits_ignore_10, _superpage_hits_T_49) node _superpage_hits_T_51 = and(_superpage_hits_T_46, _superpage_hits_T_50) node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1)) node _superpage_hits_T_52 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_53 = bits(_superpage_hits_T_52, 8, 0) node _superpage_hits_T_54 = eq(_superpage_hits_T_53, UInt<1>(0h0)) node _superpage_hits_T_55 = or(superpage_hits_ignore_11, _superpage_hits_T_54) node superpage_hits_3 = and(_superpage_hits_T_51, _superpage_hits_T_55) node hitsVec_idx = bits(vpn, 1, 0) node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn) node _hitsVec_T_1 = shr(_hitsVec_T, 2) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v) node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4) node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_6 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_7 = bits(_hitsVec_T_6, 26, 18) node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) node _hitsVec_T_9 = or(hitsVec_ignore, _hitsVec_T_8) node _hitsVec_T_10 = and(hitsVec_tagMatch, _hitsVec_T_9) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_11 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_12 = bits(_hitsVec_T_11, 17, 9) node _hitsVec_T_13 = eq(_hitsVec_T_12, UInt<1>(0h0)) node _hitsVec_T_14 = or(hitsVec_ignore_1, _hitsVec_T_13) node _hitsVec_T_15 = and(_hitsVec_T_10, _hitsVec_T_14) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_16 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_17 = bits(_hitsVec_T_16, 8, 0) node _hitsVec_T_18 = eq(_hitsVec_T_17, UInt<1>(0h0)) node _hitsVec_T_19 = or(hitsVec_ignore_2, _hitsVec_T_18) node _hitsVec_T_20 = and(_hitsVec_T_15, _hitsVec_T_19) node hitsVec_1 = and(vm_enabled, _hitsVec_T_20) node _hitsVec_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node hitsVec_tagMatch_1 = and(superpage_entries[1].valid[0], _hitsVec_tagMatch_T_1) node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_21 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_22 = bits(_hitsVec_T_21, 26, 18) node _hitsVec_T_23 = eq(_hitsVec_T_22, UInt<1>(0h0)) node _hitsVec_T_24 = or(hitsVec_ignore_3, _hitsVec_T_23) node _hitsVec_T_25 = and(hitsVec_tagMatch_1, _hitsVec_T_24) node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_26 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_27 = bits(_hitsVec_T_26, 17, 9) node _hitsVec_T_28 = eq(_hitsVec_T_27, UInt<1>(0h0)) node _hitsVec_T_29 = or(hitsVec_ignore_4, _hitsVec_T_28) node _hitsVec_T_30 = and(_hitsVec_T_25, _hitsVec_T_29) node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1)) node _hitsVec_T_31 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_32 = bits(_hitsVec_T_31, 8, 0) node _hitsVec_T_33 = eq(_hitsVec_T_32, UInt<1>(0h0)) node _hitsVec_T_34 = or(hitsVec_ignore_5, _hitsVec_T_33) node _hitsVec_T_35 = and(_hitsVec_T_30, _hitsVec_T_34) node hitsVec_2 = and(vm_enabled, _hitsVec_T_35) node _hitsVec_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node hitsVec_tagMatch_2 = and(superpage_entries[2].valid[0], _hitsVec_tagMatch_T_2) node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0)) node _hitsVec_T_36 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_37 = bits(_hitsVec_T_36, 26, 18) node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0)) node _hitsVec_T_39 = or(hitsVec_ignore_6, _hitsVec_T_38) node _hitsVec_T_40 = and(hitsVec_tagMatch_2, _hitsVec_T_39) node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0)) node _hitsVec_T_41 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_42 = bits(_hitsVec_T_41, 17, 9) node _hitsVec_T_43 = eq(_hitsVec_T_42, UInt<1>(0h0)) node _hitsVec_T_44 = or(hitsVec_ignore_7, _hitsVec_T_43) node _hitsVec_T_45 = and(_hitsVec_T_40, _hitsVec_T_44) node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1)) node _hitsVec_T_46 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_47 = bits(_hitsVec_T_46, 8, 0) node _hitsVec_T_48 = eq(_hitsVec_T_47, UInt<1>(0h0)) node _hitsVec_T_49 = or(hitsVec_ignore_8, _hitsVec_T_48) node _hitsVec_T_50 = and(_hitsVec_T_45, _hitsVec_T_49) node hitsVec_3 = and(vm_enabled, _hitsVec_T_50) node _hitsVec_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node hitsVec_tagMatch_3 = and(superpage_entries[3].valid[0], _hitsVec_tagMatch_T_3) node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0)) node _hitsVec_T_51 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_52 = bits(_hitsVec_T_51, 26, 18) node _hitsVec_T_53 = eq(_hitsVec_T_52, UInt<1>(0h0)) node _hitsVec_T_54 = or(hitsVec_ignore_9, _hitsVec_T_53) node _hitsVec_T_55 = and(hitsVec_tagMatch_3, _hitsVec_T_54) node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0)) node _hitsVec_T_56 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_57 = bits(_hitsVec_T_56, 17, 9) node _hitsVec_T_58 = eq(_hitsVec_T_57, UInt<1>(0h0)) node _hitsVec_T_59 = or(hitsVec_ignore_10, _hitsVec_T_58) node _hitsVec_T_60 = and(_hitsVec_T_55, _hitsVec_T_59) node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1)) node _hitsVec_T_61 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_62 = bits(_hitsVec_T_61, 8, 0) node _hitsVec_T_63 = eq(_hitsVec_T_62, UInt<1>(0h0)) node _hitsVec_T_64 = or(hitsVec_ignore_11, _hitsVec_T_63) node _hitsVec_T_65 = and(_hitsVec_T_60, _hitsVec_T_64) node hitsVec_4 = and(vm_enabled, _hitsVec_T_65) node _hitsVec_tagMatch_T_4 = eq(special_entry.tag_v, priv_v) node hitsVec_tagMatch_4 = and(special_entry.valid[0], _hitsVec_tagMatch_T_4) node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0)) node _hitsVec_T_66 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_67 = bits(_hitsVec_T_66, 26, 18) node _hitsVec_T_68 = eq(_hitsVec_T_67, UInt<1>(0h0)) node _hitsVec_T_69 = or(hitsVec_ignore_12, _hitsVec_T_68) node _hitsVec_T_70 = and(hitsVec_tagMatch_4, _hitsVec_T_69) node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0)) node _hitsVec_T_71 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_72 = bits(_hitsVec_T_71, 17, 9) node _hitsVec_T_73 = eq(_hitsVec_T_72, UInt<1>(0h0)) node _hitsVec_T_74 = or(hitsVec_ignore_13, _hitsVec_T_73) node _hitsVec_T_75 = and(_hitsVec_T_70, _hitsVec_T_74) node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0)) node _hitsVec_T_76 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_77 = bits(_hitsVec_T_76, 8, 0) node _hitsVec_T_78 = eq(_hitsVec_T_77, UInt<1>(0h0)) node _hitsVec_T_79 = or(hitsVec_ignore_14, _hitsVec_T_78) node _hitsVec_T_80 = and(_hitsVec_T_75, _hitsVec_T_79) node hitsVec_5 = and(vm_enabled, _hitsVec_T_80) node real_hits_lo_hi = cat(hitsVec_2, hitsVec_1) node real_hits_lo = cat(real_hits_lo_hi, hitsVec_0) node real_hits_hi_hi = cat(hitsVec_5, hitsVec_4) node real_hits_hi = cat(real_hits_hi_hi, hitsVec_3) node real_hits = cat(real_hits_hi, real_hits_lo) node _hits_T = eq(vm_enabled, UInt<1>(0h0)) node hits = cat(_hits_T, real_hits) when do_refill : node refill_v = or(r_vstage1_en, r_stage2_en) wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable connect newEntry.u, io.ptw.resp.bits.pte.u node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) connect newEntry.g, _newEntry_g_T connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw connect newEntry.ae_final, io.ptw.resp.bits.ae_final node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 connect newEntry.pf, io.ptw.resp.bits.pf connect newEntry.gf, io.ptw.resp.bits.gf connect newEntry.hr, io.ptw.resp.bits.hr connect newEntry.hw, io.ptw.resp.bits.hw connect newEntry.hx, io.ptw.resp.bits.hx node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r connect newEntry.pw, prot_w connect newEntry.px, prot_x connect newEntry.ppp, pma.io.resp.pp connect newEntry.pal, pma.io.resp.al connect newEntry.paa, pma.io.resp.aa connect newEntry.eff, pma.io.resp.eff connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag_vpn, r_refill_tag connect special_entry.tag_v, refill_v node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag_vpn, r_refill_tag connect superpage_entries[0].tag_v, refill_v node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T when invalidate_refill : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) when _T_4 : connect superpage_entries[1].tag_vpn, r_refill_tag connect superpage_entries[1].tag_v, refill_v node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[1].level, _superpage_entries_1_level_T connect superpage_entries[1].valid[0], UInt<1>(0h1) node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo) node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T when invalidate_refill : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) when _T_5 : connect superpage_entries[2].tag_vpn, r_refill_tag connect superpage_entries[2].tag_v, refill_v node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[2].level, _superpage_entries_2_level_T connect superpage_entries[2].valid[0], UInt<1>(0h1) node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo) node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T when invalidate_refill : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) when _T_6 : connect superpage_entries[3].tag_vpn, r_refill_tag connect superpage_entries[3].tag_v, refill_v node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[3].level, _superpage_entries_3_level_T connect superpage_entries[3].valid[0], UInt<1>(0h1) node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo) node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T when invalidate_refill : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) node _T_7 = eq(waddr_1, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_8 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][0].tag_vpn, r_refill_tag connect sectored_entries[0][0].tag_v, refill_v connect sectored_entries[0][0].level, UInt<2>(0h0) node idx = bits(r_refill_tag, 1, 0) connect sectored_entries[0][0].valid[idx], UInt<1>(0h1) node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo) node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo) node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo) node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo) node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo) node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo) node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo) connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T when invalidate_refill : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect r_gpa_valid, io.ptw.resp.bits.gpa.valid connect r_gpa, io.ptw.resp.bits.gpa.bits connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte node _entries_T = bits(vpn, 1, 0) wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<42> connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.ppp, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.pr, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.px, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.pw, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.hr, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.hx, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.hw, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.sr, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.sx, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 14, 14) connect _entries_WIRE.sw, _entries_T_15 node _entries_T_16 = bits(_entries_WIRE_1, 15, 15) connect _entries_WIRE.gf, _entries_T_16 node _entries_T_17 = bits(_entries_WIRE_1, 16, 16) connect _entries_WIRE.pf, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_1, 17, 17) connect _entries_WIRE.ae_stage2, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_1, 18, 18) connect _entries_WIRE.ae_final, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_1, 19, 19) connect _entries_WIRE.ae_ptw, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_1, 20, 20) connect _entries_WIRE.g, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_1, 21, 21) connect _entries_WIRE.u, _entries_T_22 node _entries_T_23 = bits(_entries_WIRE_1, 41, 22) connect _entries_WIRE.ppn, _entries_T_23 inst entries_barrier of OptimizationBarrier_TLBEntryData_29 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.ppp, _entries_WIRE.ppp connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.hr, _entries_WIRE.hr connect entries_barrier.io.x.hx, _entries_WIRE.hx connect entries_barrier.io.x.hw, _entries_WIRE.hw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.gf, _entries_WIRE.gf connect entries_barrier.io.x.pf, _entries_WIRE.pf connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<42> connect _entries_WIRE_3, superpage_entries[0].data[0] node _entries_T_24 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_24 node _entries_T_25 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.ppp, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.pr, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.px, _entries_T_31 node _entries_T_32 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.pw, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.hr, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.hx, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.hw, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.sr, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.sx, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_3, 14, 14) connect _entries_WIRE_2.sw, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_3, 15, 15) connect _entries_WIRE_2.gf, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_3, 16, 16) connect _entries_WIRE_2.pf, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_3, 17, 17) connect _entries_WIRE_2.ae_stage2, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_3, 18, 18) connect _entries_WIRE_2.ae_final, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_3, 19, 19) connect _entries_WIRE_2.ae_ptw, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_3, 20, 20) connect _entries_WIRE_2.g, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_3, 21, 21) connect _entries_WIRE_2.u, _entries_T_45 node _entries_T_46 = bits(_entries_WIRE_3, 41, 22) connect _entries_WIRE_2.ppn, _entries_T_46 inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_30 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<42> connect _entries_WIRE_5, superpage_entries[1].data[0] node _entries_T_47 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_47 node _entries_T_48 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_48 node _entries_T_49 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.ppp, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.pr, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.px, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.pw, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.hr, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.hx, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.hw, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.sr, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.sx, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_5, 14, 14) connect _entries_WIRE_4.sw, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_5, 15, 15) connect _entries_WIRE_4.gf, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_5, 16, 16) connect _entries_WIRE_4.pf, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_5, 17, 17) connect _entries_WIRE_4.ae_stage2, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_5, 18, 18) connect _entries_WIRE_4.ae_final, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_5, 19, 19) connect _entries_WIRE_4.ae_ptw, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_5, 20, 20) connect _entries_WIRE_4.g, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_5, 21, 21) connect _entries_WIRE_4.u, _entries_T_68 node _entries_T_69 = bits(_entries_WIRE_5, 41, 22) connect _entries_WIRE_4.ppn, _entries_T_69 inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_31 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<42> connect _entries_WIRE_7, superpage_entries[2].data[0] node _entries_T_70 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_71 node _entries_T_72 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_72 node _entries_T_73 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.ppp, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.pr, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.px, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.pw, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.hr, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.hx, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.hw, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.sr, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.sx, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_7, 14, 14) connect _entries_WIRE_6.sw, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_7, 15, 15) connect _entries_WIRE_6.gf, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_7, 16, 16) connect _entries_WIRE_6.pf, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_7, 17, 17) connect _entries_WIRE_6.ae_stage2, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_7, 18, 18) connect _entries_WIRE_6.ae_final, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_7, 19, 19) connect _entries_WIRE_6.ae_ptw, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_7, 20, 20) connect _entries_WIRE_6.g, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_7, 21, 21) connect _entries_WIRE_6.u, _entries_T_91 node _entries_T_92 = bits(_entries_WIRE_7, 41, 22) connect _entries_WIRE_6.ppn, _entries_T_92 inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_32 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<42> connect _entries_WIRE_9, superpage_entries[3].data[0] node _entries_T_93 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_95 node _entries_T_96 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_96 node _entries_T_97 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.ppp, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.pr, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.px, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.pw, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.hr, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.hx, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.hw, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.sr, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.sx, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_9, 14, 14) connect _entries_WIRE_8.sw, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_9, 15, 15) connect _entries_WIRE_8.gf, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_9, 16, 16) connect _entries_WIRE_8.pf, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_9, 17, 17) connect _entries_WIRE_8.ae_stage2, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_9, 18, 18) connect _entries_WIRE_8.ae_final, _entries_T_111 node _entries_T_112 = bits(_entries_WIRE_9, 19, 19) connect _entries_WIRE_8.ae_ptw, _entries_T_112 node _entries_T_113 = bits(_entries_WIRE_9, 20, 20) connect _entries_WIRE_8.g, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_9, 21, 21) connect _entries_WIRE_8.u, _entries_T_114 node _entries_T_115 = bits(_entries_WIRE_9, 41, 22) connect _entries_WIRE_8.ppn, _entries_T_115 inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_33 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<42> connect _entries_WIRE_11, special_entry.data[0] node _entries_T_116 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_119 node _entries_T_120 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_120 node _entries_T_121 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.ppp, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.pr, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.px, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.pw, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.hr, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.hx, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.hw, _entries_T_127 node _entries_T_128 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.sr, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.sx, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_11, 14, 14) connect _entries_WIRE_10.sw, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_11, 15, 15) connect _entries_WIRE_10.gf, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_11, 16, 16) connect _entries_WIRE_10.pf, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_11, 17, 17) connect _entries_WIRE_10.ae_stage2, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_11, 18, 18) connect _entries_WIRE_10.ae_final, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_11, 19, 19) connect _entries_WIRE_10.ae_ptw, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_11, 20, 20) connect _entries_WIRE_10.g, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_11, 21, 21) connect _entries_WIRE_10.u, _entries_T_137 node _entries_T_138 = bits(_entries_WIRE_11, 41, 22) connect _entries_WIRE_10.ppn, _entries_T_138 inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_34 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) node ppn_res = shr(entries_barrier_1.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, entries_barrier_1.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, entries_barrier_1.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) node ppn_res_1 = shr(entries_barrier_2.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, entries_barrier_2.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1)) node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, entries_barrier_2.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) node ppn_res_2 = shr(entries_barrier_3.io.y.ppn, 18) node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0)) node _ppn_T_17 = mux(ppn_ignore_4, vpn, UInt<1>(0h0)) node _ppn_T_18 = or(_ppn_T_17, entries_barrier_3.io.y.ppn) node _ppn_T_19 = bits(_ppn_T_18, 17, 9) node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19) node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1)) node _ppn_T_21 = mux(ppn_ignore_5, vpn, UInt<1>(0h0)) node _ppn_T_22 = or(_ppn_T_21, entries_barrier_3.io.y.ppn) node _ppn_T_23 = bits(_ppn_T_22, 8, 0) node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23) node ppn_res_3 = shr(entries_barrier_4.io.y.ppn, 18) node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0)) node _ppn_T_25 = mux(ppn_ignore_6, vpn, UInt<1>(0h0)) node _ppn_T_26 = or(_ppn_T_25, entries_barrier_4.io.y.ppn) node _ppn_T_27 = bits(_ppn_T_26, 17, 9) node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27) node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1)) node _ppn_T_29 = mux(ppn_ignore_7, vpn, UInt<1>(0h0)) node _ppn_T_30 = or(_ppn_T_29, entries_barrier_4.io.y.ppn) node _ppn_T_31 = bits(_ppn_T_30, 8, 0) node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31) node ppn_res_4 = shr(entries_barrier_5.io.y.ppn, 18) node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0)) node _ppn_T_33 = mux(ppn_ignore_8, vpn, UInt<1>(0h0)) node _ppn_T_34 = or(_ppn_T_33, entries_barrier_5.io.y.ppn) node _ppn_T_35 = bits(_ppn_T_34, 17, 9) node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35) node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0)) node _ppn_T_37 = mux(ppn_ignore_9, vpn, UInt<1>(0h0)) node _ppn_T_38 = or(_ppn_T_37, entries_barrier_5.io.y.ppn) node _ppn_T_39 = bits(_ppn_T_38, 8, 0) node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39) node _ppn_T_41 = bits(vpn, 19, 0) node _ppn_T_42 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_43 = mux(hitsVec_1, _ppn_T_8, UInt<1>(0h0)) node _ppn_T_44 = mux(hitsVec_2, _ppn_T_16, UInt<1>(0h0)) node _ppn_T_45 = mux(hitsVec_3, _ppn_T_24, UInt<1>(0h0)) node _ppn_T_46 = mux(hitsVec_4, _ppn_T_32, UInt<1>(0h0)) node _ppn_T_47 = mux(hitsVec_5, _ppn_T_40, UInt<1>(0h0)) node _ppn_T_48 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0)) node _ppn_T_49 = or(_ppn_T_42, _ppn_T_43) node _ppn_T_50 = or(_ppn_T_49, _ppn_T_44) node _ppn_T_51 = or(_ppn_T_50, _ppn_T_45) node _ppn_T_52 = or(_ppn_T_51, _ppn_T_46) node _ppn_T_53 = or(_ppn_T_52, _ppn_T_47) node _ppn_T_54 = or(_ppn_T_53, _ppn_T_48) wire ppn : UInt<20> connect ppn, _ppn_T_54 node ptw_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, entries_barrier.io.y.ae_ptw) node ptw_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, entries_barrier_3.io.y.ae_ptw) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) node final_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) node final_ae_array_lo = cat(final_ae_array_lo_hi, entries_barrier.io.y.ae_final) node final_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) node final_ae_array_hi = cat(final_ae_array_hi_hi, entries_barrier_3.io.y.ae_final) node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) node ptw_pf_array_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, entries_barrier.io.y.pf) node ptw_pf_array_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, entries_barrier_3.io.y.pf) node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) node ptw_gf_array_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, entries_barrier.io.y.gf) node ptw_gf_array_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, entries_barrier_3.io.y.gf) node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) node priv_rw_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, entries_barrier.io.y.u) node priv_rw_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, entries_barrier_3.io.y.u) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, entries_barrier.io.y.u) node priv_rw_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, entries_barrier_3.io.y.u) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) node priv_x_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, entries_barrier.io.y.u) node priv_x_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, entries_barrier_3.io.y.u) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, entries_barrier.io.y.u) node priv_x_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, entries_barrier_3.io.y.u) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<6>(0h3f), UInt<6>(0h0)) node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<6>(0h3f), UInt<6>(0h0)) node stage1_bypass_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) node stage1_bypass_lo = cat(stage1_bypass_lo_hi, entries_barrier.io.y.ae_stage2) node stage1_bypass_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) node stage1_bypass_hi = cat(stage1_bypass_hi_hi, entries_barrier_3.io.y.ae_stage2) node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) node mxr = or(io.ptw.status.mxr, _mxr_T) node r_array_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) node r_array_lo = cat(r_array_lo_hi, entries_barrier.io.y.sr) node r_array_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) node r_array_hi = cat(r_array_hi_hi, entries_barrier_3.io.y.sr) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node r_array_lo_1 = cat(r_array_lo_hi_1, entries_barrier.io.y.sx) node r_array_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node r_array_hi_1 = cat(r_array_hi_hi_1, entries_barrier_3.io.y.sx) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) node r_array = cat(UInt<1>(0h1), _r_array_T_5) node w_array_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) node w_array_lo = cat(w_array_lo_hi, entries_barrier.io.y.sw) node w_array_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) node w_array_hi = cat(w_array_hi_hi, entries_barrier_3.io.y.sw) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok, _w_array_T) node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) node w_array = cat(UInt<1>(0h1), _w_array_T_2) node x_array_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node x_array_lo = cat(x_array_lo_hi, entries_barrier.io.y.sx) node x_array_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node x_array_hi = cat(x_array_hi_hi, entries_barrier_3.io.y.sx) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok, _x_array_T) node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) node x_array = cat(UInt<1>(0h1), _x_array_T_2) node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) node stage2_bypass = mux(_stage2_bypass_T, UInt<6>(0h3f), UInt<6>(0h0)) node hr_array_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) node hr_array_lo = cat(hr_array_lo_hi, entries_barrier.io.y.hr) node hr_array_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) node hr_array_hi = cat(hr_array_hi_hi, entries_barrier_3.io.y.hr) node _hr_array_T = cat(hr_array_hi, hr_array_lo) node hr_array_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hr_array_lo_1 = cat(hr_array_lo_hi_1, entries_barrier.io.y.hx) node hr_array_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hr_array_hi_1 = cat(hr_array_hi_hi_1, entries_barrier_3.io.y.hx) node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) node hw_array_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) node hw_array_lo = cat(hw_array_lo_hi, entries_barrier.io.y.hw) node hw_array_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) node hw_array_hi = cat(hw_array_hi_hi, entries_barrier_3.io.y.hw) node _hw_array_T = cat(hw_array_hi, hw_array_lo) node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) node hx_array_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hx_array_lo = cat(hx_array_lo_hi, entries_barrier.io.y.hx) node hx_array_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hx_array_hi = cat(hx_array_hi_hi, entries_barrier_3.io.y.hx) node _hx_array_T = cat(hx_array_hi, hx_array_lo) node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo = cat(entries_barrier_1.io.y.pr, entries_barrier.io.y.pr) node pr_array_hi_hi = cat(entries_barrier_4.io.y.pr, entries_barrier_3.io.y.pr) node pr_array_hi = cat(pr_array_hi_hi, entries_barrier_2.io.y.pr) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) node _pr_array_T_4 = not(_pr_array_T_3) node pr_array = and(_pr_array_T_2, _pr_array_T_4) node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo = cat(entries_barrier_1.io.y.pw, entries_barrier.io.y.pw) node pw_array_hi_hi = cat(entries_barrier_4.io.y.pw, entries_barrier_3.io.y.pw) node pw_array_hi = cat(pw_array_hi_hi, entries_barrier_2.io.y.pw) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) node _pw_array_T_4 = not(_pw_array_T_3) node pw_array = and(_pw_array_T_2, _pw_array_T_4) node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo = cat(entries_barrier_1.io.y.px, entries_barrier.io.y.px) node px_array_hi_hi = cat(entries_barrier_4.io.y.px, entries_barrier_3.io.y.px) node px_array_hi = cat(px_array_hi_hi, entries_barrier_2.io.y.px) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = or(ptw_ae_array, final_ae_array) node _px_array_T_4 = not(_px_array_T_3) node px_array = and(_px_array_T_2, _px_array_T_4) node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo = cat(entries_barrier_1.io.y.eff, entries_barrier.io.y.eff) node eff_array_hi_hi = cat(entries_barrier_4.io.y.eff, entries_barrier_3.io.y.eff) node eff_array_hi = cat(eff_array_hi_hi, entries_barrier_2.io.y.eff) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node eff_array = cat(_eff_array_T, _eff_array_T_1) node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) node c_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) node c_array_hi = cat(c_array_hi_hi, entries_barrier_2.io.y.c) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node c_array = cat(_c_array_T, _c_array_T_1) node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) node ppp_array_lo = cat(entries_barrier_1.io.y.ppp, entries_barrier.io.y.ppp) node ppp_array_hi_hi = cat(entries_barrier_4.io.y.ppp, entries_barrier_3.io.y.ppp) node ppp_array_hi = cat(ppp_array_hi_hi, entries_barrier_2.io.y.ppp) node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo = cat(entries_barrier_1.io.y.paa, entries_barrier.io.y.paa) node paa_array_hi_hi = cat(entries_barrier_4.io.y.paa, entries_barrier_3.io.y.paa) node paa_array_hi = cat(paa_array_hi_hi, entries_barrier_2.io.y.paa) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node paa_array = cat(_paa_array_T, _paa_array_T_1) node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo = cat(entries_barrier_1.io.y.pal, entries_barrier.io.y.pal) node pal_array_hi_hi = cat(entries_barrier_4.io.y.pal, entries_barrier_3.io.y.pal) node pal_array_hi = cat(pal_array_hi_hi, entries_barrier_2.io.y.pal) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node pal_array = cat(_pal_array_T, _pal_array_T_1) node ppp_array_if_cached = or(ppp_array, c_array) node paa_array_if_cached = or(paa_array, c_array) node pal_array_if_cached = or(pal_array, c_array) node _prefetchable_array_T = and(cacheable, homogeneous) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) node prefetchable_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, entries_barrier_2.io.y.c) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) node misaligned = orr(_misaligned_T_3) node _bad_va_T = and(vm_enabled, stage1_en) node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3) node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4) node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0)) node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6) node bad_va = and(_bad_va_T, _bad_va_T_7) node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2) node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6) node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array) node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed) node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) node ae_array = or(_ae_array_T, _ae_array_T_2) node _ae_ld_array_T = not(pr_array) node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T) node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0)) node _ae_st_array_T = not(pw_array) node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(ppp_array_if_cached) node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(pal_array_if_cached) node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) node _ae_st_array_T_9 = not(paa_array_if_cached) node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) node _must_alloc_array_T = not(ppp_array) node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array) node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(paa_array) node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) node _must_alloc_array_T_8 = not(UInt<7>(0h0)) node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = not(ptw_ae_array) node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) node _pf_ld_array_T_5 = not(ptw_gf_array) node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) node _pf_st_array_T = not(w_array) node _pf_st_array_T_1 = not(ptw_ae_array) node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) node _pf_st_array_T_4 = not(ptw_gf_array) node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) node _pf_inst_array_T = not(x_array) node _pf_inst_array_T_1 = not(ptw_ae_array) node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) node _pf_inst_array_T_4 = not(ptw_gf_array) node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) node _gf_ld_array_T = and(priv_v, cmd_read) node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array) node _gf_ld_array_T_4 = not(ptw_ae_array) node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4) node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) node _gf_st_array_T = and(priv_v, cmd_write_perms) node _gf_st_array_T_1 = not(hw_array) node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array) node _gf_st_array_T_3 = not(ptw_ae_array) node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3) node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) node _gf_inst_array_T = not(hx_array) node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array) node _gf_inst_array_T_2 = not(ptw_ae_array) node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2) node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) node gpa_hits_need_gpa_mask = or(gf_ld_array, gf_st_array) node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<5>(0h1f), UInt<5>(0h0)) node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<6>(0h3f), UInt<6>(0h0)) node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) node _gpa_hits_T = bits(gpa_hits_need_gpa_mask, 5, 0) node _gpa_hits_T_1 = not(_gpa_hits_T) node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) node tlb_hit_if_not_gpa_miss = orr(real_hits) node _tlb_hit_T = and(real_hits, gpa_hits) node tlb_hit = orr(_tlb_hit_T) node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) reg state_reg : UInt<0>, clock reg state_vec : UInt<0>[1], clock regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _T_9 = and(io.req.valid, vm_enabled) when _T_9 : when sector_hits_0 : connect state_vec[0], UInt<1>(0h0) node _T_10 = or(superpage_hits_0, superpage_hits_1) node _T_11 = or(_T_10, superpage_hits_2) node _T_12 = or(_T_11, superpage_hits_3) when _T_12 : node lo = cat(superpage_hits_1, superpage_hits_0) node hi = cat(superpage_hits_3, superpage_hits_2) node _T_13 = cat(hi, lo) node hi_1 = bits(_T_13, 3, 2) node lo_1 = bits(_T_13, 1, 0) node _T_14 = orr(hi_1) node _T_15 = or(hi_1, lo_1) node _T_16 = bits(_T_15, 1, 1) node _T_17 = cat(_T_14, _T_16) node state_reg_touch_way_sized = bits(_T_17, 1, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg_1, 1, 1) node state_reg_right_subtree_state = bits(state_reg_1, 0, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_1 = bits(_state_reg_T, 0, 0) node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0)) node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2) node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0) node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0)) node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state) node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3) node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7) connect state_reg_1, _state_reg_T_8 node _multipleHits_T = bits(real_hits, 2, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_1, 0, 0) node _multipleHits_T_2 = bits(_multipleHits_T, 2, 1) node _multipleHits_T_3 = bits(_multipleHits_T_2, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_3, 0, 0) node _multipleHits_T_4 = bits(_multipleHits_T_2, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_4, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_5 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_6 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_5, _multipleHits_T_6) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_7 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_8 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_7, _multipleHits_T_8) node _multipleHits_T_9 = bits(real_hits, 5, 3) node _multipleHits_T_10 = bits(_multipleHits_T_9, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_10, 0, 0) node _multipleHits_T_11 = bits(_multipleHits_T_9, 2, 1) node _multipleHits_T_12 = bits(_multipleHits_T_11, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_12, 0, 0) node _multipleHits_T_13 = bits(_multipleHits_T_11, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_13, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_14 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_15 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_14, _multipleHits_T_15) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_16 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_17 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_16, _multipleHits_T_17) node _multipleHits_T_18 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits = or(_multipleHits_T_19, _multipleHits_T_20) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_resp_pf_ld_T = and(bad_va, cmd_read) node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) connect io.resp.pf.ld, _io_resp_pf_ld_T_3 node _io_resp_pf_st_T = and(bad_va, cmd_write_perms) node _io_resp_pf_st_T_1 = and(pf_st_array, hits) node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) connect io.resp.pf.st, _io_resp_pf_st_T_3 node _io_resp_pf_inst_T = and(pf_inst_array, hits) node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1) connect io.resp.pf.inst, _io_resp_pf_inst_T_2 node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) connect io.resp.gf.ld, _io_resp_gf_ld_T_3 node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) node _io_resp_gf_st_T_1 = and(gf_st_array, hits) node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) connect io.resp.gf.st, _io_resp_gf_st_T_3 node _io_resp_gf_inst_T = and(gf_inst_array, hits) node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) connect io.resp.gf.inst, _io_resp_gf_inst_T_2 node _io_resp_ae_ld_T = and(ae_ld_array, hits) node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) connect io.resp.ae.ld, _io_resp_ae_ld_T_1 node _io_resp_ae_st_T = and(ae_st_array, hits) node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) connect io.resp.ae.st, _io_resp_ae_st_T_1 node _io_resp_ae_inst_T = not(px_array) node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) connect io.resp.ae.inst, _io_resp_ae_inst_T_2 node _io_resp_ma_ld_T = and(misaligned, cmd_read) connect io.resp.ma.ld, _io_resp_ma_ld_T node _io_resp_ma_st_T = and(misaligned, cmd_write) connect io.resp.ma.st, _io_resp_ma_st_T connect io.resp.ma.inst, UInt<1>(0h0) node _io_resp_cacheable_T = and(c_array, hits) node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) connect io.resp.cacheable, _io_resp_cacheable_T_1 node _io_resp_must_alloc_T = and(must_alloc_array, hits) node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) connect io.resp.must_alloc, _io_resp_must_alloc_T_1 node _io_resp_prefetchable_T = and(prefetchable_array, hits) node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) connect io.resp.prefetchable, _io_resp_prefetchable_T_2 node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) connect io.resp.miss, _io_resp_miss_T_2 node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) connect io.resp.paddr, _io_resp_paddr_T_1 connect io.resp.size, io.req.bits.size connect io.resp.cmd, io.req.bits.cmd node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) connect io.resp.gpa, _io_resp_gpa_T node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag connect io.ptw.req.bits.bits.vstage1, r_vstage1_en connect io.ptw.req.bits.bits.stage2, r_stage2_en connect io.ptw.req.bits.bits.need_gpa, r_need_gpa node _T_18 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_19 = and(_T_18, io.ptw.req.bits.valid) when _T_19 : connect r_gpa_valid, UInt<1>(0h0) connect r_gpa_vpn, r_refill_tag node _T_20 = and(io.req.ready, io.req.valid) node _T_21 = and(_T_20, tlb_miss) when _T_21 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn connect r_need_gpa, tlb_hit_if_not_gpa_miss connect r_vstage1_en, vstage1_en connect r_stage2_en, stage2_en node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2) node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1) node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0) node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0) node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0) node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1) node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2) node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0]) node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0]) node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo) node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0) node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1) node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2) node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3) node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10) node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11) node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13 node _r_sectored_repl_addr_valids_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0][0].valid[2]) node r_sectored_repl_addr_valids = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0][0].valid[3]) node _r_sectored_repl_addr_T = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_1 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_2 = bits(_r_sectored_repl_addr_T_1, 0, 0) node _r_sectored_repl_addr_T_3 = mux(_r_sectored_repl_addr_T, UInt<1>(0h0), UInt<1>(0h0)) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_3 connect r_sectored_hit.valid, sector_hits_0 connect r_sectored_hit.bits, UInt<1>(0h0) node _r_superpage_hit_valid_T = or(superpage_hits_0, superpage_hits_1) node _r_superpage_hit_valid_T_1 = or(_r_superpage_hit_valid_T, superpage_hits_2) node _r_superpage_hit_valid_T_2 = or(_r_superpage_hit_valid_T_1, superpage_hits_3) connect r_superpage_hit.valid, _r_superpage_hit_valid_T_2 node r_superpage_hit_bits_lo = cat(superpage_hits_1, superpage_hits_0) node r_superpage_hit_bits_hi = cat(superpage_hits_3, superpage_hits_2) node _r_superpage_hit_bits_T = cat(r_superpage_hit_bits_hi, r_superpage_hit_bits_lo) node r_superpage_hit_bits_hi_1 = bits(_r_superpage_hit_bits_T, 3, 2) node r_superpage_hit_bits_lo_1 = bits(_r_superpage_hit_bits_T, 1, 0) node _r_superpage_hit_bits_T_1 = orr(r_superpage_hit_bits_hi_1) node _r_superpage_hit_bits_T_2 = or(r_superpage_hit_bits_hi_1, r_superpage_hit_bits_lo_1) node _r_superpage_hit_bits_T_3 = bits(_r_superpage_hit_bits_T_2, 1, 1) node _r_superpage_hit_bits_T_4 = cat(_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3) connect r_superpage_hit.bits, _r_superpage_hit_bits_T_4 node _T_22 = eq(state, UInt<2>(0h1)) when _T_22 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_23 = eq(state, UInt<2>(0h2)) node _T_24 = and(_T_23, io.sfence.valid) when _T_24 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_25 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_26 = shr(io.sfence.bits.addr, 12) node _T_27 = eq(_T_26, vpn) node _T_28 = or(_T_25, _T_27) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf assert(clock, _T_28, UInt<1>(0h1), "") : assert node hv = and(UInt<1>(0h0), io.sfence.bits.hv) node hg = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_32 = eq(hg, UInt<1>(0h0)) node _T_33 = and(_T_32, io.sfence.bits.rs1) when _T_33 : node _T_34 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_35 = shr(_T_34, 2) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = eq(sectored_entries[0][0].tag_v, hv) node _T_38 = and(_T_36, _T_37) when _T_38 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<42> connect _WIRE_1, sectored_entries[0][0].data[0] node _T_39 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_39 node _T_40 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_40 node _T_41 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_41 node _T_42 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_42 node _T_43 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_43 node _T_44 = bits(_WIRE_1, 5, 5) connect _WIRE.ppp, _T_44 node _T_45 = bits(_WIRE_1, 6, 6) connect _WIRE.pr, _T_45 node _T_46 = bits(_WIRE_1, 7, 7) connect _WIRE.px, _T_46 node _T_47 = bits(_WIRE_1, 8, 8) connect _WIRE.pw, _T_47 node _T_48 = bits(_WIRE_1, 9, 9) connect _WIRE.hr, _T_48 node _T_49 = bits(_WIRE_1, 10, 10) connect _WIRE.hx, _T_49 node _T_50 = bits(_WIRE_1, 11, 11) connect _WIRE.hw, _T_50 node _T_51 = bits(_WIRE_1, 12, 12) connect _WIRE.sr, _T_51 node _T_52 = bits(_WIRE_1, 13, 13) connect _WIRE.sx, _T_52 node _T_53 = bits(_WIRE_1, 14, 14) connect _WIRE.sw, _T_53 node _T_54 = bits(_WIRE_1, 15, 15) connect _WIRE.gf, _T_54 node _T_55 = bits(_WIRE_1, 16, 16) connect _WIRE.pf, _T_55 node _T_56 = bits(_WIRE_1, 17, 17) connect _WIRE.ae_stage2, _T_56 node _T_57 = bits(_WIRE_1, 18, 18) connect _WIRE.ae_final, _T_57 node _T_58 = bits(_WIRE_1, 19, 19) connect _WIRE.ae_ptw, _T_58 node _T_59 = bits(_WIRE_1, 20, 20) connect _WIRE.g, _T_59 node _T_60 = bits(_WIRE_1, 21, 21) connect _WIRE.u, _T_60 node _T_61 = bits(_WIRE_1, 41, 22) connect _WIRE.ppn, _T_61 wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<42> connect _WIRE_3, sectored_entries[0][0].data[1] node _T_62 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_62 node _T_63 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_63 node _T_64 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_64 node _T_65 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_65 node _T_66 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_66 node _T_67 = bits(_WIRE_3, 5, 5) connect _WIRE_2.ppp, _T_67 node _T_68 = bits(_WIRE_3, 6, 6) connect _WIRE_2.pr, _T_68 node _T_69 = bits(_WIRE_3, 7, 7) connect _WIRE_2.px, _T_69 node _T_70 = bits(_WIRE_3, 8, 8) connect _WIRE_2.pw, _T_70 node _T_71 = bits(_WIRE_3, 9, 9) connect _WIRE_2.hr, _T_71 node _T_72 = bits(_WIRE_3, 10, 10) connect _WIRE_2.hx, _T_72 node _T_73 = bits(_WIRE_3, 11, 11) connect _WIRE_2.hw, _T_73 node _T_74 = bits(_WIRE_3, 12, 12) connect _WIRE_2.sr, _T_74 node _T_75 = bits(_WIRE_3, 13, 13) connect _WIRE_2.sx, _T_75 node _T_76 = bits(_WIRE_3, 14, 14) connect _WIRE_2.sw, _T_76 node _T_77 = bits(_WIRE_3, 15, 15) connect _WIRE_2.gf, _T_77 node _T_78 = bits(_WIRE_3, 16, 16) connect _WIRE_2.pf, _T_78 node _T_79 = bits(_WIRE_3, 17, 17) connect _WIRE_2.ae_stage2, _T_79 node _T_80 = bits(_WIRE_3, 18, 18) connect _WIRE_2.ae_final, _T_80 node _T_81 = bits(_WIRE_3, 19, 19) connect _WIRE_2.ae_ptw, _T_81 node _T_82 = bits(_WIRE_3, 20, 20) connect _WIRE_2.g, _T_82 node _T_83 = bits(_WIRE_3, 21, 21) connect _WIRE_2.u, _T_83 node _T_84 = bits(_WIRE_3, 41, 22) connect _WIRE_2.ppn, _T_84 wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<42> connect _WIRE_5, sectored_entries[0][0].data[2] node _T_85 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_85 node _T_86 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_86 node _T_87 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_87 node _T_88 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_88 node _T_89 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_89 node _T_90 = bits(_WIRE_5, 5, 5) connect _WIRE_4.ppp, _T_90 node _T_91 = bits(_WIRE_5, 6, 6) connect _WIRE_4.pr, _T_91 node _T_92 = bits(_WIRE_5, 7, 7) connect _WIRE_4.px, _T_92 node _T_93 = bits(_WIRE_5, 8, 8) connect _WIRE_4.pw, _T_93 node _T_94 = bits(_WIRE_5, 9, 9) connect _WIRE_4.hr, _T_94 node _T_95 = bits(_WIRE_5, 10, 10) connect _WIRE_4.hx, _T_95 node _T_96 = bits(_WIRE_5, 11, 11) connect _WIRE_4.hw, _T_96 node _T_97 = bits(_WIRE_5, 12, 12) connect _WIRE_4.sr, _T_97 node _T_98 = bits(_WIRE_5, 13, 13) connect _WIRE_4.sx, _T_98 node _T_99 = bits(_WIRE_5, 14, 14) connect _WIRE_4.sw, _T_99 node _T_100 = bits(_WIRE_5, 15, 15) connect _WIRE_4.gf, _T_100 node _T_101 = bits(_WIRE_5, 16, 16) connect _WIRE_4.pf, _T_101 node _T_102 = bits(_WIRE_5, 17, 17) connect _WIRE_4.ae_stage2, _T_102 node _T_103 = bits(_WIRE_5, 18, 18) connect _WIRE_4.ae_final, _T_103 node _T_104 = bits(_WIRE_5, 19, 19) connect _WIRE_4.ae_ptw, _T_104 node _T_105 = bits(_WIRE_5, 20, 20) connect _WIRE_4.g, _T_105 node _T_106 = bits(_WIRE_5, 21, 21) connect _WIRE_4.u, _T_106 node _T_107 = bits(_WIRE_5, 41, 22) connect _WIRE_4.ppn, _T_107 wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<42> connect _WIRE_7, sectored_entries[0][0].data[3] node _T_108 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_108 node _T_109 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_109 node _T_110 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_110 node _T_111 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_111 node _T_112 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_112 node _T_113 = bits(_WIRE_7, 5, 5) connect _WIRE_6.ppp, _T_113 node _T_114 = bits(_WIRE_7, 6, 6) connect _WIRE_6.pr, _T_114 node _T_115 = bits(_WIRE_7, 7, 7) connect _WIRE_6.px, _T_115 node _T_116 = bits(_WIRE_7, 8, 8) connect _WIRE_6.pw, _T_116 node _T_117 = bits(_WIRE_7, 9, 9) connect _WIRE_6.hr, _T_117 node _T_118 = bits(_WIRE_7, 10, 10) connect _WIRE_6.hx, _T_118 node _T_119 = bits(_WIRE_7, 11, 11) connect _WIRE_6.hw, _T_119 node _T_120 = bits(_WIRE_7, 12, 12) connect _WIRE_6.sr, _T_120 node _T_121 = bits(_WIRE_7, 13, 13) connect _WIRE_6.sx, _T_121 node _T_122 = bits(_WIRE_7, 14, 14) connect _WIRE_6.sw, _T_122 node _T_123 = bits(_WIRE_7, 15, 15) connect _WIRE_6.gf, _T_123 node _T_124 = bits(_WIRE_7, 16, 16) connect _WIRE_6.pf, _T_124 node _T_125 = bits(_WIRE_7, 17, 17) connect _WIRE_6.ae_stage2, _T_125 node _T_126 = bits(_WIRE_7, 18, 18) connect _WIRE_6.ae_final, _T_126 node _T_127 = bits(_WIRE_7, 19, 19) connect _WIRE_6.ae_ptw, _T_127 node _T_128 = bits(_WIRE_7, 20, 20) connect _WIRE_6.g, _T_128 node _T_129 = bits(_WIRE_7, 21, 21) connect _WIRE_6.u, _T_129 node _T_130 = bits(_WIRE_7, 41, 22) connect _WIRE_6.ppn, _T_130 node _T_131 = eq(sectored_entries[0][0].tag_v, hv) node _T_132 = bits(vpn, 1, 0) node _T_133 = eq(UInt<1>(0h0), _T_132) node _T_134 = and(_T_131, _T_133) when _T_134 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_135 = eq(sectored_entries[0][0].tag_v, hv) node _T_136 = bits(vpn, 1, 0) node _T_137 = eq(UInt<1>(0h1), _T_136) node _T_138 = and(_T_135, _T_137) when _T_138 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_139 = eq(sectored_entries[0][0].tag_v, hv) node _T_140 = bits(vpn, 1, 0) node _T_141 = eq(UInt<2>(0h2), _T_140) node _T_142 = and(_T_139, _T_141) when _T_142 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_143 = eq(sectored_entries[0][0].tag_v, hv) node _T_144 = bits(vpn, 1, 0) node _T_145 = eq(UInt<2>(0h3), _T_144) node _T_146 = and(_T_143, _T_145) when _T_146 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_147 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_148 = shr(_T_147, 18) node _T_149 = eq(_T_148, UInt<1>(0h0)) when _T_149 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<42> connect _WIRE_9, sectored_entries[0][0].data[0] node _T_150 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_150 node _T_151 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_151 node _T_152 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_152 node _T_153 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_153 node _T_154 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_154 node _T_155 = bits(_WIRE_9, 5, 5) connect _WIRE_8.ppp, _T_155 node _T_156 = bits(_WIRE_9, 6, 6) connect _WIRE_8.pr, _T_156 node _T_157 = bits(_WIRE_9, 7, 7) connect _WIRE_8.px, _T_157 node _T_158 = bits(_WIRE_9, 8, 8) connect _WIRE_8.pw, _T_158 node _T_159 = bits(_WIRE_9, 9, 9) connect _WIRE_8.hr, _T_159 node _T_160 = bits(_WIRE_9, 10, 10) connect _WIRE_8.hx, _T_160 node _T_161 = bits(_WIRE_9, 11, 11) connect _WIRE_8.hw, _T_161 node _T_162 = bits(_WIRE_9, 12, 12) connect _WIRE_8.sr, _T_162 node _T_163 = bits(_WIRE_9, 13, 13) connect _WIRE_8.sx, _T_163 node _T_164 = bits(_WIRE_9, 14, 14) connect _WIRE_8.sw, _T_164 node _T_165 = bits(_WIRE_9, 15, 15) connect _WIRE_8.gf, _T_165 node _T_166 = bits(_WIRE_9, 16, 16) connect _WIRE_8.pf, _T_166 node _T_167 = bits(_WIRE_9, 17, 17) connect _WIRE_8.ae_stage2, _T_167 node _T_168 = bits(_WIRE_9, 18, 18) connect _WIRE_8.ae_final, _T_168 node _T_169 = bits(_WIRE_9, 19, 19) connect _WIRE_8.ae_ptw, _T_169 node _T_170 = bits(_WIRE_9, 20, 20) connect _WIRE_8.g, _T_170 node _T_171 = bits(_WIRE_9, 21, 21) connect _WIRE_8.u, _T_171 node _T_172 = bits(_WIRE_9, 41, 22) connect _WIRE_8.ppn, _T_172 wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<42> connect _WIRE_11, sectored_entries[0][0].data[1] node _T_173 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_173 node _T_174 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_174 node _T_175 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_175 node _T_176 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_176 node _T_177 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_177 node _T_178 = bits(_WIRE_11, 5, 5) connect _WIRE_10.ppp, _T_178 node _T_179 = bits(_WIRE_11, 6, 6) connect _WIRE_10.pr, _T_179 node _T_180 = bits(_WIRE_11, 7, 7) connect _WIRE_10.px, _T_180 node _T_181 = bits(_WIRE_11, 8, 8) connect _WIRE_10.pw, _T_181 node _T_182 = bits(_WIRE_11, 9, 9) connect _WIRE_10.hr, _T_182 node _T_183 = bits(_WIRE_11, 10, 10) connect _WIRE_10.hx, _T_183 node _T_184 = bits(_WIRE_11, 11, 11) connect _WIRE_10.hw, _T_184 node _T_185 = bits(_WIRE_11, 12, 12) connect _WIRE_10.sr, _T_185 node _T_186 = bits(_WIRE_11, 13, 13) connect _WIRE_10.sx, _T_186 node _T_187 = bits(_WIRE_11, 14, 14) connect _WIRE_10.sw, _T_187 node _T_188 = bits(_WIRE_11, 15, 15) connect _WIRE_10.gf, _T_188 node _T_189 = bits(_WIRE_11, 16, 16) connect _WIRE_10.pf, _T_189 node _T_190 = bits(_WIRE_11, 17, 17) connect _WIRE_10.ae_stage2, _T_190 node _T_191 = bits(_WIRE_11, 18, 18) connect _WIRE_10.ae_final, _T_191 node _T_192 = bits(_WIRE_11, 19, 19) connect _WIRE_10.ae_ptw, _T_192 node _T_193 = bits(_WIRE_11, 20, 20) connect _WIRE_10.g, _T_193 node _T_194 = bits(_WIRE_11, 21, 21) connect _WIRE_10.u, _T_194 node _T_195 = bits(_WIRE_11, 41, 22) connect _WIRE_10.ppn, _T_195 wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<42> connect _WIRE_13, sectored_entries[0][0].data[2] node _T_196 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_196 node _T_197 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_197 node _T_198 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_198 node _T_199 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_199 node _T_200 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_200 node _T_201 = bits(_WIRE_13, 5, 5) connect _WIRE_12.ppp, _T_201 node _T_202 = bits(_WIRE_13, 6, 6) connect _WIRE_12.pr, _T_202 node _T_203 = bits(_WIRE_13, 7, 7) connect _WIRE_12.px, _T_203 node _T_204 = bits(_WIRE_13, 8, 8) connect _WIRE_12.pw, _T_204 node _T_205 = bits(_WIRE_13, 9, 9) connect _WIRE_12.hr, _T_205 node _T_206 = bits(_WIRE_13, 10, 10) connect _WIRE_12.hx, _T_206 node _T_207 = bits(_WIRE_13, 11, 11) connect _WIRE_12.hw, _T_207 node _T_208 = bits(_WIRE_13, 12, 12) connect _WIRE_12.sr, _T_208 node _T_209 = bits(_WIRE_13, 13, 13) connect _WIRE_12.sx, _T_209 node _T_210 = bits(_WIRE_13, 14, 14) connect _WIRE_12.sw, _T_210 node _T_211 = bits(_WIRE_13, 15, 15) connect _WIRE_12.gf, _T_211 node _T_212 = bits(_WIRE_13, 16, 16) connect _WIRE_12.pf, _T_212 node _T_213 = bits(_WIRE_13, 17, 17) connect _WIRE_12.ae_stage2, _T_213 node _T_214 = bits(_WIRE_13, 18, 18) connect _WIRE_12.ae_final, _T_214 node _T_215 = bits(_WIRE_13, 19, 19) connect _WIRE_12.ae_ptw, _T_215 node _T_216 = bits(_WIRE_13, 20, 20) connect _WIRE_12.g, _T_216 node _T_217 = bits(_WIRE_13, 21, 21) connect _WIRE_12.u, _T_217 node _T_218 = bits(_WIRE_13, 41, 22) connect _WIRE_12.ppn, _T_218 wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<42> connect _WIRE_15, sectored_entries[0][0].data[3] node _T_219 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_219 node _T_220 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_220 node _T_221 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_221 node _T_222 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_222 node _T_223 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_223 node _T_224 = bits(_WIRE_15, 5, 5) connect _WIRE_14.ppp, _T_224 node _T_225 = bits(_WIRE_15, 6, 6) connect _WIRE_14.pr, _T_225 node _T_226 = bits(_WIRE_15, 7, 7) connect _WIRE_14.px, _T_226 node _T_227 = bits(_WIRE_15, 8, 8) connect _WIRE_14.pw, _T_227 node _T_228 = bits(_WIRE_15, 9, 9) connect _WIRE_14.hr, _T_228 node _T_229 = bits(_WIRE_15, 10, 10) connect _WIRE_14.hx, _T_229 node _T_230 = bits(_WIRE_15, 11, 11) connect _WIRE_14.hw, _T_230 node _T_231 = bits(_WIRE_15, 12, 12) connect _WIRE_14.sr, _T_231 node _T_232 = bits(_WIRE_15, 13, 13) connect _WIRE_14.sx, _T_232 node _T_233 = bits(_WIRE_15, 14, 14) connect _WIRE_14.sw, _T_233 node _T_234 = bits(_WIRE_15, 15, 15) connect _WIRE_14.gf, _T_234 node _T_235 = bits(_WIRE_15, 16, 16) connect _WIRE_14.pf, _T_235 node _T_236 = bits(_WIRE_15, 17, 17) connect _WIRE_14.ae_stage2, _T_236 node _T_237 = bits(_WIRE_15, 18, 18) connect _WIRE_14.ae_final, _T_237 node _T_238 = bits(_WIRE_15, 19, 19) connect _WIRE_14.ae_ptw, _T_238 node _T_239 = bits(_WIRE_15, 20, 20) connect _WIRE_14.g, _T_239 node _T_240 = bits(_WIRE_15, 21, 21) connect _WIRE_14.u, _T_240 node _T_241 = bits(_WIRE_15, 41, 22) connect _WIRE_14.ppn, _T_241 node _T_242 = eq(sectored_entries[0][0].tag_v, hv) node _T_243 = and(_T_242, _WIRE_8.fragmented_superpage) when _T_243 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_244 = eq(sectored_entries[0][0].tag_v, hv) node _T_245 = and(_T_244, _WIRE_10.fragmented_superpage) when _T_245 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_246 = eq(sectored_entries[0][0].tag_v, hv) node _T_247 = and(_T_246, _WIRE_12.fragmented_superpage) when _T_247 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_248 = eq(sectored_entries[0][0].tag_v, hv) node _T_249 = and(_T_248, _WIRE_14.fragmented_superpage) when _T_249 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_250 = eq(hg, UInt<1>(0h0)) node _T_251 = and(_T_250, io.sfence.bits.rs2) when _T_251 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<42> connect _WIRE_17, sectored_entries[0][0].data[0] node _T_252 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_252 node _T_253 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_253 node _T_254 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_254 node _T_255 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_255 node _T_256 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_256 node _T_257 = bits(_WIRE_17, 5, 5) connect _WIRE_16.ppp, _T_257 node _T_258 = bits(_WIRE_17, 6, 6) connect _WIRE_16.pr, _T_258 node _T_259 = bits(_WIRE_17, 7, 7) connect _WIRE_16.px, _T_259 node _T_260 = bits(_WIRE_17, 8, 8) connect _WIRE_16.pw, _T_260 node _T_261 = bits(_WIRE_17, 9, 9) connect _WIRE_16.hr, _T_261 node _T_262 = bits(_WIRE_17, 10, 10) connect _WIRE_16.hx, _T_262 node _T_263 = bits(_WIRE_17, 11, 11) connect _WIRE_16.hw, _T_263 node _T_264 = bits(_WIRE_17, 12, 12) connect _WIRE_16.sr, _T_264 node _T_265 = bits(_WIRE_17, 13, 13) connect _WIRE_16.sx, _T_265 node _T_266 = bits(_WIRE_17, 14, 14) connect _WIRE_16.sw, _T_266 node _T_267 = bits(_WIRE_17, 15, 15) connect _WIRE_16.gf, _T_267 node _T_268 = bits(_WIRE_17, 16, 16) connect _WIRE_16.pf, _T_268 node _T_269 = bits(_WIRE_17, 17, 17) connect _WIRE_16.ae_stage2, _T_269 node _T_270 = bits(_WIRE_17, 18, 18) connect _WIRE_16.ae_final, _T_270 node _T_271 = bits(_WIRE_17, 19, 19) connect _WIRE_16.ae_ptw, _T_271 node _T_272 = bits(_WIRE_17, 20, 20) connect _WIRE_16.g, _T_272 node _T_273 = bits(_WIRE_17, 21, 21) connect _WIRE_16.u, _T_273 node _T_274 = bits(_WIRE_17, 41, 22) connect _WIRE_16.ppn, _T_274 wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<42> connect _WIRE_19, sectored_entries[0][0].data[1] node _T_275 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_275 node _T_276 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_276 node _T_277 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_277 node _T_278 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_278 node _T_279 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_279 node _T_280 = bits(_WIRE_19, 5, 5) connect _WIRE_18.ppp, _T_280 node _T_281 = bits(_WIRE_19, 6, 6) connect _WIRE_18.pr, _T_281 node _T_282 = bits(_WIRE_19, 7, 7) connect _WIRE_18.px, _T_282 node _T_283 = bits(_WIRE_19, 8, 8) connect _WIRE_18.pw, _T_283 node _T_284 = bits(_WIRE_19, 9, 9) connect _WIRE_18.hr, _T_284 node _T_285 = bits(_WIRE_19, 10, 10) connect _WIRE_18.hx, _T_285 node _T_286 = bits(_WIRE_19, 11, 11) connect _WIRE_18.hw, _T_286 node _T_287 = bits(_WIRE_19, 12, 12) connect _WIRE_18.sr, _T_287 node _T_288 = bits(_WIRE_19, 13, 13) connect _WIRE_18.sx, _T_288 node _T_289 = bits(_WIRE_19, 14, 14) connect _WIRE_18.sw, _T_289 node _T_290 = bits(_WIRE_19, 15, 15) connect _WIRE_18.gf, _T_290 node _T_291 = bits(_WIRE_19, 16, 16) connect _WIRE_18.pf, _T_291 node _T_292 = bits(_WIRE_19, 17, 17) connect _WIRE_18.ae_stage2, _T_292 node _T_293 = bits(_WIRE_19, 18, 18) connect _WIRE_18.ae_final, _T_293 node _T_294 = bits(_WIRE_19, 19, 19) connect _WIRE_18.ae_ptw, _T_294 node _T_295 = bits(_WIRE_19, 20, 20) connect _WIRE_18.g, _T_295 node _T_296 = bits(_WIRE_19, 21, 21) connect _WIRE_18.u, _T_296 node _T_297 = bits(_WIRE_19, 41, 22) connect _WIRE_18.ppn, _T_297 wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<42> connect _WIRE_21, sectored_entries[0][0].data[2] node _T_298 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_298 node _T_299 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_299 node _T_300 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_300 node _T_301 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_301 node _T_302 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_302 node _T_303 = bits(_WIRE_21, 5, 5) connect _WIRE_20.ppp, _T_303 node _T_304 = bits(_WIRE_21, 6, 6) connect _WIRE_20.pr, _T_304 node _T_305 = bits(_WIRE_21, 7, 7) connect _WIRE_20.px, _T_305 node _T_306 = bits(_WIRE_21, 8, 8) connect _WIRE_20.pw, _T_306 node _T_307 = bits(_WIRE_21, 9, 9) connect _WIRE_20.hr, _T_307 node _T_308 = bits(_WIRE_21, 10, 10) connect _WIRE_20.hx, _T_308 node _T_309 = bits(_WIRE_21, 11, 11) connect _WIRE_20.hw, _T_309 node _T_310 = bits(_WIRE_21, 12, 12) connect _WIRE_20.sr, _T_310 node _T_311 = bits(_WIRE_21, 13, 13) connect _WIRE_20.sx, _T_311 node _T_312 = bits(_WIRE_21, 14, 14) connect _WIRE_20.sw, _T_312 node _T_313 = bits(_WIRE_21, 15, 15) connect _WIRE_20.gf, _T_313 node _T_314 = bits(_WIRE_21, 16, 16) connect _WIRE_20.pf, _T_314 node _T_315 = bits(_WIRE_21, 17, 17) connect _WIRE_20.ae_stage2, _T_315 node _T_316 = bits(_WIRE_21, 18, 18) connect _WIRE_20.ae_final, _T_316 node _T_317 = bits(_WIRE_21, 19, 19) connect _WIRE_20.ae_ptw, _T_317 node _T_318 = bits(_WIRE_21, 20, 20) connect _WIRE_20.g, _T_318 node _T_319 = bits(_WIRE_21, 21, 21) connect _WIRE_20.u, _T_319 node _T_320 = bits(_WIRE_21, 41, 22) connect _WIRE_20.ppn, _T_320 wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<42> connect _WIRE_23, sectored_entries[0][0].data[3] node _T_321 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_321 node _T_322 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_322 node _T_323 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_323 node _T_324 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_324 node _T_325 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_325 node _T_326 = bits(_WIRE_23, 5, 5) connect _WIRE_22.ppp, _T_326 node _T_327 = bits(_WIRE_23, 6, 6) connect _WIRE_22.pr, _T_327 node _T_328 = bits(_WIRE_23, 7, 7) connect _WIRE_22.px, _T_328 node _T_329 = bits(_WIRE_23, 8, 8) connect _WIRE_22.pw, _T_329 node _T_330 = bits(_WIRE_23, 9, 9) connect _WIRE_22.hr, _T_330 node _T_331 = bits(_WIRE_23, 10, 10) connect _WIRE_22.hx, _T_331 node _T_332 = bits(_WIRE_23, 11, 11) connect _WIRE_22.hw, _T_332 node _T_333 = bits(_WIRE_23, 12, 12) connect _WIRE_22.sr, _T_333 node _T_334 = bits(_WIRE_23, 13, 13) connect _WIRE_22.sx, _T_334 node _T_335 = bits(_WIRE_23, 14, 14) connect _WIRE_22.sw, _T_335 node _T_336 = bits(_WIRE_23, 15, 15) connect _WIRE_22.gf, _T_336 node _T_337 = bits(_WIRE_23, 16, 16) connect _WIRE_22.pf, _T_337 node _T_338 = bits(_WIRE_23, 17, 17) connect _WIRE_22.ae_stage2, _T_338 node _T_339 = bits(_WIRE_23, 18, 18) connect _WIRE_22.ae_final, _T_339 node _T_340 = bits(_WIRE_23, 19, 19) connect _WIRE_22.ae_ptw, _T_340 node _T_341 = bits(_WIRE_23, 20, 20) connect _WIRE_22.g, _T_341 node _T_342 = bits(_WIRE_23, 21, 21) connect _WIRE_22.u, _T_342 node _T_343 = bits(_WIRE_23, 41, 22) connect _WIRE_22.ppn, _T_343 node _T_344 = eq(sectored_entries[0][0].tag_v, hv) node _T_345 = eq(_WIRE_16.g, UInt<1>(0h0)) node _T_346 = and(_T_344, _T_345) when _T_346 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_347 = eq(sectored_entries[0][0].tag_v, hv) node _T_348 = eq(_WIRE_18.g, UInt<1>(0h0)) node _T_349 = and(_T_347, _T_348) when _T_349 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_350 = eq(sectored_entries[0][0].tag_v, hv) node _T_351 = eq(_WIRE_20.g, UInt<1>(0h0)) node _T_352 = and(_T_350, _T_351) when _T_352 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_353 = eq(sectored_entries[0][0].tag_v, hv) node _T_354 = eq(_WIRE_22.g, UInt<1>(0h0)) node _T_355 = and(_T_353, _T_354) when _T_355 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_356 = or(hv, hg) wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<42> connect _WIRE_25, sectored_entries[0][0].data[0] node _T_357 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_357 node _T_358 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_358 node _T_359 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_359 node _T_360 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_360 node _T_361 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_361 node _T_362 = bits(_WIRE_25, 5, 5) connect _WIRE_24.ppp, _T_362 node _T_363 = bits(_WIRE_25, 6, 6) connect _WIRE_24.pr, _T_363 node _T_364 = bits(_WIRE_25, 7, 7) connect _WIRE_24.px, _T_364 node _T_365 = bits(_WIRE_25, 8, 8) connect _WIRE_24.pw, _T_365 node _T_366 = bits(_WIRE_25, 9, 9) connect _WIRE_24.hr, _T_366 node _T_367 = bits(_WIRE_25, 10, 10) connect _WIRE_24.hx, _T_367 node _T_368 = bits(_WIRE_25, 11, 11) connect _WIRE_24.hw, _T_368 node _T_369 = bits(_WIRE_25, 12, 12) connect _WIRE_24.sr, _T_369 node _T_370 = bits(_WIRE_25, 13, 13) connect _WIRE_24.sx, _T_370 node _T_371 = bits(_WIRE_25, 14, 14) connect _WIRE_24.sw, _T_371 node _T_372 = bits(_WIRE_25, 15, 15) connect _WIRE_24.gf, _T_372 node _T_373 = bits(_WIRE_25, 16, 16) connect _WIRE_24.pf, _T_373 node _T_374 = bits(_WIRE_25, 17, 17) connect _WIRE_24.ae_stage2, _T_374 node _T_375 = bits(_WIRE_25, 18, 18) connect _WIRE_24.ae_final, _T_375 node _T_376 = bits(_WIRE_25, 19, 19) connect _WIRE_24.ae_ptw, _T_376 node _T_377 = bits(_WIRE_25, 20, 20) connect _WIRE_24.g, _T_377 node _T_378 = bits(_WIRE_25, 21, 21) connect _WIRE_24.u, _T_378 node _T_379 = bits(_WIRE_25, 41, 22) connect _WIRE_24.ppn, _T_379 wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<42> connect _WIRE_27, sectored_entries[0][0].data[1] node _T_380 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_380 node _T_381 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_381 node _T_382 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_382 node _T_383 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_383 node _T_384 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_384 node _T_385 = bits(_WIRE_27, 5, 5) connect _WIRE_26.ppp, _T_385 node _T_386 = bits(_WIRE_27, 6, 6) connect _WIRE_26.pr, _T_386 node _T_387 = bits(_WIRE_27, 7, 7) connect _WIRE_26.px, _T_387 node _T_388 = bits(_WIRE_27, 8, 8) connect _WIRE_26.pw, _T_388 node _T_389 = bits(_WIRE_27, 9, 9) connect _WIRE_26.hr, _T_389 node _T_390 = bits(_WIRE_27, 10, 10) connect _WIRE_26.hx, _T_390 node _T_391 = bits(_WIRE_27, 11, 11) connect _WIRE_26.hw, _T_391 node _T_392 = bits(_WIRE_27, 12, 12) connect _WIRE_26.sr, _T_392 node _T_393 = bits(_WIRE_27, 13, 13) connect _WIRE_26.sx, _T_393 node _T_394 = bits(_WIRE_27, 14, 14) connect _WIRE_26.sw, _T_394 node _T_395 = bits(_WIRE_27, 15, 15) connect _WIRE_26.gf, _T_395 node _T_396 = bits(_WIRE_27, 16, 16) connect _WIRE_26.pf, _T_396 node _T_397 = bits(_WIRE_27, 17, 17) connect _WIRE_26.ae_stage2, _T_397 node _T_398 = bits(_WIRE_27, 18, 18) connect _WIRE_26.ae_final, _T_398 node _T_399 = bits(_WIRE_27, 19, 19) connect _WIRE_26.ae_ptw, _T_399 node _T_400 = bits(_WIRE_27, 20, 20) connect _WIRE_26.g, _T_400 node _T_401 = bits(_WIRE_27, 21, 21) connect _WIRE_26.u, _T_401 node _T_402 = bits(_WIRE_27, 41, 22) connect _WIRE_26.ppn, _T_402 wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<42> connect _WIRE_29, sectored_entries[0][0].data[2] node _T_403 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_403 node _T_404 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_404 node _T_405 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_405 node _T_406 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_406 node _T_407 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_407 node _T_408 = bits(_WIRE_29, 5, 5) connect _WIRE_28.ppp, _T_408 node _T_409 = bits(_WIRE_29, 6, 6) connect _WIRE_28.pr, _T_409 node _T_410 = bits(_WIRE_29, 7, 7) connect _WIRE_28.px, _T_410 node _T_411 = bits(_WIRE_29, 8, 8) connect _WIRE_28.pw, _T_411 node _T_412 = bits(_WIRE_29, 9, 9) connect _WIRE_28.hr, _T_412 node _T_413 = bits(_WIRE_29, 10, 10) connect _WIRE_28.hx, _T_413 node _T_414 = bits(_WIRE_29, 11, 11) connect _WIRE_28.hw, _T_414 node _T_415 = bits(_WIRE_29, 12, 12) connect _WIRE_28.sr, _T_415 node _T_416 = bits(_WIRE_29, 13, 13) connect _WIRE_28.sx, _T_416 node _T_417 = bits(_WIRE_29, 14, 14) connect _WIRE_28.sw, _T_417 node _T_418 = bits(_WIRE_29, 15, 15) connect _WIRE_28.gf, _T_418 node _T_419 = bits(_WIRE_29, 16, 16) connect _WIRE_28.pf, _T_419 node _T_420 = bits(_WIRE_29, 17, 17) connect _WIRE_28.ae_stage2, _T_420 node _T_421 = bits(_WIRE_29, 18, 18) connect _WIRE_28.ae_final, _T_421 node _T_422 = bits(_WIRE_29, 19, 19) connect _WIRE_28.ae_ptw, _T_422 node _T_423 = bits(_WIRE_29, 20, 20) connect _WIRE_28.g, _T_423 node _T_424 = bits(_WIRE_29, 21, 21) connect _WIRE_28.u, _T_424 node _T_425 = bits(_WIRE_29, 41, 22) connect _WIRE_28.ppn, _T_425 wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<42> connect _WIRE_31, sectored_entries[0][0].data[3] node _T_426 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_426 node _T_427 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_427 node _T_428 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_428 node _T_429 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_429 node _T_430 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_430 node _T_431 = bits(_WIRE_31, 5, 5) connect _WIRE_30.ppp, _T_431 node _T_432 = bits(_WIRE_31, 6, 6) connect _WIRE_30.pr, _T_432 node _T_433 = bits(_WIRE_31, 7, 7) connect _WIRE_30.px, _T_433 node _T_434 = bits(_WIRE_31, 8, 8) connect _WIRE_30.pw, _T_434 node _T_435 = bits(_WIRE_31, 9, 9) connect _WIRE_30.hr, _T_435 node _T_436 = bits(_WIRE_31, 10, 10) connect _WIRE_30.hx, _T_436 node _T_437 = bits(_WIRE_31, 11, 11) connect _WIRE_30.hw, _T_437 node _T_438 = bits(_WIRE_31, 12, 12) connect _WIRE_30.sr, _T_438 node _T_439 = bits(_WIRE_31, 13, 13) connect _WIRE_30.sx, _T_439 node _T_440 = bits(_WIRE_31, 14, 14) connect _WIRE_30.sw, _T_440 node _T_441 = bits(_WIRE_31, 15, 15) connect _WIRE_30.gf, _T_441 node _T_442 = bits(_WIRE_31, 16, 16) connect _WIRE_30.pf, _T_442 node _T_443 = bits(_WIRE_31, 17, 17) connect _WIRE_30.ae_stage2, _T_443 node _T_444 = bits(_WIRE_31, 18, 18) connect _WIRE_30.ae_final, _T_444 node _T_445 = bits(_WIRE_31, 19, 19) connect _WIRE_30.ae_ptw, _T_445 node _T_446 = bits(_WIRE_31, 20, 20) connect _WIRE_30.g, _T_446 node _T_447 = bits(_WIRE_31, 21, 21) connect _WIRE_30.u, _T_447 node _T_448 = bits(_WIRE_31, 41, 22) connect _WIRE_30.ppn, _T_448 node _T_449 = eq(sectored_entries[0][0].tag_v, _T_356) when _T_449 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_450 = eq(sectored_entries[0][0].tag_v, _T_356) when _T_450 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_451 = eq(sectored_entries[0][0].tag_v, _T_356) when _T_451 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_452 = eq(sectored_entries[0][0].tag_v, _T_356) when _T_452 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_453 = eq(hg_1, UInt<1>(0h0)) node _T_454 = and(_T_453, io.sfence.bits.rs1) when _T_454 : node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_1) node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T) node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_455 = xor(superpage_entries[0].tag_vpn, vpn) node _T_456 = bits(_T_455, 26, 18) node _T_457 = eq(_T_456, UInt<1>(0h0)) node _T_458 = or(ignore, _T_457) node _T_459 = and(tagMatch, _T_458) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_460 = xor(superpage_entries[0].tag_vpn, vpn) node _T_461 = bits(_T_460, 17, 9) node _T_462 = eq(_T_461, UInt<1>(0h0)) node _T_463 = or(ignore_1, _T_462) node _T_464 = and(_T_459, _T_463) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_465 = xor(superpage_entries[0].tag_vpn, vpn) node _T_466 = bits(_T_465, 8, 0) node _T_467 = eq(_T_466, UInt<1>(0h0)) node _T_468 = or(ignore_2, _T_467) node _T_469 = and(_T_464, _T_468) when _T_469 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_470 = xor(superpage_entries[0].tag_vpn, vpn) node _T_471 = shr(_T_470, 18) node _T_472 = eq(_T_471, UInt<1>(0h0)) when _T_472 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<42> connect _WIRE_33, superpage_entries[0].data[0] node _T_473 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_473 node _T_474 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_474 node _T_475 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_475 node _T_476 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_476 node _T_477 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_477 node _T_478 = bits(_WIRE_33, 5, 5) connect _WIRE_32.ppp, _T_478 node _T_479 = bits(_WIRE_33, 6, 6) connect _WIRE_32.pr, _T_479 node _T_480 = bits(_WIRE_33, 7, 7) connect _WIRE_32.px, _T_480 node _T_481 = bits(_WIRE_33, 8, 8) connect _WIRE_32.pw, _T_481 node _T_482 = bits(_WIRE_33, 9, 9) connect _WIRE_32.hr, _T_482 node _T_483 = bits(_WIRE_33, 10, 10) connect _WIRE_32.hx, _T_483 node _T_484 = bits(_WIRE_33, 11, 11) connect _WIRE_32.hw, _T_484 node _T_485 = bits(_WIRE_33, 12, 12) connect _WIRE_32.sr, _T_485 node _T_486 = bits(_WIRE_33, 13, 13) connect _WIRE_32.sx, _T_486 node _T_487 = bits(_WIRE_33, 14, 14) connect _WIRE_32.sw, _T_487 node _T_488 = bits(_WIRE_33, 15, 15) connect _WIRE_32.gf, _T_488 node _T_489 = bits(_WIRE_33, 16, 16) connect _WIRE_32.pf, _T_489 node _T_490 = bits(_WIRE_33, 17, 17) connect _WIRE_32.ae_stage2, _T_490 node _T_491 = bits(_WIRE_33, 18, 18) connect _WIRE_32.ae_final, _T_491 node _T_492 = bits(_WIRE_33, 19, 19) connect _WIRE_32.ae_ptw, _T_492 node _T_493 = bits(_WIRE_33, 20, 20) connect _WIRE_32.g, _T_493 node _T_494 = bits(_WIRE_33, 21, 21) connect _WIRE_32.u, _T_494 node _T_495 = bits(_WIRE_33, 41, 22) connect _WIRE_32.ppn, _T_495 node _T_496 = eq(superpage_entries[0].tag_v, hv_1) node _T_497 = and(_T_496, _WIRE_32.fragmented_superpage) when _T_497 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_498 = eq(hg_1, UInt<1>(0h0)) node _T_499 = and(_T_498, io.sfence.bits.rs2) when _T_499 : wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<42> connect _WIRE_35, superpage_entries[0].data[0] node _T_500 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_500 node _T_501 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_501 node _T_502 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_502 node _T_503 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_503 node _T_504 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_504 node _T_505 = bits(_WIRE_35, 5, 5) connect _WIRE_34.ppp, _T_505 node _T_506 = bits(_WIRE_35, 6, 6) connect _WIRE_34.pr, _T_506 node _T_507 = bits(_WIRE_35, 7, 7) connect _WIRE_34.px, _T_507 node _T_508 = bits(_WIRE_35, 8, 8) connect _WIRE_34.pw, _T_508 node _T_509 = bits(_WIRE_35, 9, 9) connect _WIRE_34.hr, _T_509 node _T_510 = bits(_WIRE_35, 10, 10) connect _WIRE_34.hx, _T_510 node _T_511 = bits(_WIRE_35, 11, 11) connect _WIRE_34.hw, _T_511 node _T_512 = bits(_WIRE_35, 12, 12) connect _WIRE_34.sr, _T_512 node _T_513 = bits(_WIRE_35, 13, 13) connect _WIRE_34.sx, _T_513 node _T_514 = bits(_WIRE_35, 14, 14) connect _WIRE_34.sw, _T_514 node _T_515 = bits(_WIRE_35, 15, 15) connect _WIRE_34.gf, _T_515 node _T_516 = bits(_WIRE_35, 16, 16) connect _WIRE_34.pf, _T_516 node _T_517 = bits(_WIRE_35, 17, 17) connect _WIRE_34.ae_stage2, _T_517 node _T_518 = bits(_WIRE_35, 18, 18) connect _WIRE_34.ae_final, _T_518 node _T_519 = bits(_WIRE_35, 19, 19) connect _WIRE_34.ae_ptw, _T_519 node _T_520 = bits(_WIRE_35, 20, 20) connect _WIRE_34.g, _T_520 node _T_521 = bits(_WIRE_35, 21, 21) connect _WIRE_34.u, _T_521 node _T_522 = bits(_WIRE_35, 41, 22) connect _WIRE_34.ppn, _T_522 node _T_523 = eq(superpage_entries[0].tag_v, hv_1) node _T_524 = eq(_WIRE_34.g, UInt<1>(0h0)) node _T_525 = and(_T_523, _T_524) when _T_525 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_526 = or(hv_1, hg_1) wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<42> connect _WIRE_37, superpage_entries[0].data[0] node _T_527 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_527 node _T_528 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_528 node _T_529 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_529 node _T_530 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_530 node _T_531 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_531 node _T_532 = bits(_WIRE_37, 5, 5) connect _WIRE_36.ppp, _T_532 node _T_533 = bits(_WIRE_37, 6, 6) connect _WIRE_36.pr, _T_533 node _T_534 = bits(_WIRE_37, 7, 7) connect _WIRE_36.px, _T_534 node _T_535 = bits(_WIRE_37, 8, 8) connect _WIRE_36.pw, _T_535 node _T_536 = bits(_WIRE_37, 9, 9) connect _WIRE_36.hr, _T_536 node _T_537 = bits(_WIRE_37, 10, 10) connect _WIRE_36.hx, _T_537 node _T_538 = bits(_WIRE_37, 11, 11) connect _WIRE_36.hw, _T_538 node _T_539 = bits(_WIRE_37, 12, 12) connect _WIRE_36.sr, _T_539 node _T_540 = bits(_WIRE_37, 13, 13) connect _WIRE_36.sx, _T_540 node _T_541 = bits(_WIRE_37, 14, 14) connect _WIRE_36.sw, _T_541 node _T_542 = bits(_WIRE_37, 15, 15) connect _WIRE_36.gf, _T_542 node _T_543 = bits(_WIRE_37, 16, 16) connect _WIRE_36.pf, _T_543 node _T_544 = bits(_WIRE_37, 17, 17) connect _WIRE_36.ae_stage2, _T_544 node _T_545 = bits(_WIRE_37, 18, 18) connect _WIRE_36.ae_final, _T_545 node _T_546 = bits(_WIRE_37, 19, 19) connect _WIRE_36.ae_ptw, _T_546 node _T_547 = bits(_WIRE_37, 20, 20) connect _WIRE_36.g, _T_547 node _T_548 = bits(_WIRE_37, 21, 21) connect _WIRE_36.u, _T_548 node _T_549 = bits(_WIRE_37, 41, 22) connect _WIRE_36.ppn, _T_549 node _T_550 = eq(superpage_entries[0].tag_v, _T_526) when _T_550 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_551 = eq(hg_2, UInt<1>(0h0)) node _T_552 = and(_T_551, io.sfence.bits.rs1) when _T_552 : node _tagMatch_T_1 = eq(superpage_entries[1].tag_v, hv_2) node tagMatch_1 = and(superpage_entries[1].valid[0], _tagMatch_T_1) node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_553 = xor(superpage_entries[1].tag_vpn, vpn) node _T_554 = bits(_T_553, 26, 18) node _T_555 = eq(_T_554, UInt<1>(0h0)) node _T_556 = or(ignore_3, _T_555) node _T_557 = and(tagMatch_1, _T_556) node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_558 = xor(superpage_entries[1].tag_vpn, vpn) node _T_559 = bits(_T_558, 17, 9) node _T_560 = eq(_T_559, UInt<1>(0h0)) node _T_561 = or(ignore_4, _T_560) node _T_562 = and(_T_557, _T_561) node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h1)) node _T_563 = xor(superpage_entries[1].tag_vpn, vpn) node _T_564 = bits(_T_563, 8, 0) node _T_565 = eq(_T_564, UInt<1>(0h0)) node _T_566 = or(ignore_5, _T_565) node _T_567 = and(_T_562, _T_566) when _T_567 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_568 = xor(superpage_entries[1].tag_vpn, vpn) node _T_569 = shr(_T_568, 18) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<42> connect _WIRE_39, superpage_entries[1].data[0] node _T_571 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_571 node _T_572 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_572 node _T_573 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_573 node _T_574 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_574 node _T_575 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_575 node _T_576 = bits(_WIRE_39, 5, 5) connect _WIRE_38.ppp, _T_576 node _T_577 = bits(_WIRE_39, 6, 6) connect _WIRE_38.pr, _T_577 node _T_578 = bits(_WIRE_39, 7, 7) connect _WIRE_38.px, _T_578 node _T_579 = bits(_WIRE_39, 8, 8) connect _WIRE_38.pw, _T_579 node _T_580 = bits(_WIRE_39, 9, 9) connect _WIRE_38.hr, _T_580 node _T_581 = bits(_WIRE_39, 10, 10) connect _WIRE_38.hx, _T_581 node _T_582 = bits(_WIRE_39, 11, 11) connect _WIRE_38.hw, _T_582 node _T_583 = bits(_WIRE_39, 12, 12) connect _WIRE_38.sr, _T_583 node _T_584 = bits(_WIRE_39, 13, 13) connect _WIRE_38.sx, _T_584 node _T_585 = bits(_WIRE_39, 14, 14) connect _WIRE_38.sw, _T_585 node _T_586 = bits(_WIRE_39, 15, 15) connect _WIRE_38.gf, _T_586 node _T_587 = bits(_WIRE_39, 16, 16) connect _WIRE_38.pf, _T_587 node _T_588 = bits(_WIRE_39, 17, 17) connect _WIRE_38.ae_stage2, _T_588 node _T_589 = bits(_WIRE_39, 18, 18) connect _WIRE_38.ae_final, _T_589 node _T_590 = bits(_WIRE_39, 19, 19) connect _WIRE_38.ae_ptw, _T_590 node _T_591 = bits(_WIRE_39, 20, 20) connect _WIRE_38.g, _T_591 node _T_592 = bits(_WIRE_39, 21, 21) connect _WIRE_38.u, _T_592 node _T_593 = bits(_WIRE_39, 41, 22) connect _WIRE_38.ppn, _T_593 node _T_594 = eq(superpage_entries[1].tag_v, hv_2) node _T_595 = and(_T_594, _WIRE_38.fragmented_superpage) when _T_595 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_596 = eq(hg_2, UInt<1>(0h0)) node _T_597 = and(_T_596, io.sfence.bits.rs2) when _T_597 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<42> connect _WIRE_41, superpage_entries[1].data[0] node _T_598 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_598 node _T_599 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_599 node _T_600 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_600 node _T_601 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_601 node _T_602 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_602 node _T_603 = bits(_WIRE_41, 5, 5) connect _WIRE_40.ppp, _T_603 node _T_604 = bits(_WIRE_41, 6, 6) connect _WIRE_40.pr, _T_604 node _T_605 = bits(_WIRE_41, 7, 7) connect _WIRE_40.px, _T_605 node _T_606 = bits(_WIRE_41, 8, 8) connect _WIRE_40.pw, _T_606 node _T_607 = bits(_WIRE_41, 9, 9) connect _WIRE_40.hr, _T_607 node _T_608 = bits(_WIRE_41, 10, 10) connect _WIRE_40.hx, _T_608 node _T_609 = bits(_WIRE_41, 11, 11) connect _WIRE_40.hw, _T_609 node _T_610 = bits(_WIRE_41, 12, 12) connect _WIRE_40.sr, _T_610 node _T_611 = bits(_WIRE_41, 13, 13) connect _WIRE_40.sx, _T_611 node _T_612 = bits(_WIRE_41, 14, 14) connect _WIRE_40.sw, _T_612 node _T_613 = bits(_WIRE_41, 15, 15) connect _WIRE_40.gf, _T_613 node _T_614 = bits(_WIRE_41, 16, 16) connect _WIRE_40.pf, _T_614 node _T_615 = bits(_WIRE_41, 17, 17) connect _WIRE_40.ae_stage2, _T_615 node _T_616 = bits(_WIRE_41, 18, 18) connect _WIRE_40.ae_final, _T_616 node _T_617 = bits(_WIRE_41, 19, 19) connect _WIRE_40.ae_ptw, _T_617 node _T_618 = bits(_WIRE_41, 20, 20) connect _WIRE_40.g, _T_618 node _T_619 = bits(_WIRE_41, 21, 21) connect _WIRE_40.u, _T_619 node _T_620 = bits(_WIRE_41, 41, 22) connect _WIRE_40.ppn, _T_620 node _T_621 = eq(superpage_entries[1].tag_v, hv_2) node _T_622 = eq(_WIRE_40.g, UInt<1>(0h0)) node _T_623 = and(_T_621, _T_622) when _T_623 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_624 = or(hv_2, hg_2) wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_43 : UInt<42> connect _WIRE_43, superpage_entries[1].data[0] node _T_625 = bits(_WIRE_43, 0, 0) connect _WIRE_42.fragmented_superpage, _T_625 node _T_626 = bits(_WIRE_43, 1, 1) connect _WIRE_42.c, _T_626 node _T_627 = bits(_WIRE_43, 2, 2) connect _WIRE_42.eff, _T_627 node _T_628 = bits(_WIRE_43, 3, 3) connect _WIRE_42.paa, _T_628 node _T_629 = bits(_WIRE_43, 4, 4) connect _WIRE_42.pal, _T_629 node _T_630 = bits(_WIRE_43, 5, 5) connect _WIRE_42.ppp, _T_630 node _T_631 = bits(_WIRE_43, 6, 6) connect _WIRE_42.pr, _T_631 node _T_632 = bits(_WIRE_43, 7, 7) connect _WIRE_42.px, _T_632 node _T_633 = bits(_WIRE_43, 8, 8) connect _WIRE_42.pw, _T_633 node _T_634 = bits(_WIRE_43, 9, 9) connect _WIRE_42.hr, _T_634 node _T_635 = bits(_WIRE_43, 10, 10) connect _WIRE_42.hx, _T_635 node _T_636 = bits(_WIRE_43, 11, 11) connect _WIRE_42.hw, _T_636 node _T_637 = bits(_WIRE_43, 12, 12) connect _WIRE_42.sr, _T_637 node _T_638 = bits(_WIRE_43, 13, 13) connect _WIRE_42.sx, _T_638 node _T_639 = bits(_WIRE_43, 14, 14) connect _WIRE_42.sw, _T_639 node _T_640 = bits(_WIRE_43, 15, 15) connect _WIRE_42.gf, _T_640 node _T_641 = bits(_WIRE_43, 16, 16) connect _WIRE_42.pf, _T_641 node _T_642 = bits(_WIRE_43, 17, 17) connect _WIRE_42.ae_stage2, _T_642 node _T_643 = bits(_WIRE_43, 18, 18) connect _WIRE_42.ae_final, _T_643 node _T_644 = bits(_WIRE_43, 19, 19) connect _WIRE_42.ae_ptw, _T_644 node _T_645 = bits(_WIRE_43, 20, 20) connect _WIRE_42.g, _T_645 node _T_646 = bits(_WIRE_43, 21, 21) connect _WIRE_42.u, _T_646 node _T_647 = bits(_WIRE_43, 41, 22) connect _WIRE_42.ppn, _T_647 node _T_648 = eq(superpage_entries[1].tag_v, _T_624) when _T_648 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_649 = eq(hg_3, UInt<1>(0h0)) node _T_650 = and(_T_649, io.sfence.bits.rs1) when _T_650 : node _tagMatch_T_2 = eq(superpage_entries[2].tag_v, hv_3) node tagMatch_2 = and(superpage_entries[2].valid[0], _tagMatch_T_2) node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node ignore_6 = or(_ignore_T_6, UInt<1>(0h0)) node _T_651 = xor(superpage_entries[2].tag_vpn, vpn) node _T_652 = bits(_T_651, 26, 18) node _T_653 = eq(_T_652, UInt<1>(0h0)) node _T_654 = or(ignore_6, _T_653) node _T_655 = and(tagMatch_2, _T_654) node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ignore_7 = or(_ignore_T_7, UInt<1>(0h0)) node _T_656 = xor(superpage_entries[2].tag_vpn, vpn) node _T_657 = bits(_T_656, 17, 9) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(ignore_7, _T_658) node _T_660 = and(_T_655, _T_659) node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ignore_8 = or(_ignore_T_8, UInt<1>(0h1)) node _T_661 = xor(superpage_entries[2].tag_vpn, vpn) node _T_662 = bits(_T_661, 8, 0) node _T_663 = eq(_T_662, UInt<1>(0h0)) node _T_664 = or(ignore_8, _T_663) node _T_665 = and(_T_660, _T_664) when _T_665 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_666 = xor(superpage_entries[2].tag_vpn, vpn) node _T_667 = shr(_T_666, 18) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_45 : UInt<42> connect _WIRE_45, superpage_entries[2].data[0] node _T_669 = bits(_WIRE_45, 0, 0) connect _WIRE_44.fragmented_superpage, _T_669 node _T_670 = bits(_WIRE_45, 1, 1) connect _WIRE_44.c, _T_670 node _T_671 = bits(_WIRE_45, 2, 2) connect _WIRE_44.eff, _T_671 node _T_672 = bits(_WIRE_45, 3, 3) connect _WIRE_44.paa, _T_672 node _T_673 = bits(_WIRE_45, 4, 4) connect _WIRE_44.pal, _T_673 node _T_674 = bits(_WIRE_45, 5, 5) connect _WIRE_44.ppp, _T_674 node _T_675 = bits(_WIRE_45, 6, 6) connect _WIRE_44.pr, _T_675 node _T_676 = bits(_WIRE_45, 7, 7) connect _WIRE_44.px, _T_676 node _T_677 = bits(_WIRE_45, 8, 8) connect _WIRE_44.pw, _T_677 node _T_678 = bits(_WIRE_45, 9, 9) connect _WIRE_44.hr, _T_678 node _T_679 = bits(_WIRE_45, 10, 10) connect _WIRE_44.hx, _T_679 node _T_680 = bits(_WIRE_45, 11, 11) connect _WIRE_44.hw, _T_680 node _T_681 = bits(_WIRE_45, 12, 12) connect _WIRE_44.sr, _T_681 node _T_682 = bits(_WIRE_45, 13, 13) connect _WIRE_44.sx, _T_682 node _T_683 = bits(_WIRE_45, 14, 14) connect _WIRE_44.sw, _T_683 node _T_684 = bits(_WIRE_45, 15, 15) connect _WIRE_44.gf, _T_684 node _T_685 = bits(_WIRE_45, 16, 16) connect _WIRE_44.pf, _T_685 node _T_686 = bits(_WIRE_45, 17, 17) connect _WIRE_44.ae_stage2, _T_686 node _T_687 = bits(_WIRE_45, 18, 18) connect _WIRE_44.ae_final, _T_687 node _T_688 = bits(_WIRE_45, 19, 19) connect _WIRE_44.ae_ptw, _T_688 node _T_689 = bits(_WIRE_45, 20, 20) connect _WIRE_44.g, _T_689 node _T_690 = bits(_WIRE_45, 21, 21) connect _WIRE_44.u, _T_690 node _T_691 = bits(_WIRE_45, 41, 22) connect _WIRE_44.ppn, _T_691 node _T_692 = eq(superpage_entries[2].tag_v, hv_3) node _T_693 = and(_T_692, _WIRE_44.fragmented_superpage) when _T_693 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_694 = eq(hg_3, UInt<1>(0h0)) node _T_695 = and(_T_694, io.sfence.bits.rs2) when _T_695 : wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_47 : UInt<42> connect _WIRE_47, superpage_entries[2].data[0] node _T_696 = bits(_WIRE_47, 0, 0) connect _WIRE_46.fragmented_superpage, _T_696 node _T_697 = bits(_WIRE_47, 1, 1) connect _WIRE_46.c, _T_697 node _T_698 = bits(_WIRE_47, 2, 2) connect _WIRE_46.eff, _T_698 node _T_699 = bits(_WIRE_47, 3, 3) connect _WIRE_46.paa, _T_699 node _T_700 = bits(_WIRE_47, 4, 4) connect _WIRE_46.pal, _T_700 node _T_701 = bits(_WIRE_47, 5, 5) connect _WIRE_46.ppp, _T_701 node _T_702 = bits(_WIRE_47, 6, 6) connect _WIRE_46.pr, _T_702 node _T_703 = bits(_WIRE_47, 7, 7) connect _WIRE_46.px, _T_703 node _T_704 = bits(_WIRE_47, 8, 8) connect _WIRE_46.pw, _T_704 node _T_705 = bits(_WIRE_47, 9, 9) connect _WIRE_46.hr, _T_705 node _T_706 = bits(_WIRE_47, 10, 10) connect _WIRE_46.hx, _T_706 node _T_707 = bits(_WIRE_47, 11, 11) connect _WIRE_46.hw, _T_707 node _T_708 = bits(_WIRE_47, 12, 12) connect _WIRE_46.sr, _T_708 node _T_709 = bits(_WIRE_47, 13, 13) connect _WIRE_46.sx, _T_709 node _T_710 = bits(_WIRE_47, 14, 14) connect _WIRE_46.sw, _T_710 node _T_711 = bits(_WIRE_47, 15, 15) connect _WIRE_46.gf, _T_711 node _T_712 = bits(_WIRE_47, 16, 16) connect _WIRE_46.pf, _T_712 node _T_713 = bits(_WIRE_47, 17, 17) connect _WIRE_46.ae_stage2, _T_713 node _T_714 = bits(_WIRE_47, 18, 18) connect _WIRE_46.ae_final, _T_714 node _T_715 = bits(_WIRE_47, 19, 19) connect _WIRE_46.ae_ptw, _T_715 node _T_716 = bits(_WIRE_47, 20, 20) connect _WIRE_46.g, _T_716 node _T_717 = bits(_WIRE_47, 21, 21) connect _WIRE_46.u, _T_717 node _T_718 = bits(_WIRE_47, 41, 22) connect _WIRE_46.ppn, _T_718 node _T_719 = eq(superpage_entries[2].tag_v, hv_3) node _T_720 = eq(_WIRE_46.g, UInt<1>(0h0)) node _T_721 = and(_T_719, _T_720) when _T_721 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_722 = or(hv_3, hg_3) wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_49 : UInt<42> connect _WIRE_49, superpage_entries[2].data[0] node _T_723 = bits(_WIRE_49, 0, 0) connect _WIRE_48.fragmented_superpage, _T_723 node _T_724 = bits(_WIRE_49, 1, 1) connect _WIRE_48.c, _T_724 node _T_725 = bits(_WIRE_49, 2, 2) connect _WIRE_48.eff, _T_725 node _T_726 = bits(_WIRE_49, 3, 3) connect _WIRE_48.paa, _T_726 node _T_727 = bits(_WIRE_49, 4, 4) connect _WIRE_48.pal, _T_727 node _T_728 = bits(_WIRE_49, 5, 5) connect _WIRE_48.ppp, _T_728 node _T_729 = bits(_WIRE_49, 6, 6) connect _WIRE_48.pr, _T_729 node _T_730 = bits(_WIRE_49, 7, 7) connect _WIRE_48.px, _T_730 node _T_731 = bits(_WIRE_49, 8, 8) connect _WIRE_48.pw, _T_731 node _T_732 = bits(_WIRE_49, 9, 9) connect _WIRE_48.hr, _T_732 node _T_733 = bits(_WIRE_49, 10, 10) connect _WIRE_48.hx, _T_733 node _T_734 = bits(_WIRE_49, 11, 11) connect _WIRE_48.hw, _T_734 node _T_735 = bits(_WIRE_49, 12, 12) connect _WIRE_48.sr, _T_735 node _T_736 = bits(_WIRE_49, 13, 13) connect _WIRE_48.sx, _T_736 node _T_737 = bits(_WIRE_49, 14, 14) connect _WIRE_48.sw, _T_737 node _T_738 = bits(_WIRE_49, 15, 15) connect _WIRE_48.gf, _T_738 node _T_739 = bits(_WIRE_49, 16, 16) connect _WIRE_48.pf, _T_739 node _T_740 = bits(_WIRE_49, 17, 17) connect _WIRE_48.ae_stage2, _T_740 node _T_741 = bits(_WIRE_49, 18, 18) connect _WIRE_48.ae_final, _T_741 node _T_742 = bits(_WIRE_49, 19, 19) connect _WIRE_48.ae_ptw, _T_742 node _T_743 = bits(_WIRE_49, 20, 20) connect _WIRE_48.g, _T_743 node _T_744 = bits(_WIRE_49, 21, 21) connect _WIRE_48.u, _T_744 node _T_745 = bits(_WIRE_49, 41, 22) connect _WIRE_48.ppn, _T_745 node _T_746 = eq(superpage_entries[2].tag_v, _T_722) when _T_746 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_747 = eq(hg_4, UInt<1>(0h0)) node _T_748 = and(_T_747, io.sfence.bits.rs1) when _T_748 : node _tagMatch_T_3 = eq(superpage_entries[3].tag_v, hv_4) node tagMatch_3 = and(superpage_entries[3].valid[0], _tagMatch_T_3) node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node ignore_9 = or(_ignore_T_9, UInt<1>(0h0)) node _T_749 = xor(superpage_entries[3].tag_vpn, vpn) node _T_750 = bits(_T_749, 26, 18) node _T_751 = eq(_T_750, UInt<1>(0h0)) node _T_752 = or(ignore_9, _T_751) node _T_753 = and(tagMatch_3, _T_752) node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ignore_10 = or(_ignore_T_10, UInt<1>(0h0)) node _T_754 = xor(superpage_entries[3].tag_vpn, vpn) node _T_755 = bits(_T_754, 17, 9) node _T_756 = eq(_T_755, UInt<1>(0h0)) node _T_757 = or(ignore_10, _T_756) node _T_758 = and(_T_753, _T_757) node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ignore_11 = or(_ignore_T_11, UInt<1>(0h1)) node _T_759 = xor(superpage_entries[3].tag_vpn, vpn) node _T_760 = bits(_T_759, 8, 0) node _T_761 = eq(_T_760, UInt<1>(0h0)) node _T_762 = or(ignore_11, _T_761) node _T_763 = and(_T_758, _T_762) when _T_763 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node _T_764 = xor(superpage_entries[3].tag_vpn, vpn) node _T_765 = shr(_T_764, 18) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_51 : UInt<42> connect _WIRE_51, superpage_entries[3].data[0] node _T_767 = bits(_WIRE_51, 0, 0) connect _WIRE_50.fragmented_superpage, _T_767 node _T_768 = bits(_WIRE_51, 1, 1) connect _WIRE_50.c, _T_768 node _T_769 = bits(_WIRE_51, 2, 2) connect _WIRE_50.eff, _T_769 node _T_770 = bits(_WIRE_51, 3, 3) connect _WIRE_50.paa, _T_770 node _T_771 = bits(_WIRE_51, 4, 4) connect _WIRE_50.pal, _T_771 node _T_772 = bits(_WIRE_51, 5, 5) connect _WIRE_50.ppp, _T_772 node _T_773 = bits(_WIRE_51, 6, 6) connect _WIRE_50.pr, _T_773 node _T_774 = bits(_WIRE_51, 7, 7) connect _WIRE_50.px, _T_774 node _T_775 = bits(_WIRE_51, 8, 8) connect _WIRE_50.pw, _T_775 node _T_776 = bits(_WIRE_51, 9, 9) connect _WIRE_50.hr, _T_776 node _T_777 = bits(_WIRE_51, 10, 10) connect _WIRE_50.hx, _T_777 node _T_778 = bits(_WIRE_51, 11, 11) connect _WIRE_50.hw, _T_778 node _T_779 = bits(_WIRE_51, 12, 12) connect _WIRE_50.sr, _T_779 node _T_780 = bits(_WIRE_51, 13, 13) connect _WIRE_50.sx, _T_780 node _T_781 = bits(_WIRE_51, 14, 14) connect _WIRE_50.sw, _T_781 node _T_782 = bits(_WIRE_51, 15, 15) connect _WIRE_50.gf, _T_782 node _T_783 = bits(_WIRE_51, 16, 16) connect _WIRE_50.pf, _T_783 node _T_784 = bits(_WIRE_51, 17, 17) connect _WIRE_50.ae_stage2, _T_784 node _T_785 = bits(_WIRE_51, 18, 18) connect _WIRE_50.ae_final, _T_785 node _T_786 = bits(_WIRE_51, 19, 19) connect _WIRE_50.ae_ptw, _T_786 node _T_787 = bits(_WIRE_51, 20, 20) connect _WIRE_50.g, _T_787 node _T_788 = bits(_WIRE_51, 21, 21) connect _WIRE_50.u, _T_788 node _T_789 = bits(_WIRE_51, 41, 22) connect _WIRE_50.ppn, _T_789 node _T_790 = eq(superpage_entries[3].tag_v, hv_4) node _T_791 = and(_T_790, _WIRE_50.fragmented_superpage) when _T_791 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_792 = eq(hg_4, UInt<1>(0h0)) node _T_793 = and(_T_792, io.sfence.bits.rs2) when _T_793 : wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_53 : UInt<42> connect _WIRE_53, superpage_entries[3].data[0] node _T_794 = bits(_WIRE_53, 0, 0) connect _WIRE_52.fragmented_superpage, _T_794 node _T_795 = bits(_WIRE_53, 1, 1) connect _WIRE_52.c, _T_795 node _T_796 = bits(_WIRE_53, 2, 2) connect _WIRE_52.eff, _T_796 node _T_797 = bits(_WIRE_53, 3, 3) connect _WIRE_52.paa, _T_797 node _T_798 = bits(_WIRE_53, 4, 4) connect _WIRE_52.pal, _T_798 node _T_799 = bits(_WIRE_53, 5, 5) connect _WIRE_52.ppp, _T_799 node _T_800 = bits(_WIRE_53, 6, 6) connect _WIRE_52.pr, _T_800 node _T_801 = bits(_WIRE_53, 7, 7) connect _WIRE_52.px, _T_801 node _T_802 = bits(_WIRE_53, 8, 8) connect _WIRE_52.pw, _T_802 node _T_803 = bits(_WIRE_53, 9, 9) connect _WIRE_52.hr, _T_803 node _T_804 = bits(_WIRE_53, 10, 10) connect _WIRE_52.hx, _T_804 node _T_805 = bits(_WIRE_53, 11, 11) connect _WIRE_52.hw, _T_805 node _T_806 = bits(_WIRE_53, 12, 12) connect _WIRE_52.sr, _T_806 node _T_807 = bits(_WIRE_53, 13, 13) connect _WIRE_52.sx, _T_807 node _T_808 = bits(_WIRE_53, 14, 14) connect _WIRE_52.sw, _T_808 node _T_809 = bits(_WIRE_53, 15, 15) connect _WIRE_52.gf, _T_809 node _T_810 = bits(_WIRE_53, 16, 16) connect _WIRE_52.pf, _T_810 node _T_811 = bits(_WIRE_53, 17, 17) connect _WIRE_52.ae_stage2, _T_811 node _T_812 = bits(_WIRE_53, 18, 18) connect _WIRE_52.ae_final, _T_812 node _T_813 = bits(_WIRE_53, 19, 19) connect _WIRE_52.ae_ptw, _T_813 node _T_814 = bits(_WIRE_53, 20, 20) connect _WIRE_52.g, _T_814 node _T_815 = bits(_WIRE_53, 21, 21) connect _WIRE_52.u, _T_815 node _T_816 = bits(_WIRE_53, 41, 22) connect _WIRE_52.ppn, _T_816 node _T_817 = eq(superpage_entries[3].tag_v, hv_4) node _T_818 = eq(_WIRE_52.g, UInt<1>(0h0)) node _T_819 = and(_T_817, _T_818) when _T_819 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_820 = or(hv_4, hg_4) wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_55 : UInt<42> connect _WIRE_55, superpage_entries[3].data[0] node _T_821 = bits(_WIRE_55, 0, 0) connect _WIRE_54.fragmented_superpage, _T_821 node _T_822 = bits(_WIRE_55, 1, 1) connect _WIRE_54.c, _T_822 node _T_823 = bits(_WIRE_55, 2, 2) connect _WIRE_54.eff, _T_823 node _T_824 = bits(_WIRE_55, 3, 3) connect _WIRE_54.paa, _T_824 node _T_825 = bits(_WIRE_55, 4, 4) connect _WIRE_54.pal, _T_825 node _T_826 = bits(_WIRE_55, 5, 5) connect _WIRE_54.ppp, _T_826 node _T_827 = bits(_WIRE_55, 6, 6) connect _WIRE_54.pr, _T_827 node _T_828 = bits(_WIRE_55, 7, 7) connect _WIRE_54.px, _T_828 node _T_829 = bits(_WIRE_55, 8, 8) connect _WIRE_54.pw, _T_829 node _T_830 = bits(_WIRE_55, 9, 9) connect _WIRE_54.hr, _T_830 node _T_831 = bits(_WIRE_55, 10, 10) connect _WIRE_54.hx, _T_831 node _T_832 = bits(_WIRE_55, 11, 11) connect _WIRE_54.hw, _T_832 node _T_833 = bits(_WIRE_55, 12, 12) connect _WIRE_54.sr, _T_833 node _T_834 = bits(_WIRE_55, 13, 13) connect _WIRE_54.sx, _T_834 node _T_835 = bits(_WIRE_55, 14, 14) connect _WIRE_54.sw, _T_835 node _T_836 = bits(_WIRE_55, 15, 15) connect _WIRE_54.gf, _T_836 node _T_837 = bits(_WIRE_55, 16, 16) connect _WIRE_54.pf, _T_837 node _T_838 = bits(_WIRE_55, 17, 17) connect _WIRE_54.ae_stage2, _T_838 node _T_839 = bits(_WIRE_55, 18, 18) connect _WIRE_54.ae_final, _T_839 node _T_840 = bits(_WIRE_55, 19, 19) connect _WIRE_54.ae_ptw, _T_840 node _T_841 = bits(_WIRE_55, 20, 20) connect _WIRE_54.g, _T_841 node _T_842 = bits(_WIRE_55, 21, 21) connect _WIRE_54.u, _T_842 node _T_843 = bits(_WIRE_55, 41, 22) connect _WIRE_54.ppn, _T_843 node _T_844 = eq(superpage_entries[3].tag_v, _T_820) when _T_844 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_845 = eq(hg_5, UInt<1>(0h0)) node _T_846 = and(_T_845, io.sfence.bits.rs1) when _T_846 : node _tagMatch_T_4 = eq(special_entry.tag_v, hv_5) node tagMatch_4 = and(special_entry.valid[0], _tagMatch_T_4) node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node ignore_12 = or(_ignore_T_12, UInt<1>(0h0)) node _T_847 = xor(special_entry.tag_vpn, vpn) node _T_848 = bits(_T_847, 26, 18) node _T_849 = eq(_T_848, UInt<1>(0h0)) node _T_850 = or(ignore_12, _T_849) node _T_851 = and(tagMatch_4, _T_850) node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node ignore_13 = or(_ignore_T_13, UInt<1>(0h0)) node _T_852 = xor(special_entry.tag_vpn, vpn) node _T_853 = bits(_T_852, 17, 9) node _T_854 = eq(_T_853, UInt<1>(0h0)) node _T_855 = or(ignore_13, _T_854) node _T_856 = and(_T_851, _T_855) node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node ignore_14 = or(_ignore_T_14, UInt<1>(0h0)) node _T_857 = xor(special_entry.tag_vpn, vpn) node _T_858 = bits(_T_857, 8, 0) node _T_859 = eq(_T_858, UInt<1>(0h0)) node _T_860 = or(ignore_14, _T_859) node _T_861 = and(_T_856, _T_860) when _T_861 : connect special_entry.valid[0], UInt<1>(0h0) node _T_862 = xor(special_entry.tag_vpn, vpn) node _T_863 = shr(_T_862, 18) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_57 : UInt<42> connect _WIRE_57, special_entry.data[0] node _T_865 = bits(_WIRE_57, 0, 0) connect _WIRE_56.fragmented_superpage, _T_865 node _T_866 = bits(_WIRE_57, 1, 1) connect _WIRE_56.c, _T_866 node _T_867 = bits(_WIRE_57, 2, 2) connect _WIRE_56.eff, _T_867 node _T_868 = bits(_WIRE_57, 3, 3) connect _WIRE_56.paa, _T_868 node _T_869 = bits(_WIRE_57, 4, 4) connect _WIRE_56.pal, _T_869 node _T_870 = bits(_WIRE_57, 5, 5) connect _WIRE_56.ppp, _T_870 node _T_871 = bits(_WIRE_57, 6, 6) connect _WIRE_56.pr, _T_871 node _T_872 = bits(_WIRE_57, 7, 7) connect _WIRE_56.px, _T_872 node _T_873 = bits(_WIRE_57, 8, 8) connect _WIRE_56.pw, _T_873 node _T_874 = bits(_WIRE_57, 9, 9) connect _WIRE_56.hr, _T_874 node _T_875 = bits(_WIRE_57, 10, 10) connect _WIRE_56.hx, _T_875 node _T_876 = bits(_WIRE_57, 11, 11) connect _WIRE_56.hw, _T_876 node _T_877 = bits(_WIRE_57, 12, 12) connect _WIRE_56.sr, _T_877 node _T_878 = bits(_WIRE_57, 13, 13) connect _WIRE_56.sx, _T_878 node _T_879 = bits(_WIRE_57, 14, 14) connect _WIRE_56.sw, _T_879 node _T_880 = bits(_WIRE_57, 15, 15) connect _WIRE_56.gf, _T_880 node _T_881 = bits(_WIRE_57, 16, 16) connect _WIRE_56.pf, _T_881 node _T_882 = bits(_WIRE_57, 17, 17) connect _WIRE_56.ae_stage2, _T_882 node _T_883 = bits(_WIRE_57, 18, 18) connect _WIRE_56.ae_final, _T_883 node _T_884 = bits(_WIRE_57, 19, 19) connect _WIRE_56.ae_ptw, _T_884 node _T_885 = bits(_WIRE_57, 20, 20) connect _WIRE_56.g, _T_885 node _T_886 = bits(_WIRE_57, 21, 21) connect _WIRE_56.u, _T_886 node _T_887 = bits(_WIRE_57, 41, 22) connect _WIRE_56.ppn, _T_887 node _T_888 = eq(special_entry.tag_v, hv_5) node _T_889 = and(_T_888, _WIRE_56.fragmented_superpage) when _T_889 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_890 = eq(hg_5, UInt<1>(0h0)) node _T_891 = and(_T_890, io.sfence.bits.rs2) when _T_891 : wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_59 : UInt<42> connect _WIRE_59, special_entry.data[0] node _T_892 = bits(_WIRE_59, 0, 0) connect _WIRE_58.fragmented_superpage, _T_892 node _T_893 = bits(_WIRE_59, 1, 1) connect _WIRE_58.c, _T_893 node _T_894 = bits(_WIRE_59, 2, 2) connect _WIRE_58.eff, _T_894 node _T_895 = bits(_WIRE_59, 3, 3) connect _WIRE_58.paa, _T_895 node _T_896 = bits(_WIRE_59, 4, 4) connect _WIRE_58.pal, _T_896 node _T_897 = bits(_WIRE_59, 5, 5) connect _WIRE_58.ppp, _T_897 node _T_898 = bits(_WIRE_59, 6, 6) connect _WIRE_58.pr, _T_898 node _T_899 = bits(_WIRE_59, 7, 7) connect _WIRE_58.px, _T_899 node _T_900 = bits(_WIRE_59, 8, 8) connect _WIRE_58.pw, _T_900 node _T_901 = bits(_WIRE_59, 9, 9) connect _WIRE_58.hr, _T_901 node _T_902 = bits(_WIRE_59, 10, 10) connect _WIRE_58.hx, _T_902 node _T_903 = bits(_WIRE_59, 11, 11) connect _WIRE_58.hw, _T_903 node _T_904 = bits(_WIRE_59, 12, 12) connect _WIRE_58.sr, _T_904 node _T_905 = bits(_WIRE_59, 13, 13) connect _WIRE_58.sx, _T_905 node _T_906 = bits(_WIRE_59, 14, 14) connect _WIRE_58.sw, _T_906 node _T_907 = bits(_WIRE_59, 15, 15) connect _WIRE_58.gf, _T_907 node _T_908 = bits(_WIRE_59, 16, 16) connect _WIRE_58.pf, _T_908 node _T_909 = bits(_WIRE_59, 17, 17) connect _WIRE_58.ae_stage2, _T_909 node _T_910 = bits(_WIRE_59, 18, 18) connect _WIRE_58.ae_final, _T_910 node _T_911 = bits(_WIRE_59, 19, 19) connect _WIRE_58.ae_ptw, _T_911 node _T_912 = bits(_WIRE_59, 20, 20) connect _WIRE_58.g, _T_912 node _T_913 = bits(_WIRE_59, 21, 21) connect _WIRE_58.u, _T_913 node _T_914 = bits(_WIRE_59, 41, 22) connect _WIRE_58.ppn, _T_914 node _T_915 = eq(special_entry.tag_v, hv_5) node _T_916 = eq(_WIRE_58.g, UInt<1>(0h0)) node _T_917 = and(_T_915, _T_916) when _T_917 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_918 = or(hv_5, hg_5) wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_61 : UInt<42> connect _WIRE_61, special_entry.data[0] node _T_919 = bits(_WIRE_61, 0, 0) connect _WIRE_60.fragmented_superpage, _T_919 node _T_920 = bits(_WIRE_61, 1, 1) connect _WIRE_60.c, _T_920 node _T_921 = bits(_WIRE_61, 2, 2) connect _WIRE_60.eff, _T_921 node _T_922 = bits(_WIRE_61, 3, 3) connect _WIRE_60.paa, _T_922 node _T_923 = bits(_WIRE_61, 4, 4) connect _WIRE_60.pal, _T_923 node _T_924 = bits(_WIRE_61, 5, 5) connect _WIRE_60.ppp, _T_924 node _T_925 = bits(_WIRE_61, 6, 6) connect _WIRE_60.pr, _T_925 node _T_926 = bits(_WIRE_61, 7, 7) connect _WIRE_60.px, _T_926 node _T_927 = bits(_WIRE_61, 8, 8) connect _WIRE_60.pw, _T_927 node _T_928 = bits(_WIRE_61, 9, 9) connect _WIRE_60.hr, _T_928 node _T_929 = bits(_WIRE_61, 10, 10) connect _WIRE_60.hx, _T_929 node _T_930 = bits(_WIRE_61, 11, 11) connect _WIRE_60.hw, _T_930 node _T_931 = bits(_WIRE_61, 12, 12) connect _WIRE_60.sr, _T_931 node _T_932 = bits(_WIRE_61, 13, 13) connect _WIRE_60.sx, _T_932 node _T_933 = bits(_WIRE_61, 14, 14) connect _WIRE_60.sw, _T_933 node _T_934 = bits(_WIRE_61, 15, 15) connect _WIRE_60.gf, _T_934 node _T_935 = bits(_WIRE_61, 16, 16) connect _WIRE_60.pf, _T_935 node _T_936 = bits(_WIRE_61, 17, 17) connect _WIRE_60.ae_stage2, _T_936 node _T_937 = bits(_WIRE_61, 18, 18) connect _WIRE_60.ae_final, _T_937 node _T_938 = bits(_WIRE_61, 19, 19) connect _WIRE_60.ae_ptw, _T_938 node _T_939 = bits(_WIRE_61, 20, 20) connect _WIRE_60.g, _T_939 node _T_940 = bits(_WIRE_61, 21, 21) connect _WIRE_60.u, _T_940 node _T_941 = bits(_WIRE_61, 41, 22) connect _WIRE_60.ppn, _T_941 node _T_942 = eq(special_entry.tag_v, _T_918) when _T_942 : connect special_entry.valid[0], UInt<1>(0h0) node _T_943 = and(io.req.ready, io.req.valid) node _T_944 = and(_T_943, vsatp_mode_mismatch) when _T_944 : wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_63 : UInt<42> connect _WIRE_63, sectored_entries[0][0].data[0] node _T_945 = bits(_WIRE_63, 0, 0) connect _WIRE_62.fragmented_superpage, _T_945 node _T_946 = bits(_WIRE_63, 1, 1) connect _WIRE_62.c, _T_946 node _T_947 = bits(_WIRE_63, 2, 2) connect _WIRE_62.eff, _T_947 node _T_948 = bits(_WIRE_63, 3, 3) connect _WIRE_62.paa, _T_948 node _T_949 = bits(_WIRE_63, 4, 4) connect _WIRE_62.pal, _T_949 node _T_950 = bits(_WIRE_63, 5, 5) connect _WIRE_62.ppp, _T_950 node _T_951 = bits(_WIRE_63, 6, 6) connect _WIRE_62.pr, _T_951 node _T_952 = bits(_WIRE_63, 7, 7) connect _WIRE_62.px, _T_952 node _T_953 = bits(_WIRE_63, 8, 8) connect _WIRE_62.pw, _T_953 node _T_954 = bits(_WIRE_63, 9, 9) connect _WIRE_62.hr, _T_954 node _T_955 = bits(_WIRE_63, 10, 10) connect _WIRE_62.hx, _T_955 node _T_956 = bits(_WIRE_63, 11, 11) connect _WIRE_62.hw, _T_956 node _T_957 = bits(_WIRE_63, 12, 12) connect _WIRE_62.sr, _T_957 node _T_958 = bits(_WIRE_63, 13, 13) connect _WIRE_62.sx, _T_958 node _T_959 = bits(_WIRE_63, 14, 14) connect _WIRE_62.sw, _T_959 node _T_960 = bits(_WIRE_63, 15, 15) connect _WIRE_62.gf, _T_960 node _T_961 = bits(_WIRE_63, 16, 16) connect _WIRE_62.pf, _T_961 node _T_962 = bits(_WIRE_63, 17, 17) connect _WIRE_62.ae_stage2, _T_962 node _T_963 = bits(_WIRE_63, 18, 18) connect _WIRE_62.ae_final, _T_963 node _T_964 = bits(_WIRE_63, 19, 19) connect _WIRE_62.ae_ptw, _T_964 node _T_965 = bits(_WIRE_63, 20, 20) connect _WIRE_62.g, _T_965 node _T_966 = bits(_WIRE_63, 21, 21) connect _WIRE_62.u, _T_966 node _T_967 = bits(_WIRE_63, 41, 22) connect _WIRE_62.ppn, _T_967 wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_65 : UInt<42> connect _WIRE_65, sectored_entries[0][0].data[1] node _T_968 = bits(_WIRE_65, 0, 0) connect _WIRE_64.fragmented_superpage, _T_968 node _T_969 = bits(_WIRE_65, 1, 1) connect _WIRE_64.c, _T_969 node _T_970 = bits(_WIRE_65, 2, 2) connect _WIRE_64.eff, _T_970 node _T_971 = bits(_WIRE_65, 3, 3) connect _WIRE_64.paa, _T_971 node _T_972 = bits(_WIRE_65, 4, 4) connect _WIRE_64.pal, _T_972 node _T_973 = bits(_WIRE_65, 5, 5) connect _WIRE_64.ppp, _T_973 node _T_974 = bits(_WIRE_65, 6, 6) connect _WIRE_64.pr, _T_974 node _T_975 = bits(_WIRE_65, 7, 7) connect _WIRE_64.px, _T_975 node _T_976 = bits(_WIRE_65, 8, 8) connect _WIRE_64.pw, _T_976 node _T_977 = bits(_WIRE_65, 9, 9) connect _WIRE_64.hr, _T_977 node _T_978 = bits(_WIRE_65, 10, 10) connect _WIRE_64.hx, _T_978 node _T_979 = bits(_WIRE_65, 11, 11) connect _WIRE_64.hw, _T_979 node _T_980 = bits(_WIRE_65, 12, 12) connect _WIRE_64.sr, _T_980 node _T_981 = bits(_WIRE_65, 13, 13) connect _WIRE_64.sx, _T_981 node _T_982 = bits(_WIRE_65, 14, 14) connect _WIRE_64.sw, _T_982 node _T_983 = bits(_WIRE_65, 15, 15) connect _WIRE_64.gf, _T_983 node _T_984 = bits(_WIRE_65, 16, 16) connect _WIRE_64.pf, _T_984 node _T_985 = bits(_WIRE_65, 17, 17) connect _WIRE_64.ae_stage2, _T_985 node _T_986 = bits(_WIRE_65, 18, 18) connect _WIRE_64.ae_final, _T_986 node _T_987 = bits(_WIRE_65, 19, 19) connect _WIRE_64.ae_ptw, _T_987 node _T_988 = bits(_WIRE_65, 20, 20) connect _WIRE_64.g, _T_988 node _T_989 = bits(_WIRE_65, 21, 21) connect _WIRE_64.u, _T_989 node _T_990 = bits(_WIRE_65, 41, 22) connect _WIRE_64.ppn, _T_990 wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_67 : UInt<42> connect _WIRE_67, sectored_entries[0][0].data[2] node _T_991 = bits(_WIRE_67, 0, 0) connect _WIRE_66.fragmented_superpage, _T_991 node _T_992 = bits(_WIRE_67, 1, 1) connect _WIRE_66.c, _T_992 node _T_993 = bits(_WIRE_67, 2, 2) connect _WIRE_66.eff, _T_993 node _T_994 = bits(_WIRE_67, 3, 3) connect _WIRE_66.paa, _T_994 node _T_995 = bits(_WIRE_67, 4, 4) connect _WIRE_66.pal, _T_995 node _T_996 = bits(_WIRE_67, 5, 5) connect _WIRE_66.ppp, _T_996 node _T_997 = bits(_WIRE_67, 6, 6) connect _WIRE_66.pr, _T_997 node _T_998 = bits(_WIRE_67, 7, 7) connect _WIRE_66.px, _T_998 node _T_999 = bits(_WIRE_67, 8, 8) connect _WIRE_66.pw, _T_999 node _T_1000 = bits(_WIRE_67, 9, 9) connect _WIRE_66.hr, _T_1000 node _T_1001 = bits(_WIRE_67, 10, 10) connect _WIRE_66.hx, _T_1001 node _T_1002 = bits(_WIRE_67, 11, 11) connect _WIRE_66.hw, _T_1002 node _T_1003 = bits(_WIRE_67, 12, 12) connect _WIRE_66.sr, _T_1003 node _T_1004 = bits(_WIRE_67, 13, 13) connect _WIRE_66.sx, _T_1004 node _T_1005 = bits(_WIRE_67, 14, 14) connect _WIRE_66.sw, _T_1005 node _T_1006 = bits(_WIRE_67, 15, 15) connect _WIRE_66.gf, _T_1006 node _T_1007 = bits(_WIRE_67, 16, 16) connect _WIRE_66.pf, _T_1007 node _T_1008 = bits(_WIRE_67, 17, 17) connect _WIRE_66.ae_stage2, _T_1008 node _T_1009 = bits(_WIRE_67, 18, 18) connect _WIRE_66.ae_final, _T_1009 node _T_1010 = bits(_WIRE_67, 19, 19) connect _WIRE_66.ae_ptw, _T_1010 node _T_1011 = bits(_WIRE_67, 20, 20) connect _WIRE_66.g, _T_1011 node _T_1012 = bits(_WIRE_67, 21, 21) connect _WIRE_66.u, _T_1012 node _T_1013 = bits(_WIRE_67, 41, 22) connect _WIRE_66.ppn, _T_1013 wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_69 : UInt<42> connect _WIRE_69, sectored_entries[0][0].data[3] node _T_1014 = bits(_WIRE_69, 0, 0) connect _WIRE_68.fragmented_superpage, _T_1014 node _T_1015 = bits(_WIRE_69, 1, 1) connect _WIRE_68.c, _T_1015 node _T_1016 = bits(_WIRE_69, 2, 2) connect _WIRE_68.eff, _T_1016 node _T_1017 = bits(_WIRE_69, 3, 3) connect _WIRE_68.paa, _T_1017 node _T_1018 = bits(_WIRE_69, 4, 4) connect _WIRE_68.pal, _T_1018 node _T_1019 = bits(_WIRE_69, 5, 5) connect _WIRE_68.ppp, _T_1019 node _T_1020 = bits(_WIRE_69, 6, 6) connect _WIRE_68.pr, _T_1020 node _T_1021 = bits(_WIRE_69, 7, 7) connect _WIRE_68.px, _T_1021 node _T_1022 = bits(_WIRE_69, 8, 8) connect _WIRE_68.pw, _T_1022 node _T_1023 = bits(_WIRE_69, 9, 9) connect _WIRE_68.hr, _T_1023 node _T_1024 = bits(_WIRE_69, 10, 10) connect _WIRE_68.hx, _T_1024 node _T_1025 = bits(_WIRE_69, 11, 11) connect _WIRE_68.hw, _T_1025 node _T_1026 = bits(_WIRE_69, 12, 12) connect _WIRE_68.sr, _T_1026 node _T_1027 = bits(_WIRE_69, 13, 13) connect _WIRE_68.sx, _T_1027 node _T_1028 = bits(_WIRE_69, 14, 14) connect _WIRE_68.sw, _T_1028 node _T_1029 = bits(_WIRE_69, 15, 15) connect _WIRE_68.gf, _T_1029 node _T_1030 = bits(_WIRE_69, 16, 16) connect _WIRE_68.pf, _T_1030 node _T_1031 = bits(_WIRE_69, 17, 17) connect _WIRE_68.ae_stage2, _T_1031 node _T_1032 = bits(_WIRE_69, 18, 18) connect _WIRE_68.ae_final, _T_1032 node _T_1033 = bits(_WIRE_69, 19, 19) connect _WIRE_68.ae_ptw, _T_1033 node _T_1034 = bits(_WIRE_69, 20, 20) connect _WIRE_68.g, _T_1034 node _T_1035 = bits(_WIRE_69, 21, 21) connect _WIRE_68.u, _T_1035 node _T_1036 = bits(_WIRE_69, 41, 22) connect _WIRE_68.ppn, _T_1036 node _T_1037 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_1037 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_1038 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_1038 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_1039 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_1039 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_1040 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_1040 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_71 : UInt<42> connect _WIRE_71, superpage_entries[0].data[0] node _T_1041 = bits(_WIRE_71, 0, 0) connect _WIRE_70.fragmented_superpage, _T_1041 node _T_1042 = bits(_WIRE_71, 1, 1) connect _WIRE_70.c, _T_1042 node _T_1043 = bits(_WIRE_71, 2, 2) connect _WIRE_70.eff, _T_1043 node _T_1044 = bits(_WIRE_71, 3, 3) connect _WIRE_70.paa, _T_1044 node _T_1045 = bits(_WIRE_71, 4, 4) connect _WIRE_70.pal, _T_1045 node _T_1046 = bits(_WIRE_71, 5, 5) connect _WIRE_70.ppp, _T_1046 node _T_1047 = bits(_WIRE_71, 6, 6) connect _WIRE_70.pr, _T_1047 node _T_1048 = bits(_WIRE_71, 7, 7) connect _WIRE_70.px, _T_1048 node _T_1049 = bits(_WIRE_71, 8, 8) connect _WIRE_70.pw, _T_1049 node _T_1050 = bits(_WIRE_71, 9, 9) connect _WIRE_70.hr, _T_1050 node _T_1051 = bits(_WIRE_71, 10, 10) connect _WIRE_70.hx, _T_1051 node _T_1052 = bits(_WIRE_71, 11, 11) connect _WIRE_70.hw, _T_1052 node _T_1053 = bits(_WIRE_71, 12, 12) connect _WIRE_70.sr, _T_1053 node _T_1054 = bits(_WIRE_71, 13, 13) connect _WIRE_70.sx, _T_1054 node _T_1055 = bits(_WIRE_71, 14, 14) connect _WIRE_70.sw, _T_1055 node _T_1056 = bits(_WIRE_71, 15, 15) connect _WIRE_70.gf, _T_1056 node _T_1057 = bits(_WIRE_71, 16, 16) connect _WIRE_70.pf, _T_1057 node _T_1058 = bits(_WIRE_71, 17, 17) connect _WIRE_70.ae_stage2, _T_1058 node _T_1059 = bits(_WIRE_71, 18, 18) connect _WIRE_70.ae_final, _T_1059 node _T_1060 = bits(_WIRE_71, 19, 19) connect _WIRE_70.ae_ptw, _T_1060 node _T_1061 = bits(_WIRE_71, 20, 20) connect _WIRE_70.g, _T_1061 node _T_1062 = bits(_WIRE_71, 21, 21) connect _WIRE_70.u, _T_1062 node _T_1063 = bits(_WIRE_71, 41, 22) connect _WIRE_70.ppn, _T_1063 node _T_1064 = eq(superpage_entries[0].tag_v, UInt<1>(0h1)) when _T_1064 : connect superpage_entries[0].valid[0], UInt<1>(0h0) wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_73 : UInt<42> connect _WIRE_73, superpage_entries[1].data[0] node _T_1065 = bits(_WIRE_73, 0, 0) connect _WIRE_72.fragmented_superpage, _T_1065 node _T_1066 = bits(_WIRE_73, 1, 1) connect _WIRE_72.c, _T_1066 node _T_1067 = bits(_WIRE_73, 2, 2) connect _WIRE_72.eff, _T_1067 node _T_1068 = bits(_WIRE_73, 3, 3) connect _WIRE_72.paa, _T_1068 node _T_1069 = bits(_WIRE_73, 4, 4) connect _WIRE_72.pal, _T_1069 node _T_1070 = bits(_WIRE_73, 5, 5) connect _WIRE_72.ppp, _T_1070 node _T_1071 = bits(_WIRE_73, 6, 6) connect _WIRE_72.pr, _T_1071 node _T_1072 = bits(_WIRE_73, 7, 7) connect _WIRE_72.px, _T_1072 node _T_1073 = bits(_WIRE_73, 8, 8) connect _WIRE_72.pw, _T_1073 node _T_1074 = bits(_WIRE_73, 9, 9) connect _WIRE_72.hr, _T_1074 node _T_1075 = bits(_WIRE_73, 10, 10) connect _WIRE_72.hx, _T_1075 node _T_1076 = bits(_WIRE_73, 11, 11) connect _WIRE_72.hw, _T_1076 node _T_1077 = bits(_WIRE_73, 12, 12) connect _WIRE_72.sr, _T_1077 node _T_1078 = bits(_WIRE_73, 13, 13) connect _WIRE_72.sx, _T_1078 node _T_1079 = bits(_WIRE_73, 14, 14) connect _WIRE_72.sw, _T_1079 node _T_1080 = bits(_WIRE_73, 15, 15) connect _WIRE_72.gf, _T_1080 node _T_1081 = bits(_WIRE_73, 16, 16) connect _WIRE_72.pf, _T_1081 node _T_1082 = bits(_WIRE_73, 17, 17) connect _WIRE_72.ae_stage2, _T_1082 node _T_1083 = bits(_WIRE_73, 18, 18) connect _WIRE_72.ae_final, _T_1083 node _T_1084 = bits(_WIRE_73, 19, 19) connect _WIRE_72.ae_ptw, _T_1084 node _T_1085 = bits(_WIRE_73, 20, 20) connect _WIRE_72.g, _T_1085 node _T_1086 = bits(_WIRE_73, 21, 21) connect _WIRE_72.u, _T_1086 node _T_1087 = bits(_WIRE_73, 41, 22) connect _WIRE_72.ppn, _T_1087 node _T_1088 = eq(superpage_entries[1].tag_v, UInt<1>(0h1)) when _T_1088 : connect superpage_entries[1].valid[0], UInt<1>(0h0) wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_75 : UInt<42> connect _WIRE_75, superpage_entries[2].data[0] node _T_1089 = bits(_WIRE_75, 0, 0) connect _WIRE_74.fragmented_superpage, _T_1089 node _T_1090 = bits(_WIRE_75, 1, 1) connect _WIRE_74.c, _T_1090 node _T_1091 = bits(_WIRE_75, 2, 2) connect _WIRE_74.eff, _T_1091 node _T_1092 = bits(_WIRE_75, 3, 3) connect _WIRE_74.paa, _T_1092 node _T_1093 = bits(_WIRE_75, 4, 4) connect _WIRE_74.pal, _T_1093 node _T_1094 = bits(_WIRE_75, 5, 5) connect _WIRE_74.ppp, _T_1094 node _T_1095 = bits(_WIRE_75, 6, 6) connect _WIRE_74.pr, _T_1095 node _T_1096 = bits(_WIRE_75, 7, 7) connect _WIRE_74.px, _T_1096 node _T_1097 = bits(_WIRE_75, 8, 8) connect _WIRE_74.pw, _T_1097 node _T_1098 = bits(_WIRE_75, 9, 9) connect _WIRE_74.hr, _T_1098 node _T_1099 = bits(_WIRE_75, 10, 10) connect _WIRE_74.hx, _T_1099 node _T_1100 = bits(_WIRE_75, 11, 11) connect _WIRE_74.hw, _T_1100 node _T_1101 = bits(_WIRE_75, 12, 12) connect _WIRE_74.sr, _T_1101 node _T_1102 = bits(_WIRE_75, 13, 13) connect _WIRE_74.sx, _T_1102 node _T_1103 = bits(_WIRE_75, 14, 14) connect _WIRE_74.sw, _T_1103 node _T_1104 = bits(_WIRE_75, 15, 15) connect _WIRE_74.gf, _T_1104 node _T_1105 = bits(_WIRE_75, 16, 16) connect _WIRE_74.pf, _T_1105 node _T_1106 = bits(_WIRE_75, 17, 17) connect _WIRE_74.ae_stage2, _T_1106 node _T_1107 = bits(_WIRE_75, 18, 18) connect _WIRE_74.ae_final, _T_1107 node _T_1108 = bits(_WIRE_75, 19, 19) connect _WIRE_74.ae_ptw, _T_1108 node _T_1109 = bits(_WIRE_75, 20, 20) connect _WIRE_74.g, _T_1109 node _T_1110 = bits(_WIRE_75, 21, 21) connect _WIRE_74.u, _T_1110 node _T_1111 = bits(_WIRE_75, 41, 22) connect _WIRE_74.ppn, _T_1111 node _T_1112 = eq(superpage_entries[2].tag_v, UInt<1>(0h1)) when _T_1112 : connect superpage_entries[2].valid[0], UInt<1>(0h0) wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_77 : UInt<42> connect _WIRE_77, superpage_entries[3].data[0] node _T_1113 = bits(_WIRE_77, 0, 0) connect _WIRE_76.fragmented_superpage, _T_1113 node _T_1114 = bits(_WIRE_77, 1, 1) connect _WIRE_76.c, _T_1114 node _T_1115 = bits(_WIRE_77, 2, 2) connect _WIRE_76.eff, _T_1115 node _T_1116 = bits(_WIRE_77, 3, 3) connect _WIRE_76.paa, _T_1116 node _T_1117 = bits(_WIRE_77, 4, 4) connect _WIRE_76.pal, _T_1117 node _T_1118 = bits(_WIRE_77, 5, 5) connect _WIRE_76.ppp, _T_1118 node _T_1119 = bits(_WIRE_77, 6, 6) connect _WIRE_76.pr, _T_1119 node _T_1120 = bits(_WIRE_77, 7, 7) connect _WIRE_76.px, _T_1120 node _T_1121 = bits(_WIRE_77, 8, 8) connect _WIRE_76.pw, _T_1121 node _T_1122 = bits(_WIRE_77, 9, 9) connect _WIRE_76.hr, _T_1122 node _T_1123 = bits(_WIRE_77, 10, 10) connect _WIRE_76.hx, _T_1123 node _T_1124 = bits(_WIRE_77, 11, 11) connect _WIRE_76.hw, _T_1124 node _T_1125 = bits(_WIRE_77, 12, 12) connect _WIRE_76.sr, _T_1125 node _T_1126 = bits(_WIRE_77, 13, 13) connect _WIRE_76.sx, _T_1126 node _T_1127 = bits(_WIRE_77, 14, 14) connect _WIRE_76.sw, _T_1127 node _T_1128 = bits(_WIRE_77, 15, 15) connect _WIRE_76.gf, _T_1128 node _T_1129 = bits(_WIRE_77, 16, 16) connect _WIRE_76.pf, _T_1129 node _T_1130 = bits(_WIRE_77, 17, 17) connect _WIRE_76.ae_stage2, _T_1130 node _T_1131 = bits(_WIRE_77, 18, 18) connect _WIRE_76.ae_final, _T_1131 node _T_1132 = bits(_WIRE_77, 19, 19) connect _WIRE_76.ae_ptw, _T_1132 node _T_1133 = bits(_WIRE_77, 20, 20) connect _WIRE_76.g, _T_1133 node _T_1134 = bits(_WIRE_77, 21, 21) connect _WIRE_76.u, _T_1134 node _T_1135 = bits(_WIRE_77, 41, 22) connect _WIRE_76.ppn, _T_1135 node _T_1136 = eq(superpage_entries[3].tag_v, UInt<1>(0h1)) when _T_1136 : connect superpage_entries[3].valid[0], UInt<1>(0h0) wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_79 : UInt<42> connect _WIRE_79, special_entry.data[0] node _T_1137 = bits(_WIRE_79, 0, 0) connect _WIRE_78.fragmented_superpage, _T_1137 node _T_1138 = bits(_WIRE_79, 1, 1) connect _WIRE_78.c, _T_1138 node _T_1139 = bits(_WIRE_79, 2, 2) connect _WIRE_78.eff, _T_1139 node _T_1140 = bits(_WIRE_79, 3, 3) connect _WIRE_78.paa, _T_1140 node _T_1141 = bits(_WIRE_79, 4, 4) connect _WIRE_78.pal, _T_1141 node _T_1142 = bits(_WIRE_79, 5, 5) connect _WIRE_78.ppp, _T_1142 node _T_1143 = bits(_WIRE_79, 6, 6) connect _WIRE_78.pr, _T_1143 node _T_1144 = bits(_WIRE_79, 7, 7) connect _WIRE_78.px, _T_1144 node _T_1145 = bits(_WIRE_79, 8, 8) connect _WIRE_78.pw, _T_1145 node _T_1146 = bits(_WIRE_79, 9, 9) connect _WIRE_78.hr, _T_1146 node _T_1147 = bits(_WIRE_79, 10, 10) connect _WIRE_78.hx, _T_1147 node _T_1148 = bits(_WIRE_79, 11, 11) connect _WIRE_78.hw, _T_1148 node _T_1149 = bits(_WIRE_79, 12, 12) connect _WIRE_78.sr, _T_1149 node _T_1150 = bits(_WIRE_79, 13, 13) connect _WIRE_78.sx, _T_1150 node _T_1151 = bits(_WIRE_79, 14, 14) connect _WIRE_78.sw, _T_1151 node _T_1152 = bits(_WIRE_79, 15, 15) connect _WIRE_78.gf, _T_1152 node _T_1153 = bits(_WIRE_79, 16, 16) connect _WIRE_78.pf, _T_1153 node _T_1154 = bits(_WIRE_79, 17, 17) connect _WIRE_78.ae_stage2, _T_1154 node _T_1155 = bits(_WIRE_79, 18, 18) connect _WIRE_78.ae_final, _T_1155 node _T_1156 = bits(_WIRE_79, 19, 19) connect _WIRE_78.ae_ptw, _T_1156 node _T_1157 = bits(_WIRE_79, 20, 20) connect _WIRE_78.g, _T_1157 node _T_1158 = bits(_WIRE_79, 21, 21) connect _WIRE_78.u, _T_1158 node _T_1159 = bits(_WIRE_79, 41, 22) connect _WIRE_78.ppn, _T_1159 node _T_1160 = eq(special_entry.tag_v, UInt<1>(0h1)) when _T_1160 : connect special_entry.valid[0], UInt<1>(0h0) connect v_entries_use_stage1, vstage1_en node _T_1161 = asUInt(reset) node _T_1162 = or(multipleHits, _T_1161) when _T_1162 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect superpage_entries[1].valid[0], UInt<1>(0h0) connect superpage_entries[2].valid[0], UInt<1>(0h0) connect superpage_entries[3].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0) node _T_1163 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_1164 = eq(io.ptw.req.ready, UInt<1>(0h0)) node _T_1165 = and(io.ptw.req.valid, _T_1164) node _T_1166 = eq(state, UInt<2>(0h3)) node _T_1167 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_1168 = and(io.sfence.valid, _T_1167) node _T_1169 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_1170 = and(_T_1168, _T_1169) node _T_1171 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_1172 = and(io.sfence.valid, _T_1171) node _T_1173 = and(_T_1172, io.sfence.bits.rs2) node _T_1174 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_1175 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_1176 = and(_T_1174, _T_1175) node _T_1177 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_1178 = and(_T_1177, io.sfence.bits.rs2)	module DTLB_2( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] output [39:0] io_resp_gpa, // @[TLB.scala:320:14] output io_resp_pf_ld, // @[TLB.scala:320:14] output io_resp_pf_st, // @[TLB.scala:320:14] output io_resp_pf_inst, // @[TLB.scala:320:14] output io_resp_ae_ld, // @[TLB.scala:320:14] output io_resp_ae_st, // @[TLB.scala:320:14] output io_resp_ae_inst, // @[TLB.scala:320:14] output io_resp_cacheable, // @[TLB.scala:320:14] output io_resp_must_alloc, // @[TLB.scala:320:14] output io_resp_prefetchable, // @[TLB.scala:320:14] output [4:0] io_resp_cmd, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_status_zero2, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_mbe, // @[TLB.scala:320:14] input io_ptw_status_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_status_sxl, // @[TLB.scala:320:14] input [1:0] io_ptw_status_uxl, // @[TLB.scala:320:14] input io_ptw_status_sd_rv32, // @[TLB.scala:320:14] input [7:0] io_ptw_status_zero1, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_xs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_status_vs, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_ube, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_upie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_hie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_status_uie, // @[TLB.scala:320:14] input io_ptw_hstatus_spvp, // @[TLB.scala:320:14] input io_ptw_hstatus_spv, // @[TLB.scala:320:14] input io_ptw_hstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_debug, // @[TLB.scala:320:14] input io_ptw_gstatus_cease, // @[TLB.scala:320:14] input io_ptw_gstatus_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14] input io_ptw_gstatus_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14] input io_ptw_gstatus_v, // @[TLB.scala:320:14] input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14] input io_ptw_gstatus_mpv, // @[TLB.scala:320:14] input io_ptw_gstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_mbe, // @[TLB.scala:320:14] input io_ptw_gstatus_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14] input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14] input io_ptw_gstatus_tsr, // @[TLB.scala:320:14] input io_ptw_gstatus_tw, // @[TLB.scala:320:14] input io_ptw_gstatus_tvm, // @[TLB.scala:320:14] input io_ptw_gstatus_mxr, // @[TLB.scala:320:14] input io_ptw_gstatus_sum, // @[TLB.scala:320:14] input io_ptw_gstatus_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14] input io_ptw_gstatus_spp, // @[TLB.scala:320:14] input io_ptw_gstatus_mpie, // @[TLB.scala:320:14] input io_ptw_gstatus_ube, // @[TLB.scala:320:14] input io_ptw_gstatus_spie, // @[TLB.scala:320:14] input io_ptw_gstatus_upie, // @[TLB.scala:320:14] input io_ptw_gstatus_mie, // @[TLB.scala:320:14] input io_ptw_gstatus_hie, // @[TLB.scala:320:14] input io_ptw_gstatus_sie, // @[TLB.scala:320:14] input io_ptw_gstatus_uie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[TLB.scala:318:7] wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7] wire [6:0] hr_array = 7'h7F; // @[TLB.scala:524:21] wire [6:0] hw_array = 7'h7F; // @[TLB.scala:525:21] wire [6:0] hx_array = 7'h7F; // @[TLB.scala:526:21] wire [6:0] _must_alloc_array_T_8 = 7'h7F; // @[TLB.scala:596:19] wire [6:0] _gf_ld_array_T_1 = 7'h7F; // @[TLB.scala:600:50] wire [5:0] stage2_bypass = 6'h3F; // @[TLB.scala:523:27] wire [5:0] _hr_array_T_4 = 6'h3F; // @[TLB.scala:524:111] wire [5:0] _hw_array_T_1 = 6'h3F; // @[TLB.scala:525:55] wire [5:0] _hx_array_T_1 = 6'h3F; // @[TLB.scala:526:55] wire [5:0] _gpa_hits_hit_mask_T_4 = 6'h3F; // @[TLB.scala:606:88] wire [5:0] gpa_hits_hit_mask = 6'h3F; // @[TLB.scala:606:82] wire [5:0] _gpa_hits_T_1 = 6'h3F; // @[TLB.scala:607:16] wire [5:0] gpa_hits = 6'h3F; // @[TLB.scala:607:14] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr = 39'h0; // @[TLB.scala:318:7, :320:14] wire [7:0] _misaligned_T = 8'h1; // @[OneHot.scala:58:35] wire [7:0] _misaligned_T_2 = 8'h0; // @[TLB.scala:550:69] wire [39:0] _misaligned_T_3 = 40'h0; // @[TLB.scala:550:39] wire [6:0] _ae_array_T = 7'h0; // @[TLB.scala:582:8] wire [6:0] _gf_ld_array_T_2 = 7'h0; // @[TLB.scala:600:46] wire [6:0] gf_ld_array = 7'h0; // @[TLB.scala:600:24] wire [6:0] _gf_st_array_T_1 = 7'h0; // @[TLB.scala:601:53] wire [6:0] gf_st_array = 7'h0; // @[TLB.scala:601:24] wire [6:0] _gf_inst_array_T = 7'h0; // @[TLB.scala:602:36] wire [6:0] gf_inst_array = 7'h0; // @[TLB.scala:602:26] wire [6:0] gpa_hits_need_gpa_mask = 7'h0; // @[TLB.scala:605:73] wire [6:0] _io_resp_gf_ld_T_1 = 7'h0; // @[TLB.scala:637:58] wire [6:0] _io_resp_gf_st_T_1 = 7'h0; // @[TLB.scala:638:65] wire [6:0] _io_resp_gf_inst_T = 7'h0; // @[TLB.scala:639:48] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h1; // @[TLB.scala:318:7] wire priv_uses_vm = 1'h1; // @[TLB.scala:372:27] wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64] wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_19 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_34 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_49 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_64 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire _priv_rw_ok_T = 1'h1; // @[TLB.scala:513:24] wire _priv_rw_ok_T_1 = 1'h1; // @[TLB.scala:513:32] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire ignore_5 = 1'h1; // @[TLB.scala:182:34] wire ignore_8 = 1'h1; // @[TLB.scala:182:34] wire ignore_11 = 1'h1; // @[TLB.scala:182:34] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [5:0] _priv_rw_ok_T_6 = 6'h0; // @[TLB.scala:513:75] wire [5:0] _stage1_bypass_T = 6'h0; // @[TLB.scala:517:27] wire [5:0] stage1_bypass = 6'h0; // @[TLB.scala:517:61] wire [5:0] _gpa_hits_T = 6'h0; // @[TLB.scala:607:30] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7, :320:14, :550:69] wire [8:0] _misaligned_T_1 = 9'h0; // @[TLB.scala:318:7, :320:14, :550:69] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [1:0] io_req_bits_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [2:0] io_req_bits_size = 3'h0; // @[TLB.scala:318:7] wire [2:0] io_resp_size = 3'h0; // @[TLB.scala:318:7] wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7] wire io_req_bits_v = 1'h0; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs1 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs2 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_asid = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hv = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hg = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire priv_s = 1'h0; // @[TLB.scala:370:20] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire misaligned = 1'h0; // @[TLB.scala:550:77] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:183:37] wire _io_req_ready_T; // @[TLB.scala:631:25] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_ma_ld_T = 1'h0; // @[TLB.scala:645:31] wire _io_resp_ma_st_T = 1'h0; // @[TLB.scala:646:31] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire _r_sectored_repl_addr_T_3 = 1'h0; // @[TLB.scala:757:8] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire ignore_6 = 1'h0; // @[TLB.scala:182:34] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire ignore_9 = 1'h0; // @[TLB.scala:182:34] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire ignore_12 = 1'h0; // @[TLB.scala:182:34] wire [4:0] io_resp_cmd_0 = io_req_bits_cmd_0; // @[TLB.scala:318:7] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready; // @[TLB.scala:318:7] wire io_resp_pf_ld_0; // @[TLB.scala:318:7] wire io_resp_pf_st_0; // @[TLB.scala:318:7] wire io_resp_pf_inst_0; // @[TLB.scala:318:7] wire io_resp_ae_ld_0; // @[TLB.scala:318:7] wire io_resp_ae_st_0; // @[TLB.scala:318:7] wire io_resp_ae_inst_0; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7] wire io_resp_cacheable_0; // @[TLB.scala:318:7] wire io_resp_must_alloc_0; // @[TLB.scala:318:7] wire io_resp_prefetchable_0; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_3 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_1_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_5 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_1_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_2_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_7 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_2_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_3_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_9 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_3_valid_0; // @[TLB.scala:341:30] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_11 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34] wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T; // @[TLB.scala:399:{31,45}] wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_22 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_22; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_22; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T \| _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 \| io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_8; // @[TLB.scala:197:28] assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_13; // @[TLB.scala:182:28] assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}, :550:69] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20, :550:69] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, 2'h0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 \| _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 \| _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 \| _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 \| _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 \| _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 \| _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 \| _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 \| _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 \| _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 \| _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 \| _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 \| _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 \| _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 \| _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire _GEN_4 = sectored_entries_0_0_valid_0 \| sectored_entries_0_0_valid_1; // @[package.scala:81:59] wire _sector_hits_T; // @[package.scala:81:59] assign _sector_hits_T = _GEN_4; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59] wire _sector_hits_T_1 = _sector_hits_T \| sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _sector_hits_T_2 = _sector_hits_T_1 \| sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire [26:0] _T_147 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61] assign _sector_hits_T_3 = _T_147; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _T_147; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_470 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_470; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_470; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_470; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_6; // @[TLB.scala:183:52] assign _hitsVec_T_6 = _T_470; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_11; // @[TLB.scala:183:52] assign _hitsVec_T_11 = _T_470; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_16; // @[TLB.scala:183:52] assign _hitsVec_T_16 = _T_470; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_5 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_5; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_5; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_5; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_5; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _superpage_hits_T_8 = superpage_hits_ignore_1 \| _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_568 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52] assign _superpage_hits_T_14 = _T_568; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52] assign _superpage_hits_T_19 = _T_568; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52] assign _superpage_hits_T_24 = _T_568; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_21; // @[TLB.scala:183:52] assign _hitsVec_T_21 = _T_568; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_26; // @[TLB.scala:183:52] assign _hitsVec_T_26 = _T_568; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_31; // @[TLB.scala:183:52] assign _hitsVec_T_31 = _T_568; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_6 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_4 = _GEN_6; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN_6; // @[TLB.scala:182:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN_6; // @[TLB.scala:182:28, :197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN_6; // @[TLB.scala:182:28] wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _superpage_hits_T_22 = superpage_hits_ignore_4 \| _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}] wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_666 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52] assign _superpage_hits_T_28 = _T_666; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52] assign _superpage_hits_T_33 = _T_666; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52] assign _superpage_hits_T_38 = _T_666; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_36; // @[TLB.scala:183:52] assign _hitsVec_T_36 = _T_666; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_41; // @[TLB.scala:183:52] assign _hitsVec_T_41 = _T_666; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_46; // @[TLB.scala:183:52] assign _hitsVec_T_46 = _T_666; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_7 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_7 = _GEN_7; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_7 = _GEN_7; // @[TLB.scala:182:28] wire _ppn_ignore_T_4; // @[TLB.scala:197:28] assign _ppn_ignore_T_4 = _GEN_7; // @[TLB.scala:182:28, :197:28] wire _ignore_T_7; // @[TLB.scala:182:28] assign _ignore_T_7 = _GEN_7; // @[TLB.scala:182:28] wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _superpage_hits_T_36 = superpage_hits_ignore_7 \| _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}] wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_764 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52] assign _superpage_hits_T_42 = _T_764; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52] assign _superpage_hits_T_47 = _T_764; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52] assign _superpage_hits_T_52 = _T_764; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_51; // @[TLB.scala:183:52] assign _hitsVec_T_51 = _T_764; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_56; // @[TLB.scala:183:52] assign _hitsVec_T_56 = _T_764; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_61; // @[TLB.scala:183:52] assign _hitsVec_T_61 = _T_764; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_8 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_10 = _GEN_8; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_10 = _GEN_8; // @[TLB.scala:182:28] wire _ppn_ignore_T_6; // @[TLB.scala:197:28] assign _ppn_ignore_T_6 = _GEN_8; // @[TLB.scala:182:28, :197:28] wire _ignore_T_10; // @[TLB.scala:182:28] assign _ignore_T_10 = _GEN_8; // @[TLB.scala:182:28] wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _superpage_hits_T_50 = superpage_hits_ignore_10 \| _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}] wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13] wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_9 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_5 = _GEN_9[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_7 = _hitsVec_T_6[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_8 = _hitsVec_T_7 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _hitsVec_T_9 = _hitsVec_T_8; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_10 = hitsVec_tagMatch & _hitsVec_T_9; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_12 = _hitsVec_T_11[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_13 = _hitsVec_T_12 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _hitsVec_T_14 = hitsVec_ignore_1 \| _hitsVec_T_13; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_15 = _hitsVec_T_10 & _hitsVec_T_14; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_20 = _hitsVec_T_15; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_17 = _hitsVec_T_16[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_18 = _hitsVec_T_17 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire hitsVec_1 = vm_enabled & _hitsVec_T_20; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_22 = _hitsVec_T_21[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_23 = _hitsVec_T_22 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _hitsVec_T_24 = _hitsVec_T_23; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_25 = hitsVec_tagMatch_1 & _hitsVec_T_24; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_27 = _hitsVec_T_26[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_28 = _hitsVec_T_27 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _hitsVec_T_29 = hitsVec_ignore_4 \| _hitsVec_T_28; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_30 = _hitsVec_T_25 & _hitsVec_T_29; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_35 = _hitsVec_T_30; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_32 = _hitsVec_T_31[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_33 = _hitsVec_T_32 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire hitsVec_2 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_37 = _hitsVec_T_36[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_38 = _hitsVec_T_37 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _hitsVec_T_39 = _hitsVec_T_38; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_40 = hitsVec_tagMatch_2 & _hitsVec_T_39; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_42 = _hitsVec_T_41[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_43 = _hitsVec_T_42 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _hitsVec_T_44 = hitsVec_ignore_7 \| _hitsVec_T_43; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_45 = _hitsVec_T_40 & _hitsVec_T_44; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_50 = _hitsVec_T_45; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_47 = _hitsVec_T_46[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_48 = _hitsVec_T_47 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire hitsVec_3 = vm_enabled & _hitsVec_T_50; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_52 = _hitsVec_T_51[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_53 = _hitsVec_T_52 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _hitsVec_T_54 = _hitsVec_T_53; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_55 = hitsVec_tagMatch_3 & _hitsVec_T_54; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_57 = _hitsVec_T_56[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_58 = _hitsVec_T_57 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _hitsVec_T_59 = hitsVec_ignore_10 \| _hitsVec_T_58; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_60 = _hitsVec_T_55 & _hitsVec_T_59; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_65 = _hitsVec_T_60; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_62 = _hitsVec_T_61[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_63 = _hitsVec_T_62 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire hitsVec_4 = vm_enabled & _hitsVec_T_65; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_862 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_66; // @[TLB.scala:183:52] assign _hitsVec_T_66 = _T_862; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_71; // @[TLB.scala:183:52] assign _hitsVec_T_71 = _T_862; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_76; // @[TLB.scala:183:52] assign _hitsVec_T_76 = _T_862; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_67 = _hitsVec_T_66[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_68 = _hitsVec_T_67 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _hitsVec_T_69 = _hitsVec_T_68; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_70 = hitsVec_tagMatch_4 & _hitsVec_T_69; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_72 = _hitsVec_T_71[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_73 = _hitsVec_T_72 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _hitsVec_T_74 = hitsVec_ignore_13 \| _hitsVec_T_73; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_75 = _hitsVec_T_70 & _hitsVec_T_74; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_77 = _hitsVec_T_76[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_78 = _hitsVec_T_77 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14, :550:69] wire _hitsVec_T_79 = hitsVec_ignore_14 \| _hitsVec_T_78; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_80 = _hitsVec_T_75 & _hitsVec_T_79; // @[TLB.scala:183:{29,40}] wire hitsVec_5 = vm_enabled & _hitsVec_T_80; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo = {real_hits_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_hi = {real_hits_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [5:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [6:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_10 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_10; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_10; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_lo = _GEN_10; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_lo = _GEN_10; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_lo = _GEN_10; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_lo = _GEN_10; // @[TLB.scala:217:24] wire [1:0] _GEN_11 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_11; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_11; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_11; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_11; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_11; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_11; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_12 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_12; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_12; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_12; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_12; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_12; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_12; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_13 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_13; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_13; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_13; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_13; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_13; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_13; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_14 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_14; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_14; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_14; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_14; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_14; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_14; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_15 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_15; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_15; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_15; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_15; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_15; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_15; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_16 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_16; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_16; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_16; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_16; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_16; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_16; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_17 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_17; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_17; // @[TLB.scala:217:24] wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_17; // @[TLB.scala:217:24] wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_17; // @[TLB.scala:217:24] wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_17; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_17; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_23; // @[TLB.scala:170:77] wire _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_18 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_18[_entries_T]; // @[package.scala:163:13] assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77] wire [19:0] _entries_T_46; // @[TLB.scala:170:77] wire _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire _entries_T_24; // @[TLB.scala:170:77] assign _entries_T_24 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_24; // @[TLB.scala:170:77] assign _entries_T_25 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_45; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_46; // @[TLB.scala:170:77] wire [19:0] _entries_T_69; // @[TLB.scala:170:77] wire _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire _entries_T_48; // @[TLB.scala:170:77] wire _entries_T_47; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_47; // @[TLB.scala:170:77] assign _entries_T_48 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_48; // @[TLB.scala:170:77] assign _entries_T_49 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_68; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_69; // @[TLB.scala:170:77] wire [19:0] _entries_T_92; // @[TLB.scala:170:77] wire _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire _entries_T_72; // @[TLB.scala:170:77] wire _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_71; // @[TLB.scala:170:77] assign _entries_T_72 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_72; // @[TLB.scala:170:77] assign _entries_T_73 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_91; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_92; // @[TLB.scala:170:77] wire [19:0] _entries_T_115; // @[TLB.scala:170:77] wire _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire _entries_T_96; // @[TLB.scala:170:77] wire _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_95; // @[TLB.scala:170:77] assign _entries_T_96 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_96; // @[TLB.scala:170:77] assign _entries_T_97 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_114; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_115; // @[TLB.scala:170:77] wire [19:0] _entries_T_138; // @[TLB.scala:170:77] wire _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire _entries_T_120; // @[TLB.scala:170:77] wire _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_119; // @[TLB.scala:170:77] assign _entries_T_120 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_120; // @[TLB.scala:170:77] assign _entries_T_121 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_137; // @[TLB.scala:170:77] assign _entries_T_138 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_138; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_1_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] \| _entries_barrier_1_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] \| _entries_barrier_1_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_2_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] \| _entries_barrier_2_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] \| _entries_barrier_2_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_2 = _entries_barrier_3_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] \| _entries_barrier_3_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] \| _entries_barrier_3_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_3 = _entries_barrier_4_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] \| _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] \| _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_4 = _entries_barrier_5_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] \| _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] \| _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_43 = hitsVec_1 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_44 = hitsVec_2 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_45 = hitsVec_3 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_46 = hitsVec_4 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_47 = hitsVec_5 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_48 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_49 = _ppn_T_42 \| _ppn_T_43; // @[Mux.scala:30:73] wire [19:0] _ppn_T_50 = _ppn_T_49 \| _ppn_T_44; // @[Mux.scala:30:73] wire [19:0] _ppn_T_51 = _ppn_T_50 \| _ppn_T_45; // @[Mux.scala:30:73] wire [19:0] _ppn_T_52 = _ppn_T_51 \| _ppn_T_46; // @[Mux.scala:30:73] wire [19:0] _ppn_T_53 = _ppn_T_52 \| _ppn_T_47; // @[Mux.scala:30:73] wire [19:0] _ppn_T_54 = _ppn_T_53 \| _ppn_T_48; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_54; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo = {final_ae_array_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi = {final_ae_array_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [6:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [6:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [6:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire [1:0] _GEN_19 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi = _GEN_19; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_1 = _GEN_19; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi = _GEN_19; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_1 = _GEN_19; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_20 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi = _GEN_20; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_1 = _GEN_20; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi = _GEN_20; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_1 = _GEN_20; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_2; // @[package.scala:45:27] wire [5:0] priv_rw_ok = _priv_rw_ok_T_3; // @[TLB.scala:513:{23,70}] wire [2:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo = {priv_x_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi = {priv_x_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [5:0] priv_x_ok = _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [5:0] _stage1_bypass_T_2 = {6{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo = {stage1_bypass_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi = {stage1_bypass_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [5:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 \| _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo = {r_array_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi = {r_array_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_21 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_1 = _GEN_21; // @[package.scala:45:27] wire [1:0] x_array_lo_hi; // @[package.scala:45:27] assign x_array_lo_hi = _GEN_21; // @[package.scala:45:27] wire [2:0] r_array_lo_1 = {r_array_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_22 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_1 = _GEN_22; // @[package.scala:45:27] wire [1:0] x_array_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi = _GEN_22; // @[package.scala:45:27] wire [2:0] r_array_hi_1 = {r_array_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [5:0] _r_array_T_2 = mxr ? _r_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _r_array_T_3 = _r_array_T \| _r_array_T_2; // @[package.scala:45:27] wire [5:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [5:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [6:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [6:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo = {w_array_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi = {w_array_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [5:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [5:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [6:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo = {x_array_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_hi = {x_array_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [5:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [5:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [6:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo = {hr_array_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi = {hr_array_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_23 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_1 = _GEN_23; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi; // @[package.scala:45:27] assign hx_array_lo_hi = _GEN_23; // @[package.scala:45:27] wire [2:0] hr_array_lo_1 = {hr_array_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_24 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_1 = _GEN_24; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi = _GEN_24; // @[package.scala:45:27] wire [2:0] hr_array_hi_1 = {hr_array_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [5:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _hr_array_T_3 = _hr_array_T \| _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo = {hw_array_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi = {hw_array_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo = {hx_array_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_hi = {hx_array_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo = {_entries_barrier_1_io_y_pr, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi = {_entries_barrier_4_io_y_pr, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi = {pr_array_hi_hi, _entries_barrier_2_io_y_pr}; // @[package.scala:45:27, :267:25] wire [4:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [6:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [6:0] _GEN_25 = ptw_ae_array \| final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [6:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_25; // @[TLB.scala:529:104] wire [6:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_25; // @[TLB.scala:529:104, :531:104] wire [6:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_25; // @[TLB.scala:529:104, :533:104] wire [6:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [6:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo = {_entries_barrier_1_io_y_pw, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi = {_entries_barrier_4_io_y_pw, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi = {pw_array_hi_hi, _entries_barrier_2_io_y_pw}; // @[package.scala:45:27, :267:25] wire [4:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [6:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [6:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [6:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo = {_entries_barrier_1_io_y_px, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi = {_entries_barrier_4_io_y_px, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi = {px_array_hi_hi, _entries_barrier_2_io_y_px}; // @[package.scala:45:27, :267:25] wire [4:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [6:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [6:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [6:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo = {_entries_barrier_1_io_y_eff, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi = {_entries_barrier_4_io_y_eff, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi = {eff_array_hi_hi, _entries_barrier_2_io_y_eff}; // @[package.scala:45:27, :267:25] wire [4:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [6:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_26 = {_entries_barrier_1_io_y_c, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo; // @[package.scala:45:27] assign c_array_lo = _GEN_26; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo; // @[package.scala:45:27] assign prefetchable_array_lo = _GEN_26; // @[package.scala:45:27] wire [1:0] _GEN_27 = {_entries_barrier_4_io_y_c, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi = _GEN_27; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi = _GEN_27; // @[package.scala:45:27] wire [2:0] c_array_hi = {c_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [6:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [6:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo = {_entries_barrier_1_io_y_ppp, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi = {_entries_barrier_4_io_y_ppp, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi = {ppp_array_hi_hi, _entries_barrier_2_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [4:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [6:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo = {_entries_barrier_1_io_y_paa, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi = {_entries_barrier_4_io_y_paa, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi = {paa_array_hi_hi, _entries_barrier_2_io_y_paa}; // @[package.scala:45:27, :267:25] wire [4:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [6:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo = {_entries_barrier_1_io_y_pal, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi = {_entries_barrier_4_io_y_pal, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi = {pal_array_hi_hi, _entries_barrier_2_io_y_pal}; // @[package.scala:45:27, :267:25] wire [4:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [6:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [6:0] ppp_array_if_cached = ppp_array \| c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [6:0] paa_array_if_cached = paa_array \| c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [6:0] pal_array_if_cached = pal_array \| c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_hi = {prefetchable_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [6:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:550:39, :559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 \| _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _GEN_28 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_28; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_28; // @[package.scala:16:47] wire _GEN_29 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_29; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_29; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_29; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T \| _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire cmd_lrsc = _cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_30 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_30; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_30; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_31; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_31; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_31; // @[package.scala:16:47] wire _GEN_32 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_32; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_32; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_33; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_33; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_33; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T \| _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 \| _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 \| _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire cmd_amo_logical = _cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_34 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_34; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_34; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_35; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_35; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_35; // @[package.scala:16:47] wire _GEN_36 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_36; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_36; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_37; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_37; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_37; // @[package.scala:16:47] wire _GEN_38 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_38; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_38; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_38; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T \| _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 \| _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 \| _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 \| _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire cmd_amo_arithmetic = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_39 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41] wire cmd_put_partial; // @[TLB.scala:573:41] assign cmd_put_partial = _GEN_39; // @[TLB.scala:573:41] wire _cmd_write_T_1; // @[Consts.scala:90:49] assign _cmd_write_T_1 = _GEN_39; // @[TLB.scala:573:41] wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _GEN_40 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_1; // @[package.scala:16:47] assign _cmd_read_T_1 = _GEN_40; // @[package.scala:16:47] wire _cmd_readx_T; // @[TLB.scala:575:56] assign _cmd_readx_T = _GEN_40; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T \| _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 \| _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 \| _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 \| _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 \| _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 \| _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 \| _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 \| _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 \| _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 \| _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 \| _cmd_read_T_22; // @[package.scala:81:59] wire cmd_read = _cmd_read_T_6 \| _cmd_read_T_23; // @[package.scala:81:59] wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7] wire _cmd_write_T_2 = _cmd_write_T \| _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 \| _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 \| _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 \| _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 \| _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 \| _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 \| _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 \| _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 \| _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 \| _cmd_write_T_20; // @[package.scala:81:59] wire cmd_write = _cmd_write_T_4 \| _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = _cmd_write_perms_T \| _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire cmd_write_perms = cmd_write \| _cmd_write_perms_T_2; // @[package.scala:81:59] wire [6:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [6:0] _ae_array_T_2 = cmd_lrsc ? _ae_array_T_1 : 7'h0; // @[TLB.scala:570:33, :583:{8,19}] wire [6:0] ae_array = _ae_array_T_2; // @[TLB.scala:582:37, :583:8] wire [6:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [6:0] _ae_ld_array_T_1 = ae_array \| _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [6:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 7'h0; // @[TLB.scala:586:{24,44}] wire [6:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [6:0] _ae_st_array_T_1 = ae_array \| _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [6:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 7'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [6:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [6:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 7'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [6:0] _ae_st_array_T_5 = _ae_st_array_T_2 \| _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [6:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [6:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_6 : 7'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [6:0] _ae_st_array_T_8 = _ae_st_array_T_5 \| _ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [6:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [6:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_9 : 7'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [6:0] ae_st_array = _ae_st_array_T_8 \| _ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [6:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [6:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 7'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [6:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [6:0] _must_alloc_array_T_3 = cmd_amo_logical ? _must_alloc_array_T_2 : 7'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [6:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 \| _must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [6:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [6:0] _must_alloc_array_T_6 = cmd_amo_arithmetic ? _must_alloc_array_T_5 : 7'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [6:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 \| _must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [6:0] _must_alloc_array_T_9 = {7{cmd_lrsc}}; // @[TLB.scala:570:33, :596:8] wire [6:0] must_alloc_array = _must_alloc_array_T_7 \| _must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [6:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [6:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [6:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [6:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 \| ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [6:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [6:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [6:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 7'h0; // @[TLB.scala:597:{24,104}] wire [6:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [6:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [6:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [6:0] _pf_st_array_T_3 = _pf_st_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [6:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [6:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [6:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 7'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [6:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [6:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [6:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [6:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [6:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [6:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [6:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [6:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [6:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [6:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [6:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [6:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [4:0] _gpa_hits_hit_mask_T_2 = {5{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = \|real_hits; // @[package.scala:45:27] wire tlb_hit = \|_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [2:0] state_reg_1; // @[Replacement.scala:168:70] wire [1:0] _GEN_41 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo; // @[OneHot.scala:21:45] assign lo = _GEN_41; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_lo = _GEN_41; // @[OneHot.scala:21:45] wire [1:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_42 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi; // @[OneHot.scala:21:45] assign hi = _GEN_42; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_hi = _GEN_42; // @[OneHot.scala:21:45] wire [1:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_reg_touch_way_sized = {\|hi_1, hi_1[1] \| lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38] wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13] wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _multipleHits_T = real_hits[2:0]; // @[package.scala:45:27] wire _multipleHits_T_1 = _multipleHits_T[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_1; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_2 = _multipleHits_T[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_3 = _multipleHits_T_2[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_3; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_4 = _multipleHits_T_2[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_4; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 \| multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_6 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_6; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_7 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne \| multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_8 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_7 \| _multipleHits_T_8; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_9 = real_hits[5:3]; // @[package.scala:45:27] wire _multipleHits_T_10 = _multipleHits_T_9[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_10; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_11 = _multipleHits_T_9[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_12 = _multipleHits_T_11[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_12; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_13 = _multipleHits_T_11[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_13; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 \| multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_15 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_15; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_16 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 \| multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_17 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_16 \| _multipleHits_T_17; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_18 = multipleHits_leftOne_2 \| multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo \| multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_19 \| _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28] wire [6:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = \|_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T \| _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28] wire [6:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64] wire _io_resp_pf_st_T_2 = \|_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T \| _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}] assign io_resp_pf_st_0 = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48] wire [6:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = \|_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va \| _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [6:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = \|_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [6:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33] assign _io_resp_ae_st_T_1 = \|_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign io_resp_ae_st_0 = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41] wire [6:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [6:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = \|_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] wire [6:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = \|_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [6:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43] assign _io_resp_must_alloc_T_1 = \|_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign io_resp_must_alloc_0 = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51] wire [6:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = \|_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T \| tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 \| multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38] wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27] wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27] wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70] wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T \| sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire r_sectored_repl_addr_valids = _r_sectored_repl_addr_valids_T_1 \| sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_valids; // @[package.scala:81:59] wire _r_sectored_repl_addr_T_1 = ~r_sectored_repl_addr_valids; // @[package.scala:81:59] wire _r_sectored_repl_addr_T_2 = _r_sectored_repl_addr_T_1; // @[OneHot.scala:48:45] wire _r_superpage_hit_valid_T = superpage_hits_0 \| superpage_hits_1; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T \| superpage_hits_2; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 \| superpage_hits_3; // @[package.scala:81:59] wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_superpage_hit_bits_T_1 = \|r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 \| r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45] wire _tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire tagMatch = superpage_entries_0_valid_0 & _tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire ignore_1 = _ignore_T_1; // @[TLB.scala:182:{28,34}] wire _ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire _tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire tagMatch_1 = superpage_entries_1_valid_0 & _tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire ignore_4 = _ignore_T_4; // @[TLB.scala:182:{28,34}] wire _ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire _tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire tagMatch_2 = superpage_entries_2_valid_0 & _tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire ignore_7 = _ignore_T_7; // @[TLB.scala:182:{28,34}] wire _ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire _tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire tagMatch_3 = superpage_entries_3_valid_0 & _tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire ignore_10 = _ignore_T_10; // @[TLB.scala:182:{28,34}] wire _ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire _tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire tagMatch_4 = special_entry_valid_0 & _tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56] wire ignore_13 = _ignore_T_13; // @[TLB.scala:182:{28,34}] wire _ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire ignore_14 = _ignore_T_14; // @[TLB.scala:182:{28,34}] wire _GEN_43 = do_refill & ~io_ptw_resp_bits_homogeneous_0; // @[TLB.scala:211:18, :318:7, :346:56, :408:29, :446:20, :474:{39,70}] wire _GEN_44 = ~(io_ptw_resp_bits_level_0[1]) & r_superpage_repl_addr == 2'h0; // @[TLB.scala:211:18, :318:7, :341:30, :355:34, :476:{40,58}, :478:{82,91}] wire _GEN_45 = do_refill & io_ptw_resp_bits_homogeneous_0 & _GEN_44; // @[TLB.scala:211:18, :318:7, :341:30, :408:29, :446:20, :474:70, :476:58, :478:91] wire _GEN_46 = ~(io_ptw_resp_bits_level_0[1]) & r_superpage_repl_addr == 2'h1; // @[TLB.scala:197:28, :211:18, :318:7, :341:30, :355:34, :476:{40,58}, :478:{82,91}] wire _GEN_47 = do_refill & io_ptw_resp_bits_homogeneous_0 & _GEN_46; // @[TLB.scala:211:18, :318:7, :341:30, :408:29, :446:20, :474:70, :476:58, :478:91] wire _GEN_48 = ~(io_ptw_resp_bits_level_0[1]) & r_superpage_repl_addr == 2'h2; // @[TLB.scala:211:18, :318:7, :341:30, :355:34, :476:{40,58}, :478:{82,91}] wire _GEN_49 = do_refill & io_ptw_resp_bits_homogeneous_0 & _GEN_48; // @[TLB.scala:211:18, :318:7, :341:30, :408:29, :446:20, :474:70, :476:58, :478:91] wire _GEN_50 = ~(io_ptw_resp_bits_level_0[1]) & (&r_superpage_repl_addr); // @[TLB.scala:211:18, :318:7, :341:30, :355:34, :476:{40,58}, :478:{82,91}] wire _GEN_51 = do_refill & io_ptw_resp_bits_homogeneous_0 & _GEN_50; // @[TLB.scala:211:18, :318:7, :341:30, :408:29, :446:20, :474:70, :476:58, :478:91] wire _GEN_52 = ~io_ptw_resp_bits_homogeneous_0 \| ~(io_ptw_resp_bits_level_0[1]); // @[TLB.scala:318:7, :339:29, :474:{39,70}, :476:{40,58}, :486:84] wire _GEN_53 = ~do_refill \| _GEN_52; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:84] wire _GEN_54 = idx == 2'h0; // @[package.scala:163:13] wire _GEN_55 = idx == 2'h1; // @[package.scala:163:13] wire _GEN_56 = idx == 2'h2; // @[package.scala:163:13] wire _T_1163 = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] wire _T_21 = io_req_ready & io_req_valid_0 & tlb_miss; // @[Decoupled.scala:51:35] wire _T_1162 = multipleHits \| reset; // @[Misc.scala:183:49] wire _GEN_57 = _T_1162 \| io_sfence_valid_0 & ~sectored_entries_0_0_tag_v; // @[TLB.scala:220:46, :223:{19,32,36}, :318:7, :339:29, :446:20, :718:19, :723:42, :728:46, :732:{24,41}] always @(posedge clock) begin // @[TLB.scala:318:7] if (_GEN_53) begin // @[TLB.scala:339:29, :446:20, :474:70] end else begin // @[TLB.scala:339:29, :446:20, :474:70] sectored_entries_0_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_0_tag_v <= _GEN_53 & sectored_entries_0_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70] if (~do_refill \| _GEN_52 \| ~_GEN_54) begin // @[TLB.scala:216:16, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_data_0 <= _sectored_entries_0_0_data_T; // @[TLB.scala:217:24, :339:29] if (~do_refill \| _GEN_52 \| ~_GEN_55) begin // @[TLB.scala:216:16, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_data_1 <= _sectored_entries_0_0_data_T; // @[TLB.scala:217:24, :339:29] if (~do_refill \| _GEN_52 \| ~_GEN_56) begin // @[TLB.scala:216:16, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_data_2 <= _sectored_entries_0_0_data_T; // @[TLB.scala:217:24, :339:29] if (~do_refill \| _GEN_52 \| ~(&idx)) begin // @[package.scala:163:13] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_data_3 <= _sectored_entries_0_0_data_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_0_valid_0 <= ~_GEN_57 & (_GEN_53 ? sectored_entries_0_0_valid_0 : ~invalidate_refill & (_GEN_54 \| r_sectored_hit_valid & sectored_entries_0_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{32,36}, :339:29, :357:27, :410:88, :446:20, :474:70, :487:38, :489:34, :718:19, :723:42, :728:46, :732:41] sectored_entries_0_0_valid_1 <= ~_GEN_57 & (_GEN_53 ? sectored_entries_0_0_valid_1 : ~invalidate_refill & (_GEN_55 \| r_sectored_hit_valid & sectored_entries_0_0_valid_1)); // @[TLB.scala:216:16, :220:46, :223:{32,36}, :339:29, :357:27, :410:88, :446:20, :474:70, :487:38, :489:34, :718:19, :723:42, :728:46, :732:41] sectored_entries_0_0_valid_2 <= ~_GEN_57 & (_GEN_53 ? sectored_entries_0_0_valid_2 : ~invalidate_refill & (_GEN_56 \| r_sectored_hit_valid & sectored_entries_0_0_valid_2)); // @[TLB.scala:216:16, :220:46, :223:{32,36}, :339:29, :357:27, :410:88, :446:20, :474:70, :487:38, :489:34, :718:19, :723:42, :728:46, :732:41] sectored_entries_0_0_valid_3 <= ~_GEN_57 & (_GEN_53 ? sectored_entries_0_0_valid_3 : ~invalidate_refill & ((&idx) \| r_sectored_hit_valid & sectored_entries_0_0_valid_3)); // @[package.scala:163:13] if (_GEN_45) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_level <= {1'h0, _superpage_entries_0_level_T}; // @[package.scala:163:13] superpage_entries_0_tag_vpn <= r_refill_tag; // @[TLB.scala:341:30, :354:25] end superpage_entries_0_tag_v <= (~do_refill \| ~io_ptw_resp_bits_homogeneous_0 \| ~_GEN_44) & superpage_entries_0_tag_v; // @[TLB.scala:211:18, :212:16, :318:7, :341:30, :408:29, :446:20, :474:70, :476:58, :478:91] if (_GEN_45) // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_data_0 <= _superpage_entries_0_data_0_T; // @[TLB.scala:217:24, :341:30] superpage_entries_0_valid_0 <= ~(_T_1162 \| io_sfence_valid_0 & ~superpage_entries_0_tag_v) & (_GEN_45 ? ~invalidate_refill : superpage_entries_0_valid_0); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :341:30, :410:88, :446:20, :474:70, :476:58, :480:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_47) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_1_level <= {1'h0, _superpage_entries_1_level_T}; // @[package.scala:163:13] superpage_entries_1_tag_vpn <= r_refill_tag; // @[TLB.scala:341:30, :354:25] end superpage_entries_1_tag_v <= (~do_refill \| ~io_ptw_resp_bits_homogeneous_0 \| ~_GEN_46) & superpage_entries_1_tag_v; // @[TLB.scala:211:18, :212:16, :318:7, :341:30, :408:29, :446:20, :474:70, :476:58, :478:91] if (_GEN_47) // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_1_data_0 <= _superpage_entries_1_data_0_T; // @[TLB.scala:217:24, :341:30] superpage_entries_1_valid_0 <= ~(_T_1162 \| io_sfence_valid_0 & ~superpage_entries_1_tag_v) & (_GEN_47 ? ~invalidate_refill : superpage_entries_1_valid_0); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :341:30, :410:88, :446:20, :474:70, :476:58, :480:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_49) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_2_level <= {1'h0, _superpage_entries_2_level_T}; // @[package.scala:163:13] superpage_entries_2_tag_vpn <= r_refill_tag; // @[TLB.scala:341:30, :354:25] end superpage_entries_2_tag_v <= (~do_refill \| ~io_ptw_resp_bits_homogeneous_0 \| ~_GEN_48) & superpage_entries_2_tag_v; // @[TLB.scala:211:18, :212:16, :318:7, :341:30, :408:29, :446:20, :474:70, :476:58, :478:91] if (_GEN_49) // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_2_data_0 <= _superpage_entries_2_data_0_T; // @[TLB.scala:217:24, :341:30] superpage_entries_2_valid_0 <= ~(_T_1162 \| io_sfence_valid_0 & ~superpage_entries_2_tag_v) & (_GEN_49 ? ~invalidate_refill : superpage_entries_2_valid_0); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :341:30, :410:88, :446:20, :474:70, :476:58, :480:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_51) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_3_level <= {1'h0, _superpage_entries_3_level_T}; // @[package.scala:163:13] superpage_entries_3_tag_vpn <= r_refill_tag; // @[TLB.scala:341:30, :354:25] end superpage_entries_3_tag_v <= (~do_refill \| ~io_ptw_resp_bits_homogeneous_0 \| ~_GEN_50) & superpage_entries_3_tag_v; // @[TLB.scala:211:18, :212:16, :318:7, :341:30, :408:29, :446:20, :474:70, :476:58, :478:91] if (_GEN_51) // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_3_data_0 <= _superpage_entries_3_data_0_T; // @[TLB.scala:217:24, :341:30] superpage_entries_3_valid_0 <= ~(_T_1162 \| io_sfence_valid_0 & ~superpage_entries_3_tag_v) & (_GEN_51 ? ~invalidate_refill : superpage_entries_3_valid_0); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :341:30, :410:88, :446:20, :474:70, :476:58, :480:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_43) begin // @[TLB.scala:211:18, :346:56, :446:20, :474:70] special_entry_level <= _special_entry_level_T; // @[package.scala:163:13] special_entry_tag_vpn <= r_refill_tag; // @[TLB.scala:346:56, :354:25] special_entry_data_0 <= _special_entry_data_0_T; // @[TLB.scala:217:24, :346:56] end special_entry_tag_v <= ~_GEN_43 & special_entry_tag_v; // @[TLB.scala:211:18, :212:16, :346:56, :446:20, :474:70] special_entry_valid_0 <= ~(_T_1162 \| io_sfence_valid_0 & ~special_entry_tag_v) & (_GEN_43 \| special_entry_valid_0); // @[TLB.scala:211:18, :216:16, :220:46, :223:{19,32,36}, :318:7, :346:56, :446:20, :474:70, :718:19, :723:42, :728:46, :732:{24,41}] if (_T_21) begin // @[Decoupled.scala:51:35] r_refill_tag <= vpn; // @[TLB.scala:335:30, :354:25] r_superpage_repl_addr <= _r_superpage_repl_addr_T_13; // @[TLB.scala:355:34, :757:8] r_sectored_hit_valid <= sector_hits_0; // @[TLB.scala:172:55, :357:27] r_superpage_hit_valid <= _r_superpage_hit_valid_T_2; // @[package.scala:81:59] r_superpage_hit_bits <= _r_superpage_hit_bits_T_4; // @[OneHot.scala:32:10] r_need_gpa <= tlb_hit_if_not_gpa_miss; // @[TLB.scala:361:23, :610:43] end r_gpa_valid <= ~_T_1163 & (do_refill ? io_ptw_resp_bits_gpa_valid_0 : r_gpa_valid); // @[Decoupled.scala:51:35] if (do_refill) begin // @[TLB.scala:408:29] r_gpa <= io_ptw_resp_bits_gpa_bits_0; // @[TLB.scala:318:7, :363:18] r_gpa_is_pte <= io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :365:25] end if (_T_1163) // @[Decoupled.scala:51:35] r_gpa_vpn <= r_refill_tag; // @[TLB.scala:354:25, :364:22] if (reset) begin // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] state_reg_1 <= 3'h0; // @[Replacement.scala:168:70] end else begin // @[TLB.scala:318:7] if (io_ptw_resp_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (state == 2'h2 & io_sfence_valid_0) // @[TLB.scala:318:7, :352:22, :709:{17,28}] state <= 2'h3; // @[TLB.scala:352:22] else if (_T_22) begin // @[package.scala:16:47] if (io_ptw_req_ready_0) // @[TLB.scala:318:7] state <= _state_T; // @[TLB.scala:352:22, :704:45] else if (io_sfence_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (_T_21) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] end else if (_T_21) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] if (io_req_valid_0 & vm_enabled & (superpage_hits_0 \| superpage_hits_1 \| superpage_hits_2 \| superpage_hits_3)) // @[package.scala:81:59] state_reg_1 <= _state_reg_T_8; // @[Replacement.scala:168:70, :202:12] end always @(posedge) OptimizationBarrier_TLBEntryData_28 mpu_ppn_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_mpu_ppn_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_mpu_ppn_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_mpu_ppn_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_mpu_ppn_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_mpu_ppn_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_mpu_ppn_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_mpu_ppn_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_mpu_ppn_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_mpu_ppn_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_mpu_ppn_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_mpu_ppn_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_mpu_ppn_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_mpu_ppn_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_mpu_ppn_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_mpu_ppn_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_mpu_ppn_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_mpu_ppn_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_mpu_ppn_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_mpu_ppn_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_mpu_ppn_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_mpu_ppn_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_mpu_ppn_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_mpu_ppn_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_mpu_ppn_barrier_io_y_ppn) ); // @[package.scala:267:25] PMPChecker_s6 pmp ( // @[TLB.scala:416:19] .clock (clock), .reset (reset), .io_prv (mpu_priv[1:0]), // @[TLB.scala:415:27, :420:14] .io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_0_addr (io_ptw_pmp_0_addr_0), // @[TLB.scala:318:7] .io_pmp_0_mask (io_ptw_pmp_0_mask_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_1_addr (io_ptw_pmp_1_addr_0), // @[TLB.scala:318:7] .io_pmp_1_mask (io_ptw_pmp_1_mask_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_2_addr (io_ptw_pmp_2_addr_0), // @[TLB.scala:318:7] .io_pmp_2_mask (io_ptw_pmp_2_mask_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_3_addr (io_ptw_pmp_3_addr_0), // @[TLB.scala:318:7] .io_pmp_3_mask (io_ptw_pmp_3_mask_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_4_addr (io_ptw_pmp_4_addr_0), // @[TLB.scala:318:7] .io_pmp_4_mask (io_ptw_pmp_4_mask_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_5_addr (io_ptw_pmp_5_addr_0), // @[TLB.scala:318:7] .io_pmp_5_mask (io_ptw_pmp_5_mask_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_6_addr (io_ptw_pmp_6_addr_0), // @[TLB.scala:318:7] .io_pmp_6_mask (io_ptw_pmp_6_mask_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_7_addr (io_ptw_pmp_7_addr_0), // @[TLB.scala:318:7] .io_pmp_7_mask (io_ptw_pmp_7_mask_0), // @[TLB.scala:318:7] .io_addr (mpu_physaddr[31:0]), // @[TLB.scala:414:25, :417:15] .io_r (_pmp_io_r), .io_w (_pmp_io_w), .io_x (_pmp_io_x) ); // @[TLB.scala:416:19] PMAChecker_2 pma ( // @[TLB.scala:422:19] .clock (clock), .reset (reset), .io_paddr (mpu_physaddr), // @[TLB.scala:414:25] .io_resp_cacheable (cacheable), .io_resp_r (_pma_io_resp_r), .io_resp_w (_pma_io_resp_w), .io_resp_pp (_pma_io_resp_pp), .io_resp_al (_pma_io_resp_al), .io_resp_aa (_pma_io_resp_aa), .io_resp_x (_pma_io_resp_x), .io_resp_eff (_pma_io_resp_eff) ); // @[TLB.scala:422:19] assign newEntry_ppp = _pma_io_resp_pp; // @[TLB.scala:422:19, :449:24] assign newEntry_pal = _pma_io_resp_al; // @[TLB.scala:422:19, :449:24] assign newEntry_paa = _pma_io_resp_aa; // @[TLB.scala:422:19, :449:24] assign newEntry_eff = _pma_io_resp_eff; // @[TLB.scala:422:19, :449:24] OptimizationBarrier_TLBEntryData_29 entries_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_io_y_ppn), .io_y_u (_entries_barrier_io_y_u), .io_y_ae_ptw (_entries_barrier_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_io_y_ae_stage2), .io_y_pf (_entries_barrier_io_y_pf), .io_y_gf (_entries_barrier_io_y_gf), .io_y_sw (_entries_barrier_io_y_sw), .io_y_sx (_entries_barrier_io_y_sx), .io_y_sr (_entries_barrier_io_y_sr), .io_y_hw (_entries_barrier_io_y_hw), .io_y_hx (_entries_barrier_io_y_hx), .io_y_hr (_entries_barrier_io_y_hr), .io_y_pw (_entries_barrier_io_y_pw), .io_y_px (_entries_barrier_io_y_px), .io_y_pr (_entries_barrier_io_y_pr), .io_y_ppp (_entries_barrier_io_y_ppp), .io_y_pal (_entries_barrier_io_y_pal), .io_y_paa (_entries_barrier_io_y_paa), .io_y_eff (_entries_barrier_io_y_eff), .io_y_c (_entries_barrier_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_30 entries_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_2_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_2_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_2_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_2_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_2_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_2_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_2_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_2_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_2_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_2_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_2_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_2_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_2_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_2_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_2_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_2_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_2_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_2_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_2_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_2_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_2_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_2_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_1_io_y_ppn), .io_y_u (_entries_barrier_1_io_y_u), .io_y_ae_ptw (_entries_barrier_1_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_1_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_1_io_y_ae_stage2), .io_y_pf (_entries_barrier_1_io_y_pf), .io_y_gf (_entries_barrier_1_io_y_gf), .io_y_sw (_entries_barrier_1_io_y_sw), .io_y_sx (_entries_barrier_1_io_y_sx), .io_y_sr (_entries_barrier_1_io_y_sr), .io_y_hw (_entries_barrier_1_io_y_hw), .io_y_hx (_entries_barrier_1_io_y_hx), .io_y_hr (_entries_barrier_1_io_y_hr), .io_y_pw (_entries_barrier_1_io_y_pw), .io_y_px (_entries_barrier_1_io_y_px), .io_y_pr (_entries_barrier_1_io_y_pr), .io_y_ppp (_entries_barrier_1_io_y_ppp), .io_y_pal (_entries_barrier_1_io_y_pal), .io_y_paa (_entries_barrier_1_io_y_paa), .io_y_eff (_entries_barrier_1_io_y_eff), .io_y_c (_entries_barrier_1_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_31 entries_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_4_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_4_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_4_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_4_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_4_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_4_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_4_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_4_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_4_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_4_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_4_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_4_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_4_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_4_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_4_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_4_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_4_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_4_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_4_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_4_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_4_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_4_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_2_io_y_ppn), .io_y_u (_entries_barrier_2_io_y_u), .io_y_ae_ptw (_entries_barrier_2_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_2_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_2_io_y_ae_stage2), .io_y_pf (_entries_barrier_2_io_y_pf), .io_y_gf (_entries_barrier_2_io_y_gf), .io_y_sw (_entries_barrier_2_io_y_sw), .io_y_sx (_entries_barrier_2_io_y_sx), .io_y_sr (_entries_barrier_2_io_y_sr), .io_y_hw (_entries_barrier_2_io_y_hw), .io_y_hx (_entries_barrier_2_io_y_hx), .io_y_hr (_entries_barrier_2_io_y_hr), .io_y_pw (_entries_barrier_2_io_y_pw), .io_y_px (_entries_barrier_2_io_y_px), .io_y_pr (_entries_barrier_2_io_y_pr), .io_y_ppp (_entries_barrier_2_io_y_ppp), .io_y_pal (_entries_barrier_2_io_y_pal), .io_y_paa (_entries_barrier_2_io_y_paa), .io_y_eff (_entries_barrier_2_io_y_eff), .io_y_c (_entries_barrier_2_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_32 entries_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_6_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_6_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_6_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_6_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_6_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_6_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_6_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_6_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_6_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_6_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_6_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_6_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_6_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_6_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_6_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_6_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_6_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_6_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_6_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_6_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_6_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_6_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_3_io_y_ppn), .io_y_u (_entries_barrier_3_io_y_u), .io_y_ae_ptw (_entries_barrier_3_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_3_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_3_io_y_ae_stage2), .io_y_pf (_entries_barrier_3_io_y_pf), .io_y_gf (_entries_barrier_3_io_y_gf), .io_y_sw (_entries_barrier_3_io_y_sw), .io_y_sx (_entries_barrier_3_io_y_sx), .io_y_sr (_entries_barrier_3_io_y_sr), .io_y_hw (_entries_barrier_3_io_y_hw), .io_y_hx (_entries_barrier_3_io_y_hx), .io_y_hr (_entries_barrier_3_io_y_hr), .io_y_pw (_entries_barrier_3_io_y_pw), .io_y_px (_entries_barrier_3_io_y_px), .io_y_pr (_entries_barrier_3_io_y_pr), .io_y_ppp (_entries_barrier_3_io_y_ppp), .io_y_pal (_entries_barrier_3_io_y_pal), .io_y_paa (_entries_barrier_3_io_y_paa), .io_y_eff (_entries_barrier_3_io_y_eff), .io_y_c (_entries_barrier_3_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_33 entries_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_8_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_8_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_8_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_8_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_8_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_8_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_8_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_8_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_8_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_8_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_8_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_8_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_8_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_8_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_8_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_8_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_8_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_8_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_8_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_8_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_8_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_8_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_4_io_y_ppn), .io_y_u (_entries_barrier_4_io_y_u), .io_y_ae_ptw (_entries_barrier_4_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_4_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_4_io_y_ae_stage2), .io_y_pf (_entries_barrier_4_io_y_pf), .io_y_gf (_entries_barrier_4_io_y_gf), .io_y_sw (_entries_barrier_4_io_y_sw), .io_y_sx (_entries_barrier_4_io_y_sx), .io_y_sr (_entries_barrier_4_io_y_sr), .io_y_hw (_entries_barrier_4_io_y_hw), .io_y_hx (_entries_barrier_4_io_y_hx), .io_y_hr (_entries_barrier_4_io_y_hr), .io_y_pw (_entries_barrier_4_io_y_pw), .io_y_px (_entries_barrier_4_io_y_px), .io_y_pr (_entries_barrier_4_io_y_pr), .io_y_ppp (_entries_barrier_4_io_y_ppp), .io_y_pal (_entries_barrier_4_io_y_pal), .io_y_paa (_entries_barrier_4_io_y_paa), .io_y_eff (_entries_barrier_4_io_y_eff), .io_y_c (_entries_barrier_4_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_34 entries_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_10_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_10_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_10_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_10_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_10_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_10_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_10_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_10_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_10_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_10_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_10_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_10_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_10_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_10_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_10_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_10_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_10_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_10_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_10_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_10_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_10_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_10_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_5_io_y_ppn), .io_y_u (_entries_barrier_5_io_y_u), .io_y_ae_ptw (_entries_barrier_5_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_5_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_5_io_y_ae_stage2), .io_y_pf (_entries_barrier_5_io_y_pf), .io_y_gf (_entries_barrier_5_io_y_gf), .io_y_sw (_entries_barrier_5_io_y_sw), .io_y_sx (_entries_barrier_5_io_y_sx), .io_y_sr (_entries_barrier_5_io_y_sr), .io_y_hw (_entries_barrier_5_io_y_hw), .io_y_hx (_entries_barrier_5_io_y_hx), .io_y_hr (_entries_barrier_5_io_y_hr) ); // @[package.scala:267:25] assign io_resp_miss = io_resp_miss_0; // @[TLB.scala:318:7] assign io_resp_paddr = io_resp_paddr_0; // @[TLB.scala:318:7] assign io_resp_gpa = io_resp_gpa_0; // @[TLB.scala:318:7] assign io_resp_pf_ld = io_resp_pf_ld_0; // @[TLB.scala:318:7] assign io_resp_pf_st = io_resp_pf_st_0; // @[TLB.scala:318:7] assign io_resp_pf_inst = io_resp_pf_inst_0; // @[TLB.scala:318:7] assign io_resp_ae_ld = io_resp_ae_ld_0; // @[TLB.scala:318:7] assign io_resp_ae_st = io_resp_ae_st_0; // @[TLB.scala:318:7] assign io_resp_ae_inst = io_resp_ae_inst_0; // @[TLB.scala:318:7] assign io_resp_cacheable = io_resp_cacheable_0; // @[TLB.scala:318:7] assign io_resp_must_alloc = io_resp_must_alloc_0; // @[TLB.scala:318:7] assign io_resp_prefetchable = io_resp_prefetchable_0; // @[TLB.scala:318:7] assign io_resp_cmd = io_resp_cmd_0; // @[TLB.scala:318:7] assign io_ptw_req_valid = io_ptw_req_valid_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_need_gpa = io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_178 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_322 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_178( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_322 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

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